Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the X86 target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 113;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(X86InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(X86InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static X86InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static X86InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_TruePredicateBit = 48,
37
  Feature_HasCMovBit = 20,
38
  Feature_NoCMovBit = 99,
39
  Feature_HasMMXBit = 80,
40
  Feature_Has3DNowBit = 82,
41
  Feature_HasSSE1Bit = 34,
42
  Feature_UseSSE1Bit = 42,
43
  Feature_HasSSE2Bit = 35,
44
  Feature_UseSSE2Bit = 43,
45
  Feature_HasSSE3Bit = 26,
46
  Feature_UseSSE3Bit = 51,
47
  Feature_HasSSSE3Bit = 81,
48
  Feature_UseSSSE3Bit = 52,
49
  Feature_UseSSE41Bit = 49,
50
  Feature_HasSSE42Bit = 56,
51
  Feature_UseSSE42Bit = 55,
52
  Feature_HasSSE4ABit = 65,
53
  Feature_NoAVXBit = 61,
54
  Feature_HasAVXBit = 44,
55
  Feature_HasAVX2Bit = 38,
56
  Feature_HasAVX1OnlyBit = 36,
57
  Feature_HasAVX512Bit = 68,
58
  Feature_UseAVXBit = 40,
59
  Feature_NoAVX512Bit = 31,
60
  Feature_HasCDIBit = 72,
61
  Feature_HasVPOPCNTDQBit = 76,
62
  Feature_HasERIBit = 75,
63
  Feature_HasDQIBit = 70,
64
  Feature_NoDQIBit = 53,
65
  Feature_HasBWIBit = 71,
66
  Feature_NoBWIBit = 50,
67
  Feature_HasVLXBit = 69,
68
  Feature_NoVLXBit = 30,
69
  Feature_NoVLX_Or_NoBWIBit = 47,
70
  Feature_NoVLX_Or_NoDQIBit = 106,
71
  Feature_HasVNNIBit = 78,
72
  Feature_HasBITALGBit = 79,
73
  Feature_HasPOPCNTBit = 54,
74
  Feature_HasAESBit = 58,
75
  Feature_HasVAESBit = 60,
76
  Feature_NoVLX_Or_NoVAESBit = 59,
77
  Feature_HasFXSRBit = 27,
78
  Feature_HasXSAVEBit = 88,
79
  Feature_HasXSAVEOPTBit = 89,
80
  Feature_HasXSAVECBit = 90,
81
  Feature_HasXSAVESBit = 91,
82
  Feature_HasPCLMULBit = 62,
83
  Feature_NoVLX_Or_NoVPCLMULQDQBit = 63,
84
  Feature_HasVPCLMULQDQBit = 64,
85
  Feature_HasGFNIBit = 67,
86
  Feature_HasFMABit = 28,
87
  Feature_HasFMA4Bit = 32,
88
  Feature_NoFMA4Bit = 29,
89
  Feature_HasXOPBit = 33,
90
  Feature_HasTBMBit = 9,
91
  Feature_NoTBMBit = 103,
92
  Feature_HasLWPBit = 10,
93
  Feature_HasMOVBEBit = 3,
94
  Feature_HasRDRANDBit = 4,
95
  Feature_HasF16CBit = 66,
96
  Feature_HasFSGSBaseBit = 92,
97
  Feature_HasLZCNTBit = 6,
98
  Feature_HasBMIBit = 7,
99
  Feature_HasBMI2Bit = 8,
100
  Feature_NoBMI2Bit = 102,
101
  Feature_HasVBMIBit = 73,
102
  Feature_HasVBMI2Bit = 77,
103
  Feature_HasIFMABit = 74,
104
  Feature_HasRTMBit = 86,
105
  Feature_HasSHABit = 57,
106
  Feature_HasRDSEEDBit = 5,
107
  Feature_HasSSEPrefetchBit = 45,
108
  Feature_NoSSEPrefetchBit = 83,
109
  Feature_HasPrefetchWBit = 84,
110
  Feature_HasPREFETCHWT1Bit = 85,
111
  Feature_HasLAHFSAHFBit = 2,
112
  Feature_HasMWAITXBit = 11,
113
  Feature_HasCLZEROBit = 15,
114
  Feature_HasCLDEMOTEBit = 18,
115
  Feature_HasMOVDIRIBit = 13,
116
  Feature_HasMOVDIR64BBit = 14,
117
  Feature_HasPTWRITEBit = 95,
118
  Feature_FPStackf32Bit = 24,
119
  Feature_FPStackf64Bit = 25,
120
  Feature_HasCLFLUSHOPTBit = 16,
121
  Feature_HasCLWBBit = 17,
122
  Feature_HasWBNOINVDBit = 87,
123
  Feature_HasRDPIDBit = 94,
124
  Feature_HasWAITPKGBit = 12,
125
  Feature_HasINVPCIDBit = 93,
126
  Feature_HasCmpxchg8bBit = 100,
127
  Feature_HasCmpxchg16bBit = 101,
128
  Feature_Not64BitModeBit = 0,
129
  Feature_In64BitModeBit = 1,
130
  Feature_IsLP64Bit = 97,
131
  Feature_NotLP64Bit = 96,
132
  Feature_NotWin64WithoutFPBit = 98,
133
  Feature_IsPS4Bit = 108,
134
  Feature_NotPS4Bit = 107,
135
  Feature_KernelCodeBit = 109,
136
  Feature_NearDataBit = 111,
137
  Feature_IsNotPICBit = 110,
138
  Feature_OptForSizeBit = 39,
139
  Feature_OptForMinSizeBit = 37,
140
  Feature_OptForSpeedBit = 105,
141
  Feature_UseIncDecBit = 19,
142
  Feature_NoSSE41_Or_OptForSizeBit = 41,
143
  Feature_CallImmAddrBit = 112,
144
  Feature_FavorMemIndirectCallBit = 21,
145
  Feature_HasFastSHLDRotateBit = 104,
146
  Feature_HasMFenceBit = 46,
147
  Feature_UseRetpolineIndirectCallsBit = 23,
148
  Feature_NotUseRetpolineIndirectCallsBit = 22,
149
};
150
151
PredicateBitset X86InstructionSelector::
152
14.7k
computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const {
153
14.7k
  PredicateBitset Features;
154
14.7k
  if (true)
155
14.7k
    Features[Feature_TruePredicateBit] = 1;
156
14.7k
  if (Subtarget->hasCMov())
157
13.1k
    Features[Feature_HasCMovBit] = 1;
158
14.7k
  if (!Subtarget->hasCMov())
159
1.55k
    Features[Feature_NoCMovBit] = 1;
160
14.7k
  if (Subtarget->hasMMX())
161
5.50k
    Features[Feature_HasMMXBit] = 1;
162
14.7k
  if (Subtarget->has3DNow())
163
54
    Features[Feature_Has3DNowBit] = 1;
164
14.7k
  if (Subtarget->hasSSE1())
165
13.1k
    Features[Feature_HasSSE1Bit] = 1;
166
14.7k
  if (Subtarget->hasSSE1() && 
!Subtarget->hasAVX()13.1k
)
167
8.73k
    Features[Feature_UseSSE1Bit] = 1;
168
14.7k
  if (Subtarget->hasSSE2())
169
13.0k
    Features[Feature_HasSSE2Bit] = 1;
170
14.7k
  if (Subtarget->hasSSE2() && 
!Subtarget->hasAVX()13.0k
)
171
8.66k
    Features[Feature_UseSSE2Bit] = 1;
172
14.7k
  if (Subtarget->hasSSE3())
173
8.00k
    Features[Feature_HasSSE3Bit] = 1;
174
14.7k
  if (Subtarget->hasSSE3() && 
!Subtarget->hasAVX()8.00k
)
175
3.63k
    Features[Feature_UseSSE3Bit] = 1;
176
14.7k
  if (Subtarget->hasSSSE3())
177
7.44k
    Features[Feature_HasSSSE3Bit] = 1;
178
14.7k
  if (Subtarget->hasSSSE3() && 
!Subtarget->hasAVX()7.44k
)
179
3.07k
    Features[Feature_UseSSSE3Bit] = 1;
180
14.7k
  if (Subtarget->hasSSE41() && 
!Subtarget->hasAVX()5.45k
)
181
1.07k
    Features[Feature_UseSSE41Bit] = 1;
182
14.7k
  if (Subtarget->hasSSE42())
183
4.91k
    Features[Feature_HasSSE42Bit] = 1;
184
14.7k
  if (Subtarget->hasSSE42() && 
!Subtarget->hasAVX()4.91k
)
185
545
    Features[Feature_UseSSE42Bit] = 1;
186
14.7k
  if (Subtarget->hasSSE4A())
187
301
    Features[Feature_HasSSE4ABit] = 1;
188
14.7k
  if (!Subtarget->hasAVX())
189
10.3k
    Features[Feature_NoAVXBit] = 1;
190
14.7k
  if (Subtarget->hasAVX())
191
4.37k
    Features[Feature_HasAVXBit] = 1;
192
14.7k
  if (Subtarget->hasAVX2())
193
3.29k
    Features[Feature_HasAVX2Bit] = 1;
194
14.7k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX2()4.37k
)
195
1.08k
    Features[Feature_HasAVX1OnlyBit] = 1;
196
14.7k
  if (Subtarget->hasAVX512())
197
1.60k
    Features[Feature_HasAVX512Bit] = 1;
198
14.7k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX512()4.37k
)
199
2.76k
    Features[Feature_UseAVXBit] = 1;
200
14.7k
  if (!Subtarget->hasAVX512())
201
13.1k
    Features[Feature_NoAVX512Bit] = 1;
202
14.7k
  if (Subtarget->hasCDI())
203
295
    Features[Feature_HasCDIBit] = 1;
204
14.7k
  if (Subtarget->hasVPOPCNTDQ())
205
24
    Features[Feature_HasVPOPCNTDQBit] = 1;
206
14.7k
  if (Subtarget->hasERI())
207
100
    Features[Feature_HasERIBit] = 1;
208
14.7k
  if (Subtarget->hasDQI())
209
444
    Features[Feature_HasDQIBit] = 1;
210
14.7k
  if (!Subtarget->hasDQI())
211
14.2k
    Features[Feature_NoDQIBit] = 1;
212
14.7k
  if (Subtarget->hasBWI())
213
761
    Features[Feature_HasBWIBit] = 1;
214
14.7k
  if (!Subtarget->hasBWI())
215
13.9k
    Features[Feature_NoBWIBit] = 1;
216
14.7k
  if (Subtarget->hasVLX())
217
754
    Features[Feature_HasVLXBit] = 1;
218
14.7k
  if (!Subtarget->hasVLX())
219
13.9k
    Features[Feature_NoVLXBit] = 1;
220
14.7k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasBWI()754
)
221
14.2k
    Features[Feature_NoVLX_Or_NoBWIBit] = 1;
222
14.7k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasDQI()754
)
223
14.3k
    Features[Feature_NoVLX_Or_NoDQIBit] = 1;
224
14.7k
  if (Subtarget->hasVNNI())
225
13
    Features[Feature_HasVNNIBit] = 1;
226
14.7k
  if (Subtarget->hasBITALG())
227
16
    Features[Feature_HasBITALGBit] = 1;
228
14.7k
  if (Subtarget->hasPOPCNT())
229
2.12k
    Features[Feature_HasPOPCNTBit] = 1;
230
14.7k
  if (Subtarget->hasAES())
231
501
    Features[Feature_HasAESBit] = 1;
232
14.7k
  if (Subtarget->hasVAES())
233
7
    Features[Feature_HasVAESBit] = 1;
234
14.7k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVAES()754
)
235
14.7k
    Features[Feature_NoVLX_Or_NoVAESBit] = 1;
236
14.7k
  if (Subtarget->hasFXSR())
237
5.01k
    Features[Feature_HasFXSRBit] = 1;
238
14.7k
  if (Subtarget->hasXSAVE())
239
1.78k
    Features[Feature_HasXSAVEBit] = 1;
240
14.7k
  if (Subtarget->hasXSAVEOPT())
241
1.71k
    Features[Feature_HasXSAVEOPTBit] = 1;
242
14.7k
  if (Subtarget->hasXSAVEC())
243
250
    Features[Feature_HasXSAVECBit] = 1;
244
14.7k
  if (Subtarget->hasXSAVES())
245
250
    Features[Feature_HasXSAVESBit] = 1;
246
14.7k
  if (Subtarget->hasPCLMUL())
247
946
    Features[Feature_HasPCLMULBit] = 1;
248
14.7k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVPCLMULQDQ()754
)
249
14.7k
    Features[Feature_NoVLX_Or_NoVPCLMULQDQBit] = 1;
250
14.7k
  if (Subtarget->hasVPCLMULQDQ())
251
12
    Features[Feature_HasVPCLMULQDQBit] = 1;
252
14.7k
  if (Subtarget->hasGFNI())
253
9
    Features[Feature_HasGFNIBit] = 1;
254
14.7k
  if (Subtarget->hasFMA())
255
2.81k
    Features[Feature_HasFMABit] = 1;
256
14.7k
  if (Subtarget->hasFMA4())
257
190
    Features[Feature_HasFMA4Bit] = 1;
258
14.7k
  if (!Subtarget->hasFMA4())
259
14.5k
    Features[Feature_NoFMA4Bit] = 1;
260
14.7k
  if (Subtarget->hasXOP())
261
170
    Features[Feature_HasXOPBit] = 1;
262
14.7k
  if (Subtarget->hasTBM())
263
80
    Features[Feature_HasTBMBit] = 1;
264
14.7k
  if (!Subtarget->hasTBM())
265
14.6k
    Features[Feature_NoTBMBit] = 1;
266
14.7k
  if (Subtarget->hasLWP())
267
79
    Features[Feature_HasLWPBit] = 1;
268
14.7k
  if (Subtarget->hasMOVBE())
269
1.60k
    Features[Feature_HasMOVBEBit] = 1;
270
14.7k
  if (Subtarget->hasRDRAND())
271
604
    Features[Feature_HasRDRANDBit] = 1;
272
14.7k
  if (Subtarget->hasF16C())
273
2.87k
    Features[Feature_HasF16CBit] = 1;
274
14.7k
  if (Subtarget->hasFSGSBase())
275
542
    Features[Feature_HasFSGSBaseBit] = 1;
276
14.7k
  if (Subtarget->hasLZCNT())
277
1.53k
    Features[Feature_HasLZCNTBit] = 1;
278
14.7k
  if (Subtarget->hasBMI())
279
1.56k
    Features[Feature_HasBMIBit] = 1;
280
14.7k
  if (Subtarget->hasBMI2())
281
1.42k
    Features[Feature_HasBMI2Bit] = 1;
282
14.7k
  if (!Subtarget->hasBMI2())
283
13.2k
    Features[Feature_NoBMI2Bit] = 1;
284
14.7k
  if (Subtarget->hasVBMI())
285
48
    Features[Feature_HasVBMIBit] = 1;
286
14.7k
  if (Subtarget->hasVBMI2())
287
28
    Features[Feature_HasVBMI2Bit] = 1;
288
14.7k
  if (Subtarget->hasIFMA())
289
19
    Features[Feature_HasIFMABit] = 1;
290
14.7k
  if (Subtarget->hasRTM())
291
10
    Features[Feature_HasRTMBit] = 1;
292
14.7k
  if (Subtarget->hasSHA())
293
70
    Features[Feature_HasSHABit] = 1;
294
14.7k
  if (Subtarget->hasRDSEED())
295
360
    Features[Feature_HasRDSEEDBit] = 1;
296
14.7k
  if (Subtarget->hasSSEPrefetch())
297
13.1k
    Features[Feature_HasSSEPrefetchBit] = 1;
298
14.7k
  if (!Subtarget->hasSSEPrefetch())
299
1.60k
    Features[Feature_NoSSEPrefetchBit] = 1;
300
14.7k
  if (Subtarget->hasPRFCHW())
301
580
    Features[Feature_HasPrefetchWBit] = 1;
302
14.7k
  if (Subtarget->hasPREFETCHWT1())
303
101
    Features[Feature_HasPREFETCHWT1Bit] = 1;
304
14.7k
  if (Subtarget->hasLAHFSAHF())
305
7.06k
    Features[Feature_HasLAHFSAHFBit] = 1;
306
14.7k
  if (Subtarget->hasMWAITX())
307
29
    Features[Feature_HasMWAITXBit] = 1;
308
14.7k
  if (Subtarget->hasCLZERO())
309
16
    Features[Feature_HasCLZEROBit] = 1;
310
14.7k
  if (Subtarget->hasCLDEMOTE())
311
3
    Features[Feature_HasCLDEMOTEBit] = 1;
312
14.7k
  if (Subtarget->hasMOVDIRI())
313
4
    Features[Feature_HasMOVDIRIBit] = 1;
314
14.7k
  if (Subtarget->hasMOVDIR64B())
315
3
    Features[Feature_HasMOVDIR64BBit] = 1;
316
14.7k
  if (Subtarget->hasPTWRITE())
317
6
    Features[Feature_HasPTWRITEBit] = 1;
318
14.7k
  if (!Subtarget->hasSSE1())
319
1.61k
    Features[Feature_FPStackf32Bit] = 1;
320
14.7k
  if (!Subtarget->hasSSE2())
321
1.68k
    Features[Feature_FPStackf64Bit] = 1;
322
14.7k
  if (Subtarget->hasCLFLUSHOPT())
323
250
    Features[Feature_HasCLFLUSHOPTBit] = 1;
324
14.7k
  if (Subtarget->hasCLWB())
325
167
    Features[Feature_HasCLWBBit] = 1;
326
14.7k
  if (Subtarget->hasWBNOINVD())
327
9
    Features[Feature_HasWBNOINVDBit] = 1;
328
14.7k
  if (Subtarget->hasRDPID())
329
14
    Features[Feature_HasRDPIDBit] = 1;
330
14.7k
  if (Subtarget->hasWAITPKG())
331
3
    Features[Feature_HasWAITPKGBit] = 1;
332
14.7k
  if (Subtarget->hasINVPCID())
333
1.26k
    Features[Feature_HasINVPCIDBit] = 1;
334
14.7k
  if (Subtarget->hasCmpxchg8b())
335
14.6k
    Features[Feature_HasCmpxchg8bBit] = 1;
336
14.7k
  if (Subtarget->hasCmpxchg16b())
337
4.00k
    Features[Feature_HasCmpxchg16bBit] = 1;
338
14.7k
  if (!Subtarget->is64Bit())
339
3.07k
    Features[Feature_Not64BitModeBit] = 1;
340
14.7k
  if (Subtarget->is64Bit())
341
11.6k
    Features[Feature_In64BitModeBit] = 1;
342
14.7k
  if (Subtarget->isTarget64BitLP64())
343
11.5k
    Features[Feature_IsLP64Bit] = 1;
344
14.7k
  if (!Subtarget->isTarget64BitLP64())
345
3.14k
    Features[Feature_NotLP64Bit] = 1;
346
14.7k
  if (Subtarget->isTargetPS4())
347
38
    Features[Feature_IsPS4Bit] = 1;
348
14.7k
  if (!Subtarget->isTargetPS4())
349
14.6k
    Features[Feature_NotPS4Bit] = 1;
350
14.7k
  if (TM.getCodeModel() == CodeModel::Kernel)
351
4
    Features[Feature_KernelCodeBit] = 1;
352
14.7k
  if (TM.getCodeModel() == CodeModel::Small ||
TM.getCodeModel() == CodeModel::Kernel250
)
353
14.4k
    Features[Feature_NearDataBit] = 1;
354
14.7k
  if (!TM.isPositionIndependent())
355
7.97k
    Features[Feature_IsNotPICBit] = 1;
356
14.7k
  if (Subtarget->isLegalToCallImmediateAddr())
357
1.78k
    Features[Feature_CallImmAddrBit] = 1;
358
14.7k
  if (!Subtarget->slowTwoMemOps())
359
14.4k
    Features[Feature_FavorMemIndirectCallBit] = 1;
360
14.7k
  if (Subtarget->hasFastSHLDRotate())
361
1.46k
    Features[Feature_HasFastSHLDRotateBit] = 1;
362
14.7k
  if (Subtarget->hasMFence())
363
13.0k
    Features[Feature_HasMFenceBit] = 1;
364
14.7k
  if (Subtarget->useRetpolineIndirectCalls())
365
17
    Features[Feature_UseRetpolineIndirectCallsBit] = 1;
366
14.7k
  if (!Subtarget->useRetpolineIndirectCalls())
367
14.7k
    Features[Feature_NotUseRetpolineIndirectCallsBit] = 1;
368
14.7k
  return Features;
369
14.7k
}
370
371
PredicateBitset X86InstructionSelector::
372
2.27k
computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, const MachineFunction *MF) const {
373
2.27k
  PredicateBitset Features;
374
2.27k
  if (!Subtarget->isTargetWin64() ||
Subtarget->getFrameLowering()->hasFP(*MF)0
)
375
2.27k
    Features[Feature_NotWin64WithoutFPBit] = 1;
376
2.27k
  if (MF->getFunction().optForSize())
377
2
    Features[Feature_OptForSizeBit] = 1;
378
2.27k
  if (MF->getFunction().optForMinSize())
379
0
    Features[Feature_OptForMinSizeBit] = 1;
380
2.27k
  if (!MF->getFunction().optForSize())
381
2.26k
    Features[Feature_OptForSpeedBit] = 1;
382
2.27k
  if (!Subtarget->slowIncDec() || 
MF->getFunction().optForSize()9
)
383
2.26k
    Features[Feature_UseIncDecBit] = 1;
384
2.27k
  if (MF->getFunction().optForSize() || 
!Subtarget->hasSSE41()2.26k
)
385
1.44k
    Features[Feature_NoSSE41_Or_OptForSizeBit] = 1;
386
2.27k
  return Features;
387
2.27k
}
388
389
// LLT Objects.
390
enum {
391
  GILLT_s1,
392
  GILLT_s8,
393
  GILLT_s16,
394
  GILLT_s32,
395
  GILLT_s64,
396
  GILLT_s80,
397
  GILLT_s128,
398
  GILLT_v2s1,
399
  GILLT_v2s64,
400
  GILLT_v4s1,
401
  GILLT_v4s32,
402
  GILLT_v4s64,
403
  GILLT_v8s1,
404
  GILLT_v8s16,
405
  GILLT_v8s32,
406
  GILLT_v8s64,
407
  GILLT_v16s1,
408
  GILLT_v16s8,
409
  GILLT_v16s16,
410
  GILLT_v16s32,
411
  GILLT_v32s1,
412
  GILLT_v32s8,
413
  GILLT_v32s16,
414
  GILLT_v64s1,
415
  GILLT_v64s8,
416
};
417
const static size_t NumTypeObjects = 25;
418
const static LLT TypeObjects[] = {
419
  LLT::scalar(1),
420
  LLT::scalar(8),
421
  LLT::scalar(16),
422
  LLT::scalar(32),
423
  LLT::scalar(64),
424
  LLT::scalar(80),
425
  LLT::scalar(128),
426
  LLT::vector(2, 1),
427
  LLT::vector(2, 64),
428
  LLT::vector(4, 1),
429
  LLT::vector(4, 32),
430
  LLT::vector(4, 64),
431
  LLT::vector(8, 1),
432
  LLT::vector(8, 16),
433
  LLT::vector(8, 32),
434
  LLT::vector(8, 64),
435
  LLT::vector(16, 1),
436
  LLT::vector(16, 8),
437
  LLT::vector(16, 16),
438
  LLT::vector(16, 32),
439
  LLT::vector(32, 1),
440
  LLT::vector(32, 8),
441
  LLT::vector(32, 16),
442
  LLT::vector(64, 1),
443
  LLT::vector(64, 8),
444
};
445
446
// Feature bitsets.
447
enum {
448
  GIFBS_Invalid,
449
  GIFBS_FPStackf32,
450
  GIFBS_FPStackf64,
451
  GIFBS_Has3DNow,
452
  GIFBS_HasAVX,
453
  GIFBS_HasAVX1Only,
454
  GIFBS_HasAVX2,
455
  GIFBS_HasAVX512,
456
  GIFBS_HasBITALG,
457
  GIFBS_HasBMI,
458
  GIFBS_HasBMI2,
459
  GIFBS_HasBWI,
460
  GIFBS_HasCDI,
461
  GIFBS_HasDQI,
462
  GIFBS_HasLWP,
463
  GIFBS_HasMFence,
464
  GIFBS_HasMMX,
465
  GIFBS_HasMOVBE,
466
  GIFBS_HasPTWRITE,
467
  GIFBS_HasRTM,
468
  GIFBS_HasSHA,
469
  GIFBS_HasSSE1,
470
  GIFBS_HasSSE2,
471
  GIFBS_HasSSE42,
472
  GIFBS_HasSSE4A,
473
  GIFBS_HasTBM,
474
  GIFBS_HasVLX,
475
  GIFBS_HasVPOPCNTDQ,
476
  GIFBS_HasWAITPKG,
477
  GIFBS_HasWBNOINVD,
478
  GIFBS_HasXOP,
479
  GIFBS_In64BitMode,
480
  GIFBS_NoDQI,
481
  GIFBS_Not64BitMode,
482
  GIFBS_UseAVX,
483
  GIFBS_UseIncDec,
484
  GIFBS_UseSSE1,
485
  GIFBS_UseSSE2,
486
  GIFBS_UseSSE41,
487
  GIFBS_UseSSSE3,
488
  GIFBS_HasAES_HasAVX,
489
  GIFBS_HasAES_NoAVX,
490
  GIFBS_HasAVX_NoVLX,
491
  GIFBS_HasAVX_NoVLX_Or_NoBWI,
492
  GIFBS_HasAVX2_NoVLX,
493
  GIFBS_HasAVX2_NoVLX_Or_NoBWI,
494
  GIFBS_HasAVX512_HasVAES,
495
  GIFBS_HasAVX512_HasVLX,
496
  GIFBS_HasAVX512_HasVPCLMULQDQ,
497
  GIFBS_HasAVX512_NoBWI,
498
  GIFBS_HasBITALG_HasVLX,
499
  GIFBS_HasBWI_HasVLX,
500
  GIFBS_HasCDI_HasVLX,
501
  GIFBS_HasDQI_HasVLX,
502
  GIFBS_HasDQI_NoBWI,
503
  GIFBS_HasFSGSBase_In64BitMode,
504
  GIFBS_HasPCLMUL_NoAVX,
505
  GIFBS_HasPTWRITE_In64BitMode,
506
  GIFBS_HasRDPID_Not64BitMode,
507
  GIFBS_HasSSE2_NoAVX512,
508
  GIFBS_HasVAES_HasVLX,
509
  GIFBS_HasVAES_NoVLX,
510
  GIFBS_HasVLX_HasVPCLMULQDQ,
511
  GIFBS_HasVLX_HasVPOPCNTDQ,
512
  GIFBS_HasVPCLMULQDQ_NoVLX,
513
  GIFBS_HasWAITPKG_In64BitMode,
514
  GIFBS_HasWAITPKG_Not64BitMode,
515
  GIFBS_Not64BitMode_OptForSize,
516
  GIFBS_NotWin64WithoutFP_OptForMinSize,
517
  GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES,
518
  GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ,
519
  GIFBS_HasDQI_HasVLX_NoBWI,
520
};
521
const static PredicateBitset FeatureBitsets[] {
522
  {}, // GIFBS_Invalid
523
  {Feature_FPStackf32Bit, },
524
  {Feature_FPStackf64Bit, },
525
  {Feature_Has3DNowBit, },
526
  {Feature_HasAVXBit, },
527
  {Feature_HasAVX1OnlyBit, },
528
  {Feature_HasAVX2Bit, },
529
  {Feature_HasAVX512Bit, },
530
  {Feature_HasBITALGBit, },
531
  {Feature_HasBMIBit, },
532
  {Feature_HasBMI2Bit, },
533
  {Feature_HasBWIBit, },
534
  {Feature_HasCDIBit, },
535
  {Feature_HasDQIBit, },
536
  {Feature_HasLWPBit, },
537
  {Feature_HasMFenceBit, },
538
  {Feature_HasMMXBit, },
539
  {Feature_HasMOVBEBit, },
540
  {Feature_HasPTWRITEBit, },
541
  {Feature_HasRTMBit, },
542
  {Feature_HasSHABit, },
543
  {Feature_HasSSE1Bit, },
544
  {Feature_HasSSE2Bit, },
545
  {Feature_HasSSE42Bit, },
546
  {Feature_HasSSE4ABit, },
547
  {Feature_HasTBMBit, },
548
  {Feature_HasVLXBit, },
549
  {Feature_HasVPOPCNTDQBit, },
550
  {Feature_HasWAITPKGBit, },
551
  {Feature_HasWBNOINVDBit, },
552
  {Feature_HasXOPBit, },
553
  {Feature_In64BitModeBit, },
554
  {Feature_NoDQIBit, },
555
  {Feature_Not64BitModeBit, },
556
  {Feature_UseAVXBit, },
557
  {Feature_UseIncDecBit, },
558
  {Feature_UseSSE1Bit, },
559
  {Feature_UseSSE2Bit, },
560
  {Feature_UseSSE41Bit, },
561
  {Feature_UseSSSE3Bit, },
562
  {Feature_HasAESBit, Feature_HasAVXBit, },
563
  {Feature_HasAESBit, Feature_NoAVXBit, },
564
  {Feature_HasAVXBit, Feature_NoVLXBit, },
565
  {Feature_HasAVXBit, Feature_NoVLX_Or_NoBWIBit, },
566
  {Feature_HasAVX2Bit, Feature_NoVLXBit, },
567
  {Feature_HasAVX2Bit, Feature_NoVLX_Or_NoBWIBit, },
568
  {Feature_HasAVX512Bit, Feature_HasVAESBit, },
569
  {Feature_HasAVX512Bit, Feature_HasVLXBit, },
570
  {Feature_HasAVX512Bit, Feature_HasVPCLMULQDQBit, },
571
  {Feature_HasAVX512Bit, Feature_NoBWIBit, },
572
  {Feature_HasBITALGBit, Feature_HasVLXBit, },
573
  {Feature_HasBWIBit, Feature_HasVLXBit, },
574
  {Feature_HasCDIBit, Feature_HasVLXBit, },
575
  {Feature_HasDQIBit, Feature_HasVLXBit, },
576
  {Feature_HasDQIBit, Feature_NoBWIBit, },
577
  {Feature_HasFSGSBaseBit, Feature_In64BitModeBit, },
578
  {Feature_HasPCLMULBit, Feature_NoAVXBit, },
579
  {Feature_HasPTWRITEBit, Feature_In64BitModeBit, },
580
  {Feature_HasRDPIDBit, Feature_Not64BitModeBit, },
581
  {Feature_HasSSE2Bit, Feature_NoAVX512Bit, },
582
  {Feature_HasVAESBit, Feature_HasVLXBit, },
583
  {Feature_HasVAESBit, Feature_NoVLXBit, },
584
  {Feature_HasVLXBit, Feature_HasVPCLMULQDQBit, },
585
  {Feature_HasVLXBit, Feature_HasVPOPCNTDQBit, },
586
  {Feature_HasVPCLMULQDQBit, Feature_NoVLXBit, },
587
  {Feature_HasWAITPKGBit, Feature_In64BitModeBit, },
588
  {Feature_HasWAITPKGBit, Feature_Not64BitModeBit, },
589
  {Feature_Not64BitModeBit, Feature_OptForSizeBit, },
590
  {Feature_NotWin64WithoutFPBit, Feature_OptForMinSizeBit, },
591
  {Feature_HasAESBit, Feature_HasAVXBit, Feature_NoVLX_Or_NoVAESBit, },
592
  {Feature_HasAVXBit, Feature_HasPCLMULBit, Feature_NoVLX_Or_NoVPCLMULQDQBit, },
593
  {Feature_HasDQIBit, Feature_HasVLXBit, Feature_NoBWIBit, },
594
};
595
596
// ComplexPattern predicates.
597
enum {
598
  GICP_Invalid,
599
};
600
// See constructor for table contents
601
602
// PatFrag predicates.
603
enum {
604
  GIPFP_I64_Predicate_AndMask64 = GIPFP_I64_Invalid + 1,
605
  GIPFP_I64_Predicate_BTCBTSMask64,
606
  GIPFP_I64_Predicate_BTRMask64,
607
  GIPFP_I64_Predicate_PrefetchWT1Level,
608
  GIPFP_I64_Predicate_i16immSExt8,
609
  GIPFP_I64_Predicate_i32immSExt8,
610
  GIPFP_I64_Predicate_i64immSExt32,
611
  GIPFP_I64_Predicate_i64immSExt8,
612
  GIPFP_I64_Predicate_i64immZExt32,
613
  GIPFP_I64_Predicate_i64immZExt32SExt8,
614
  GIPFP_I64_Predicate_immff00_ffff,
615
};
616
74
bool X86InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
617
74
  switch (PredicateID) {
618
74
  case GIPFP_I64_Predicate_AndMask64: {
619
0
    
620
0
  return isMask_64(Imm) && !isUInt<32>(Imm);
621
74
622
74
    
llvm_unreachable0
("ImmediateCode should have returned");
623
74
    
return false0
;
624
74
  }
625
74
  case GIPFP_I64_Predicate_BTCBTSMask64: {
626
0
    
627
0
  return !isInt<32>(Imm) && isPowerOf2_64(Imm);
628
74
629
74
    
llvm_unreachable0
("ImmediateCode should have returned");
630
74
    
return false0
;
631
74
  }
632
74
  case GIPFP_I64_Predicate_BTRMask64: {
633
0
    
634
0
  return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);
635
74
636
74
    
llvm_unreachable0
("ImmediateCode should have returned");
637
74
    
return false0
;
638
74
  }
639
74
  case GIPFP_I64_Predicate_PrefetchWT1Level: {
640
0
    
641
0
  return Imm < 3;
642
74
643
74
    
llvm_unreachable0
("ImmediateCode should have returned");
644
74
    
return false0
;
645
74
  }
646
74
  case GIPFP_I64_Predicate_i16immSExt8: {
647
5
     return isInt<8>(Imm); 
648
74
    
llvm_unreachable0
("ImmediateCode should have returned");
649
74
    
return false0
;
650
74
  }
651
74
  case GIPFP_I64_Predicate_i32immSExt8: {
652
21
     return isInt<8>(Imm); 
653
74
    
llvm_unreachable0
("ImmediateCode should have returned");
654
74
    
return false0
;
655
74
  }
656
74
  case GIPFP_I64_Predicate_i64immSExt32: {
657
43
     return isInt<32>(Imm); 
658
74
    
llvm_unreachable0
("ImmediateCode should have returned");
659
74
    
return false0
;
660
74
  }
661
74
  case GIPFP_I64_Predicate_i64immSExt8: {
662
5
     return isInt<8>(Imm); 
663
74
    
llvm_unreachable0
("ImmediateCode should have returned");
664
74
    
return false0
;
665
74
  }
666
74
  case GIPFP_I64_Predicate_i64immZExt32: {
667
0
     return isUInt<32>(Imm); 
668
74
    
llvm_unreachable0
("ImmediateCode should have returned");
669
74
    
return false0
;
670
74
  }
671
74
  case GIPFP_I64_Predicate_i64immZExt32SExt8: {
672
0
    
673
0
  return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
674
74
675
74
    
llvm_unreachable0
("ImmediateCode should have returned");
676
74
    
return false0
;
677
74
  }
678
74
  case GIPFP_I64_Predicate_immff00_ffff: {
679
0
    
680
0
  return Imm >= 0xff00 && Imm <= 0xffff;
681
74
682
74
    
llvm_unreachable0
("ImmediateCode should have returned");
683
74
    
return false0
;
684
0
  }
685
0
  }
686
0
  llvm_unreachable("Unknown predicate");
687
0
  return false;
688
0
}
689
// PatFrag predicates.
690
enum {
691
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
692
  GIPFP_APFloat_Predicate_fpimm1,
693
  GIPFP_APFloat_Predicate_fpimmneg0,
694
  GIPFP_APFloat_Predicate_fpimmneg1,
695
};
696
5
bool X86InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
697
5
  switch (PredicateID) {
698
5
  case GIPFP_APFloat_Predicate_fpimm0: {
699
5
    
700
5
  return Imm.isExactlyValue(+0.0);
701
5
702
5
    
llvm_unreachable0
("ImmediateCode should have returned");
703
5
    
return false0
;
704
5
  }
705
5
  case GIPFP_APFloat_Predicate_fpimm1: {
706
0
    
707
0
  return Imm.isExactlyValue(+1.0);
708
5
709
5
    
llvm_unreachable0
("ImmediateCode should have returned");
710
5
    
return false0
;
711
5
  }
712
5
  case GIPFP_APFloat_Predicate_fpimmneg0: {
713
0
    
714
0
  return Imm.isExactlyValue(-0.0);
715
5
716
5
    
llvm_unreachable0
("ImmediateCode should have returned");
717
5
    
return false0
;
718
5
  }
719
5
  case GIPFP_APFloat_Predicate_fpimmneg1: {
720
0
    
721
0
  return Imm.isExactlyValue(-1.0);
722
5
723
5
    
llvm_unreachable0
("ImmediateCode should have returned");
724
5
    
return false0
;
725
0
  }
726
0
  }
727
0
  llvm_unreachable("Unknown predicate");
728
0
  return false;
729
0
}
730
0
bool X86InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
731
0
  llvm_unreachable("Unknown predicate");
732
0
  return false;
733
0
}
734
0
bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
735
0
  const MachineFunction &MF = *MI.getParent()->getParent();
736
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
737
0
  (void)MRI;
738
0
  llvm_unreachable("Unknown predicate");
739
0
  return false;
740
0
}
741
742
X86InstructionSelector::ComplexMatcherMemFn
743
X86InstructionSelector::ComplexPredicateFns[] = {
744
  nullptr, // GICP_Invalid
745
};
746
747
// Custom renderers.
748
enum {
749
  GICR_Invalid,
750
};
751
X86InstructionSelector::CustomRendererFn
752
X86InstructionSelector::CustomRenderers[] = {
753
  nullptr, // GICP_Invalid
754
};
755
756
2.27k
bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
757
2.27k
  MachineFunction &MF = *I.getParent()->getParent();
758
2.27k
  MachineRegisterInfo &MRI = MF.getRegInfo();
759
2.27k
  // FIXME: This should be computed on a per-function basis rather than per-insn.
760
2.27k
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
761
2.27k
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
762
2.27k
  NewMIVector OutMIs;
763
2.27k
  State.MIs.clear();
764
2.27k
  State.MIs.push_back(&I);
765
2.27k
766
2.27k
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
767
803
    return true;
768
803
  }
769
1.46k
770
1.46k
  return false;
771
1.46k
}
772
773
2.27k
const int64_t *X86InstructionSelector::getMatchTable() const {
774
2.27k
  constexpr static int64_t MatchTable0[] = {
775
2.27k
    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 146, /*)*//*default:*//*Label 41*/ 33222,
776
2.27k
    /*TargetOpcode::G_ADD*//*Label 0*/ 116,
777
2.27k
    /*TargetOpcode::G_SUB*//*Label 1*/ 1733,
778
2.27k
    /*TargetOpcode::G_MUL*//*Label 2*/ 2814, 0, 0, 0, 0,
779
2.27k
    /*TargetOpcode::G_AND*//*Label 3*/ 3580,
780
2.27k
    /*TargetOpcode::G_OR*//*Label 4*/ 7085,
781
2.27k
    /*TargetOpcode::G_XOR*//*Label 5*/ 10339, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
782
2.27k
    /*TargetOpcode::G_CONCAT_VECTORS*//*Label 6*/ 12895, 0, 0,
783
2.27k
    /*TargetOpcode::G_BITCAST*//*Label 7*/ 13147, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
784
2.27k
    /*TargetOpcode::G_INTRINSIC*//*Label 8*/ 13547,
785
2.27k
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 9*/ 19642,
786
2.27k
    /*TargetOpcode::G_ANYEXT*//*Label 10*/ 21073,
787
2.27k
    /*TargetOpcode::G_TRUNC*//*Label 11*/ 21881,
788
2.27k
    /*TargetOpcode::G_CONSTANT*//*Label 12*/ 22312,
789
2.27k
    /*TargetOpcode::G_FCONSTANT*//*Label 13*/ 22515, 0, 0,
790
2.27k
    /*TargetOpcode::G_SEXT*//*Label 14*/ 22708,
791
2.27k
    /*TargetOpcode::G_ZEXT*//*Label 15*/ 23513,
792
2.27k
    /*TargetOpcode::G_SHL*//*Label 16*/ 23927,
793
2.27k
    /*TargetOpcode::G_LSHR*//*Label 17*/ 24242,
794
2.27k
    /*TargetOpcode::G_ASHR*//*Label 18*/ 24541, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
795
2.27k
    /*TargetOpcode::G_FADD*//*Label 19*/ 24840,
796
2.27k
    /*TargetOpcode::G_FSUB*//*Label 20*/ 25462,
797
2.27k
    /*TargetOpcode::G_FMUL*//*Label 21*/ 26084, 0,
798
2.27k
    /*TargetOpcode::G_FDIV*//*Label 22*/ 26706, 0, 0, 0, 0, 0, 0, 0,
799
2.27k
    /*TargetOpcode::G_FNEG*//*Label 23*/ 27328,
800
2.27k
    /*TargetOpcode::G_FPEXT*//*Label 24*/ 27426,
801
2.27k
    /*TargetOpcode::G_FPTRUNC*//*Label 25*/ 27702,
802
2.27k
    /*TargetOpcode::G_FPTOSI*//*Label 26*/ 27987,
803
2.27k
    /*TargetOpcode::G_FPTOUI*//*Label 27*/ 28617,
804
2.27k
    /*TargetOpcode::G_SITOFP*//*Label 28*/ 28971,
805
2.27k
    /*TargetOpcode::G_UITOFP*//*Label 29*/ 29801,
806
2.27k
    /*TargetOpcode::G_FABS*//*Label 30*/ 30255, 0, 0, 0,
807
2.27k
    /*TargetOpcode::G_BR*//*Label 31*/ 30353, 0, 0, 0, 0,
808
2.27k
    /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 32*/ 30366,
809
2.27k
    /*TargetOpcode::G_CTLZ*//*Label 33*/ 30451, 0,
810
2.27k
    /*TargetOpcode::G_CTPOP*//*Label 34*/ 30614,
811
2.27k
    /*TargetOpcode::G_BSWAP*//*Label 35*/ 30926,
812
2.27k
    /*TargetOpcode::G_FCEIL*//*Label 36*/ 31016,
813
2.27k
    /*TargetOpcode::G_FCOS*//*Label 37*/ 31720,
814
2.27k
    /*TargetOpcode::G_FSIN*//*Label 38*/ 31818,
815
2.27k
    /*TargetOpcode::G_FSQRT*//*Label 39*/ 31916,
816
2.27k
    /*TargetOpcode::G_FFLOOR*//*Label 40*/ 32518,
817
2.27k
    // Label 0: @116
818
2.27k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 58*/ 1732,
819
2.27k
    /*GILLT_s8*//*Label 42*/ 146,
820
2.27k
    /*GILLT_s16*//*Label 43*/ 260,
821
2.27k
    /*GILLT_s32*//*Label 44*/ 432,
822
2.27k
    /*GILLT_s64*//*Label 45*/ 604, 0, 0, 0,
823
2.27k
    /*GILLT_v2s64*//*Label 46*/ 804, 0,
824
2.27k
    /*GILLT_v4s32*//*Label 47*/ 885,
825
2.27k
    /*GILLT_v4s64*//*Label 48*/ 1088, 0,
826
2.27k
    /*GILLT_v8s16*//*Label 49*/ 1146,
827
2.27k
    /*GILLT_v8s32*//*Label 50*/ 1349,
828
2.27k
    /*GILLT_v8s64*//*Label 51*/ 1407, 0,
829
2.27k
    /*GILLT_v16s8*//*Label 52*/ 1439,
830
2.27k
    /*GILLT_v16s16*//*Label 53*/ 1520,
831
2.27k
    /*GILLT_v16s32*//*Label 54*/ 1578, 0,
832
2.27k
    /*GILLT_v32s8*//*Label 55*/ 1610,
833
2.27k
    /*GILLT_v32s16*//*Label 56*/ 1668, 0,
834
2.27k
    /*GILLT_v64s8*//*Label 57*/ 1700,
835
2.27k
    // Label 42: @146
836
2.27k
    GIM_Try, /*On fail goto*//*Label 59*/ 259,
837
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
838
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
839
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
840
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
841
2.27k
      GIM_Try, /*On fail goto*//*Label 60*/ 188, // Rule ID 17366 //
842
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
843
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
844
2.27k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, 1:{ *:[i8] })  =>  (INC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
845
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r,
846
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
847
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
848
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
849
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
850
2.27k
        // GIR_Coverage, 17366,
851
2.27k
        GIR_Done,
852
2.27k
      // Label 60: @188
853
2.27k
      GIM_Try, /*On fail goto*//*Label 61*/ 212, // Rule ID 17370 //
854
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
855
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
856
2.27k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, -1:{ *:[i8] })  =>  (DEC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
857
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r,
858
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
859
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
860
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
861
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
862
2.27k
        // GIR_Coverage, 17370,
863
2.27k
        GIR_Done,
864
2.27k
      // Label 61: @212
865
2.27k
      GIM_Try, /*On fail goto*//*Label 62*/ 242, // Rule ID 17321 //
866
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
867
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
868
2.27k
        // MIs[1] Operand 1
869
2.27k
        // No operand predicates
870
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
871
2.27k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
872
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri,
873
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
874
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
875
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
876
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
877
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
878
2.27k
        // GIR_Coverage, 17321,
879
2.27k
        GIR_Done,
880
2.27k
      // Label 62: @242
881
2.27k
      GIM_Try, /*On fail goto*//*Label 63*/ 258, // Rule ID 17313 //
882
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
883
2.27k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
884
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD8rr,
885
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
886
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
887
2.27k
        // GIR_Coverage, 17313,
888
2.27k
        GIR_Done,
889
2.27k
      // Label 63: @258
890
2.27k
      GIM_Reject,
891
2.27k
    // Label 59: @259
892
2.27k
    GIM_Reject,
893
2.27k
    // Label 43: @260
894
2.27k
    GIM_Try, /*On fail goto*//*Label 64*/ 431,
895
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
896
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
897
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
898
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
899
2.27k
      GIM_Try, /*On fail goto*//*Label 65*/ 303, // Rule ID 17175 //
900
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
901
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, 128:{ *:[i16] })  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -128:{ *:[i16] })
902
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
903
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
904
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
905
2.27k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
906
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
907
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
908
2.27k
        // GIR_Coverage, 17175,
909
2.27k
        GIR_Done,
910
2.27k
      // Label 65: @303
911
2.27k
      GIM_Try, /*On fail goto*//*Label 66*/ 327, // Rule ID 17367 //
912
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
913
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
914
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, 1:{ *:[i16] })  =>  (INC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
915
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r,
916
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
917
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
918
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
919
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
920
2.27k
        // GIR_Coverage, 17367,
921
2.27k
        GIR_Done,
922
2.27k
      // Label 66: @327
923
2.27k
      GIM_Try, /*On fail goto*//*Label 67*/ 351, // Rule ID 17371 //
924
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
925
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
926
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, -1:{ *:[i16] })  =>  (DEC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
927
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r,
928
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
929
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
930
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
931
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
932
2.27k
        // GIR_Coverage, 17371,
933
2.27k
        GIR_Done,
934
2.27k
      // Label 67: @351
935
2.27k
      GIM_Try, /*On fail goto*//*Label 68*/ 384, // Rule ID 17324 //
936
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
937
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
938
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
939
2.27k
        // MIs[1] Operand 1
940
2.27k
        // No operand predicates
941
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
942
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (ADD16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
943
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8,
944
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
945
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
946
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
947
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
948
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
949
2.27k
        // GIR_Coverage, 17324,
950
2.27k
        GIR_Done,
951
2.27k
      // Label 68: @384
952
2.27k
      GIM_Try, /*On fail goto*//*Label 69*/ 414, // Rule ID 17322 //
953
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
954
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
955
2.27k
        // MIs[1] Operand 1
956
2.27k
        // No operand predicates
957
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
958
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
959
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri,
960
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
961
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
962
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
963
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
964
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
965
2.27k
        // GIR_Coverage, 17322,
966
2.27k
        GIR_Done,
967
2.27k
      // Label 69: @414
968
2.27k
      GIM_Try, /*On fail goto*//*Label 70*/ 430, // Rule ID 17314 //
969
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
970
2.27k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
971
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD16rr,
972
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
973
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
974
2.27k
        // GIR_Coverage, 17314,
975
2.27k
        GIR_Done,
976
2.27k
      // Label 70: @430
977
2.27k
      GIM_Reject,
978
2.27k
    // Label 64: @431
979
2.27k
    GIM_Reject,
980
2.27k
    // Label 44: @432
981
2.27k
    GIM_Try, /*On fail goto*//*Label 71*/ 603,
982
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
983
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
984
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
985
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
986
2.27k
      GIM_Try, /*On fail goto*//*Label 72*/ 475, // Rule ID 17177 //
987
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
988
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, 128:{ *:[i32] })  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -128:{ *:[i32] })
989
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
990
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
991
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
992
2.27k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
993
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
994
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
995
2.27k
        // GIR_Coverage, 17177,
996
2.27k
        GIR_Done,
997
2.27k
      // Label 72: @475
998
2.27k
      GIM_Try, /*On fail goto*//*Label 73*/ 499, // Rule ID 17368 //
999
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1000
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1001
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (INC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1002
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r,
1003
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1004
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1005
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1006
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1007
2.27k
        // GIR_Coverage, 17368,
1008
2.27k
        GIR_Done,
1009
2.27k
      // Label 73: @499
1010
2.27k
      GIM_Try, /*On fail goto*//*Label 74*/ 523, // Rule ID 17372 //
1011
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1012
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1013
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })  =>  (DEC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1014
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r,
1015
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1016
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1017
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1018
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1019
2.27k
        // GIR_Coverage, 17372,
1020
2.27k
        GIR_Done,
1021
2.27k
      // Label 74: @523
1022
2.27k
      GIM_Try, /*On fail goto*//*Label 75*/ 556, // Rule ID 17325 //
1023
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1024
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1025
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1026
2.27k
        // MIs[1] Operand 1
1027
2.27k
        // No operand predicates
1028
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1029
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (ADD32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1030
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8,
1031
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1032
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1033
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1034
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1035
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1036
2.27k
        // GIR_Coverage, 17325,
1037
2.27k
        GIR_Done,
1038
2.27k
      // Label 75: @556
1039
2.27k
      GIM_Try, /*On fail goto*//*Label 76*/ 586, // Rule ID 17323 //
1040
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1041
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1042
2.27k
        // MIs[1] Operand 1
1043
2.27k
        // No operand predicates
1044
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1045
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1046
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri,
1047
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1048
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1049
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1050
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1051
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1052
2.27k
        // GIR_Coverage, 17323,
1053
2.27k
        GIR_Done,
1054
2.27k
      // Label 76: @586
1055
2.27k
      GIM_Try, /*On fail goto*//*Label 77*/ 602, // Rule ID 17315 //
1056
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1057
2.27k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1058
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD32rr,
1059
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1060
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1061
2.27k
        // GIR_Coverage, 17315,
1062
2.27k
        GIR_Done,
1063
2.27k
      // Label 77: @602
1064
2.27k
      GIM_Reject,
1065
2.27k
    // Label 71: @603
1066
2.27k
    GIM_Reject,
1067
2.27k
    // Label 45: @604
1068
2.27k
    GIM_Try, /*On fail goto*//*Label 78*/ 803,
1069
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1070
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1071
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1072
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1073
2.27k
      GIM_Try, /*On fail goto*//*Label 79*/ 647, // Rule ID 17179 //
1074
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
1075
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 128:{ *:[i64] })  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -128:{ *:[i64] })
1076
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1077
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1078
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1079
2.27k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
1080
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1081
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1082
2.27k
        // GIR_Coverage, 17179,
1083
2.27k
        GIR_Done,
1084
2.27k
      // Label 79: @647
1085
2.27k
      GIM_Try, /*On fail goto*//*Label 80*/ 672, // Rule ID 17184 //
1086
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 2147483648,
1087
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 2147483648:{ *:[i64] })  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -2147483648:{ *:[i64] })
1088
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1089
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1090
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1091
2.27k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648,
1092
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1093
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1094
2.27k
        // GIR_Coverage, 17184,
1095
2.27k
        GIR_Done,
1096
2.27k
      // Label 80: @672
1097
2.27k
      GIM_Try, /*On fail goto*//*Label 81*/ 696, // Rule ID 17369 //
1098
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1099
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1100
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })  =>  (INC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1101
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r,
1102
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1103
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1104
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1105
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1106
2.27k
        // GIR_Coverage, 17369,
1107
2.27k
        GIR_Done,
1108
2.27k
      // Label 81: @696
1109
2.27k
      GIM_Try, /*On fail goto*//*Label 82*/ 720, // Rule ID 17373 //
1110
2.27k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1111
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1112
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })  =>  (DEC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1113
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r,
1114
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1115
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1116
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1117
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1118
2.27k
        // GIR_Coverage, 17373,
1119
2.27k
        GIR_Done,
1120
2.27k
      // Label 82: @720
1121
2.27k
      GIM_Try, /*On fail goto*//*Label 83*/ 753, // Rule ID 17326 //
1122
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1123
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1124
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1125
2.27k
        // MIs[1] Operand 1
1126
2.27k
        // No operand predicates
1127
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1128
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (ADD64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1129
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8,
1130
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1131
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1132
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1133
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1134
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1135
2.27k
        // GIR_Coverage, 17326,
1136
2.27k
        GIR_Done,
1137
2.27k
      // Label 83: @753
1138
2.27k
      GIM_Try, /*On fail goto*//*Label 84*/ 786, // Rule ID 17327 //
1139
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1140
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1141
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1142
2.27k
        // MIs[1] Operand 1
1143
2.27k
        // No operand predicates
1144
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1145
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (ADD64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1146
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32,
1147
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1148
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1149
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1150
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1151
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1152
2.27k
        // GIR_Coverage, 17327,
1153
2.27k
        GIR_Done,
1154
2.27k
      // Label 84: @786
1155
2.27k
      GIM_Try, /*On fail goto*//*Label 85*/ 802, // Rule ID 17316 //
1156
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1157
2.27k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1158
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr,
1159
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1160
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1161
2.27k
        // GIR_Coverage, 17316,
1162
2.27k
        GIR_Done,
1163
2.27k
      // Label 85: @802
1164
2.27k
      GIM_Reject,
1165
2.27k
    // Label 78: @803
1166
2.27k
    GIM_Reject,
1167
2.27k
    // Label 46: @804
1168
2.27k
    GIM_Try, /*On fail goto*//*Label 86*/ 884,
1169
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1170
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1171
2.27k
      GIM_Try, /*On fail goto*//*Label 87*/ 837, // Rule ID 1811 //
1172
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1173
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1174
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1175
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1176
2.27k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1177
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQrr,
1178
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1179
2.27k
        // GIR_Coverage, 1811,
1180
2.27k
        GIR_Done,
1181
2.27k
      // Label 87: @837
1182
2.27k
      GIM_Try, /*On fail goto*//*Label 88*/ 860, // Rule ID 1813 //
1183
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1184
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1185
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1186
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1187
2.27k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1188
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDQrr,
1189
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1190
2.27k
        // GIR_Coverage, 1813,
1191
2.27k
        GIR_Done,
1192
2.27k
      // Label 88: @860
1193
2.27k
      GIM_Try, /*On fail goto*//*Label 89*/ 883, // Rule ID 3825 //
1194
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1195
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1196
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1197
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1198
2.27k
        // (add:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPADDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1199
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ128rr,
1200
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1201
2.27k
        // GIR_Coverage, 3825,
1202
2.27k
        GIR_Done,
1203
2.27k
      // Label 89: @883
1204
2.27k
      GIM_Reject,
1205
2.27k
    // Label 86: @884
1206
2.27k
    GIM_Reject,
1207
2.27k
    // Label 47: @885
1208
2.27k
    GIM_Try, /*On fail goto*//*Label 90*/ 1087,
1209
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1210
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1211
2.27k
      GIM_Try, /*On fail goto*//*Label 91*/ 956, // Rule ID 12182 //
1212
2.27k
        GIM_CheckFeatures, GIFBS_HasXOP,
1213
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1214
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1215
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1216
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1217
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1218
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1219
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1220
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1221
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1222
2.27k
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3)  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1223
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1224
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1225
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1226
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1227
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1228
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1229
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1230
2.27k
        // GIR_Coverage, 12182,
1231
2.27k
        GIR_Done,
1232
2.27k
      // Label 91: @956
1233
2.27k
      GIM_Try, /*On fail goto*//*Label 92*/ 1017, // Rule ID 19456 //
1234
2.27k
        GIM_CheckFeatures, GIFBS_HasXOP,
1235
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1236
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1237
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1238
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1239
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1240
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1241
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1242
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1243
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1244
2.27k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2))  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1245
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1246
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1247
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1248
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1249
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1250
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1251
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1252
2.27k
        // GIR_Coverage, 19456,
1253
2.27k
        GIR_Done,
1254
2.27k
      // Label 92: @1017
1255
2.27k
      GIM_Try, /*On fail goto*//*Label 93*/ 1040, // Rule ID 1805 //
1256
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1257
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1258
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1259
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1260
2.27k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1261
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDrr,
1262
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1263
2.27k
        // GIR_Coverage, 1805,
1264
2.27k
        GIR_Done,
1265
2.27k
      // Label 93: @1040
1266
2.27k
      GIM_Try, /*On fail goto*//*Label 94*/ 1063, // Rule ID 1807 //
1267
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1268
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1269
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1270
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1271
2.27k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1272
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDDrr,
1273
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1274
2.27k
        // GIR_Coverage, 1807,
1275
2.27k
        GIR_Done,
1276
2.27k
      // Label 94: @1063
1277
2.27k
      GIM_Try, /*On fail goto*//*Label 95*/ 1086, // Rule ID 3852 //
1278
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1279
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1280
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1281
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1282
2.27k
        // (add:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPADDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1283
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ128rr,
1284
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1285
2.27k
        // GIR_Coverage, 3852,
1286
2.27k
        GIR_Done,
1287
2.27k
      // Label 95: @1086
1288
2.27k
      GIM_Reject,
1289
2.27k
    // Label 90: @1087
1290
2.27k
    GIM_Reject,
1291
2.27k
    // Label 48: @1088
1292
2.27k
    GIM_Try, /*On fail goto*//*Label 96*/ 1145,
1293
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1294
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1295
2.27k
      GIM_Try, /*On fail goto*//*Label 97*/ 1121, // Rule ID 1815 //
1296
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1297
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1298
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1299
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1300
2.27k
        // (add:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPADDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1301
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQYrr,
1302
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1303
2.27k
        // GIR_Coverage, 1815,
1304
2.27k
        GIR_Done,
1305
2.27k
      // Label 97: @1121
1306
2.27k
      GIM_Try, /*On fail goto*//*Label 98*/ 1144, // Rule ID 3816 //
1307
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1308
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1309
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1310
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1311
2.27k
        // (add:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPADDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1312
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ256rr,
1313
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1314
2.27k
        // GIR_Coverage, 3816,
1315
2.27k
        GIR_Done,
1316
2.27k
      // Label 98: @1144
1317
2.27k
      GIM_Reject,
1318
2.27k
    // Label 96: @1145
1319
2.27k
    GIM_Reject,
1320
2.27k
    // Label 49: @1146
1321
2.27k
    GIM_Try, /*On fail goto*//*Label 99*/ 1348,
1322
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1323
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1324
2.27k
      GIM_Try, /*On fail goto*//*Label 100*/ 1217, // Rule ID 12181 //
1325
2.27k
        GIM_CheckFeatures, GIFBS_HasXOP,
1326
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1327
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1328
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1329
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1330
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1331
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1332
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1333
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1334
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1335
2.27k
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3)  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1336
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1337
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1338
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1339
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1340
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1341
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1342
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1343
2.27k
        // GIR_Coverage, 12181,
1344
2.27k
        GIR_Done,
1345
2.27k
      // Label 100: @1217
1346
2.27k
      GIM_Try, /*On fail goto*//*Label 101*/ 1278, // Rule ID 19455 //
1347
2.27k
        GIM_CheckFeatures, GIFBS_HasXOP,
1348
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1349
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1350
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1351
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1352
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1353
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1354
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1355
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1356
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1357
2.27k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2))  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1358
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1359
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1360
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1361
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1362
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1363
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1364
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1365
2.27k
        // GIR_Coverage, 19455,
1366
2.27k
        GIR_Done,
1367
2.27k
      // Label 101: @1278
1368
2.27k
      GIM_Try, /*On fail goto*//*Label 102*/ 1301, // Rule ID 1799 //
1369
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1370
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1371
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1372
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1373
2.27k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1374
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWrr,
1375
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1376
2.27k
        // GIR_Coverage, 1799,
1377
2.27k
        GIR_Done,
1378
2.27k
      // Label 102: @1301
1379
2.27k
      GIM_Try, /*On fail goto*//*Label 103*/ 1324, // Rule ID 1801 //
1380
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1381
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1382
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1383
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1384
2.27k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1385
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDWrr,
1386
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1387
2.27k
        // GIR_Coverage, 1801,
1388
2.27k
        GIR_Done,
1389
2.27k
      // Label 103: @1324
1390
2.27k
      GIM_Try, /*On fail goto*//*Label 104*/ 1347, // Rule ID 3873 //
1391
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1392
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1393
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1394
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1395
2.27k
        // (add:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPADDWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1396
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ128rr,
1397
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1398
2.27k
        // GIR_Coverage, 3873,
1399
2.27k
        GIR_Done,
1400
2.27k
      // Label 104: @1347
1401
2.27k
      GIM_Reject,
1402
2.27k
    // Label 99: @1348
1403
2.27k
    GIM_Reject,
1404
2.27k
    // Label 50: @1349
1405
2.27k
    GIM_Try, /*On fail goto*//*Label 105*/ 1406,
1406
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1407
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1408
2.27k
      GIM_Try, /*On fail goto*//*Label 106*/ 1382, // Rule ID 1809 //
1409
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1410
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1411
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1412
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1413
2.27k
        // (add:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPADDDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1414
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDYrr,
1415
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1416
2.27k
        // GIR_Coverage, 1809,
1417
2.27k
        GIR_Done,
1418
2.27k
      // Label 106: @1382
1419
2.27k
      GIM_Try, /*On fail goto*//*Label 107*/ 1405, // Rule ID 3843 //
1420
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1421
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1422
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1423
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1424
2.27k
        // (add:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPADDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1425
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ256rr,
1426
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1427
2.27k
        // GIR_Coverage, 3843,
1428
2.27k
        GIR_Done,
1429
2.27k
      // Label 107: @1405
1430
2.27k
      GIM_Reject,
1431
2.27k
    // Label 105: @1406
1432
2.27k
    GIM_Reject,
1433
2.27k
    // Label 51: @1407
1434
2.27k
    GIM_Try, /*On fail goto*//*Label 108*/ 1438, // Rule ID 3807 //
1435
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1436
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
1437
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
1438
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1439
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1440
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1441
2.27k
      // (add:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPADDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
1442
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZrr,
1443
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1444
2.27k
      // GIR_Coverage, 3807,
1445
2.27k
      GIR_Done,
1446
2.27k
    // Label 108: @1438
1447
2.27k
    GIM_Reject,
1448
2.27k
    // Label 52: @1439
1449
2.27k
    GIM_Try, /*On fail goto*//*Label 109*/ 1519,
1450
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1451
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1452
2.27k
      GIM_Try, /*On fail goto*//*Label 110*/ 1472, // Rule ID 1793 //
1453
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1454
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1455
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1456
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1457
2.27k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1458
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBrr,
1459
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1460
2.27k
        // GIR_Coverage, 1793,
1461
2.27k
        GIR_Done,
1462
2.27k
      // Label 110: @1472
1463
2.27k
      GIM_Try, /*On fail goto*//*Label 111*/ 1495, // Rule ID 1795 //
1464
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1465
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1466
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1467
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1468
2.27k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1469
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDBrr,
1470
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1471
2.27k
        // GIR_Coverage, 1795,
1472
2.27k
        GIR_Done,
1473
2.27k
      // Label 111: @1495
1474
2.27k
      GIM_Try, /*On fail goto*//*Label 112*/ 1518, // Rule ID 3891 //
1475
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1476
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1477
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1478
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1479
2.27k
        // (add:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPADDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
1480
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ128rr,
1481
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482
2.27k
        // GIR_Coverage, 3891,
1483
2.27k
        GIR_Done,
1484
2.27k
      // Label 112: @1518
1485
2.27k
      GIM_Reject,
1486
2.27k
    // Label 109: @1519
1487
2.27k
    GIM_Reject,
1488
2.27k
    // Label 53: @1520
1489
2.27k
    GIM_Try, /*On fail goto*//*Label 113*/ 1577,
1490
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
1491
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
1492
2.27k
      GIM_Try, /*On fail goto*//*Label 114*/ 1553, // Rule ID 1803 //
1493
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1494
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1495
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1496
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1497
2.27k
        // (add:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPADDWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
1498
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWYrr,
1499
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1500
2.27k
        // GIR_Coverage, 1803,
1501
2.27k
        GIR_Done,
1502
2.27k
      // Label 114: @1553
1503
2.27k
      GIM_Try, /*On fail goto*//*Label 115*/ 1576, // Rule ID 3867 //
1504
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1505
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1506
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1507
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1508
2.27k
        // (add:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPADDWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
1509
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ256rr,
1510
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1511
2.27k
        // GIR_Coverage, 3867,
1512
2.27k
        GIR_Done,
1513
2.27k
      // Label 115: @1576
1514
2.27k
      GIM_Reject,
1515
2.27k
    // Label 113: @1577
1516
2.27k
    GIM_Reject,
1517
2.27k
    // Label 54: @1578
1518
2.27k
    GIM_Try, /*On fail goto*//*Label 116*/ 1609, // Rule ID 3834 //
1519
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1520
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
1521
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
1522
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1523
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1524
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1525
2.27k
      // (add:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPADDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
1526
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZrr,
1527
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528
2.27k
      // GIR_Coverage, 3834,
1529
2.27k
      GIR_Done,
1530
2.27k
    // Label 116: @1609
1531
2.27k
    GIM_Reject,
1532
2.27k
    // Label 55: @1610
1533
2.27k
    GIM_Try, /*On fail goto*//*Label 117*/ 1667,
1534
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
1535
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
1536
2.27k
      GIM_Try, /*On fail goto*//*Label 118*/ 1643, // Rule ID 1797 //
1537
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1538
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1539
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1540
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1541
2.27k
        // (add:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPADDBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
1542
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBYrr,
1543
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1544
2.27k
        // GIR_Coverage, 1797,
1545
2.27k
        GIR_Done,
1546
2.27k
      // Label 118: @1643
1547
2.27k
      GIM_Try, /*On fail goto*//*Label 119*/ 1666, // Rule ID 3885 //
1548
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1549
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1550
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1551
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1552
2.27k
        // (add:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPADDBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
1553
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ256rr,
1554
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1555
2.27k
        // GIR_Coverage, 3885,
1556
2.27k
        GIR_Done,
1557
2.27k
      // Label 119: @1666
1558
2.27k
      GIM_Reject,
1559
2.27k
    // Label 117: @1667
1560
2.27k
    GIM_Reject,
1561
2.27k
    // Label 56: @1668
1562
2.27k
    GIM_Try, /*On fail goto*//*Label 120*/ 1699, // Rule ID 3861 //
1563
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
1564
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
1565
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
1566
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1567
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1568
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1569
2.27k
      // (add:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPADDWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
1570
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZrr,
1571
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1572
2.27k
      // GIR_Coverage, 3861,
1573
2.27k
      GIR_Done,
1574
2.27k
    // Label 120: @1699
1575
2.27k
    GIM_Reject,
1576
2.27k
    // Label 57: @1700
1577
2.27k
    GIM_Try, /*On fail goto*//*Label 121*/ 1731, // Rule ID 3879 //
1578
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
1579
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
1580
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
1581
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1582
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1583
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1584
2.27k
      // (add:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPADDBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
1585
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZrr,
1586
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1587
2.27k
      // GIR_Coverage, 3879,
1588
2.27k
      GIR_Done,
1589
2.27k
    // Label 121: @1731
1590
2.27k
    GIM_Reject,
1591
2.27k
    // Label 58: @1732
1592
2.27k
    GIM_Reject,
1593
2.27k
    // Label 1: @1733
1594
2.27k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 138*/ 2813,
1595
2.27k
    /*GILLT_s8*//*Label 122*/ 1763,
1596
2.27k
    /*GILLT_s16*//*Label 123*/ 1829,
1597
2.27k
    /*GILLT_s32*//*Label 124*/ 1928,
1598
2.27k
    /*GILLT_s64*//*Label 125*/ 2027, 0, 0, 0,
1599
2.27k
    /*GILLT_v2s64*//*Label 126*/ 2129, 0,
1600
2.27k
    /*GILLT_v4s32*//*Label 127*/ 2210,
1601
2.27k
    /*GILLT_v4s64*//*Label 128*/ 2291, 0,
1602
2.27k
    /*GILLT_v8s16*//*Label 129*/ 2349,
1603
2.27k
    /*GILLT_v8s32*//*Label 130*/ 2430,
1604
2.27k
    /*GILLT_v8s64*//*Label 131*/ 2488, 0,
1605
2.27k
    /*GILLT_v16s8*//*Label 132*/ 2520,
1606
2.27k
    /*GILLT_v16s16*//*Label 133*/ 2601,
1607
2.27k
    /*GILLT_v16s32*//*Label 134*/ 2659, 0,
1608
2.27k
    /*GILLT_v32s8*//*Label 135*/ 2691,
1609
2.27k
    /*GILLT_v32s16*//*Label 136*/ 2749, 0,
1610
2.27k
    /*GILLT_v64s8*//*Label 137*/ 2781,
1611
2.27k
    // Label 122: @1763
1612
2.27k
    GIM_Try, /*On fail goto*//*Label 139*/ 1828,
1613
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
1614
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
1615
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
1616
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
1617
2.27k
      GIM_Try, /*On fail goto*//*Label 140*/ 1811, // Rule ID 17336 //
1618
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1619
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1620
2.27k
        // MIs[1] Operand 1
1621
2.27k
        // No operand predicates
1622
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1623
2.27k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (SUB8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
1624
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri,
1625
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1626
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1627
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1628
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1629
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1630
2.27k
        // GIR_Coverage, 17336,
1631
2.27k
        GIR_Done,
1632
2.27k
      // Label 140: @1811
1633
2.27k
      GIM_Try, /*On fail goto*//*Label 141*/ 1827, // Rule ID 17328 //
1634
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
1635
2.27k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (SUB8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
1636
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB8rr,
1637
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1638
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639
2.27k
        // GIR_Coverage, 17328,
1640
2.27k
        GIR_Done,
1641
2.27k
      // Label 141: @1827
1642
2.27k
      GIM_Reject,
1643
2.27k
    // Label 139: @1828
1644
2.27k
    GIM_Reject,
1645
2.27k
    // Label 123: @1829
1646
2.27k
    GIM_Try, /*On fail goto*//*Label 142*/ 1927,
1647
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1648
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
1649
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
1650
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
1651
2.27k
      GIM_Try, /*On fail goto*//*Label 143*/ 1880, // Rule ID 17339 //
1652
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1653
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1654
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
1655
2.27k
        // MIs[1] Operand 1
1656
2.27k
        // No operand predicates
1657
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1658
2.27k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
1659
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
1660
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1661
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1662
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1663
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1664
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1665
2.27k
        // GIR_Coverage, 17339,
1666
2.27k
        GIR_Done,
1667
2.27k
      // Label 143: @1880
1668
2.27k
      GIM_Try, /*On fail goto*//*Label 144*/ 1910, // Rule ID 17337 //
1669
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1670
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1671
2.27k
        // MIs[1] Operand 1
1672
2.27k
        // No operand predicates
1673
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1674
2.27k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (SUB16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
1675
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri,
1676
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1677
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1678
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1679
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1680
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1681
2.27k
        // GIR_Coverage, 17337,
1682
2.27k
        GIR_Done,
1683
2.27k
      // Label 144: @1910
1684
2.27k
      GIM_Try, /*On fail goto*//*Label 145*/ 1926, // Rule ID 17329 //
1685
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
1686
2.27k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (SUB16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
1687
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB16rr,
1688
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1689
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1690
2.27k
        // GIR_Coverage, 17329,
1691
2.27k
        GIR_Done,
1692
2.27k
      // Label 145: @1926
1693
2.27k
      GIM_Reject,
1694
2.27k
    // Label 142: @1927
1695
2.27k
    GIM_Reject,
1696
2.27k
    // Label 124: @1928
1697
2.27k
    GIM_Try, /*On fail goto*//*Label 146*/ 2026,
1698
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1699
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1700
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
1701
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
1702
2.27k
      GIM_Try, /*On fail goto*//*Label 147*/ 1979, // Rule ID 17340 //
1703
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1704
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1705
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1706
2.27k
        // MIs[1] Operand 1
1707
2.27k
        // No operand predicates
1708
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1709
2.27k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1710
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1711
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1712
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1713
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1714
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1715
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1716
2.27k
        // GIR_Coverage, 17340,
1717
2.27k
        GIR_Done,
1718
2.27k
      // Label 147: @1979
1719
2.27k
      GIM_Try, /*On fail goto*//*Label 148*/ 2009, // Rule ID 17338 //
1720
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1721
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1722
2.27k
        // MIs[1] Operand 1
1723
2.27k
        // No operand predicates
1724
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1725
2.27k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (SUB32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1726
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri,
1727
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1728
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1729
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1730
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1731
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1732
2.27k
        // GIR_Coverage, 17338,
1733
2.27k
        GIR_Done,
1734
2.27k
      // Label 148: @2009
1735
2.27k
      GIM_Try, /*On fail goto*//*Label 149*/ 2025, // Rule ID 17330 //
1736
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1737
2.27k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (SUB32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1738
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB32rr,
1739
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1740
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1741
2.27k
        // GIR_Coverage, 17330,
1742
2.27k
        GIR_Done,
1743
2.27k
      // Label 149: @2025
1744
2.27k
      GIM_Reject,
1745
2.27k
    // Label 146: @2026
1746
2.27k
    GIM_Reject,
1747
2.27k
    // Label 125: @2027
1748
2.27k
    GIM_Try, /*On fail goto*//*Label 150*/ 2128,
1749
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1750
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1751
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1752
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1753
2.27k
      GIM_Try, /*On fail goto*//*Label 151*/ 2078, // Rule ID 17341 //
1754
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1755
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1756
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1757
2.27k
        // MIs[1] Operand 1
1758
2.27k
        // No operand predicates
1759
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1760
2.27k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1761
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1762
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1763
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1764
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1765
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1766
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1767
2.27k
        // GIR_Coverage, 17341,
1768
2.27k
        GIR_Done,
1769
2.27k
      // Label 151: @2078
1770
2.27k
      GIM_Try, /*On fail goto*//*Label 152*/ 2111, // Rule ID 17342 //
1771
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1772
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1773
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1774
2.27k
        // MIs[1] Operand 1
1775
2.27k
        // No operand predicates
1776
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1777
2.27k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1778
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1779
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1780
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1781
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1782
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
1783
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1784
2.27k
        // GIR_Coverage, 17342,
1785
2.27k
        GIR_Done,
1786
2.27k
      // Label 152: @2111
1787
2.27k
      GIM_Try, /*On fail goto*//*Label 153*/ 2127, // Rule ID 17331 //
1788
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1789
2.27k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (SUB64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1790
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB64rr,
1791
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1792
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1793
2.27k
        // GIR_Coverage, 17331,
1794
2.27k
        GIR_Done,
1795
2.27k
      // Label 153: @2127
1796
2.27k
      GIM_Reject,
1797
2.27k
    // Label 150: @2128
1798
2.27k
    GIM_Reject,
1799
2.27k
    // Label 126: @2129
1800
2.27k
    GIM_Try, /*On fail goto*//*Label 154*/ 2209,
1801
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1802
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1803
2.27k
      GIM_Try, /*On fail goto*//*Label 155*/ 2162, // Rule ID 1877 //
1804
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1805
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1806
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1807
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1808
2.27k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1809
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQrr,
1810
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1811
2.27k
        // GIR_Coverage, 1877,
1812
2.27k
        GIR_Done,
1813
2.27k
      // Label 155: @2162
1814
2.27k
      GIM_Try, /*On fail goto*//*Label 156*/ 2185, // Rule ID 1879 //
1815
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1816
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1817
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1818
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1819
2.27k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1820
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBQrr,
1821
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1822
2.27k
        // GIR_Coverage, 1879,
1823
2.27k
        GIR_Done,
1824
2.27k
      // Label 156: @2185
1825
2.27k
      GIM_Try, /*On fail goto*//*Label 157*/ 2208, // Rule ID 3915 //
1826
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1827
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1828
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1829
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1830
2.27k
        // (sub:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPSUBQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1831
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ128rr,
1832
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1833
2.27k
        // GIR_Coverage, 3915,
1834
2.27k
        GIR_Done,
1835
2.27k
      // Label 157: @2208
1836
2.27k
      GIM_Reject,
1837
2.27k
    // Label 154: @2209
1838
2.27k
    GIM_Reject,
1839
2.27k
    // Label 127: @2210
1840
2.27k
    GIM_Try, /*On fail goto*//*Label 158*/ 2290,
1841
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1842
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1843
2.27k
      GIM_Try, /*On fail goto*//*Label 159*/ 2243, // Rule ID 1871 //
1844
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1845
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1846
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1847
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1848
2.27k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1849
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDrr,
1850
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1851
2.27k
        // GIR_Coverage, 1871,
1852
2.27k
        GIR_Done,
1853
2.27k
      // Label 159: @2243
1854
2.27k
      GIM_Try, /*On fail goto*//*Label 160*/ 2266, // Rule ID 1873 //
1855
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1856
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1857
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1858
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1859
2.27k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1860
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBDrr,
1861
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1862
2.27k
        // GIR_Coverage, 1873,
1863
2.27k
        GIR_Done,
1864
2.27k
      // Label 160: @2266
1865
2.27k
      GIM_Try, /*On fail goto*//*Label 161*/ 2289, // Rule ID 3942 //
1866
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1867
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1868
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1869
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1870
2.27k
        // (sub:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPSUBDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1871
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ128rr,
1872
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1873
2.27k
        // GIR_Coverage, 3942,
1874
2.27k
        GIR_Done,
1875
2.27k
      // Label 161: @2289
1876
2.27k
      GIM_Reject,
1877
2.27k
    // Label 158: @2290
1878
2.27k
    GIM_Reject,
1879
2.27k
    // Label 128: @2291
1880
2.27k
    GIM_Try, /*On fail goto*//*Label 162*/ 2348,
1881
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1882
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1883
2.27k
      GIM_Try, /*On fail goto*//*Label 163*/ 2324, // Rule ID 1881 //
1884
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1885
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1886
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1887
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1888
2.27k
        // (sub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPSUBQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1889
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQYrr,
1890
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891
2.27k
        // GIR_Coverage, 1881,
1892
2.27k
        GIR_Done,
1893
2.27k
      // Label 163: @2324
1894
2.27k
      GIM_Try, /*On fail goto*//*Label 164*/ 2347, // Rule ID 3906 //
1895
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1896
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1897
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1898
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1899
2.27k
        // (sub:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPSUBQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1900
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ256rr,
1901
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1902
2.27k
        // GIR_Coverage, 3906,
1903
2.27k
        GIR_Done,
1904
2.27k
      // Label 164: @2347
1905
2.27k
      GIM_Reject,
1906
2.27k
    // Label 162: @2348
1907
2.27k
    GIM_Reject,
1908
2.27k
    // Label 129: @2349
1909
2.27k
    GIM_Try, /*On fail goto*//*Label 165*/ 2429,
1910
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1911
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1912
2.27k
      GIM_Try, /*On fail goto*//*Label 166*/ 2382, // Rule ID 1865 //
1913
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1914
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1915
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1916
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1917
2.27k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1918
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWrr,
1919
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1920
2.27k
        // GIR_Coverage, 1865,
1921
2.27k
        GIR_Done,
1922
2.27k
      // Label 166: @2382
1923
2.27k
      GIM_Try, /*On fail goto*//*Label 167*/ 2405, // Rule ID 1867 //
1924
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1925
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1926
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1927
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1928
2.27k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1929
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBWrr,
1930
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1931
2.27k
        // GIR_Coverage, 1867,
1932
2.27k
        GIR_Done,
1933
2.27k
      // Label 167: @2405
1934
2.27k
      GIM_Try, /*On fail goto*//*Label 168*/ 2428, // Rule ID 3963 //
1935
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1936
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1937
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1938
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1939
2.27k
        // (sub:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPSUBWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1940
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ128rr,
1941
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942
2.27k
        // GIR_Coverage, 3963,
1943
2.27k
        GIR_Done,
1944
2.27k
      // Label 168: @2428
1945
2.27k
      GIM_Reject,
1946
2.27k
    // Label 165: @2429
1947
2.27k
    GIM_Reject,
1948
2.27k
    // Label 130: @2430
1949
2.27k
    GIM_Try, /*On fail goto*//*Label 169*/ 2487,
1950
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1951
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1952
2.27k
      GIM_Try, /*On fail goto*//*Label 170*/ 2463, // Rule ID 1875 //
1953
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1954
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1955
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1956
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1957
2.27k
        // (sub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPSUBDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1958
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDYrr,
1959
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1960
2.27k
        // GIR_Coverage, 1875,
1961
2.27k
        GIR_Done,
1962
2.27k
      // Label 170: @2463
1963
2.27k
      GIM_Try, /*On fail goto*//*Label 171*/ 2486, // Rule ID 3933 //
1964
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1965
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1966
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1967
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1968
2.27k
        // (sub:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPSUBDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1969
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ256rr,
1970
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1971
2.27k
        // GIR_Coverage, 3933,
1972
2.27k
        GIR_Done,
1973
2.27k
      // Label 171: @2486
1974
2.27k
      GIM_Reject,
1975
2.27k
    // Label 169: @2487
1976
2.27k
    GIM_Reject,
1977
2.27k
    // Label 131: @2488
1978
2.27k
    GIM_Try, /*On fail goto*//*Label 172*/ 2519, // Rule ID 3897 //
1979
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1980
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
1981
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
1982
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1983
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1984
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1985
2.27k
      // (sub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPSUBQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
1986
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZrr,
1987
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1988
2.27k
      // GIR_Coverage, 3897,
1989
2.27k
      GIR_Done,
1990
2.27k
    // Label 172: @2519
1991
2.27k
    GIM_Reject,
1992
2.27k
    // Label 132: @2520
1993
2.27k
    GIM_Try, /*On fail goto*//*Label 173*/ 2600,
1994
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1995
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1996
2.27k
      GIM_Try, /*On fail goto*//*Label 174*/ 2553, // Rule ID 1859 //
1997
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1998
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1999
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2000
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2001
2.27k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2002
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBrr,
2003
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2004
2.27k
        // GIR_Coverage, 1859,
2005
2.27k
        GIR_Done,
2006
2.27k
      // Label 174: @2553
2007
2.27k
      GIM_Try, /*On fail goto*//*Label 175*/ 2576, // Rule ID 1861 //
2008
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2009
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2010
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2011
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2012
2.27k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2013
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBBrr,
2014
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2015
2.27k
        // GIR_Coverage, 1861,
2016
2.27k
        GIR_Done,
2017
2.27k
      // Label 175: @2576
2018
2.27k
      GIM_Try, /*On fail goto*//*Label 176*/ 2599, // Rule ID 3981 //
2019
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2020
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2021
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2022
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2023
2.27k
        // (sub:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPSUBBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
2024
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ128rr,
2025
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2026
2.27k
        // GIR_Coverage, 3981,
2027
2.27k
        GIR_Done,
2028
2.27k
      // Label 176: @2599
2029
2.27k
      GIM_Reject,
2030
2.27k
    // Label 173: @2600
2031
2.27k
    GIM_Reject,
2032
2.27k
    // Label 133: @2601
2033
2.27k
    GIM_Try, /*On fail goto*//*Label 177*/ 2658,
2034
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2035
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2036
2.27k
      GIM_Try, /*On fail goto*//*Label 178*/ 2634, // Rule ID 1869 //
2037
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2038
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2039
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2040
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2041
2.27k
        // (sub:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPSUBWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2042
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWYrr,
2043
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2044
2.27k
        // GIR_Coverage, 1869,
2045
2.27k
        GIR_Done,
2046
2.27k
      // Label 178: @2634
2047
2.27k
      GIM_Try, /*On fail goto*//*Label 179*/ 2657, // Rule ID 3957 //
2048
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2049
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2050
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2051
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2052
2.27k
        // (sub:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPSUBWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2053
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ256rr,
2054
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2055
2.27k
        // GIR_Coverage, 3957,
2056
2.27k
        GIR_Done,
2057
2.27k
      // Label 179: @2657
2058
2.27k
      GIM_Reject,
2059
2.27k
    // Label 177: @2658
2060
2.27k
    GIM_Reject,
2061
2.27k
    // Label 134: @2659
2062
2.27k
    GIM_Try, /*On fail goto*//*Label 180*/ 2690, // Rule ID 3924 //
2063
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2064
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2065
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2066
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2067
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2068
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2069
2.27k
      // (sub:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPSUBDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2070
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZrr,
2071
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2072
2.27k
      // GIR_Coverage, 3924,
2073
2.27k
      GIR_Done,
2074
2.27k
    // Label 180: @2690
2075
2.27k
    GIM_Reject,
2076
2.27k
    // Label 135: @2691
2077
2.27k
    GIM_Try, /*On fail goto*//*Label 181*/ 2748,
2078
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
2079
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
2080
2.27k
      GIM_Try, /*On fail goto*//*Label 182*/ 2724, // Rule ID 1863 //
2081
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2082
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2083
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2084
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2085
2.27k
        // (sub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPSUBBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
2086
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBYrr,
2087
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2088
2.27k
        // GIR_Coverage, 1863,
2089
2.27k
        GIR_Done,
2090
2.27k
      // Label 182: @2724
2091
2.27k
      GIM_Try, /*On fail goto*//*Label 183*/ 2747, // Rule ID 3975 //
2092
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2093
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2094
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2095
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2096
2.27k
        // (sub:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPSUBBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
2097
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ256rr,
2098
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2099
2.27k
        // GIR_Coverage, 3975,
2100
2.27k
        GIR_Done,
2101
2.27k
      // Label 183: @2747
2102
2.27k
      GIM_Reject,
2103
2.27k
    // Label 181: @2748
2104
2.27k
    GIM_Reject,
2105
2.27k
    // Label 136: @2749
2106
2.27k
    GIM_Try, /*On fail goto*//*Label 184*/ 2780, // Rule ID 3951 //
2107
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
2108
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2109
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2110
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2111
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2112
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2113
2.27k
      // (sub:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPSUBWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2114
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZrr,
2115
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2116
2.27k
      // GIR_Coverage, 3951,
2117
2.27k
      GIR_Done,
2118
2.27k
    // Label 184: @2780
2119
2.27k
    GIM_Reject,
2120
2.27k
    // Label 137: @2781
2121
2.27k
    GIM_Try, /*On fail goto*//*Label 185*/ 2812, // Rule ID 3969 //
2122
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
2123
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
2124
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
2125
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2126
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2127
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2128
2.27k
      // (sub:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPSUBBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
2129
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZrr,
2130
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2131
2.27k
      // GIR_Coverage, 3969,
2132
2.27k
      GIR_Done,
2133
2.27k
    // Label 185: @2812
2134
2.27k
    GIM_Reject,
2135
2.27k
    // Label 138: @2813
2136
2.27k
    GIM_Reject,
2137
2.27k
    // Label 2: @2814
2138
2.27k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 198*/ 3579,
2139
2.27k
    /*GILLT_s16*//*Label 186*/ 2841,
2140
2.27k
    /*GILLT_s32*//*Label 187*/ 2940,
2141
2.27k
    /*GILLT_s64*//*Label 188*/ 3039, 0, 0, 0,
2142
2.27k
    /*GILLT_v2s64*//*Label 189*/ 3141, 0,
2143
2.27k
    /*GILLT_v4s32*//*Label 190*/ 3173,
2144
2.27k
    /*GILLT_v4s64*//*Label 191*/ 3254, 0,
2145
2.27k
    /*GILLT_v8s16*//*Label 192*/ 3286,
2146
2.27k
    /*GILLT_v8s32*//*Label 193*/ 3367,
2147
2.27k
    /*GILLT_v8s64*//*Label 194*/ 3425, 0, 0,
2148
2.27k
    /*GILLT_v16s16*//*Label 195*/ 3457,
2149
2.27k
    /*GILLT_v16s32*//*Label 196*/ 3515, 0, 0,
2150
2.27k
    /*GILLT_v32s16*//*Label 197*/ 3547,
2151
2.27k
    // Label 186: @2841
2152
2.27k
    GIM_Try, /*On fail goto*//*Label 199*/ 2939,
2153
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2154
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2155
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2156
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2157
2.27k
      GIM_Try, /*On fail goto*//*Label 200*/ 2892, // Rule ID 17356 //
2158
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2159
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2160
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2161
2.27k
        // MIs[1] Operand 1
2162
2.27k
        // No operand predicates
2163
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2164
2.27k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (IMUL16rri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2165
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8,
2166
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2167
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2168
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2169
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2170
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2171
2.27k
        // GIR_Coverage, 17356,
2172
2.27k
        GIR_Done,
2173
2.27k
      // Label 200: @2892
2174
2.27k
      GIM_Try, /*On fail goto*//*Label 201*/ 2922, // Rule ID 17354 //
2175
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2176
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2177
2.27k
        // MIs[1] Operand 1
2178
2.27k
        // No operand predicates
2179
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2180
2.27k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (IMUL16rri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2181
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri,
2182
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2183
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2184
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2185
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2186
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2187
2.27k
        // GIR_Coverage, 17354,
2188
2.27k
        GIR_Done,
2189
2.27k
      // Label 201: @2922
2190
2.27k
      GIM_Try, /*On fail goto*//*Label 202*/ 2938, // Rule ID 17348 //
2191
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2192
2.27k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (IMUL16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2193
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL16rr,
2194
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2195
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2196
2.27k
        // GIR_Coverage, 17348,
2197
2.27k
        GIR_Done,
2198
2.27k
      // Label 202: @2938
2199
2.27k
      GIM_Reject,
2200
2.27k
    // Label 199: @2939
2201
2.27k
    GIM_Reject,
2202
2.27k
    // Label 187: @2940
2203
2.27k
    GIM_Try, /*On fail goto*//*Label 203*/ 3038,
2204
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2205
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2206
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2207
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2208
2.27k
      GIM_Try, /*On fail goto*//*Label 204*/ 2991, // Rule ID 17357 //
2209
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2210
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2211
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
2212
2.27k
        // MIs[1] Operand 1
2213
2.27k
        // No operand predicates
2214
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2215
2.27k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (IMUL32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
2216
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8,
2217
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2218
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2219
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2220
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2221
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2222
2.27k
        // GIR_Coverage, 17357,
2223
2.27k
        GIR_Done,
2224
2.27k
      // Label 204: @2991
2225
2.27k
      GIM_Try, /*On fail goto*//*Label 205*/ 3021, // Rule ID 17355 //
2226
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2227
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2228
2.27k
        // MIs[1] Operand 1
2229
2.27k
        // No operand predicates
2230
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2231
2.27k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (IMUL32rri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
2232
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri,
2233
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2234
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2235
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2236
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2237
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2238
2.27k
        // GIR_Coverage, 17355,
2239
2.27k
        GIR_Done,
2240
2.27k
      // Label 205: @3021
2241
2.27k
      GIM_Try, /*On fail goto*//*Label 206*/ 3037, // Rule ID 17349 //
2242
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
2243
2.27k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (IMUL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
2244
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL32rr,
2245
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2246
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2247
2.27k
        // GIR_Coverage, 17349,
2248
2.27k
        GIR_Done,
2249
2.27k
      // Label 206: @3037
2250
2.27k
      GIM_Reject,
2251
2.27k
    // Label 203: @3038
2252
2.27k
    GIM_Reject,
2253
2.27k
    // Label 188: @3039
2254
2.27k
    GIM_Try, /*On fail goto*//*Label 207*/ 3140,
2255
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2256
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2257
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
2258
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
2259
2.27k
      GIM_Try, /*On fail goto*//*Label 208*/ 3090, // Rule ID 17358 //
2260
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2261
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2262
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
2263
2.27k
        // MIs[1] Operand 1
2264
2.27k
        // No operand predicates
2265
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2266
2.27k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (IMUL64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
2267
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8,
2268
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2269
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2270
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2271
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2272
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2273
2.27k
        // GIR_Coverage, 17358,
2274
2.27k
        GIR_Done,
2275
2.27k
      // Label 208: @3090
2276
2.27k
      GIM_Try, /*On fail goto*//*Label 209*/ 3123, // Rule ID 17359 //
2277
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2278
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2279
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
2280
2.27k
        // MIs[1] Operand 1
2281
2.27k
        // No operand predicates
2282
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2283
2.27k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (IMUL64rri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
2284
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32,
2285
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2286
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2287
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2288
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2289
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2290
2.27k
        // GIR_Coverage, 17359,
2291
2.27k
        GIR_Done,
2292
2.27k
      // Label 209: @3123
2293
2.27k
      GIM_Try, /*On fail goto*//*Label 210*/ 3139, // Rule ID 17350 //
2294
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
2295
2.27k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (IMUL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
2296
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL64rr,
2297
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2298
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299
2.27k
        // GIR_Coverage, 17350,
2300
2.27k
        GIR_Done,
2301
2.27k
      // Label 210: @3139
2302
2.27k
      GIM_Reject,
2303
2.27k
    // Label 207: @3140
2304
2.27k
    GIM_Reject,
2305
2.27k
    // Label 189: @3141
2306
2.27k
    GIM_Try, /*On fail goto*//*Label 211*/ 3172, // Rule ID 4194 //
2307
2.27k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2308
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2309
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2310
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2311
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2312
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2313
2.27k
      // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPMULLQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
2314
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ128rr,
2315
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2316
2.27k
      // GIR_Coverage, 4194,
2317
2.27k
      GIR_Done,
2318
2.27k
    // Label 211: @3172
2319
2.27k
    GIM_Reject,
2320
2.27k
    // Label 190: @3173
2321
2.27k
    GIM_Try, /*On fail goto*//*Label 212*/ 3253,
2322
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2323
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2324
2.27k
      GIM_Try, /*On fail goto*//*Label 213*/ 3206, // Rule ID 2499 //
2325
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
2326
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2327
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2328
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2329
2.27k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2330
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDrr,
2331
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2332
2.27k
        // GIR_Coverage, 2499,
2333
2.27k
        GIR_Done,
2334
2.27k
      // Label 213: @3206
2335
2.27k
      GIM_Try, /*On fail goto*//*Label 214*/ 3229, // Rule ID 2507 //
2336
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE41,
2337
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2338
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2339
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2340
2.27k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2341
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLDrr,
2342
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2343
2.27k
        // GIR_Coverage, 2507,
2344
2.27k
        GIR_Done,
2345
2.27k
      // Label 214: @3229
2346
2.27k
      GIM_Try, /*On fail goto*//*Label 215*/ 3252, // Rule ID 4149 //
2347
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2348
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2349
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2350
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2351
2.27k
        // (mul:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPMULLDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
2352
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ128rr,
2353
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2354
2.27k
        // GIR_Coverage, 4149,
2355
2.27k
        GIR_Done,
2356
2.27k
      // Label 215: @3252
2357
2.27k
      GIM_Reject,
2358
2.27k
    // Label 212: @3253
2359
2.27k
    GIM_Reject,
2360
2.27k
    // Label 191: @3254
2361
2.27k
    GIM_Try, /*On fail goto*//*Label 216*/ 3285, // Rule ID 4185 //
2362
2.27k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2363
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
2364
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
2365
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2366
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2367
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2368
2.27k
      // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPMULLQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
2369
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ256rr,
2370
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2371
2.27k
      // GIR_Coverage, 4185,
2372
2.27k
      GIR_Done,
2373
2.27k
    // Label 216: @3285
2374
2.27k
    GIM_Reject,
2375
2.27k
    // Label 192: @3286
2376
2.27k
    GIM_Try, /*On fail goto*//*Label 217*/ 3366,
2377
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2378
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2379
2.27k
      GIM_Try, /*On fail goto*//*Label 218*/ 3319, // Rule ID 1841 //
2380
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
2381
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2382
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2383
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2384
2.27k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2385
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWrr,
2386
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2387
2.27k
        // GIR_Coverage, 1841,
2388
2.27k
        GIR_Done,
2389
2.27k
      // Label 218: @3319
2390
2.27k
      GIM_Try, /*On fail goto*//*Label 219*/ 3342, // Rule ID 1843 //
2391
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2392
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2393
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2394
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2395
2.27k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2396
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLWrr,
2397
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2398
2.27k
        // GIR_Coverage, 1843,
2399
2.27k
        GIR_Done,
2400
2.27k
      // Label 219: @3342
2401
2.27k
      GIM_Try, /*On fail goto*//*Label 220*/ 3365, // Rule ID 4170 //
2402
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2403
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2404
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2405
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2406
2.27k
        // (mul:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPMULLWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
2407
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ128rr,
2408
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2409
2.27k
        // GIR_Coverage, 4170,
2410
2.27k
        GIR_Done,
2411
2.27k
      // Label 220: @3365
2412
2.27k
      GIM_Reject,
2413
2.27k
    // Label 217: @3366
2414
2.27k
    GIM_Reject,
2415
2.27k
    // Label 193: @3367
2416
2.27k
    GIM_Try, /*On fail goto*//*Label 221*/ 3424,
2417
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
2418
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
2419
2.27k
      GIM_Try, /*On fail goto*//*Label 222*/ 3400, // Rule ID 2503 //
2420
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
2421
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2422
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2423
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2424
2.27k
        // (mul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPMULLDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
2425
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDYrr,
2426
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2427
2.27k
        // GIR_Coverage, 2503,
2428
2.27k
        GIR_Done,
2429
2.27k
      // Label 222: @3400
2430
2.27k
      GIM_Try, /*On fail goto*//*Label 223*/ 3423, // Rule ID 4140 //
2431
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2432
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2433
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2434
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2435
2.27k
        // (mul:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPMULLDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
2436
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ256rr,
2437
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2438
2.27k
        // GIR_Coverage, 4140,
2439
2.27k
        GIR_Done,
2440
2.27k
      // Label 223: @3423
2441
2.27k
      GIM_Reject,
2442
2.27k
    // Label 221: @3424
2443
2.27k
    GIM_Reject,
2444
2.27k
    // Label 194: @3425
2445
2.27k
    GIM_Try, /*On fail goto*//*Label 224*/ 3456, // Rule ID 4176 //
2446
2.27k
      GIM_CheckFeatures, GIFBS_HasDQI,
2447
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
2448
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
2449
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2450
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2451
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2452
2.27k
      // (mul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPMULLQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
2453
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZrr,
2454
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2455
2.27k
      // GIR_Coverage, 4176,
2456
2.27k
      GIR_Done,
2457
2.27k
    // Label 224: @3456
2458
2.27k
    GIM_Reject,
2459
2.27k
    // Label 195: @3457
2460
2.27k
    GIM_Try, /*On fail goto*//*Label 225*/ 3514,
2461
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2462
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2463
2.27k
      GIM_Try, /*On fail goto*//*Label 226*/ 3490, // Rule ID 1845 //
2464
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2465
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2466
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2467
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2468
2.27k
        // (mul:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPMULLWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2469
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWYrr,
2470
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2471
2.27k
        // GIR_Coverage, 1845,
2472
2.27k
        GIR_Done,
2473
2.27k
      // Label 226: @3490
2474
2.27k
      GIM_Try, /*On fail goto*//*Label 227*/ 3513, // Rule ID 4164 //
2475
2.27k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2476
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2477
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2478
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2479
2.27k
        // (mul:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPMULLWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2480
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ256rr,
2481
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2482
2.27k
        // GIR_Coverage, 4164,
2483
2.27k
        GIR_Done,
2484
2.27k
      // Label 227: @3513
2485
2.27k
      GIM_Reject,
2486
2.27k
    // Label 225: @3514
2487
2.27k
    GIM_Reject,
2488
2.27k
    // Label 196: @3515
2489
2.27k
    GIM_Try, /*On fail goto*//*Label 228*/ 3546, // Rule ID 4131 //
2490
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2491
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2492
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2493
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2494
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2495
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2496
2.27k
      // (mul:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPMULLDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2497
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZrr,
2498
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2499
2.27k
      // GIR_Coverage, 4131,
2500
2.27k
      GIR_Done,
2501
2.27k
    // Label 228: @3546
2502
2.27k
    GIM_Reject,
2503
2.27k
    // Label 197: @3547
2504
2.27k
    GIM_Try, /*On fail goto*//*Label 229*/ 3578, // Rule ID 4158 //
2505
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
2506
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2507
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2508
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2509
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2510
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2511
2.27k
      // (mul:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPMULLWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2512
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZrr,
2513
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2514
2.27k
      // GIR_Coverage, 4158,
2515
2.27k
      GIR_Done,
2516
2.27k
    // Label 229: @3578
2517
2.27k
    GIM_Reject,
2518
2.27k
    // Label 198: @3579
2519
2.27k
    GIM_Reject,
2520
2.27k
    // Label 3: @3580
2521
2.27k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 253*/ 7084,
2522
2.27k
    /*GILLT_s1*//*Label 230*/ 3611,
2523
2.27k
    /*GILLT_s8*//*Label 231*/ 3909,
2524
2.27k
    /*GILLT_s16*//*Label 232*/ 3975,
2525
2.27k
    /*GILLT_s32*//*Label 233*/ 4074,
2526
2.27k
    /*GILLT_s64*//*Label 234*/ 5045, 0, 0,
2527
2.27k
    /*GILLT_v2s1*//*Label 235*/ 5917,
2528
2.27k
    /*GILLT_v2s64*//*Label 236*/ 6010,
2529
2.27k
    /*GILLT_v4s1*//*Label 237*/ 6091,
2530
2.27k
    /*GILLT_v4s32*//*Label 238*/ 6184,
2531
2.27k
    /*GILLT_v4s64*//*Label 239*/ 6265,
2532
2.27k
    /*GILLT_v8s1*//*Label 240*/ 6346,
2533
2.27k
    /*GILLT_v8s16*//*Label 241*/ 6455,
2534
2.27k
    /*GILLT_v8s32*//*Label 242*/ 6536,
2535
2.27k
    /*GILLT_v8s64*//*Label 243*/ 6617,
2536
2.27k
    /*GILLT_v16s1*//*Label 244*/ 6649,
2537
2.27k
    /*GILLT_v16s8*//*Label 245*/ 6681,
2538
2.27k
    /*GILLT_v16s16*//*Label 246*/ 6762,
2539
2.27k
    /*GILLT_v16s32*//*Label 247*/ 6843,
2540
2.27k
    /*GILLT_v32s1*//*Label 248*/ 6875,
2541
2.27k
    /*GILLT_v32s8*//*Label 249*/ 6907,
2542
2.27k
    /*GILLT_v32s16*//*Label 250*/ 6988,
2543
2.27k
    /*GILLT_v64s1*//*Label 251*/ 7020,
2544
2.27k
    /*GILLT_v64s8*//*Label 252*/ 7052,
2545
2.27k
    // Label 230: @3611
2546
2.27k
    GIM_Try, /*On fail goto*//*Label 254*/ 3908,
2547
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
2548
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2549
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
2550
2.27k
      GIM_Try, /*On fail goto*//*Label 255*/ 3726, // Rule ID 13709 //
2551
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2552
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2553
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2554
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2555
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2556
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2557
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2558
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2559
2.27k
        // (and:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2560
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2561
2.27k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2562
2.27k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2563
2.27k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2564
2.27k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2565
2.27k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2566
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2567
2.27k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2568
2.27k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2569
2.27k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2570
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2571
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2572
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2573
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2574
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2575
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2576
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2577
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2578
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2579
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2580
2.27k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2581
2.27k
        // GIR_Coverage, 13709,
2582
2.27k
        GIR_Done,
2583
2.27k
      // Label 255: @3726
2584
2.27k
      GIM_Try, /*On fail goto*//*Label 256*/ 3827, // Rule ID 19600 //
2585
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2586
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2587
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2588
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2589
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2590
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2591
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2592
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2593
2.27k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }))  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2594
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2595
2.27k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2596
2.27k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2597
2.27k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2598
2.27k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2599
2.27k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2
2600
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2601
2.27k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2602
2.27k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2603
2.27k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2604
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2605
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2606
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2607
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2608
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2609
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2610
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2611
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2612
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2613
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2614
2.27k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2615
2.27k
        // GIR_Coverage, 19600,
2616
2.27k
        GIR_Done,
2617
2.27k
      // Label 256: @3827
2618
2.27k
      GIM_Try, /*On fail goto*//*Label 257*/ 3907, // Rule ID 13705 //
2619
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2620
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2621
2.27k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2622
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2623
2.27k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2624
2.27k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2625
2.27k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2626
2.27k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2627
2.27k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2628
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2629
2.27k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2630
2.27k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2631
2.27k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
2632
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2633
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
2634
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2635
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2636
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2637
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2638
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2639
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2640
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2641
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2642
2.27k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2643
2.27k
        // GIR_Coverage, 13705,
2644
2.27k
        GIR_Done,
2645
2.27k
      // Label 257: @3907
2646
2.27k
      GIM_Reject,
2647
2.27k
    // Label 254: @3908
2648
2.27k
    GIM_Reject,
2649
2.27k
    // Label 231: @3909
2650
2.27k
    GIM_Try, /*On fail goto*//*Label 258*/ 3974,
2651
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
2652
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
2653
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
2654
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
2655
2.27k
      GIM_Try, /*On fail goto*//*Label 259*/ 3957, // Rule ID 17420 //
2656
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2657
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2658
2.27k
        // MIs[1] Operand 1
2659
2.27k
        // No operand predicates
2660
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2661
2.27k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (AND8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
2662
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri,
2663
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2664
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2665
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2666
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2667
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2668
2.27k
        // GIR_Coverage, 17420,
2669
2.27k
        GIR_Done,
2670
2.27k
      // Label 259: @3957
2671
2.27k
      GIM_Try, /*On fail goto*//*Label 260*/ 3973, // Rule ID 17412 //
2672
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
2673
2.27k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (AND8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
2674
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND8rr,
2675
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2676
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677
2.27k
        // GIR_Coverage, 17412,
2678
2.27k
        GIR_Done,
2679
2.27k
      // Label 260: @3973
2680
2.27k
      GIM_Reject,
2681
2.27k
    // Label 258: @3974
2682
2.27k
    GIM_Reject,
2683
2.27k
    // Label 232: @3975
2684
2.27k
    GIM_Try, /*On fail goto*//*Label 261*/ 4073,
2685
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2686
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2687
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2688
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2689
2.27k
      GIM_Try, /*On fail goto*//*Label 262*/ 4026, // Rule ID 17423 //
2690
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2691
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2692
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2693
2.27k
        // MIs[1] Operand 1
2694
2.27k
        // No operand predicates
2695
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2696
2.27k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (AND16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2697
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8,
2698
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2699
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2700
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2701
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2702
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2703
2.27k
        // GIR_Coverage, 17423,
2704
2.27k
        GIR_Done,
2705
2.27k
      // Label 262: @4026
2706
2.27k
      GIM_Try, /*On fail goto*//*Label 263*/ 4056, // Rule ID 17421 //
2707
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2708
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2709
2.27k
        // MIs[1] Operand 1
2710
2.27k
        // No operand predicates
2711
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2712
2.27k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (AND16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2713
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri,
2714
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2715
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2716
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2717
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2718
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2719
2.27k
        // GIR_Coverage, 17421,
2720
2.27k
        GIR_Done,
2721
2.27k
      // Label 263: @4056
2722
2.27k
      GIM_Try, /*On fail goto*//*Label 264*/ 4072, // Rule ID 17413 //
2723
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2724
2.27k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (AND16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2725
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND16rr,
2726
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2727
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2728
2.27k
        // GIR_Coverage, 17413,
2729
2.27k
        GIR_Done,
2730
2.27k
      // Label 264: @4072
2731
2.27k
      GIM_Reject,
2732
2.27k
    // Label 261: @4073
2733
2.27k
    GIM_Reject,
2734
2.27k
    // Label 233: @4074
2735
2.27k
    GIM_Try, /*On fail goto*//*Label 265*/ 5044,
2736
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2737
2.27k
      GIM_Try, /*On fail goto*//*Label 266*/ 4155, // Rule ID 19383 //
2738
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2739
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2740
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2741
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2742
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2743
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2744
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2745
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2746
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2747
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2748
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2749
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2750
2.27k
        // MIs[2] src
2751
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2752
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2753
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2754
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2755
2.27k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2756
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2757
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2758
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2759
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2760
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2761
2.27k
        // GIR_Coverage, 19383,
2762
2.27k
        GIR_Done,
2763
2.27k
      // Label 266: @4155
2764
2.27k
      GIM_Try, /*On fail goto*//*Label 267*/ 4230, // Rule ID 19395 //
2765
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2766
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2767
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2768
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2769
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2770
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2771
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2772
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2773
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2774
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2775
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2776
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2777
2.27k
        // MIs[2] src
2778
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2779
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2780
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2781
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2782
2.27k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2783
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2784
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2785
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2786
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2787
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2788
2.27k
        // GIR_Coverage, 19395,
2789
2.27k
        GIR_Done,
2790
2.27k
      // Label 267: @4230
2791
2.27k
      GIM_Try, /*On fail goto*//*Label 268*/ 4305, // Rule ID 12009 //
2792
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2793
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2794
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2795
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2796
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2797
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2798
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2799
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2800
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2801
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2802
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2803
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2804
2.27k
        // MIs[2] src
2805
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2806
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
2807
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2808
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2809
2.27k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2810
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2811
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2812
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2813
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2814
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2815
2.27k
        // GIR_Coverage, 12009,
2816
2.27k
        GIR_Done,
2817
2.27k
      // Label 268: @4305
2818
2.27k
      GIM_Try, /*On fail goto*//*Label 269*/ 4380, // Rule ID 12021 //
2819
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2820
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2821
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2822
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2823
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2824
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2825
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2826
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2827
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2828
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2829
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2830
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2831
2.27k
        // MIs[2] src
2832
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2833
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2834
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2835
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2836
2.27k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2837
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2838
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2839
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2840
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2841
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2842
2.27k
        // GIR_Coverage, 12021,
2843
2.27k
        GIR_Done,
2844
2.27k
      // Label 269: @4380
2845
2.27k
      GIM_Try, /*On fail goto*//*Label 270*/ 4434, // Rule ID 19367 //
2846
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
2847
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2848
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2849
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2850
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2851
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2852
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2853
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2854
2.27k
        // MIs[0] src
2855
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2856
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2857
2.27k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2858
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2859
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2860
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2861
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2862
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2863
2.27k
        // GIR_Coverage, 19367,
2864
2.27k
        GIR_Done,
2865
2.27k
      // Label 270: @4434
2866
2.27k
      GIM_Try, /*On fail goto*//*Label 271*/ 4488, // Rule ID 19377 //
2867
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2868
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2869
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2870
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2871
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2872
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2873
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2874
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2875
2.27k
        // MIs[0] src
2876
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2877
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2878
2.27k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2879
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2880
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2881
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2882
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2883
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2884
2.27k
        // GIR_Coverage, 19377,
2885
2.27k
        GIR_Done,
2886
2.27k
      // Label 271: @4488
2887
2.27k
      GIM_Try, /*On fail goto*//*Label 272*/ 4542, // Rule ID 19371 //
2888
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
2889
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2890
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2891
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
2892
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2893
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2894
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
2895
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
2896
2.27k
        // MIs[0] src
2897
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2898
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2899
2.27k
        // (and:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2900
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2901
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2902
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
2903
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2904
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2905
2.27k
        // GIR_Coverage, 19371,
2906
2.27k
        GIR_Done,
2907
2.27k
      // Label 272: @4542
2908
2.27k
      GIM_Try, /*On fail goto*//*Label 273*/ 4596, // Rule ID 11987 //
2909
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
2910
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2911
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2912
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2913
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2914
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2915
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2916
2.27k
        // MIs[1] src
2917
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
2918
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2919
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2920
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2921
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2922
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2923
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2924
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2925
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2926
2.27k
        // GIR_Coverage, 11987,
2927
2.27k
        GIR_Done,
2928
2.27k
      // Label 273: @4596
2929
2.27k
      GIM_Try, /*On fail goto*//*Label 274*/ 4650, // Rule ID 12003 //
2930
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
2931
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2932
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2933
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2934
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2935
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2936
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2937
2.27k
        // MIs[1] src
2938
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
2939
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2940
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2941
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2942
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2943
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2944
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2945
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2946
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2947
2.27k
        // GIR_Coverage, 12003,
2948
2.27k
        GIR_Done,
2949
2.27k
      // Label 274: @4650
2950
2.27k
      GIM_Try, /*On fail goto*//*Label 275*/ 4704, // Rule ID 11991 //
2951
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
2952
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2953
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2954
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2955
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2956
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
2957
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2958
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
2959
2.27k
        // MIs[1] src
2960
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2961
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2962
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2963
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2964
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2965
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2966
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2967
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2968
2.27k
        // GIR_Coverage, 11991,
2969
2.27k
        GIR_Done,
2970
2.27k
      // Label 275: @4704
2971
2.27k
      GIM_Try, /*On fail goto*//*Label 276*/ 4755, // Rule ID 17189 //
2972
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2973
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2974
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2975
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
2976
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 65535:{ *:[i32] })  =>  (MOVZX32rr16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src1, sub_16bit:{ *:[i32] }))
2977
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
2978
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
2979
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2980
2.27k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1
2981
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2982
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16,
2983
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2984
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2985
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
2986
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2987
2.27k
        // GIR_Coverage, 17189,
2988
2.27k
        GIR_Done,
2989
2.27k
      // Label 276: @4755
2990
2.27k
      GIM_Try, /*On fail goto*//*Label 277*/ 4806, // Rule ID 17190 //
2991
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2992
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2993
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2994
2.27k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2995
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 255:{ *:[i32] })  =>  (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src1, sub_8bit:{ *:[i32] }))
2996
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
2997
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
2998
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2999
2.27k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1
3000
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3001
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8,
3002
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3003
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3004
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3005
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3006
2.27k
        // GIR_Coverage, 17190,
3007
2.27k
        GIR_Done,
3008
2.27k
      // Label 277: @4806
3009
2.27k
      GIM_Try, /*On fail goto*//*Label 278*/ 4851, // Rule ID 17424 //
3010
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3011
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3012
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3013
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3014
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3015
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
3016
2.27k
        // MIs[1] Operand 1
3017
2.27k
        // No operand predicates
3018
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3019
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (AND32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
3020
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8,
3021
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3022
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3023
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3024
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3025
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3026
2.27k
        // GIR_Coverage, 17424,
3027
2.27k
        GIR_Done,
3028
2.27k
      // Label 278: @4851
3029
2.27k
      GIM_Try, /*On fail goto*//*Label 279*/ 4893, // Rule ID 17422 //
3030
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3031
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3032
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3033
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3034
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3035
2.27k
        // MIs[1] Operand 1
3036
2.27k
        // No operand predicates
3037
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3038
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (AND32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
3039
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri,
3040
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3041
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3042
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3043
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3044
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3045
2.27k
        // GIR_Coverage, 17422,
3046
2.27k
        GIR_Done,
3047
2.27k
      // Label 279: @4893
3048
2.27k
      GIM_Try, /*On fail goto*//*Label 280*/ 4954, // Rule ID 12045 //
3049
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3050
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3051
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3052
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3053
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3054
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3055
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3056
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3057
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3058
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3059
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3060
2.27k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src2)  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3061
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3062
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3063
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3064
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3065
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3066
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3067
2.27k
        // GIR_Coverage, 12045,
3068
2.27k
        GIR_Done,
3069
2.27k
      // Label 280: @4954
3070
2.27k
      GIM_Try, /*On fail goto*//*Label 281*/ 5015, // Rule ID 19411 //
3071
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3072
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3073
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3074
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3075
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3076
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3077
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3078
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3079
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3080
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3081
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3082
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src2, (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }))  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3083
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3084
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3085
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3086
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3087
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3088
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3089
2.27k
        // GIR_Coverage, 19411,
3090
2.27k
        GIR_Done,
3091
2.27k
      // Label 281: @5015
3092
2.27k
      GIM_Try, /*On fail goto*//*Label 282*/ 5043, // Rule ID 17414 //
3093
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3094
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3095
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3096
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3097
2.27k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (AND32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3098
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND32rr,
3099
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3100
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3101
2.27k
        // GIR_Coverage, 17414,
3102
2.27k
        GIR_Done,
3103
2.27k
      // Label 282: @5043
3104
2.27k
      GIM_Reject,
3105
2.27k
    // Label 265: @5044
3106
2.27k
    GIM_Reject,
3107
2.27k
    // Label 234: @5045
3108
2.27k
    GIM_Try, /*On fail goto*//*Label 283*/ 5916,
3109
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3110
2.27k
      GIM_Try, /*On fail goto*//*Label 284*/ 5126, // Rule ID 19384 //
3111
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3112
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3113
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3114
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3115
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3116
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3117
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3118
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3119
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3120
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3121
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3122
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3123
2.27k
        // MIs[2] src
3124
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3125
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3126
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3127
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3128
2.27k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3129
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3130
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3131
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3132
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3133
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3134
2.27k
        // GIR_Coverage, 19384,
3135
2.27k
        GIR_Done,
3136
2.27k
      // Label 284: @5126
3137
2.27k
      GIM_Try, /*On fail goto*//*Label 285*/ 5201, // Rule ID 19396 //
3138
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3139
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3140
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3141
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3142
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3143
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3144
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3145
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3146
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3147
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3148
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3149
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3150
2.27k
        // MIs[2] src
3151
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3152
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3153
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3154
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3155
2.27k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3156
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3157
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3158
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3159
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3160
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3161
2.27k
        // GIR_Coverage, 19396,
3162
2.27k
        GIR_Done,
3163
2.27k
      // Label 285: @5201
3164
2.27k
      GIM_Try, /*On fail goto*//*Label 286*/ 5276, // Rule ID 12010 //
3165
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3166
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3167
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3168
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3169
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3170
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3171
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3172
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3173
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3174
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3175
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3176
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3177
2.27k
        // MIs[2] src
3178
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3179
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
3180
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3181
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3182
2.27k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3183
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3184
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3185
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3186
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3187
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3188
2.27k
        // GIR_Coverage, 12010,
3189
2.27k
        GIR_Done,
3190
2.27k
      // Label 286: @5276
3191
2.27k
      GIM_Try, /*On fail goto*//*Label 287*/ 5351, // Rule ID 12022 //
3192
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3193
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3194
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3195
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3196
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3197
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3198
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3199
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3200
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3201
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3202
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3203
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3204
2.27k
        // MIs[2] src
3205
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3206
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3207
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3208
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3209
2.27k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3210
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3211
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3212
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3213
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3214
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3215
2.27k
        // GIR_Coverage, 12022,
3216
2.27k
        GIR_Done,
3217
2.27k
      // Label 287: @5351
3218
2.27k
      GIM_Try, /*On fail goto*//*Label 288*/ 5405, // Rule ID 19368 //
3219
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3220
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3221
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3222
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3223
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3224
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3225
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3226
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3227
2.27k
        // MIs[0] src
3228
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3229
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3230
2.27k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3231
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3232
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3233
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3234
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3235
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3236
2.27k
        // GIR_Coverage, 19368,
3237
2.27k
        GIR_Done,
3238
2.27k
      // Label 288: @5405
3239
2.27k
      GIM_Try, /*On fail goto*//*Label 289*/ 5459, // Rule ID 19378 //
3240
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3241
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3242
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3243
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3244
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3245
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3246
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3247
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3248
2.27k
        // MIs[0] src
3249
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3250
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3251
2.27k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3252
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3253
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3254
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3255
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3256
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3257
2.27k
        // GIR_Coverage, 19378,
3258
2.27k
        GIR_Done,
3259
2.27k
      // Label 289: @5459
3260
2.27k
      GIM_Try, /*On fail goto*//*Label 290*/ 5513, // Rule ID 19372 //
3261
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3262
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3263
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3264
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3265
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3266
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3267
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3268
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
3269
2.27k
        // MIs[0] src
3270
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3271
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3272
2.27k
        // (and:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3273
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3274
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3275
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
3276
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3277
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3278
2.27k
        // GIR_Coverage, 19372,
3279
2.27k
        GIR_Done,
3280
2.27k
      // Label 290: @5513
3281
2.27k
      GIM_Try, /*On fail goto*//*Label 291*/ 5567, // Rule ID 11988 //
3282
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3283
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3284
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3285
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3286
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3287
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3288
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3289
2.27k
        // MIs[1] src
3290
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3291
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3292
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3293
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3294
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3295
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3296
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3297
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3298
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3299
2.27k
        // GIR_Coverage, 11988,
3300
2.27k
        GIR_Done,
3301
2.27k
      // Label 291: @5567
3302
2.27k
      GIM_Try, /*On fail goto*//*Label 292*/ 5621, // Rule ID 12004 //
3303
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
3304
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3305
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3306
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3307
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3308
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3309
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3310
2.27k
        // MIs[1] src
3311
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3312
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3313
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3314
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3315
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3316
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3317
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3318
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3319
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3320
2.27k
        // GIR_Coverage, 12004,
3321
2.27k
        GIR_Done,
3322
2.27k
      // Label 292: @5621
3323
2.27k
      GIM_Try, /*On fail goto*//*Label 293*/ 5675, // Rule ID 11992 //
3324
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3325
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3326
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3327
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3328
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3329
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3330
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3331
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3332
2.27k
        // MIs[1] src
3333
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3334
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3335
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3336
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3337
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3338
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3339
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3340
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3341
2.27k
        // GIR_Coverage, 11992,
3342
2.27k
        GIR_Done,
3343
2.27k
      // Label 293: @5675
3344
2.27k
      GIM_Try, /*On fail goto*//*Label 294*/ 5720, // Rule ID 17425 //
3345
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3346
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3347
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3348
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3349
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3350
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
3351
2.27k
        // MIs[1] Operand 1
3352
2.27k
        // No operand predicates
3353
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3354
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (AND64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
3355
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8,
3356
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3357
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3358
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3359
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3360
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3361
2.27k
        // GIR_Coverage, 17425,
3362
2.27k
        GIR_Done,
3363
2.27k
      // Label 294: @5720
3364
2.27k
      GIM_Try, /*On fail goto*//*Label 295*/ 5765, // Rule ID 17426 //
3365
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3366
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3367
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3368
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3369
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3370
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
3371
2.27k
        // MIs[1] Operand 1
3372
2.27k
        // No operand predicates
3373
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3374
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (AND64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
3375
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32,
3376
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3377
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3378
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3379
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3380
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3381
2.27k
        // GIR_Coverage, 17426,
3382
2.27k
        GIR_Done,
3383
2.27k
      // Label 295: @5765
3384
2.27k
      GIM_Try, /*On fail goto*//*Label 296*/ 5826, // Rule ID 12046 //
3385
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3386
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3387
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3388
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3389
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3390
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3391
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3392
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3393
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3394
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3395
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3396
2.27k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src2)  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3397
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3398
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3399
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3400
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3401
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3402
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3403
2.27k
        // GIR_Coverage, 12046,
3404
2.27k
        GIR_Done,
3405
2.27k
      // Label 296: @5826
3406
2.27k
      GIM_Try, /*On fail goto*//*Label 297*/ 5887, // Rule ID 19412 //
3407
2.27k
        GIM_CheckFeatures, GIFBS_HasBMI,
3408
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3409
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3410
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3411
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3412
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3413
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3414
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3415
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3416
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3417
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3418
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src2, (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }))  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3419
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3420
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3421
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3422
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3423
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3424
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3425
2.27k
        // GIR_Coverage, 19412,
3426
2.27k
        GIR_Done,
3427
2.27k
      // Label 297: @5887
3428
2.27k
      GIM_Try, /*On fail goto*//*Label 298*/ 5915, // Rule ID 17415 //
3429
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3430
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3431
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3432
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3433
2.27k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (AND64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3434
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND64rr,
3435
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3436
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3437
2.27k
        // GIR_Coverage, 17415,
3438
2.27k
        GIR_Done,
3439
2.27k
      // Label 298: @5915
3440
2.27k
      GIM_Reject,
3441
2.27k
    // Label 283: @5916
3442
2.27k
    GIM_Reject,
3443
2.27k
    // Label 235: @5917
3444
2.27k
    GIM_Try, /*On fail goto*//*Label 299*/ 6009, // Rule ID 13706 //
3445
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
3446
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
3447
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3448
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID,
3449
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID,
3450
2.27k
      // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3451
2.27k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3452
2.27k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3453
2.27k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3454
2.27k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3455
2.27k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3456
2.27k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3457
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3458
2.27k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3459
2.27k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3460
2.27k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3461
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3462
2.27k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3463
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3464
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3465
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3466
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3467
2.27k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3468
2.27k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3469
2.27k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3470
2.27k
      GIR_EraseFromParent, /*InsnID*/0,
3471
2.27k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3472
2.27k
      // GIR_Coverage, 13706,
3473
2.27k
      GIR_Done,
3474
2.27k
    // Label 299: @6009
3475
2.27k
    GIM_Reject,
3476
2.27k
    // Label 236: @6010
3477
2.27k
    GIM_Try, /*On fail goto*//*Label 300*/ 6090,
3478
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3479
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3480
2.27k
      GIM_Try, /*On fail goto*//*Label 301*/ 6043, // Rule ID 1533 //
3481
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3482
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3483
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3484
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3485
2.27k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3486
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3487
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3488
2.27k
        // GIR_Coverage, 1533,
3489
2.27k
        GIR_Done,
3490
2.27k
      // Label 301: @6043
3491
2.27k
      GIM_Try, /*On fail goto*//*Label 302*/ 6066, // Rule ID 1535 //
3492
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3493
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3494
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3495
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3496
2.27k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3497
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3498
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3499
2.27k
        // GIR_Coverage, 1535,
3500
2.27k
        GIR_Done,
3501
2.27k
      // Label 302: @6066
3502
2.27k
      GIM_Try, /*On fail goto*//*Label 303*/ 6089, // Rule ID 4878 //
3503
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3504
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3505
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3506
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3507
2.27k
        // (and:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPANDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
3508
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr,
3509
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3510
2.27k
        // GIR_Coverage, 4878,
3511
2.27k
        GIR_Done,
3512
2.27k
      // Label 303: @6089
3513
2.27k
      GIM_Reject,
3514
2.27k
    // Label 300: @6090
3515
2.27k
    GIM_Reject,
3516
2.27k
    // Label 237: @6091
3517
2.27k
    GIM_Try, /*On fail goto*//*Label 304*/ 6183, // Rule ID 13707 //
3518
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
3519
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
3520
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3521
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID,
3522
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID,
3523
2.27k
      // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3524
2.27k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3525
2.27k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3526
2.27k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3527
2.27k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3528
2.27k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3529
2.27k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3530
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3531
2.27k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3532
2.27k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3533
2.27k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3534
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3535
2.27k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3536
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3537
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3538
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3539
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3540
2.27k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3541
2.27k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3542
2.27k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3543
2.27k
      GIR_EraseFromParent, /*InsnID*/0,
3544
2.27k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3545
2.27k
      // GIR_Coverage, 13707,
3546
2.27k
      GIR_Done,
3547
2.27k
    // Label 304: @6183
3548
2.27k
    GIM_Reject,
3549
2.27k
    // Label 238: @6184
3550
2.27k
    GIM_Try, /*On fail goto*//*Label 305*/ 6264,
3551
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3552
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3553
2.27k
      GIM_Try, /*On fail goto*//*Label 306*/ 6217, // Rule ID 4905 //
3554
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3555
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3556
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3557
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3558
2.27k
        // (and:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPANDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
3559
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ128rr,
3560
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3561
2.27k
        // GIR_Coverage, 4905,
3562
2.27k
        GIR_Done,
3563
2.27k
      // Label 306: @6217
3564
2.27k
      GIM_Try, /*On fail goto*//*Label 307*/ 6240, // Rule ID 12419 //
3565
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3566
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3567
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3568
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3569
2.27k
        // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
3570
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3571
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3572
2.27k
        // GIR_Coverage, 12419,
3573
2.27k
        GIR_Done,
3574
2.27k
      // Label 307: @6240
3575
2.27k
      GIM_Try, /*On fail goto*//*Label 308*/ 6263, // Rule ID 12443 //
3576
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3577
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3578
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3579
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3580
2.27k
        // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
3581
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3582
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3583
2.27k
        // GIR_Coverage, 12443,
3584
2.27k
        GIR_Done,
3585
2.27k
      // Label 308: @6263
3586
2.27k
      GIM_Reject,
3587
2.27k
    // Label 305: @6264
3588
2.27k
    GIM_Reject,
3589
2.27k
    // Label 239: @6265
3590
2.27k
    GIM_Try, /*On fail goto*//*Label 309*/ 6345,
3591
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
3592
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
3593
2.27k
      GIM_Try, /*On fail goto*//*Label 310*/ 6298, // Rule ID 1537 //
3594
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3595
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3596
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3597
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3598
2.27k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPANDYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3599
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3600
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3601
2.27k
        // GIR_Coverage, 1537,
3602
2.27k
        GIR_Done,
3603
2.27k
      // Label 310: @6298
3604
2.27k
      GIM_Try, /*On fail goto*//*Label 311*/ 6321, // Rule ID 4869 //
3605
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3606
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3607
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3608
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3609
2.27k
        // (and:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPANDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
3610
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr,
3611
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3612
2.27k
        // GIR_Coverage, 4869,
3613
2.27k
        GIR_Done,
3614
2.27k
      // Label 311: @6321
3615
2.27k
      GIM_Try, /*On fail goto*//*Label 312*/ 6344, // Rule ID 12372 //
3616
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3617
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3618
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3619
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3620
2.27k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VANDPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3621
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3622
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3623
2.27k
        // GIR_Coverage, 12372,
3624
2.27k
        GIR_Done,
3625
2.27k
      // Label 312: @6344
3626
2.27k
      GIM_Reject,
3627
2.27k
    // Label 309: @6345
3628
2.27k
    GIM_Reject,
3629
2.27k
    // Label 240: @6346
3630
2.27k
    GIM_Try, /*On fail goto*//*Label 313*/ 6454,
3631
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
3632
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
3633
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID,
3634
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID,
3635
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID,
3636
2.27k
      GIM_Try, /*On fail goto*//*Label 314*/ 6379, // Rule ID 3593 //
3637
2.27k
        GIM_CheckFeatures, GIFBS_HasDQI,
3638
2.27k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (KANDBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)
3639
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDBrr,
3640
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3641
2.27k
        // GIR_Coverage, 3593,
3642
2.27k
        GIR_Done,
3643
2.27k
      // Label 314: @6379
3644
2.27k
      GIM_Try, /*On fail goto*//*Label 315*/ 6453, // Rule ID 13704 //
3645
2.27k
        GIM_CheckFeatures, GIFBS_NoDQI,
3646
2.27k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] })
3647
2.27k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3648
2.27k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3649
2.27k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3650
2.27k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3651
2.27k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3652
2.27k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3653
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3654
2.27k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3655
2.27k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3656
2.27k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3657
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3658
2.27k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3659
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3660
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3661
2.27k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3662
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3663
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3664
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3665
2.27k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3666
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
3667
2.27k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12,
3668
2.27k
        // GIR_Coverage, 13704,
3669
2.27k
        GIR_Done,
3670
2.27k
      // Label 315: @6453
3671
2.27k
      GIM_Reject,
3672
2.27k
    // Label 313: @6454
3673
2.27k
    GIM_Reject,
3674
2.27k
    // Label 241: @6455
3675
2.27k
    GIM_Try, /*On fail goto*//*Label 316*/ 6535,
3676
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3677
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3678
2.27k
      GIM_Try, /*On fail goto*//*Label 317*/ 6488, // Rule ID 12418 //
3679
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3680
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3681
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3682
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3683
2.27k
        // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
3684
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3685
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3686
2.27k
        // GIR_Coverage, 12418,
3687
2.27k
        GIR_Done,
3688
2.27k
      // Label 317: @6488
3689
2.27k
      GIM_Try, /*On fail goto*//*Label 318*/ 6511, // Rule ID 12442 //
3690
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3691
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3692
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3693
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3694
2.27k
        // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
3695
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3696
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3697
2.27k
        // GIR_Coverage, 12442,
3698
2.27k
        GIR_Done,
3699
2.27k
      // Label 318: @6511
3700
2.27k
      GIM_Try, /*On fail goto*//*Label 319*/ 6534, // Rule ID 14223 //
3701
2.27k
        GIM_CheckFeatures, GIFBS_HasVLX,
3702
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3703
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3704
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3705
2.27k
        // (and:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPANDQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
3706
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr,
3707
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3708
2.27k
        // GIR_Coverage, 14223,
3709
2.27k
        GIR_Done,
3710
2.27k
      // Label 319: @6534
3711
2.27k
      GIM_Reject,
3712
2.27k
    // Label 316: @6535
3713
2.27k
    GIM_Reject,
3714
2.27k
    // Label 242: @6536
3715
2.27k
    GIM_Try, /*On fail goto*//*Label 320*/ 6616,
3716
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
3717
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
3718
2.27k
      GIM_Try, /*On fail goto*//*Label 321*/ 6569, // Rule ID 4896 //
3719
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3720
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3721
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3722
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3723
2.27k
        // (and:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPANDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
3724
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ256rr,
3725
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3726
2.27k
        // GIR_Coverage, 4896,
3727
2.27k
        GIR_Done,
3728
2.27k
      // Label 321: @6569
3729
2.27k
      GIM_Try, /*On fail goto*//*Label 322*/ 6592, // Rule ID 12347 //
3730
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3731
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3732
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3733
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3734
2.27k
        // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPANDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
3735
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3736
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3737
2.27k
        // GIR_Coverage, 12347,
3738
2.27k
        GIR_Done,
3739
2.27k
      // Label 322: @6592
3740
2.27k
      GIM_Try, /*On fail goto*//*Label 323*/ 6615, // Rule ID 12371 //
3741
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3742
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3743
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3744
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3745
2.27k
        // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VANDPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
3746
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3747
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3748
2.27k
        // GIR_Coverage, 12371,
3749
2.27k
        GIR_Done,
3750
2.27k
      // Label 323: @6615
3751
2.27k
      GIM_Reject,
3752
2.27k
    // Label 320: @6616
3753
2.27k
    GIM_Reject,
3754
2.27k
    // Label 243: @6617
3755
2.27k
    GIM_Try, /*On fail goto*//*Label 324*/ 6648, // Rule ID 4860 //
3756
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3757
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
3758
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
3759
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3760
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3761
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3762
2.27k
      // (and:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPANDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
3763
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr,
3764
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3765
2.27k
      // GIR_Coverage, 4860,
3766
2.27k
      GIR_Done,
3767
2.27k
    // Label 324: @6648
3768
2.27k
    GIM_Reject,
3769
2.27k
    // Label 244: @6649
3770
2.27k
    GIM_Try, /*On fail goto*//*Label 325*/ 6680, // Rule ID 3594 //
3771
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3772
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
3773
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
3774
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID,
3775
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID,
3776
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID,
3777
2.27k
      // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)  =>  (KANDWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)
3778
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDWrr,
3779
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3780
2.27k
      // GIR_Coverage, 3594,
3781
2.27k
      GIR_Done,
3782
2.27k
    // Label 325: @6680
3783
2.27k
    GIM_Reject,
3784
2.27k
    // Label 245: @6681
3785
2.27k
    GIM_Try, /*On fail goto*//*Label 326*/ 6761,
3786
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3787
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3788
2.27k
      GIM_Try, /*On fail goto*//*Label 327*/ 6714, // Rule ID 12417 //
3789
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3790
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3791
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3792
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3793
2.27k
        // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
3794
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3795
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3796
2.27k
        // GIR_Coverage, 12417,
3797
2.27k
        GIR_Done,
3798
2.27k
      // Label 327: @6714
3799
2.27k
      GIM_Try, /*On fail goto*//*Label 328*/ 6737, // Rule ID 12441 //
3800
2.27k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3801
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3802
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3803
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3804
2.27k
        // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
3805
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3806
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3807
2.27k
        // GIR_Coverage, 12441,
3808
2.27k
        GIR_Done,
3809
2.27k
      // Label 328: @6737
3810
2.27k
      GIM_Try, /*On fail goto*//*Label 329*/ 6760, // Rule ID 14222 //
3811
2.27k
        GIM_CheckFeatures, GIFBS_HasVLX,
3812
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3813
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3814
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3815
2.27k
        // (and:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPANDQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
3816
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr,
3817
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3818
2.27k
        // GIR_Coverage, 14222,
3819
2.27k
        GIR_Done,
3820
2.27k
      // Label 329: @6760
3821
2.27k
      GIM_Reject,
3822
2.27k
    // Label 326: @6761
3823
2.27k
    GIM_Reject,
3824
2.27k
    // Label 246: @6762
3825
2.27k
    GIM_Try, /*On fail goto*//*Label 330*/ 6842,
3826
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
3827
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
3828
2.27k
      GIM_Try, /*On fail goto*//*Label 331*/ 6795, // Rule ID 12346 //
3829
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3830
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3831
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3832
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3833
2.27k
        // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPANDYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
3834
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3835
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3836
2.27k
        // GIR_Coverage, 12346,
3837
2.27k
        GIR_Done,
3838
2.27k
      // Label 331: @6795
3839
2.27k
      GIM_Try, /*On fail goto*//*Label 332*/ 6818, // Rule ID 12370 //
3840
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3841
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3842
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3843
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3844
2.27k
        // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VANDPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
3845
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3846
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3847
2.27k
        // GIR_Coverage, 12370,
3848
2.27k
        GIR_Done,
3849
2.27k
      // Label 332: @6818
3850
2.27k
      GIM_Try, /*On fail goto*//*Label 333*/ 6841, // Rule ID 14247 //
3851
2.27k
        GIM_CheckFeatures, GIFBS_HasVLX,
3852
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3853
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3854
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3855
2.27k
        // (and:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPANDQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
3856
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr,
3857
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3858
2.27k
        // GIR_Coverage, 14247,
3859
2.27k
        GIR_Done,
3860
2.27k
      // Label 333: @6841
3861
2.27k
      GIM_Reject,
3862
2.27k
    // Label 330: @6842
3863
2.27k
    GIM_Reject,
3864
2.27k
    // Label 247: @6843
3865
2.27k
    GIM_Try, /*On fail goto*//*Label 334*/ 6874, // Rule ID 4887 //
3866
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3867
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
3868
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
3869
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3870
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3871
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3872
2.27k
      // (and:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPANDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
3873
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZrr,
3874
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3875
2.27k
      // GIR_Coverage, 4887,
3876
2.27k
      GIR_Done,
3877
2.27k
    // Label 334: @6874
3878
2.27k
    GIM_Reject,
3879
2.27k
    // Label 248: @6875
3880
2.27k
    GIM_Try, /*On fail goto*//*Label 335*/ 6906, // Rule ID 3595 //
3881
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
3882
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1,
3883
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1,
3884
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID,
3885
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID,
3886
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID,
3887
2.27k
      // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)  =>  (KANDDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)
3888
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDDrr,
3889
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3890
2.27k
      // GIR_Coverage, 3595,
3891
2.27k
      GIR_Done,
3892
2.27k
    // Label 335: @6906
3893
2.27k
    GIM_Reject,
3894
2.27k
    // Label 249: @6907
3895
2.27k
    GIM_Try, /*On fail goto*//*Label 336*/ 6987,
3896
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
3897
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
3898
2.27k
      GIM_Try, /*On fail goto*//*Label 337*/ 6940, // Rule ID 12345 //
3899
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3900
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3901
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3902
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3903
2.27k
        // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPANDYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
3904
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3905
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3906
2.27k
        // GIR_Coverage, 12345,
3907
2.27k
        GIR_Done,
3908
2.27k
      // Label 337: @6940
3909
2.27k
      GIM_Try, /*On fail goto*//*Label 338*/ 6963, // Rule ID 12369 //
3910
2.27k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3911
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3912
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3913
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3914
2.27k
        // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VANDPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
3915
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3916
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3917
2.27k
        // GIR_Coverage, 12369,
3918
2.27k
        GIR_Done,
3919
2.27k
      // Label 338: @6963
3920
2.27k
      GIM_Try, /*On fail goto*//*Label 339*/ 6986, // Rule ID 14246 //
3921
2.27k
        GIM_CheckFeatures, GIFBS_HasVLX,
3922
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3923
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3924
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3925
2.27k
        // (and:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPANDQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
3926
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr,
3927
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3928
2.27k
        // GIR_Coverage, 14246,
3929
2.27k
        GIR_Done,
3930
2.27k
      // Label 339: @6986
3931
2.27k
      GIM_Reject,
3932
2.27k
    // Label 336: @6987
3933
2.27k
    GIM_Reject,
3934
2.27k
    // Label 250: @6988
3935
2.27k
    GIM_Try, /*On fail goto*//*Label 340*/ 7019, // Rule ID 14271 //
3936
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3937
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
3938
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
3939
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3940
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3941
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3942
2.27k
      // (and:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPANDQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
3943
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr,
3944
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3945
2.27k
      // GIR_Coverage, 14271,
3946
2.27k
      GIR_Done,
3947
2.27k
    // Label 340: @7019
3948
2.27k
    GIM_Reject,
3949
2.27k
    // Label 251: @7020
3950
2.27k
    GIM_Try, /*On fail goto*//*Label 341*/ 7051, // Rule ID 3596 //
3951
2.27k
      GIM_CheckFeatures, GIFBS_HasBWI,
3952
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1,
3953
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1,
3954
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID,
3955
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID,
3956
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID,
3957
2.27k
      // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)  =>  (KANDQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)
3958
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDQrr,
3959
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3960
2.27k
      // GIR_Coverage, 3596,
3961
2.27k
      GIR_Done,
3962
2.27k
    // Label 341: @7051
3963
2.27k
    GIM_Reject,
3964
2.27k
    // Label 252: @7052
3965
2.27k
    GIM_Try, /*On fail goto*//*Label 342*/ 7083, // Rule ID 14270 //
3966
2.27k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3967
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
3968
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
3969
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3970
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3971
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3972
2.27k
      // (and:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPANDQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
3973
2.27k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr,
3974
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3975
2.27k
      // GIR_Coverage, 14270,
3976
2.27k
      GIR_Done,
3977
2.27k
    // Label 342: @7083
3978
2.27k
    GIM_Reject,
3979
2.27k
    // Label 253: @7084
3980
2.27k
    GIM_Reject,
3981
2.27k
    // Label 4: @7085
3982
2.27k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 366*/ 10338,
3983
2.27k
    /*GILLT_s1*//*Label 343*/ 7116,
3984
2.27k
    /*GILLT_s8*//*Label 344*/ 7209,
3985
2.27k
    /*GILLT_s16*//*Label 345*/ 7275,
3986
2.27k
    /*GILLT_s32*//*Label 346*/ 7374,
3987
2.27k
    /*GILLT_s64*//*Label 347*/ 8271, 0, 0,
3988
2.27k
    /*GILLT_v2s1*//*Label 348*/ 9171,
3989
2.27k
    /*GILLT_v2s64*//*Label 349*/ 9264,
3990
2.27k
    /*GILLT_v4s1*//*Label 350*/ 9345,
3991
2.27k
    /*GILLT_v4s32*//*Label 351*/ 9438,
3992
2.27k
    /*GILLT_v4s64*//*Label 352*/ 9519,
3993
2.27k
    /*GILLT_v8s1*//*Label 353*/ 9600,
3994
2.27k
    /*GILLT_v8s16*//*Label 354*/ 9709,
3995
2.27k
    /*GILLT_v8s32*//*Label 355*/ 9790,
3996
2.27k
    /*GILLT_v8s64*//*Label 356*/ 9871,
3997
2.27k
    /*GILLT_v16s1*//*Label 357*/ 9903,
3998
2.27k
    /*GILLT_v16s8*//*Label 358*/ 9935,
3999
2.27k
    /*GILLT_v16s16*//*Label 359*/ 10016,
4000
2.27k
    /*GILLT_v16s32*//*Label 360*/ 10097,
4001
2.27k
    /*GILLT_v32s1*//*Label 361*/ 10129,
4002
2.27k
    /*GILLT_v32s8*//*Label 362*/ 10161,
4003
2.27k
    /*GILLT_v32s16*//*Label 363*/ 10242,
4004
2.27k
    /*GILLT_v64s1*//*Label 364*/ 10274,
4005
2.27k
    /*GILLT_v64s8*//*Label 365*/ 10306,
4006
2.27k
    // Label 343: @7116
4007
2.27k
    GIM_Try, /*On fail goto*//*Label 367*/ 7208, // Rule ID 13713 //
4008
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
4009
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
4010
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
4011
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
4012
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
4013
2.27k
      // (or:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
4014
2.27k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4015
2.27k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4016
2.27k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4017
2.27k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4018
2.27k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4019
2.27k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4020
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4021
2.27k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4022
2.27k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4023
2.27k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
4024
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4025
2.27k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4026
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4027
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4028
2.27k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
4029
2.27k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4030
2.27k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4031
2.27k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4032
2.27k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4033
2.27k
      GIR_EraseFromParent, /*InsnID*/0,
4034
2.27k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
4035
2.27k
      // GIR_Coverage, 13713,
4036
2.27k
      GIR_Done,
4037
2.27k
    // Label 367: @7208
4038
2.27k
    GIM_Reject,
4039
2.27k
    // Label 344: @7209
4040
2.27k
    GIM_Try, /*On fail goto*//*Label 368*/ 7274,
4041
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
4042
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
4043
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
4044
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
4045
2.27k
      GIM_Try, /*On fail goto*//*Label 369*/ 7257, // Rule ID 17390 //
4046
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4047
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4048
2.27k
        // MIs[1] Operand 1
4049
2.27k
        // No operand predicates
4050
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4051
2.27k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (OR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
4052
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri,
4053
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4054
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4055
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4056
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4057
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4058
2.27k
        // GIR_Coverage, 17390,
4059
2.27k
        GIR_Done,
4060
2.27k
      // Label 369: @7257
4061
2.27k
      GIM_Try, /*On fail goto*//*Label 370*/ 7273, // Rule ID 17382 //
4062
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
4063
2.27k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (OR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
4064
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR8rr,
4065
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4066
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4067
2.27k
        // GIR_Coverage, 17382,
4068
2.27k
        GIR_Done,
4069
2.27k
      // Label 370: @7273
4070
2.27k
      GIM_Reject,
4071
2.27k
    // Label 368: @7274
4072
2.27k
    GIM_Reject,
4073
2.27k
    // Label 345: @7275
4074
2.27k
    GIM_Try, /*On fail goto*//*Label 371*/ 7373,
4075
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
4076
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
4077
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
4078
2.27k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
4079
2.27k
      GIM_Try, /*On fail goto*//*Label 372*/ 7326, // Rule ID 17393 //
4080
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4081
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4082
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
4083
2.27k
        // MIs[1] Operand 1
4084
2.27k
        // No operand predicates
4085
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4086
2.27k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (OR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
4087
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8,
4088
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4089
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4090
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4091
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4092
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4093
2.27k
        // GIR_Coverage, 17393,
4094
2.27k
        GIR_Done,
4095
2.27k
      // Label 372: @7326
4096
2.27k
      GIM_Try, /*On fail goto*//*Label 373*/ 7356, // Rule ID 17391 //
4097
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4098
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4099
2.27k
        // MIs[1] Operand 1
4100
2.27k
        // No operand predicates
4101
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4102
2.27k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (OR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
4103
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri,
4104
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4105
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4106
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4107
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4108
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4109
2.27k
        // GIR_Coverage, 17391,
4110
2.27k
        GIR_Done,
4111
2.27k
      // Label 373: @7356
4112
2.27k
      GIM_Try, /*On fail goto*//*Label 374*/ 7372, // Rule ID 17383 //
4113
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
4114
2.27k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (OR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
4115
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR16rr,
4116
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4117
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4118
2.27k
        // GIR_Coverage, 17383,
4119
2.27k
        GIR_Done,
4120
2.27k
      // Label 374: @7372
4121
2.27k
      GIM_Reject,
4122
2.27k
    // Label 371: @7373
4123
2.27k
    GIM_Reject,
4124
2.27k
    // Label 346: @7374
4125
2.27k
    GIM_Try, /*On fail goto*//*Label 375*/ 8270,
4126
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4127
2.27k
      GIM_Try, /*On fail goto*//*Label 376*/ 7455, // Rule ID 19391 //
4128
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4129
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4130
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4131
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4132
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4133
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4134
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4135
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4136
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4137
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4138
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4139
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4140
2.27k
        // MIs[2] src
4141
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4142
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4143
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4144
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4145
2.27k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4146
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
4147
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4148
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4149
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4150
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4151
2.27k
        // GIR_Coverage, 19391,
4152
2.27k
        GIR_Done,
4153
2.27k
      // Label 376: @7455
4154
2.27k
      GIM_Try, /*On fail goto*//*Label 377*/ 7530, // Rule ID 19393 //
4155
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4156
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4157
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4158
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4159
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4160
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4161
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4162
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4163
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4164
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4165
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4166
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4167
2.27k
        // MIs[2] src
4168
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4169
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4170
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4171
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4172
2.27k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4173
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4174
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4175
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4176
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4177
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4178
2.27k
        // GIR_Coverage, 19393,
4179
2.27k
        GIR_Done,
4180
2.27k
      // Label 377: @7530
4181
2.27k
      GIM_Try, /*On fail goto*//*Label 378*/ 7605, // Rule ID 19379 //
4182
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4183
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4184
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4185
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4186
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4187
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4188
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4189
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4190
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4191
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4192
2.27k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR32RegClassID,
4193
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4194
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4195
2.27k
        // MIs[0] src
4196
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4197
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4198
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4199
2.27k
        // (or:{ *:[i32] } (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4200
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4201
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4202
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
4203
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4204
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4205
2.27k
        // GIR_Coverage, 19379,
4206
2.27k
        GIR_Done,
4207
2.27k
      // Label 378: @7605
4208
2.27k
      GIM_Try, /*On fail goto*//*Label 379*/ 7680, // Rule ID 12017 //
4209
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4210
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4211
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4212
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4213
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4214
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4215
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4216
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4217
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4218
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4219
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4220
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4221
2.27k
        // MIs[2] src
4222
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4223
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4224
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4225
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4226
2.27k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4227
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
4228
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4229
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4230
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4231
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4232
2.27k
        // GIR_Coverage, 12017,
4233
2.27k
        GIR_Done,
4234
2.27k
      // Label 379: @7680
4235
2.27k
      GIM_Try, /*On fail goto*//*Label 380*/ 7755, // Rule ID 12019 //
4236
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4237
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4238
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4239
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4240
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4241
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4242
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4243
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4244
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4245
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4246
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4247
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4248
2.27k
        // MIs[2] src
4249
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4250
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4251
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4252
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4253
2.27k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4254
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4255
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4256
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4257
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4258
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4259
2.27k
        // GIR_Coverage, 12019,
4260
2.27k
        GIR_Done,
4261
2.27k
      // Label 380: @7755
4262
2.27k
      GIM_Try, /*On fail goto*//*Label 381*/ 7830, // Rule ID 12005 //
4263
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4264
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4265
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4266
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4267
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4268
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4269
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4270
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4271
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4272
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4273
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4274
2.27k
        // MIs[2] src
4275
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4276
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4277
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4278
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4279
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4280
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4281
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4282
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4283
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4284
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4285
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4286
2.27k
        // GIR_Coverage, 12005,
4287
2.27k
        GIR_Done,
4288
2.27k
      // Label 381: @7830
4289
2.27k
      GIM_Try, /*On fail goto*//*Label 382*/ 7884, // Rule ID 19387 //
4290
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4291
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4292
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4293
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4294
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4295
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4296
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4297
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4298
2.27k
        // MIs[0] src
4299
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4300
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4301
2.27k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4302
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4303
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4304
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4305
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4306
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4307
2.27k
        // GIR_Coverage, 19387,
4308
2.27k
        GIR_Done,
4309
2.27k
      // Label 382: @7884
4310
2.27k
      GIM_Try, /*On fail goto*//*Label 383*/ 7938, // Rule ID 19389 //
4311
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4312
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4313
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4314
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4315
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4316
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4317
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4318
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4319
2.27k
        // MIs[0] src
4320
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4321
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4322
2.27k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4323
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4324
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4325
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4326
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4327
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4328
2.27k
        // GIR_Coverage, 19389,
4329
2.27k
        GIR_Done,
4330
2.27k
      // Label 383: @7938
4331
2.27k
      GIM_Try, /*On fail goto*//*Label 384*/ 7992, // Rule ID 19381 //
4332
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4333
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4334
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4335
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4336
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4337
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4338
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4339
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
4340
2.27k
        // MIs[0] src
4341
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4342
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4343
2.27k
        // (or:{ *:[i32] } (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4344
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4345
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4346
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4347
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4348
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4349
2.27k
        // GIR_Coverage, 19381,
4350
2.27k
        GIR_Done,
4351
2.27k
      // Label 384: @7992
4352
2.27k
      GIM_Try, /*On fail goto*//*Label 385*/ 8046, // Rule ID 12013 //
4353
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4354
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4355
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4356
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4357
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4358
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4359
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4360
2.27k
        // MIs[1] src
4361
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4362
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4363
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4364
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4365
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4366
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4367
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4368
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4369
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4370
2.27k
        // GIR_Coverage, 12013,
4371
2.27k
        GIR_Done,
4372
2.27k
      // Label 385: @8046
4373
2.27k
      GIM_Try, /*On fail goto*//*Label 386*/ 8100, // Rule ID 12015 //
4374
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4375
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4376
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4377
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4378
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4379
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4380
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4381
2.27k
        // MIs[1] src
4382
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4383
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4384
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4385
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4386
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4387
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4388
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4389
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4390
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4391
2.27k
        // GIR_Coverage, 12015,
4392
2.27k
        GIR_Done,
4393
2.27k
      // Label 386: @8100
4394
2.27k
      GIM_Try, /*On fail goto*//*Label 387*/ 8154, // Rule ID 12007 //
4395
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4396
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4397
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4398
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4399
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4400
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4401
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4402
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4403
2.27k
        // MIs[1] src
4404
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4405
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4406
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4407
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4408
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4409
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4410
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4411
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4412
2.27k
        // GIR_Coverage, 12007,
4413
2.27k
        GIR_Done,
4414
2.27k
      // Label 387: @8154
4415
2.27k
      GIM_Try, /*On fail goto*//*Label 388*/ 8199, // Rule ID 17394 //
4416
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4417
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4418
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4419
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4420
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4421
2.27k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
4422
2.27k
        // MIs[1] Operand 1
4423
2.27k
        // No operand predicates
4424
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4425
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (OR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
4426
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8,
4427
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4428
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4429
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4430
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4431
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4432
2.27k
        // GIR_Coverage, 17394,
4433
2.27k
        GIR_Done,
4434
2.27k
      // Label 388: @8199
4435
2.27k
      GIM_Try, /*On fail goto*//*Label 389*/ 8241, // Rule ID 17392 //
4436
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4437
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4438
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4439
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4440
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4441
2.27k
        // MIs[1] Operand 1
4442
2.27k
        // No operand predicates
4443
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4444
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (OR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
4445
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri,
4446
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4447
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4448
2.27k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4449
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4450
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4451
2.27k
        // GIR_Coverage, 17392,
4452
2.27k
        GIR_Done,
4453
2.27k
      // Label 389: @8241
4454
2.27k
      GIM_Try, /*On fail goto*//*Label 390*/ 8269, // Rule ID 17384 //
4455
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4456
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4457
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4458
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
4459
2.27k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (OR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
4460
2.27k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR32rr,
4461
2.27k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4462
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4463
2.27k
        // GIR_Coverage, 17384,
4464
2.27k
        GIR_Done,
4465
2.27k
      // Label 390: @8269
4466
2.27k
      GIM_Reject,
4467
2.27k
    // Label 375: @8270
4468
2.27k
    GIM_Reject,
4469
2.27k
    // Label 347: @8271
4470
2.27k
    GIM_Try, /*On fail goto*//*Label 391*/ 9170,
4471
2.27k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4472
2.27k
      GIM_Try, /*On fail goto*//*Label 392*/ 8352, // Rule ID 19392 //
4473
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4474
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4475
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4476
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4477
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4478
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4479
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4480
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4481
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4482
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4483
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4484
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4485
2.27k
        // MIs[2] src
4486
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4487
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4488
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4489
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4490
2.27k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4491
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4492
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4493
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4494
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4495
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4496
2.27k
        // GIR_Coverage, 19392,
4497
2.27k
        GIR_Done,
4498
2.27k
      // Label 392: @8352
4499
2.27k
      GIM_Try, /*On fail goto*//*Label 393*/ 8427, // Rule ID 19394 //
4500
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4501
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4502
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4503
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4504
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4505
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4506
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4507
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4508
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4509
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4510
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4511
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4512
2.27k
        // MIs[2] src
4513
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4514
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4515
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4516
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4517
2.27k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4518
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4519
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4520
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4521
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4522
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4523
2.27k
        // GIR_Coverage, 19394,
4524
2.27k
        GIR_Done,
4525
2.27k
      // Label 393: @8427
4526
2.27k
      GIM_Try, /*On fail goto*//*Label 394*/ 8502, // Rule ID 19380 //
4527
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4528
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4529
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4530
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4531
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4532
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4533
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4534
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4535
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4536
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4537
2.27k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR64RegClassID,
4538
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4539
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4540
2.27k
        // MIs[0] src
4541
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4542
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4543
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4544
2.27k
        // (or:{ *:[i64] } (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4545
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4546
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4547
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
4548
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4549
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4550
2.27k
        // GIR_Coverage, 19380,
4551
2.27k
        GIR_Done,
4552
2.27k
      // Label 394: @8502
4553
2.27k
      GIM_Try, /*On fail goto*//*Label 395*/ 8577, // Rule ID 12018 //
4554
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4555
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4556
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4557
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4558
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4559
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4560
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4561
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4562
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4563
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4564
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4565
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4566
2.27k
        // MIs[2] src
4567
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4568
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4569
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4570
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4571
2.27k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4572
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4573
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4574
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4575
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4576
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4577
2.27k
        // GIR_Coverage, 12018,
4578
2.27k
        GIR_Done,
4579
2.27k
      // Label 395: @8577
4580
2.27k
      GIM_Try, /*On fail goto*//*Label 396*/ 8652, // Rule ID 12020 //
4581
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4582
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4583
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4584
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4585
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4586
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4587
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4588
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4589
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4590
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4591
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4592
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4593
2.27k
        // MIs[2] src
4594
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4595
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4596
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4597
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4598
2.27k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4599
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4600
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4601
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4602
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4603
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4604
2.27k
        // GIR_Coverage, 12020,
4605
2.27k
        GIR_Done,
4606
2.27k
      // Label 396: @8652
4607
2.27k
      GIM_Try, /*On fail goto*//*Label 397*/ 8727, // Rule ID 12006 //
4608
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4609
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4610
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4611
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4612
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4613
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4614
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4615
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4616
2.27k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4617
2.27k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4618
2.27k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4619
2.27k
        // MIs[2] src
4620
2.27k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4621
2.27k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4622
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4623
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4624
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4625
2.27k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4626
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4627
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4628
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4629
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4630
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4631
2.27k
        // GIR_Coverage, 12006,
4632
2.27k
        GIR_Done,
4633
2.27k
      // Label 397: @8727
4634
2.27k
      GIM_Try, /*On fail goto*//*Label 398*/ 8781, // Rule ID 19388 //
4635
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4636
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4637
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4638
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4639
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4640
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4641
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4642
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4643
2.27k
        // MIs[0] src
4644
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4645
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4646
2.27k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4647
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4648
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4649
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4650
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4651
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4652
2.27k
        // GIR_Coverage, 19388,
4653
2.27k
        GIR_Done,
4654
2.27k
      // Label 398: @8781
4655
2.27k
      GIM_Try, /*On fail goto*//*Label 399*/ 8835, // Rule ID 19390 //
4656
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4657
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4658
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4659
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4660
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4661
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4662
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4663
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4664
2.27k
        // MIs[0] src
4665
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4666
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4667
2.27k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4668
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4669
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4670
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4671
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4672
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4673
2.27k
        // GIR_Coverage, 19390,
4674
2.27k
        GIR_Done,
4675
2.27k
      // Label 399: @8835
4676
2.27k
      GIM_Try, /*On fail goto*//*Label 400*/ 8889, // Rule ID 19382 //
4677
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4678
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4679
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4680
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4681
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4682
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4683
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4684
2.27k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
4685
2.27k
        // MIs[0] src
4686
2.27k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4687
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4688
2.27k
        // (or:{ *:[i64] } (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4689
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4690
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4691
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4692
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4693
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4694
2.27k
        // GIR_Coverage, 19382,
4695
2.27k
        GIR_Done,
4696
2.27k
      // Label 400: @8889
4697
2.27k
      GIM_Try, /*On fail goto*//*Label 401*/ 8943, // Rule ID 12014 //
4698
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4699
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4700
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4701
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4702
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4703
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4704
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4705
2.27k
        // MIs[1] src
4706
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4707
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4708
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4709
2.27k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4710
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4711
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4712
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4713
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4714
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4715
2.27k
        // GIR_Coverage, 12014,
4716
2.27k
        GIR_Done,
4717
2.27k
      // Label 401: @8943
4718
2.27k
      GIM_Try, /*On fail goto*//*Label 402*/ 8997, // Rule ID 12016 //
4719
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4720
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4721
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4722
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4723
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4724
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4725
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4726
2.27k
        // MIs[1] src
4727
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4728
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4729
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4730
2.27k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4731
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4732
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4733
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4734
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4735
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4736
2.27k
        // GIR_Coverage, 12016,
4737
2.27k
        GIR_Done,
4738
2.27k
      // Label 402: @8997
4739
2.27k
      GIM_Try, /*On fail goto*//*Label 403*/ 9051, // Rule ID 12008 //
4740
2.27k
        GIM_CheckFeatures, GIFBS_HasTBM,
4741
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4742
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4743
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4744
2.27k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4745
2.27k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4746
2.27k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4747
2.27k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4748
2.27k
        // MIs[1] src
4749
2.27k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4750
2.27k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4751
2.27k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4752
2.27k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4753
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4754
2.27k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4755
2.27k
        GIR_EraseFromParent, /*InsnID*/0,
4756
2.27k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4757
2.27k
        // GIR_Coverage, 12008,
4758
2.27k
        GIR_Done,
4759
2.27k
      // Label 403: @9051
4760
2.27k
      GIM_Try, /*On fail goto*//*Label 404*/ 9096, // Rule ID 17395 //
4761
2.27k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4762
2.27k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4763
2.27k
        GIM_CheckRegBa