Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the X86 target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 113;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(X86InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(X86InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static X86InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static X86InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_TruePredicateBit = 48,
37
  Feature_HasCMovBit = 20,
38
  Feature_NoCMovBit = 100,
39
  Feature_HasMMXBit = 81,
40
  Feature_Has3DNowBit = 83,
41
  Feature_HasSSE1Bit = 34,
42
  Feature_UseSSE1Bit = 42,
43
  Feature_HasSSE2Bit = 35,
44
  Feature_UseSSE2Bit = 43,
45
  Feature_HasSSE3Bit = 26,
46
  Feature_UseSSE3Bit = 51,
47
  Feature_HasSSSE3Bit = 82,
48
  Feature_UseSSSE3Bit = 52,
49
  Feature_UseSSE41Bit = 49,
50
  Feature_HasSSE42Bit = 56,
51
  Feature_UseSSE42Bit = 55,
52
  Feature_HasSSE4ABit = 65,
53
  Feature_NoAVXBit = 61,
54
  Feature_HasAVXBit = 44,
55
  Feature_HasAVX2Bit = 38,
56
  Feature_HasAVX1OnlyBit = 36,
57
  Feature_HasAVX512Bit = 69,
58
  Feature_UseAVXBit = 40,
59
  Feature_UseAVX2Bit = 67,
60
  Feature_NoAVX512Bit = 31,
61
  Feature_HasCDIBit = 73,
62
  Feature_HasVPOPCNTDQBit = 77,
63
  Feature_HasERIBit = 76,
64
  Feature_HasDQIBit = 71,
65
  Feature_NoDQIBit = 53,
66
  Feature_HasBWIBit = 72,
67
  Feature_NoBWIBit = 50,
68
  Feature_HasVLXBit = 70,
69
  Feature_NoVLXBit = 30,
70
  Feature_NoVLX_Or_NoBWIBit = 47,
71
  Feature_NoVLX_Or_NoDQIBit = 104,
72
  Feature_HasVNNIBit = 79,
73
  Feature_HasBITALGBit = 80,
74
  Feature_HasPOPCNTBit = 54,
75
  Feature_HasAESBit = 58,
76
  Feature_HasVAESBit = 60,
77
  Feature_NoVLX_Or_NoVAESBit = 59,
78
  Feature_HasFXSRBit = 27,
79
  Feature_HasXSAVEBit = 89,
80
  Feature_HasXSAVEOPTBit = 90,
81
  Feature_HasXSAVECBit = 91,
82
  Feature_HasXSAVESBit = 92,
83
  Feature_HasPCLMULBit = 62,
84
  Feature_NoVLX_Or_NoVPCLMULQDQBit = 63,
85
  Feature_HasVPCLMULQDQBit = 64,
86
  Feature_HasGFNIBit = 68,
87
  Feature_HasFMABit = 28,
88
  Feature_HasFMA4Bit = 32,
89
  Feature_NoFMA4Bit = 29,
90
  Feature_HasXOPBit = 33,
91
  Feature_HasTBMBit = 9,
92
  Feature_NoTBMBit = 111,
93
  Feature_HasLWPBit = 10,
94
  Feature_HasMOVBEBit = 3,
95
  Feature_HasRDRANDBit = 4,
96
  Feature_HasF16CBit = 66,
97
  Feature_HasFSGSBaseBit = 93,
98
  Feature_HasLZCNTBit = 6,
99
  Feature_HasBMIBit = 7,
100
  Feature_HasBMI2Bit = 8,
101
  Feature_NoBMI2Bit = 112,
102
  Feature_HasVBMIBit = 74,
103
  Feature_HasVBMI2Bit = 78,
104
  Feature_HasIFMABit = 75,
105
  Feature_HasRTMBit = 87,
106
  Feature_HasSHABit = 57,
107
  Feature_HasRDSEEDBit = 5,
108
  Feature_HasSSEPrefetchBit = 45,
109
  Feature_NoSSEPrefetchBit = 84,
110
  Feature_HasPrefetchWBit = 85,
111
  Feature_HasPREFETCHWT1Bit = 86,
112
  Feature_HasLAHFSAHFBit = 2,
113
  Feature_HasMWAITXBit = 11,
114
  Feature_HasCLZEROBit = 15,
115
  Feature_HasCLDEMOTEBit = 18,
116
  Feature_HasMOVDIRIBit = 13,
117
  Feature_HasMOVDIR64BBit = 14,
118
  Feature_HasPTWRITEBit = 96,
119
  Feature_FPStackf32Bit = 24,
120
  Feature_FPStackf64Bit = 25,
121
  Feature_HasCLFLUSHOPTBit = 16,
122
  Feature_HasCLWBBit = 17,
123
  Feature_HasWBNOINVDBit = 88,
124
  Feature_HasRDPIDBit = 95,
125
  Feature_HasWAITPKGBit = 12,
126
  Feature_HasINVPCIDBit = 94,
127
  Feature_HasCmpxchg16bBit = 101,
128
  Feature_Not64BitModeBit = 0,
129
  Feature_In64BitModeBit = 1,
130
  Feature_IsLP64Bit = 98,
131
  Feature_NotLP64Bit = 97,
132
  Feature_NotWin64WithoutFPBit = 99,
133
  Feature_IsPS4Bit = 106,
134
  Feature_NotPS4Bit = 105,
135
  Feature_KernelCodeBit = 107,
136
  Feature_NearDataBit = 109,
137
  Feature_IsNotPICBit = 108,
138
  Feature_OptForSizeBit = 39,
139
  Feature_OptForMinSizeBit = 37,
140
  Feature_OptForSpeedBit = 103,
141
  Feature_UseIncDecBit = 19,
142
  Feature_NoSSE41_Or_OptForSizeBit = 41,
143
  Feature_CallImmAddrBit = 110,
144
  Feature_FavorMemIndirectCallBit = 21,
145
  Feature_HasFastSHLDRotateBit = 102,
146
  Feature_HasMFenceBit = 46,
147
  Feature_UseRetpolineIndirectCallsBit = 23,
148
  Feature_NotUseRetpolineIndirectCallsBit = 22,
149
};
150
151
PredicateBitset X86InstructionSelector::
152
12.4k
computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const {
153
12.4k
  PredicateBitset Features;
154
12.4k
  if (true)
155
12.4k
    Features[Feature_TruePredicateBit] = 1;
156
12.4k
  if (Subtarget->hasCMov())
157
10.9k
    Features[Feature_HasCMovBit] = 1;
158
12.4k
  if (!Subtarget->hasCMov())
159
1.49k
    Features[Feature_NoCMovBit] = 1;
160
12.4k
  if (Subtarget->hasMMX())
161
4.56k
    Features[Feature_HasMMXBit] = 1;
162
12.4k
  if (Subtarget->has3DNow())
163
54
    Features[Feature_Has3DNowBit] = 1;
164
12.4k
  if (Subtarget->hasSSE1())
165
10.9k
    Features[Feature_HasSSE1Bit] = 1;
166
12.4k
  if (Subtarget->hasSSE1() && 
!Subtarget->hasAVX()10.9k
)
167
7.51k
    Features[Feature_UseSSE1Bit] = 1;
168
12.4k
  if (Subtarget->hasSSE2())
169
10.8k
    Features[Feature_HasSSE2Bit] = 1;
170
12.4k
  if (Subtarget->hasSSE2() && 
!Subtarget->hasAVX()10.8k
)
171
7.45k
    Features[Feature_UseSSE2Bit] = 1;
172
12.4k
  if (Subtarget->hasSSE3())
173
6.33k
    Features[Feature_HasSSE3Bit] = 1;
174
12.4k
  if (Subtarget->hasSSE3() && 
!Subtarget->hasAVX()6.33k
)
175
2.90k
    Features[Feature_UseSSE3Bit] = 1;
176
12.4k
  if (Subtarget->hasSSSE3())
177
5.63k
    Features[Feature_HasSSSE3Bit] = 1;
178
12.4k
  if (Subtarget->hasSSSE3() && 
!Subtarget->hasAVX()5.63k
)
179
2.20k
    Features[Feature_UseSSSE3Bit] = 1;
180
12.4k
  if (Subtarget->hasSSE41() && 
!Subtarget->hasAVX()4.40k
)
181
969
    Features[Feature_UseSSE41Bit] = 1;
182
12.4k
  if (Subtarget->hasSSE42())
183
3.93k
    Features[Feature_HasSSE42Bit] = 1;
184
12.4k
  if (Subtarget->hasSSE42() && 
!Subtarget->hasAVX()3.93k
)
185
492
    Features[Feature_UseSSE42Bit] = 1;
186
12.4k
  if (Subtarget->hasSSE4A())
187
318
    Features[Feature_HasSSE4ABit] = 1;
188
12.4k
  if (!Subtarget->hasAVX())
189
9.05k
    Features[Feature_NoAVXBit] = 1;
190
12.4k
  if (Subtarget->hasAVX())
191
3.43k
    Features[Feature_HasAVXBit] = 1;
192
12.4k
  if (Subtarget->hasAVX2())
193
2.42k
    Features[Feature_HasAVX2Bit] = 1;
194
12.4k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX2()3.43k
)
195
1.01k
    Features[Feature_HasAVX1OnlyBit] = 1;
196
12.4k
  if (Subtarget->hasAVX512())
197
1.24k
    Features[Feature_HasAVX512Bit] = 1;
198
12.4k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX512()3.43k
)
199
2.19k
    Features[Feature_UseAVXBit] = 1;
200
12.4k
  if (Subtarget->hasAVX2() && 
!Subtarget->hasAVX512()2.42k
)
201
1.18k
    Features[Feature_UseAVX2Bit] = 1;
202
12.4k
  if (!Subtarget->hasAVX512())
203
11.2k
    Features[Feature_NoAVX512Bit] = 1;
204
12.4k
  if (Subtarget->hasCDI())
205
273
    Features[Feature_HasCDIBit] = 1;
206
12.4k
  if (Subtarget->hasVPOPCNTDQ())
207
31
    Features[Feature_HasVPOPCNTDQBit] = 1;
208
12.4k
  if (Subtarget->hasERI())
209
97
    Features[Feature_HasERIBit] = 1;
210
12.4k
  if (Subtarget->hasDQI())
211
369
    Features[Feature_HasDQIBit] = 1;
212
12.4k
  if (!Subtarget->hasDQI())
213
12.1k
    Features[Feature_NoDQIBit] = 1;
214
12.4k
  if (Subtarget->hasBWI())
215
583
    Features[Feature_HasBWIBit] = 1;
216
12.4k
  if (!Subtarget->hasBWI())
217
11.9k
    Features[Feature_NoBWIBit] = 1;
218
12.4k
  if (Subtarget->hasVLX())
219
610
    Features[Feature_HasVLXBit] = 1;
220
12.4k
  if (!Subtarget->hasVLX())
221
11.8k
    Features[Feature_NoVLXBit] = 1;
222
12.4k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasBWI()610
)
223
12.1k
    Features[Feature_NoVLX_Or_NoBWIBit] = 1;
224
12.4k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasDQI()610
)
225
12.1k
    Features[Feature_NoVLX_Or_NoDQIBit] = 1;
226
12.4k
  if (Subtarget->hasVNNI())
227
18
    Features[Feature_HasVNNIBit] = 1;
228
12.4k
  if (Subtarget->hasBITALG())
229
21
    Features[Feature_HasBITALGBit] = 1;
230
12.4k
  if (Subtarget->hasPOPCNT())
231
1.84k
    Features[Feature_HasPOPCNTBit] = 1;
232
12.4k
  if (Subtarget->hasAES())
233
489
    Features[Feature_HasAESBit] = 1;
234
12.4k
  if (Subtarget->hasVAES())
235
13
    Features[Feature_HasVAESBit] = 1;
236
12.4k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVAES()610
)
237
12.4k
    Features[Feature_NoVLX_Or_NoVAESBit] = 1;
238
12.4k
  if (Subtarget->hasFXSR())
239
4.14k
    Features[Feature_HasFXSRBit] = 1;
240
12.4k
  if (Subtarget->hasXSAVE())
241
1.52k
    Features[Feature_HasXSAVEBit] = 1;
242
12.4k
  if (Subtarget->hasXSAVEOPT())
243
1.45k
    Features[Feature_HasXSAVEOPTBit] = 1;
244
12.4k
  if (Subtarget->hasXSAVEC())
245
299
    Features[Feature_HasXSAVECBit] = 1;
246
12.4k
  if (Subtarget->hasXSAVES())
247
299
    Features[Feature_HasXSAVESBit] = 1;
248
12.4k
  if (Subtarget->hasPCLMUL())
249
1.07k
    Features[Feature_HasPCLMULBit] = 1;
250
12.4k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVPCLMULQDQ()610
)
251
12.4k
    Features[Feature_NoVLX_Or_NoVPCLMULQDQBit] = 1;
252
12.4k
  if (Subtarget->hasVPCLMULQDQ())
253
18
    Features[Feature_HasVPCLMULQDQBit] = 1;
254
12.4k
  if (Subtarget->hasGFNI())
255
15
    Features[Feature_HasGFNIBit] = 1;
256
12.4k
  if (Subtarget->hasFMA())
257
2.13k
    Features[Feature_HasFMABit] = 1;
258
12.4k
  if (Subtarget->hasFMA4())
259
165
    Features[Feature_HasFMA4Bit] = 1;
260
12.4k
  if (!Subtarget->hasFMA4())
261
12.3k
    Features[Feature_NoFMA4Bit] = 1;
262
12.4k
  if (Subtarget->hasXOP())
263
144
    Features[Feature_HasXOPBit] = 1;
264
12.4k
  if (Subtarget->hasTBM())
265
87
    Features[Feature_HasTBMBit] = 1;
266
12.4k
  if (!Subtarget->hasTBM())
267
12.4k
    Features[Feature_NoTBMBit] = 1;
268
12.4k
  if (Subtarget->hasLWP())
269
90
    Features[Feature_HasLWPBit] = 1;
270
12.4k
  if (Subtarget->hasMOVBE())
271
1.30k
    Features[Feature_HasMOVBEBit] = 1;
272
12.4k
  if (Subtarget->hasRDRAND())
273
706
    Features[Feature_HasRDRANDBit] = 1;
274
12.4k
  if (Subtarget->hasF16C())
275
2.21k
    Features[Feature_HasF16CBit] = 1;
276
12.4k
  if (Subtarget->hasFSGSBase())
277
665
    Features[Feature_HasFSGSBaseBit] = 1;
278
12.4k
  if (Subtarget->hasLZCNT())
279
1.24k
    Features[Feature_HasLZCNTBit] = 1;
280
12.4k
  if (Subtarget->hasBMI())
281
1.27k
    Features[Feature_HasBMIBit] = 1;
282
12.4k
  if (Subtarget->hasBMI2())
283
1.12k
    Features[Feature_HasBMI2Bit] = 1;
284
12.4k
  if (!Subtarget->hasBMI2())
285
11.3k
    Features[Feature_NoBMI2Bit] = 1;
286
12.4k
  if (Subtarget->hasVBMI())
287
49
    Features[Feature_HasVBMIBit] = 1;
288
12.4k
  if (Subtarget->hasVBMI2())
289
22
    Features[Feature_HasVBMI2Bit] = 1;
290
12.4k
  if (Subtarget->hasIFMA())
291
27
    Features[Feature_HasIFMABit] = 1;
292
12.4k
  if (Subtarget->hasRTM())
293
222
    Features[Feature_HasRTMBit] = 1;
294
12.4k
  if (Subtarget->hasSHA())
295
103
    Features[Feature_HasSHABit] = 1;
296
12.4k
  if (Subtarget->hasRDSEED())
297
437
    Features[Feature_HasRDSEEDBit] = 1;
298
12.4k
  if (Subtarget->hasSSEPrefetch())
299
10.9k
    Features[Feature_HasSSEPrefetchBit] = 1;
300
12.4k
  if (!Subtarget->hasSSEPrefetch())
301
1.54k
    Features[Feature_NoSSEPrefetchBit] = 1;
302
12.4k
  if (Subtarget->hasPRFCHW())
303
668
    Features[Feature_HasPrefetchWBit] = 1;
304
12.4k
  if (Subtarget->hasPREFETCHWT1())
305
98
    Features[Feature_HasPREFETCHWT1Bit] = 1;
306
12.4k
  if (Subtarget->hasLAHFSAHF())
307
6.07k
    Features[Feature_HasLAHFSAHFBit] = 1;
308
12.4k
  if (Subtarget->hasMWAITX())
309
69
    Features[Feature_HasMWAITXBit] = 1;
310
12.4k
  if (Subtarget->hasCLZERO())
311
50
    Features[Feature_HasCLZEROBit] = 1;
312
12.4k
  if (Subtarget->hasCLDEMOTE())
313
3
    Features[Feature_HasCLDEMOTEBit] = 1;
314
12.4k
  if (Subtarget->hasMOVDIRI())
315
4
    Features[Feature_HasMOVDIRIBit] = 1;
316
12.4k
  if (Subtarget->hasMOVDIR64B())
317
3
    Features[Feature_HasMOVDIR64BBit] = 1;
318
12.4k
  if (Subtarget->hasPTWRITE())
319
6
    Features[Feature_HasPTWRITEBit] = 1;
320
12.4k
  if (!Subtarget->hasSSE1())
321
1.54k
    Features[Feature_FPStackf32Bit] = 1;
322
12.4k
  if (!Subtarget->hasSSE2())
323
1.60k
    Features[Feature_FPStackf64Bit] = 1;
324
12.4k
  if (Subtarget->hasCLFLUSHOPT())
325
300
    Features[Feature_HasCLFLUSHOPTBit] = 1;
326
12.4k
  if (Subtarget->hasCLWB())
327
158
    Features[Feature_HasCLWBBit] = 1;
328
12.4k
  if (Subtarget->hasWBNOINVD())
329
7
    Features[Feature_HasWBNOINVDBit] = 1;
330
12.4k
  if (Subtarget->hasRDPID())
331
16
    Features[Feature_HasRDPIDBit] = 1;
332
12.4k
  if (Subtarget->hasWAITPKG())
333
3
    Features[Feature_HasWAITPKGBit] = 1;
334
12.4k
  if (Subtarget->hasINVPCID())
335
930
    Features[Feature_HasINVPCIDBit] = 1;
336
12.4k
  if (Subtarget->hasCmpxchg16b())
337
3.82k
    Features[Feature_HasCmpxchg16bBit] = 1;
338
12.4k
  if (!Subtarget->is64Bit())
339
3.10k
    Features[Feature_Not64BitModeBit] = 1;
340
12.4k
  if (Subtarget->is64Bit())
341
9.38k
    Features[Feature_In64BitModeBit] = 1;
342
12.4k
  if (Subtarget->isTarget64BitLP64())
343
9.32k
    Features[Feature_IsLP64Bit] = 1;
344
12.4k
  if (!Subtarget->isTarget64BitLP64())
345
3.17k
    Features[Feature_NotLP64Bit] = 1;
346
12.4k
  if (Subtarget->isTargetPS4())
347
32
    Features[Feature_IsPS4Bit] = 1;
348
12.4k
  if (!Subtarget->isTargetPS4())
349
12.4k
    Features[Feature_NotPS4Bit] = 1;
350
12.4k
  if (TM.getCodeModel() == CodeModel::Kernel)
351
4
    Features[Feature_KernelCodeBit] = 1;
352
12.4k
  if (TM.getCodeModel() == CodeModel::Small ||
TM.getCodeModel() == CodeModel::Kernel238
)
353
12.2k
    Features[Feature_NearDataBit] = 1;
354
12.4k
  if (!TM.isPositionIndependent())
355
7.36k
    Features[Feature_IsNotPICBit] = 1;
356
12.4k
  if (Subtarget->isLegalToCallImmediateAddr())
357
1.77k
    Features[Feature_CallImmAddrBit] = 1;
358
12.4k
  if (!Subtarget->slowTwoMemOps())
359
12.2k
    Features[Feature_FavorMemIndirectCallBit] = 1;
360
12.4k
  if (Subtarget->hasFastSHLDRotate())
361
1.25k
    Features[Feature_HasFastSHLDRotateBit] = 1;
362
12.4k
  if (Subtarget->hasMFence())
363
10.9k
    Features[Feature_HasMFenceBit] = 1;
364
12.4k
  if (Subtarget->useRetpolineIndirectCalls())
365
17
    Features[Feature_UseRetpolineIndirectCallsBit] = 1;
366
12.4k
  if (!Subtarget->useRetpolineIndirectCalls())
367
12.4k
    Features[Feature_NotUseRetpolineIndirectCallsBit] = 1;
368
12.4k
  return Features;
369
12.4k
}
370
371
PredicateBitset X86InstructionSelector::
372
2.08k
computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, const MachineFunction *MF) const {
373
2.08k
  PredicateBitset Features;
374
2.08k
  if (!Subtarget->isTargetWin64() ||
Subtarget->getFrameLowering()->hasFP(*MF)0
)
375
2.08k
    Features[Feature_NotWin64WithoutFPBit] = 1;
376
2.08k
  if (MF->getFunction().optForSize())
377
2
    Features[Feature_OptForSizeBit] = 1;
378
2.08k
  if (MF->getFunction().optForMinSize())
379
0
    Features[Feature_OptForMinSizeBit] = 1;
380
2.08k
  if (!MF->getFunction().optForSize())
381
2.08k
    Features[Feature_OptForSpeedBit] = 1;
382
2.08k
  if (!Subtarget->slowIncDec() || 
MF->getFunction().optForSize()206
)
383
1.88k
    Features[Feature_UseIncDecBit] = 1;
384
2.08k
  if (MF->getFunction().optForSize() || 
!Subtarget->hasSSE41()2.08k
)
385
1.35k
    Features[Feature_NoSSE41_Or_OptForSizeBit] = 1;
386
2.08k
  return Features;
387
2.08k
}
388
389
// LLT Objects.
390
enum {
391
  GILLT_s1,
392
  GILLT_s8,
393
  GILLT_s16,
394
  GILLT_s32,
395
  GILLT_s64,
396
  GILLT_s80,
397
  GILLT_s128,
398
  GILLT_v2s1,
399
  GILLT_v2s64,
400
  GILLT_v4s1,
401
  GILLT_v4s32,
402
  GILLT_v4s64,
403
  GILLT_v8s1,
404
  GILLT_v8s16,
405
  GILLT_v8s32,
406
  GILLT_v8s64,
407
  GILLT_v16s1,
408
  GILLT_v16s8,
409
  GILLT_v16s16,
410
  GILLT_v16s32,
411
  GILLT_v32s1,
412
  GILLT_v32s8,
413
  GILLT_v32s16,
414
  GILLT_v64s1,
415
  GILLT_v64s8,
416
};
417
const static size_t NumTypeObjects = 25;
418
const static LLT TypeObjects[] = {
419
  LLT::scalar(1),
420
  LLT::scalar(8),
421
  LLT::scalar(16),
422
  LLT::scalar(32),
423
  LLT::scalar(64),
424
  LLT::scalar(80),
425
  LLT::scalar(128),
426
  LLT::vector(2, 1),
427
  LLT::vector(2, 64),
428
  LLT::vector(4, 1),
429
  LLT::vector(4, 32),
430
  LLT::vector(4, 64),
431
  LLT::vector(8, 1),
432
  LLT::vector(8, 16),
433
  LLT::vector(8, 32),
434
  LLT::vector(8, 64),
435
  LLT::vector(16, 1),
436
  LLT::vector(16, 8),
437
  LLT::vector(16, 16),
438
  LLT::vector(16, 32),
439
  LLT::vector(32, 1),
440
  LLT::vector(32, 8),
441
  LLT::vector(32, 16),
442
  LLT::vector(64, 1),
443
  LLT::vector(64, 8),
444
};
445
446
// Feature bitsets.
447
enum {
448
  GIFBS_Invalid,
449
  GIFBS_FPStackf32,
450
  GIFBS_FPStackf64,
451
  GIFBS_Has3DNow,
452
  GIFBS_HasAVX,
453
  GIFBS_HasAVX1Only,
454
  GIFBS_HasAVX2,
455
  GIFBS_HasAVX512,
456
  GIFBS_HasBITALG,
457
  GIFBS_HasBMI,
458
  GIFBS_HasBMI2,
459
  GIFBS_HasBWI,
460
  GIFBS_HasCDI,
461
  GIFBS_HasDQI,
462
  GIFBS_HasLWP,
463
  GIFBS_HasMFence,
464
  GIFBS_HasMMX,
465
  GIFBS_HasMOVBE,
466
  GIFBS_HasPTWRITE,
467
  GIFBS_HasRTM,
468
  GIFBS_HasSHA,
469
  GIFBS_HasSSE1,
470
  GIFBS_HasSSE2,
471
  GIFBS_HasSSE42,
472
  GIFBS_HasSSE4A,
473
  GIFBS_HasTBM,
474
  GIFBS_HasVLX,
475
  GIFBS_HasVPOPCNTDQ,
476
  GIFBS_HasWAITPKG,
477
  GIFBS_HasWBNOINVD,
478
  GIFBS_HasXOP,
479
  GIFBS_In64BitMode,
480
  GIFBS_NoDQI,
481
  GIFBS_Not64BitMode,
482
  GIFBS_UseAVX,
483
  GIFBS_UseIncDec,
484
  GIFBS_UseSSE1,
485
  GIFBS_UseSSE2,
486
  GIFBS_UseSSE41,
487
  GIFBS_UseSSSE3,
488
  GIFBS_HasAES_HasAVX,
489
  GIFBS_HasAES_NoAVX,
490
  GIFBS_HasAVX_NoVLX,
491
  GIFBS_HasAVX_NoVLX_Or_NoBWI,
492
  GIFBS_HasAVX2_NoVLX,
493
  GIFBS_HasAVX2_NoVLX_Or_NoBWI,
494
  GIFBS_HasAVX512_HasVAES,
495
  GIFBS_HasAVX512_HasVLX,
496
  GIFBS_HasAVX512_HasVPCLMULQDQ,
497
  GIFBS_HasBITALG_HasVLX,
498
  GIFBS_HasBWI_HasVLX,
499
  GIFBS_HasCDI_HasVLX,
500
  GIFBS_HasDQI_HasVLX,
501
  GIFBS_HasDQI_NoBWI,
502
  GIFBS_HasFSGSBase_In64BitMode,
503
  GIFBS_HasPCLMUL_NoAVX,
504
  GIFBS_HasPTWRITE_In64BitMode,
505
  GIFBS_HasRDPID_Not64BitMode,
506
  GIFBS_HasSSE2_NoAVX512,
507
  GIFBS_HasVAES_HasVLX,
508
  GIFBS_HasVAES_NoVLX,
509
  GIFBS_HasVLX_HasVPCLMULQDQ,
510
  GIFBS_HasVLX_HasVPOPCNTDQ,
511
  GIFBS_HasVPCLMULQDQ_NoVLX,
512
  GIFBS_HasWAITPKG_In64BitMode,
513
  GIFBS_HasWAITPKG_Not64BitMode,
514
  GIFBS_Not64BitMode_OptForSize,
515
  GIFBS_NotWin64WithoutFP_OptForMinSize,
516
  GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES,
517
  GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ,
518
  GIFBS_HasDQI_HasVLX_NoBWI,
519
};
520
const static PredicateBitset FeatureBitsets[] {
521
  {}, // GIFBS_Invalid
522
  {Feature_FPStackf32Bit, },
523
  {Feature_FPStackf64Bit, },
524
  {Feature_Has3DNowBit, },
525
  {Feature_HasAVXBit, },
526
  {Feature_HasAVX1OnlyBit, },
527
  {Feature_HasAVX2Bit, },
528
  {Feature_HasAVX512Bit, },
529
  {Feature_HasBITALGBit, },
530
  {Feature_HasBMIBit, },
531
  {Feature_HasBMI2Bit, },
532
  {Feature_HasBWIBit, },
533
  {Feature_HasCDIBit, },
534
  {Feature_HasDQIBit, },
535
  {Feature_HasLWPBit, },
536
  {Feature_HasMFenceBit, },
537
  {Feature_HasMMXBit, },
538
  {Feature_HasMOVBEBit, },
539
  {Feature_HasPTWRITEBit, },
540
  {Feature_HasRTMBit, },
541
  {Feature_HasSHABit, },
542
  {Feature_HasSSE1Bit, },
543
  {Feature_HasSSE2Bit, },
544
  {Feature_HasSSE42Bit, },
545
  {Feature_HasSSE4ABit, },
546
  {Feature_HasTBMBit, },
547
  {Feature_HasVLXBit, },
548
  {Feature_HasVPOPCNTDQBit, },
549
  {Feature_HasWAITPKGBit, },
550
  {Feature_HasWBNOINVDBit, },
551
  {Feature_HasXOPBit, },
552
  {Feature_In64BitModeBit, },
553
  {Feature_NoDQIBit, },
554
  {Feature_Not64BitModeBit, },
555
  {Feature_UseAVXBit, },
556
  {Feature_UseIncDecBit, },
557
  {Feature_UseSSE1Bit, },
558
  {Feature_UseSSE2Bit, },
559
  {Feature_UseSSE41Bit, },
560
  {Feature_UseSSSE3Bit, },
561
  {Feature_HasAESBit, Feature_HasAVXBit, },
562
  {Feature_HasAESBit, Feature_NoAVXBit, },
563
  {Feature_HasAVXBit, Feature_NoVLXBit, },
564
  {Feature_HasAVXBit, Feature_NoVLX_Or_NoBWIBit, },
565
  {Feature_HasAVX2Bit, Feature_NoVLXBit, },
566
  {Feature_HasAVX2Bit, Feature_NoVLX_Or_NoBWIBit, },
567
  {Feature_HasAVX512Bit, Feature_HasVAESBit, },
568
  {Feature_HasAVX512Bit, Feature_HasVLXBit, },
569
  {Feature_HasAVX512Bit, Feature_HasVPCLMULQDQBit, },
570
  {Feature_HasBITALGBit, Feature_HasVLXBit, },
571
  {Feature_HasBWIBit, Feature_HasVLXBit, },
572
  {Feature_HasCDIBit, Feature_HasVLXBit, },
573
  {Feature_HasDQIBit, Feature_HasVLXBit, },
574
  {Feature_HasDQIBit, Feature_NoBWIBit, },
575
  {Feature_HasFSGSBaseBit, Feature_In64BitModeBit, },
576
  {Feature_HasPCLMULBit, Feature_NoAVXBit, },
577
  {Feature_HasPTWRITEBit, Feature_In64BitModeBit, },
578
  {Feature_HasRDPIDBit, Feature_Not64BitModeBit, },
579
  {Feature_HasSSE2Bit, Feature_NoAVX512Bit, },
580
  {Feature_HasVAESBit, Feature_HasVLXBit, },
581
  {Feature_HasVAESBit, Feature_NoVLXBit, },
582
  {Feature_HasVLXBit, Feature_HasVPCLMULQDQBit, },
583
  {Feature_HasVLXBit, Feature_HasVPOPCNTDQBit, },
584
  {Feature_HasVPCLMULQDQBit, Feature_NoVLXBit, },
585
  {Feature_HasWAITPKGBit, Feature_In64BitModeBit, },
586
  {Feature_HasWAITPKGBit, Feature_Not64BitModeBit, },
587
  {Feature_Not64BitModeBit, Feature_OptForSizeBit, },
588
  {Feature_NotWin64WithoutFPBit, Feature_OptForMinSizeBit, },
589
  {Feature_HasAESBit, Feature_HasAVXBit, Feature_NoVLX_Or_NoVAESBit, },
590
  {Feature_HasAVXBit, Feature_HasPCLMULBit, Feature_NoVLX_Or_NoVPCLMULQDQBit, },
591
  {Feature_HasDQIBit, Feature_HasVLXBit, Feature_NoBWIBit, },
592
};
593
594
// ComplexPattern predicates.
595
enum {
596
  GICP_Invalid,
597
};
598
// See constructor for table contents
599
600
// PatFrag predicates.
601
enum {
602
  GIPFP_I64_Predicate_AndMask64 = GIPFP_I64_Invalid + 1,
603
  GIPFP_I64_Predicate_BTCBTSMask64,
604
  GIPFP_I64_Predicate_BTRMask64,
605
  GIPFP_I64_Predicate_PrefetchWT1Level,
606
  GIPFP_I64_Predicate_i16immSExt8,
607
  GIPFP_I64_Predicate_i32immSExt8,
608
  GIPFP_I64_Predicate_i64immSExt32,
609
  GIPFP_I64_Predicate_i64immSExt8,
610
  GIPFP_I64_Predicate_i64immZExt32,
611
  GIPFP_I64_Predicate_i64immZExt32SExt8,
612
  GIPFP_I64_Predicate_immShift16,
613
  GIPFP_I64_Predicate_immShift32,
614
  GIPFP_I64_Predicate_immShift64,
615
  GIPFP_I64_Predicate_immShift8,
616
  GIPFP_I64_Predicate_immff00_ffff,
617
};
618
79
bool X86InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
619
79
  switch (PredicateID) {
620
79
  case GIPFP_I64_Predicate_AndMask64: {
621
0
    
622
0
  return isMask_64(Imm) && !isUInt<32>(Imm);
623
79
624
79
    
llvm_unreachable0
("ImmediateCode should have returned");
625
79
    
return false0
;
626
79
  }
627
79
  case GIPFP_I64_Predicate_BTCBTSMask64: {
628
0
    
629
0
  return !isInt<32>(Imm) && isPowerOf2_64(Imm);
630
79
631
79
    
llvm_unreachable0
("ImmediateCode should have returned");
632
79
    
return false0
;
633
79
  }
634
79
  case GIPFP_I64_Predicate_BTRMask64: {
635
0
    
636
0
  return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);
637
79
638
79
    
llvm_unreachable0
("ImmediateCode should have returned");
639
79
    
return false0
;
640
79
  }
641
79
  case GIPFP_I64_Predicate_PrefetchWT1Level: {
642
0
    
643
0
  return Imm < 3;
644
79
645
79
    
llvm_unreachable0
("ImmediateCode should have returned");
646
79
    
return false0
;
647
79
  }
648
79
  case GIPFP_I64_Predicate_i16immSExt8: {
649
5
     return isInt<8>(Imm); 
650
79
    
llvm_unreachable0
("ImmediateCode should have returned");
651
79
    
return false0
;
652
79
  }
653
79
  case GIPFP_I64_Predicate_i32immSExt8: {
654
21
     return isInt<8>(Imm); 
655
79
    
llvm_unreachable0
("ImmediateCode should have returned");
656
79
    
return false0
;
657
79
  }
658
79
  case GIPFP_I64_Predicate_i64immSExt32: {
659
48
     return isInt<32>(Imm); 
660
79
    
llvm_unreachable0
("ImmediateCode should have returned");
661
79
    
return false0
;
662
79
  }
663
79
  case GIPFP_I64_Predicate_i64immSExt8: {
664
5
     return isInt<8>(Imm); 
665
79
    
llvm_unreachable0
("ImmediateCode should have returned");
666
79
    
return false0
;
667
79
  }
668
79
  case GIPFP_I64_Predicate_i64immZExt32: {
669
0
     return isUInt<32>(Imm); 
670
79
    
llvm_unreachable0
("ImmediateCode should have returned");
671
79
    
return false0
;
672
79
  }
673
79
  case GIPFP_I64_Predicate_i64immZExt32SExt8: {
674
0
    
675
0
  return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
676
79
677
79
    
llvm_unreachable0
("ImmediateCode should have returned");
678
79
    
return false0
;
679
79
  }
680
79
  case GIPFP_I64_Predicate_immShift16: {
681
0
    
682
0
  return countTrailingOnes<uint64_t>(Imm) >= 4;
683
79
684
79
    
llvm_unreachable0
("ImmediateCode should have returned");
685
79
    
return false0
;
686
79
  }
687
79
  case GIPFP_I64_Predicate_immShift32: {
688
0
    
689
0
  return countTrailingOnes<uint64_t>(Imm) >= 5;
690
79
691
79
    
llvm_unreachable0
("ImmediateCode should have returned");
692
79
    
return false0
;
693
79
  }
694
79
  case GIPFP_I64_Predicate_immShift64: {
695
0
    
696
0
  return countTrailingOnes<uint64_t>(Imm) >= 6;
697
79
698
79
    
llvm_unreachable0
("ImmediateCode should have returned");
699
79
    
return false0
;
700
79
  }
701
79
  case GIPFP_I64_Predicate_immShift8: {
702
0
    
703
0
  return countTrailingOnes<uint64_t>(Imm) >= 3;
704
79
705
79
    
llvm_unreachable0
("ImmediateCode should have returned");
706
79
    
return false0
;
707
79
  }
708
79
  case GIPFP_I64_Predicate_immff00_ffff: {
709
0
    
710
0
  return Imm >= 0xff00 && Imm <= 0xffff;
711
79
712
79
    
llvm_unreachable0
("ImmediateCode should have returned");
713
79
    
return false0
;
714
0
  }
715
0
  }
716
0
  llvm_unreachable("Unknown predicate");
717
0
  return false;
718
0
}
719
// PatFrag predicates.
720
enum {
721
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
722
  GIPFP_APFloat_Predicate_fpimm1,
723
  GIPFP_APFloat_Predicate_fpimmneg0,
724
  GIPFP_APFloat_Predicate_fpimmneg1,
725
};
726
5
bool X86InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
727
5
  switch (PredicateID) {
728
5
  case GIPFP_APFloat_Predicate_fpimm0: {
729
5
    
730
5
  return Imm.isExactlyValue(+0.0);
731
5
732
5
    
llvm_unreachable0
("ImmediateCode should have returned");
733
5
    
return false0
;
734
5
  }
735
5
  case GIPFP_APFloat_Predicate_fpimm1: {
736
0
    
737
0
  return Imm.isExactlyValue(+1.0);
738
5
739
5
    
llvm_unreachable0
("ImmediateCode should have returned");
740
5
    
return false0
;
741
5
  }
742
5
  case GIPFP_APFloat_Predicate_fpimmneg0: {
743
0
    
744
0
  return Imm.isExactlyValue(-0.0);
745
5
746
5
    
llvm_unreachable0
("ImmediateCode should have returned");
747
5
    
return false0
;
748
5
  }
749
5
  case GIPFP_APFloat_Predicate_fpimmneg1: {
750
0
    
751
0
  return Imm.isExactlyValue(-1.0);
752
5
753
5
    
llvm_unreachable0
("ImmediateCode should have returned");
754
5
    
return false0
;
755
0
  }
756
0
  }
757
0
  llvm_unreachable("Unknown predicate");
758
0
  return false;
759
0
}
760
0
bool X86InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
761
0
  llvm_unreachable("Unknown predicate");
762
0
  return false;
763
0
}
764
0
bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
765
0
  const MachineFunction &MF = *MI.getParent()->getParent();
766
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
767
0
  (void)MRI;
768
0
  llvm_unreachable("Unknown predicate");
769
0
  return false;
770
0
}
771
772
X86InstructionSelector::ComplexMatcherMemFn
773
X86InstructionSelector::ComplexPredicateFns[] = {
774
  nullptr, // GICP_Invalid
775
};
776
777
// Custom renderers.
778
enum {
779
  GICR_Invalid,
780
};
781
X86InstructionSelector::CustomRendererFn
782
X86InstructionSelector::CustomRenderers[] = {
783
  nullptr, // GICP_Invalid
784
};
785
786
2.08k
bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
787
2.08k
  MachineFunction &MF = *I.getParent()->getParent();
788
2.08k
  MachineRegisterInfo &MRI = MF.getRegInfo();
789
2.08k
  // FIXME: This should be computed on a per-function basis rather than per-insn.
790
2.08k
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
791
2.08k
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
792
2.08k
  NewMIVector OutMIs;
793
2.08k
  State.MIs.clear();
794
2.08k
  State.MIs.push_back(&I);
795
2.08k
796
2.08k
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
797
757
    return true;
798
757
  }
799
1.33k
800
1.33k
  return false;
801
1.33k
}
802
803
2.08k
const int64_t *X86InstructionSelector::getMatchTable() const {
804
2.08k
  constexpr static int64_t MatchTable0[] = {
805
2.08k
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 34*/ 29511,
806
2.08k
    /*TargetOpcode::G_ADD*//*Label 0*/ 106,
807
2.08k
    /*TargetOpcode::G_SUB*//*Label 1*/ 1723,
808
2.08k
    /*TargetOpcode::G_MUL*//*Label 2*/ 2804, 0, 0, 0, 0,
809
2.08k
    /*TargetOpcode::G_AND*//*Label 3*/ 3570,
810
2.08k
    /*TargetOpcode::G_OR*//*Label 4*/ 6682,
811
2.08k
    /*TargetOpcode::G_XOR*//*Label 5*/ 9353, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
812
2.08k
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 11326, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
813
2.08k
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 11726,
814
2.08k
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 18309,
815
2.08k
    /*TargetOpcode::G_ANYEXT*//*Label 9*/ 19740,
816
2.08k
    /*TargetOpcode::G_TRUNC*//*Label 10*/ 19856,
817
2.08k
    /*TargetOpcode::G_CONSTANT*//*Label 11*/ 20191,
818
2.08k
    /*TargetOpcode::G_FCONSTANT*//*Label 12*/ 20394, 0, 0,
819
2.08k
    /*TargetOpcode::G_SEXT*//*Label 13*/ 20587,
820
2.08k
    /*TargetOpcode::G_ZEXT*//*Label 14*/ 21130,
821
2.08k
    /*TargetOpcode::G_SHL*//*Label 15*/ 21265,
822
2.08k
    /*TargetOpcode::G_LSHR*//*Label 16*/ 21990,
823
2.08k
    /*TargetOpcode::G_ASHR*//*Label 17*/ 22821, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
824
2.08k
    /*TargetOpcode::G_FADD*//*Label 18*/ 23478,
825
2.08k
    /*TargetOpcode::G_FSUB*//*Label 19*/ 24091,
826
2.08k
    /*TargetOpcode::G_FMUL*//*Label 20*/ 24704, 0,
827
2.08k
    /*TargetOpcode::G_FDIV*//*Label 21*/ 25317, 0, 0, 0, 0, 0, 0,
828
2.08k
    /*TargetOpcode::G_FNEG*//*Label 22*/ 25930,
829
2.08k
    /*TargetOpcode::G_FPEXT*//*Label 23*/ 26019,
830
2.08k
    /*TargetOpcode::G_FPTRUNC*//*Label 24*/ 26295,
831
2.08k
    /*TargetOpcode::G_FPTOSI*//*Label 25*/ 26580,
832
2.08k
    /*TargetOpcode::G_FPTOUI*//*Label 26*/ 27210,
833
2.08k
    /*TargetOpcode::G_SITOFP*//*Label 27*/ 27564,
834
2.08k
    /*TargetOpcode::G_UITOFP*//*Label 28*/ 28394, 0, 0, 0,
835
2.08k
    /*TargetOpcode::G_BR*//*Label 29*/ 28848, 0, 0, 0, 0,
836
2.08k
    /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 30*/ 28861,
837
2.08k
    /*TargetOpcode::G_CTLZ*//*Label 31*/ 28946, 0,
838
2.08k
    /*TargetOpcode::G_CTPOP*//*Label 32*/ 29109,
839
2.08k
    /*TargetOpcode::G_BSWAP*//*Label 33*/ 29421,
840
2.08k
    // Label 0: @106
841
2.08k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 51*/ 1722,
842
2.08k
    /*GILLT_s8*//*Label 35*/ 136,
843
2.08k
    /*GILLT_s16*//*Label 36*/ 250,
844
2.08k
    /*GILLT_s32*//*Label 37*/ 422,
845
2.08k
    /*GILLT_s64*//*Label 38*/ 594, 0, 0, 0,
846
2.08k
    /*GILLT_v2s64*//*Label 39*/ 794, 0,
847
2.08k
    /*GILLT_v4s32*//*Label 40*/ 875,
848
2.08k
    /*GILLT_v4s64*//*Label 41*/ 1078, 0,
849
2.08k
    /*GILLT_v8s16*//*Label 42*/ 1136,
850
2.08k
    /*GILLT_v8s32*//*Label 43*/ 1339,
851
2.08k
    /*GILLT_v8s64*//*Label 44*/ 1397, 0,
852
2.08k
    /*GILLT_v16s8*//*Label 45*/ 1429,
853
2.08k
    /*GILLT_v16s16*//*Label 46*/ 1510,
854
2.08k
    /*GILLT_v16s32*//*Label 47*/ 1568, 0,
855
2.08k
    /*GILLT_v32s8*//*Label 48*/ 1600,
856
2.08k
    /*GILLT_v32s16*//*Label 49*/ 1658, 0,
857
2.08k
    /*GILLT_v64s8*//*Label 50*/ 1690,
858
2.08k
    // Label 35: @136
859
2.08k
    GIM_Try, /*On fail goto*//*Label 52*/ 249,
860
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
861
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
862
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
863
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
864
2.08k
      GIM_Try, /*On fail goto*//*Label 53*/ 178, // Rule ID 16142 //
865
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
866
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
867
2.08k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, 1:{ *:[i8] })  =>  (INC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
868
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r,
869
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
870
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
871
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
872
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
873
2.08k
        // GIR_Coverage, 16142,
874
2.08k
        GIR_Done,
875
2.08k
      // Label 53: @178
876
2.08k
      GIM_Try, /*On fail goto*//*Label 54*/ 202, // Rule ID 16146 //
877
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
878
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
879
2.08k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, -1:{ *:[i8] })  =>  (DEC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
880
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r,
881
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
882
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
883
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
884
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885
2.08k
        // GIR_Coverage, 16146,
886
2.08k
        GIR_Done,
887
2.08k
      // Label 54: @202
888
2.08k
      GIM_Try, /*On fail goto*//*Label 55*/ 232, // Rule ID 16096 //
889
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
890
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
891
2.08k
        // MIs[1] Operand 1
892
2.08k
        // No operand predicates
893
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
894
2.08k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
895
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri,
896
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
897
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
898
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
899
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
900
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
901
2.08k
        // GIR_Coverage, 16096,
902
2.08k
        GIR_Done,
903
2.08k
      // Label 55: @232
904
2.08k
      GIM_Try, /*On fail goto*//*Label 56*/ 248, // Rule ID 16088 //
905
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
906
2.08k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
907
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD8rr,
908
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
909
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
910
2.08k
        // GIR_Coverage, 16088,
911
2.08k
        GIR_Done,
912
2.08k
      // Label 56: @248
913
2.08k
      GIM_Reject,
914
2.08k
    // Label 52: @249
915
2.08k
    GIM_Reject,
916
2.08k
    // Label 36: @250
917
2.08k
    GIM_Try, /*On fail goto*//*Label 57*/ 421,
918
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
919
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
920
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
921
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
922
2.08k
      GIM_Try, /*On fail goto*//*Label 58*/ 293, // Rule ID 15954 //
923
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
924
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, 128:{ *:[i16] })  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -128:{ *:[i16] })
925
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
926
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
927
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
928
2.08k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
929
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
930
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
931
2.08k
        // GIR_Coverage, 15954,
932
2.08k
        GIR_Done,
933
2.08k
      // Label 58: @293
934
2.08k
      GIM_Try, /*On fail goto*//*Label 59*/ 317, // Rule ID 16143 //
935
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
936
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
937
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, 1:{ *:[i16] })  =>  (INC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
938
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r,
939
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
940
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
941
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
942
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
943
2.08k
        // GIR_Coverage, 16143,
944
2.08k
        GIR_Done,
945
2.08k
      // Label 59: @317
946
2.08k
      GIM_Try, /*On fail goto*//*Label 60*/ 341, // Rule ID 16147 //
947
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
948
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
949
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, -1:{ *:[i16] })  =>  (DEC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
950
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r,
951
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
952
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
953
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
954
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
955
2.08k
        // GIR_Coverage, 16147,
956
2.08k
        GIR_Done,
957
2.08k
      // Label 60: @341
958
2.08k
      GIM_Try, /*On fail goto*//*Label 61*/ 374, // Rule ID 16099 //
959
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
960
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
961
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
962
2.08k
        // MIs[1] Operand 1
963
2.08k
        // No operand predicates
964
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
965
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (ADD16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
966
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8,
967
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
968
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
969
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
970
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
971
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
972
2.08k
        // GIR_Coverage, 16099,
973
2.08k
        GIR_Done,
974
2.08k
      // Label 61: @374
975
2.08k
      GIM_Try, /*On fail goto*//*Label 62*/ 404, // Rule ID 16097 //
976
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
977
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
978
2.08k
        // MIs[1] Operand 1
979
2.08k
        // No operand predicates
980
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
981
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
982
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri,
983
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
984
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
985
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
986
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
987
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
988
2.08k
        // GIR_Coverage, 16097,
989
2.08k
        GIR_Done,
990
2.08k
      // Label 62: @404
991
2.08k
      GIM_Try, /*On fail goto*//*Label 63*/ 420, // Rule ID 16089 //
992
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
993
2.08k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
994
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD16rr,
995
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
996
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
997
2.08k
        // GIR_Coverage, 16089,
998
2.08k
        GIR_Done,
999
2.08k
      // Label 63: @420
1000
2.08k
      GIM_Reject,
1001
2.08k
    // Label 57: @421
1002
2.08k
    GIM_Reject,
1003
2.08k
    // Label 37: @422
1004
2.08k
    GIM_Try, /*On fail goto*//*Label 64*/ 593,
1005
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1006
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1007
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
1008
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
1009
2.08k
      GIM_Try, /*On fail goto*//*Label 65*/ 465, // Rule ID 15956 //
1010
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
1011
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, 128:{ *:[i32] })  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -128:{ *:[i32] })
1012
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1013
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1014
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1015
2.08k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
1016
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1017
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1018
2.08k
        // GIR_Coverage, 15956,
1019
2.08k
        GIR_Done,
1020
2.08k
      // Label 65: @465
1021
2.08k
      GIM_Try, /*On fail goto*//*Label 66*/ 489, // Rule ID 16144 //
1022
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1023
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1024
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (INC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1025
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r,
1026
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1027
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1028
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1029
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1030
2.08k
        // GIR_Coverage, 16144,
1031
2.08k
        GIR_Done,
1032
2.08k
      // Label 66: @489
1033
2.08k
      GIM_Try, /*On fail goto*//*Label 67*/ 513, // Rule ID 16148 //
1034
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1035
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1036
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })  =>  (DEC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1037
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r,
1038
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1039
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1040
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1041
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1042
2.08k
        // GIR_Coverage, 16148,
1043
2.08k
        GIR_Done,
1044
2.08k
      // Label 67: @513
1045
2.08k
      GIM_Try, /*On fail goto*//*Label 68*/ 546, // Rule ID 16100 //
1046
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1047
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1048
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1049
2.08k
        // MIs[1] Operand 1
1050
2.08k
        // No operand predicates
1051
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1052
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (ADD32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1053
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8,
1054
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1055
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1056
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1057
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1058
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1059
2.08k
        // GIR_Coverage, 16100,
1060
2.08k
        GIR_Done,
1061
2.08k
      // Label 68: @546
1062
2.08k
      GIM_Try, /*On fail goto*//*Label 69*/ 576, // Rule ID 16098 //
1063
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1064
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1065
2.08k
        // MIs[1] Operand 1
1066
2.08k
        // No operand predicates
1067
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1068
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1069
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri,
1070
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1071
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1072
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1073
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1074
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1075
2.08k
        // GIR_Coverage, 16098,
1076
2.08k
        GIR_Done,
1077
2.08k
      // Label 69: @576
1078
2.08k
      GIM_Try, /*On fail goto*//*Label 70*/ 592, // Rule ID 16090 //
1079
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1080
2.08k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1081
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD32rr,
1082
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1083
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1084
2.08k
        // GIR_Coverage, 16090,
1085
2.08k
        GIR_Done,
1086
2.08k
      // Label 70: @592
1087
2.08k
      GIM_Reject,
1088
2.08k
    // Label 64: @593
1089
2.08k
    GIM_Reject,
1090
2.08k
    // Label 38: @594
1091
2.08k
    GIM_Try, /*On fail goto*//*Label 71*/ 793,
1092
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1093
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1094
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1095
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1096
2.08k
      GIM_Try, /*On fail goto*//*Label 72*/ 637, // Rule ID 15958 //
1097
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
1098
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 128:{ *:[i64] })  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -128:{ *:[i64] })
1099
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1100
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1101
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1102
2.08k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
1103
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1104
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1105
2.08k
        // GIR_Coverage, 15958,
1106
2.08k
        GIR_Done,
1107
2.08k
      // Label 72: @637
1108
2.08k
      GIM_Try, /*On fail goto*//*Label 73*/ 662, // Rule ID 15960 //
1109
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 2147483648,
1110
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 2147483648:{ *:[i64] })  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -2147483648:{ *:[i64] })
1111
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1112
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1113
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1114
2.08k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648,
1115
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1116
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1117
2.08k
        // GIR_Coverage, 15960,
1118
2.08k
        GIR_Done,
1119
2.08k
      // Label 73: @662
1120
2.08k
      GIM_Try, /*On fail goto*//*Label 74*/ 686, // Rule ID 16145 //
1121
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1122
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1123
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })  =>  (INC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1124
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r,
1125
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1126
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1127
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1128
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1129
2.08k
        // GIR_Coverage, 16145,
1130
2.08k
        GIR_Done,
1131
2.08k
      // Label 74: @686
1132
2.08k
      GIM_Try, /*On fail goto*//*Label 75*/ 710, // Rule ID 16149 //
1133
2.08k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1134
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1135
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })  =>  (DEC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1136
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r,
1137
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1138
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1139
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1140
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1141
2.08k
        // GIR_Coverage, 16149,
1142
2.08k
        GIR_Done,
1143
2.08k
      // Label 75: @710
1144
2.08k
      GIM_Try, /*On fail goto*//*Label 76*/ 743, // Rule ID 16101 //
1145
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1146
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1147
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1148
2.08k
        // MIs[1] Operand 1
1149
2.08k
        // No operand predicates
1150
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1151
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (ADD64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1152
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8,
1153
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1154
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1155
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1156
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1157
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1158
2.08k
        // GIR_Coverage, 16101,
1159
2.08k
        GIR_Done,
1160
2.08k
      // Label 76: @743
1161
2.08k
      GIM_Try, /*On fail goto*//*Label 77*/ 776, // Rule ID 16102 //
1162
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1163
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1164
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1165
2.08k
        // MIs[1] Operand 1
1166
2.08k
        // No operand predicates
1167
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1168
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (ADD64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1169
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32,
1170
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1171
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1172
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1173
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1174
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1175
2.08k
        // GIR_Coverage, 16102,
1176
2.08k
        GIR_Done,
1177
2.08k
      // Label 77: @776
1178
2.08k
      GIM_Try, /*On fail goto*//*Label 78*/ 792, // Rule ID 16091 //
1179
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1180
2.08k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1181
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr,
1182
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1183
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1184
2.08k
        // GIR_Coverage, 16091,
1185
2.08k
        GIR_Done,
1186
2.08k
      // Label 78: @792
1187
2.08k
      GIM_Reject,
1188
2.08k
    // Label 71: @793
1189
2.08k
    GIM_Reject,
1190
2.08k
    // Label 39: @794
1191
2.08k
    GIM_Try, /*On fail goto*//*Label 79*/ 874,
1192
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1193
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1194
2.08k
      GIM_Try, /*On fail goto*//*Label 80*/ 827, // Rule ID 1819 //
1195
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1196
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1197
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1198
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1199
2.08k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1200
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQrr,
1201
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1202
2.08k
        // GIR_Coverage, 1819,
1203
2.08k
        GIR_Done,
1204
2.08k
      // Label 80: @827
1205
2.08k
      GIM_Try, /*On fail goto*//*Label 81*/ 850, // Rule ID 1821 //
1206
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1207
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1208
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1209
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1210
2.08k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1211
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDQrr,
1212
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1213
2.08k
        // GIR_Coverage, 1821,
1214
2.08k
        GIR_Done,
1215
2.08k
      // Label 81: @850
1216
2.08k
      GIM_Try, /*On fail goto*//*Label 82*/ 873, // Rule ID 3833 //
1217
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1218
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1219
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1220
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1221
2.08k
        // (add:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPADDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1222
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ128rr,
1223
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1224
2.08k
        // GIR_Coverage, 3833,
1225
2.08k
        GIR_Done,
1226
2.08k
      // Label 82: @873
1227
2.08k
      GIM_Reject,
1228
2.08k
    // Label 79: @874
1229
2.08k
    GIM_Reject,
1230
2.08k
    // Label 40: @875
1231
2.08k
    GIM_Try, /*On fail goto*//*Label 83*/ 1077,
1232
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1233
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1234
2.08k
      GIM_Try, /*On fail goto*//*Label 84*/ 946, // Rule ID 12364 //
1235
2.08k
        GIM_CheckFeatures, GIFBS_HasXOP,
1236
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1237
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1238
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1239
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1240
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1241
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1242
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1243
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1244
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1245
2.08k
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3)  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1246
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1247
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1248
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1249
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1250
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1251
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1252
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1253
2.08k
        // GIR_Coverage, 12364,
1254
2.08k
        GIR_Done,
1255
2.08k
      // Label 84: @946
1256
2.08k
      GIM_Try, /*On fail goto*//*Label 85*/ 1007, // Rule ID 18207 //
1257
2.08k
        GIM_CheckFeatures, GIFBS_HasXOP,
1258
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1259
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1260
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1261
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1262
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1263
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1264
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1265
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1266
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1267
2.08k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2))  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1268
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1269
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1270
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1271
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1272
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1273
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1274
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1275
2.08k
        // GIR_Coverage, 18207,
1276
2.08k
        GIR_Done,
1277
2.08k
      // Label 85: @1007
1278
2.08k
      GIM_Try, /*On fail goto*//*Label 86*/ 1030, // Rule ID 1813 //
1279
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1280
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1281
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1282
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1283
2.08k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1284
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDrr,
1285
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1286
2.08k
        // GIR_Coverage, 1813,
1287
2.08k
        GIR_Done,
1288
2.08k
      // Label 86: @1030
1289
2.08k
      GIM_Try, /*On fail goto*//*Label 87*/ 1053, // Rule ID 1815 //
1290
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1291
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1292
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1293
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1294
2.08k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1295
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDDrr,
1296
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1297
2.08k
        // GIR_Coverage, 1815,
1298
2.08k
        GIR_Done,
1299
2.08k
      // Label 87: @1053
1300
2.08k
      GIM_Try, /*On fail goto*//*Label 88*/ 1076, // Rule ID 3860 //
1301
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1302
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1303
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1304
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1305
2.08k
        // (add:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPADDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1306
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ128rr,
1307
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1308
2.08k
        // GIR_Coverage, 3860,
1309
2.08k
        GIR_Done,
1310
2.08k
      // Label 88: @1076
1311
2.08k
      GIM_Reject,
1312
2.08k
    // Label 83: @1077
1313
2.08k
    GIM_Reject,
1314
2.08k
    // Label 41: @1078
1315
2.08k
    GIM_Try, /*On fail goto*//*Label 89*/ 1135,
1316
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1317
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1318
2.08k
      GIM_Try, /*On fail goto*//*Label 90*/ 1111, // Rule ID 1823 //
1319
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1320
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1321
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1322
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1323
2.08k
        // (add:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPADDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1324
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQYrr,
1325
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1326
2.08k
        // GIR_Coverage, 1823,
1327
2.08k
        GIR_Done,
1328
2.08k
      // Label 90: @1111
1329
2.08k
      GIM_Try, /*On fail goto*//*Label 91*/ 1134, // Rule ID 3824 //
1330
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1331
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1332
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1333
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1334
2.08k
        // (add:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPADDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1335
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ256rr,
1336
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1337
2.08k
        // GIR_Coverage, 3824,
1338
2.08k
        GIR_Done,
1339
2.08k
      // Label 91: @1134
1340
2.08k
      GIM_Reject,
1341
2.08k
    // Label 89: @1135
1342
2.08k
    GIM_Reject,
1343
2.08k
    // Label 42: @1136
1344
2.08k
    GIM_Try, /*On fail goto*//*Label 92*/ 1338,
1345
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1346
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1347
2.08k
      GIM_Try, /*On fail goto*//*Label 93*/ 1207, // Rule ID 12363 //
1348
2.08k
        GIM_CheckFeatures, GIFBS_HasXOP,
1349
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1350
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1351
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1352
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1353
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1354
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1355
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1356
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1357
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1358
2.08k
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3)  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1359
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1360
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1361
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1362
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1363
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1364
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1365
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1366
2.08k
        // GIR_Coverage, 12363,
1367
2.08k
        GIR_Done,
1368
2.08k
      // Label 93: @1207
1369
2.08k
      GIM_Try, /*On fail goto*//*Label 94*/ 1268, // Rule ID 18206 //
1370
2.08k
        GIM_CheckFeatures, GIFBS_HasXOP,
1371
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1372
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1373
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1374
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1375
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1376
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1377
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1378
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1379
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1380
2.08k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2))  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1381
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1382
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1383
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1384
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1385
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1386
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1387
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1388
2.08k
        // GIR_Coverage, 18206,
1389
2.08k
        GIR_Done,
1390
2.08k
      // Label 94: @1268
1391
2.08k
      GIM_Try, /*On fail goto*//*Label 95*/ 1291, // Rule ID 1807 //
1392
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1393
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1394
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1395
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1396
2.08k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1397
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWrr,
1398
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1399
2.08k
        // GIR_Coverage, 1807,
1400
2.08k
        GIR_Done,
1401
2.08k
      // Label 95: @1291
1402
2.08k
      GIM_Try, /*On fail goto*//*Label 96*/ 1314, // Rule ID 1809 //
1403
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1404
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1405
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1406
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1407
2.08k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1408
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDWrr,
1409
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1410
2.08k
        // GIR_Coverage, 1809,
1411
2.08k
        GIR_Done,
1412
2.08k
      // Label 96: @1314
1413
2.08k
      GIM_Try, /*On fail goto*//*Label 97*/ 1337, // Rule ID 3881 //
1414
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1415
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1416
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1417
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1418
2.08k
        // (add:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPADDWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1419
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ128rr,
1420
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1421
2.08k
        // GIR_Coverage, 3881,
1422
2.08k
        GIR_Done,
1423
2.08k
      // Label 97: @1337
1424
2.08k
      GIM_Reject,
1425
2.08k
    // Label 92: @1338
1426
2.08k
    GIM_Reject,
1427
2.08k
    // Label 43: @1339
1428
2.08k
    GIM_Try, /*On fail goto*//*Label 98*/ 1396,
1429
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1430
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1431
2.08k
      GIM_Try, /*On fail goto*//*Label 99*/ 1372, // Rule ID 1817 //
1432
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1433
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1434
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1435
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1436
2.08k
        // (add:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPADDDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1437
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDYrr,
1438
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1439
2.08k
        // GIR_Coverage, 1817,
1440
2.08k
        GIR_Done,
1441
2.08k
      // Label 99: @1372
1442
2.08k
      GIM_Try, /*On fail goto*//*Label 100*/ 1395, // Rule ID 3851 //
1443
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1444
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1445
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1446
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1447
2.08k
        // (add:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPADDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1448
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ256rr,
1449
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1450
2.08k
        // GIR_Coverage, 3851,
1451
2.08k
        GIR_Done,
1452
2.08k
      // Label 100: @1395
1453
2.08k
      GIM_Reject,
1454
2.08k
    // Label 98: @1396
1455
2.08k
    GIM_Reject,
1456
2.08k
    // Label 44: @1397
1457
2.08k
    GIM_Try, /*On fail goto*//*Label 101*/ 1428, // Rule ID 3815 //
1458
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1459
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
1460
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
1461
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1462
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1463
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1464
2.08k
      // (add:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPADDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
1465
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZrr,
1466
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1467
2.08k
      // GIR_Coverage, 3815,
1468
2.08k
      GIR_Done,
1469
2.08k
    // Label 101: @1428
1470
2.08k
    GIM_Reject,
1471
2.08k
    // Label 45: @1429
1472
2.08k
    GIM_Try, /*On fail goto*//*Label 102*/ 1509,
1473
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1474
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1475
2.08k
      GIM_Try, /*On fail goto*//*Label 103*/ 1462, // Rule ID 1801 //
1476
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1477
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1478
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1479
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1480
2.08k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1481
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBrr,
1482
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1483
2.08k
        // GIR_Coverage, 1801,
1484
2.08k
        GIR_Done,
1485
2.08k
      // Label 103: @1462
1486
2.08k
      GIM_Try, /*On fail goto*//*Label 104*/ 1485, // Rule ID 1803 //
1487
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1488
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1489
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1490
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1491
2.08k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1492
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDBrr,
1493
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1494
2.08k
        // GIR_Coverage, 1803,
1495
2.08k
        GIR_Done,
1496
2.08k
      // Label 104: @1485
1497
2.08k
      GIM_Try, /*On fail goto*//*Label 105*/ 1508, // Rule ID 3899 //
1498
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1499
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1500
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1501
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1502
2.08k
        // (add:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPADDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
1503
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ128rr,
1504
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1505
2.08k
        // GIR_Coverage, 3899,
1506
2.08k
        GIR_Done,
1507
2.08k
      // Label 105: @1508
1508
2.08k
      GIM_Reject,
1509
2.08k
    // Label 102: @1509
1510
2.08k
    GIM_Reject,
1511
2.08k
    // Label 46: @1510
1512
2.08k
    GIM_Try, /*On fail goto*//*Label 106*/ 1567,
1513
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
1514
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
1515
2.08k
      GIM_Try, /*On fail goto*//*Label 107*/ 1543, // Rule ID 1811 //
1516
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1517
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1518
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1519
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1520
2.08k
        // (add:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPADDWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
1521
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWYrr,
1522
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1523
2.08k
        // GIR_Coverage, 1811,
1524
2.08k
        GIR_Done,
1525
2.08k
      // Label 107: @1543
1526
2.08k
      GIM_Try, /*On fail goto*//*Label 108*/ 1566, // Rule ID 3875 //
1527
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1528
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1529
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1530
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1531
2.08k
        // (add:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPADDWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
1532
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ256rr,
1533
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1534
2.08k
        // GIR_Coverage, 3875,
1535
2.08k
        GIR_Done,
1536
2.08k
      // Label 108: @1566
1537
2.08k
      GIM_Reject,
1538
2.08k
    // Label 106: @1567
1539
2.08k
    GIM_Reject,
1540
2.08k
    // Label 47: @1568
1541
2.08k
    GIM_Try, /*On fail goto*//*Label 109*/ 1599, // Rule ID 3842 //
1542
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1543
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
1544
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
1545
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1546
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1547
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1548
2.08k
      // (add:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPADDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
1549
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZrr,
1550
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1551
2.08k
      // GIR_Coverage, 3842,
1552
2.08k
      GIR_Done,
1553
2.08k
    // Label 109: @1599
1554
2.08k
    GIM_Reject,
1555
2.08k
    // Label 48: @1600
1556
2.08k
    GIM_Try, /*On fail goto*//*Label 110*/ 1657,
1557
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
1558
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
1559
2.08k
      GIM_Try, /*On fail goto*//*Label 111*/ 1633, // Rule ID 1805 //
1560
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1561
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1562
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1563
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1564
2.08k
        // (add:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPADDBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
1565
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBYrr,
1566
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1567
2.08k
        // GIR_Coverage, 1805,
1568
2.08k
        GIR_Done,
1569
2.08k
      // Label 111: @1633
1570
2.08k
      GIM_Try, /*On fail goto*//*Label 112*/ 1656, // Rule ID 3893 //
1571
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1572
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1573
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1574
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1575
2.08k
        // (add:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPADDBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
1576
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ256rr,
1577
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1578
2.08k
        // GIR_Coverage, 3893,
1579
2.08k
        GIR_Done,
1580
2.08k
      // Label 112: @1656
1581
2.08k
      GIM_Reject,
1582
2.08k
    // Label 110: @1657
1583
2.08k
    GIM_Reject,
1584
2.08k
    // Label 49: @1658
1585
2.08k
    GIM_Try, /*On fail goto*//*Label 113*/ 1689, // Rule ID 3869 //
1586
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
1587
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
1588
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
1589
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1590
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1591
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1592
2.08k
      // (add:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPADDWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
1593
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZrr,
1594
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1595
2.08k
      // GIR_Coverage, 3869,
1596
2.08k
      GIR_Done,
1597
2.08k
    // Label 113: @1689
1598
2.08k
    GIM_Reject,
1599
2.08k
    // Label 50: @1690
1600
2.08k
    GIM_Try, /*On fail goto*//*Label 114*/ 1721, // Rule ID 3887 //
1601
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
1602
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
1603
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
1604
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1605
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1606
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1607
2.08k
      // (add:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPADDBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
1608
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZrr,
1609
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1610
2.08k
      // GIR_Coverage, 3887,
1611
2.08k
      GIR_Done,
1612
2.08k
    // Label 114: @1721
1613
2.08k
    GIM_Reject,
1614
2.08k
    // Label 51: @1722
1615
2.08k
    GIM_Reject,
1616
2.08k
    // Label 1: @1723
1617
2.08k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 131*/ 2803,
1618
2.08k
    /*GILLT_s8*//*Label 115*/ 1753,
1619
2.08k
    /*GILLT_s16*//*Label 116*/ 1819,
1620
2.08k
    /*GILLT_s32*//*Label 117*/ 1918,
1621
2.08k
    /*GILLT_s64*//*Label 118*/ 2017, 0, 0, 0,
1622
2.08k
    /*GILLT_v2s64*//*Label 119*/ 2119, 0,
1623
2.08k
    /*GILLT_v4s32*//*Label 120*/ 2200,
1624
2.08k
    /*GILLT_v4s64*//*Label 121*/ 2281, 0,
1625
2.08k
    /*GILLT_v8s16*//*Label 122*/ 2339,
1626
2.08k
    /*GILLT_v8s32*//*Label 123*/ 2420,
1627
2.08k
    /*GILLT_v8s64*//*Label 124*/ 2478, 0,
1628
2.08k
    /*GILLT_v16s8*//*Label 125*/ 2510,
1629
2.08k
    /*GILLT_v16s16*//*Label 126*/ 2591,
1630
2.08k
    /*GILLT_v16s32*//*Label 127*/ 2649, 0,
1631
2.08k
    /*GILLT_v32s8*//*Label 128*/ 2681,
1632
2.08k
    /*GILLT_v32s16*//*Label 129*/ 2739, 0,
1633
2.08k
    /*GILLT_v64s8*//*Label 130*/ 2771,
1634
2.08k
    // Label 115: @1753
1635
2.08k
    GIM_Try, /*On fail goto*//*Label 132*/ 1818,
1636
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
1637
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
1638
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
1639
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
1640
2.08k
      GIM_Try, /*On fail goto*//*Label 133*/ 1801, // Rule ID 16111 //
1641
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1642
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1643
2.08k
        // MIs[1] Operand 1
1644
2.08k
        // No operand predicates
1645
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1646
2.08k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (SUB8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
1647
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri,
1648
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1649
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1650
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1651
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1652
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1653
2.08k
        // GIR_Coverage, 16111,
1654
2.08k
        GIR_Done,
1655
2.08k
      // Label 133: @1801
1656
2.08k
      GIM_Try, /*On fail goto*//*Label 134*/ 1817, // Rule ID 16103 //
1657
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
1658
2.08k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (SUB8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
1659
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB8rr,
1660
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1661
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1662
2.08k
        // GIR_Coverage, 16103,
1663
2.08k
        GIR_Done,
1664
2.08k
      // Label 134: @1817
1665
2.08k
      GIM_Reject,
1666
2.08k
    // Label 132: @1818
1667
2.08k
    GIM_Reject,
1668
2.08k
    // Label 116: @1819
1669
2.08k
    GIM_Try, /*On fail goto*//*Label 135*/ 1917,
1670
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1671
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
1672
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
1673
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
1674
2.08k
      GIM_Try, /*On fail goto*//*Label 136*/ 1870, // Rule ID 16114 //
1675
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1676
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1677
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
1678
2.08k
        // MIs[1] Operand 1
1679
2.08k
        // No operand predicates
1680
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1681
2.08k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
1682
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
1683
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1684
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1685
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1686
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1687
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1688
2.08k
        // GIR_Coverage, 16114,
1689
2.08k
        GIR_Done,
1690
2.08k
      // Label 136: @1870
1691
2.08k
      GIM_Try, /*On fail goto*//*Label 137*/ 1900, // Rule ID 16112 //
1692
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1693
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1694
2.08k
        // MIs[1] Operand 1
1695
2.08k
        // No operand predicates
1696
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1697
2.08k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (SUB16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
1698
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri,
1699
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1700
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1701
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1702
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1703
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1704
2.08k
        // GIR_Coverage, 16112,
1705
2.08k
        GIR_Done,
1706
2.08k
      // Label 137: @1900
1707
2.08k
      GIM_Try, /*On fail goto*//*Label 138*/ 1916, // Rule ID 16104 //
1708
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
1709
2.08k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (SUB16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
1710
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB16rr,
1711
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1712
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1713
2.08k
        // GIR_Coverage, 16104,
1714
2.08k
        GIR_Done,
1715
2.08k
      // Label 138: @1916
1716
2.08k
      GIM_Reject,
1717
2.08k
    // Label 135: @1917
1718
2.08k
    GIM_Reject,
1719
2.08k
    // Label 117: @1918
1720
2.08k
    GIM_Try, /*On fail goto*//*Label 139*/ 2016,
1721
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1722
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1723
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
1724
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
1725
2.08k
      GIM_Try, /*On fail goto*//*Label 140*/ 1969, // Rule ID 16115 //
1726
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1727
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1728
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1729
2.08k
        // MIs[1] Operand 1
1730
2.08k
        // No operand predicates
1731
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1732
2.08k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1733
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1734
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1735
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1736
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1737
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1738
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1739
2.08k
        // GIR_Coverage, 16115,
1740
2.08k
        GIR_Done,
1741
2.08k
      // Label 140: @1969
1742
2.08k
      GIM_Try, /*On fail goto*//*Label 141*/ 1999, // Rule ID 16113 //
1743
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1744
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1745
2.08k
        // MIs[1] Operand 1
1746
2.08k
        // No operand predicates
1747
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1748
2.08k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (SUB32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1749
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri,
1750
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1751
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1752
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1753
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1754
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1755
2.08k
        // GIR_Coverage, 16113,
1756
2.08k
        GIR_Done,
1757
2.08k
      // Label 141: @1999
1758
2.08k
      GIM_Try, /*On fail goto*//*Label 142*/ 2015, // Rule ID 16105 //
1759
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1760
2.08k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (SUB32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1761
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB32rr,
1762
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1763
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1764
2.08k
        // GIR_Coverage, 16105,
1765
2.08k
        GIR_Done,
1766
2.08k
      // Label 142: @2015
1767
2.08k
      GIM_Reject,
1768
2.08k
    // Label 139: @2016
1769
2.08k
    GIM_Reject,
1770
2.08k
    // Label 118: @2017
1771
2.08k
    GIM_Try, /*On fail goto*//*Label 143*/ 2118,
1772
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1773
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1774
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1775
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1776
2.08k
      GIM_Try, /*On fail goto*//*Label 144*/ 2068, // Rule ID 16116 //
1777
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1778
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1779
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1780
2.08k
        // MIs[1] Operand 1
1781
2.08k
        // No operand predicates
1782
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1783
2.08k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1784
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1785
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1786
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1787
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1788
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1789
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1790
2.08k
        // GIR_Coverage, 16116,
1791
2.08k
        GIR_Done,
1792
2.08k
      // Label 144: @2068
1793
2.08k
      GIM_Try, /*On fail goto*//*Label 145*/ 2101, // Rule ID 16117 //
1794
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1795
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1796
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1797
2.08k
        // MIs[1] Operand 1
1798
2.08k
        // No operand predicates
1799
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1800
2.08k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1801
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1802
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1803
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1804
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1805
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
1806
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1807
2.08k
        // GIR_Coverage, 16117,
1808
2.08k
        GIR_Done,
1809
2.08k
      // Label 145: @2101
1810
2.08k
      GIM_Try, /*On fail goto*//*Label 146*/ 2117, // Rule ID 16106 //
1811
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1812
2.08k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (SUB64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1813
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB64rr,
1814
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1815
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1816
2.08k
        // GIR_Coverage, 16106,
1817
2.08k
        GIR_Done,
1818
2.08k
      // Label 146: @2117
1819
2.08k
      GIM_Reject,
1820
2.08k
    // Label 143: @2118
1821
2.08k
    GIM_Reject,
1822
2.08k
    // Label 119: @2119
1823
2.08k
    GIM_Try, /*On fail goto*//*Label 147*/ 2199,
1824
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1825
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1826
2.08k
      GIM_Try, /*On fail goto*//*Label 148*/ 2152, // Rule ID 1885 //
1827
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1828
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1829
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1830
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1831
2.08k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1832
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQrr,
1833
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1834
2.08k
        // GIR_Coverage, 1885,
1835
2.08k
        GIR_Done,
1836
2.08k
      // Label 148: @2152
1837
2.08k
      GIM_Try, /*On fail goto*//*Label 149*/ 2175, // Rule ID 1887 //
1838
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1839
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1840
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1841
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1842
2.08k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1843
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBQrr,
1844
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1845
2.08k
        // GIR_Coverage, 1887,
1846
2.08k
        GIR_Done,
1847
2.08k
      // Label 149: @2175
1848
2.08k
      GIM_Try, /*On fail goto*//*Label 150*/ 2198, // Rule ID 3923 //
1849
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1850
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1851
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1852
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1853
2.08k
        // (sub:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPSUBQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1854
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ128rr,
1855
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1856
2.08k
        // GIR_Coverage, 3923,
1857
2.08k
        GIR_Done,
1858
2.08k
      // Label 150: @2198
1859
2.08k
      GIM_Reject,
1860
2.08k
    // Label 147: @2199
1861
2.08k
    GIM_Reject,
1862
2.08k
    // Label 120: @2200
1863
2.08k
    GIM_Try, /*On fail goto*//*Label 151*/ 2280,
1864
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1865
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1866
2.08k
      GIM_Try, /*On fail goto*//*Label 152*/ 2233, // Rule ID 1879 //
1867
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1868
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1869
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1870
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1871
2.08k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1872
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDrr,
1873
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1874
2.08k
        // GIR_Coverage, 1879,
1875
2.08k
        GIR_Done,
1876
2.08k
      // Label 152: @2233
1877
2.08k
      GIM_Try, /*On fail goto*//*Label 153*/ 2256, // Rule ID 1881 //
1878
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1879
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1880
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1881
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1882
2.08k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1883
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBDrr,
1884
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1885
2.08k
        // GIR_Coverage, 1881,
1886
2.08k
        GIR_Done,
1887
2.08k
      // Label 153: @2256
1888
2.08k
      GIM_Try, /*On fail goto*//*Label 154*/ 2279, // Rule ID 3950 //
1889
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1890
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1891
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1892
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1893
2.08k
        // (sub:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPSUBDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1894
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ128rr,
1895
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1896
2.08k
        // GIR_Coverage, 3950,
1897
2.08k
        GIR_Done,
1898
2.08k
      // Label 154: @2279
1899
2.08k
      GIM_Reject,
1900
2.08k
    // Label 151: @2280
1901
2.08k
    GIM_Reject,
1902
2.08k
    // Label 121: @2281
1903
2.08k
    GIM_Try, /*On fail goto*//*Label 155*/ 2338,
1904
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1905
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1906
2.08k
      GIM_Try, /*On fail goto*//*Label 156*/ 2314, // Rule ID 1889 //
1907
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1908
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1909
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1910
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1911
2.08k
        // (sub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPSUBQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1912
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQYrr,
1913
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1914
2.08k
        // GIR_Coverage, 1889,
1915
2.08k
        GIR_Done,
1916
2.08k
      // Label 156: @2314
1917
2.08k
      GIM_Try, /*On fail goto*//*Label 157*/ 2337, // Rule ID 3914 //
1918
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1919
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1920
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1921
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1922
2.08k
        // (sub:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPSUBQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1923
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ256rr,
1924
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1925
2.08k
        // GIR_Coverage, 3914,
1926
2.08k
        GIR_Done,
1927
2.08k
      // Label 157: @2337
1928
2.08k
      GIM_Reject,
1929
2.08k
    // Label 155: @2338
1930
2.08k
    GIM_Reject,
1931
2.08k
    // Label 122: @2339
1932
2.08k
    GIM_Try, /*On fail goto*//*Label 158*/ 2419,
1933
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1934
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1935
2.08k
      GIM_Try, /*On fail goto*//*Label 159*/ 2372, // Rule ID 1873 //
1936
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1937
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1938
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1939
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1940
2.08k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1941
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWrr,
1942
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1943
2.08k
        // GIR_Coverage, 1873,
1944
2.08k
        GIR_Done,
1945
2.08k
      // Label 159: @2372
1946
2.08k
      GIM_Try, /*On fail goto*//*Label 160*/ 2395, // Rule ID 1875 //
1947
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1948
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1949
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1950
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1951
2.08k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1952
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBWrr,
1953
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1954
2.08k
        // GIR_Coverage, 1875,
1955
2.08k
        GIR_Done,
1956
2.08k
      // Label 160: @2395
1957
2.08k
      GIM_Try, /*On fail goto*//*Label 161*/ 2418, // Rule ID 3971 //
1958
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1959
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1960
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1961
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1962
2.08k
        // (sub:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPSUBWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1963
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ128rr,
1964
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1965
2.08k
        // GIR_Coverage, 3971,
1966
2.08k
        GIR_Done,
1967
2.08k
      // Label 161: @2418
1968
2.08k
      GIM_Reject,
1969
2.08k
    // Label 158: @2419
1970
2.08k
    GIM_Reject,
1971
2.08k
    // Label 123: @2420
1972
2.08k
    GIM_Try, /*On fail goto*//*Label 162*/ 2477,
1973
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1974
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1975
2.08k
      GIM_Try, /*On fail goto*//*Label 163*/ 2453, // Rule ID 1883 //
1976
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1977
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1978
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1979
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1980
2.08k
        // (sub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPSUBDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1981
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDYrr,
1982
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1983
2.08k
        // GIR_Coverage, 1883,
1984
2.08k
        GIR_Done,
1985
2.08k
      // Label 163: @2453
1986
2.08k
      GIM_Try, /*On fail goto*//*Label 164*/ 2476, // Rule ID 3941 //
1987
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1988
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1989
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1990
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1991
2.08k
        // (sub:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPSUBDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1992
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ256rr,
1993
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1994
2.08k
        // GIR_Coverage, 3941,
1995
2.08k
        GIR_Done,
1996
2.08k
      // Label 164: @2476
1997
2.08k
      GIM_Reject,
1998
2.08k
    // Label 162: @2477
1999
2.08k
    GIM_Reject,
2000
2.08k
    // Label 124: @2478
2001
2.08k
    GIM_Try, /*On fail goto*//*Label 165*/ 2509, // Rule ID 3905 //
2002
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2003
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
2004
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
2005
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2006
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2007
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2008
2.08k
      // (sub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPSUBQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
2009
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZrr,
2010
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2011
2.08k
      // GIR_Coverage, 3905,
2012
2.08k
      GIR_Done,
2013
2.08k
    // Label 165: @2509
2014
2.08k
    GIM_Reject,
2015
2.08k
    // Label 125: @2510
2016
2.08k
    GIM_Try, /*On fail goto*//*Label 166*/ 2590,
2017
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2018
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2019
2.08k
      GIM_Try, /*On fail goto*//*Label 167*/ 2543, // Rule ID 1867 //
2020
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
2021
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2022
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2023
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2024
2.08k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2025
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBrr,
2026
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2027
2.08k
        // GIR_Coverage, 1867,
2028
2.08k
        GIR_Done,
2029
2.08k
      // Label 167: @2543
2030
2.08k
      GIM_Try, /*On fail goto*//*Label 168*/ 2566, // Rule ID 1869 //
2031
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2032
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2033
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2034
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2035
2.08k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2036
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBBrr,
2037
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2038
2.08k
        // GIR_Coverage, 1869,
2039
2.08k
        GIR_Done,
2040
2.08k
      // Label 168: @2566
2041
2.08k
      GIM_Try, /*On fail goto*//*Label 169*/ 2589, // Rule ID 3989 //
2042
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2043
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2044
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2045
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2046
2.08k
        // (sub:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPSUBBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
2047
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ128rr,
2048
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2049
2.08k
        // GIR_Coverage, 3989,
2050
2.08k
        GIR_Done,
2051
2.08k
      // Label 169: @2589
2052
2.08k
      GIM_Reject,
2053
2.08k
    // Label 166: @2590
2054
2.08k
    GIM_Reject,
2055
2.08k
    // Label 126: @2591
2056
2.08k
    GIM_Try, /*On fail goto*//*Label 170*/ 2648,
2057
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2058
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2059
2.08k
      GIM_Try, /*On fail goto*//*Label 171*/ 2624, // Rule ID 1877 //
2060
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2061
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2062
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2063
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2064
2.08k
        // (sub:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPSUBWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2065
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWYrr,
2066
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2067
2.08k
        // GIR_Coverage, 1877,
2068
2.08k
        GIR_Done,
2069
2.08k
      // Label 171: @2624
2070
2.08k
      GIM_Try, /*On fail goto*//*Label 172*/ 2647, // Rule ID 3965 //
2071
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2072
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2073
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2074
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2075
2.08k
        // (sub:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPSUBWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2076
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ256rr,
2077
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2078
2.08k
        // GIR_Coverage, 3965,
2079
2.08k
        GIR_Done,
2080
2.08k
      // Label 172: @2647
2081
2.08k
      GIM_Reject,
2082
2.08k
    // Label 170: @2648
2083
2.08k
    GIM_Reject,
2084
2.08k
    // Label 127: @2649
2085
2.08k
    GIM_Try, /*On fail goto*//*Label 173*/ 2680, // Rule ID 3932 //
2086
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2087
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2088
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2089
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2090
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2091
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2092
2.08k
      // (sub:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPSUBDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2093
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZrr,
2094
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2095
2.08k
      // GIR_Coverage, 3932,
2096
2.08k
      GIR_Done,
2097
2.08k
    // Label 173: @2680
2098
2.08k
    GIM_Reject,
2099
2.08k
    // Label 128: @2681
2100
2.08k
    GIM_Try, /*On fail goto*//*Label 174*/ 2738,
2101
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
2102
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
2103
2.08k
      GIM_Try, /*On fail goto*//*Label 175*/ 2714, // Rule ID 1871 //
2104
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2105
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2106
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2107
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2108
2.08k
        // (sub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPSUBBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
2109
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBYrr,
2110
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2111
2.08k
        // GIR_Coverage, 1871,
2112
2.08k
        GIR_Done,
2113
2.08k
      // Label 175: @2714
2114
2.08k
      GIM_Try, /*On fail goto*//*Label 176*/ 2737, // Rule ID 3983 //
2115
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2116
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2117
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2118
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2119
2.08k
        // (sub:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPSUBBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
2120
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ256rr,
2121
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2122
2.08k
        // GIR_Coverage, 3983,
2123
2.08k
        GIR_Done,
2124
2.08k
      // Label 176: @2737
2125
2.08k
      GIM_Reject,
2126
2.08k
    // Label 174: @2738
2127
2.08k
    GIM_Reject,
2128
2.08k
    // Label 129: @2739
2129
2.08k
    GIM_Try, /*On fail goto*//*Label 177*/ 2770, // Rule ID 3959 //
2130
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
2131
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2132
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2133
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2134
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2135
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2136
2.08k
      // (sub:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPSUBWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2137
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZrr,
2138
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2139
2.08k
      // GIR_Coverage, 3959,
2140
2.08k
      GIR_Done,
2141
2.08k
    // Label 177: @2770
2142
2.08k
    GIM_Reject,
2143
2.08k
    // Label 130: @2771
2144
2.08k
    GIM_Try, /*On fail goto*//*Label 178*/ 2802, // Rule ID 3977 //
2145
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
2146
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
2147
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
2148
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2149
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2150
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2151
2.08k
      // (sub:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPSUBBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
2152
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZrr,
2153
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2154
2.08k
      // GIR_Coverage, 3977,
2155
2.08k
      GIR_Done,
2156
2.08k
    // Label 178: @2802
2157
2.08k
    GIM_Reject,
2158
2.08k
    // Label 131: @2803
2159
2.08k
    GIM_Reject,
2160
2.08k
    // Label 2: @2804
2161
2.08k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 191*/ 3569,
2162
2.08k
    /*GILLT_s16*//*Label 179*/ 2831,
2163
2.08k
    /*GILLT_s32*//*Label 180*/ 2930,
2164
2.08k
    /*GILLT_s64*//*Label 181*/ 3029, 0, 0, 0,
2165
2.08k
    /*GILLT_v2s64*//*Label 182*/ 3131, 0,
2166
2.08k
    /*GILLT_v4s32*//*Label 183*/ 3163,
2167
2.08k
    /*GILLT_v4s64*//*Label 184*/ 3244, 0,
2168
2.08k
    /*GILLT_v8s16*//*Label 185*/ 3276,
2169
2.08k
    /*GILLT_v8s32*//*Label 186*/ 3357,
2170
2.08k
    /*GILLT_v8s64*//*Label 187*/ 3415, 0, 0,
2171
2.08k
    /*GILLT_v16s16*//*Label 188*/ 3447,
2172
2.08k
    /*GILLT_v16s32*//*Label 189*/ 3505, 0, 0,
2173
2.08k
    /*GILLT_v32s16*//*Label 190*/ 3537,
2174
2.08k
    // Label 179: @2831
2175
2.08k
    GIM_Try, /*On fail goto*//*Label 192*/ 2929,
2176
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2177
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2178
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2179
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2180
2.08k
      GIM_Try, /*On fail goto*//*Label 193*/ 2882, // Rule ID 16132 //
2181
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2182
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2183
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2184
2.08k
        // MIs[1] Operand 1
2185
2.08k
        // No operand predicates
2186
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2187
2.08k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (IMUL16rri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2188
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8,
2189
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2190
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2191
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2192
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2193
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2194
2.08k
        // GIR_Coverage, 16132,
2195
2.08k
        GIR_Done,
2196
2.08k
      // Label 193: @2882
2197
2.08k
      GIM_Try, /*On fail goto*//*Label 194*/ 2912, // Rule ID 16130 //
2198
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2199
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2200
2.08k
        // MIs[1] Operand 1
2201
2.08k
        // No operand predicates
2202
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2203
2.08k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (IMUL16rri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2204
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri,
2205
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2206
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2207
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2208
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2209
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2210
2.08k
        // GIR_Coverage, 16130,
2211
2.08k
        GIR_Done,
2212
2.08k
      // Label 194: @2912
2213
2.08k
      GIM_Try, /*On fail goto*//*Label 195*/ 2928, // Rule ID 16124 //
2214
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2215
2.08k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (IMUL16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2216
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL16rr,
2217
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2218
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2219
2.08k
        // GIR_Coverage, 16124,
2220
2.08k
        GIR_Done,
2221
2.08k
      // Label 195: @2928
2222
2.08k
      GIM_Reject,
2223
2.08k
    // Label 192: @2929
2224
2.08k
    GIM_Reject,
2225
2.08k
    // Label 180: @2930
2226
2.08k
    GIM_Try, /*On fail goto*//*Label 196*/ 3028,
2227
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2228
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2229
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2230
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2231
2.08k
      GIM_Try, /*On fail goto*//*Label 197*/ 2981, // Rule ID 16133 //
2232
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2233
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2234
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
2235
2.08k
        // MIs[1] Operand 1
2236
2.08k
        // No operand predicates
2237
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2238
2.08k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (IMUL32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
2239
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8,
2240
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2241
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2242
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2243
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2244
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2245
2.08k
        // GIR_Coverage, 16133,
2246
2.08k
        GIR_Done,
2247
2.08k
      // Label 197: @2981
2248
2.08k
      GIM_Try, /*On fail goto*//*Label 198*/ 3011, // Rule ID 16131 //
2249
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2250
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2251
2.08k
        // MIs[1] Operand 1
2252
2.08k
        // No operand predicates
2253
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2254
2.08k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (IMUL32rri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
2255
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri,
2256
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2257
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2258
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2259
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2260
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2261
2.08k
        // GIR_Coverage, 16131,
2262
2.08k
        GIR_Done,
2263
2.08k
      // Label 198: @3011
2264
2.08k
      GIM_Try, /*On fail goto*//*Label 199*/ 3027, // Rule ID 16125 //
2265
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
2266
2.08k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (IMUL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
2267
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL32rr,
2268
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2269
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2270
2.08k
        // GIR_Coverage, 16125,
2271
2.08k
        GIR_Done,
2272
2.08k
      // Label 199: @3027
2273
2.08k
      GIM_Reject,
2274
2.08k
    // Label 196: @3028
2275
2.08k
    GIM_Reject,
2276
2.08k
    // Label 181: @3029
2277
2.08k
    GIM_Try, /*On fail goto*//*Label 200*/ 3130,
2278
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2279
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2280
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
2281
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
2282
2.08k
      GIM_Try, /*On fail goto*//*Label 201*/ 3080, // Rule ID 16134 //
2283
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2284
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2285
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
2286
2.08k
        // MIs[1] Operand 1
2287
2.08k
        // No operand predicates
2288
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2289
2.08k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (IMUL64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
2290
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8,
2291
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2292
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2293
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2294
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2295
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2296
2.08k
        // GIR_Coverage, 16134,
2297
2.08k
        GIR_Done,
2298
2.08k
      // Label 201: @3080
2299
2.08k
      GIM_Try, /*On fail goto*//*Label 202*/ 3113, // Rule ID 16135 //
2300
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2301
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2302
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
2303
2.08k
        // MIs[1] Operand 1
2304
2.08k
        // No operand predicates
2305
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2306
2.08k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (IMUL64rri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
2307
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32,
2308
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2309
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2310
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2311
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2312
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2313
2.08k
        // GIR_Coverage, 16135,
2314
2.08k
        GIR_Done,
2315
2.08k
      // Label 202: @3113
2316
2.08k
      GIM_Try, /*On fail goto*//*Label 203*/ 3129, // Rule ID 16126 //
2317
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
2318
2.08k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (IMUL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
2319
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL64rr,
2320
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2321
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2322
2.08k
        // GIR_Coverage, 16126,
2323
2.08k
        GIR_Done,
2324
2.08k
      // Label 203: @3129
2325
2.08k
      GIM_Reject,
2326
2.08k
    // Label 200: @3130
2327
2.08k
    GIM_Reject,
2328
2.08k
    // Label 182: @3131
2329
2.08k
    GIM_Try, /*On fail goto*//*Label 204*/ 3162, // Rule ID 4202 //
2330
2.08k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2331
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2332
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2333
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2334
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2335
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2336
2.08k
      // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPMULLQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
2337
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ128rr,
2338
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2339
2.08k
      // GIR_Coverage, 4202,
2340
2.08k
      GIR_Done,
2341
2.08k
    // Label 204: @3162
2342
2.08k
    GIM_Reject,
2343
2.08k
    // Label 183: @3163
2344
2.08k
    GIM_Try, /*On fail goto*//*Label 205*/ 3243,
2345
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2346
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2347
2.08k
      GIM_Try, /*On fail goto*//*Label 206*/ 3196, // Rule ID 2507 //
2348
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
2349
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2350
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2351
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2352
2.08k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2353
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDrr,
2354
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2355
2.08k
        // GIR_Coverage, 2507,
2356
2.08k
        GIR_Done,
2357
2.08k
      // Label 206: @3196
2358
2.08k
      GIM_Try, /*On fail goto*//*Label 207*/ 3219, // Rule ID 2515 //
2359
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE41,
2360
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2361
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2362
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2363
2.08k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2364
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLDrr,
2365
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2366
2.08k
        // GIR_Coverage, 2515,
2367
2.08k
        GIR_Done,
2368
2.08k
      // Label 207: @3219
2369
2.08k
      GIM_Try, /*On fail goto*//*Label 208*/ 3242, // Rule ID 4157 //
2370
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2371
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2372
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2373
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2374
2.08k
        // (mul:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPMULLDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
2375
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ128rr,
2376
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2377
2.08k
        // GIR_Coverage, 4157,
2378
2.08k
        GIR_Done,
2379
2.08k
      // Label 208: @3242
2380
2.08k
      GIM_Reject,
2381
2.08k
    // Label 205: @3243
2382
2.08k
    GIM_Reject,
2383
2.08k
    // Label 184: @3244
2384
2.08k
    GIM_Try, /*On fail goto*//*Label 209*/ 3275, // Rule ID 4193 //
2385
2.08k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2386
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
2387
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
2388
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2389
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2390
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2391
2.08k
      // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPMULLQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
2392
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ256rr,
2393
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2394
2.08k
      // GIR_Coverage, 4193,
2395
2.08k
      GIR_Done,
2396
2.08k
    // Label 209: @3275
2397
2.08k
    GIM_Reject,
2398
2.08k
    // Label 185: @3276
2399
2.08k
    GIM_Try, /*On fail goto*//*Label 210*/ 3356,
2400
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2401
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2402
2.08k
      GIM_Try, /*On fail goto*//*Label 211*/ 3309, // Rule ID 1849 //
2403
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
2404
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2405
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2406
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2407
2.08k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2408
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWrr,
2409
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2410
2.08k
        // GIR_Coverage, 1849,
2411
2.08k
        GIR_Done,
2412
2.08k
      // Label 211: @3309
2413
2.08k
      GIM_Try, /*On fail goto*//*Label 212*/ 3332, // Rule ID 1851 //
2414
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2415
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2416
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2417
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2418
2.08k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2419
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLWrr,
2420
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2421
2.08k
        // GIR_Coverage, 1851,
2422
2.08k
        GIR_Done,
2423
2.08k
      // Label 212: @3332
2424
2.08k
      GIM_Try, /*On fail goto*//*Label 213*/ 3355, // Rule ID 4178 //
2425
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2426
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2427
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2428
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2429
2.08k
        // (mul:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPMULLWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
2430
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ128rr,
2431
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2432
2.08k
        // GIR_Coverage, 4178,
2433
2.08k
        GIR_Done,
2434
2.08k
      // Label 213: @3355
2435
2.08k
      GIM_Reject,
2436
2.08k
    // Label 210: @3356
2437
2.08k
    GIM_Reject,
2438
2.08k
    // Label 186: @3357
2439
2.08k
    GIM_Try, /*On fail goto*//*Label 214*/ 3414,
2440
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
2441
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
2442
2.08k
      GIM_Try, /*On fail goto*//*Label 215*/ 3390, // Rule ID 2511 //
2443
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
2444
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2445
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2446
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2447
2.08k
        // (mul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPMULLDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
2448
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDYrr,
2449
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2450
2.08k
        // GIR_Coverage, 2511,
2451
2.08k
        GIR_Done,
2452
2.08k
      // Label 215: @3390
2453
2.08k
      GIM_Try, /*On fail goto*//*Label 216*/ 3413, // Rule ID 4148 //
2454
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2455
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2456
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2457
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2458
2.08k
        // (mul:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPMULLDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
2459
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ256rr,
2460
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2461
2.08k
        // GIR_Coverage, 4148,
2462
2.08k
        GIR_Done,
2463
2.08k
      // Label 216: @3413
2464
2.08k
      GIM_Reject,
2465
2.08k
    // Label 214: @3414
2466
2.08k
    GIM_Reject,
2467
2.08k
    // Label 187: @3415
2468
2.08k
    GIM_Try, /*On fail goto*//*Label 217*/ 3446, // Rule ID 4184 //
2469
2.08k
      GIM_CheckFeatures, GIFBS_HasDQI,
2470
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
2471
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
2472
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2473
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2474
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2475
2.08k
      // (mul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPMULLQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
2476
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZrr,
2477
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2478
2.08k
      // GIR_Coverage, 4184,
2479
2.08k
      GIR_Done,
2480
2.08k
    // Label 217: @3446
2481
2.08k
    GIM_Reject,
2482
2.08k
    // Label 188: @3447
2483
2.08k
    GIM_Try, /*On fail goto*//*Label 218*/ 3504,
2484
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2485
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2486
2.08k
      GIM_Try, /*On fail goto*//*Label 219*/ 3480, // Rule ID 1853 //
2487
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2488
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2489
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2490
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2491
2.08k
        // (mul:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPMULLWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2492
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWYrr,
2493
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2494
2.08k
        // GIR_Coverage, 1853,
2495
2.08k
        GIR_Done,
2496
2.08k
      // Label 219: @3480
2497
2.08k
      GIM_Try, /*On fail goto*//*Label 220*/ 3503, // Rule ID 4172 //
2498
2.08k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2499
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2500
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2501
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2502
2.08k
        // (mul:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPMULLWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2503
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ256rr,
2504
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2505
2.08k
        // GIR_Coverage, 4172,
2506
2.08k
        GIR_Done,
2507
2.08k
      // Label 220: @3503
2508
2.08k
      GIM_Reject,
2509
2.08k
    // Label 218: @3504
2510
2.08k
    GIM_Reject,
2511
2.08k
    // Label 189: @3505
2512
2.08k
    GIM_Try, /*On fail goto*//*Label 221*/ 3536, // Rule ID 4139 //
2513
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2514
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2515
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2516
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2517
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2518
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2519
2.08k
      // (mul:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPMULLDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2520
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZrr,
2521
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2522
2.08k
      // GIR_Coverage, 4139,
2523
2.08k
      GIR_Done,
2524
2.08k
    // Label 221: @3536
2525
2.08k
    GIM_Reject,
2526
2.08k
    // Label 190: @3537
2527
2.08k
    GIM_Try, /*On fail goto*//*Label 222*/ 3568, // Rule ID 4166 //
2528
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
2529
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2530
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2531
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2532
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2533
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2534
2.08k
      // (mul:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPMULLWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2535
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZrr,
2536
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2537
2.08k
      // GIR_Coverage, 4166,
2538
2.08k
      GIR_Done,
2539
2.08k
    // Label 222: @3568
2540
2.08k
    GIM_Reject,
2541
2.08k
    // Label 191: @3569
2542
2.08k
    GIM_Reject,
2543
2.08k
    // Label 3: @3570
2544
2.08k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 24, /*)*//*default:*//*Label 237*/ 6681,
2545
2.08k
    /*GILLT_s1*//*Label 223*/ 3600,
2546
2.08k
    /*GILLT_s8*//*Label 224*/ 3898,
2547
2.08k
    /*GILLT_s16*//*Label 225*/ 3964,
2548
2.08k
    /*GILLT_s32*//*Label 226*/ 4063,
2549
2.08k
    /*GILLT_s64*//*Label 227*/ 5224, 0, 0,
2550
2.08k
    /*GILLT_v2s1*//*Label 228*/ 6096,
2551
2.08k
    /*GILLT_v2s64*//*Label 229*/ 6189,
2552
2.08k
    /*GILLT_v4s1*//*Label 230*/ 6270, 0,
2553
2.08k
    /*GILLT_v4s64*//*Label 231*/ 6363,
2554
2.08k
    /*GILLT_v8s1*//*Label 232*/ 6444, 0, 0,
2555
2.08k
    /*GILLT_v8s64*//*Label 233*/ 6553,
2556
2.08k
    /*GILLT_v16s1*//*Label 234*/ 6585, 0, 0, 0,
2557
2.08k
    /*GILLT_v32s1*//*Label 235*/ 6617, 0, 0,
2558
2.08k
    /*GILLT_v64s1*//*Label 236*/ 6649,
2559
2.08k
    // Label 223: @3600
2560
2.08k
    GIM_Try, /*On fail goto*//*Label 238*/ 3897,
2561
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
2562
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2563
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
2564
2.08k
      GIM_Try, /*On fail goto*//*Label 239*/ 3715, // Rule ID 13729 //
2565
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2566
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2567
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2568
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2569
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2570
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2571
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2572
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2573
2.08k
        // (and:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2574
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2575
2.08k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2576
2.08k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2577
2.08k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2578
2.08k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2579
2.08k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2580
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2581
2.08k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2582
2.08k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2583
2.08k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2584
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2585
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2586
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2587
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2588
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2589
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2590
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2591
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2592
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2593
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2594
2.08k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2595
2.08k
        // GIR_Coverage, 13729,
2596
2.08k
        GIR_Done,
2597
2.08k
      // Label 239: @3715
2598
2.08k
      GIM_Try, /*On fail goto*//*Label 240*/ 3816, // Rule ID 18279 //
2599
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2600
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2601
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2602
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2603
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2604
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2605
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2606
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2607
2.08k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }))  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2608
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2609
2.08k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2610
2.08k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2611
2.08k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2612
2.08k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2613
2.08k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2
2614
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2615
2.08k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2616
2.08k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2617
2.08k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2618
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2619
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2620
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2621
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2622
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2623
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2624
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2625
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2626
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2627
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2628
2.08k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2629
2.08k
        // GIR_Coverage, 18279,
2630
2.08k
        GIR_Done,
2631
2.08k
      // Label 240: @3816
2632
2.08k
      GIM_Try, /*On fail goto*//*Label 241*/ 3896, // Rule ID 13725 //
2633
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2634
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2635
2.08k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2636
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2637
2.08k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2638
2.08k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2639
2.08k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2640
2.08k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2641
2.08k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2642
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2643
2.08k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2644
2.08k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2645
2.08k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
2646
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2647
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
2648
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2649
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2650
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2651
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2652
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2653
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2654
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2655
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2656
2.08k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2657
2.08k
        // GIR_Coverage, 13725,
2658
2.08k
        GIR_Done,
2659
2.08k
      // Label 241: @3896
2660
2.08k
      GIM_Reject,
2661
2.08k
    // Label 238: @3897
2662
2.08k
    GIM_Reject,
2663
2.08k
    // Label 224: @3898
2664
2.08k
    GIM_Try, /*On fail goto*//*Label 242*/ 3963,
2665
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
2666
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
2667
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
2668
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
2669
2.08k
      GIM_Try, /*On fail goto*//*Label 243*/ 3946, // Rule ID 16188 //
2670
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2671
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2672
2.08k
        // MIs[1] Operand 1
2673
2.08k
        // No operand predicates
2674
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2675
2.08k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (AND8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
2676
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri,
2677
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2678
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2679
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2680
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2681
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2682
2.08k
        // GIR_Coverage, 16188,
2683
2.08k
        GIR_Done,
2684
2.08k
      // Label 243: @3946
2685
2.08k
      GIM_Try, /*On fail goto*//*Label 244*/ 3962, // Rule ID 16180 //
2686
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
2687
2.08k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (AND8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
2688
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND8rr,
2689
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2690
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2691
2.08k
        // GIR_Coverage, 16180,
2692
2.08k
        GIR_Done,
2693
2.08k
      // Label 244: @3962
2694
2.08k
      GIM_Reject,
2695
2.08k
    // Label 242: @3963
2696
2.08k
    GIM_Reject,
2697
2.08k
    // Label 225: @3964
2698
2.08k
    GIM_Try, /*On fail goto*//*Label 245*/ 4062,
2699
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2700
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2701
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2702
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2703
2.08k
      GIM_Try, /*On fail goto*//*Label 246*/ 4015, // Rule ID 16191 //
2704
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2705
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2706
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2707
2.08k
        // MIs[1] Operand 1
2708
2.08k
        // No operand predicates
2709
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2710
2.08k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (AND16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2711
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8,
2712
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2713
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2714
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2715
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2716
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2717
2.08k
        // GIR_Coverage, 16191,
2718
2.08k
        GIR_Done,
2719
2.08k
      // Label 246: @4015
2720
2.08k
      GIM_Try, /*On fail goto*//*Label 247*/ 4045, // Rule ID 16189 //
2721
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2722
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2723
2.08k
        // MIs[1] Operand 1
2724
2.08k
        // No operand predicates
2725
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2726
2.08k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (AND16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2727
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri,
2728
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2729
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2730
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2731
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2732
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2733
2.08k
        // GIR_Coverage, 16189,
2734
2.08k
        GIR_Done,
2735
2.08k
      // Label 247: @4045
2736
2.08k
      GIM_Try, /*On fail goto*//*Label 248*/ 4061, // Rule ID 16181 //
2737
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2738
2.08k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (AND16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2739
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND16rr,
2740
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2741
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2742
2.08k
        // GIR_Coverage, 16181,
2743
2.08k
        GIR_Done,
2744
2.08k
      // Label 248: @4061
2745
2.08k
      GIM_Reject,
2746
2.08k
    // Label 245: @4062
2747
2.08k
    GIM_Reject,
2748
2.08k
    // Label 226: @4063
2749
2.08k
    GIM_Try, /*On fail goto*//*Label 249*/ 5223,
2750
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2751
2.08k
      GIM_Try, /*On fail goto*//*Label 250*/ 4164, // Rule ID 18138 //
2752
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI2,
2753
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2754
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2755
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2756
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
2757
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2758
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
2759
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
2760
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2761
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC,
2762
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2763
2.08k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
2764
2.08k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB,
2765
2.08k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2766
2.08k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
2767
2.08k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 32,
2768
2.08k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/X86::GR32RegClassID,
2769
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
2770
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2771
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2772
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
2773
2.08k
        // (and:{ *:[i32] } (srl:{ *:[i32] } -1:{ *:[i32] }, (trunc:{ *:[i8] } (sub:{ *:[i32] } 32:{ *:[i32] }, GR32:{ *:[i32] }:$lz))), GR32:{ *:[i32] }:$src)  =>  (BZHI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src, GR32:{ *:[i32] }:$lz)
2774
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BZHI32rr,
2775
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2776
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2777
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // lz
2778
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2779
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2780
2.08k
        // GIR_Coverage, 18138,
2781
2.08k
        GIR_Done,
2782
2.08k
      // Label 250: @4164
2783
2.08k
      GIM_Try, /*On fail goto*//*Label 251*/ 4259, // Rule ID 12211 //
2784
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI2,
2785
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2786
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2787
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2788
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2789
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
2790
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2791
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
2792
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
2793
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2794
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC,
2795
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2796
2.08k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
2797
2.08k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB,
2798
2.08k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2799
2.08k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
2800
2.08k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 32,
2801
2.08k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/X86::GR32RegClassID,
2802
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2803
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2804
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
2805
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (srl:{ *:[i32] } -1:{ *:[i32] }, (trunc:{ *:[i8] } (sub:{ *:[i32] } 32:{ *:[i32] }, GR32:{ *:[i32] }:$lz))))  =>  (BZHI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src, GR32:{ *:[i32] }:$lz)
2806
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BZHI32rr,
2807
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2808
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2809
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // lz
2810
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2811
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2812
2.08k
        // GIR_Coverage, 12211,
2813
2.08k
        GIR_Done,
2814
2.08k
      // Label 251: @4259
2815
2.08k
      GIM_Try, /*On fail goto*//*Label 252*/ 4334, // Rule ID 18148 //
2816
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2817
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2818
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2819
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2820
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2821
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2822
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2823
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2824
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2825
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2826
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2827
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2828
2.08k
        // MIs[2] src
2829
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2830
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2831
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2832
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2833
2.08k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2834
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2835
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2836
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2837
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2838
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2839
2.08k
        // GIR_Coverage, 18148,
2840
2.08k
        GIR_Done,
2841
2.08k
      // Label 252: @4334
2842
2.08k
      GIM_Try, /*On fail goto*//*Label 253*/ 4409, // Rule ID 18160 //
2843
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2844
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2845
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2846
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2847
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2848
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2849
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2850
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2851
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2852
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2853
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2854
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2855
2.08k
        // MIs[2] src
2856
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2857
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2858
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2859
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2860
2.08k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2861
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2862
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2863
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2864
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2865
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2866
2.08k
        // GIR_Coverage, 18160,
2867
2.08k
        GIR_Done,
2868
2.08k
      // Label 253: @4409
2869
2.08k
      GIM_Try, /*On fail goto*//*Label 254*/ 4484, // Rule ID 12227 //
2870
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2871
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2872
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2873
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2874
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2875
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2876
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2877
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2878
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2879
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2880
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2881
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2882
2.08k
        // MIs[2] src
2883
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2884
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
2885
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2886
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2887
2.08k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2888
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2889
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2890
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2891
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2892
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2893
2.08k
        // GIR_Coverage, 12227,
2894
2.08k
        GIR_Done,
2895
2.08k
      // Label 254: @4484
2896
2.08k
      GIM_Try, /*On fail goto*//*Label 255*/ 4559, // Rule ID 12239 //
2897
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2898
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2899
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2900
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2901
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2902
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2903
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2904
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2905
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2906
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2907
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2908
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2909
2.08k
        // MIs[2] src
2910
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2911
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2912
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2913
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2914
2.08k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2915
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2916
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2917
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2918
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2919
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2920
2.08k
        // GIR_Coverage, 12239,
2921
2.08k
        GIR_Done,
2922
2.08k
      // Label 255: @4559
2923
2.08k
      GIM_Try, /*On fail goto*//*Label 256*/ 4613, // Rule ID 18142 //
2924
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2925
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2926
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2927
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2928
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2929
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2930
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2931
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2932
2.08k
        // MIs[0] src
2933
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2934
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2935
2.08k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2936
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2937
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2938
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2939
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2940
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2941
2.08k
        // GIR_Coverage, 18142,
2942
2.08k
        GIR_Done,
2943
2.08k
      // Label 256: @4613
2944
2.08k
      GIM_Try, /*On fail goto*//*Label 257*/ 4667, // Rule ID 18668 //
2945
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
2946
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2947
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2948
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2949
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2950
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2951
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2952
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2953
2.08k
        // MIs[0] src
2954
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2955
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2956
2.08k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2957
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2958
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2959
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2960
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2961
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2962
2.08k
        // GIR_Coverage, 18668,
2963
2.08k
        GIR_Done,
2964
2.08k
      // Label 257: @4667
2965
2.08k
      GIM_Try, /*On fail goto*//*Label 258*/ 4721, // Rule ID 18672 //
2966
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
2967
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2968
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2969
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
2970
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2971
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2972
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
2973
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
2974
2.08k
        // MIs[0] src
2975
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2976
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2977
2.08k
        // (and:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2978
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2979
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2980
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
2981
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
2982
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2983
2.08k
        // GIR_Coverage, 18672,
2984
2.08k
        GIR_Done,
2985
2.08k
      // Label 258: @4721
2986
2.08k
      GIM_Try, /*On fail goto*//*Label 259*/ 4775, // Rule ID 12221 //
2987
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
2988
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2989
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2990
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2991
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2992
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2993
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2994
2.08k
        // MIs[1] src
2995
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
2996
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2997
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2998
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2999
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
3000
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3001
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3002
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3003
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3004
2.08k
        // GIR_Coverage, 12221,
3005
2.08k
        GIR_Done,
3006
2.08k
      // Label 259: @4775
3007
2.08k
      GIM_Try, /*On fail goto*//*Label 260*/ 4829, // Rule ID 16387 //
3008
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3009
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3010
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3011
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3012
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3013
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3014
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3015
2.08k
        // MIs[1] src
3016
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3017
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3018
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3019
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3020
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
3021
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3022
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3023
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3024
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3025
2.08k
        // GIR_Coverage, 16387,
3026
2.08k
        GIR_Done,
3027
2.08k
      // Label 260: @4829
3028
2.08k
      GIM_Try, /*On fail goto*//*Label 261*/ 4883, // Rule ID 16391 //
3029
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3030
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3031
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3032
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3033
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3034
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3035
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3036
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3037
2.08k
        // MIs[1] src
3038
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3039
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3040
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3041
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
3042
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3043
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3044
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3045
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3046
2.08k
        // GIR_Coverage, 16391,
3047
2.08k
        GIR_Done,
3048
2.08k
      // Label 261: @4883
3049
2.08k
      GIM_Try, /*On fail goto*//*Label 262*/ 4934, // Rule ID 15964 //
3050
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3051
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3052
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3053
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
3054
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 65535:{ *:[i32] })  =>  (MOVZX32rr16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src1, sub_16bit:{ *:[i32] }))
3055
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3056
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3057
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3058
2.08k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1
3059
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3060
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16,
3061
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3062
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3063
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3064
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3065
2.08k
        // GIR_Coverage, 15964,
3066
2.08k
        GIR_Done,
3067
2.08k
      // Label 262: @4934
3068
2.08k
      GIM_Try, /*On fail goto*//*Label 263*/ 4985, // Rule ID 15965 //
3069
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3070
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3071
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3072
2.08k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
3073
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 255:{ *:[i32] })  =>  (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src1, sub_8bit:{ *:[i32] }))
3074
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
3075
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3076
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3077
2.08k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1
3078
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3079
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8,
3080
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3081
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3082
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3083
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3084
2.08k
        // GIR_Coverage, 15965,
3085
2.08k
        GIR_Done,
3086
2.08k
      // Label 263: @4985
3087
2.08k
      GIM_Try, /*On fail goto*//*Label 264*/ 5030, // Rule ID 16192 //
3088
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3089
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3090
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3091
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3092
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3093
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
3094
2.08k
        // MIs[1] Operand 1
3095
2.08k
        // No operand predicates
3096
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3097
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (AND32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
3098
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8,
3099
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3100
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3101
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3102
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3103
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3104
2.08k
        // GIR_Coverage, 16192,
3105
2.08k
        GIR_Done,
3106
2.08k
      // Label 264: @5030
3107
2.08k
      GIM_Try, /*On fail goto*//*Label 265*/ 5072, // Rule ID 16190 //
3108
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3109
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3110
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3111
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3112
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3113
2.08k
        // MIs[1] Operand 1
3114
2.08k
        // No operand predicates
3115
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3116
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (AND32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
3117
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri,
3118
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3119
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3120
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3121
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3122
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3123
2.08k
        // GIR_Coverage, 16190,
3124
2.08k
        GIR_Done,
3125
2.08k
      // Label 265: @5072
3126
2.08k
      GIM_Try, /*On fail goto*//*Label 266*/ 5133, // Rule ID 12249 //
3127
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3128
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3129
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3130
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3131
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3132
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3133
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3134
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3135
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3136
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3137
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3138
2.08k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src2)  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3139
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3140
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3141
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3142
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3143
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3144
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3145
2.08k
        // GIR_Coverage, 12249,
3146
2.08k
        GIR_Done,
3147
2.08k
      // Label 266: @5133
3148
2.08k
      GIM_Try, /*On fail goto*//*Label 267*/ 5194, // Rule ID 18162 //
3149
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3150
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3151
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3152
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3153
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3154
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3155
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3156
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3157
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3158
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3159
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3160
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src2, (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }))  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3161
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3162
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3163
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3164
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3165
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3166
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3167
2.08k
        // GIR_Coverage, 18162,
3168
2.08k
        GIR_Done,
3169
2.08k
      // Label 267: @5194
3170
2.08k
      GIM_Try, /*On fail goto*//*Label 268*/ 5222, // Rule ID 16182 //
3171
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3172
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3173
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3174
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3175
2.08k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (AND32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3176
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND32rr,
3177
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3178
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3179
2.08k
        // GIR_Coverage, 16182,
3180
2.08k
        GIR_Done,
3181
2.08k
      // Label 268: @5222
3182
2.08k
      GIM_Reject,
3183
2.08k
    // Label 249: @5223
3184
2.08k
    GIM_Reject,
3185
2.08k
    // Label 227: @5224
3186
2.08k
    GIM_Try, /*On fail goto*//*Label 269*/ 6095,
3187
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3188
2.08k
      GIM_Try, /*On fail goto*//*Label 270*/ 5305, // Rule ID 18149 //
3189
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3190
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3191
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3192
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3193
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3194
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3195
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3196
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3197
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3198
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3199
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3200
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3201
2.08k
        // MIs[2] src
3202
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3203
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3204
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3205
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3206
2.08k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3207
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3208
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3209
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3210
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3211
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3212
2.08k
        // GIR_Coverage, 18149,
3213
2.08k
        GIR_Done,
3214
2.08k
      // Label 270: @5305
3215
2.08k
      GIM_Try, /*On fail goto*//*Label 271*/ 5380, // Rule ID 18161 //
3216
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3217
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3218
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3219
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3220
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3221
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3222
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3223
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3224
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3225
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3226
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3227
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3228
2.08k
        // MIs[2] src
3229
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3230
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3231
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3232
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3233
2.08k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3234
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3235
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3236
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3237
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3238
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3239
2.08k
        // GIR_Coverage, 18161,
3240
2.08k
        GIR_Done,
3241
2.08k
      // Label 271: @5380
3242
2.08k
      GIM_Try, /*On fail goto*//*Label 272*/ 5455, // Rule ID 12228 //
3243
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3244
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3245
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3246
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3247
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3248
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3249
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3250
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3251
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3252
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3253
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3254
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3255
2.08k
        // MIs[2] src
3256
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3257
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
3258
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3259
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3260
2.08k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3261
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3262
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3263
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3264
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3265
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3266
2.08k
        // GIR_Coverage, 12228,
3267
2.08k
        GIR_Done,
3268
2.08k
      // Label 272: @5455
3269
2.08k
      GIM_Try, /*On fail goto*//*Label 273*/ 5530, // Rule ID 12240 //
3270
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3271
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3272
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3273
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3274
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3275
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3276
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3277
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3278
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3279
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3280
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3281
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3282
2.08k
        // MIs[2] src
3283
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3284
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3285
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3286
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3287
2.08k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3288
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3289
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3290
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3291
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3292
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3293
2.08k
        // GIR_Coverage, 12240,
3294
2.08k
        GIR_Done,
3295
2.08k
      // Label 273: @5530
3296
2.08k
      GIM_Try, /*On fail goto*//*Label 274*/ 5584, // Rule ID 18143 //
3297
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3298
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3299
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3300
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3301
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3302
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3303
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3304
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3305
2.08k
        // MIs[0] src
3306
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3307
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3308
2.08k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3309
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3310
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3311
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3312
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3313
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3314
2.08k
        // GIR_Coverage, 18143,
3315
2.08k
        GIR_Done,
3316
2.08k
      // Label 274: @5584
3317
2.08k
      GIM_Try, /*On fail goto*//*Label 275*/ 5638, // Rule ID 18669 //
3318
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3319
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3320
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3321
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3322
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3323
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3324
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3325
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3326
2.08k
        // MIs[0] src
3327
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3328
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3329
2.08k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3330
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3331
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3332
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3333
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3334
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3335
2.08k
        // GIR_Coverage, 18669,
3336
2.08k
        GIR_Done,
3337
2.08k
      // Label 275: @5638
3338
2.08k
      GIM_Try, /*On fail goto*//*Label 276*/ 5692, // Rule ID 18673 //
3339
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3340
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3341
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3342
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3343
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3344
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3345
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3346
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
3347
2.08k
        // MIs[0] src
3348
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3349
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3350
2.08k
        // (and:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3351
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3352
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3353
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
3354
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3355
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3356
2.08k
        // GIR_Coverage, 18673,
3357
2.08k
        GIR_Done,
3358
2.08k
      // Label 276: @5692
3359
2.08k
      GIM_Try, /*On fail goto*//*Label 277*/ 5746, // Rule ID 12222 //
3360
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3361
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3362
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3363
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3364
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3365
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3366
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3367
2.08k
        // MIs[1] src
3368
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3369
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3370
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3371
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3372
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3373
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3374
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3375
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3376
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3377
2.08k
        // GIR_Coverage, 12222,
3378
2.08k
        GIR_Done,
3379
2.08k
      // Label 277: @5746
3380
2.08k
      GIM_Try, /*On fail goto*//*Label 278*/ 5800, // Rule ID 16388 //
3381
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3382
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3383
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3384
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3385
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3386
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3387
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3388
2.08k
        // MIs[1] src
3389
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3390
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3391
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3392
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3393
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3394
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3395
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3396
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3397
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3398
2.08k
        // GIR_Coverage, 16388,
3399
2.08k
        GIR_Done,
3400
2.08k
      // Label 278: @5800
3401
2.08k
      GIM_Try, /*On fail goto*//*Label 279*/ 5854, // Rule ID 16392 //
3402
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3403
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3404
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3405
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3406
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3407
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3408
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3409
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3410
2.08k
        // MIs[1] src
3411
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3412
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3413
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3414
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3415
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3416
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3417
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3418
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3419
2.08k
        // GIR_Coverage, 16392,
3420
2.08k
        GIR_Done,
3421
2.08k
      // Label 279: @5854
3422
2.08k
      GIM_Try, /*On fail goto*//*Label 280*/ 5899, // Rule ID 16193 //
3423
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3424
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3425
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3426
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3427
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3428
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
3429
2.08k
        // MIs[1] Operand 1
3430
2.08k
        // No operand predicates
3431
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3432
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (AND64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
3433
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8,
3434
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3435
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3436
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3437
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3438
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3439
2.08k
        // GIR_Coverage, 16193,
3440
2.08k
        GIR_Done,
3441
2.08k
      // Label 280: @5899
3442
2.08k
      GIM_Try, /*On fail goto*//*Label 281*/ 5944, // Rule ID 16194 //
3443
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3444
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3445
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3446
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3447
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3448
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
3449
2.08k
        // MIs[1] Operand 1
3450
2.08k
        // No operand predicates
3451
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3452
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (AND64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
3453
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32,
3454
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3455
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3456
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3457
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3458
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3459
2.08k
        // GIR_Coverage, 16194,
3460
2.08k
        GIR_Done,
3461
2.08k
      // Label 281: @5944
3462
2.08k
      GIM_Try, /*On fail goto*//*Label 282*/ 6005, // Rule ID 12250 //
3463
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3464
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3465
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3466
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3467
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3468
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3469
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3470
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3471
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3472
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3473
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3474
2.08k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src2)  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3475
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3476
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3477
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3478
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3479
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3480
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3481
2.08k
        // GIR_Coverage, 12250,
3482
2.08k
        GIR_Done,
3483
2.08k
      // Label 282: @6005
3484
2.08k
      GIM_Try, /*On fail goto*//*Label 283*/ 6066, // Rule ID 18163 //
3485
2.08k
        GIM_CheckFeatures, GIFBS_HasBMI,
3486
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3487
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3488
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3489
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3490
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3491
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3492
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3493
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3494
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3495
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3496
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src2, (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }))  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3497
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3498
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3499
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3500
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3501
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3502
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3503
2.08k
        // GIR_Coverage, 18163,
3504
2.08k
        GIR_Done,
3505
2.08k
      // Label 283: @6066
3506
2.08k
      GIM_Try, /*On fail goto*//*Label 284*/ 6094, // Rule ID 16183 //
3507
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3508
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3509
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3510
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3511
2.08k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (AND64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3512
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND64rr,
3513
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3514
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3515
2.08k
        // GIR_Coverage, 16183,
3516
2.08k
        GIR_Done,
3517
2.08k
      // Label 284: @6094
3518
2.08k
      GIM_Reject,
3519
2.08k
    // Label 269: @6095
3520
2.08k
    GIM_Reject,
3521
2.08k
    // Label 228: @6096
3522
2.08k
    GIM_Try, /*On fail goto*//*Label 285*/ 6188, // Rule ID 13726 //
3523
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
3524
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
3525
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3526
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID,
3527
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID,
3528
2.08k
      // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3529
2.08k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3530
2.08k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3531
2.08k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3532
2.08k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3533
2.08k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3534
2.08k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3535
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3536
2.08k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3537
2.08k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3538
2.08k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3539
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3540
2.08k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3541
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3542
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3543
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3544
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3545
2.08k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3546
2.08k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3547
2.08k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3548
2.08k
      GIR_EraseFromParent, /*InsnID*/0,
3549
2.08k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3550
2.08k
      // GIR_Coverage, 13726,
3551
2.08k
      GIR_Done,
3552
2.08k
    // Label 285: @6188
3553
2.08k
    GIM_Reject,
3554
2.08k
    // Label 229: @6189
3555
2.08k
    GIM_Try, /*On fail goto*//*Label 286*/ 6269,
3556
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3557
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3558
2.08k
      GIM_Try, /*On fail goto*//*Label 287*/ 6222, // Rule ID 1541 //
3559
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3560
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3561
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3562
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3563
2.08k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3564
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3565
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3566
2.08k
        // GIR_Coverage, 1541,
3567
2.08k
        GIR_Done,
3568
2.08k
      // Label 287: @6222
3569
2.08k
      GIM_Try, /*On fail goto*//*Label 288*/ 6245, // Rule ID 1543 //
3570
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3571
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3572
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3573
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3574
2.08k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3575
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3576
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3577
2.08k
        // GIR_Coverage, 1543,
3578
2.08k
        GIR_Done,
3579
2.08k
      // Label 288: @6245
3580
2.08k
      GIM_Try, /*On fail goto*//*Label 289*/ 6268, // Rule ID 4886 //
3581
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3582
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3583
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3584
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3585
2.08k
        // (and:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPANDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
3586
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr,
3587
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3588
2.08k
        // GIR_Coverage, 4886,
3589
2.08k
        GIR_Done,
3590
2.08k
      // Label 289: @6268
3591
2.08k
      GIM_Reject,
3592
2.08k
    // Label 286: @6269
3593
2.08k
    GIM_Reject,
3594
2.08k
    // Label 230: @6270
3595
2.08k
    GIM_Try, /*On fail goto*//*Label 290*/ 6362, // Rule ID 13727 //
3596
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
3597
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
3598
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3599
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID,
3600
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID,
3601
2.08k
      // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3602
2.08k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3603
2.08k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3604
2.08k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3605
2.08k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3606
2.08k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3607
2.08k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3608
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3609
2.08k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3610
2.08k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3611
2.08k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3612
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3613
2.08k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3614
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3615
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3616
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3617
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3618
2.08k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3619
2.08k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3620
2.08k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3621
2.08k
      GIR_EraseFromParent, /*InsnID*/0,
3622
2.08k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3623
2.08k
      // GIR_Coverage, 13727,
3624
2.08k
      GIR_Done,
3625
2.08k
    // Label 290: @6362
3626
2.08k
    GIM_Reject,
3627
2.08k
    // Label 231: @6363
3628
2.08k
    GIM_Try, /*On fail goto*//*Label 291*/ 6443,
3629
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
3630
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
3631
2.08k
      GIM_Try, /*On fail goto*//*Label 292*/ 6396, // Rule ID 1545 //
3632
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3633
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3634
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3635
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3636
2.08k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPANDYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3637
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3638
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3639
2.08k
        // GIR_Coverage, 1545,
3640
2.08k
        GIR_Done,
3641
2.08k
      // Label 292: @6396
3642
2.08k
      GIM_Try, /*On fail goto*//*Label 293*/ 6419, // Rule ID 4877 //
3643
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3644
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3645
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3646
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3647
2.08k
        // (and:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPANDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
3648
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr,
3649
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3650
2.08k
        // GIR_Coverage, 4877,
3651
2.08k
        GIR_Done,
3652
2.08k
      // Label 293: @6419
3653
2.08k
      GIM_Try, /*On fail goto*//*Label 294*/ 6442, // Rule ID 12509 //
3654
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3655
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3656
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3657
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3658
2.08k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VANDPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3659
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3660
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3661
2.08k
        // GIR_Coverage, 12509,
3662
2.08k
        GIR_Done,
3663
2.08k
      // Label 294: @6442
3664
2.08k
      GIM_Reject,
3665
2.08k
    // Label 291: @6443
3666
2.08k
    GIM_Reject,
3667
2.08k
    // Label 232: @6444
3668
2.08k
    GIM_Try, /*On fail goto*//*Label 295*/ 6552,
3669
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
3670
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
3671
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID,
3672
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID,
3673
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID,
3674
2.08k
      GIM_Try, /*On fail goto*//*Label 296*/ 6477, // Rule ID 3601 //
3675
2.08k
        GIM_CheckFeatures, GIFBS_HasDQI,
3676
2.08k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (KANDBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)
3677
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDBrr,
3678
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3679
2.08k
        // GIR_Coverage, 3601,
3680
2.08k
        GIR_Done,
3681
2.08k
      // Label 296: @6477
3682
2.08k
      GIM_Try, /*On fail goto*//*Label 297*/ 6551, // Rule ID 13724 //
3683
2.08k
        GIM_CheckFeatures, GIFBS_NoDQI,
3684
2.08k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] })
3685
2.08k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3686
2.08k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3687
2.08k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3688
2.08k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3689
2.08k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3690
2.08k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3691
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3692
2.08k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3693
2.08k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3694
2.08k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3695
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3696
2.08k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3697
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3698
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3699
2.08k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3700
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3701
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3702
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3703
2.08k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3704
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3705
2.08k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12,
3706
2.08k
        // GIR_Coverage, 13724,
3707
2.08k
        GIR_Done,
3708
2.08k
      // Label 297: @6551
3709
2.08k
      GIM_Reject,
3710
2.08k
    // Label 295: @6552
3711
2.08k
    GIM_Reject,
3712
2.08k
    // Label 233: @6553
3713
2.08k
    GIM_Try, /*On fail goto*//*Label 298*/ 6584, // Rule ID 4868 //
3714
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3715
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
3716
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
3717
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3718
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3719
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3720
2.08k
      // (and:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPANDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
3721
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr,
3722
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3723
2.08k
      // GIR_Coverage, 4868,
3724
2.08k
      GIR_Done,
3725
2.08k
    // Label 298: @6584
3726
2.08k
    GIM_Reject,
3727
2.08k
    // Label 234: @6585
3728
2.08k
    GIM_Try, /*On fail goto*//*Label 299*/ 6616, // Rule ID 3602 //
3729
2.08k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3730
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
3731
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
3732
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID,
3733
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID,
3734
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID,
3735
2.08k
      // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)  =>  (KANDWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)
3736
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDWrr,
3737
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3738
2.08k
      // GIR_Coverage, 3602,
3739
2.08k
      GIR_Done,
3740
2.08k
    // Label 299: @6616
3741
2.08k
    GIM_Reject,
3742
2.08k
    // Label 235: @6617
3743
2.08k
    GIM_Try, /*On fail goto*//*Label 300*/ 6648, // Rule ID 3603 //
3744
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
3745
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1,
3746
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1,
3747
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID,
3748
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID,
3749
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID,
3750
2.08k
      // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)  =>  (KANDDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)
3751
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDDrr,
3752
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3753
2.08k
      // GIR_Coverage, 3603,
3754
2.08k
      GIR_Done,
3755
2.08k
    // Label 300: @6648
3756
2.08k
    GIM_Reject,
3757
2.08k
    // Label 236: @6649
3758
2.08k
    GIM_Try, /*On fail goto*//*Label 301*/ 6680, // Rule ID 3604 //
3759
2.08k
      GIM_CheckFeatures, GIFBS_HasBWI,
3760
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1,
3761
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1,
3762
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID,
3763
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID,
3764
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID,
3765
2.08k
      // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)  =>  (KANDQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)
3766
2.08k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDQrr,
3767
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3768
2.08k
      // GIR_Coverage, 3604,
3769
2.08k
      GIR_Done,
3770
2.08k
    // Label 301: @6680
3771
2.08k
    GIM_Reject,
3772
2.08k
    // Label 237: @6681
3773
2.08k
    GIM_Reject,
3774
2.08k
    // Label 4: @6682
3775
2.08k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 24, /*)*//*default:*//*Label 316*/ 9352,
3776
2.08k
    /*GILLT_s1*//*Label 302*/ 6712,
3777
2.08k
    /*GILLT_s8*//*Label 303*/ 6805,
3778
2.08k
    /*GILLT_s16*//*Label 304*/ 6871,
3779
2.08k
    /*GILLT_s32*//*Label 305*/ 6970,
3780
2.08k
    /*GILLT_s64*//*Label 306*/ 7867, 0, 0,
3781
2.08k
    /*GILLT_v2s1*//*Label 307*/ 8767,
3782
2.08k
    /*GILLT_v2s64*//*Label 308*/ 8860,
3783
2.08k
    /*GILLT_v4s1*//*Label 309*/ 8941, 0,
3784
2.08k
    /*GILLT_v4s64*//*Label 310*/ 9034,
3785
2.08k
    /*GILLT_v8s1*//*Label 311*/ 9115, 0, 0,
3786
2.08k
    /*GILLT_v8s64*//*Label 312*/ 9224,
3787
2.08k
    /*GILLT_v16s1*//*Label 313*/ 9256, 0, 0, 0,
3788
2.08k
    /*GILLT_v32s1*//*Label 314*/ 9288, 0, 0,
3789
2.08k
    /*GILLT_v64s1*//*Label 315*/ 9320,
3790
2.08k
    // Label 302: @6712
3791
2.08k
    GIM_Try, /*On fail goto*//*Label 317*/ 6804, // Rule ID 13733 //
3792
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
3793
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
3794
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3795
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
3796
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
3797
2.08k
      // (or:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3798
2.08k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3799
2.08k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3800
2.08k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3801
2.08k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3802
2.08k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3803
2.08k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3804
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3805
2.08k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3806
2.08k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3807
2.08k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3808
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3809
2.08k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
3810
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3811
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3812
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3813
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3814
2.08k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3815
2.08k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3816
2.08k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3817
2.08k
      GIR_EraseFromParent, /*InsnID*/0,
3818
2.08k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3819
2.08k
      // GIR_Coverage, 13733,
3820
2.08k
      GIR_Done,
3821
2.08k
    // Label 317: @6804
3822
2.08k
    GIM_Reject,
3823
2.08k
    // Label 303: @6805
3824
2.08k
    GIM_Try, /*On fail goto*//*Label 318*/ 6870,
3825
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
3826
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
3827
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
3828
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
3829
2.08k
      GIM_Try, /*On fail goto*//*Label 319*/ 6853, // Rule ID 16158 //
3830
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3831
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3832
2.08k
        // MIs[1] Operand 1
3833
2.08k
        // No operand predicates
3834
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3835
2.08k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (OR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
3836
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri,
3837
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3838
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3839
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3840
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3841
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3842
2.08k
        // GIR_Coverage, 16158,
3843
2.08k
        GIR_Done,
3844
2.08k
      // Label 319: @6853
3845
2.08k
      GIM_Try, /*On fail goto*//*Label 320*/ 6869, // Rule ID 16150 //
3846
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
3847
2.08k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (OR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
3848
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR8rr,
3849
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3850
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3851
2.08k
        // GIR_Coverage, 16150,
3852
2.08k
        GIR_Done,
3853
2.08k
      // Label 320: @6869
3854
2.08k
      GIM_Reject,
3855
2.08k
    // Label 318: @6870
3856
2.08k
    GIM_Reject,
3857
2.08k
    // Label 304: @6871
3858
2.08k
    GIM_Try, /*On fail goto*//*Label 321*/ 6969,
3859
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3860
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3861
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
3862
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
3863
2.08k
      GIM_Try, /*On fail goto*//*Label 322*/ 6922, // Rule ID 16161 //
3864
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3865
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3866
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
3867
2.08k
        // MIs[1] Operand 1
3868
2.08k
        // No operand predicates
3869
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3870
2.08k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (OR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
3871
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8,
3872
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3873
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3874
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3875
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3876
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3877
2.08k
        // GIR_Coverage, 16161,
3878
2.08k
        GIR_Done,
3879
2.08k
      // Label 322: @6922
3880
2.08k
      GIM_Try, /*On fail goto*//*Label 323*/ 6952, // Rule ID 16159 //
3881
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3882
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3883
2.08k
        // MIs[1] Operand 1
3884
2.08k
        // No operand predicates
3885
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3886
2.08k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (OR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
3887
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri,
3888
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3889
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3890
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3891
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3892
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3893
2.08k
        // GIR_Coverage, 16159,
3894
2.08k
        GIR_Done,
3895
2.08k
      // Label 323: @6952
3896
2.08k
      GIM_Try, /*On fail goto*//*Label 324*/ 6968, // Rule ID 16151 //
3897
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
3898
2.08k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (OR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
3899
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR16rr,
3900
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3901
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3902
2.08k
        // GIR_Coverage, 16151,
3903
2.08k
        GIR_Done,
3904
2.08k
      // Label 324: @6968
3905
2.08k
      GIM_Reject,
3906
2.08k
    // Label 321: @6969
3907
2.08k
    GIM_Reject,
3908
2.08k
    // Label 305: @6970
3909
2.08k
    GIM_Try, /*On fail goto*//*Label 325*/ 7866,
3910
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3911
2.08k
      GIM_Try, /*On fail goto*//*Label 326*/ 7051, // Rule ID 18156 //
3912
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3913
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3914
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3915
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3916
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3917
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3918
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3919
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3920
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3921
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3922
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3923
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3924
2.08k
        // MIs[2] src
3925
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3926
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3927
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3928
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3929
2.08k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3930
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
3931
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3932
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3933
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3934
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3935
2.08k
        // GIR_Coverage, 18156,
3936
2.08k
        GIR_Done,
3937
2.08k
      // Label 326: @7051
3938
2.08k
      GIM_Try, /*On fail goto*//*Label 327*/ 7126, // Rule ID 18158 //
3939
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3940
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3941
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3942
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3943
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3944
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3945
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3946
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3947
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3948
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3949
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3950
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3951
2.08k
        // MIs[2] src
3952
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3953
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3954
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3955
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3956
2.08k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3957
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
3958
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3959
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3960
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3961
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3962
2.08k
        // GIR_Coverage, 18158,
3963
2.08k
        GIR_Done,
3964
2.08k
      // Label 327: @7126
3965
2.08k
      GIM_Try, /*On fail goto*//*Label 328*/ 7201, // Rule ID 18144 //
3966
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3967
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3968
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3969
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3970
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3971
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3972
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3973
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3974
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3975
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3976
2.08k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR32RegClassID,
3977
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
3978
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3979
2.08k
        // MIs[0] src
3980
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3981
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3982
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3983
2.08k
        // (or:{ *:[i32] } (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3984
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
3985
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3986
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
3987
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
3988
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3989
2.08k
        // GIR_Coverage, 18144,
3990
2.08k
        GIR_Done,
3991
2.08k
      // Label 328: @7201
3992
2.08k
      GIM_Try, /*On fail goto*//*Label 329*/ 7276, // Rule ID 12235 //
3993
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
3994
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3995
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3996
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3997
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3998
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3999
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4000
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4001
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4002
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4003
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4004
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4005
2.08k
        // MIs[2] src
4006
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4007
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4008
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4009
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4010
2.08k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4011
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
4012
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4013
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4014
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4015
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4016
2.08k
        // GIR_Coverage, 12235,
4017
2.08k
        GIR_Done,
4018
2.08k
      // Label 329: @7276
4019
2.08k
      GIM_Try, /*On fail goto*//*Label 330*/ 7351, // Rule ID 12237 //
4020
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4021
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4022
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4023
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4024
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4025
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4026
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4027
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4028
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4029
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4030
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4031
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4032
2.08k
        // MIs[2] src
4033
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4034
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4035
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4036
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4037
2.08k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4038
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4039
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4040
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4041
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4042
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4043
2.08k
        // GIR_Coverage, 12237,
4044
2.08k
        GIR_Done,
4045
2.08k
      // Label 330: @7351
4046
2.08k
      GIM_Try, /*On fail goto*//*Label 331*/ 7426, // Rule ID 12223 //
4047
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4048
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4049
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4050
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4051
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4052
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4053
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4054
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4055
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4056
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4057
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4058
2.08k
        // MIs[2] src
4059
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4060
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4061
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4062
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4063
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4064
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4065
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4066
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4067
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4068
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4069
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4070
2.08k
        // GIR_Coverage, 12223,
4071
2.08k
        GIR_Done,
4072
2.08k
      // Label 331: @7426
4073
2.08k
      GIM_Try, /*On fail goto*//*Label 332*/ 7480, // Rule ID 18152 //
4074
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4075
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4076
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4077
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4078
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4079
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4080
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4081
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4082
2.08k
        // MIs[0] src
4083
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4084
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4085
2.08k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4086
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4087
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4088
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4089
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4090
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4091
2.08k
        // GIR_Coverage, 18152,
4092
2.08k
        GIR_Done,
4093
2.08k
      // Label 332: @7480
4094
2.08k
      GIM_Try, /*On fail goto*//*Label 333*/ 7534, // Rule ID 18154 //
4095
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4096
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4097
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4098
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4099
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4100
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4101
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4102
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4103
2.08k
        // MIs[0] src
4104
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4105
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4106
2.08k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4107
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4108
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4109
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4110
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4111
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4112
2.08k
        // GIR_Coverage, 18154,
4113
2.08k
        GIR_Done,
4114
2.08k
      // Label 333: @7534
4115
2.08k
      GIM_Try, /*On fail goto*//*Label 334*/ 7588, // Rule ID 18146 //
4116
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4117
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4118
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4119
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4120
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4121
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4122
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4123
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
4124
2.08k
        // MIs[0] src
4125
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4126
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4127
2.08k
        // (or:{ *:[i32] } (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4128
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4129
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4130
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4131
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4132
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4133
2.08k
        // GIR_Coverage, 18146,
4134
2.08k
        GIR_Done,
4135
2.08k
      // Label 334: @7588
4136
2.08k
      GIM_Try, /*On fail goto*//*Label 335*/ 7642, // Rule ID 12231 //
4137
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4138
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4139
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4140
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4141
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4142
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4143
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4144
2.08k
        // MIs[1] src
4145
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4146
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4147
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4148
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4149
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4150
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4151
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4152
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4153
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4154
2.08k
        // GIR_Coverage, 12231,
4155
2.08k
        GIR_Done,
4156
2.08k
      // Label 335: @7642
4157
2.08k
      GIM_Try, /*On fail goto*//*Label 336*/ 7696, // Rule ID 12233 //
4158
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4159
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4160
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4161
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4162
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4163
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4164
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4165
2.08k
        // MIs[1] src
4166
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4167
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4168
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4169
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4170
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4171
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4172
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4173
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4174
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4175
2.08k
        // GIR_Coverage, 12233,
4176
2.08k
        GIR_Done,
4177
2.08k
      // Label 336: @7696
4178
2.08k
      GIM_Try, /*On fail goto*//*Label 337*/ 7750, // Rule ID 12225 //
4179
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4180
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4181
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4182
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4183
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4184
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4185
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4186
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4187
2.08k
        // MIs[1] src
4188
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4189
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4190
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4191
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4192
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4193
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4194
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4195
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4196
2.08k
        // GIR_Coverage, 12225,
4197
2.08k
        GIR_Done,
4198
2.08k
      // Label 337: @7750
4199
2.08k
      GIM_Try, /*On fail goto*//*Label 338*/ 7795, // Rule ID 16162 //
4200
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4201
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4202
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4203
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4204
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4205
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
4206
2.08k
        // MIs[1] Operand 1
4207
2.08k
        // No operand predicates
4208
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4209
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (OR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
4210
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8,
4211
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4212
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4213
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4214
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4215
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4216
2.08k
        // GIR_Coverage, 16162,
4217
2.08k
        GIR_Done,
4218
2.08k
      // Label 338: @7795
4219
2.08k
      GIM_Try, /*On fail goto*//*Label 339*/ 7837, // Rule ID 16160 //
4220
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4221
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4222
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4223
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4224
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4225
2.08k
        // MIs[1] Operand 1
4226
2.08k
        // No operand predicates
4227
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4228
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (OR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
4229
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri,
4230
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4231
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4232
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4233
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4234
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4235
2.08k
        // GIR_Coverage, 16160,
4236
2.08k
        GIR_Done,
4237
2.08k
      // Label 339: @7837
4238
2.08k
      GIM_Try, /*On fail goto*//*Label 340*/ 7865, // Rule ID 16152 //
4239
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4240
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4241
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4242
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
4243
2.08k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (OR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
4244
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR32rr,
4245
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4246
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4247
2.08k
        // GIR_Coverage, 16152,
4248
2.08k
        GIR_Done,
4249
2.08k
      // Label 340: @7865
4250
2.08k
      GIM_Reject,
4251
2.08k
    // Label 325: @7866
4252
2.08k
    GIM_Reject,
4253
2.08k
    // Label 306: @7867
4254
2.08k
    GIM_Try, /*On fail goto*//*Label 341*/ 8766,
4255
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4256
2.08k
      GIM_Try, /*On fail goto*//*Label 342*/ 7948, // Rule ID 18157 //
4257
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4258
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4259
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4260
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4261
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4262
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4263
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4264
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4265
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4266
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4267
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4268
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4269
2.08k
        // MIs[2] src
4270
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4271
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4272
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4273
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4274
2.08k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4275
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4276
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4277
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4278
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4279
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4280
2.08k
        // GIR_Coverage, 18157,
4281
2.08k
        GIR_Done,
4282
2.08k
      // Label 342: @7948
4283
2.08k
      GIM_Try, /*On fail goto*//*Label 343*/ 8023, // Rule ID 18159 //
4284
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4285
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4286
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4287
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4288
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4289
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4290
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4291
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4292
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4293
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4294
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4295
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4296
2.08k
        // MIs[2] src
4297
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4298
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4299
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4300
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4301
2.08k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4302
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4303
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4304
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4305
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4306
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4307
2.08k
        // GIR_Coverage, 18159,
4308
2.08k
        GIR_Done,
4309
2.08k
      // Label 343: @8023
4310
2.08k
      GIM_Try, /*On fail goto*//*Label 344*/ 8098, // Rule ID 18145 //
4311
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4312
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4313
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4314
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4315
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4316
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4317
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4318
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4319
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4320
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4321
2.08k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR64RegClassID,
4322
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4323
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4324
2.08k
        // MIs[0] src
4325
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4326
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4327
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4328
2.08k
        // (or:{ *:[i64] } (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4329
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4330
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4331
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
4332
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4333
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4334
2.08k
        // GIR_Coverage, 18145,
4335
2.08k
        GIR_Done,
4336
2.08k
      // Label 344: @8098
4337
2.08k
      GIM_Try, /*On fail goto*//*Label 345*/ 8173, // Rule ID 12236 //
4338
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4339
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4340
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4341
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4342
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4343
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4344
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4345
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4346
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4347
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4348
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4349
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4350
2.08k
        // MIs[2] src
4351
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4352
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4353
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4354
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4355
2.08k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4356
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4357
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4358
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4359
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4360
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361
2.08k
        // GIR_Coverage, 12236,
4362
2.08k
        GIR_Done,
4363
2.08k
      // Label 345: @8173
4364
2.08k
      GIM_Try, /*On fail goto*//*Label 346*/ 8248, // Rule ID 12238 //
4365
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4366
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4367
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4368
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4369
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4370
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4371
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4372
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4373
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4374
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4375
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4376
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4377
2.08k
        // MIs[2] src
4378
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4379
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4380
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4381
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4382
2.08k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4383
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4384
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4385
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4386
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4387
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4388
2.08k
        // GIR_Coverage, 12238,
4389
2.08k
        GIR_Done,
4390
2.08k
      // Label 346: @8248
4391
2.08k
      GIM_Try, /*On fail goto*//*Label 347*/ 8323, // Rule ID 12224 //
4392
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4393
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4394
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4395
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4396
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4397
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4398
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4399
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4400
2.08k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4401
2.08k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4402
2.08k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4403
2.08k
        // MIs[2] src
4404
2.08k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4405
2.08k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4406
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4407
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4408
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4409
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4410
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4411
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4412
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4413
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4414
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4415
2.08k
        // GIR_Coverage, 12224,
4416
2.08k
        GIR_Done,
4417
2.08k
      // Label 347: @8323
4418
2.08k
      GIM_Try, /*On fail goto*//*Label 348*/ 8377, // Rule ID 18153 //
4419
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4420
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4421
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4422
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4423
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4424
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4425
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4426
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4427
2.08k
        // MIs[0] src
4428
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4429
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4430
2.08k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4431
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4432
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4433
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4434
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4435
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4436
2.08k
        // GIR_Coverage, 18153,
4437
2.08k
        GIR_Done,
4438
2.08k
      // Label 348: @8377
4439
2.08k
      GIM_Try, /*On fail goto*//*Label 349*/ 8431, // Rule ID 18155 //
4440
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4441
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4442
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4443
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4444
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4445
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4446
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4447
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4448
2.08k
        // MIs[0] src
4449
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4450
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4451
2.08k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4452
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4453
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4454
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4455
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4456
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457
2.08k
        // GIR_Coverage, 18155,
4458
2.08k
        GIR_Done,
4459
2.08k
      // Label 349: @8431
4460
2.08k
      GIM_Try, /*On fail goto*//*Label 350*/ 8485, // Rule ID 18147 //
4461
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4462
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4463
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4464
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4465
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4466
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4467
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4468
2.08k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
4469
2.08k
        // MIs[0] src
4470
2.08k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4471
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4472
2.08k
        // (or:{ *:[i64] } (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4473
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4474
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4475
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4476
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4477
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4478
2.08k
        // GIR_Coverage, 18147,
4479
2.08k
        GIR_Done,
4480
2.08k
      // Label 350: @8485
4481
2.08k
      GIM_Try, /*On fail goto*//*Label 351*/ 8539, // Rule ID 12232 //
4482
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4483
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4484
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4485
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4486
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4487
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4488
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4489
2.08k
        // MIs[1] src
4490
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4491
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4492
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4493
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4494
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4495
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4496
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4497
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4498
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4499
2.08k
        // GIR_Coverage, 12232,
4500
2.08k
        GIR_Done,
4501
2.08k
      // Label 351: @8539
4502
2.08k
      GIM_Try, /*On fail goto*//*Label 352*/ 8593, // Rule ID 12234 //
4503
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4504
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4505
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4506
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4507
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4508
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4509
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4510
2.08k
        // MIs[1] src
4511
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4512
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4513
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4514
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4515
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4516
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4517
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4518
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4519
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4520
2.08k
        // GIR_Coverage, 12234,
4521
2.08k
        GIR_Done,
4522
2.08k
      // Label 352: @8593
4523
2.08k
      GIM_Try, /*On fail goto*//*Label 353*/ 8647, // Rule ID 12226 //
4524
2.08k
        GIM_CheckFeatures, GIFBS_HasTBM,
4525
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4526
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4527
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4528
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4529
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4530
2.08k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4531
2.08k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4532
2.08k
        // MIs[1] src
4533
2.08k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4534
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4535
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4536
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4537
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4538
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4539
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4540
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4541
2.08k
        // GIR_Coverage, 12226,
4542
2.08k
        GIR_Done,
4543
2.08k
      // Label 353: @8647
4544
2.08k
      GIM_Try, /*On fail goto*//*Label 354*/ 8692, // Rule ID 16163 //
4545
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4546
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4547
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4548
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4549
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4550
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
4551
2.08k
        // MIs[1] Operand 1
4552
2.08k
        // No operand predicates
4553
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4554
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (OR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
4555
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri8,
4556
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4557
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4558
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4559
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4560
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4561
2.08k
        // GIR_Coverage, 16163,
4562
2.08k
        GIR_Done,
4563
2.08k
      // Label 354: @8692
4564
2.08k
      GIM_Try, /*On fail goto*//*Label 355*/ 8737, // Rule ID 16164 //
4565
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4566
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4567
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4568
2.08k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4569
2.08k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4570
2.08k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
4571
2.08k
        // MIs[1] Operand 1
4572
2.08k
        // No operand predicates
4573
2.08k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4574
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (OR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
4575
2.08k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri32,
4576
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4577
2.08k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4578
2.08k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4579
2.08k
        GIR_EraseFromParent, /*InsnID*/0,
4580
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4581
2.08k
        // GIR_Coverage, 16164,
4582
2.08k
        GIR_Done,
4583
2.08k
      // Label 355: @8737
4584
2.08k
      GIM_Try, /*On fail goto*//*Label 356*/ 8765, // Rule ID 16153 //
4585
2.08k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4586
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4587
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4588
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
4589
2.08k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (OR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
4590
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR64rr,
4591
2.08k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4592
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4593
2.08k
        // GIR_Coverage, 16153,
4594
2.08k
        GIR_Done,
4595
2.08k
      // Label 356: @8765
4596
2.08k
      GIM_Reject,
4597
2.08k
    // Label 341: @8766
4598
2.08k
    GIM_Reject,
4599
2.08k
    // Label 307: @8767
4600
2.08k
    GIM_Try, /*On fail goto*//*Label 357*/ 8859, // Rule ID 13734 //
4601
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
4602
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
4603
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
4604
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID,
4605
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID,
4606
2.08k
      // (or:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
4607
2.08k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4608
2.08k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4609
2.08k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4610
2.08k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4611
2.08k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4612
2.08k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4613
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4614
2.08k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4615
2.08k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4616
2.08k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
4617
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4618
2.08k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4619
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4620
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4621
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
4622
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4623
2.08k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4624
2.08k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4625
2.08k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4626
2.08k
      GIR_EraseFromParent, /*InsnID*/0,
4627
2.08k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
4628
2.08k
      // GIR_Coverage, 13734,
4629
2.08k
      GIR_Done,
4630
2.08k
    // Label 357: @8859
4631
2.08k
    GIM_Reject,
4632
2.08k
    // Label 308: @8860
4633
2.08k
    GIM_Try, /*On fail goto*//*Label 358*/ 8940,
4634
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4635
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4636
2.08k
      GIM_Try, /*On fail goto*//*Label 359*/ 8893, // Rule ID 1547 //
4637
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
4638
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
4639
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
4640
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
4641
2.08k
        // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
4642
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr,
4643
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4644
2.08k
        // GIR_Coverage, 1547,
4645
2.08k
        GIR_Done,
4646
2.08k
      // Label 359: @8893
4647
2.08k
      GIM_Try, /*On fail goto*//*Label 360*/ 8916, // Rule ID 1549 //
4648
2.08k
        GIM_CheckFeatures, GIFBS_UseSSE2,
4649
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
4650
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
4651
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
4652
2.08k
        // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
4653
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr,
4654
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4655
2.08k
        // GIR_Coverage, 1549,
4656
2.08k
        GIR_Done,
4657
2.08k
      // Label 360: @8916
4658
2.08k
      GIM_Try, /*On fail goto*//*Label 361*/ 8939, // Rule ID 4934 //
4659
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
4660
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
4661
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
4662
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
4663
2.08k
        // (or:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
4664
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr,
4665
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4666
2.08k
        // GIR_Coverage, 4934,
4667
2.08k
        GIR_Done,
4668
2.08k
      // Label 361: @8939
4669
2.08k
      GIM_Reject,
4670
2.08k
    // Label 358: @8940
4671
2.08k
    GIM_Reject,
4672
2.08k
    // Label 309: @8941
4673
2.08k
    GIM_Try, /*On fail goto*//*Label 362*/ 9033, // Rule ID 13735 //
4674
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
4675
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
4676
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
4677
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID,
4678
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID,
4679
2.08k
      // (or:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
4680
2.08k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4681
2.08k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4682
2.08k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4683
2.08k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4684
2.08k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4685
2.08k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4686
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4687
2.08k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4688
2.08k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4689
2.08k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
4690
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4691
2.08k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4692
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4693
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4694
2.08k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
4695
2.08k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4696
2.08k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4697
2.08k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4698
2.08k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4699
2.08k
      GIR_EraseFromParent, /*InsnID*/0,
4700
2.08k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
4701
2.08k
      // GIR_Coverage, 13735,
4702
2.08k
      GIR_Done,
4703
2.08k
    // Label 362: @9033
4704
2.08k
    GIM_Reject,
4705
2.08k
    // Label 310: @9034
4706
2.08k
    GIM_Try, /*On fail goto*//*Label 363*/ 9114,
4707
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
4708
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
4709
2.08k
      GIM_Try, /*On fail goto*//*Label 364*/ 9067, // Rule ID 1551 //
4710
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
4711
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
4712
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
4713
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
4714
2.08k
        // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
4715
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr,
4716
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4717
2.08k
        // GIR_Coverage, 1551,
4718
2.08k
        GIR_Done,
4719
2.08k
      // Label 364: @9067
4720
2.08k
      GIM_Try, /*On fail goto*//*Label 365*/ 9090, // Rule ID 4925 //
4721
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
4722
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
4723
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
4724
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
4725
2.08k
        // (or:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
4726
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr,
4727
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4728
2.08k
        // GIR_Coverage, 4925,
4729
2.08k
        GIR_Done,
4730
2.08k
      // Label 365: @9090
4731
2.08k
      GIM_Try, /*On fail goto*//*Label 366*/ 9113, // Rule ID 12510 //
4732
2.08k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
4733
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
4734
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
4735
2.08k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
4736
2.08k
        // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
4737
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr,
4738
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4739
2.08k
        // GIR_Coverage, 12510,
4740
2.08k
        GIR_Done,
4741
2.08k
      // Label 366: @9113
4742
2.08k
      GIM_Reject,
4743
2.08k
    // Label 363: @9114
4744
2.08k
    GIM_Reject,
4745
2.08k
    // Label 311: @9115
4746
2.08k
    GIM_Try, /*On fail goto*//*Label 367*/ 9223,
4747
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
4748
2.08k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
4749
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID,
4750
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID,
4751
2.08k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID,
4752
2.08k
      GIM_Try, /*On fail goto*//*Label 368*/ 9148, // Rule ID 3605 //
4753
2.08k
        GIM_CheckFeatures, GIFBS_HasDQI,
4754
2.08k
        // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (KORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)
4755
2.08k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORBrr,
4756
2.08k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4757
2.08k
        // GIR_Coverage, 3605,
4758
2.08k
        GIR_Done,
4759