Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenGlobalISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the X86 target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 114;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(X86InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(X86InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static X86InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static X86InstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33
#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_TruePredicateBit = 48,
37
  Feature_HasCMovBit = 21,
38
  Feature_NoCMovBit = 100,
39
  Feature_HasMMXBit = 81,
40
  Feature_Has3DNowBit = 83,
41
  Feature_HasSSE1Bit = 35,
42
  Feature_UseSSE1Bit = 41,
43
  Feature_HasSSE2Bit = 36,
44
  Feature_UseSSE2Bit = 42,
45
  Feature_HasSSE3Bit = 27,
46
  Feature_UseSSE3Bit = 51,
47
  Feature_HasSSSE3Bit = 82,
48
  Feature_UseSSSE3Bit = 52,
49
  Feature_NoSSE41Bit = 103,
50
  Feature_UseSSE41Bit = 49,
51
  Feature_HasSSE42Bit = 56,
52
  Feature_UseSSE42Bit = 55,
53
  Feature_HasSSE4ABit = 65,
54
  Feature_NoAVXBit = 61,
55
  Feature_HasAVXBit = 43,
56
  Feature_HasAVX2Bit = 39,
57
  Feature_HasAVX1OnlyBit = 37,
58
  Feature_HasAVX512Bit = 69,
59
  Feature_UseAVXBit = 40,
60
  Feature_UseAVX2Bit = 67,
61
  Feature_NoAVX512Bit = 32,
62
  Feature_HasCDIBit = 73,
63
  Feature_HasVPOPCNTDQBit = 77,
64
  Feature_HasERIBit = 76,
65
  Feature_HasDQIBit = 71,
66
  Feature_NoDQIBit = 53,
67
  Feature_HasBWIBit = 72,
68
  Feature_NoBWIBit = 50,
69
  Feature_HasVLXBit = 70,
70
  Feature_NoVLXBit = 31,
71
  Feature_NoVLX_Or_NoBWIBit = 47,
72
  Feature_NoVLX_Or_NoDQIBit = 105,
73
  Feature_HasVNNIBit = 79,
74
  Feature_HasBITALGBit = 80,
75
  Feature_HasPOPCNTBit = 54,
76
  Feature_HasAESBit = 58,
77
  Feature_HasVAESBit = 60,
78
  Feature_NoVLX_Or_NoVAESBit = 59,
79
  Feature_HasFXSRBit = 28,
80
  Feature_HasXSAVEBit = 89,
81
  Feature_HasXSAVEOPTBit = 90,
82
  Feature_HasXSAVECBit = 91,
83
  Feature_HasXSAVESBit = 92,
84
  Feature_HasPCLMULBit = 62,
85
  Feature_NoVLX_Or_NoVPCLMULQDQBit = 63,
86
  Feature_HasVPCLMULQDQBit = 64,
87
  Feature_HasGFNIBit = 68,
88
  Feature_HasFMABit = 29,
89
  Feature_HasFMA4Bit = 33,
90
  Feature_NoFMA4Bit = 30,
91
  Feature_HasXOPBit = 34,
92
  Feature_HasTBMBit = 9,
93
  Feature_NoTBMBit = 112,
94
  Feature_HasLWPBit = 10,
95
  Feature_HasMOVBEBit = 3,
96
  Feature_HasRDRANDBit = 4,
97
  Feature_HasF16CBit = 66,
98
  Feature_HasFSGSBaseBit = 93,
99
  Feature_HasLZCNTBit = 6,
100
  Feature_HasBMIBit = 7,
101
  Feature_HasBMI2Bit = 8,
102
  Feature_NoBMI2Bit = 113,
103
  Feature_HasVBMIBit = 74,
104
  Feature_HasVBMI2Bit = 78,
105
  Feature_HasIFMABit = 75,
106
  Feature_HasRTMBit = 87,
107
  Feature_HasADXBit = 20,
108
  Feature_HasSHABit = 57,
109
  Feature_HasRDSEEDBit = 5,
110
  Feature_HasSSEPrefetchBit = 45,
111
  Feature_NoSSEPrefetchBit = 84,
112
  Feature_HasPrefetchWBit = 85,
113
  Feature_HasPREFETCHWT1Bit = 86,
114
  Feature_HasLAHFSAHFBit = 2,
115
  Feature_HasMWAITXBit = 11,
116
  Feature_HasCLZEROBit = 15,
117
  Feature_HasCLDEMOTEBit = 18,
118
  Feature_HasMOVDIRIBit = 13,
119
  Feature_HasMOVDIR64BBit = 14,
120
  Feature_HasPTWRITEBit = 96,
121
  Feature_FPStackf32Bit = 25,
122
  Feature_FPStackf64Bit = 26,
123
  Feature_HasCLFLUSHOPTBit = 16,
124
  Feature_HasCLWBBit = 17,
125
  Feature_HasWBNOINVDBit = 88,
126
  Feature_HasRDPIDBit = 95,
127
  Feature_HasWAITPKGBit = 12,
128
  Feature_HasINVPCIDBit = 94,
129
  Feature_HasCmpxchg16bBit = 101,
130
  Feature_Not64BitModeBit = 0,
131
  Feature_In64BitModeBit = 1,
132
  Feature_IsLP64Bit = 98,
133
  Feature_NotLP64Bit = 97,
134
  Feature_NotWin64WithoutFPBit = 99,
135
  Feature_IsPS4Bit = 107,
136
  Feature_NotPS4Bit = 106,
137
  Feature_KernelCodeBit = 108,
138
  Feature_NearDataBit = 110,
139
  Feature_IsNotPICBit = 109,
140
  Feature_OptForSizeBit = 44,
141
  Feature_OptForMinSizeBit = 38,
142
  Feature_OptForSpeedBit = 104,
143
  Feature_UseIncDecBit = 19,
144
  Feature_CallImmAddrBit = 111,
145
  Feature_FavorMemIndirectCallBit = 22,
146
  Feature_HasFastSHLDRotateBit = 102,
147
  Feature_HasMFenceBit = 46,
148
  Feature_UseRetpolineBit = 24,
149
  Feature_NotUseRetpolineBit = 23,
150
};
151
152
PredicateBitset X86InstructionSelector::
153
12.1k
computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const {
154
12.1k
  PredicateBitset Features;
155
12.1k
  if (true)
156
12.1k
    Features[Feature_TruePredicateBit] = 1;
157
12.1k
  if (Subtarget->hasCMov())
158
10.6k
    Features[Feature_HasCMovBit] = 1;
159
12.1k
  if (!Subtarget->hasCMov())
160
1.45k
    Features[Feature_NoCMovBit] = 1;
161
12.1k
  if (Subtarget->hasMMX())
162
4.47k
    Features[Feature_HasMMXBit] = 1;
163
12.1k
  if (Subtarget->has3DNow())
164
38
    Features[Feature_Has3DNowBit] = 1;
165
12.1k
  if (Subtarget->hasSSE1())
166
10.6k
    Features[Feature_HasSSE1Bit] = 1;
167
12.1k
  if (Subtarget->hasSSE1() && 
!Subtarget->hasAVX()10.6k
)
168
7.30k
    Features[Feature_UseSSE1Bit] = 1;
169
12.1k
  if (Subtarget->hasSSE2())
170
10.5k
    Features[Feature_HasSSE2Bit] = 1;
171
12.1k
  if (Subtarget->hasSSE2() && 
!Subtarget->hasAVX()10.5k
)
172
7.24k
    Features[Feature_UseSSE2Bit] = 1;
173
12.1k
  if (Subtarget->hasSSE3())
174
6.21k
    Features[Feature_HasSSE3Bit] = 1;
175
12.1k
  if (Subtarget->hasSSE3() && 
!Subtarget->hasAVX()6.21k
)
176
2.88k
    Features[Feature_UseSSE3Bit] = 1;
177
12.1k
  if (Subtarget->hasSSSE3())
178
5.51k
    Features[Feature_HasSSSE3Bit] = 1;
179
12.1k
  if (Subtarget->hasSSSE3() && 
!Subtarget->hasAVX()5.51k
)
180
2.17k
    Features[Feature_UseSSSE3Bit] = 1;
181
12.1k
  if (!Subtarget->hasSSE41())
182
7.84k
    Features[Feature_NoSSE41Bit] = 1;
183
12.1k
  if (Subtarget->hasSSE41() && 
!Subtarget->hasAVX()4.28k
)
184
951
    Features[Feature_UseSSE41Bit] = 1;
185
12.1k
  if (Subtarget->hasSSE42())
186
3.81k
    Features[Feature_HasSSE42Bit] = 1;
187
12.1k
  if (Subtarget->hasSSE42() && 
!Subtarget->hasAVX()3.81k
)
188
483
    Features[Feature_UseSSE42Bit] = 1;
189
12.1k
  if (Subtarget->hasSSE4A())
190
307
    Features[Feature_HasSSE4ABit] = 1;
191
12.1k
  if (!Subtarget->hasAVX())
192
8.79k
    Features[Feature_NoAVXBit] = 1;
193
12.1k
  if (Subtarget->hasAVX())
194
3.33k
    Features[Feature_HasAVXBit] = 1;
195
12.1k
  if (Subtarget->hasAVX2())
196
2.33k
    Features[Feature_HasAVX2Bit] = 1;
197
12.1k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX2()3.33k
)
198
993
    Features[Feature_HasAVX1OnlyBit] = 1;
199
12.1k
  if (Subtarget->hasAVX512())
200
1.19k
    Features[Feature_HasAVX512Bit] = 1;
201
12.1k
  if (Subtarget->hasAVX() && 
!Subtarget->hasAVX512()3.33k
)
202
2.14k
    Features[Feature_UseAVXBit] = 1;
203
12.1k
  if (Subtarget->hasAVX2() && 
!Subtarget->hasAVX512()2.33k
)
204
1.14k
    Features[Feature_UseAVX2Bit] = 1;
205
12.1k
  if (!Subtarget->hasAVX512())
206
10.9k
    Features[Feature_NoAVX512Bit] = 1;
207
12.1k
  if (Subtarget->hasCDI())
208
260
    Features[Feature_HasCDIBit] = 1;
209
12.1k
  if (Subtarget->hasVPOPCNTDQ())
210
28
    Features[Feature_HasVPOPCNTDQBit] = 1;
211
12.1k
  if (Subtarget->hasERI())
212
91
    Features[Feature_HasERIBit] = 1;
213
12.1k
  if (Subtarget->hasDQI())
214
353
    Features[Feature_HasDQIBit] = 1;
215
12.1k
  if (!Subtarget->hasDQI())
216
11.7k
    Features[Feature_NoDQIBit] = 1;
217
12.1k
  if (Subtarget->hasBWI())
218
564
    Features[Feature_HasBWIBit] = 1;
219
12.1k
  if (!Subtarget->hasBWI())
220
11.5k
    Features[Feature_NoBWIBit] = 1;
221
12.1k
  if (Subtarget->hasVLX())
222
585
    Features[Feature_HasVLXBit] = 1;
223
12.1k
  if (!Subtarget->hasVLX())
224
11.5k
    Features[Feature_NoVLXBit] = 1;
225
12.1k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasBWI()585
)
226
11.7k
    Features[Feature_NoVLX_Or_NoBWIBit] = 1;
227
12.1k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasDQI()585
)
228
11.8k
    Features[Feature_NoVLX_Or_NoDQIBit] = 1;
229
12.1k
  if (Subtarget->hasVNNI())
230
16
    Features[Feature_HasVNNIBit] = 1;
231
12.1k
  if (Subtarget->hasBITALG())
232
19
    Features[Feature_HasBITALGBit] = 1;
233
12.1k
  if (Subtarget->hasPOPCNT())
234
1.79k
    Features[Feature_HasPOPCNTBit] = 1;
235
12.1k
  if (Subtarget->hasAES())
236
1.03k
    Features[Feature_HasAESBit] = 1;
237
12.1k
  if (Subtarget->hasVAES())
238
11
    Features[Feature_HasVAESBit] = 1;
239
12.1k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVAES()585
)
240
12.1k
    Features[Feature_NoVLX_Or_NoVAESBit] = 1;
241
12.1k
  if (Subtarget->hasFXSR())
242
4.07k
    Features[Feature_HasFXSRBit] = 1;
243
12.1k
  if (Subtarget->hasXSAVE())
244
1.48k
    Features[Feature_HasXSAVEBit] = 1;
245
12.1k
  if (Subtarget->hasXSAVEOPT())
246
1.41k
    Features[Feature_HasXSAVEOPTBit] = 1;
247
12.1k
  if (Subtarget->hasXSAVEC())
248
286
    Features[Feature_HasXSAVECBit] = 1;
249
12.1k
  if (Subtarget->hasXSAVES())
250
286
    Features[Feature_HasXSAVESBit] = 1;
251
12.1k
  if (Subtarget->hasPCLMUL())
252
1.04k
    Features[Feature_HasPCLMULBit] = 1;
253
12.1k
  if (!Subtarget->hasVLX() || 
!Subtarget->hasVPCLMULQDQ()585
)
254
12.1k
    Features[Feature_NoVLX_Or_NoVPCLMULQDQBit] = 1;
255
12.1k
  if (Subtarget->hasVPCLMULQDQ())
256
16
    Features[Feature_HasVPCLMULQDQBit] = 1;
257
12.1k
  if (Subtarget->hasGFNI())
258
12
    Features[Feature_HasGFNIBit] = 1;
259
12.1k
  if (Subtarget->hasFMA())
260
2.06k
    Features[Feature_HasFMABit] = 1;
261
12.1k
  if (Subtarget->hasFMA4())
262
160
    Features[Feature_HasFMA4Bit] = 1;
263
12.1k
  if (!Subtarget->hasFMA4())
264
11.9k
    Features[Feature_NoFMA4Bit] = 1;
265
12.1k
  if (Subtarget->hasXOP())
266
139
    Features[Feature_HasXOPBit] = 1;
267
12.1k
  if (Subtarget->hasTBM())
268
80
    Features[Feature_HasTBMBit] = 1;
269
12.1k
  if (!Subtarget->hasTBM())
270
12.0k
    Features[Feature_NoTBMBit] = 1;
271
12.1k
  if (Subtarget->hasLWP())
272
86
    Features[Feature_HasLWPBit] = 1;
273
12.1k
  if (Subtarget->hasMOVBE())
274
1.26k
    Features[Feature_HasMOVBEBit] = 1;
275
12.1k
  if (Subtarget->hasRDRAND())
276
677
    Features[Feature_HasRDRANDBit] = 1;
277
12.1k
  if (Subtarget->hasF16C())
278
2.14k
    Features[Feature_HasF16CBit] = 1;
279
12.1k
  if (Subtarget->hasFSGSBase())
280
636
    Features[Feature_HasFSGSBaseBit] = 1;
281
12.1k
  if (Subtarget->hasLZCNT())
282
1.21k
    Features[Feature_HasLZCNTBit] = 1;
283
12.1k
  if (Subtarget->hasBMI())
284
1.23k
    Features[Feature_HasBMIBit] = 1;
285
12.1k
  if (Subtarget->hasBMI2())
286
1.08k
    Features[Feature_HasBMI2Bit] = 1;
287
12.1k
  if (!Subtarget->hasBMI2())
288
11.0k
    Features[Feature_NoBMI2Bit] = 1;
289
12.1k
  if (Subtarget->hasVBMI())
290
46
    Features[Feature_HasVBMIBit] = 1;
291
12.1k
  if (Subtarget->hasVBMI2())
292
20
    Features[Feature_HasVBMI2Bit] = 1;
293
12.1k
  if (Subtarget->hasIFMA())
294
24
    Features[Feature_HasIFMABit] = 1;
295
12.1k
  if (Subtarget->hasRTM())
296
212
    Features[Feature_HasRTMBit] = 1;
297
12.1k
  if (Subtarget->hasADX())
298
378
    Features[Feature_HasADXBit] = 1;
299
12.1k
  if (Subtarget->hasSHA())
300
96
    Features[Feature_HasSHABit] = 1;
301
12.1k
  if (Subtarget->hasRDSEED())
302
416
    Features[Feature_HasRDSEEDBit] = 1;
303
12.1k
  if (Subtarget->hasSSEPrefetch())
304
10.6k
    Features[Feature_HasSSEPrefetchBit] = 1;
305
12.1k
  if (!Subtarget->hasSSEPrefetch())
306
1.48k
    Features[Feature_NoSSEPrefetchBit] = 1;
307
12.1k
  if (Subtarget->hasPRFCHW())
308
638
    Features[Feature_HasPrefetchWBit] = 1;
309
12.1k
  if (Subtarget->hasPREFETCHWT1())
310
92
    Features[Feature_HasPREFETCHWT1Bit] = 1;
311
12.1k
  if (Subtarget->hasLAHFSAHF())
312
5.95k
    Features[Feature_HasLAHFSAHFBit] = 1;
313
12.1k
  if (Subtarget->hasMWAITX())
314
67
    Features[Feature_HasMWAITXBit] = 1;
315
12.1k
  if (Subtarget->hasCLZERO())
316
49
    Features[Feature_HasCLZEROBit] = 1;
317
12.1k
  if (Subtarget->hasCLDEMOTE())
318
2
    Features[Feature_HasCLDEMOTEBit] = 1;
319
12.1k
  if (Subtarget->hasMOVDIRI())
320
3
    Features[Feature_HasMOVDIRIBit] = 1;
321
12.1k
  if (Subtarget->hasMOVDIR64B())
322
2
    Features[Feature_HasMOVDIR64BBit] = 1;
323
12.1k
  if (Subtarget->hasPTWRITE())
324
4
    Features[Feature_HasPTWRITEBit] = 1;
325
12.1k
  if (!Subtarget->hasSSE1())
326
1.49k
    Features[Feature_FPStackf32Bit] = 1;
327
12.1k
  if (!Subtarget->hasSSE2())
328
1.54k
    Features[Feature_FPStackf64Bit] = 1;
329
12.1k
  if (Subtarget->hasCLFLUSHOPT())
330
287
    Features[Feature_HasCLFLUSHOPTBit] = 1;
331
12.1k
  if (Subtarget->hasCLWB())
332
152
    Features[Feature_HasCLWBBit] = 1;
333
12.1k
  if (Subtarget->hasWBNOINVD())
334
6
    Features[Feature_HasWBNOINVDBit] = 1;
335
12.1k
  if (Subtarget->hasRDPID())
336
12
    Features[Feature_HasRDPIDBit] = 1;
337
12.1k
  if (Subtarget->hasWAITPKG())
338
2
    Features[Feature_HasWAITPKGBit] = 1;
339
12.1k
  if (Subtarget->hasINVPCID())
340
910
    Features[Feature_HasINVPCIDBit] = 1;
341
12.1k
  if (Subtarget->hasCmpxchg16b())
342
3.77k
    Features[Feature_HasCmpxchg16bBit] = 1;
343
12.1k
  if (!Subtarget->is64Bit())
344
3.03k
    Features[Feature_Not64BitModeBit] = 1;
345
12.1k
  if (Subtarget->is64Bit())
346
9.08k
    Features[Feature_In64BitModeBit] = 1;
347
12.1k
  if (Subtarget->isTarget64BitLP64())
348
9.02k
    Features[Feature_IsLP64Bit] = 1;
349
12.1k
  if (!Subtarget->isTarget64BitLP64())
350
3.10k
    Features[Feature_NotLP64Bit] = 1;
351
12.1k
  if (Subtarget->isTargetPS4())
352
32
    Features[Feature_IsPS4Bit] = 1;
353
12.1k
  if (!Subtarget->isTargetPS4())
354
12.0k
    Features[Feature_NotPS4Bit] = 1;
355
12.1k
  if (TM.getCodeModel() == CodeModel::Kernel)
356
3
    Features[Feature_KernelCodeBit] = 1;
357
12.1k
  if (TM.getCodeModel() == CodeModel::Small ||
TM.getCodeModel() == CodeModel::Kernel224
)
358
11.9k
    Features[Feature_NearDataBit] = 1;
359
12.1k
  if (!TM.isPositionIndependent())
360
6.85k
    Features[Feature_IsNotPICBit] = 1;
361
12.1k
  if (Subtarget->isLegalToCallImmediateAddr())
362
1.70k
    Features[Feature_CallImmAddrBit] = 1;
363
12.1k
  if (!Subtarget->slowTwoMemOps())
364
11.8k
    Features[Feature_FavorMemIndirectCallBit] = 1;
365
12.1k
  if (Subtarget->hasFastSHLDRotate())
366
1.22k
    Features[Feature_HasFastSHLDRotateBit] = 1;
367
12.1k
  if (Subtarget->hasMFence())
368
10.6k
    Features[Feature_HasMFenceBit] = 1;
369
12.1k
  if (Subtarget->useRetpoline())
370
12
    Features[Feature_UseRetpolineBit] = 1;
371
12.1k
  if (!Subtarget->useRetpoline())
372
12.1k
    Features[Feature_NotUseRetpolineBit] = 1;
373
12.1k
  return Features;
374
12.1k
}
375
376
PredicateBitset X86InstructionSelector::
377
1.91k
computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, const MachineFunction *MF) const {
378
1.91k
  PredicateBitset Features;
379
1.91k
  if (!Subtarget->isTargetWin64() ||
Subtarget->getFrameLowering()->hasFP(*MF)0
)
380
1.91k
    Features[Feature_NotWin64WithoutFPBit] = 1;
381
1.91k
  if (MF->getFunction().optForSize())
382
2
    Features[Feature_OptForSizeBit] = 1;
383
1.91k
  if (MF->getFunction().optForMinSize())
384
0
    Features[Feature_OptForMinSizeBit] = 1;
385
1.91k
  if (!MF->getFunction().optForSize())
386
1.90k
    Features[Feature_OptForSpeedBit] = 1;
387
1.91k
  if (!Subtarget->slowIncDec() || 
MF->getFunction().optForSize()206
)
388
1.70k
    Features[Feature_UseIncDecBit] = 1;
389
1.91k
  return Features;
390
1.91k
}
391
392
// LLT Objects.
393
enum {
394
  GILLT_s1,
395
  GILLT_s8,
396
  GILLT_s16,
397
  GILLT_s32,
398
  GILLT_s64,
399
  GILLT_s80,
400
  GILLT_s128,
401
  GILLT_v2s1,
402
  GILLT_v2s64,
403
  GILLT_v4s1,
404
  GILLT_v4s32,
405
  GILLT_v4s64,
406
  GILLT_v8s1,
407
  GILLT_v8s16,
408
  GILLT_v8s32,
409
  GILLT_v8s64,
410
  GILLT_v16s1,
411
  GILLT_v16s8,
412
  GILLT_v16s16,
413
  GILLT_v16s32,
414
  GILLT_v32s1,
415
  GILLT_v32s8,
416
  GILLT_v32s16,
417
  GILLT_v64s1,
418
  GILLT_v64s8,
419
};
420
const static size_t NumTypeObjects = 25;
421
const static LLT TypeObjects[] = {
422
  LLT::scalar(1),
423
  LLT::scalar(8),
424
  LLT::scalar(16),
425
  LLT::scalar(32),
426
  LLT::scalar(64),
427
  LLT::scalar(80),
428
  LLT::scalar(128),
429
  LLT::vector(2, 1),
430
  LLT::vector(2, 64),
431
  LLT::vector(4, 1),
432
  LLT::vector(4, 32),
433
  LLT::vector(4, 64),
434
  LLT::vector(8, 1),
435
  LLT::vector(8, 16),
436
  LLT::vector(8, 32),
437
  LLT::vector(8, 64),
438
  LLT::vector(16, 1),
439
  LLT::vector(16, 8),
440
  LLT::vector(16, 16),
441
  LLT::vector(16, 32),
442
  LLT::vector(32, 1),
443
  LLT::vector(32, 8),
444
  LLT::vector(32, 16),
445
  LLT::vector(64, 1),
446
  LLT::vector(64, 8),
447
};
448
449
// Feature bitsets.
450
enum {
451
  GIFBS_Invalid,
452
  GIFBS_FPStackf32,
453
  GIFBS_FPStackf64,
454
  GIFBS_Has3DNow,
455
  GIFBS_HasAVX,
456
  GIFBS_HasAVX1Only,
457
  GIFBS_HasAVX2,
458
  GIFBS_HasAVX512,
459
  GIFBS_HasBMI,
460
  GIFBS_HasBMI2,
461
  GIFBS_HasBWI,
462
  GIFBS_HasDQI,
463
  GIFBS_HasLWP,
464
  GIFBS_HasMFence,
465
  GIFBS_HasMMX,
466
  GIFBS_HasMOVBE,
467
  GIFBS_HasPTWRITE,
468
  GIFBS_HasRTM,
469
  GIFBS_HasSHA,
470
  GIFBS_HasSSE1,
471
  GIFBS_HasSSE2,
472
  GIFBS_HasSSE42,
473
  GIFBS_HasSSE4A,
474
  GIFBS_HasTBM,
475
  GIFBS_HasVLX,
476
  GIFBS_HasWAITPKG,
477
  GIFBS_HasWBNOINVD,
478
  GIFBS_HasXOP,
479
  GIFBS_In64BitMode,
480
  GIFBS_NoDQI,
481
  GIFBS_Not64BitMode,
482
  GIFBS_UseAVX,
483
  GIFBS_UseIncDec,
484
  GIFBS_UseSSE1,
485
  GIFBS_UseSSE2,
486
  GIFBS_UseSSE41,
487
  GIFBS_UseSSSE3,
488
  GIFBS_HasAES_HasAVX,
489
  GIFBS_HasAES_NoAVX,
490
  GIFBS_HasAVX_NoVLX,
491
  GIFBS_HasAVX_NoVLX_Or_NoBWI,
492
  GIFBS_HasAVX2_NoVLX,
493
  GIFBS_HasAVX2_NoVLX_Or_NoBWI,
494
  GIFBS_HasAVX512_HasVAES,
495
  GIFBS_HasAVX512_HasVLX,
496
  GIFBS_HasAVX512_HasVPCLMULQDQ,
497
  GIFBS_HasBWI_HasVLX,
498
  GIFBS_HasDQI_HasVLX,
499
  GIFBS_HasDQI_NoBWI,
500
  GIFBS_HasFSGSBase_In64BitMode,
501
  GIFBS_HasPCLMUL_NoAVX,
502
  GIFBS_HasPTWRITE_In64BitMode,
503
  GIFBS_HasRDPID_Not64BitMode,
504
  GIFBS_HasSSE2_NoAVX512,
505
  GIFBS_HasVAES_HasVLX,
506
  GIFBS_HasVAES_NoVLX,
507
  GIFBS_HasVLX_HasVPCLMULQDQ,
508
  GIFBS_HasVPCLMULQDQ_NoVLX,
509
  GIFBS_HasWAITPKG_In64BitMode,
510
  GIFBS_HasWAITPKG_Not64BitMode,
511
  GIFBS_Not64BitMode_OptForSize,
512
  GIFBS_NotWin64WithoutFP_OptForMinSize,
513
  GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES,
514
  GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ,
515
};
516
const static PredicateBitset FeatureBitsets[] {
517
  {}, // GIFBS_Invalid
518
  {Feature_FPStackf32Bit, },
519
  {Feature_FPStackf64Bit, },
520
  {Feature_Has3DNowBit, },
521
  {Feature_HasAVXBit, },
522
  {Feature_HasAVX1OnlyBit, },
523
  {Feature_HasAVX2Bit, },
524
  {Feature_HasAVX512Bit, },
525
  {Feature_HasBMIBit, },
526
  {Feature_HasBMI2Bit, },
527
  {Feature_HasBWIBit, },
528
  {Feature_HasDQIBit, },
529
  {Feature_HasLWPBit, },
530
  {Feature_HasMFenceBit, },
531
  {Feature_HasMMXBit, },
532
  {Feature_HasMOVBEBit, },
533
  {Feature_HasPTWRITEBit, },
534
  {Feature_HasRTMBit, },
535
  {Feature_HasSHABit, },
536
  {Feature_HasSSE1Bit, },
537
  {Feature_HasSSE2Bit, },
538
  {Feature_HasSSE42Bit, },
539
  {Feature_HasSSE4ABit, },
540
  {Feature_HasTBMBit, },
541
  {Feature_HasVLXBit, },
542
  {Feature_HasWAITPKGBit, },
543
  {Feature_HasWBNOINVDBit, },
544
  {Feature_HasXOPBit, },
545
  {Feature_In64BitModeBit, },
546
  {Feature_NoDQIBit, },
547
  {Feature_Not64BitModeBit, },
548
  {Feature_UseAVXBit, },
549
  {Feature_UseIncDecBit, },
550
  {Feature_UseSSE1Bit, },
551
  {Feature_UseSSE2Bit, },
552
  {Feature_UseSSE41Bit, },
553
  {Feature_UseSSSE3Bit, },
554
  {Feature_HasAESBit, Feature_HasAVXBit, },
555
  {Feature_HasAESBit, Feature_NoAVXBit, },
556
  {Feature_HasAVXBit, Feature_NoVLXBit, },
557
  {Feature_HasAVXBit, Feature_NoVLX_Or_NoBWIBit, },
558
  {Feature_HasAVX2Bit, Feature_NoVLXBit, },
559
  {Feature_HasAVX2Bit, Feature_NoVLX_Or_NoBWIBit, },
560
  {Feature_HasAVX512Bit, Feature_HasVAESBit, },
561
  {Feature_HasAVX512Bit, Feature_HasVLXBit, },
562
  {Feature_HasAVX512Bit, Feature_HasVPCLMULQDQBit, },
563
  {Feature_HasBWIBit, Feature_HasVLXBit, },
564
  {Feature_HasDQIBit, Feature_HasVLXBit, },
565
  {Feature_HasDQIBit, Feature_NoBWIBit, },
566
  {Feature_HasFSGSBaseBit, Feature_In64BitModeBit, },
567
  {Feature_HasPCLMULBit, Feature_NoAVXBit, },
568
  {Feature_HasPTWRITEBit, Feature_In64BitModeBit, },
569
  {Feature_HasRDPIDBit, Feature_Not64BitModeBit, },
570
  {Feature_HasSSE2Bit, Feature_NoAVX512Bit, },
571
  {Feature_HasVAESBit, Feature_HasVLXBit, },
572
  {Feature_HasVAESBit, Feature_NoVLXBit, },
573
  {Feature_HasVLXBit, Feature_HasVPCLMULQDQBit, },
574
  {Feature_HasVPCLMULQDQBit, Feature_NoVLXBit, },
575
  {Feature_HasWAITPKGBit, Feature_In64BitModeBit, },
576
  {Feature_HasWAITPKGBit, Feature_Not64BitModeBit, },
577
  {Feature_Not64BitModeBit, Feature_OptForSizeBit, },
578
  {Feature_NotWin64WithoutFPBit, Feature_OptForMinSizeBit, },
579
  {Feature_HasAESBit, Feature_HasAVXBit, Feature_NoVLX_Or_NoVAESBit, },
580
  {Feature_HasAVXBit, Feature_HasPCLMULBit, Feature_NoVLX_Or_NoVPCLMULQDQBit, },
581
};
582
583
// ComplexPattern predicates.
584
enum {
585
  GICP_Invalid,
586
};
587
// See constructor for table contents
588
589
// PatFrag predicates.
590
enum {
591
  GIPFP_I64_Predicate_AndMask64 = GIPFP_I64_Invalid + 1,
592
  GIPFP_I64_Predicate_BTCBTSMask64,
593
  GIPFP_I64_Predicate_BTRMask64,
594
  GIPFP_I64_Predicate_PrefetchWT1Level,
595
  GIPFP_I64_Predicate_i16immSExt8,
596
  GIPFP_I64_Predicate_i32immSExt8,
597
  GIPFP_I64_Predicate_i64immSExt32,
598
  GIPFP_I64_Predicate_i64immSExt8,
599
  GIPFP_I64_Predicate_i64immZExt32,
600
  GIPFP_I64_Predicate_i64immZExt32SExt8,
601
  GIPFP_I64_Predicate_immShift16,
602
  GIPFP_I64_Predicate_immShift32,
603
  GIPFP_I64_Predicate_immShift64,
604
  GIPFP_I64_Predicate_immShift8,
605
  GIPFP_I64_Predicate_immff00_ffff,
606
};
607
60
bool X86InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
608
60
  switch (PredicateID) {
609
60
  case GIPFP_I64_Predicate_AndMask64: {
610
0
    
611
0
  return isMask_64(Imm) && !isUInt<32>(Imm);
612
60
613
60
    
llvm_unreachable0
("ImmediateCode should have returned");
614
60
    
return false0
;
615
60
  }
616
60
  case GIPFP_I64_Predicate_BTCBTSMask64: {
617
0
    
618
0
  return !isInt<32>(Imm) && isPowerOf2_64(Imm);
619
60
620
60
    
llvm_unreachable0
("ImmediateCode should have returned");
621
60
    
return false0
;
622
60
  }
623
60
  case GIPFP_I64_Predicate_BTRMask64: {
624
0
    
625
0
  return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);
626
60
627
60
    
llvm_unreachable0
("ImmediateCode should have returned");
628
60
    
return false0
;
629
60
  }
630
60
  case GIPFP_I64_Predicate_PrefetchWT1Level: {
631
0
    
632
0
  return Imm < 3;
633
60
634
60
    
llvm_unreachable0
("ImmediateCode should have returned");
635
60
    
return false0
;
636
60
  }
637
60
  case GIPFP_I64_Predicate_i16immSExt8: {
638
5
     return isInt<8>(Imm); 
639
60
    
llvm_unreachable0
("ImmediateCode should have returned");
640
60
    
return false0
;
641
60
  }
642
60
  case GIPFP_I64_Predicate_i32immSExt8: {
643
10
     return isInt<8>(Imm); 
644
60
    
llvm_unreachable0
("ImmediateCode should have returned");
645
60
    
return false0
;
646
60
  }
647
60
  case GIPFP_I64_Predicate_i64immSExt32: {
648
41
     return isInt<32>(Imm); 
649
60
    
llvm_unreachable0
("ImmediateCode should have returned");
650
60
    
return false0
;
651
60
  }
652
60
  case GIPFP_I64_Predicate_i64immSExt8: {
653
4
     return isInt<8>(Imm); 
654
60
    
llvm_unreachable0
("ImmediateCode should have returned");
655
60
    
return false0
;
656
60
  }
657
60
  case GIPFP_I64_Predicate_i64immZExt32: {
658
0
     return isUInt<32>(Imm); 
659
60
    
llvm_unreachable0
("ImmediateCode should have returned");
660
60
    
return false0
;
661
60
  }
662
60
  case GIPFP_I64_Predicate_i64immZExt32SExt8: {
663
0
    
664
0
  return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
665
60
666
60
    
llvm_unreachable0
("ImmediateCode should have returned");
667
60
    
return false0
;
668
60
  }
669
60
  case GIPFP_I64_Predicate_immShift16: {
670
0
    
671
0
  return countTrailingOnes<uint64_t>(Imm) >= 4;
672
60
673
60
    
llvm_unreachable0
("ImmediateCode should have returned");
674
60
    
return false0
;
675
60
  }
676
60
  case GIPFP_I64_Predicate_immShift32: {
677
0
    
678
0
  return countTrailingOnes<uint64_t>(Imm) >= 5;
679
60
680
60
    
llvm_unreachable0
("ImmediateCode should have returned");
681
60
    
return false0
;
682
60
  }
683
60
  case GIPFP_I64_Predicate_immShift64: {
684
0
    
685
0
  return countTrailingOnes<uint64_t>(Imm) >= 6;
686
60
687
60
    
llvm_unreachable0
("ImmediateCode should have returned");
688
60
    
return false0
;
689
60
  }
690
60
  case GIPFP_I64_Predicate_immShift8: {
691
0
    
692
0
  return countTrailingOnes<uint64_t>(Imm) >= 3;
693
60
694
60
    
llvm_unreachable0
("ImmediateCode should have returned");
695
60
    
return false0
;
696
60
  }
697
60
  case GIPFP_I64_Predicate_immff00_ffff: {
698
0
    
699
0
  return Imm >= 0xff00 && Imm <= 0xffff;
700
60
701
60
    
llvm_unreachable0
("ImmediateCode should have returned");
702
60
    
return false0
;
703
0
  }
704
0
  }
705
0
  llvm_unreachable("Unknown predicate");
706
0
  return false;
707
0
}
708
// PatFrag predicates.
709
enum {
710
  GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1,
711
  GIPFP_APFloat_Predicate_fpimm1,
712
  GIPFP_APFloat_Predicate_fpimmneg0,
713
  GIPFP_APFloat_Predicate_fpimmneg1,
714
};
715
5
bool X86InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
716
5
  switch (PredicateID) {
717
5
  case GIPFP_APFloat_Predicate_fpimm0: {
718
5
    
719
5
  return Imm.isExactlyValue(+0.0);
720
5
721
5
    
llvm_unreachable0
("ImmediateCode should have returned");
722
5
    
return false0
;
723
5
  }
724
5
  case GIPFP_APFloat_Predicate_fpimm1: {
725
0
    
726
0
  return Imm.isExactlyValue(+1.0);
727
5
728
5
    
llvm_unreachable0
("ImmediateCode should have returned");
729
5
    
return false0
;
730
5
  }
731
5
  case GIPFP_APFloat_Predicate_fpimmneg0: {
732
0
    
733
0
  return Imm.isExactlyValue(-0.0);
734
5
735
5
    
llvm_unreachable0
("ImmediateCode should have returned");
736
5
    
return false0
;
737
5
  }
738
5
  case GIPFP_APFloat_Predicate_fpimmneg1: {
739
0
    
740
0
  return Imm.isExactlyValue(-1.0);
741
5
742
5
    
llvm_unreachable0
("ImmediateCode should have returned");
743
5
    
return false0
;
744
0
  }
745
0
  }
746
0
  llvm_unreachable("Unknown predicate");
747
0
  return false;
748
0
}
749
0
bool X86InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
750
0
  llvm_unreachable("Unknown predicate");
751
0
  return false;
752
0
}
753
0
bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
754
0
  const MachineFunction &MF = *MI.getParent()->getParent();
755
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
756
0
  (void)MRI;
757
0
  llvm_unreachable("Unknown predicate");
758
0
  return false;
759
0
}
760
761
X86InstructionSelector::ComplexMatcherMemFn
762
X86InstructionSelector::ComplexPredicateFns[] = {
763
  nullptr, // GICP_Invalid
764
};
765
766
// Custom renderers.
767
enum {
768
  GICR_Invalid,
769
};
770
X86InstructionSelector::CustomRendererFn
771
X86InstructionSelector::CustomRenderers[] = {
772
  nullptr, // GICP_Invalid
773
};
774
775
1.91k
bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
776
1.91k
  MachineFunction &MF = *I.getParent()->getParent();
777
1.91k
  MachineRegisterInfo &MRI = MF.getRegInfo();
778
1.91k
  // FIXME: This should be computed on a per-function basis rather than per-insn.
779
1.91k
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
780
1.91k
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
781
1.91k
  NewMIVector OutMIs;
782
1.91k
  State.MIs.clear();
783
1.91k
  State.MIs.push_back(&I);
784
1.91k
785
1.91k
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
786
697
    return true;
787
697
  }
788
1.21k
789
1.21k
  return false;
790
1.21k
}
791
792
1.91k
const int64_t *X86InstructionSelector::getMatchTable() const {
793
1.91k
  constexpr static int64_t MatchTable0[] = {
794
1.91k
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 31*/ 32754,
795
1.91k
    /*TargetOpcode::G_ADD*//*Label 0*/ 95,
796
1.91k
    /*TargetOpcode::G_SUB*//*Label 1*/ 1712,
797
1.91k
    /*TargetOpcode::G_MUL*//*Label 2*/ 2793, 0, 0, 0, 0,
798
1.91k
    /*TargetOpcode::G_AND*//*Label 3*/ 3559,
799
1.91k
    /*TargetOpcode::G_OR*//*Label 4*/ 6671,
800
1.91k
    /*TargetOpcode::G_XOR*//*Label 5*/ 9342, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
801
1.91k
    /*TargetOpcode::G_BITCAST*//*Label 6*/ 11315, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
802
1.91k
    /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 14608,
803
1.91k
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 22151,
804
1.91k
    /*TargetOpcode::G_ANYEXT*//*Label 9*/ 23582,
805
1.91k
    /*TargetOpcode::G_TRUNC*//*Label 10*/ 23698,
806
1.91k
    /*TargetOpcode::G_CONSTANT*//*Label 11*/ 24033,
807
1.91k
    /*TargetOpcode::G_FCONSTANT*//*Label 12*/ 24236, 0, 0,
808
1.91k
    /*TargetOpcode::G_SEXT*//*Label 13*/ 24429,
809
1.91k
    /*TargetOpcode::G_ZEXT*//*Label 14*/ 24933,
810
1.91k
    /*TargetOpcode::G_SHL*//*Label 15*/ 25068,
811
1.91k
    /*TargetOpcode::G_LSHR*//*Label 16*/ 25793,
812
1.91k
    /*TargetOpcode::G_ASHR*//*Label 17*/ 26624, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
813
1.91k
    /*TargetOpcode::G_FADD*//*Label 18*/ 27281,
814
1.91k
    /*TargetOpcode::G_FSUB*//*Label 19*/ 27894,
815
1.91k
    /*TargetOpcode::G_FMUL*//*Label 20*/ 28507, 0,
816
1.91k
    /*TargetOpcode::G_FDIV*//*Label 21*/ 29120, 0, 0, 0, 0, 0, 0,
817
1.91k
    /*TargetOpcode::G_FNEG*//*Label 22*/ 29733,
818
1.91k
    /*TargetOpcode::G_FPEXT*//*Label 23*/ 29822,
819
1.91k
    /*TargetOpcode::G_FPTRUNC*//*Label 24*/ 30098,
820
1.91k
    /*TargetOpcode::G_FPTOSI*//*Label 25*/ 30383,
821
1.91k
    /*TargetOpcode::G_FPTOUI*//*Label 26*/ 31013,
822
1.91k
    /*TargetOpcode::G_SITOFP*//*Label 27*/ 31367,
823
1.91k
    /*TargetOpcode::G_UITOFP*//*Label 28*/ 32197, 0, 0, 0,
824
1.91k
    /*TargetOpcode::G_BR*//*Label 29*/ 32651, 0, 0, 0,
825
1.91k
    /*TargetOpcode::G_BSWAP*//*Label 30*/ 32664,
826
1.91k
    // Label 0: @95
827
1.91k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 48*/ 1711,
828
1.91k
    /*GILLT_s8*//*Label 32*/ 125,
829
1.91k
    /*GILLT_s16*//*Label 33*/ 239,
830
1.91k
    /*GILLT_s32*//*Label 34*/ 411,
831
1.91k
    /*GILLT_s64*//*Label 35*/ 583, 0, 0, 0,
832
1.91k
    /*GILLT_v2s64*//*Label 36*/ 783, 0,
833
1.91k
    /*GILLT_v4s32*//*Label 37*/ 864,
834
1.91k
    /*GILLT_v4s64*//*Label 38*/ 1067, 0,
835
1.91k
    /*GILLT_v8s16*//*Label 39*/ 1125,
836
1.91k
    /*GILLT_v8s32*//*Label 40*/ 1328,
837
1.91k
    /*GILLT_v8s64*//*Label 41*/ 1386, 0,
838
1.91k
    /*GILLT_v16s8*//*Label 42*/ 1418,
839
1.91k
    /*GILLT_v16s16*//*Label 43*/ 1499,
840
1.91k
    /*GILLT_v16s32*//*Label 44*/ 1557, 0,
841
1.91k
    /*GILLT_v32s8*//*Label 45*/ 1589,
842
1.91k
    /*GILLT_v32s16*//*Label 46*/ 1647, 0,
843
1.91k
    /*GILLT_v64s8*//*Label 47*/ 1679,
844
1.91k
    // Label 32: @125
845
1.91k
    GIM_Try, /*On fail goto*//*Label 49*/ 238,
846
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
847
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
848
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
849
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
850
1.91k
      GIM_Try, /*On fail goto*//*Label 50*/ 167, // Rule ID 15950 //
851
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
852
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
853
1.91k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, 1:{ *:[i8] })  =>  (INC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
854
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r,
855
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
856
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
857
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
858
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
859
1.91k
        // GIR_Coverage, 15950,
860
1.91k
        GIR_Done,
861
1.91k
      // Label 50: @167
862
1.91k
      GIM_Try, /*On fail goto*//*Label 51*/ 191, // Rule ID 15954 //
863
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
864
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
865
1.91k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, -1:{ *:[i8] })  =>  (DEC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src)
866
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r,
867
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
868
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
869
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
870
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
871
1.91k
        // GIR_Coverage, 15954,
872
1.91k
        GIR_Done,
873
1.91k
      // Label 51: @191
874
1.91k
      GIM_Try, /*On fail goto*//*Label 52*/ 221, // Rule ID 15904 //
875
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
876
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
877
1.91k
        // MIs[1] Operand 1
878
1.91k
        // No operand predicates
879
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
880
1.91k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
881
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri,
882
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
883
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
884
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
885
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
886
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
887
1.91k
        // GIR_Coverage, 15904,
888
1.91k
        GIR_Done,
889
1.91k
      // Label 52: @221
890
1.91k
      GIM_Try, /*On fail goto*//*Label 53*/ 237, // Rule ID 15896 //
891
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
892
1.91k
        // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
893
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD8rr,
894
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
895
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
896
1.91k
        // GIR_Coverage, 15896,
897
1.91k
        GIR_Done,
898
1.91k
      // Label 53: @237
899
1.91k
      GIM_Reject,
900
1.91k
    // Label 49: @238
901
1.91k
    GIM_Reject,
902
1.91k
    // Label 33: @239
903
1.91k
    GIM_Try, /*On fail goto*//*Label 54*/ 410,
904
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
905
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
906
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
907
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
908
1.91k
      GIM_Try, /*On fail goto*//*Label 55*/ 282, // Rule ID 15762 //
909
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
910
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, 128:{ *:[i16] })  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -128:{ *:[i16] })
911
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
912
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
913
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
914
1.91k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
915
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
916
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
917
1.91k
        // GIR_Coverage, 15762,
918
1.91k
        GIR_Done,
919
1.91k
      // Label 55: @282
920
1.91k
      GIM_Try, /*On fail goto*//*Label 56*/ 306, // Rule ID 15951 //
921
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
922
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
923
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, 1:{ *:[i16] })  =>  (INC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
924
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r,
925
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
926
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
927
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
928
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
929
1.91k
        // GIR_Coverage, 15951,
930
1.91k
        GIR_Done,
931
1.91k
      // Label 56: @306
932
1.91k
      GIM_Try, /*On fail goto*//*Label 57*/ 330, // Rule ID 15955 //
933
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
934
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
935
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, -1:{ *:[i16] })  =>  (DEC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src)
936
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r,
937
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
938
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
939
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
940
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
941
1.91k
        // GIR_Coverage, 15955,
942
1.91k
        GIR_Done,
943
1.91k
      // Label 57: @330
944
1.91k
      GIM_Try, /*On fail goto*//*Label 58*/ 363, // Rule ID 15907 //
945
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
946
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
947
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
948
1.91k
        // MIs[1] Operand 1
949
1.91k
        // No operand predicates
950
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
951
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (ADD16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
952
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8,
953
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
954
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
955
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
956
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
957
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
958
1.91k
        // GIR_Coverage, 15907,
959
1.91k
        GIR_Done,
960
1.91k
      // Label 58: @363
961
1.91k
      GIM_Try, /*On fail goto*//*Label 59*/ 393, // Rule ID 15905 //
962
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
963
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
964
1.91k
        // MIs[1] Operand 1
965
1.91k
        // No operand predicates
966
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
967
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
968
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri,
969
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
970
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
971
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
972
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
973
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
974
1.91k
        // GIR_Coverage, 15905,
975
1.91k
        GIR_Done,
976
1.91k
      // Label 59: @393
977
1.91k
      GIM_Try, /*On fail goto*//*Label 60*/ 409, // Rule ID 15897 //
978
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
979
1.91k
        // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
980
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD16rr,
981
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
982
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
983
1.91k
        // GIR_Coverage, 15897,
984
1.91k
        GIR_Done,
985
1.91k
      // Label 60: @409
986
1.91k
      GIM_Reject,
987
1.91k
    // Label 54: @410
988
1.91k
    GIM_Reject,
989
1.91k
    // Label 34: @411
990
1.91k
    GIM_Try, /*On fail goto*//*Label 61*/ 582,
991
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
992
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
993
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
994
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
995
1.91k
      GIM_Try, /*On fail goto*//*Label 62*/ 454, // Rule ID 15764 //
996
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
997
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, 128:{ *:[i32] })  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -128:{ *:[i32] })
998
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
999
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1000
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1001
1.91k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
1002
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1003
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1004
1.91k
        // GIR_Coverage, 15764,
1005
1.91k
        GIR_Done,
1006
1.91k
      // Label 62: @454
1007
1.91k
      GIM_Try, /*On fail goto*//*Label 63*/ 478, // Rule ID 15952 //
1008
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1009
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1010
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (INC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1011
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r,
1012
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1013
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1014
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1015
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1016
1.91k
        // GIR_Coverage, 15952,
1017
1.91k
        GIR_Done,
1018
1.91k
      // Label 63: @478
1019
1.91k
      GIM_Try, /*On fail goto*//*Label 64*/ 502, // Rule ID 15956 //
1020
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1021
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1022
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })  =>  (DEC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
1023
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r,
1024
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1025
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1026
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1027
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1028
1.91k
        // GIR_Coverage, 15956,
1029
1.91k
        GIR_Done,
1030
1.91k
      // Label 64: @502
1031
1.91k
      GIM_Try, /*On fail goto*//*Label 65*/ 535, // Rule ID 15908 //
1032
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1033
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1034
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1035
1.91k
        // MIs[1] Operand 1
1036
1.91k
        // No operand predicates
1037
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1038
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (ADD32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1039
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8,
1040
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1041
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1042
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1043
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1044
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1045
1.91k
        // GIR_Coverage, 15908,
1046
1.91k
        GIR_Done,
1047
1.91k
      // Label 65: @535
1048
1.91k
      GIM_Try, /*On fail goto*//*Label 66*/ 565, // Rule ID 15906 //
1049
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1050
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1051
1.91k
        // MIs[1] Operand 1
1052
1.91k
        // No operand predicates
1053
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1054
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1055
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri,
1056
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1057
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1058
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1059
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1060
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1061
1.91k
        // GIR_Coverage, 15906,
1062
1.91k
        GIR_Done,
1063
1.91k
      // Label 66: @565
1064
1.91k
      GIM_Try, /*On fail goto*//*Label 67*/ 581, // Rule ID 15898 //
1065
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1066
1.91k
        // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1067
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD32rr,
1068
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1069
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1070
1.91k
        // GIR_Coverage, 15898,
1071
1.91k
        GIR_Done,
1072
1.91k
      // Label 67: @581
1073
1.91k
      GIM_Reject,
1074
1.91k
    // Label 61: @582
1075
1.91k
    GIM_Reject,
1076
1.91k
    // Label 35: @583
1077
1.91k
    GIM_Try, /*On fail goto*//*Label 68*/ 782,
1078
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1079
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1080
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1081
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1082
1.91k
      GIM_Try, /*On fail goto*//*Label 69*/ 626, // Rule ID 15766 //
1083
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128,
1084
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 128:{ *:[i64] })  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -128:{ *:[i64] })
1085
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1086
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1087
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1088
1.91k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-128,
1089
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1090
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1091
1.91k
        // GIR_Coverage, 15766,
1092
1.91k
        GIR_Done,
1093
1.91k
      // Label 69: @626
1094
1.91k
      GIM_Try, /*On fail goto*//*Label 70*/ 651, // Rule ID 15768 //
1095
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 2147483648,
1096
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 2147483648:{ *:[i64] })  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -2147483648:{ *:[i64] })
1097
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1098
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1099
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1100
1.91k
        GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648,
1101
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1102
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1103
1.91k
        // GIR_Coverage, 15768,
1104
1.91k
        GIR_Done,
1105
1.91k
      // Label 70: @651
1106
1.91k
      GIM_Try, /*On fail goto*//*Label 71*/ 675, // Rule ID 15953 //
1107
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1108
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
1109
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })  =>  (INC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1110
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r,
1111
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1112
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1113
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1114
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1115
1.91k
        // GIR_Coverage, 15953,
1116
1.91k
        GIR_Done,
1117
1.91k
      // Label 71: @675
1118
1.91k
      GIM_Try, /*On fail goto*//*Label 72*/ 699, // Rule ID 15957 //
1119
1.91k
        GIM_CheckFeatures, GIFBS_UseIncDec,
1120
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
1121
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })  =>  (DEC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
1122
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r,
1123
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1124
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1125
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1126
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1127
1.91k
        // GIR_Coverage, 15957,
1128
1.91k
        GIR_Done,
1129
1.91k
      // Label 72: @699
1130
1.91k
      GIM_Try, /*On fail goto*//*Label 73*/ 732, // Rule ID 15909 //
1131
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1132
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1133
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1134
1.91k
        // MIs[1] Operand 1
1135
1.91k
        // No operand predicates
1136
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1137
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (ADD64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1138
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8,
1139
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1140
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1141
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1142
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1143
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1144
1.91k
        // GIR_Coverage, 15909,
1145
1.91k
        GIR_Done,
1146
1.91k
      // Label 73: @732
1147
1.91k
      GIM_Try, /*On fail goto*//*Label 74*/ 765, // Rule ID 15910 //
1148
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1149
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1150
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1151
1.91k
        // MIs[1] Operand 1
1152
1.91k
        // No operand predicates
1153
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1154
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (ADD64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1155
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32,
1156
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1157
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1158
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1159
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1160
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1161
1.91k
        // GIR_Coverage, 15910,
1162
1.91k
        GIR_Done,
1163
1.91k
      // Label 74: @765
1164
1.91k
      GIM_Try, /*On fail goto*//*Label 75*/ 781, // Rule ID 15899 //
1165
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1166
1.91k
        // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1167
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr,
1168
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1169
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1170
1.91k
        // GIR_Coverage, 15899,
1171
1.91k
        GIR_Done,
1172
1.91k
      // Label 75: @781
1173
1.91k
      GIM_Reject,
1174
1.91k
    // Label 68: @782
1175
1.91k
    GIM_Reject,
1176
1.91k
    // Label 36: @783
1177
1.91k
    GIM_Try, /*On fail goto*//*Label 76*/ 863,
1178
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1179
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1180
1.91k
      GIM_Try, /*On fail goto*//*Label 77*/ 816, // Rule ID 1823 //
1181
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1182
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1183
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1184
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1185
1.91k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1186
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQrr,
1187
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1188
1.91k
        // GIR_Coverage, 1823,
1189
1.91k
        GIR_Done,
1190
1.91k
      // Label 77: @816
1191
1.91k
      GIM_Try, /*On fail goto*//*Label 78*/ 839, // Rule ID 1825 //
1192
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1193
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1194
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1195
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1196
1.91k
        // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1197
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDQrr,
1198
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1199
1.91k
        // GIR_Coverage, 1825,
1200
1.91k
        GIR_Done,
1201
1.91k
      // Label 78: @839
1202
1.91k
      GIM_Try, /*On fail goto*//*Label 79*/ 862, // Rule ID 3837 //
1203
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1204
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1205
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1206
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1207
1.91k
        // (add:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPADDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1208
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ128rr,
1209
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1210
1.91k
        // GIR_Coverage, 3837,
1211
1.91k
        GIR_Done,
1212
1.91k
      // Label 79: @862
1213
1.91k
      GIM_Reject,
1214
1.91k
    // Label 76: @863
1215
1.91k
    GIM_Reject,
1216
1.91k
    // Label 37: @864
1217
1.91k
    GIM_Try, /*On fail goto*//*Label 80*/ 1066,
1218
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1219
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1220
1.91k
      GIM_Try, /*On fail goto*//*Label 81*/ 935, // Rule ID 12390 //
1221
1.91k
        GIM_CheckFeatures, GIFBS_HasXOP,
1222
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1223
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1224
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1225
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1226
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1227
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1228
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1229
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1230
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1231
1.91k
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3)  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1232
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1233
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1234
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1235
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1236
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1237
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1238
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1239
1.91k
        // GIR_Coverage, 12390,
1240
1.91k
        GIR_Done,
1241
1.91k
      // Label 81: @935
1242
1.91k
      GIM_Try, /*On fail goto*//*Label 82*/ 996, // Rule ID 18099 //
1243
1.91k
        GIM_CheckFeatures, GIFBS_HasXOP,
1244
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1245
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1246
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1247
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1248
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1249
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1250
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1251
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1252
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1253
1.91k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2))  =>  (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3)
1254
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr,
1255
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1256
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1257
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1258
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1259
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1260
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1261
1.91k
        // GIR_Coverage, 18099,
1262
1.91k
        GIR_Done,
1263
1.91k
      // Label 82: @996
1264
1.91k
      GIM_Try, /*On fail goto*//*Label 83*/ 1019, // Rule ID 1817 //
1265
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1266
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1267
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1268
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1269
1.91k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1270
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDrr,
1271
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1272
1.91k
        // GIR_Coverage, 1817,
1273
1.91k
        GIR_Done,
1274
1.91k
      // Label 83: @1019
1275
1.91k
      GIM_Try, /*On fail goto*//*Label 84*/ 1042, // Rule ID 1819 //
1276
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1277
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1278
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1279
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1280
1.91k
        // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1281
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDDrr,
1282
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1283
1.91k
        // GIR_Coverage, 1819,
1284
1.91k
        GIR_Done,
1285
1.91k
      // Label 84: @1042
1286
1.91k
      GIM_Try, /*On fail goto*//*Label 85*/ 1065, // Rule ID 3864 //
1287
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1288
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1289
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1290
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1291
1.91k
        // (add:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPADDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1292
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ128rr,
1293
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1294
1.91k
        // GIR_Coverage, 3864,
1295
1.91k
        GIR_Done,
1296
1.91k
      // Label 85: @1065
1297
1.91k
      GIM_Reject,
1298
1.91k
    // Label 80: @1066
1299
1.91k
    GIM_Reject,
1300
1.91k
    // Label 38: @1067
1301
1.91k
    GIM_Try, /*On fail goto*//*Label 86*/ 1124,
1302
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1303
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1304
1.91k
      GIM_Try, /*On fail goto*//*Label 87*/ 1100, // Rule ID 1827 //
1305
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1306
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1307
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1308
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1309
1.91k
        // (add:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPADDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1310
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQYrr,
1311
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1312
1.91k
        // GIR_Coverage, 1827,
1313
1.91k
        GIR_Done,
1314
1.91k
      // Label 87: @1100
1315
1.91k
      GIM_Try, /*On fail goto*//*Label 88*/ 1123, // Rule ID 3828 //
1316
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1317
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1318
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1319
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1320
1.91k
        // (add:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPADDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1321
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ256rr,
1322
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1323
1.91k
        // GIR_Coverage, 3828,
1324
1.91k
        GIR_Done,
1325
1.91k
      // Label 88: @1123
1326
1.91k
      GIM_Reject,
1327
1.91k
    // Label 86: @1124
1328
1.91k
    GIM_Reject,
1329
1.91k
    // Label 39: @1125
1330
1.91k
    GIM_Try, /*On fail goto*//*Label 89*/ 1327,
1331
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1332
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1333
1.91k
      GIM_Try, /*On fail goto*//*Label 90*/ 1196, // Rule ID 12389 //
1334
1.91k
        GIM_CheckFeatures, GIFBS_HasXOP,
1335
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1336
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1337
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1338
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1339
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1340
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1341
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1342
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1343
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1344
1.91k
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3)  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1345
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1346
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1347
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1348
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1349
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
1350
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1351
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1352
1.91k
        // GIR_Coverage, 12389,
1353
1.91k
        GIR_Done,
1354
1.91k
      // Label 90: @1196
1355
1.91k
      GIM_Try, /*On fail goto*//*Label 91*/ 1257, // Rule ID 18098 //
1356
1.91k
        GIM_CheckFeatures, GIFBS_HasXOP,
1357
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1358
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1359
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1360
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1361
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1362
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1363
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID,
1364
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID,
1365
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1366
1.91k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2))  =>  (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3)
1367
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr,
1368
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1369
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
1370
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
1371
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
1372
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1373
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1374
1.91k
        // GIR_Coverage, 18098,
1375
1.91k
        GIR_Done,
1376
1.91k
      // Label 91: @1257
1377
1.91k
      GIM_Try, /*On fail goto*//*Label 92*/ 1280, // Rule ID 1811 //
1378
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1379
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1380
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1381
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1382
1.91k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1383
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWrr,
1384
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1385
1.91k
        // GIR_Coverage, 1811,
1386
1.91k
        GIR_Done,
1387
1.91k
      // Label 92: @1280
1388
1.91k
      GIM_Try, /*On fail goto*//*Label 93*/ 1303, // Rule ID 1813 //
1389
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1390
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1391
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1392
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1393
1.91k
        // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1394
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDWrr,
1395
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1396
1.91k
        // GIR_Coverage, 1813,
1397
1.91k
        GIR_Done,
1398
1.91k
      // Label 93: @1303
1399
1.91k
      GIM_Try, /*On fail goto*//*Label 94*/ 1326, // Rule ID 3885 //
1400
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1401
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1402
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1403
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1404
1.91k
        // (add:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPADDWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1405
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ128rr,
1406
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1407
1.91k
        // GIR_Coverage, 3885,
1408
1.91k
        GIR_Done,
1409
1.91k
      // Label 94: @1326
1410
1.91k
      GIM_Reject,
1411
1.91k
    // Label 89: @1327
1412
1.91k
    GIM_Reject,
1413
1.91k
    // Label 40: @1328
1414
1.91k
    GIM_Try, /*On fail goto*//*Label 95*/ 1385,
1415
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1416
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1417
1.91k
      GIM_Try, /*On fail goto*//*Label 96*/ 1361, // Rule ID 1821 //
1418
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1419
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1420
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1421
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1422
1.91k
        // (add:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPADDDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1423
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDYrr,
1424
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1425
1.91k
        // GIR_Coverage, 1821,
1426
1.91k
        GIR_Done,
1427
1.91k
      // Label 96: @1361
1428
1.91k
      GIM_Try, /*On fail goto*//*Label 97*/ 1384, // Rule ID 3855 //
1429
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1430
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1431
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1432
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1433
1.91k
        // (add:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPADDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1434
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ256rr,
1435
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1436
1.91k
        // GIR_Coverage, 3855,
1437
1.91k
        GIR_Done,
1438
1.91k
      // Label 97: @1384
1439
1.91k
      GIM_Reject,
1440
1.91k
    // Label 95: @1385
1441
1.91k
    GIM_Reject,
1442
1.91k
    // Label 41: @1386
1443
1.91k
    GIM_Try, /*On fail goto*//*Label 98*/ 1417, // Rule ID 3819 //
1444
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1445
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
1446
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
1447
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1448
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1449
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1450
1.91k
      // (add:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPADDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
1451
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZrr,
1452
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1453
1.91k
      // GIR_Coverage, 3819,
1454
1.91k
      GIR_Done,
1455
1.91k
    // Label 98: @1417
1456
1.91k
    GIM_Reject,
1457
1.91k
    // Label 42: @1418
1458
1.91k
    GIM_Try, /*On fail goto*//*Label 99*/ 1498,
1459
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1460
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1461
1.91k
      GIM_Try, /*On fail goto*//*Label 100*/ 1451, // Rule ID 1805 //
1462
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1463
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1464
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1465
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1466
1.91k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1467
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBrr,
1468
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1469
1.91k
        // GIR_Coverage, 1805,
1470
1.91k
        GIR_Done,
1471
1.91k
      // Label 100: @1451
1472
1.91k
      GIM_Try, /*On fail goto*//*Label 101*/ 1474, // Rule ID 1807 //
1473
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1474
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1475
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1476
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1477
1.91k
        // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
1478
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDBrr,
1479
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1480
1.91k
        // GIR_Coverage, 1807,
1481
1.91k
        GIR_Done,
1482
1.91k
      // Label 101: @1474
1483
1.91k
      GIM_Try, /*On fail goto*//*Label 102*/ 1497, // Rule ID 3903 //
1484
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1485
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1486
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1487
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1488
1.91k
        // (add:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPADDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
1489
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ128rr,
1490
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1491
1.91k
        // GIR_Coverage, 3903,
1492
1.91k
        GIR_Done,
1493
1.91k
      // Label 102: @1497
1494
1.91k
      GIM_Reject,
1495
1.91k
    // Label 99: @1498
1496
1.91k
    GIM_Reject,
1497
1.91k
    // Label 43: @1499
1498
1.91k
    GIM_Try, /*On fail goto*//*Label 103*/ 1556,
1499
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
1500
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
1501
1.91k
      GIM_Try, /*On fail goto*//*Label 104*/ 1532, // Rule ID 1815 //
1502
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1503
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1504
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1505
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1506
1.91k
        // (add:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPADDWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
1507
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWYrr,
1508
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1509
1.91k
        // GIR_Coverage, 1815,
1510
1.91k
        GIR_Done,
1511
1.91k
      // Label 104: @1532
1512
1.91k
      GIM_Try, /*On fail goto*//*Label 105*/ 1555, // Rule ID 3879 //
1513
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1514
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1515
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1516
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1517
1.91k
        // (add:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPADDWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
1518
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ256rr,
1519
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1520
1.91k
        // GIR_Coverage, 3879,
1521
1.91k
        GIR_Done,
1522
1.91k
      // Label 105: @1555
1523
1.91k
      GIM_Reject,
1524
1.91k
    // Label 103: @1556
1525
1.91k
    GIM_Reject,
1526
1.91k
    // Label 44: @1557
1527
1.91k
    GIM_Try, /*On fail goto*//*Label 106*/ 1588, // Rule ID 3846 //
1528
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1529
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
1530
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
1531
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1532
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1533
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1534
1.91k
      // (add:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPADDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
1535
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZrr,
1536
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1537
1.91k
      // GIR_Coverage, 3846,
1538
1.91k
      GIR_Done,
1539
1.91k
    // Label 106: @1588
1540
1.91k
    GIM_Reject,
1541
1.91k
    // Label 45: @1589
1542
1.91k
    GIM_Try, /*On fail goto*//*Label 107*/ 1646,
1543
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
1544
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
1545
1.91k
      GIM_Try, /*On fail goto*//*Label 108*/ 1622, // Rule ID 1809 //
1546
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
1547
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1548
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1549
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1550
1.91k
        // (add:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPADDBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
1551
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBYrr,
1552
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1553
1.91k
        // GIR_Coverage, 1809,
1554
1.91k
        GIR_Done,
1555
1.91k
      // Label 108: @1622
1556
1.91k
      GIM_Try, /*On fail goto*//*Label 109*/ 1645, // Rule ID 3897 //
1557
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1558
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1559
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1560
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1561
1.91k
        // (add:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPADDBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
1562
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ256rr,
1563
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1564
1.91k
        // GIR_Coverage, 3897,
1565
1.91k
        GIR_Done,
1566
1.91k
      // Label 109: @1645
1567
1.91k
      GIM_Reject,
1568
1.91k
    // Label 107: @1646
1569
1.91k
    GIM_Reject,
1570
1.91k
    // Label 46: @1647
1571
1.91k
    GIM_Try, /*On fail goto*//*Label 110*/ 1678, // Rule ID 3873 //
1572
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
1573
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
1574
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
1575
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1576
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1577
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1578
1.91k
      // (add:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPADDWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
1579
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZrr,
1580
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1581
1.91k
      // GIR_Coverage, 3873,
1582
1.91k
      GIR_Done,
1583
1.91k
    // Label 110: @1678
1584
1.91k
    GIM_Reject,
1585
1.91k
    // Label 47: @1679
1586
1.91k
    GIM_Try, /*On fail goto*//*Label 111*/ 1710, // Rule ID 3891 //
1587
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
1588
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
1589
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
1590
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1591
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1592
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1593
1.91k
      // (add:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPADDBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
1594
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZrr,
1595
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1596
1.91k
      // GIR_Coverage, 3891,
1597
1.91k
      GIR_Done,
1598
1.91k
    // Label 111: @1710
1599
1.91k
    GIM_Reject,
1600
1.91k
    // Label 48: @1711
1601
1.91k
    GIM_Reject,
1602
1.91k
    // Label 1: @1712
1603
1.91k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 128*/ 2792,
1604
1.91k
    /*GILLT_s8*//*Label 112*/ 1742,
1605
1.91k
    /*GILLT_s16*//*Label 113*/ 1808,
1606
1.91k
    /*GILLT_s32*//*Label 114*/ 1907,
1607
1.91k
    /*GILLT_s64*//*Label 115*/ 2006, 0, 0, 0,
1608
1.91k
    /*GILLT_v2s64*//*Label 116*/ 2108, 0,
1609
1.91k
    /*GILLT_v4s32*//*Label 117*/ 2189,
1610
1.91k
    /*GILLT_v4s64*//*Label 118*/ 2270, 0,
1611
1.91k
    /*GILLT_v8s16*//*Label 119*/ 2328,
1612
1.91k
    /*GILLT_v8s32*//*Label 120*/ 2409,
1613
1.91k
    /*GILLT_v8s64*//*Label 121*/ 2467, 0,
1614
1.91k
    /*GILLT_v16s8*//*Label 122*/ 2499,
1615
1.91k
    /*GILLT_v16s16*//*Label 123*/ 2580,
1616
1.91k
    /*GILLT_v16s32*//*Label 124*/ 2638, 0,
1617
1.91k
    /*GILLT_v32s8*//*Label 125*/ 2670,
1618
1.91k
    /*GILLT_v32s16*//*Label 126*/ 2728, 0,
1619
1.91k
    /*GILLT_v64s8*//*Label 127*/ 2760,
1620
1.91k
    // Label 112: @1742
1621
1.91k
    GIM_Try, /*On fail goto*//*Label 129*/ 1807,
1622
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
1623
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
1624
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
1625
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
1626
1.91k
      GIM_Try, /*On fail goto*//*Label 130*/ 1790, // Rule ID 15919 //
1627
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1628
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1629
1.91k
        // MIs[1] Operand 1
1630
1.91k
        // No operand predicates
1631
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1632
1.91k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (SUB8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
1633
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri,
1634
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1635
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1636
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1637
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1638
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639
1.91k
        // GIR_Coverage, 15919,
1640
1.91k
        GIR_Done,
1641
1.91k
      // Label 130: @1790
1642
1.91k
      GIM_Try, /*On fail goto*//*Label 131*/ 1806, // Rule ID 15911 //
1643
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
1644
1.91k
        // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (SUB8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
1645
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB8rr,
1646
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1647
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1648
1.91k
        // GIR_Coverage, 15911,
1649
1.91k
        GIR_Done,
1650
1.91k
      // Label 131: @1806
1651
1.91k
      GIM_Reject,
1652
1.91k
    // Label 129: @1807
1653
1.91k
    GIM_Reject,
1654
1.91k
    // Label 113: @1808
1655
1.91k
    GIM_Try, /*On fail goto*//*Label 132*/ 1906,
1656
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
1657
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
1658
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
1659
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
1660
1.91k
      GIM_Try, /*On fail goto*//*Label 133*/ 1859, // Rule ID 15922 //
1661
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1662
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1663
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
1664
1.91k
        // MIs[1] Operand 1
1665
1.91k
        // No operand predicates
1666
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1667
1.91k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
1668
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8,
1669
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1670
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1671
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1672
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1673
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1674
1.91k
        // GIR_Coverage, 15922,
1675
1.91k
        GIR_Done,
1676
1.91k
      // Label 133: @1859
1677
1.91k
      GIM_Try, /*On fail goto*//*Label 134*/ 1889, // Rule ID 15920 //
1678
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1679
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1680
1.91k
        // MIs[1] Operand 1
1681
1.91k
        // No operand predicates
1682
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1683
1.91k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (SUB16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
1684
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri,
1685
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1686
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1687
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1688
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1689
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1690
1.91k
        // GIR_Coverage, 15920,
1691
1.91k
        GIR_Done,
1692
1.91k
      // Label 134: @1889
1693
1.91k
      GIM_Try, /*On fail goto*//*Label 135*/ 1905, // Rule ID 15912 //
1694
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
1695
1.91k
        // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (SUB16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
1696
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB16rr,
1697
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1698
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1699
1.91k
        // GIR_Coverage, 15912,
1700
1.91k
        GIR_Done,
1701
1.91k
      // Label 135: @1905
1702
1.91k
      GIM_Reject,
1703
1.91k
    // Label 132: @1906
1704
1.91k
    GIM_Reject,
1705
1.91k
    // Label 114: @1907
1706
1.91k
    GIM_Try, /*On fail goto*//*Label 136*/ 2005,
1707
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1708
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1709
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
1710
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
1711
1.91k
      GIM_Try, /*On fail goto*//*Label 137*/ 1958, // Rule ID 15923 //
1712
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1713
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1714
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
1715
1.91k
        // MIs[1] Operand 1
1716
1.91k
        // No operand predicates
1717
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1718
1.91k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
1719
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8,
1720
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1721
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1722
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1723
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1724
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1725
1.91k
        // GIR_Coverage, 15923,
1726
1.91k
        GIR_Done,
1727
1.91k
      // Label 137: @1958
1728
1.91k
      GIM_Try, /*On fail goto*//*Label 138*/ 1988, // Rule ID 15921 //
1729
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1730
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1731
1.91k
        // MIs[1] Operand 1
1732
1.91k
        // No operand predicates
1733
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1734
1.91k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (SUB32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
1735
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri,
1736
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1737
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1738
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1739
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1740
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1741
1.91k
        // GIR_Coverage, 15921,
1742
1.91k
        GIR_Done,
1743
1.91k
      // Label 138: @1988
1744
1.91k
      GIM_Try, /*On fail goto*//*Label 139*/ 2004, // Rule ID 15913 //
1745
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
1746
1.91k
        // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (SUB32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
1747
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB32rr,
1748
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1749
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1750
1.91k
        // GIR_Coverage, 15913,
1751
1.91k
        GIR_Done,
1752
1.91k
      // Label 139: @2004
1753
1.91k
      GIM_Reject,
1754
1.91k
    // Label 136: @2005
1755
1.91k
    GIM_Reject,
1756
1.91k
    // Label 115: @2006
1757
1.91k
    GIM_Try, /*On fail goto*//*Label 140*/ 2107,
1758
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1759
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1760
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
1761
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
1762
1.91k
      GIM_Try, /*On fail goto*//*Label 141*/ 2057, // Rule ID 15924 //
1763
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1764
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1765
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
1766
1.91k
        // MIs[1] Operand 1
1767
1.91k
        // No operand predicates
1768
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1769
1.91k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
1770
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8,
1771
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1772
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1773
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1774
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1775
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1776
1.91k
        // GIR_Coverage, 15924,
1777
1.91k
        GIR_Done,
1778
1.91k
      // Label 141: @2057
1779
1.91k
      GIM_Try, /*On fail goto*//*Label 142*/ 2090, // Rule ID 15925 //
1780
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1781
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1782
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
1783
1.91k
        // MIs[1] Operand 1
1784
1.91k
        // No operand predicates
1785
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1786
1.91k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
1787
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32,
1788
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1789
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1790
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
1791
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
1792
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1793
1.91k
        // GIR_Coverage, 15925,
1794
1.91k
        GIR_Done,
1795
1.91k
      // Label 142: @2090
1796
1.91k
      GIM_Try, /*On fail goto*//*Label 143*/ 2106, // Rule ID 15914 //
1797
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
1798
1.91k
        // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (SUB64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
1799
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB64rr,
1800
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
1801
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1802
1.91k
        // GIR_Coverage, 15914,
1803
1.91k
        GIR_Done,
1804
1.91k
      // Label 143: @2106
1805
1.91k
      GIM_Reject,
1806
1.91k
    // Label 140: @2107
1807
1.91k
    GIM_Reject,
1808
1.91k
    // Label 116: @2108
1809
1.91k
    GIM_Try, /*On fail goto*//*Label 144*/ 2188,
1810
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1811
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1812
1.91k
      GIM_Try, /*On fail goto*//*Label 145*/ 2141, // Rule ID 1889 //
1813
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1814
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1815
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1816
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1817
1.91k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1818
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQrr,
1819
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1820
1.91k
        // GIR_Coverage, 1889,
1821
1.91k
        GIR_Done,
1822
1.91k
      // Label 145: @2141
1823
1.91k
      GIM_Try, /*On fail goto*//*Label 146*/ 2164, // Rule ID 1891 //
1824
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1825
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1826
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1827
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1828
1.91k
        // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
1829
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBQrr,
1830
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1831
1.91k
        // GIR_Coverage, 1891,
1832
1.91k
        GIR_Done,
1833
1.91k
      // Label 146: @2164
1834
1.91k
      GIM_Try, /*On fail goto*//*Label 147*/ 2187, // Rule ID 3927 //
1835
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1836
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1837
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1838
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1839
1.91k
        // (sub:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPSUBQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
1840
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ128rr,
1841
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1842
1.91k
        // GIR_Coverage, 3927,
1843
1.91k
        GIR_Done,
1844
1.91k
      // Label 147: @2187
1845
1.91k
      GIM_Reject,
1846
1.91k
    // Label 144: @2188
1847
1.91k
    GIM_Reject,
1848
1.91k
    // Label 117: @2189
1849
1.91k
    GIM_Try, /*On fail goto*//*Label 148*/ 2269,
1850
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1851
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1852
1.91k
      GIM_Try, /*On fail goto*//*Label 149*/ 2222, // Rule ID 1883 //
1853
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
1854
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1855
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1856
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1857
1.91k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1858
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDrr,
1859
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1860
1.91k
        // GIR_Coverage, 1883,
1861
1.91k
        GIR_Done,
1862
1.91k
      // Label 149: @2222
1863
1.91k
      GIM_Try, /*On fail goto*//*Label 150*/ 2245, // Rule ID 1885 //
1864
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1865
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1866
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1867
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1868
1.91k
        // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
1869
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBDrr,
1870
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1871
1.91k
        // GIR_Coverage, 1885,
1872
1.91k
        GIR_Done,
1873
1.91k
      // Label 150: @2245
1874
1.91k
      GIM_Try, /*On fail goto*//*Label 151*/ 2268, // Rule ID 3954 //
1875
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1876
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1877
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1878
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1879
1.91k
        // (sub:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPSUBDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
1880
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ128rr,
1881
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1882
1.91k
        // GIR_Coverage, 3954,
1883
1.91k
        GIR_Done,
1884
1.91k
      // Label 151: @2268
1885
1.91k
      GIM_Reject,
1886
1.91k
    // Label 148: @2269
1887
1.91k
    GIM_Reject,
1888
1.91k
    // Label 118: @2270
1889
1.91k
    GIM_Try, /*On fail goto*//*Label 152*/ 2327,
1890
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
1891
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
1892
1.91k
      GIM_Try, /*On fail goto*//*Label 153*/ 2303, // Rule ID 1893 //
1893
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1894
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1895
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1896
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1897
1.91k
        // (sub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPSUBQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
1898
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQYrr,
1899
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1900
1.91k
        // GIR_Coverage, 1893,
1901
1.91k
        GIR_Done,
1902
1.91k
      // Label 153: @2303
1903
1.91k
      GIM_Try, /*On fail goto*//*Label 154*/ 2326, // Rule ID 3918 //
1904
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1905
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1906
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1907
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1908
1.91k
        // (sub:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPSUBQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
1909
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ256rr,
1910
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1911
1.91k
        // GIR_Coverage, 3918,
1912
1.91k
        GIR_Done,
1913
1.91k
      // Label 154: @2326
1914
1.91k
      GIM_Reject,
1915
1.91k
    // Label 152: @2327
1916
1.91k
    GIM_Reject,
1917
1.91k
    // Label 119: @2328
1918
1.91k
    GIM_Try, /*On fail goto*//*Label 155*/ 2408,
1919
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1920
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1921
1.91k
      GIM_Try, /*On fail goto*//*Label 156*/ 2361, // Rule ID 1877 //
1922
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
1923
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1924
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1925
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1926
1.91k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1927
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWrr,
1928
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1929
1.91k
        // GIR_Coverage, 1877,
1930
1.91k
        GIR_Done,
1931
1.91k
      // Label 156: @2361
1932
1.91k
      GIM_Try, /*On fail goto*//*Label 157*/ 2384, // Rule ID 1879 //
1933
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
1934
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
1935
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
1936
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
1937
1.91k
        // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
1938
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBWrr,
1939
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1940
1.91k
        // GIR_Coverage, 1879,
1941
1.91k
        GIR_Done,
1942
1.91k
      // Label 157: @2384
1943
1.91k
      GIM_Try, /*On fail goto*//*Label 158*/ 2407, // Rule ID 3975 //
1944
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
1945
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
1946
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
1947
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
1948
1.91k
        // (sub:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPSUBWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
1949
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ128rr,
1950
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1951
1.91k
        // GIR_Coverage, 3975,
1952
1.91k
        GIR_Done,
1953
1.91k
      // Label 158: @2407
1954
1.91k
      GIM_Reject,
1955
1.91k
    // Label 155: @2408
1956
1.91k
    GIM_Reject,
1957
1.91k
    // Label 120: @2409
1958
1.91k
    GIM_Try, /*On fail goto*//*Label 159*/ 2466,
1959
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
1960
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
1961
1.91k
      GIM_Try, /*On fail goto*//*Label 160*/ 2442, // Rule ID 1887 //
1962
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
1963
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
1964
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
1965
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
1966
1.91k
        // (sub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPSUBDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
1967
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDYrr,
1968
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1969
1.91k
        // GIR_Coverage, 1887,
1970
1.91k
        GIR_Done,
1971
1.91k
      // Label 160: @2442
1972
1.91k
      GIM_Try, /*On fail goto*//*Label 161*/ 2465, // Rule ID 3945 //
1973
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
1974
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
1975
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
1976
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
1977
1.91k
        // (sub:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPSUBDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
1978
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ256rr,
1979
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1980
1.91k
        // GIR_Coverage, 3945,
1981
1.91k
        GIR_Done,
1982
1.91k
      // Label 161: @2465
1983
1.91k
      GIM_Reject,
1984
1.91k
    // Label 159: @2466
1985
1.91k
    GIM_Reject,
1986
1.91k
    // Label 121: @2467
1987
1.91k
    GIM_Try, /*On fail goto*//*Label 162*/ 2498, // Rule ID 3909 //
1988
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
1989
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
1990
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
1991
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
1992
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
1993
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
1994
1.91k
      // (sub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPSUBQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
1995
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZrr,
1996
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1997
1.91k
      // GIR_Coverage, 3909,
1998
1.91k
      GIR_Done,
1999
1.91k
    // Label 162: @2498
2000
1.91k
    GIM_Reject,
2001
1.91k
    // Label 122: @2499
2002
1.91k
    GIM_Try, /*On fail goto*//*Label 163*/ 2579,
2003
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2004
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2005
1.91k
      GIM_Try, /*On fail goto*//*Label 164*/ 2532, // Rule ID 1871 //
2006
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
2007
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2008
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2009
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2010
1.91k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (VPSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2011
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBrr,
2012
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2013
1.91k
        // GIR_Coverage, 1871,
2014
1.91k
        GIR_Done,
2015
1.91k
      // Label 164: @2532
2016
1.91k
      GIM_Try, /*On fail goto*//*Label 165*/ 2555, // Rule ID 1873 //
2017
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2018
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2019
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2020
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2021
1.91k
        // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)  =>  (PSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2)
2022
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBBrr,
2023
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2024
1.91k
        // GIR_Coverage, 1873,
2025
1.91k
        GIR_Done,
2026
1.91k
      // Label 165: @2555
2027
1.91k
      GIM_Try, /*On fail goto*//*Label 166*/ 2578, // Rule ID 3993 //
2028
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2029
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2030
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2031
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2032
1.91k
        // (sub:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)  =>  (VPSUBBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2)
2033
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ128rr,
2034
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2035
1.91k
        // GIR_Coverage, 3993,
2036
1.91k
        GIR_Done,
2037
1.91k
      // Label 166: @2578
2038
1.91k
      GIM_Reject,
2039
1.91k
    // Label 163: @2579
2040
1.91k
    GIM_Reject,
2041
1.91k
    // Label 123: @2580
2042
1.91k
    GIM_Try, /*On fail goto*//*Label 167*/ 2637,
2043
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2044
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2045
1.91k
      GIM_Try, /*On fail goto*//*Label 168*/ 2613, // Rule ID 1881 //
2046
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2047
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2048
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2049
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2050
1.91k
        // (sub:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPSUBWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2051
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWYrr,
2052
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2053
1.91k
        // GIR_Coverage, 1881,
2054
1.91k
        GIR_Done,
2055
1.91k
      // Label 168: @2613
2056
1.91k
      GIM_Try, /*On fail goto*//*Label 169*/ 2636, // Rule ID 3969 //
2057
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2058
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2059
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2060
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2061
1.91k
        // (sub:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPSUBWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2062
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ256rr,
2063
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2064
1.91k
        // GIR_Coverage, 3969,
2065
1.91k
        GIR_Done,
2066
1.91k
      // Label 169: @2636
2067
1.91k
      GIM_Reject,
2068
1.91k
    // Label 167: @2637
2069
1.91k
    GIM_Reject,
2070
1.91k
    // Label 124: @2638
2071
1.91k
    GIM_Try, /*On fail goto*//*Label 170*/ 2669, // Rule ID 3936 //
2072
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2073
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2074
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2075
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2076
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2077
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2078
1.91k
      // (sub:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPSUBDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2079
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZrr,
2080
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2081
1.91k
      // GIR_Coverage, 3936,
2082
1.91k
      GIR_Done,
2083
1.91k
    // Label 170: @2669
2084
1.91k
    GIM_Reject,
2085
1.91k
    // Label 125: @2670
2086
1.91k
    GIM_Try, /*On fail goto*//*Label 171*/ 2727,
2087
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8,
2088
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8,
2089
1.91k
      GIM_Try, /*On fail goto*//*Label 172*/ 2703, // Rule ID 1875 //
2090
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2091
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2092
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2093
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2094
1.91k
        // (sub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)  =>  (VPSUBBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2)
2095
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBYrr,
2096
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2097
1.91k
        // GIR_Coverage, 1875,
2098
1.91k
        GIR_Done,
2099
1.91k
      // Label 172: @2703
2100
1.91k
      GIM_Try, /*On fail goto*//*Label 173*/ 2726, // Rule ID 3987 //
2101
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2102
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2103
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2104
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2105
1.91k
        // (sub:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)  =>  (VPSUBBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2)
2106
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ256rr,
2107
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2108
1.91k
        // GIR_Coverage, 3987,
2109
1.91k
        GIR_Done,
2110
1.91k
      // Label 173: @2726
2111
1.91k
      GIM_Reject,
2112
1.91k
    // Label 171: @2727
2113
1.91k
    GIM_Reject,
2114
1.91k
    // Label 126: @2728
2115
1.91k
    GIM_Try, /*On fail goto*//*Label 174*/ 2759, // Rule ID 3963 //
2116
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
2117
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2118
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2119
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2120
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2121
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2122
1.91k
      // (sub:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPSUBWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2123
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZrr,
2124
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2125
1.91k
      // GIR_Coverage, 3963,
2126
1.91k
      GIR_Done,
2127
1.91k
    // Label 174: @2759
2128
1.91k
    GIM_Reject,
2129
1.91k
    // Label 127: @2760
2130
1.91k
    GIM_Try, /*On fail goto*//*Label 175*/ 2791, // Rule ID 3981 //
2131
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
2132
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8,
2133
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8,
2134
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2135
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2136
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2137
1.91k
      // (sub:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)  =>  (VPSUBBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2)
2138
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZrr,
2139
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140
1.91k
      // GIR_Coverage, 3981,
2141
1.91k
      GIR_Done,
2142
1.91k
    // Label 175: @2791
2143
1.91k
    GIM_Reject,
2144
1.91k
    // Label 128: @2792
2145
1.91k
    GIM_Reject,
2146
1.91k
    // Label 2: @2793
2147
1.91k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 188*/ 3558,
2148
1.91k
    /*GILLT_s16*//*Label 176*/ 2820,
2149
1.91k
    /*GILLT_s32*//*Label 177*/ 2919,
2150
1.91k
    /*GILLT_s64*//*Label 178*/ 3018, 0, 0, 0,
2151
1.91k
    /*GILLT_v2s64*//*Label 179*/ 3120, 0,
2152
1.91k
    /*GILLT_v4s32*//*Label 180*/ 3152,
2153
1.91k
    /*GILLT_v4s64*//*Label 181*/ 3233, 0,
2154
1.91k
    /*GILLT_v8s16*//*Label 182*/ 3265,
2155
1.91k
    /*GILLT_v8s32*//*Label 183*/ 3346,
2156
1.91k
    /*GILLT_v8s64*//*Label 184*/ 3404, 0, 0,
2157
1.91k
    /*GILLT_v16s16*//*Label 185*/ 3436,
2158
1.91k
    /*GILLT_v16s32*//*Label 186*/ 3494, 0, 0,
2159
1.91k
    /*GILLT_v32s16*//*Label 187*/ 3526,
2160
1.91k
    // Label 176: @2820
2161
1.91k
    GIM_Try, /*On fail goto*//*Label 189*/ 2918,
2162
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2163
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2164
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2165
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2166
1.91k
      GIM_Try, /*On fail goto*//*Label 190*/ 2871, // Rule ID 15940 //
2167
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2168
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2169
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2170
1.91k
        // MIs[1] Operand 1
2171
1.91k
        // No operand predicates
2172
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2173
1.91k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (IMUL16rri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2174
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8,
2175
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2176
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2177
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2178
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2179
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2180
1.91k
        // GIR_Coverage, 15940,
2181
1.91k
        GIR_Done,
2182
1.91k
      // Label 190: @2871
2183
1.91k
      GIM_Try, /*On fail goto*//*Label 191*/ 2901, // Rule ID 15938 //
2184
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2185
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2186
1.91k
        // MIs[1] Operand 1
2187
1.91k
        // No operand predicates
2188
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2189
1.91k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (IMUL16rri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2190
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri,
2191
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2192
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2193
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2194
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2195
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2196
1.91k
        // GIR_Coverage, 15938,
2197
1.91k
        GIR_Done,
2198
1.91k
      // Label 191: @2901
2199
1.91k
      GIM_Try, /*On fail goto*//*Label 192*/ 2917, // Rule ID 15932 //
2200
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2201
1.91k
        // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (IMUL16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2202
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL16rr,
2203
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2204
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2205
1.91k
        // GIR_Coverage, 15932,
2206
1.91k
        GIR_Done,
2207
1.91k
      // Label 192: @2917
2208
1.91k
      GIM_Reject,
2209
1.91k
    // Label 189: @2918
2210
1.91k
    GIM_Reject,
2211
1.91k
    // Label 177: @2919
2212
1.91k
    GIM_Try, /*On fail goto*//*Label 193*/ 3017,
2213
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2214
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2215
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2216
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2217
1.91k
      GIM_Try, /*On fail goto*//*Label 194*/ 2970, // Rule ID 15941 //
2218
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2219
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2220
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
2221
1.91k
        // MIs[1] Operand 1
2222
1.91k
        // No operand predicates
2223
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2224
1.91k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (IMUL32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
2225
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8,
2226
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2227
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2228
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2229
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2230
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2231
1.91k
        // GIR_Coverage, 15941,
2232
1.91k
        GIR_Done,
2233
1.91k
      // Label 194: @2970
2234
1.91k
      GIM_Try, /*On fail goto*//*Label 195*/ 3000, // Rule ID 15939 //
2235
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2236
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2237
1.91k
        // MIs[1] Operand 1
2238
1.91k
        // No operand predicates
2239
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2240
1.91k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (IMUL32rri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
2241
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri,
2242
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2243
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2244
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2245
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2246
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2247
1.91k
        // GIR_Coverage, 15939,
2248
1.91k
        GIR_Done,
2249
1.91k
      // Label 195: @3000
2250
1.91k
      GIM_Try, /*On fail goto*//*Label 196*/ 3016, // Rule ID 15933 //
2251
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
2252
1.91k
        // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (IMUL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
2253
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL32rr,
2254
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2255
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2256
1.91k
        // GIR_Coverage, 15933,
2257
1.91k
        GIR_Done,
2258
1.91k
      // Label 196: @3016
2259
1.91k
      GIM_Reject,
2260
1.91k
    // Label 193: @3017
2261
1.91k
    GIM_Reject,
2262
1.91k
    // Label 178: @3018
2263
1.91k
    GIM_Try, /*On fail goto*//*Label 197*/ 3119,
2264
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2265
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2266
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
2267
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
2268
1.91k
      GIM_Try, /*On fail goto*//*Label 198*/ 3069, // Rule ID 15942 //
2269
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2270
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2271
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
2272
1.91k
        // MIs[1] Operand 1
2273
1.91k
        // No operand predicates
2274
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2275
1.91k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (IMUL64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
2276
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8,
2277
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2278
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2279
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2280
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2281
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2282
1.91k
        // GIR_Coverage, 15942,
2283
1.91k
        GIR_Done,
2284
1.91k
      // Label 198: @3069
2285
1.91k
      GIM_Try, /*On fail goto*//*Label 199*/ 3102, // Rule ID 15943 //
2286
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2287
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2288
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
2289
1.91k
        // MIs[1] Operand 1
2290
1.91k
        // No operand predicates
2291
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2292
1.91k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (IMUL64rri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
2293
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32,
2294
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2295
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2296
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2297
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2298
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299
1.91k
        // GIR_Coverage, 15943,
2300
1.91k
        GIR_Done,
2301
1.91k
      // Label 199: @3102
2302
1.91k
      GIM_Try, /*On fail goto*//*Label 200*/ 3118, // Rule ID 15934 //
2303
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
2304
1.91k
        // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (IMUL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
2305
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL64rr,
2306
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2307
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2308
1.91k
        // GIR_Coverage, 15934,
2309
1.91k
        GIR_Done,
2310
1.91k
      // Label 200: @3118
2311
1.91k
      GIM_Reject,
2312
1.91k
    // Label 197: @3119
2313
1.91k
    GIM_Reject,
2314
1.91k
    // Label 179: @3120
2315
1.91k
    GIM_Try, /*On fail goto*//*Label 201*/ 3151, // Rule ID 4206 //
2316
1.91k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2317
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2318
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2319
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2320
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2321
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2322
1.91k
      // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPMULLQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
2323
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ128rr,
2324
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2325
1.91k
      // GIR_Coverage, 4206,
2326
1.91k
      GIR_Done,
2327
1.91k
    // Label 201: @3151
2328
1.91k
    GIM_Reject,
2329
1.91k
    // Label 180: @3152
2330
1.91k
    GIM_Try, /*On fail goto*//*Label 202*/ 3232,
2331
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2332
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2333
1.91k
      GIM_Try, /*On fail goto*//*Label 203*/ 3185, // Rule ID 2511 //
2334
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
2335
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2336
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2337
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2338
1.91k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (VPMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2339
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDrr,
2340
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2341
1.91k
        // GIR_Coverage, 2511,
2342
1.91k
        GIR_Done,
2343
1.91k
      // Label 203: @3185
2344
1.91k
      GIM_Try, /*On fail goto*//*Label 204*/ 3208, // Rule ID 2519 //
2345
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE41,
2346
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2347
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2348
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2349
1.91k
        // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)  =>  (PMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)
2350
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLDrr,
2351
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2352
1.91k
        // GIR_Coverage, 2519,
2353
1.91k
        GIR_Done,
2354
1.91k
      // Label 204: @3208
2355
1.91k
      GIM_Try, /*On fail goto*//*Label 205*/ 3231, // Rule ID 4161 //
2356
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2357
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2358
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2359
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2360
1.91k
        // (mul:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)  =>  (VPMULLDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2)
2361
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ128rr,
2362
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2363
1.91k
        // GIR_Coverage, 4161,
2364
1.91k
        GIR_Done,
2365
1.91k
      // Label 205: @3231
2366
1.91k
      GIM_Reject,
2367
1.91k
    // Label 202: @3232
2368
1.91k
    GIM_Reject,
2369
1.91k
    // Label 181: @3233
2370
1.91k
    GIM_Try, /*On fail goto*//*Label 206*/ 3264, // Rule ID 4197 //
2371
1.91k
      GIM_CheckFeatures, GIFBS_HasDQI_HasVLX,
2372
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
2373
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
2374
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2375
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2376
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2377
1.91k
      // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPMULLQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
2378
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ256rr,
2379
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2380
1.91k
      // GIR_Coverage, 4197,
2381
1.91k
      GIR_Done,
2382
1.91k
    // Label 206: @3264
2383
1.91k
    GIM_Reject,
2384
1.91k
    // Label 182: @3265
2385
1.91k
    GIM_Try, /*On fail goto*//*Label 207*/ 3345,
2386
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2387
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2388
1.91k
      GIM_Try, /*On fail goto*//*Label 208*/ 3298, // Rule ID 1853 //
2389
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI,
2390
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2391
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2392
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2393
1.91k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (VPMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2394
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWrr,
2395
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2396
1.91k
        // GIR_Coverage, 1853,
2397
1.91k
        GIR_Done,
2398
1.91k
      // Label 208: @3298
2399
1.91k
      GIM_Try, /*On fail goto*//*Label 209*/ 3321, // Rule ID 1855 //
2400
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
2401
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
2402
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
2403
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
2404
1.91k
        // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)  =>  (PMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)
2405
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLWrr,
2406
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2407
1.91k
        // GIR_Coverage, 1855,
2408
1.91k
        GIR_Done,
2409
1.91k
      // Label 209: @3321
2410
1.91k
      GIM_Try, /*On fail goto*//*Label 210*/ 3344, // Rule ID 4182 //
2411
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2412
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
2413
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
2414
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
2415
1.91k
        // (mul:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)  =>  (VPMULLWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2)
2416
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ128rr,
2417
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2418
1.91k
        // GIR_Coverage, 4182,
2419
1.91k
        GIR_Done,
2420
1.91k
      // Label 210: @3344
2421
1.91k
      GIM_Reject,
2422
1.91k
    // Label 207: @3345
2423
1.91k
    GIM_Reject,
2424
1.91k
    // Label 183: @3346
2425
1.91k
    GIM_Try, /*On fail goto*//*Label 211*/ 3403,
2426
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
2427
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32,
2428
1.91k
      GIM_Try, /*On fail goto*//*Label 212*/ 3379, // Rule ID 2515 //
2429
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
2430
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2431
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2432
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2433
1.91k
        // (mul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)  =>  (VPMULLDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2)
2434
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDYrr,
2435
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2436
1.91k
        // GIR_Coverage, 2515,
2437
1.91k
        GIR_Done,
2438
1.91k
      // Label 212: @3379
2439
1.91k
      GIM_Try, /*On fail goto*//*Label 213*/ 3402, // Rule ID 4152 //
2440
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
2441
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2442
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2443
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2444
1.91k
        // (mul:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)  =>  (VPMULLDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2)
2445
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ256rr,
2446
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2447
1.91k
        // GIR_Coverage, 4152,
2448
1.91k
        GIR_Done,
2449
1.91k
      // Label 213: @3402
2450
1.91k
      GIM_Reject,
2451
1.91k
    // Label 211: @3403
2452
1.91k
    GIM_Reject,
2453
1.91k
    // Label 184: @3404
2454
1.91k
    GIM_Try, /*On fail goto*//*Label 214*/ 3435, // Rule ID 4188 //
2455
1.91k
      GIM_CheckFeatures, GIFBS_HasDQI,
2456
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
2457
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
2458
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2459
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2460
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2461
1.91k
      // (mul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPMULLQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
2462
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZrr,
2463
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2464
1.91k
      // GIR_Coverage, 4188,
2465
1.91k
      GIR_Done,
2466
1.91k
    // Label 214: @3435
2467
1.91k
    GIM_Reject,
2468
1.91k
    // Label 185: @3436
2469
1.91k
    GIM_Try, /*On fail goto*//*Label 215*/ 3493,
2470
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
2471
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
2472
1.91k
      GIM_Try, /*On fail goto*//*Label 216*/ 3469, // Rule ID 1857 //
2473
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI,
2474
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
2475
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
2476
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
2477
1.91k
        // (mul:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)  =>  (VPMULLWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2)
2478
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWYrr,
2479
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2480
1.91k
        // GIR_Coverage, 1857,
2481
1.91k
        GIR_Done,
2482
1.91k
      // Label 216: @3469
2483
1.91k
      GIM_Try, /*On fail goto*//*Label 217*/ 3492, // Rule ID 4176 //
2484
1.91k
        GIM_CheckFeatures, GIFBS_HasBWI_HasVLX,
2485
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
2486
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
2487
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
2488
1.91k
        // (mul:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)  =>  (VPMULLWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2)
2489
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ256rr,
2490
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2491
1.91k
        // GIR_Coverage, 4176,
2492
1.91k
        GIR_Done,
2493
1.91k
      // Label 217: @3492
2494
1.91k
      GIM_Reject,
2495
1.91k
    // Label 215: @3493
2496
1.91k
    GIM_Reject,
2497
1.91k
    // Label 186: @3494
2498
1.91k
    GIM_Try, /*On fail goto*//*Label 218*/ 3525, // Rule ID 4143 //
2499
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
2500
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
2501
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32,
2502
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2503
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2504
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2505
1.91k
      // (mul:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)  =>  (VPMULLDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2)
2506
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZrr,
2507
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2508
1.91k
      // GIR_Coverage, 4143,
2509
1.91k
      GIR_Done,
2510
1.91k
    // Label 218: @3525
2511
1.91k
    GIM_Reject,
2512
1.91k
    // Label 187: @3526
2513
1.91k
    GIM_Try, /*On fail goto*//*Label 219*/ 3557, // Rule ID 4170 //
2514
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
2515
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
2516
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16,
2517
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
2518
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
2519
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
2520
1.91k
      // (mul:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)  =>  (VPMULLWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2)
2521
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZrr,
2522
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2523
1.91k
      // GIR_Coverage, 4170,
2524
1.91k
      GIR_Done,
2525
1.91k
    // Label 219: @3557
2526
1.91k
    GIM_Reject,
2527
1.91k
    // Label 188: @3558
2528
1.91k
    GIM_Reject,
2529
1.91k
    // Label 3: @3559
2530
1.91k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 24, /*)*//*default:*//*Label 234*/ 6670,
2531
1.91k
    /*GILLT_s1*//*Label 220*/ 3589,
2532
1.91k
    /*GILLT_s8*//*Label 221*/ 3887,
2533
1.91k
    /*GILLT_s16*//*Label 222*/ 3953,
2534
1.91k
    /*GILLT_s32*//*Label 223*/ 4052,
2535
1.91k
    /*GILLT_s64*//*Label 224*/ 5213, 0, 0,
2536
1.91k
    /*GILLT_v2s1*//*Label 225*/ 6085,
2537
1.91k
    /*GILLT_v2s64*//*Label 226*/ 6178,
2538
1.91k
    /*GILLT_v4s1*//*Label 227*/ 6259, 0,
2539
1.91k
    /*GILLT_v4s64*//*Label 228*/ 6352,
2540
1.91k
    /*GILLT_v8s1*//*Label 229*/ 6433, 0, 0,
2541
1.91k
    /*GILLT_v8s64*//*Label 230*/ 6542,
2542
1.91k
    /*GILLT_v16s1*//*Label 231*/ 6574, 0, 0, 0,
2543
1.91k
    /*GILLT_v32s1*//*Label 232*/ 6606, 0, 0,
2544
1.91k
    /*GILLT_v64s1*//*Label 233*/ 6638,
2545
1.91k
    // Label 220: @3589
2546
1.91k
    GIM_Try, /*On fail goto*//*Label 235*/ 3886,
2547
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
2548
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
2549
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
2550
1.91k
      GIM_Try, /*On fail goto*//*Label 236*/ 3704, // Rule ID 13773 //
2551
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2552
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2553
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2554
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2555
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2556
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2557
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2558
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2559
1.91k
        // (and:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2560
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2561
1.91k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2562
1.91k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2563
1.91k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2564
1.91k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2565
1.91k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2566
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2567
1.91k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2568
1.91k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2569
1.91k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2570
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2571
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2572
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2573
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2574
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2575
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2576
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2577
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2578
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2579
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2580
1.91k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2581
1.91k
        // GIR_Coverage, 13773,
2582
1.91k
        GIR_Done,
2583
1.91k
      // Label 236: @3704
2584
1.91k
      GIM_Try, /*On fail goto*//*Label 237*/ 3805, // Rule ID 18182 //
2585
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2586
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2587
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2588
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2589
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2590
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID,
2591
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2592
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2593
1.91k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }))  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2594
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2595
1.91k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2596
1.91k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2597
1.91k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2598
1.91k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2599
1.91k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2
2600
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2601
1.91k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2602
1.91k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2603
1.91k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1
2604
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2605
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr,
2606
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2607
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2608
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2609
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2610
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2611
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2612
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2613
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2614
1.91k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2615
1.91k
        // GIR_Coverage, 18182,
2616
1.91k
        GIR_Done,
2617
1.91k
      // Label 237: @3805
2618
1.91k
      GIM_Try, /*On fail goto*//*Label 238*/ 3885, // Rule ID 13769 //
2619
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
2620
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
2621
1.91k
        // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
2622
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2623
1.91k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2624
1.91k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2625
1.91k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2626
1.91k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2627
1.91k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
2628
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2629
1.91k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2630
1.91k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2631
1.91k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
2632
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
2633
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
2634
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2635
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2636
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2637
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2638
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2639
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2640
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2641
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2642
1.91k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
2643
1.91k
        // GIR_Coverage, 13769,
2644
1.91k
        GIR_Done,
2645
1.91k
      // Label 238: @3885
2646
1.91k
      GIM_Reject,
2647
1.91k
    // Label 235: @3886
2648
1.91k
    GIM_Reject,
2649
1.91k
    // Label 221: @3887
2650
1.91k
    GIM_Try, /*On fail goto*//*Label 239*/ 3952,
2651
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
2652
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
2653
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
2654
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
2655
1.91k
      GIM_Try, /*On fail goto*//*Label 240*/ 3935, // Rule ID 15996 //
2656
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2657
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2658
1.91k
        // MIs[1] Operand 1
2659
1.91k
        // No operand predicates
2660
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2661
1.91k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (AND8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
2662
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri,
2663
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2664
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2665
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2666
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2667
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2668
1.91k
        // GIR_Coverage, 15996,
2669
1.91k
        GIR_Done,
2670
1.91k
      // Label 240: @3935
2671
1.91k
      GIM_Try, /*On fail goto*//*Label 241*/ 3951, // Rule ID 15988 //
2672
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
2673
1.91k
        // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (AND8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
2674
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND8rr,
2675
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2676
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677
1.91k
        // GIR_Coverage, 15988,
2678
1.91k
        GIR_Done,
2679
1.91k
      // Label 241: @3951
2680
1.91k
      GIM_Reject,
2681
1.91k
    // Label 239: @3952
2682
1.91k
    GIM_Reject,
2683
1.91k
    // Label 222: @3953
2684
1.91k
    GIM_Try, /*On fail goto*//*Label 242*/ 4051,
2685
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
2686
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
2687
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
2688
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
2689
1.91k
      GIM_Try, /*On fail goto*//*Label 243*/ 4004, // Rule ID 15999 //
2690
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2691
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2692
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
2693
1.91k
        // MIs[1] Operand 1
2694
1.91k
        // No operand predicates
2695
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2696
1.91k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (AND16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
2697
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8,
2698
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2699
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2700
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2701
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2702
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2703
1.91k
        // GIR_Coverage, 15999,
2704
1.91k
        GIR_Done,
2705
1.91k
      // Label 243: @4004
2706
1.91k
      GIM_Try, /*On fail goto*//*Label 244*/ 4034, // Rule ID 15997 //
2707
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2708
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2709
1.91k
        // MIs[1] Operand 1
2710
1.91k
        // No operand predicates
2711
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2712
1.91k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (AND16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
2713
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri,
2714
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2715
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2716
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
2717
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2718
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2719
1.91k
        // GIR_Coverage, 15997,
2720
1.91k
        GIR_Done,
2721
1.91k
      // Label 244: @4034
2722
1.91k
      GIM_Try, /*On fail goto*//*Label 245*/ 4050, // Rule ID 15989 //
2723
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
2724
1.91k
        // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (AND16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
2725
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND16rr,
2726
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
2727
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2728
1.91k
        // GIR_Coverage, 15989,
2729
1.91k
        GIR_Done,
2730
1.91k
      // Label 245: @4050
2731
1.91k
      GIM_Reject,
2732
1.91k
    // Label 242: @4051
2733
1.91k
    GIM_Reject,
2734
1.91k
    // Label 223: @4052
2735
1.91k
    GIM_Try, /*On fail goto*//*Label 246*/ 5212,
2736
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2737
1.91k
      GIM_Try, /*On fail goto*//*Label 247*/ 4153, // Rule ID 18030 //
2738
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI2,
2739
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2740
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2741
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2742
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
2743
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2744
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
2745
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
2746
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2747
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC,
2748
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2749
1.91k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
2750
1.91k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB,
2751
1.91k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2752
1.91k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
2753
1.91k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 32,
2754
1.91k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/X86::GR32RegClassID,
2755
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
2756
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2757
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2758
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
2759
1.91k
        // (and:{ *:[i32] } (srl:{ *:[i32] } -1:{ *:[i32] }, (trunc:{ *:[i8] } (sub:{ *:[i32] } 32:{ *:[i32] }, GR32:{ *:[i32] }:$lz))), GR32:{ *:[i32] }:$src)  =>  (BZHI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src, GR32:{ *:[i32] }:$lz)
2760
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BZHI32rr,
2761
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2762
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
2763
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // lz
2764
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2765
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2766
1.91k
        // GIR_Coverage, 18030,
2767
1.91k
        GIR_Done,
2768
1.91k
      // Label 247: @4153
2769
1.91k
      GIM_Try, /*On fail goto*//*Label 248*/ 4248, // Rule ID 12253 //
2770
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI2,
2771
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2772
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2773
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2774
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2775
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
2776
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2777
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
2778
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
2779
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2780
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC,
2781
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2782
1.91k
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
2783
1.91k
        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB,
2784
1.91k
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2785
1.91k
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
2786
1.91k
        GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 32,
2787
1.91k
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/X86::GR32RegClassID,
2788
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2789
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2790
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/3,
2791
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (srl:{ *:[i32] } -1:{ *:[i32] }, (trunc:{ *:[i8] } (sub:{ *:[i32] } 32:{ *:[i32] }, GR32:{ *:[i32] }:$lz))))  =>  (BZHI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src, GR32:{ *:[i32] }:$lz)
2792
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BZHI32rr,
2793
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2794
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2795
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // lz
2796
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2797
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2798
1.91k
        // GIR_Coverage, 12253,
2799
1.91k
        GIR_Done,
2800
1.91k
      // Label 248: @4248
2801
1.91k
      GIM_Try, /*On fail goto*//*Label 249*/ 4323, // Rule ID 18040 //
2802
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2803
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2804
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2805
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2806
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2807
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2808
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2809
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2810
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2811
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2812
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2813
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2814
1.91k
        // MIs[2] src
2815
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2816
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2817
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2818
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2819
1.91k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2820
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2821
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2822
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2823
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2824
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2825
1.91k
        // GIR_Coverage, 18040,
2826
1.91k
        GIR_Done,
2827
1.91k
      // Label 249: @4323
2828
1.91k
      GIM_Try, /*On fail goto*//*Label 250*/ 4398, // Rule ID 18052 //
2829
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2830
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2831
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2832
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2833
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2834
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2835
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2836
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2837
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2838
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2839
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
2840
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2841
1.91k
        // MIs[2] src
2842
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2843
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2844
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2845
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2846
1.91k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2847
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2848
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2849
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2850
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2851
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2852
1.91k
        // GIR_Coverage, 18052,
2853
1.91k
        GIR_Done,
2854
1.91k
      // Label 250: @4398
2855
1.91k
      GIM_Try, /*On fail goto*//*Label 251*/ 4473, // Rule ID 12269 //
2856
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2857
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2858
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2859
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2860
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2861
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2862
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2863
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2864
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2865
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2866
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2867
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2868
1.91k
        // MIs[2] src
2869
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2870
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
2871
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2872
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2873
1.91k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2874
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr,
2875
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2876
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2877
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2878
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2879
1.91k
        // GIR_Coverage, 12269,
2880
1.91k
        GIR_Done,
2881
1.91k
      // Label 251: @4473
2882
1.91k
      GIM_Try, /*On fail goto*//*Label 252*/ 4548, // Rule ID 12281 //
2883
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2884
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2885
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2886
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2887
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
2888
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2889
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2890
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2891
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2892
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2893
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
2894
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
2895
1.91k
        // MIs[2] src
2896
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2897
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
2898
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2899
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
2900
1.91k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2901
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr,
2902
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2903
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2904
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2905
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2906
1.91k
        // GIR_Coverage, 12281,
2907
1.91k
        GIR_Done,
2908
1.91k
      // Label 252: @4548
2909
1.91k
      GIM_Try, /*On fail goto*//*Label 253*/ 4602, // Rule ID 18034 //
2910
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2911
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2912
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2913
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2914
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2915
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2916
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2917
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2918
1.91k
        // MIs[0] src
2919
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2920
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2921
1.91k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2922
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2923
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2924
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2925
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2926
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2927
1.91k
        // GIR_Coverage, 18034,
2928
1.91k
        GIR_Done,
2929
1.91k
      // Label 253: @4602
2930
1.91k
      GIM_Try, /*On fail goto*//*Label 254*/ 4656, // Rule ID 18556 //
2931
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
2932
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2933
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2934
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2935
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2936
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2937
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
2938
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
2939
1.91k
        // MIs[0] src
2940
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
2941
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2942
1.91k
        // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2943
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
2944
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2945
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
2946
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2947
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2948
1.91k
        // GIR_Coverage, 18556,
2949
1.91k
        GIR_Done,
2950
1.91k
      // Label 254: @4656
2951
1.91k
      GIM_Try, /*On fail goto*//*Label 255*/ 4710, // Rule ID 18560 //
2952
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
2953
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2954
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2955
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
2956
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2957
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2958
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
2959
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
2960
1.91k
        // MIs[0] src
2961
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2962
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2963
1.91k
        // (and:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2964
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
2965
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2966
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
2967
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2968
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2969
1.91k
        // GIR_Coverage, 18560,
2970
1.91k
        GIR_Done,
2971
1.91k
      // Label 255: @4710
2972
1.91k
      GIM_Try, /*On fail goto*//*Label 256*/ 4764, // Rule ID 12263 //
2973
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
2974
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2975
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2976
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2977
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2978
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2979
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2980
1.91k
        // MIs[1] src
2981
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
2982
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
2983
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2984
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
2985
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr,
2986
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
2987
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2988
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
2989
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2990
1.91k
        // GIR_Coverage, 12263,
2991
1.91k
        GIR_Done,
2992
1.91k
      // Label 256: @4764
2993
1.91k
      GIM_Try, /*On fail goto*//*Label 257*/ 4818, // Rule ID 16267 //
2994
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
2995
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2996
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
2997
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
2998
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2999
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3000
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3001
1.91k
        // MIs[1] src
3002
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3003
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3004
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3005
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3006
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr,
3007
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3008
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3009
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3010
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3011
1.91k
        // GIR_Coverage, 16267,
3012
1.91k
        GIR_Done,
3013
1.91k
      // Label 257: @4818
3014
1.91k
      GIM_Try, /*On fail goto*//*Label 258*/ 4872, // Rule ID 16271 //
3015
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3016
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3017
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3018
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3019
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3020
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3021
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3022
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3023
1.91k
        // MIs[1] src
3024
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3025
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3026
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3027
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr,
3028
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3029
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3030
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3031
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3032
1.91k
        // GIR_Coverage, 16271,
3033
1.91k
        GIR_Done,
3034
1.91k
      // Label 258: @4872
3035
1.91k
      GIM_Try, /*On fail goto*//*Label 259*/ 4923, // Rule ID 15772 //
3036
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3037
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3038
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3039
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
3040
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 65535:{ *:[i32] })  =>  (MOVZX32rr16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src1, sub_16bit:{ *:[i32] }))
3041
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
3042
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3043
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3044
1.91k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1
3045
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3046
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16,
3047
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3048
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3049
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3050
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3051
1.91k
        // GIR_Coverage, 15772,
3052
1.91k
        GIR_Done,
3053
1.91k
      // Label 259: @4923
3054
1.91k
      GIM_Try, /*On fail goto*//*Label 260*/ 4974, // Rule ID 15773 //
3055
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3056
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3057
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3058
1.91k
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
3059
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 255:{ *:[i32] })  =>  (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src1, sub_8bit:{ *:[i32] }))
3060
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
3061
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3062
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3063
1.91k
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1
3064
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3065
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8,
3066
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3067
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3068
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3069
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3070
1.91k
        // GIR_Coverage, 15773,
3071
1.91k
        GIR_Done,
3072
1.91k
      // Label 260: @4974
3073
1.91k
      GIM_Try, /*On fail goto*//*Label 261*/ 5019, // Rule ID 16000 //
3074
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3075
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3076
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3077
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3078
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3079
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
3080
1.91k
        // MIs[1] Operand 1
3081
1.91k
        // No operand predicates
3082
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3083
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (AND32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
3084
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8,
3085
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3086
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3087
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3088
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3089
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3090
1.91k
        // GIR_Coverage, 16000,
3091
1.91k
        GIR_Done,
3092
1.91k
      // Label 261: @5019
3093
1.91k
      GIM_Try, /*On fail goto*//*Label 262*/ 5061, // Rule ID 15998 //
3094
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3095
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3096
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3097
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3098
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3099
1.91k
        // MIs[1] Operand 1
3100
1.91k
        // No operand predicates
3101
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3102
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (AND32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
3103
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri,
3104
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3105
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3106
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3107
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3108
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3109
1.91k
        // GIR_Coverage, 15998,
3110
1.91k
        GIR_Done,
3111
1.91k
      // Label 262: @5061
3112
1.91k
      GIM_Try, /*On fail goto*//*Label 263*/ 5122, // Rule ID 12283 //
3113
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3114
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3115
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3116
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3117
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3118
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3119
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3120
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3121
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3122
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3123
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3124
1.91k
        // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src2)  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3125
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3126
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3127
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3128
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3129
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3130
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3131
1.91k
        // GIR_Coverage, 12283,
3132
1.91k
        GIR_Done,
3133
1.91k
      // Label 263: @5122
3134
1.91k
      GIM_Try, /*On fail goto*//*Label 264*/ 5183, // Rule ID 18054 //
3135
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3136
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3137
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3138
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3139
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3140
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3141
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3142
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3143
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3144
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3145
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3146
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src2, (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }))  =>  (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3147
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr,
3148
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3149
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3150
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3151
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3152
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3153
1.91k
        // GIR_Coverage, 18054,
3154
1.91k
        GIR_Done,
3155
1.91k
      // Label 264: @5183
3156
1.91k
      GIM_Try, /*On fail goto*//*Label 265*/ 5211, // Rule ID 15990 //
3157
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3158
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3159
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
3160
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
3161
1.91k
        // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (AND32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
3162
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND32rr,
3163
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3164
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3165
1.91k
        // GIR_Coverage, 15990,
3166
1.91k
        GIR_Done,
3167
1.91k
      // Label 265: @5211
3168
1.91k
      GIM_Reject,
3169
1.91k
    // Label 246: @5212
3170
1.91k
    GIM_Reject,
3171
1.91k
    // Label 224: @5213
3172
1.91k
    GIM_Try, /*On fail goto*//*Label 266*/ 6084,
3173
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3174
1.91k
      GIM_Try, /*On fail goto*//*Label 267*/ 5294, // Rule ID 18041 //
3175
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3176
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3177
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3178
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3179
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3180
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3181
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3182
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3183
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3184
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3185
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3186
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3187
1.91k
        // MIs[2] src
3188
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3189
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3190
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3191
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3192
1.91k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3193
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3194
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3195
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3196
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3197
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3198
1.91k
        // GIR_Coverage, 18041,
3199
1.91k
        GIR_Done,
3200
1.91k
      // Label 267: @5294
3201
1.91k
      GIM_Try, /*On fail goto*//*Label 268*/ 5369, // Rule ID 18053 //
3202
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3203
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3204
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3205
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3206
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3207
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3208
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3209
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3210
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3211
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3212
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3213
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3214
1.91k
        // MIs[2] src
3215
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3216
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3217
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3218
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3219
1.91k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3220
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3221
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3222
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3223
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3224
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3225
1.91k
        // GIR_Coverage, 18053,
3226
1.91k
        GIR_Done,
3227
1.91k
      // Label 268: @5369
3228
1.91k
      GIM_Try, /*On fail goto*//*Label 269*/ 5444, // Rule ID 12270 //
3229
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3230
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3231
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3232
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3233
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3234
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3235
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3236
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3237
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3238
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3239
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3240
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3241
1.91k
        // MIs[2] src
3242
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3243
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
3244
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3245
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3246
1.91k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3247
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr,
3248
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3249
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3250
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3251
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3252
1.91k
        // GIR_Coverage, 12270,
3253
1.91k
        GIR_Done,
3254
1.91k
      // Label 269: @5444
3255
1.91k
      GIM_Try, /*On fail goto*//*Label 270*/ 5519, // Rule ID 12282 //
3256
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3257
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3258
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3259
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3260
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3261
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3262
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3263
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3264
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3265
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3266
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3267
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3268
1.91k
        // MIs[2] src
3269
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3270
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3271
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3272
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3273
1.91k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3274
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr,
3275
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3276
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3277
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3278
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3279
1.91k
        // GIR_Coverage, 12282,
3280
1.91k
        GIR_Done,
3281
1.91k
      // Label 270: @5519
3282
1.91k
      GIM_Try, /*On fail goto*//*Label 271*/ 5573, // Rule ID 18035 //
3283
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3284
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3285
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3286
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3287
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3288
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3289
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3290
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3291
1.91k
        // MIs[0] src
3292
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3293
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3294
1.91k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3295
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3296
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3297
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3298
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3299
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3300
1.91k
        // GIR_Coverage, 18035,
3301
1.91k
        GIR_Done,
3302
1.91k
      // Label 271: @5573
3303
1.91k
      GIM_Try, /*On fail goto*//*Label 272*/ 5627, // Rule ID 18557 //
3304
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3305
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3306
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3307
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3308
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3309
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3310
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3311
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3312
1.91k
        // MIs[0] src
3313
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
3314
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3315
1.91k
        // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3316
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3317
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3318
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3319
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3320
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3321
1.91k
        // GIR_Coverage, 18557,
3322
1.91k
        GIR_Done,
3323
1.91k
      // Label 272: @5627
3324
1.91k
      GIM_Try, /*On fail goto*//*Label 273*/ 5681, // Rule ID 18561 //
3325
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3326
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3327
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3328
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3329
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3330
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3331
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3332
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
3333
1.91k
        // MIs[0] src
3334
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3335
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3336
1.91k
        // (and:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3337
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3338
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3339
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
3340
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3341
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3342
1.91k
        // GIR_Coverage, 18561,
3343
1.91k
        GIR_Done,
3344
1.91k
      // Label 273: @5681
3345
1.91k
      GIM_Try, /*On fail goto*//*Label 274*/ 5735, // Rule ID 12264 //
3346
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3347
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3348
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3349
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3350
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3351
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3352
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3353
1.91k
        // MIs[1] src
3354
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3355
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3356
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3357
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3358
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr,
3359
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3360
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3361
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3362
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3363
1.91k
        // GIR_Coverage, 12264,
3364
1.91k
        GIR_Done,
3365
1.91k
      // Label 274: @5735
3366
1.91k
      GIM_Try, /*On fail goto*//*Label 275*/ 5789, // Rule ID 16268 //
3367
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3368
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3369
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3370
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3371
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3372
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3373
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3374
1.91k
        // MIs[1] src
3375
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
3376
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3377
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3378
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3379
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr,
3380
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3381
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3382
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3383
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3384
1.91k
        // GIR_Coverage, 16268,
3385
1.91k
        GIR_Done,
3386
1.91k
      // Label 275: @5789
3387
1.91k
      GIM_Try, /*On fail goto*//*Label 276*/ 5843, // Rule ID 16272 //
3388
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3389
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3390
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3391
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3392
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3393
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
3394
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3395
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0,
3396
1.91k
        // MIs[1] src
3397
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3398
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3399
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
3400
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr,
3401
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3402
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
3403
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3404
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3405
1.91k
        // GIR_Coverage, 16272,
3406
1.91k
        GIR_Done,
3407
1.91k
      // Label 276: @5843
3408
1.91k
      GIM_Try, /*On fail goto*//*Label 277*/ 5888, // Rule ID 16001 //
3409
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3410
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3411
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3412
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3413
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3414
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
3415
1.91k
        // MIs[1] Operand 1
3416
1.91k
        // No operand predicates
3417
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3418
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (AND64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
3419
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8,
3420
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3421
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3422
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3423
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3424
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3425
1.91k
        // GIR_Coverage, 16001,
3426
1.91k
        GIR_Done,
3427
1.91k
      // Label 277: @5888
3428
1.91k
      GIM_Try, /*On fail goto*//*Label 278*/ 5933, // Rule ID 16002 //
3429
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3430
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3431
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3432
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3433
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3434
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
3435
1.91k
        // MIs[1] Operand 1
3436
1.91k
        // No operand predicates
3437
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3438
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (AND64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
3439
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32,
3440
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3441
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3442
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3443
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3444
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3445
1.91k
        // GIR_Coverage, 16002,
3446
1.91k
        GIR_Done,
3447
1.91k
      // Label 278: @5933
3448
1.91k
      GIM_Try, /*On fail goto*//*Label 279*/ 5994, // Rule ID 12284 //
3449
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3450
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3451
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3452
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3453
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3454
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3455
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3456
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3457
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3458
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3459
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3460
1.91k
        // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src2)  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3461
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3462
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3463
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3464
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
3465
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3466
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3467
1.91k
        // GIR_Coverage, 12284,
3468
1.91k
        GIR_Done,
3469
1.91k
      // Label 279: @5994
3470
1.91k
      GIM_Try, /*On fail goto*//*Label 280*/ 6055, // Rule ID 18055 //
3471
1.91k
        GIM_CheckFeatures, GIFBS_HasBMI,
3472
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3473
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3474
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3475
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3476
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3477
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
3478
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
3479
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
3480
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3481
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3482
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src2, (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }))  =>  (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3483
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr,
3484
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3485
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
3486
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
3487
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3488
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3489
1.91k
        // GIR_Coverage, 18055,
3490
1.91k
        GIR_Done,
3491
1.91k
      // Label 280: @6055
3492
1.91k
      GIM_Try, /*On fail goto*//*Label 281*/ 6083, // Rule ID 15991 //
3493
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3494
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
3495
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
3496
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
3497
1.91k
        // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (AND64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
3498
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND64rr,
3499
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3500
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3501
1.91k
        // GIR_Coverage, 15991,
3502
1.91k
        GIR_Done,
3503
1.91k
      // Label 281: @6083
3504
1.91k
      GIM_Reject,
3505
1.91k
    // Label 266: @6084
3506
1.91k
    GIM_Reject,
3507
1.91k
    // Label 225: @6085
3508
1.91k
    GIM_Try, /*On fail goto*//*Label 282*/ 6177, // Rule ID 13770 //
3509
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
3510
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
3511
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3512
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID,
3513
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID,
3514
1.91k
      // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3515
1.91k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3516
1.91k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3517
1.91k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3518
1.91k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3519
1.91k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3520
1.91k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3521
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3522
1.91k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3523
1.91k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3524
1.91k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3525
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3526
1.91k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3527
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3528
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3529
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3530
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3531
1.91k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3532
1.91k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3533
1.91k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3534
1.91k
      GIR_EraseFromParent, /*InsnID*/0,
3535
1.91k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3536
1.91k
      // GIR_Coverage, 13770,
3537
1.91k
      GIR_Done,
3538
1.91k
    // Label 282: @6177
3539
1.91k
    GIM_Reject,
3540
1.91k
    // Label 226: @6178
3541
1.91k
    GIM_Try, /*On fail goto*//*Label 283*/ 6258,
3542
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3543
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3544
1.91k
      GIM_Try, /*On fail goto*//*Label 284*/ 6211, // Rule ID 1545 //
3545
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
3546
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3547
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3548
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3549
1.91k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3550
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr,
3551
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3552
1.91k
        // GIR_Coverage, 1545,
3553
1.91k
        GIR_Done,
3554
1.91k
      // Label 284: @6211
3555
1.91k
      GIM_Try, /*On fail goto*//*Label 285*/ 6234, // Rule ID 1547 //
3556
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
3557
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
3558
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
3559
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
3560
1.91k
        // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
3561
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr,
3562
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3563
1.91k
        // GIR_Coverage, 1547,
3564
1.91k
        GIR_Done,
3565
1.91k
      // Label 285: @6234
3566
1.91k
      GIM_Try, /*On fail goto*//*Label 286*/ 6257, // Rule ID 4890 //
3567
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3568
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
3569
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
3570
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
3571
1.91k
        // (and:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPANDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
3572
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr,
3573
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3574
1.91k
        // GIR_Coverage, 4890,
3575
1.91k
        GIR_Done,
3576
1.91k
      // Label 286: @6257
3577
1.91k
      GIM_Reject,
3578
1.91k
    // Label 283: @6258
3579
1.91k
    GIM_Reject,
3580
1.91k
    // Label 227: @6259
3581
1.91k
    GIM_Try, /*On fail goto*//*Label 287*/ 6351, // Rule ID 13771 //
3582
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
3583
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
3584
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3585
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID,
3586
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID,
3587
1.91k
      // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3588
1.91k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3589
1.91k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3590
1.91k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3591
1.91k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3592
1.91k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3593
1.91k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3594
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3595
1.91k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3596
1.91k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3597
1.91k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3598
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3599
1.91k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3600
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3601
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3602
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3603
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3604
1.91k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3605
1.91k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3606
1.91k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3607
1.91k
      GIR_EraseFromParent, /*InsnID*/0,
3608
1.91k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3609
1.91k
      // GIR_Coverage, 13771,
3610
1.91k
      GIR_Done,
3611
1.91k
    // Label 287: @6351
3612
1.91k
    GIM_Reject,
3613
1.91k
    // Label 228: @6352
3614
1.91k
    GIM_Try, /*On fail goto*//*Label 288*/ 6432,
3615
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
3616
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
3617
1.91k
      GIM_Try, /*On fail goto*//*Label 289*/ 6385, // Rule ID 1549 //
3618
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
3619
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3620
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3621
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3622
1.91k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPANDYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3623
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr,
3624
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3625
1.91k
        // GIR_Coverage, 1549,
3626
1.91k
        GIR_Done,
3627
1.91k
      // Label 289: @6385
3628
1.91k
      GIM_Try, /*On fail goto*//*Label 290*/ 6408, // Rule ID 4881 //
3629
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
3630
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
3631
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
3632
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
3633
1.91k
        // (and:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPANDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
3634
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr,
3635
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3636
1.91k
        // GIR_Coverage, 4881,
3637
1.91k
        GIR_Done,
3638
1.91k
      // Label 290: @6408
3639
1.91k
      GIM_Try, /*On fail goto*//*Label 291*/ 6431, // Rule ID 12539 //
3640
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
3641
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
3642
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
3643
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
3644
1.91k
        // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VANDPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
3645
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr,
3646
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3647
1.91k
        // GIR_Coverage, 12539,
3648
1.91k
        GIR_Done,
3649
1.91k
      // Label 291: @6431
3650
1.91k
      GIM_Reject,
3651
1.91k
    // Label 288: @6432
3652
1.91k
    GIM_Reject,
3653
1.91k
    // Label 229: @6433
3654
1.91k
    GIM_Try, /*On fail goto*//*Label 292*/ 6541,
3655
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
3656
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
3657
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID,
3658
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID,
3659
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID,
3660
1.91k
      GIM_Try, /*On fail goto*//*Label 293*/ 6466, // Rule ID 3605 //
3661
1.91k
        GIM_CheckFeatures, GIFBS_HasDQI,
3662
1.91k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (KANDBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)
3663
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDBrr,
3664
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3665
1.91k
        // GIR_Coverage, 3605,
3666
1.91k
        GIR_Done,
3667
1.91k
      // Label 293: @6466
3668
1.91k
      GIM_Try, /*On fail goto*//*Label 294*/ 6540, // Rule ID 13768 //
3669
1.91k
        GIM_CheckFeatures, GIFBS_NoDQI,
3670
1.91k
        // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] })
3671
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3672
1.91k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3673
1.91k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3674
1.91k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3675
1.91k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3676
1.91k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3677
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3678
1.91k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3679
1.91k
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3680
1.91k
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3681
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3682
1.91k
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr,
3683
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3684
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3685
1.91k
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3686
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3687
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3688
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3689
1.91k
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3690
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3691
1.91k
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12,
3692
1.91k
        // GIR_Coverage, 13768,
3693
1.91k
        GIR_Done,
3694
1.91k
      // Label 294: @6540
3695
1.91k
      GIM_Reject,
3696
1.91k
    // Label 292: @6541
3697
1.91k
    GIM_Reject,
3698
1.91k
    // Label 230: @6542
3699
1.91k
    GIM_Try, /*On fail goto*//*Label 295*/ 6573, // Rule ID 4872 //
3700
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3701
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
3702
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64,
3703
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID,
3704
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID,
3705
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID,
3706
1.91k
      // (and:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)  =>  (VPANDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2)
3707
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr,
3708
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3709
1.91k
      // GIR_Coverage, 4872,
3710
1.91k
      GIR_Done,
3711
1.91k
    // Label 295: @6573
3712
1.91k
    GIM_Reject,
3713
1.91k
    // Label 231: @6574
3714
1.91k
    GIM_Try, /*On fail goto*//*Label 296*/ 6605, // Rule ID 3606 //
3715
1.91k
      GIM_CheckFeatures, GIFBS_HasAVX512,
3716
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
3717
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
3718
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID,
3719
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID,
3720
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID,
3721
1.91k
      // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)  =>  (KANDWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2)
3722
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDWrr,
3723
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3724
1.91k
      // GIR_Coverage, 3606,
3725
1.91k
      GIR_Done,
3726
1.91k
    // Label 296: @6605
3727
1.91k
    GIM_Reject,
3728
1.91k
    // Label 232: @6606
3729
1.91k
    GIM_Try, /*On fail goto*//*Label 297*/ 6637, // Rule ID 3607 //
3730
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
3731
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1,
3732
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1,
3733
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID,
3734
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID,
3735
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID,
3736
1.91k
      // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)  =>  (KANDDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2)
3737
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDDrr,
3738
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3739
1.91k
      // GIR_Coverage, 3607,
3740
1.91k
      GIR_Done,
3741
1.91k
    // Label 297: @6637
3742
1.91k
    GIM_Reject,
3743
1.91k
    // Label 233: @6638
3744
1.91k
    GIM_Try, /*On fail goto*//*Label 298*/ 6669, // Rule ID 3608 //
3745
1.91k
      GIM_CheckFeatures, GIFBS_HasBWI,
3746
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1,
3747
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1,
3748
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID,
3749
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID,
3750
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID,
3751
1.91k
      // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)  =>  (KANDQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2)
3752
1.91k
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDQrr,
3753
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3754
1.91k
      // GIR_Coverage, 3608,
3755
1.91k
      GIR_Done,
3756
1.91k
    // Label 298: @6669
3757
1.91k
    GIM_Reject,
3758
1.91k
    // Label 234: @6670
3759
1.91k
    GIM_Reject,
3760
1.91k
    // Label 4: @6671
3761
1.91k
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 24, /*)*//*default:*//*Label 313*/ 9341,
3762
1.91k
    /*GILLT_s1*//*Label 299*/ 6701,
3763
1.91k
    /*GILLT_s8*//*Label 300*/ 6794,
3764
1.91k
    /*GILLT_s16*//*Label 301*/ 6860,
3765
1.91k
    /*GILLT_s32*//*Label 302*/ 6959,
3766
1.91k
    /*GILLT_s64*//*Label 303*/ 7856, 0, 0,
3767
1.91k
    /*GILLT_v2s1*//*Label 304*/ 8756,
3768
1.91k
    /*GILLT_v2s64*//*Label 305*/ 8849,
3769
1.91k
    /*GILLT_v4s1*//*Label 306*/ 8930, 0,
3770
1.91k
    /*GILLT_v4s64*//*Label 307*/ 9023,
3771
1.91k
    /*GILLT_v8s1*//*Label 308*/ 9104, 0, 0,
3772
1.91k
    /*GILLT_v8s64*//*Label 309*/ 9213,
3773
1.91k
    /*GILLT_v16s1*//*Label 310*/ 9245, 0, 0, 0,
3774
1.91k
    /*GILLT_v32s1*//*Label 311*/ 9277, 0, 0,
3775
1.91k
    /*GILLT_v64s1*//*Label 312*/ 9309,
3776
1.91k
    // Label 299: @6701
3777
1.91k
    GIM_Try, /*On fail goto*//*Label 314*/ 6793, // Rule ID 13777 //
3778
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
3779
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
3780
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
3781
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID,
3782
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID,
3783
1.91k
      // (or:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
3784
1.91k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
3785
1.91k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
3786
1.91k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
3787
1.91k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3788
1.91k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3789
1.91k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
3790
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3791
1.91k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3792
1.91k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3793
1.91k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
3794
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3795
1.91k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
3796
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3797
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3798
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
3799
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3800
1.91k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3801
1.91k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3802
1.91k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3803
1.91k
      GIR_EraseFromParent, /*InsnID*/0,
3804
1.91k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
3805
1.91k
      // GIR_Coverage, 13777,
3806
1.91k
      GIR_Done,
3807
1.91k
    // Label 314: @6793
3808
1.91k
    GIM_Reject,
3809
1.91k
    // Label 300: @6794
3810
1.91k
    GIM_Try, /*On fail goto*//*Label 315*/ 6859,
3811
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
3812
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
3813
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
3814
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
3815
1.91k
      GIM_Try, /*On fail goto*//*Label 316*/ 6842, // Rule ID 15966 //
3816
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3817
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3818
1.91k
        // MIs[1] Operand 1
3819
1.91k
        // No operand predicates
3820
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3821
1.91k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)  =>  (OR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2)
3822
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri,
3823
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3824
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3825
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3826
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3827
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3828
1.91k
        // GIR_Coverage, 15966,
3829
1.91k
        GIR_Done,
3830
1.91k
      // Label 316: @6842
3831
1.91k
      GIM_Try, /*On fail goto*//*Label 317*/ 6858, // Rule ID 15958 //
3832
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
3833
1.91k
        // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)  =>  (OR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2)
3834
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR8rr,
3835
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3836
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3837
1.91k
        // GIR_Coverage, 15958,
3838
1.91k
        GIR_Done,
3839
1.91k
      // Label 317: @6858
3840
1.91k
      GIM_Reject,
3841
1.91k
    // Label 315: @6859
3842
1.91k
    GIM_Reject,
3843
1.91k
    // Label 301: @6860
3844
1.91k
    GIM_Try, /*On fail goto*//*Label 318*/ 6958,
3845
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
3846
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
3847
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID,
3848
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID,
3849
1.91k
      GIM_Try, /*On fail goto*//*Label 319*/ 6911, // Rule ID 15969 //
3850
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3851
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3852
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8,
3853
1.91k
        // MIs[1] Operand 1
3854
1.91k
        // No operand predicates
3855
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3856
1.91k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)  =>  (OR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2)
3857
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8,
3858
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3859
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3860
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3861
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3862
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3863
1.91k
        // GIR_Coverage, 15969,
3864
1.91k
        GIR_Done,
3865
1.91k
      // Label 319: @6911
3866
1.91k
      GIM_Try, /*On fail goto*//*Label 320*/ 6941, // Rule ID 15967 //
3867
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3868
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3869
1.91k
        // MIs[1] Operand 1
3870
1.91k
        // No operand predicates
3871
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3872
1.91k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)  =>  (OR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2)
3873
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri,
3874
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3875
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3876
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
3877
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3878
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3879
1.91k
        // GIR_Coverage, 15967,
3880
1.91k
        GIR_Done,
3881
1.91k
      // Label 320: @6941
3882
1.91k
      GIM_Try, /*On fail goto*//*Label 321*/ 6957, // Rule ID 15959 //
3883
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID,
3884
1.91k
        // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)  =>  (OR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2)
3885
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR16rr,
3886
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
3887
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3888
1.91k
        // GIR_Coverage, 15959,
3889
1.91k
        GIR_Done,
3890
1.91k
      // Label 321: @6957
3891
1.91k
      GIM_Reject,
3892
1.91k
    // Label 318: @6958
3893
1.91k
    GIM_Reject,
3894
1.91k
    // Label 302: @6959
3895
1.91k
    GIM_Try, /*On fail goto*//*Label 322*/ 7855,
3896
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3897
1.91k
      GIM_Try, /*On fail goto*//*Label 323*/ 7040, // Rule ID 18048 //
3898
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3899
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3900
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3901
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3902
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3903
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3904
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3905
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3906
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3907
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3908
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3909
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3910
1.91k
        // MIs[2] src
3911
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3912
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3913
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3914
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3915
1.91k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3916
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
3917
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3918
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3919
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3920
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3921
1.91k
        // GIR_Coverage, 18048,
3922
1.91k
        GIR_Done,
3923
1.91k
      // Label 323: @7040
3924
1.91k
      GIM_Try, /*On fail goto*//*Label 324*/ 7115, // Rule ID 18050 //
3925
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3926
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3927
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3928
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3929
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
3930
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3931
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3932
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3933
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
3934
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3935
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
3936
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3937
1.91k
        // MIs[2] src
3938
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3939
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3940
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3941
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3942
1.91k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3943
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
3944
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3945
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
3946
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3947
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3948
1.91k
        // GIR_Coverage, 18050,
3949
1.91k
        GIR_Done,
3950
1.91k
      // Label 324: @7115
3951
1.91k
      GIM_Try, /*On fail goto*//*Label 325*/ 7190, // Rule ID 18036 //
3952
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3953
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3954
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3955
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3956
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3957
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3958
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3959
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3960
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
3961
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3962
1.91k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR32RegClassID,
3963
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
3964
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3965
1.91k
        // MIs[0] src
3966
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3967
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3968
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3969
1.91k
        // (or:{ *:[i32] } (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3970
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
3971
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3972
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
3973
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
3974
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3975
1.91k
        // GIR_Coverage, 18036,
3976
1.91k
        GIR_Done,
3977
1.91k
      // Label 325: @7190
3978
1.91k
      GIM_Try, /*On fail goto*//*Label 326*/ 7265, // Rule ID 12277 //
3979
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
3980
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3981
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
3982
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3983
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
3984
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3985
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3986
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
3987
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
3988
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3989
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
3990
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
3991
1.91k
        // MIs[2] src
3992
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
3993
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
3994
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
3995
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
3996
1.91k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
3997
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr,
3998
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3999
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4000
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4001
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4002
1.91k
        // GIR_Coverage, 12277,
4003
1.91k
        GIR_Done,
4004
1.91k
      // Label 326: @7265
4005
1.91k
      GIM_Try, /*On fail goto*//*Label 327*/ 7340, // Rule ID 12279 //
4006
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4007
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4008
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4009
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4010
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4011
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4012
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4013
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4014
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4015
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4016
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4017
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4018
1.91k
        // MIs[2] src
4019
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4020
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4021
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4022
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4023
1.91k
        // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4024
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr,
4025
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4026
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4027
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4028
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4029
1.91k
        // GIR_Coverage, 12279,
4030
1.91k
        GIR_Done,
4031
1.91k
      // Label 327: @7340
4032
1.91k
      GIM_Try, /*On fail goto*//*Label 328*/ 7415, // Rule ID 12265 //
4033
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4034
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4035
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4036
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4037
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4038
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4039
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4040
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4041
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4042
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4043
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4044
1.91k
        // MIs[2] src
4045
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4046
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4047
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4048
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4049
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4050
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4051
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4052
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4053
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4054
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4055
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4056
1.91k
        // GIR_Coverage, 12265,
4057
1.91k
        GIR_Done,
4058
1.91k
      // Label 328: @7415
4059
1.91k
      GIM_Try, /*On fail goto*//*Label 329*/ 7469, // Rule ID 18044 //
4060
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4061
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4062
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4063
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4064
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4065
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4066
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4067
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4068
1.91k
        // MIs[0] src
4069
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4070
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4071
1.91k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4072
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4073
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4074
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4075
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4076
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4077
1.91k
        // GIR_Coverage, 18044,
4078
1.91k
        GIR_Done,
4079
1.91k
      // Label 329: @7469
4080
1.91k
      GIM_Try, /*On fail goto*//*Label 330*/ 7523, // Rule ID 18046 //
4081
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4082
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4083
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4084
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4085
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4086
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4087
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID,
4088
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4089
1.91k
        // MIs[0] src
4090
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4091
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4092
1.91k
        // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src)  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4093
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4094
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4095
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4096
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4097
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4098
1.91k
        // GIR_Coverage, 18046,
4099
1.91k
        GIR_Done,
4100
1.91k
      // Label 330: @7523
4101
1.91k
      GIM_Try, /*On fail goto*//*Label 331*/ 7577, // Rule ID 18038 //
4102
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4103
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4104
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4105
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4106
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4107
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4108
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4109
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID,
4110
1.91k
        // MIs[0] src
4111
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4112
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4113
1.91k
        // (or:{ *:[i32] } (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src)  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4114
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4115
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4116
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4117
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4118
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4119
1.91k
        // GIR_Coverage, 18038,
4120
1.91k
        GIR_Done,
4121
1.91k
      // Label 331: @7577
4122
1.91k
      GIM_Try, /*On fail goto*//*Label 332*/ 7631, // Rule ID 12273 //
4123
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4124
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4125
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4126
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4127
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4128
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4129
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4130
1.91k
        // MIs[1] src
4131
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4132
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4133
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4134
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }))  =>  (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4135
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr,
4136
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4137
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4138
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4139
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4140
1.91k
        // GIR_Coverage, 12273,
4141
1.91k
        GIR_Done,
4142
1.91k
      // Label 332: @7631
4143
1.91k
      GIM_Try, /*On fail goto*//*Label 333*/ 7685, // Rule ID 12275 //
4144
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4145
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4146
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4147
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4148
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4149
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4150
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4151
1.91k
        // MIs[1] src
4152
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4153
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4154
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4155
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }))  =>  (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4156
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr,
4157
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4158
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4159
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4160
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4161
1.91k
        // GIR_Coverage, 12275,
4162
1.91k
        GIR_Done,
4163
1.91k
      // Label 333: @7685
4164
1.91k
      GIM_Try, /*On fail goto*//*Label 334*/ 7739, // Rule ID 12267 //
4165
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4166
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4167
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4168
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4169
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4170
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4171
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4172
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4173
1.91k
        // MIs[1] src
4174
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4175
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4176
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src))  =>  (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src)
4177
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr,
4178
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4179
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4180
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4181
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4182
1.91k
        // GIR_Coverage, 12267,
4183
1.91k
        GIR_Done,
4184
1.91k
      // Label 334: @7739
4185
1.91k
      GIM_Try, /*On fail goto*//*Label 335*/ 7784, // Rule ID 15970 //
4186
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4187
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4188
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4189
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4190
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4191
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8,
4192
1.91k
        // MIs[1] Operand 1
4193
1.91k
        // No operand predicates
4194
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4195
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)  =>  (OR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2)
4196
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8,
4197
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4198
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4199
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4200
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4201
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4202
1.91k
        // GIR_Coverage, 15970,
4203
1.91k
        GIR_Done,
4204
1.91k
      // Label 335: @7784
4205
1.91k
      GIM_Try, /*On fail goto*//*Label 336*/ 7826, // Rule ID 15968 //
4206
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4207
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4208
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4209
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4210
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4211
1.91k
        // MIs[1] Operand 1
4212
1.91k
        // No operand predicates
4213
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4214
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)  =>  (OR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2)
4215
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri,
4216
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4217
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4218
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4219
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4220
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221
1.91k
        // GIR_Coverage, 15968,
4222
1.91k
        GIR_Done,
4223
1.91k
      // Label 336: @7826
4224
1.91k
      GIM_Try, /*On fail goto*//*Label 337*/ 7854, // Rule ID 15960 //
4225
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4226
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID,
4227
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID,
4228
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID,
4229
1.91k
        // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)  =>  (OR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2)
4230
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR32rr,
4231
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4232
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4233
1.91k
        // GIR_Coverage, 15960,
4234
1.91k
        GIR_Done,
4235
1.91k
      // Label 337: @7854
4236
1.91k
      GIM_Reject,
4237
1.91k
    // Label 322: @7855
4238
1.91k
    GIM_Reject,
4239
1.91k
    // Label 303: @7856
4240
1.91k
    GIM_Try, /*On fail goto*//*Label 338*/ 8755,
4241
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4242
1.91k
      GIM_Try, /*On fail goto*//*Label 339*/ 7937, // Rule ID 18049 //
4243
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4244
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4245
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4246
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4247
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4248
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4249
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4250
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4251
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4252
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4253
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4254
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4255
1.91k
        // MIs[2] src
4256
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4257
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4258
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4259
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4260
1.91k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4261
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4262
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4263
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4264
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4265
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4266
1.91k
        // GIR_Coverage, 18049,
4267
1.91k
        GIR_Done,
4268
1.91k
      // Label 339: @7937
4269
1.91k
      GIM_Try, /*On fail goto*//*Label 340*/ 8012, // Rule ID 18051 //
4270
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4271
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4272
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4273
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4274
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4275
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4276
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4277
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4278
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4279
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4280
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR,
4281
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4282
1.91k
        // MIs[2] src
4283
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4284
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4285
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4286
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4287
1.91k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4288
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4289
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4290
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4291
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4292
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4293
1.91k
        // GIR_Coverage, 18051,
4294
1.91k
        GIR_Done,
4295
1.91k
      // Label 340: @8012
4296
1.91k
      GIM_Try, /*On fail goto*//*Label 341*/ 8087, // Rule ID 18037 //
4297
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4298
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4299
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4300
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4301
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4302
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4303
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4304
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4305
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4306
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4307
1.91k
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR64RegClassID,
4308
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4309
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4310
1.91k
        // MIs[0] src
4311
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4312
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4313
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4314
1.91k
        // (or:{ *:[i64] } (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4315
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4316
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4317
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
4318
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4319
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4320
1.91k
        // GIR_Coverage, 18037,
4321
1.91k
        GIR_Done,
4322
1.91k
      // Label 341: @8087
4323
1.91k
      GIM_Try, /*On fail goto*//*Label 342*/ 8162, // Rule ID 12278 //
4324
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4325
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4326
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4327
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4328
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4329
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4330
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4331
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4332
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4333
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4334
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4335
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4336
1.91k
        // MIs[2] src
4337
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4338
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1,
4339
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4340
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4341
1.91k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4342
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr,
4343
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4344
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4345
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4346
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4347
1.91k
        // GIR_Coverage, 12278,
4348
1.91k
        GIR_Done,
4349
1.91k
      // Label 342: @8162
4350
1.91k
      GIM_Try, /*On fail goto*//*Label 343*/ 8237, // Rule ID 12280 //
4351
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4352
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4353
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4354
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4355
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4356
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4357
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4358
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4359
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4360
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4361
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4362
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4363
1.91k
        // MIs[2] src
4364
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
4365
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4366
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4367
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4368
1.91k
        // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4369
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr,
4370
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4371
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4372
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4373
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4374
1.91k
        // GIR_Coverage, 12280,
4375
1.91k
        GIR_Done,
4376
1.91k
      // Label 343: @8237
4377
1.91k
      GIM_Try, /*On fail goto*//*Label 344*/ 8312, // Rule ID 12266 //
4378
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4379
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4380
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4381
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4382
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4383
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4384
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4385
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4386
1.91k
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4387
1.91k
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD,
4388
1.91k
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4389
1.91k
        // MIs[2] src
4390
1.91k
        GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4391
1.91k
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1,
4392
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4393
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4394
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/2,
4395
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4396
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4397
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4398
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4399
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4400
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4401
1.91k
        // GIR_Coverage, 12266,
4402
1.91k
        GIR_Done,
4403
1.91k
      // Label 344: @8312
4404
1.91k
      GIM_Try, /*On fail goto*//*Label 345*/ 8366, // Rule ID 18045 //
4405
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4406
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4407
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4408
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4409
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4410
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4411
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4412
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4413
1.91k
        // MIs[0] src
4414
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4415
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4416
1.91k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4417
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4418
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4419
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4420
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4421
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4422
1.91k
        // GIR_Coverage, 18045,
4423
1.91k
        GIR_Done,
4424
1.91k
      // Label 345: @8366
4425
1.91k
      GIM_Try, /*On fail goto*//*Label 346*/ 8420, // Rule ID 18047 //
4426
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4427
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4428
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4429
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4430
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4431
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4432
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID,
4433
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4434
1.91k
        // MIs[0] src
4435
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
4436
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4437
1.91k
        // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src)  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4438
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4439
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4440
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
4441
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4442
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4443
1.91k
        // GIR_Coverage, 18047,
4444
1.91k
        GIR_Done,
4445
1.91k
      // Label 346: @8420
4446
1.91k
      GIM_Try, /*On fail goto*//*Label 347*/ 8474, // Rule ID 18039 //
4447
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4448
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4449
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4450
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4451
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4452
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4453
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4454
1.91k
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID,
4455
1.91k
        // MIs[0] src
4456
1.91k
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4457
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4458
1.91k
        // (or:{ *:[i64] } (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src)  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4459
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4460
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4461
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src
4462
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4463
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4464
1.91k
        // GIR_Coverage, 18039,
4465
1.91k
        GIR_Done,
4466
1.91k
      // Label 347: @8474
4467
1.91k
      GIM_Try, /*On fail goto*//*Label 348*/ 8528, // Rule ID 12274 //
4468
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4469
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4470
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4471
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4472
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4473
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4474
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4475
1.91k
        // MIs[1] src
4476
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4477
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1,
4478
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4479
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }))  =>  (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4480
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr,
4481
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4482
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4483
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4484
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4485
1.91k
        // GIR_Coverage, 12274,
4486
1.91k
        GIR_Done,
4487
1.91k
      // Label 348: @8528
4488
1.91k
      GIM_Try, /*On fail goto*//*Label 349*/ 8582, // Rule ID 12276 //
4489
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4490
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4491
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4492
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4493
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4494
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4495
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4496
1.91k
        // MIs[1] src
4497
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
4498
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4499
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4500
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }))  =>  (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4501
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr,
4502
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4503
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4504
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4505
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4506
1.91k
        // GIR_Coverage, 12276,
4507
1.91k
        GIR_Done,
4508
1.91k
      // Label 349: @8582
4509
1.91k
      GIM_Try, /*On fail goto*//*Label 350*/ 8636, // Rule ID 12268 //
4510
1.91k
        GIM_CheckFeatures, GIFBS_HasTBM,
4511
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4512
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4513
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4514
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4515
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
4516
1.91k
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
4517
1.91k
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
4518
1.91k
        // MIs[1] src
4519
1.91k
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
4520
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4521
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src))  =>  (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src)
4522
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr,
4523
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4524
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4525
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4526
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4527
1.91k
        // GIR_Coverage, 12268,
4528
1.91k
        GIR_Done,
4529
1.91k
      // Label 350: @8636
4530
1.91k
      GIM_Try, /*On fail goto*//*Label 351*/ 8681, // Rule ID 15971 //
4531
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4532
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4533
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4534
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4535
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4536
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8,
4537
1.91k
        // MIs[1] Operand 1
4538
1.91k
        // No operand predicates
4539
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4540
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)  =>  (OR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2)
4541
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri8,
4542
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4543
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4544
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4545
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4546
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4547
1.91k
        // GIR_Coverage, 15971,
4548
1.91k
        GIR_Done,
4549
1.91k
      // Label 351: @8681
4550
1.91k
      GIM_Try, /*On fail goto*//*Label 352*/ 8726, // Rule ID 15972 //
4551
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4552
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4553
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4554
1.91k
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4555
1.91k
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4556
1.91k
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32,
4557
1.91k
        // MIs[1] Operand 1
4558
1.91k
        // No operand predicates
4559
1.91k
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4560
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)  =>  (OR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2)
4561
1.91k
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri32,
4562
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4563
1.91k
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4564
1.91k
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2
4565
1.91k
        GIR_EraseFromParent, /*InsnID*/0,
4566
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4567
1.91k
        // GIR_Coverage, 15972,
4568
1.91k
        GIR_Done,
4569
1.91k
      // Label 352: @8726
4570
1.91k
      GIM_Try, /*On fail goto*//*Label 353*/ 8754, // Rule ID 15961 //
4571
1.91k
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4572
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID,
4573
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID,
4574
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID,
4575
1.91k
        // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)  =>  (OR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2)
4576
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR64rr,
4577
1.91k
        GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS,
4578
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4579
1.91k
        // GIR_Coverage, 15961,
4580
1.91k
        GIR_Done,
4581
1.91k
      // Label 353: @8754
4582
1.91k
      GIM_Reject,
4583
1.91k
    // Label 338: @8755
4584
1.91k
    GIM_Reject,
4585
1.91k
    // Label 304: @8756
4586
1.91k
    GIM_Try, /*On fail goto*//*Label 354*/ 8848, // Rule ID 13778 //
4587
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1,
4588
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1,
4589
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
4590
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID,
4591
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID,
4592
1.91k
      // (or:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
4593
1.91k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4594
1.91k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4595
1.91k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4596
1.91k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4597
1.91k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4598
1.91k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4599
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4600
1.91k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4601
1.91k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4602
1.91k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
4603
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4604
1.91k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4605
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4606
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4607
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
4608
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4609
1.91k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4610
1.91k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4611
1.91k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4612
1.91k
      GIR_EraseFromParent, /*InsnID*/0,
4613
1.91k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
4614
1.91k
      // GIR_Coverage, 13778,
4615
1.91k
      GIR_Done,
4616
1.91k
    // Label 354: @8848
4617
1.91k
    GIM_Reject,
4618
1.91k
    // Label 305: @8849
4619
1.91k
    GIM_Try, /*On fail goto*//*Label 355*/ 8929,
4620
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4621
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4622
1.91k
      GIM_Try, /*On fail goto*//*Label 356*/ 8882, // Rule ID 1551 //
4623
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX_NoVLX,
4624
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
4625
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
4626
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
4627
1.91k
        // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (VPORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
4628
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr,
4629
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4630
1.91k
        // GIR_Coverage, 1551,
4631
1.91k
        GIR_Done,
4632
1.91k
      // Label 356: @8882
4633
1.91k
      GIM_Try, /*On fail goto*//*Label 357*/ 8905, // Rule ID 1553 //
4634
1.91k
        GIM_CheckFeatures, GIFBS_UseSSE2,
4635
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID,
4636
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID,
4637
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID,
4638
1.91k
        // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)  =>  (PORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2)
4639
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr,
4640
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4641
1.91k
        // GIR_Coverage, 1553,
4642
1.91k
        GIR_Done,
4643
1.91k
      // Label 357: @8905
4644
1.91k
      GIM_Try, /*On fail goto*//*Label 358*/ 8928, // Rule ID 4938 //
4645
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
4646
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID,
4647
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID,
4648
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID,
4649
1.91k
        // (or:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)  =>  (VPORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2)
4650
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr,
4651
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4652
1.91k
        // GIR_Coverage, 4938,
4653
1.91k
        GIR_Done,
4654
1.91k
      // Label 358: @8928
4655
1.91k
      GIM_Reject,
4656
1.91k
    // Label 355: @8929
4657
1.91k
    GIM_Reject,
4658
1.91k
    // Label 306: @8930
4659
1.91k
    GIM_Try, /*On fail goto*//*Label 359*/ 9022, // Rule ID 13779 //
4660
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
4661
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
4662
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID,
4663
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID,
4664
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID,
4665
1.91k
      // (or:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] })
4666
1.91k
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4667
1.91k
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4668
1.91k
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4669
1.91k
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4670
1.91k
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4671
1.91k
      GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4672
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4673
1.91k
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4674
1.91k
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4675
1.91k
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1
4676
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4677
1.91k
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr,
4678
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4679
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4680
1.91k
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
4681
1.91k
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4682
1.91k
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4683
1.91k
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4684
1.91k
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4685
1.91k
      GIR_EraseFromParent, /*InsnID*/0,
4686
1.91k
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8,
4687
1.91k
      // GIR_Coverage, 13779,
4688
1.91k
      GIR_Done,
4689
1.91k
    // Label 359: @9022
4690
1.91k
    GIM_Reject,
4691
1.91k
    // Label 307: @9023
4692
1.91k
    GIM_Try, /*On fail goto*//*Label 360*/ 9103,
4693
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
4694
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64,
4695
1.91k
      GIM_Try, /*On fail goto*//*Label 361*/ 9056, // Rule ID 1555 //
4696
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX,
4697
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
4698
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
4699
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
4700
1.91k
        // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VPORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
4701
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr,
4702
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4703
1.91k
        // GIR_Coverage, 1555,
4704
1.91k
        GIR_Done,
4705
1.91k
      // Label 361: @9056
4706
1.91k
      GIM_Try, /*On fail goto*//*Label 362*/ 9079, // Rule ID 4929 //
4707
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX,
4708
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID,
4709
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID,
4710
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID,
4711
1.91k
        // (or:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)  =>  (VPORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2)
4712
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr,
4713
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4714
1.91k
        // GIR_Coverage, 4929,
4715
1.91k
        GIR_Done,
4716
1.91k
      // Label 362: @9079
4717
1.91k
      GIM_Try, /*On fail goto*//*Label 363*/ 9102, // Rule ID 12540 //
4718
1.91k
        GIM_CheckFeatures, GIFBS_HasAVX1Only,
4719
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID,
4720
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID,
4721
1.91k
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID,
4722
1.91k
        // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)  =>  (VORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2)
4723
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr,
4724
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4725
1.91k
        // GIR_Coverage, 12540,
4726
1.91k
        GIR_Done,
4727
1.91k
      // Label 363: @9102
4728
1.91k
      GIM_Reject,
4729
1.91k
    // Label 360: @9103
4730
1.91k
    GIM_Reject,
4731
1.91k
    // Label 308: @9104
4732
1.91k
    GIM_Try, /*On fail goto*//*Label 364*/ 9212,
4733
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
4734
1.91k
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
4735
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID,
4736
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID,
4737
1.91k
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID,
4738
1.91k
      GIM_Try, /*On fail goto*//*Label 365*/ 9137, // Rule ID 3609 //
4739
1.91k
        GIM_CheckFeatures, GIFBS_HasDQI,
4740
1.91k
        // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (KORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)
4741
1.91k
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORBrr,
4742
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4743
1.91k
        // GIR_Coverage, 3609,
4744
1.91k
        GIR_Done,
4745
1.91k
      // Label 365: @9137
4746
1.91k
      GIM_Try, /*On fail goto*//*Label 366*/ 9211, // Rule ID 13776 //
4747
1.91k
        GIM_CheckFeatures, GIFBS_NoDQI,
4748
1.91k
        // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2)  =>  (COPY_TO_REGCLASS:{ *:[v8i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] })
4749
1.91k
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
4750
1.91k
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
4751
1.91k
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
4752
1.91k
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4753
1.91k
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4754
1.91k
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2
4755
1.91k
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4756
1.91k
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,