Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace X86 {
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enum {
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  GPRRegBankID,
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  VECRRegBankID,
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  NumRegisterBanks,
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};
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} // end namespace X86
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static RegisterBank *RegBanks[];
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protected:
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  X86GenRegisterBankInfo();
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace X86 {
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (X86::GR8RegClassID - 0)) |
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    (1u << (X86::GR16RegClassID - 0)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
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    (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
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    (1u << (X86::GR32RegClassID - 0)) |
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    (1u << (X86::GR32_NOSPRegClassID - 0)) |
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    (1u << (X86::GR8_NOREXRegClassID - 0)) |
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    (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
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    (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
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    (1u << (X86::GR16_NOREXRegClassID - 0)) |
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    (1u << (X86::GR16_ABCDRegClassID - 0)) |
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    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 0)) |
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    (1u << (X86::GR32_NOREXRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (X86::GR64RegClassID - 32)) |
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    (1u << (X86::GR64_with_sub_8bitRegClassID - 32)) |
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    (1u << (X86::GR64_NOSPRegClassID - 32)) |
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    (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 32)) |
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    (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 32)) |
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    (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
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    (1u << (X86::GR32_ABCDRegClassID - 32)) |
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    (1u << (X86::GR32_TCRegClassID - 32)) |
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    (1u << (X86::GR32_ADRegClassID - 32)) |
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    (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 32)) |
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    (1u << (X86::GR64_NOREX_NOSPRegClassID - 32)) |
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    (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 32)) |
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    (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
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    (1u << (X86::GR64_NOREXRegClassID - 32)) |
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    (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 32)) |
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    (1u << (X86::GR64_TCRegClassID - 32)) |
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    (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 32)) |
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    (1u << (X86::GR64_TCW64RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) |
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    (1u << (X86::GR64_ADRegClassID - 64)) |
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    (1u << (X86::GR64_ABCDRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
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    (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) |
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    (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 64)) |
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    (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
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    0,
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};
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const uint32_t VECRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (X86::FR32XRegClassID - 0)) |
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    (1u << (X86::FR32RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (X86::FR64XRegClassID - 32)) |
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    (1u << (X86::FR64RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (X86::VR512RegClassID - 64)) |
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    (1u << (X86::VR128XRegClassID - 64)) |
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    (1u << (X86::VR256XRegClassID - 64)) |
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    (1u << (X86::VR512_with_sub_xmm_in_FR128RegClassID - 64)) |
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    (1u << (X86::FR128RegClassID - 64)) |
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    (1u << (X86::VR128RegClassID - 64)) |
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    (1u << (X86::VR256RegClassID - 64)) |
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    (1u << (X86::VR512_with_sub_xmm_in_VR128HRegClassID - 64)) |
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    (1u << (X86::VR128HRegClassID - 64)) |
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    (1u << (X86::VR256HRegClassID - 64)) |
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    (1u << (X86::VR512_with_sub_xmm_in_VR128LRegClassID - 64)) |
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    (1u << (X86::VR128LRegClassID - 64)) |
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    (1u << (X86::VR256LRegClassID - 64)) |
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    0,
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};
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RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 87);
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RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 87);
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} // end namespace X86
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RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
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    &X86::GPRRegBank,
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    &X86::VECRRegBank,
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};
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X86GenRegisterBankInfo::X86GenRegisterBankInfo()
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12.1k
    : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) {
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  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  unsigned Index = 0;
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  for (const auto &RB : RegBanks)
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    assert(Index++ == RB->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL