Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass X86MCRegisterClasses[];
17
18
namespace X86 {
19
enum {
20
  NoRegister,
21
  AH = 1,
22
  AL = 2,
23
  AX = 3,
24
  BH = 4,
25
  BL = 5,
26
  BP = 6,
27
  BPH = 7,
28
  BPL = 8,
29
  BX = 9,
30
  CH = 10,
31
  CL = 11,
32
  CS = 12,
33
  CX = 13,
34
  DF = 14,
35
  DH = 15,
36
  DI = 16,
37
  DIH = 17,
38
  DIL = 18,
39
  DL = 19,
40
  DS = 20,
41
  DX = 21,
42
  EAX = 22,
43
  EBP = 23,
44
  EBX = 24,
45
  ECX = 25,
46
  EDI = 26,
47
  EDX = 27,
48
  EFLAGS = 28,
49
  EIP = 29,
50
  EIZ = 30,
51
  ES = 31,
52
  ESI = 32,
53
  ESP = 33,
54
  FPSW = 34,
55
  FS = 35,
56
  GS = 36,
57
  HAX = 37,
58
  HBP = 38,
59
  HBX = 39,
60
  HCX = 40,
61
  HDI = 41,
62
  HDX = 42,
63
  HIP = 43,
64
  HSI = 44,
65
  HSP = 45,
66
  IP = 46,
67
  RAX = 47,
68
  RBP = 48,
69
  RBX = 49,
70
  RCX = 50,
71
  RDI = 51,
72
  RDX = 52,
73
  RIP = 53,
74
  RIZ = 54,
75
  RSI = 55,
76
  RSP = 56,
77
  SI = 57,
78
  SIH = 58,
79
  SIL = 59,
80
  SP = 60,
81
  SPH = 61,
82
  SPL = 62,
83
  SS = 63,
84
  SSP = 64,
85
  BND0 = 65,
86
  BND1 = 66,
87
  BND2 = 67,
88
  BND3 = 68,
89
  CR0 = 69,
90
  CR1 = 70,
91
  CR2 = 71,
92
  CR3 = 72,
93
  CR4 = 73,
94
  CR5 = 74,
95
  CR6 = 75,
96
  CR7 = 76,
97
  CR8 = 77,
98
  CR9 = 78,
99
  CR10 = 79,
100
  CR11 = 80,
101
  CR12 = 81,
102
  CR13 = 82,
103
  CR14 = 83,
104
  CR15 = 84,
105
  DR0 = 85,
106
  DR1 = 86,
107
  DR2 = 87,
108
  DR3 = 88,
109
  DR4 = 89,
110
  DR5 = 90,
111
  DR6 = 91,
112
  DR7 = 92,
113
  DR8 = 93,
114
  DR9 = 94,
115
  DR10 = 95,
116
  DR11 = 96,
117
  DR12 = 97,
118
  DR13 = 98,
119
  DR14 = 99,
120
  DR15 = 100,
121
  FP0 = 101,
122
  FP1 = 102,
123
  FP2 = 103,
124
  FP3 = 104,
125
  FP4 = 105,
126
  FP5 = 106,
127
  FP6 = 107,
128
  FP7 = 108,
129
  K0 = 109,
130
  K1 = 110,
131
  K2 = 111,
132
  K3 = 112,
133
  K4 = 113,
134
  K5 = 114,
135
  K6 = 115,
136
  K7 = 116,
137
  MM0 = 117,
138
  MM1 = 118,
139
  MM2 = 119,
140
  MM3 = 120,
141
  MM4 = 121,
142
  MM5 = 122,
143
  MM6 = 123,
144
  MM7 = 124,
145
  R8 = 125,
146
  R9 = 126,
147
  R10 = 127,
148
  R11 = 128,
149
  R12 = 129,
150
  R13 = 130,
151
  R14 = 131,
152
  R15 = 132,
153
  ST0 = 133,
154
  ST1 = 134,
155
  ST2 = 135,
156
  ST3 = 136,
157
  ST4 = 137,
158
  ST5 = 138,
159
  ST6 = 139,
160
  ST7 = 140,
161
  XMM0 = 141,
162
  XMM1 = 142,
163
  XMM2 = 143,
164
  XMM3 = 144,
165
  XMM4 = 145,
166
  XMM5 = 146,
167
  XMM6 = 147,
168
  XMM7 = 148,
169
  XMM8 = 149,
170
  XMM9 = 150,
171
  XMM10 = 151,
172
  XMM11 = 152,
173
  XMM12 = 153,
174
  XMM13 = 154,
175
  XMM14 = 155,
176
  XMM15 = 156,
177
  XMM16 = 157,
178
  XMM17 = 158,
179
  XMM18 = 159,
180
  XMM19 = 160,
181
  XMM20 = 161,
182
  XMM21 = 162,
183
  XMM22 = 163,
184
  XMM23 = 164,
185
  XMM24 = 165,
186
  XMM25 = 166,
187
  XMM26 = 167,
188
  XMM27 = 168,
189
  XMM28 = 169,
190
  XMM29 = 170,
191
  XMM30 = 171,
192
  XMM31 = 172,
193
  YMM0 = 173,
194
  YMM1 = 174,
195
  YMM2 = 175,
196
  YMM3 = 176,
197
  YMM4 = 177,
198
  YMM5 = 178,
199
  YMM6 = 179,
200
  YMM7 = 180,
201
  YMM8 = 181,
202
  YMM9 = 182,
203
  YMM10 = 183,
204
  YMM11 = 184,
205
  YMM12 = 185,
206
  YMM13 = 186,
207
  YMM14 = 187,
208
  YMM15 = 188,
209
  YMM16 = 189,
210
  YMM17 = 190,
211
  YMM18 = 191,
212
  YMM19 = 192,
213
  YMM20 = 193,
214
  YMM21 = 194,
215
  YMM22 = 195,
216
  YMM23 = 196,
217
  YMM24 = 197,
218
  YMM25 = 198,
219
  YMM26 = 199,
220
  YMM27 = 200,
221
  YMM28 = 201,
222
  YMM29 = 202,
223
  YMM30 = 203,
224
  YMM31 = 204,
225
  ZMM0 = 205,
226
  ZMM1 = 206,
227
  ZMM2 = 207,
228
  ZMM3 = 208,
229
  ZMM4 = 209,
230
  ZMM5 = 210,
231
  ZMM6 = 211,
232
  ZMM7 = 212,
233
  ZMM8 = 213,
234
  ZMM9 = 214,
235
  ZMM10 = 215,
236
  ZMM11 = 216,
237
  ZMM12 = 217,
238
  ZMM13 = 218,
239
  ZMM14 = 219,
240
  ZMM15 = 220,
241
  ZMM16 = 221,
242
  ZMM17 = 222,
243
  ZMM18 = 223,
244
  ZMM19 = 224,
245
  ZMM20 = 225,
246
  ZMM21 = 226,
247
  ZMM22 = 227,
248
  ZMM23 = 228,
249
  ZMM24 = 229,
250
  ZMM25 = 230,
251
  ZMM26 = 231,
252
  ZMM27 = 232,
253
  ZMM28 = 233,
254
  ZMM29 = 234,
255
  ZMM30 = 235,
256
  ZMM31 = 236,
257
  R8B = 237,
258
  R9B = 238,
259
  R10B = 239,
260
  R11B = 240,
261
  R12B = 241,
262
  R13B = 242,
263
  R14B = 243,
264
  R15B = 244,
265
  R8BH = 245,
266
  R9BH = 246,
267
  R10BH = 247,
268
  R11BH = 248,
269
  R12BH = 249,
270
  R13BH = 250,
271
  R14BH = 251,
272
  R15BH = 252,
273
  R8D = 253,
274
  R9D = 254,
275
  R10D = 255,
276
  R11D = 256,
277
  R12D = 257,
278
  R13D = 258,
279
  R14D = 259,
280
  R15D = 260,
281
  R8W = 261,
282
  R9W = 262,
283
  R10W = 263,
284
  R11W = 264,
285
  R12W = 265,
286
  R13W = 266,
287
  R14W = 267,
288
  R15W = 268,
289
  R8WH = 269,
290
  R9WH = 270,
291
  R10WH = 271,
292
  R11WH = 272,
293
  R12WH = 273,
294
  R13WH = 274,
295
  R14WH = 275,
296
  R15WH = 276,
297
  NUM_TARGET_REGS   // 277
298
};
299
} // end namespace X86
300
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// Register classes
302
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namespace X86 {
304
enum {
305
  GR8RegClassID = 0,
306
  GRH8RegClassID = 1,
307
  GR8_NOREXRegClassID = 2,
308
  GR8_ABCD_HRegClassID = 3,
309
  GR8_ABCD_LRegClassID = 4,
310
  GRH16RegClassID = 5,
311
  GR16RegClassID = 6,
312
  GR16_NOREXRegClassID = 7,
313
  VK1RegClassID = 8,
314
  VK16RegClassID = 9,
315
  VK2RegClassID = 10,
316
  VK4RegClassID = 11,
317
  VK8RegClassID = 12,
318
  VK16WMRegClassID = 13,
319
  VK1WMRegClassID = 14,
320
  VK2WMRegClassID = 15,
321
  VK4WMRegClassID = 16,
322
  VK8WMRegClassID = 17,
323
  SEGMENT_REGRegClassID = 18,
324
  GR16_ABCDRegClassID = 19,
325
  FPCCRRegClassID = 20,
326
  FR32XRegClassID = 21,
327
  LOW32_ADDR_ACCESS_RBPRegClassID = 22,
328
  LOW32_ADDR_ACCESSRegClassID = 23,
329
  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24,
330
  DEBUG_REGRegClassID = 25,
331
  FR32RegClassID = 26,
332
  GR32RegClassID = 27,
333
  GR32_NOSPRegClassID = 28,
334
  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29,
335
  GR32_NOREXRegClassID = 30,
336
  VK32RegClassID = 31,
337
  GR32_NOREX_NOSPRegClassID = 32,
338
  RFP32RegClassID = 33,
339
  VK32WMRegClassID = 34,
340
  GR32_ABCDRegClassID = 35,
341
  GR32_TCRegClassID = 36,
342
  GR32_ABCD_and_GR32_TCRegClassID = 37,
343
  GR32_ADRegClassID = 38,
344
  GR32_BPSPRegClassID = 39,
345
  GR32_BSIRegClassID = 40,
346
  GR32_CBRegClassID = 41,
347
  GR32_DCRegClassID = 42,
348
  GR32_DIBPRegClassID = 43,
349
  GR32_SIDIRegClassID = 44,
350
  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 45,
351
  CCRRegClassID = 46,
352
  DFCCRRegClassID = 47,
353
  GR32_ABCD_and_GR32_BSIRegClassID = 48,
354
  GR32_AD_and_GR32_DCRegClassID = 49,
355
  GR32_BPSP_and_GR32_DIBPRegClassID = 50,
356
  GR32_BPSP_and_GR32_TCRegClassID = 51,
357
  GR32_BSI_and_GR32_SIDIRegClassID = 52,
358
  GR32_CB_and_GR32_DCRegClassID = 53,
359
  GR32_DIBP_and_GR32_SIDIRegClassID = 54,
360
  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 55,
361
  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 56,
362
  RFP64RegClassID = 57,
363
  FR64XRegClassID = 58,
364
  GR64RegClassID = 59,
365
  CONTROL_REGRegClassID = 60,
366
  FR64RegClassID = 61,
367
  GR64_with_sub_8bitRegClassID = 62,
368
  GR64_NOSPRegClassID = 63,
369
  GR64_TCRegClassID = 64,
370
  GR64_NOREXRegClassID = 65,
371
  GR64_TCW64RegClassID = 66,
372
  GR64_TC_with_sub_8bitRegClassID = 67,
373
  GR64_NOSP_and_GR64_TCRegClassID = 68,
374
  GR64_TCW64_with_sub_8bitRegClassID = 69,
375
  GR64_TC_and_GR64_TCW64RegClassID = 70,
376
  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 71,
377
  VK64RegClassID = 72,
378
  VR64RegClassID = 73,
379
  GR64_NOREX_NOSPRegClassID = 74,
380
  GR64_NOREX_and_GR64_TCRegClassID = 75,
381
  GR64_NOSP_and_GR64_TCW64RegClassID = 76,
382
  GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 77,
383
  VK64WMRegClassID = 78,
384
  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 79,
385
  GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 80,
386
  GR64_NOREX_NOSP_and_GR64_TCRegClassID = 81,
387
  GR64_NOREX_and_GR64_TCW64RegClassID = 82,
388
  GR64_ABCDRegClassID = 83,
389
  GR64_with_sub_32bit_in_GR32_TCRegClassID = 84,
390
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 85,
391
  GR64_ADRegClassID = 86,
392
  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 87,
393
  GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 88,
394
  GR64_with_sub_32bit_in_GR32_BSIRegClassID = 89,
395
  GR64_with_sub_32bit_in_GR32_CBRegClassID = 90,
396
  GR64_with_sub_32bit_in_GR32_DCRegClassID = 91,
397
  GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 92,
398
  GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 93,
399
  GR64_and_LOW32_ADDR_ACCESSRegClassID = 94,
400
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 95,
401
  GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 96,
402
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 97,
403
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 98,
404
  GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 99,
405
  GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 100,
406
  GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 101,
407
  RSTRegClassID = 102,
408
  RFP80RegClassID = 103,
409
  VR128XRegClassID = 104,
410
  VR128RegClassID = 105,
411
  VR128HRegClassID = 106,
412
  VR128LRegClassID = 107,
413
  BNDRRegClassID = 108,
414
  VR256XRegClassID = 109,
415
  VR256RegClassID = 110,
416
  VR256HRegClassID = 111,
417
  VR256LRegClassID = 112,
418
  VR512RegClassID = 113,
419
  VR512_with_sub_xmm_in_FR32RegClassID = 114,
420
  VR512_with_sub_xmm_in_VR128HRegClassID = 115,
421
  VR512_with_sub_xmm_in_VR128LRegClassID = 116,
422
423
  };
424
} // end namespace X86
425
426
427
// Subregister indices
428
429
namespace X86 {
430
enum {
431
  NoSubRegister,
432
  sub_8bit, // 1
433
  sub_8bit_hi,  // 2
434
  sub_8bit_hi_phony,  // 3
435
  sub_16bit,  // 4
436
  sub_16bit_hi, // 5
437
  sub_32bit,  // 6
438
  sub_xmm,  // 7
439
  sub_ymm,  // 8
440
  NUM_TARGET_SUBREGS
441
};
442
} // end namespace X86
443
444
} // end namespace llvm
445
446
#endif // GET_REGINFO_ENUM
447
448
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
449
|*                                                                            *|
450
|* MC Register Information                                                    *|
451
|*                                                                            *|
452
|* Automatically generated file, do not edit!                                 *|
453
|*                                                                            *|
454
\*===----------------------------------------------------------------------===*/
455
456
457
#ifdef GET_REGINFO_MC_DESC
458
#undef GET_REGINFO_MC_DESC
459
460
namespace llvm {
461
462
extern const MCPhysReg X86RegDiffLists[] = {
463
  /* 0 */ 0, 1, 0,
464
  /* 3 */ 64875, 1, 1, 0,
465
  /* 7 */ 65259, 1, 1, 0,
466
  /* 11 */ 65397, 1, 1, 0,
467
  /* 15 */ 65466, 1, 1, 0,
468
  /* 19 */ 2, 1, 0,
469
  /* 22 */ 4, 1, 0,
470
  /* 25 */ 6, 1, 0,
471
  /* 28 */ 11, 1, 0,
472
  /* 31 */ 22, 1, 0,
473
  /* 34 */ 26, 1, 0,
474
  /* 37 */ 29, 1, 0,
475
  /* 40 */ 64851, 1, 0,
476
  /* 43 */ 10, 3, 0,
477
  /* 46 */ 4, 0,
478
  /* 48 */ 5, 0,
479
  /* 50 */ 65292, 1, 7, 0,
480
  /* 54 */ 65417, 1, 7, 0,
481
  /* 58 */ 10, 3, 7, 0,
482
  /* 62 */ 65512, 8, 0,
483
  /* 65 */ 65342, 1, 11, 0,
484
  /* 69 */ 65348, 1, 11, 0,
485
  /* 73 */ 65442, 1, 11, 0,
486
  /* 77 */ 65448, 1, 11, 0,
487
  /* 81 */ 12, 0,
488
  /* 83 */ 65342, 1, 14, 0,
489
  /* 87 */ 65348, 1, 14, 0,
490
  /* 91 */ 65442, 1, 14, 0,
491
  /* 95 */ 65448, 1, 14, 0,
492
  /* 99 */ 21, 0,
493
  /* 101 */ 22, 0,
494
  /* 103 */ 65534, 65509, 23, 0,
495
  /* 107 */ 65535, 65509, 23, 0,
496
  /* 111 */ 65534, 65511, 23, 0,
497
  /* 115 */ 65535, 65511, 23, 0,
498
  /* 119 */ 65524, 23, 0,
499
  /* 122 */ 128, 8, 65512, 8, 24, 0,
500
  /* 128 */ 65519, 24, 0,
501
  /* 131 */ 65522, 24, 0,
502
  /* 134 */ 65511, 65526, 2, 65535, 24, 0,
503
  /* 140 */ 2, 6, 25, 0,
504
  /* 144 */ 6, 6, 25, 0,
505
  /* 148 */ 65534, 10, 25, 0,
506
  /* 152 */ 65535, 10, 25, 0,
507
  /* 156 */ 2, 12, 25, 0,
508
  /* 160 */ 3, 12, 25, 0,
509
  /* 164 */ 4, 15, 25, 0,
510
  /* 168 */ 5, 15, 25, 0,
511
  /* 172 */ 65534, 17, 25, 0,
512
  /* 176 */ 65535, 17, 25, 0,
513
  /* 180 */ 1, 19, 25, 0,
514
  /* 184 */ 2, 19, 25, 0,
515
  /* 188 */ 65521, 25, 0,
516
  /* 191 */ 26, 0,
517
  /* 193 */ 65511, 65530, 65534, 65532, 27, 0,
518
  /* 199 */ 65511, 65524, 65534, 65535, 30, 0,
519
  /* 205 */ 65511, 65519, 2, 65535, 31, 0,
520
  /* 211 */ 32, 32, 0,
521
  /* 214 */ 65511, 65521, 65532, 65535, 35, 0,
522
  /* 220 */ 65511, 65517, 65535, 65535, 36, 0,
523
  /* 226 */ 64829, 0,
524
  /* 228 */ 64900, 0,
525
  /* 230 */ 64923, 0,
526
  /* 232 */ 65131, 0,
527
  /* 234 */ 65520, 65408, 0,
528
  /* 237 */ 16, 65528, 65408, 0,
529
  /* 241 */ 24, 65528, 65408, 0,
530
  /* 245 */ 65430, 0,
531
  /* 247 */ 65432, 0,
532
  /* 249 */ 65461, 0,
533
  /* 251 */ 65493, 0,
534
  /* 253 */ 65504, 65504, 0,
535
  /* 256 */ 65509, 0,
536
  /* 258 */ 65511, 0,
537
  /* 260 */ 65514, 0,
538
  /* 262 */ 65513, 27, 2, 65535, 65520, 0,
539
  /* 268 */ 65513, 25, 2, 65535, 65522, 0,
540
  /* 274 */ 65525, 0,
541
  /* 276 */ 65530, 0,
542
  /* 278 */ 65531, 0,
543
  /* 280 */ 65534, 65532, 0,
544
  /* 283 */ 65512, 17, 65533, 0,
545
  /* 287 */ 65534, 0,
546
  /* 289 */ 2, 65535, 0,
547
  /* 292 */ 65532, 65535, 0,
548
  /* 295 */ 65534, 65535, 0,
549
  /* 298 */ 65535, 65535, 0,
550
};
551
552
extern const LaneBitmask X86LaneMaskLists[] = {
553
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
554
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
555
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(),
556
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(),
557
  /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
558
  /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(),
559
  /* 19 */ LaneBitmask(0x00000010), LaneBitmask::getAll(),
560
};
561
562
extern const uint16_t X86SubRegIdxLists[] = {
563
  /* 0 */ 1, 2, 0,
564
  /* 3 */ 1, 3, 0,
565
  /* 6 */ 6, 4, 1, 2, 5, 0,
566
  /* 12 */ 6, 4, 1, 3, 5, 0,
567
  /* 18 */ 6, 4, 5, 0,
568
  /* 22 */ 8, 7, 0,
569
};
570
571
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
572
  { 65535, 65535 },
573
  { 0, 8 }, // sub_8bit
574
  { 8, 8 }, // sub_8bit_hi
575
  { 8, 8 }, // sub_8bit_hi_phony
576
  { 0, 16 },  // sub_16bit
577
  { 16, 16 }, // sub_16bit_hi
578
  { 0, 32 },  // sub_32bit
579
  { 0, 128 }, // sub_xmm
580
  { 0, 256 }, // sub_ymm
581
};
582
583
extern const char X86RegStrings[] = {
584
  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
585
  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
586
  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
587
  /* 18 */ 'C', 'R', '1', '0', 0,
588
  /* 23 */ 'D', 'R', '1', '0', 0,
589
  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
590
  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
591
  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
592
  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
593
  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
594
  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
595
  /* 64 */ 'B', 'N', 'D', '0', 0,
596
  /* 69 */ 'K', '0', 0,
597
  /* 72 */ 'X', 'M', 'M', '0', 0,
598
  /* 77 */ 'Y', 'M', 'M', '0', 0,
599
  /* 82 */ 'Z', 'M', 'M', '0', 0,
600
  /* 87 */ 'F', 'P', '0', 0,
601
  /* 91 */ 'C', 'R', '0', 0,
602
  /* 95 */ 'D', 'R', '0', 0,
603
  /* 99 */ 'S', 'T', '0', 0,
604
  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
605
  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
606
  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
607
  /* 121 */ 'C', 'R', '1', '1', 0,
608
  /* 126 */ 'D', 'R', '1', '1', 0,
609
  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
610
  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
611
  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
612
  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
613
  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
614
  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
615
  /* 167 */ 'B', 'N', 'D', '1', 0,
616
  /* 172 */ 'K', '1', 0,
617
  /* 175 */ 'X', 'M', 'M', '1', 0,
618
  /* 180 */ 'Y', 'M', 'M', '1', 0,
619
  /* 185 */ 'Z', 'M', 'M', '1', 0,
620
  /* 190 */ 'F', 'P', '1', 0,
621
  /* 194 */ 'C', 'R', '1', 0,
622
  /* 198 */ 'D', 'R', '1', 0,
623
  /* 202 */ 'S', 'T', '1', 0,
624
  /* 206 */ 'X', 'M', 'M', '1', '2', 0,
625
  /* 212 */ 'Y', 'M', 'M', '1', '2', 0,
626
  /* 218 */ 'Z', 'M', 'M', '1', '2', 0,
627
  /* 224 */ 'C', 'R', '1', '2', 0,
628
  /* 229 */ 'D', 'R', '1', '2', 0,
629
  /* 234 */ 'X', 'M', 'M', '2', '2', 0,
630
  /* 240 */ 'Y', 'M', 'M', '2', '2', 0,
631
  /* 246 */ 'Z', 'M', 'M', '2', '2', 0,
632
  /* 252 */ 'B', 'N', 'D', '2', 0,
633
  /* 257 */ 'K', '2', 0,
634
  /* 260 */ 'X', 'M', 'M', '2', 0,
635
  /* 265 */ 'Y', 'M', 'M', '2', 0,
636
  /* 270 */ 'Z', 'M', 'M', '2', 0,
637
  /* 275 */ 'F', 'P', '2', 0,
638
  /* 279 */ 'C', 'R', '2', 0,
639
  /* 283 */ 'D', 'R', '2', 0,
640
  /* 287 */ 'S', 'T', '2', 0,
641
  /* 291 */ 'X', 'M', 'M', '1', '3', 0,
642
  /* 297 */ 'Y', 'M', 'M', '1', '3', 0,
643
  /* 303 */ 'Z', 'M', 'M', '1', '3', 0,
644
  /* 309 */ 'C', 'R', '1', '3', 0,
645
  /* 314 */ 'D', 'R', '1', '3', 0,
646
  /* 319 */ 'X', 'M', 'M', '2', '3', 0,
647
  /* 325 */ 'Y', 'M', 'M', '2', '3', 0,
648
  /* 331 */ 'Z', 'M', 'M', '2', '3', 0,
649
  /* 337 */ 'B', 'N', 'D', '3', 0,
650
  /* 342 */ 'K', '3', 0,
651
  /* 345 */ 'X', 'M', 'M', '3', 0,
652
  /* 350 */ 'Y', 'M', 'M', '3', 0,
653
  /* 355 */ 'Z', 'M', 'M', '3', 0,
654
  /* 360 */ 'F', 'P', '3', 0,
655
  /* 364 */ 'C', 'R', '3', 0,
656
  /* 368 */ 'D', 'R', '3', 0,
657
  /* 372 */ 'S', 'T', '3', 0,
658
  /* 376 */ 'X', 'M', 'M', '1', '4', 0,
659
  /* 382 */ 'Y', 'M', 'M', '1', '4', 0,
660
  /* 388 */ 'Z', 'M', 'M', '1', '4', 0,
661
  /* 394 */ 'C', 'R', '1', '4', 0,
662
  /* 399 */ 'D', 'R', '1', '4', 0,
663
  /* 404 */ 'X', 'M', 'M', '2', '4', 0,
664
  /* 410 */ 'Y', 'M', 'M', '2', '4', 0,
665
  /* 416 */ 'Z', 'M', 'M', '2', '4', 0,
666
  /* 422 */ 'K', '4', 0,
667
  /* 425 */ 'X', 'M', 'M', '4', 0,
668
  /* 430 */ 'Y', 'M', 'M', '4', 0,
669
  /* 435 */ 'Z', 'M', 'M', '4', 0,
670
  /* 440 */ 'F', 'P', '4', 0,
671
  /* 444 */ 'C', 'R', '4', 0,
672
  /* 448 */ 'D', 'R', '4', 0,
673
  /* 452 */ 'S', 'T', '4', 0,
674
  /* 456 */ 'X', 'M', 'M', '1', '5', 0,
675
  /* 462 */ 'Y', 'M', 'M', '1', '5', 0,
676
  /* 468 */ 'Z', 'M', 'M', '1', '5', 0,
677
  /* 474 */ 'C', 'R', '1', '5', 0,
678
  /* 479 */ 'D', 'R', '1', '5', 0,
679
  /* 484 */ 'X', 'M', 'M', '2', '5', 0,
680
  /* 490 */ 'Y', 'M', 'M', '2', '5', 0,
681
  /* 496 */ 'Z', 'M', 'M', '2', '5', 0,
682
  /* 502 */ 'K', '5', 0,
683
  /* 505 */ 'X', 'M', 'M', '5', 0,
684
  /* 510 */ 'Y', 'M', 'M', '5', 0,
685
  /* 515 */ 'Z', 'M', 'M', '5', 0,
686
  /* 520 */ 'F', 'P', '5', 0,
687
  /* 524 */ 'C', 'R', '5', 0,
688
  /* 528 */ 'D', 'R', '5', 0,
689
  /* 532 */ 'S', 'T', '5', 0,
690
  /* 536 */ 'X', 'M', 'M', '1', '6', 0,
691
  /* 542 */ 'Y', 'M', 'M', '1', '6', 0,
692
  /* 548 */ 'Z', 'M', 'M', '1', '6', 0,
693
  /* 554 */ 'X', 'M', 'M', '2', '6', 0,
694
  /* 560 */ 'Y', 'M', 'M', '2', '6', 0,
695
  /* 566 */ 'Z', 'M', 'M', '2', '6', 0,
696
  /* 572 */ 'K', '6', 0,
697
  /* 575 */ 'X', 'M', 'M', '6', 0,
698
  /* 580 */ 'Y', 'M', 'M', '6', 0,
699
  /* 585 */ 'Z', 'M', 'M', '6', 0,
700
  /* 590 */ 'F', 'P', '6', 0,
701
  /* 594 */ 'C', 'R', '6', 0,
702
  /* 598 */ 'D', 'R', '6', 0,
703
  /* 602 */ 'S', 'T', '6', 0,
704
  /* 606 */ 'X', 'M', 'M', '1', '7', 0,
705
  /* 612 */ 'Y', 'M', 'M', '1', '7', 0,
706
  /* 618 */ 'Z', 'M', 'M', '1', '7', 0,
707
  /* 624 */ 'X', 'M', 'M', '2', '7', 0,
708
  /* 630 */ 'Y', 'M', 'M', '2', '7', 0,
709
  /* 636 */ 'Z', 'M', 'M', '2', '7', 0,
710
  /* 642 */ 'K', '7', 0,
711
  /* 645 */ 'X', 'M', 'M', '7', 0,
712
  /* 650 */ 'Y', 'M', 'M', '7', 0,
713
  /* 655 */ 'Z', 'M', 'M', '7', 0,
714
  /* 660 */ 'F', 'P', '7', 0,
715
  /* 664 */ 'C', 'R', '7', 0,
716
  /* 668 */ 'D', 'R', '7', 0,
717
  /* 672 */ 'S', 'T', '7', 0,
718
  /* 676 */ 'X', 'M', 'M', '1', '8', 0,
719
  /* 682 */ 'Y', 'M', 'M', '1', '8', 0,
720
  /* 688 */ 'Z', 'M', 'M', '1', '8', 0,
721
  /* 694 */ 'X', 'M', 'M', '2', '8', 0,
722
  /* 700 */ 'Y', 'M', 'M', '2', '8', 0,
723
  /* 706 */ 'Z', 'M', 'M', '2', '8', 0,
724
  /* 712 */ 'X', 'M', 'M', '8', 0,
725
  /* 717 */ 'Y', 'M', 'M', '8', 0,
726
  /* 722 */ 'Z', 'M', 'M', '8', 0,
727
  /* 727 */ 'C', 'R', '8', 0,
728
  /* 731 */ 'D', 'R', '8', 0,
729
  /* 735 */ 'X', 'M', 'M', '1', '9', 0,
730
  /* 741 */ 'Y', 'M', 'M', '1', '9', 0,
731
  /* 747 */ 'Z', 'M', 'M', '1', '9', 0,
732
  /* 753 */ 'X', 'M', 'M', '2', '9', 0,
733
  /* 759 */ 'Y', 'M', 'M', '2', '9', 0,
734
  /* 765 */ 'Z', 'M', 'M', '2', '9', 0,
735
  /* 771 */ 'X', 'M', 'M', '9', 0,
736
  /* 776 */ 'Y', 'M', 'M', '9', 0,
737
  /* 781 */ 'Z', 'M', 'M', '9', 0,
738
  /* 786 */ 'C', 'R', '9', 0,
739
  /* 790 */ 'D', 'R', '9', 0,
740
  /* 794 */ 'R', '1', '0', 'B', 0,
741
  /* 799 */ 'R', '1', '1', 'B', 0,
742
  /* 804 */ 'R', '1', '2', 'B', 0,
743
  /* 809 */ 'R', '1', '3', 'B', 0,
744
  /* 814 */ 'R', '1', '4', 'B', 0,
745
  /* 819 */ 'R', '1', '5', 'B', 0,
746
  /* 824 */ 'R', '8', 'B', 0,
747
  /* 828 */ 'R', '9', 'B', 0,
748
  /* 832 */ 'R', '1', '0', 'D', 0,
749
  /* 837 */ 'R', '1', '1', 'D', 0,
750
  /* 842 */ 'R', '1', '2', 'D', 0,
751
  /* 847 */ 'R', '1', '3', 'D', 0,
752
  /* 852 */ 'R', '1', '4', 'D', 0,
753
  /* 857 */ 'R', '1', '5', 'D', 0,
754
  /* 862 */ 'R', '8', 'D', 0,
755
  /* 866 */ 'R', '9', 'D', 0,
756
  /* 870 */ 'D', 'F', 0,
757
  /* 873 */ 'A', 'H', 0,
758
  /* 876 */ 'R', '1', '0', 'B', 'H', 0,
759
  /* 882 */ 'R', '1', '1', 'B', 'H', 0,
760
  /* 888 */ 'R', '1', '2', 'B', 'H', 0,
761
  /* 894 */ 'R', '1', '3', 'B', 'H', 0,
762
  /* 900 */ 'R', '1', '4', 'B', 'H', 0,
763
  /* 906 */ 'R', '1', '5', 'B', 'H', 0,
764
  /* 912 */ 'R', '8', 'B', 'H', 0,
765
  /* 917 */ 'R', '9', 'B', 'H', 0,
766
  /* 922 */ 'C', 'H', 0,
767
  /* 925 */ 'D', 'H', 0,
768
  /* 928 */ 'D', 'I', 'H', 0,
769
  /* 932 */ 'S', 'I', 'H', 0,
770
  /* 936 */ 'B', 'P', 'H', 0,
771
  /* 940 */ 'S', 'P', 'H', 0,
772
  /* 944 */ 'R', '1', '0', 'W', 'H', 0,
773
  /* 950 */ 'R', '1', '1', 'W', 'H', 0,
774
  /* 956 */ 'R', '1', '2', 'W', 'H', 0,
775
  /* 962 */ 'R', '1', '3', 'W', 'H', 0,
776
  /* 968 */ 'R', '1', '4', 'W', 'H', 0,
777
  /* 974 */ 'R', '1', '5', 'W', 'H', 0,
778
  /* 980 */ 'R', '8', 'W', 'H', 0,
779
  /* 985 */ 'R', '9', 'W', 'H', 0,
780
  /* 990 */ 'E', 'D', 'I', 0,
781
  /* 994 */ 'H', 'D', 'I', 0,
782
  /* 998 */ 'R', 'D', 'I', 0,
783
  /* 1002 */ 'E', 'S', 'I', 0,
784
  /* 1006 */ 'H', 'S', 'I', 0,
785
  /* 1010 */ 'R', 'S', 'I', 0,
786
  /* 1014 */ 'A', 'L', 0,
787
  /* 1017 */ 'B', 'L', 0,
788
  /* 1020 */ 'C', 'L', 0,
789
  /* 1023 */ 'D', 'L', 0,
790
  /* 1026 */ 'D', 'I', 'L', 0,
791
  /* 1030 */ 'S', 'I', 'L', 0,
792
  /* 1034 */ 'B', 'P', 'L', 0,
793
  /* 1038 */ 'S', 'P', 'L', 0,
794
  /* 1042 */ 'E', 'B', 'P', 0,
795
  /* 1046 */ 'H', 'B', 'P', 0,
796
  /* 1050 */ 'R', 'B', 'P', 0,
797
  /* 1054 */ 'E', 'I', 'P', 0,
798
  /* 1058 */ 'H', 'I', 'P', 0,
799
  /* 1062 */ 'R', 'I', 'P', 0,
800
  /* 1066 */ 'E', 'S', 'P', 0,
801
  /* 1070 */ 'H', 'S', 'P', 0,
802
  /* 1074 */ 'R', 'S', 'P', 0,
803
  /* 1078 */ 'S', 'S', 'P', 0,
804
  /* 1082 */ 'C', 'S', 0,
805
  /* 1085 */ 'D', 'S', 0,
806
  /* 1088 */ 'E', 'S', 0,
807
  /* 1091 */ 'F', 'S', 0,
808
  /* 1094 */ 'E', 'F', 'L', 'A', 'G', 'S', 0,
809
  /* 1101 */ 'S', 'S', 0,
810
  /* 1104 */ 'R', '1', '0', 'W', 0,
811
  /* 1109 */ 'R', '1', '1', 'W', 0,
812
  /* 1114 */ 'R', '1', '2', 'W', 0,
813
  /* 1119 */ 'R', '1', '3', 'W', 0,
814
  /* 1124 */ 'R', '1', '4', 'W', 0,
815
  /* 1129 */ 'R', '1', '5', 'W', 0,
816
  /* 1134 */ 'R', '8', 'W', 0,
817
  /* 1138 */ 'R', '9', 'W', 0,
818
  /* 1142 */ 'F', 'P', 'S', 'W', 0,
819
  /* 1147 */ 'E', 'A', 'X', 0,
820
  /* 1151 */ 'H', 'A', 'X', 0,
821
  /* 1155 */ 'R', 'A', 'X', 0,
822
  /* 1159 */ 'E', 'B', 'X', 0,
823
  /* 1163 */ 'H', 'B', 'X', 0,
824
  /* 1167 */ 'R', 'B', 'X', 0,
825
  /* 1171 */ 'E', 'C', 'X', 0,
826
  /* 1175 */ 'H', 'C', 'X', 0,
827
  /* 1179 */ 'R', 'C', 'X', 0,
828
  /* 1183 */ 'E', 'D', 'X', 0,
829
  /* 1187 */ 'H', 'D', 'X', 0,
830
  /* 1191 */ 'R', 'D', 'X', 0,
831
  /* 1195 */ 'E', 'I', 'Z', 0,
832
  /* 1199 */ 'R', 'I', 'Z', 0,
833
};
834
835
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
836
  { 5, 0, 0, 0, 0, 0 },
837
  { 873, 2, 184, 2, 4641, 0 },
838
  { 1014, 2, 180, 2, 4641, 0 },
839
  { 1148, 298, 181, 0, 0, 2 },
840
  { 879, 2, 168, 2, 4593, 0 },
841
  { 1017, 2, 164, 2, 4593, 0 },
842
  { 1043, 289, 173, 3, 352, 5 },
843
  { 936, 2, 176, 2, 768, 0 },
844
  { 1034, 2, 172, 2, 736, 0 },
845
  { 1160, 292, 165, 0, 304, 2 },
846
  { 922, 2, 160, 2, 4497, 0 },
847
  { 1020, 2, 156, 2, 4497, 0 },
848
  { 1082, 2, 2, 2, 4497, 0 },
849
  { 1172, 295, 157, 0, 400, 2 },
850
  { 870, 2, 2, 2, 4449, 0 },
851
  { 925, 2, 144, 2, 4449, 0 },
852
  { 991, 289, 149, 3, 448, 5 },
853
  { 928, 2, 152, 2, 1296, 0 },
854
  { 1026, 2, 148, 2, 4130, 0 },
855
  { 1023, 2, 140, 2, 4417, 0 },
856
  { 1085, 2, 2, 2, 4417, 0 },
857
  { 1184, 280, 141, 0, 688, 2 },
858
  { 1147, 221, 142, 7, 1524, 8 },
859
  { 1042, 206, 142, 13, 1236, 12 },
860
  { 1159, 215, 142, 7, 1460, 8 },
861
  { 1171, 200, 142, 7, 1172, 8 },
862
  { 990, 135, 142, 13, 869, 12 },
863
  { 1183, 194, 142, 7, 928, 8 },
864
  { 1094, 2, 2, 2, 1584, 0 },
865
  { 1054, 284, 126, 19, 496, 16 },
866
  { 1195, 2, 2, 2, 4417, 0 },
867
  { 1088, 2, 2, 2, 4417, 0 },
868
  { 1002, 269, 105, 13, 243, 12 },
869
  { 1066, 263, 105, 13, 243, 12 },
870
  { 1142, 2, 2, 2, 4593, 0 },
871
  { 1091, 2, 2, 2, 4593, 0 },
872
  { 1098, 2, 2, 2, 4593, 0 },
873
  { 1151, 2, 188, 2, 4161, 0 },
874
  { 1046, 2, 188, 2, 4161, 0 },
875
  { 1163, 2, 188, 2, 4161, 0 },
876
  { 1175, 2, 188, 2, 4161, 0 },
877
  { 994, 2, 188, 2, 4161, 0 },
878
  { 1187, 2, 188, 2, 4161, 0 },
879
  { 1058, 2, 131, 2, 3923, 0 },
880
  { 1006, 2, 119, 2, 3955, 0 },
881
  { 1070, 2, 119, 2, 3955, 0 },
882
  { 1055, 2, 128, 2, 1616, 0 },
883
  { 1155, 220, 2, 6, 1396, 8 },
884
  { 1050, 205, 2, 12, 1108, 12 },
885
  { 1167, 214, 2, 6, 1332, 8 },
886
  { 1179, 199, 2, 6, 1044, 8 },
887
  { 998, 134, 2, 12, 805, 12 },
888
  { 1191, 193, 2, 6, 928, 8 },
889
  { 1062, 283, 2, 18, 496, 16 },
890
  { 1199, 2, 2, 2, 3488, 0 },
891
  { 1010, 268, 2, 12, 179, 12 },
892
  { 1074, 262, 2, 12, 179, 12 },
893
  { 1003, 289, 112, 3, 544, 5 },
894
  { 932, 2, 115, 2, 3152, 0 },
895
  { 1030, 2, 111, 2, 3056, 0 },
896
  { 1067, 289, 104, 3, 592, 5 },
897
  { 940, 2, 107, 2, 3248, 0 },
898
  { 1038, 2, 103, 2, 3719, 0 },
899
  { 1101, 2, 2, 2, 4097, 0 },
900
  { 1078, 2, 2, 2, 4097, 0 },
901
  { 64, 2, 2, 2, 4097, 0 },
902
  { 167, 2, 2, 2, 4097, 0 },
903
  { 252, 2, 2, 2, 4097, 0 },
904
  { 337, 2, 2, 2, 4097, 0 },
905
  { 91, 2, 2, 2, 4097, 0 },
906
  { 194, 2, 2, 2, 4097, 0 },
907
  { 279, 2, 2, 2, 4097, 0 },
908
  { 364, 2, 2, 2, 4097, 0 },
909
  { 444, 2, 2, 2, 4097, 0 },
910
  { 524, 2, 2, 2, 4097, 0 },
911
  { 594, 2, 2, 2, 4097, 0 },
912
  { 664, 2, 2, 2, 4097, 0 },
913
  { 727, 2, 2, 2, 4097, 0 },
914
  { 786, 2, 2, 2, 4097, 0 },
915
  { 18, 2, 2, 2, 4097, 0 },
916
  { 121, 2, 2, 2, 4097, 0 },
917
  { 224, 2, 2, 2, 4097, 0 },
918
  { 309, 2, 2, 2, 4097, 0 },
919
  { 394, 2, 2, 2, 4097, 0 },
920
  { 474, 2, 2, 2, 4097, 0 },
921
  { 95, 2, 2, 2, 4097, 0 },
922
  { 198, 2, 2, 2, 4097, 0 },
923
  { 283, 2, 2, 2, 4097, 0 },
924
  { 368, 2, 2, 2, 4097, 0 },
925
  { 448, 2, 2, 2, 4097, 0 },
926
  { 528, 2, 2, 2, 4097, 0 },
927
  { 598, 2, 2, 2, 4097, 0 },
928
  { 668, 2, 2, 2, 4097, 0 },
929
  { 731, 2, 2, 2, 4097, 0 },
930
  { 790, 2, 2, 2, 4097, 0 },
931
  { 23, 2, 2, 2, 4097, 0 },
932
  { 126, 2, 2, 2, 4097, 0 },
933
  { 229, 2, 2, 2, 4097, 0 },
934
  { 314, 2, 2, 2, 4097, 0 },
935
  { 399, 2, 2, 2, 4097, 0 },
936
  { 479, 2, 2, 2, 4097, 0 },
937
  { 87, 2, 2, 2, 4097, 0 },
938
  { 190, 2, 2, 2, 4097, 0 },
939
  { 275, 2, 2, 2, 4097, 0 },
940
  { 360, 2, 2, 2, 4097, 0 },
941
  { 440, 2, 2, 2, 4097, 0 },
942
  { 520, 2, 2, 2, 4097, 0 },
943
  { 590, 2, 2, 2, 4097, 0 },
944
  { 660, 2, 2, 2, 4097, 0 },
945
  { 69, 2, 2, 2, 4097, 0 },
946
  { 172, 2, 2, 2, 4097, 0 },
947
  { 257, 2, 2, 2, 4097, 0 },
948
  { 342, 2, 2, 2, 4097, 0 },
949
  { 422, 2, 2, 2, 4097, 0 },
950
  { 502, 2, 2, 2, 4097, 0 },
951
  { 572, 2, 2, 2, 4097, 0 },
952
  { 642, 2, 2, 2, 4097, 0 },
953
  { 73, 2, 2, 2, 4097, 0 },
954
  { 176, 2, 2, 2, 4097, 0 },
955
  { 261, 2, 2, 2, 4097, 0 },
956
  { 346, 2, 2, 2, 4097, 0 },
957
  { 426, 2, 2, 2, 4097, 0 },
958
  { 506, 2, 2, 2, 4097, 0 },
959
  { 576, 2, 2, 2, 4097, 0 },
960
  { 646, 2, 2, 2, 4097, 0 },
961
  { 728, 122, 2, 12, 115, 12 },
962
  { 787, 122, 2, 12, 115, 12 },
963
  { 19, 122, 2, 12, 115, 12 },
964
  { 122, 122, 2, 12, 115, 12 },
965
  { 225, 122, 2, 12, 115, 12 },
966
  { 310, 122, 2, 12, 115, 12 },
967
  { 395, 122, 2, 12, 115, 12 },
968
  { 475, 122, 2, 12, 115, 12 },
969
  { 99, 2, 2, 2, 4385, 0 },
970
  { 202, 2, 2, 2, 4385, 0 },
971
  { 287, 2, 2, 2, 4385, 0 },
972
  { 372, 2, 2, 2, 4385, 0 },
973
  { 452, 2, 2, 2, 4385, 0 },
974
  { 532, 2, 2, 2, 4385, 0 },
975
  { 602, 2, 2, 2, 4385, 0 },
976
  { 672, 2, 2, 2, 4385, 0 },
977
  { 72, 2, 211, 2, 4385, 0 },
978
  { 175, 2, 211, 2, 4385, 0 },
979
  { 260, 2, 211, 2, 4385, 0 },
980
  { 345, 2, 211, 2, 4385, 0 },
981
  { 425, 2, 211, 2, 4385, 0 },
982
  { 505, 2, 211, 2, 4385, 0 },
983
  { 575, 2, 211, 2, 4385, 0 },
984
  { 645, 2, 211, 2, 4385, 0 },
985
  { 712, 2, 211, 2, 4385, 0 },
986
  { 771, 2, 211, 2, 4385, 0 },
987
  { 0, 2, 211, 2, 4385, 0 },
988
  { 103, 2, 211, 2, 4385, 0 },
989
  { 206, 2, 211, 2, 4385, 0 },
990
  { 291, 2, 211, 2, 4385, 0 },
991
  { 376, 2, 211, 2, 4385, 0 },
992
  { 456, 2, 211, 2, 4385, 0 },
993
  { 536, 2, 211, 2, 4385, 0 },
994
  { 606, 2, 211, 2, 4385, 0 },
995
  { 676, 2, 211, 2, 4385, 0 },
996
  { 735, 2, 211, 2, 4385, 0 },
997
  { 28, 2, 211, 2, 4385, 0 },
998
  { 131, 2, 211, 2, 4385, 0 },
999
  { 234, 2, 211, 2, 4385, 0 },
1000
  { 319, 2, 211, 2, 4385, 0 },
1001
  { 404, 2, 211, 2, 4385, 0 },
1002
  { 484, 2, 211, 2, 4385, 0 },
1003
  { 554, 2, 211, 2, 4385, 0 },
1004
  { 624, 2, 211, 2, 4385, 0 },
1005
  { 694, 2, 211, 2, 4385, 0 },
1006
  { 753, 2, 211, 2, 4385, 0 },
1007
  { 46, 2, 211, 2, 4385, 0 },
1008
  { 149, 2, 211, 2, 4385, 0 },
1009
  { 77, 254, 212, 23, 4017, 19 },
1010
  { 180, 254, 212, 23, 4017, 19 },
1011
  { 265, 254, 212, 23, 4017, 19 },
1012
  { 350, 254, 212, 23, 4017, 19 },
1013
  { 430, 254, 212, 23, 4017, 19 },
1014
  { 510, 254, 212, 23, 4017, 19 },
1015
  { 580, 254, 212, 23, 4017, 19 },
1016
  { 650, 254, 212, 23, 4017, 19 },
1017
  { 717, 254, 212, 23, 4017, 19 },
1018
  { 776, 254, 212, 23, 4017, 19 },
1019
  { 6, 254, 212, 23, 4017, 19 },
1020
  { 109, 254, 212, 23, 4017, 19 },
1021
  { 212, 254, 212, 23, 4017, 19 },
1022
  { 297, 254, 212, 23, 4017, 19 },
1023
  { 382, 254, 212, 23, 4017, 19 },
1024
  { 462, 254, 212, 23, 4017, 19 },
1025
  { 542, 254, 212, 23, 4017, 19 },
1026
  { 612, 254, 212, 23, 4017, 19 },
1027
  { 682, 254, 212, 23, 4017, 19 },
1028
  { 741, 254, 212, 23, 4017, 19 },
1029
  { 34, 254, 212, 23, 4017, 19 },
1030
  { 137, 254, 212, 23, 4017, 19 },
1031
  { 240, 254, 212, 23, 4017, 19 },
1032
  { 325, 254, 212, 23, 4017, 19 },
1033
  { 410, 254, 212, 23, 4017, 19 },
1034
  { 490, 254, 212, 23, 4017, 19 },
1035
  { 560, 254, 212, 23, 4017, 19 },
1036
  { 630, 254, 212, 23, 4017, 19 },
1037
  { 700, 254, 212, 23, 4017, 19 },
1038
  { 759, 254, 212, 23, 4017, 19 },
1039
  { 52, 254, 212, 23, 4017, 19 },
1040
  { 155, 254, 212, 23, 4017, 19 },
1041
  { 82, 253, 2, 22, 3985, 19 },
1042
  { 185, 253, 2, 22, 3985, 19 },
1043
  { 270, 253, 2, 22, 3985, 19 },
1044
  { 355, 253, 2, 22, 3985, 19 },
1045
  { 435, 253, 2, 22, 3985, 19 },
1046
  { 515, 253, 2, 22, 3985, 19 },
1047
  { 585, 253, 2, 22, 3985, 19 },
1048
  { 655, 253, 2, 22, 3985, 19 },
1049
  { 722, 253, 2, 22, 3985, 19 },
1050
  { 781, 253, 2, 22, 3985, 19 },
1051
  { 12, 253, 2, 22, 3985, 19 },
1052
  { 115, 253, 2, 22, 3985, 19 },
1053
  { 218, 253, 2, 22, 3985, 19 },
1054
  { 303, 253, 2, 22, 3985, 19 },
1055
  { 388, 253, 2, 22, 3985, 19 },
1056
  { 468, 253, 2, 22, 3985, 19 },
1057
  { 548, 253, 2, 22, 3985, 19 },
1058
  { 618, 253, 2, 22, 3985, 19 },
1059
  { 688, 253, 2, 22, 3985, 19 },
1060
  { 747, 253, 2, 22, 3985, 19 },
1061
  { 40, 253, 2, 22, 3985, 19 },
1062
  { 143, 253, 2, 22, 3985, 19 },
1063
  { 246, 253, 2, 22, 3985, 19 },
1064
  { 331, 253, 2, 22, 3985, 19 },
1065
  { 416, 253, 2, 22, 3985, 19 },
1066
  { 496, 253, 2, 22, 3985, 19 },
1067
  { 566, 253, 2, 22, 3985, 19 },
1068
  { 636, 253, 2, 22, 3985, 19 },
1069
  { 706, 253, 2, 22, 3985, 19 },
1070
  { 765, 253, 2, 22, 3985, 19 },
1071
  { 58, 253, 2, 22, 3985, 19 },
1072
  { 161, 253, 2, 22, 3985, 19 },
1073
  { 824, 2, 241, 2, 3683, 0 },
1074
  { 828, 2, 241, 2, 3683, 0 },
1075
  { 794, 2, 241, 2, 3683, 0 },
1076
  { 799, 2, 241, 2, 3683, 0 },
1077
  { 804, 2, 241, 2, 3683, 0 },
1078
  { 809, 2, 241, 2, 3683, 0 },
1079
  { 814, 2, 241, 2, 3683, 0 },
1080
  { 819, 2, 241, 2, 3683, 0 },
1081
  { 912, 2, 237, 2, 3651, 0 },
1082
  { 917, 2, 237, 2, 3651, 0 },
1083
  { 876, 2, 237, 2, 3651, 0 },
1084
  { 882, 2, 237, 2, 3651, 0 },
1085
  { 888, 2, 237, 2, 3651, 0 },
1086
  { 894, 2, 237, 2, 3651, 0 },
1087
  { 900, 2, 237, 2, 3651, 0 },
1088
  { 906, 2, 237, 2, 3651, 0 },
1089
  { 862, 123, 235, 13, 51, 12 },
1090
  { 866, 123, 235, 13, 51, 12 },
1091
  { 832, 123, 235, 13, 51, 12 },
1092
  { 837, 123, 235, 13, 51, 12 },
1093
  { 842, 123, 235, 13, 51, 12 },
1094
  { 847, 123, 235, 13, 51, 12 },
1095
  { 852, 123, 235, 13, 51, 12 },
1096
  { 857, 123, 235, 13, 51, 12 },
1097
  { 1134, 62, 238, 3, 643, 5 },
1098
  { 1138, 62, 238, 3, 643, 5 },
1099
  { 1104, 62, 238, 3, 643, 5 },
1100
  { 1109, 62, 238, 3, 643, 5 },
1101
  { 1114, 62, 238, 3, 643, 5 },
1102
  { 1119, 62, 238, 3, 643, 5 },
1103
  { 1124, 62, 238, 3, 643, 5 },
1104
  { 1129, 62, 238, 3, 643, 5 },
1105
  { 980, 2, 234, 2, 3619, 0 },
1106
  { 985, 2, 234, 2, 3619, 0 },
1107
  { 944, 2, 234, 2, 3619, 0 },
1108
  { 950, 2, 234, 2, 3619, 0 },
1109
  { 956, 2, 234, 2, 3619, 0 },
1110
  { 962, 2, 234, 2, 3619, 0 },
1111
  { 968, 2, 234, 2, 3619, 0 },
1112
  { 974, 2, 234, 2, 3619, 0 },
1113
};
1114
1115
extern const MCPhysReg X86RegUnitRoots[][2] = {
1116
  { X86::AH },
1117
  { X86::AL },
1118
  { X86::BH },
1119
  { X86::BL },
1120
  { X86::BPL },
1121
  { X86::BPH },
1122
  { X86::CH },
1123
  { X86::CL },
1124
  { X86::CS },
1125
  { X86::DF },
1126
  { X86::DH },
1127
  { X86::DIL },
1128
  { X86::DIH },
1129
  { X86::DL },
1130
  { X86::DS },
1131
  { X86::HAX },
1132
  { X86::HBP },
1133
  { X86::HBX },
1134
  { X86::HCX },
1135
  { X86::HDI },
1136
  { X86::HDX },
1137
  { X86::EFLAGS },
1138
  { X86::IP },
1139
  { X86::HIP },
1140
  { X86::EIZ },
1141
  { X86::ES },
1142
  { X86::SIL },
1143
  { X86::SIH },
1144
  { X86::HSI },
1145
  { X86::SPL },
1146
  { X86::SPH },
1147
  { X86::HSP },
1148
  { X86::FPSW },
1149
  { X86::FS },
1150
  { X86::GS },
1151
  { X86::RIZ },
1152
  { X86::SS },
1153
  { X86::SSP },
1154
  { X86::BND0 },
1155
  { X86::BND1 },
1156
  { X86::BND2 },
1157
  { X86::BND3 },
1158
  { X86::CR0 },
1159
  { X86::CR1 },
1160
  { X86::CR2 },
1161
  { X86::CR3 },
1162
  { X86::CR4 },
1163
  { X86::CR5 },
1164
  { X86::CR6 },
1165
  { X86::CR7 },
1166
  { X86::CR8 },
1167
  { X86::CR9 },
1168
  { X86::CR10 },
1169
  { X86::CR11 },
1170
  { X86::CR12 },
1171
  { X86::CR13 },
1172
  { X86::CR14 },
1173
  { X86::CR15 },
1174
  { X86::DR0 },
1175
  { X86::DR1 },
1176
  { X86::DR2 },
1177
  { X86::DR3 },
1178
  { X86::DR4 },
1179
  { X86::DR5 },
1180
  { X86::DR6 },
1181
  { X86::DR7 },
1182
  { X86::DR8 },
1183
  { X86::DR9 },
1184
  { X86::DR10 },
1185
  { X86::DR11 },
1186
  { X86::DR12 },
1187
  { X86::DR13 },
1188
  { X86::DR14 },
1189
  { X86::DR15 },
1190
  { X86::FP0 },
1191
  { X86::FP1 },
1192
  { X86::FP2 },
1193
  { X86::FP3 },
1194
  { X86::FP4 },
1195
  { X86::FP5 },
1196
  { X86::FP6 },
1197
  { X86::FP7 },
1198
  { X86::K0 },
1199
  { X86::K1 },
1200
  { X86::K2 },
1201
  { X86::K3 },
1202
  { X86::K4 },
1203
  { X86::K5 },
1204
  { X86::K6 },
1205
  { X86::K7 },
1206
  { X86::MM0 },
1207
  { X86::MM1 },
1208
  { X86::MM2 },
1209
  { X86::MM3 },
1210
  { X86::MM4 },
1211
  { X86::MM5 },
1212
  { X86::MM6 },
1213
  { X86::MM7 },
1214
  { X86::R8B },
1215
  { X86::R8BH },
1216
  { X86::R8WH },
1217
  { X86::R9B },
1218
  { X86::R9BH },
1219
  { X86::R9WH },
1220
  { X86::R10B },
1221
  { X86::R10BH },
1222
  { X86::R10WH },
1223
  { X86::R11B },
1224
  { X86::R11BH },
1225
  { X86::R11WH },
1226
  { X86::R12B },
1227
  { X86::R12BH },
1228
  { X86::R12WH },
1229
  { X86::R13B },
1230
  { X86::R13BH },
1231
  { X86::R13WH },
1232
  { X86::R14B },
1233
  { X86::R14BH },
1234
  { X86::R14WH },
1235
  { X86::R15B },
1236
  { X86::R15BH },
1237
  { X86::R15WH },
1238
  { X86::ST0 },
1239
  { X86::ST1 },
1240
  { X86::ST2 },
1241
  { X86::ST3 },
1242
  { X86::ST4 },
1243
  { X86::ST5 },
1244
  { X86::ST6 },
1245
  { X86::ST7 },
1246
  { X86::XMM0 },
1247
  { X86::XMM1 },
1248
  { X86::XMM2 },
1249
  { X86::XMM3 },
1250
  { X86::XMM4 },
1251
  { X86::XMM5 },
1252
  { X86::XMM6 },
1253
  { X86::XMM7 },
1254
  { X86::XMM8 },
1255
  { X86::XMM9 },
1256
  { X86::XMM10 },
1257
  { X86::XMM11 },
1258
  { X86::XMM12 },
1259
  { X86::XMM13 },
1260
  { X86::XMM14 },
1261
  { X86::XMM15 },
1262
  { X86::XMM16 },
1263
  { X86::XMM17 },
1264
  { X86::XMM18 },
1265
  { X86::XMM19 },
1266
  { X86::XMM20 },
1267
  { X86::XMM21 },
1268
  { X86::XMM22 },
1269
  { X86::XMM23 },
1270
  { X86::XMM24 },
1271
  { X86::XMM25 },
1272
  { X86::XMM26 },
1273
  { X86::XMM27 },
1274
  { X86::XMM28 },
1275
  { X86::XMM29 },
1276
  { X86::XMM30 },
1277
  { X86::XMM31 },
1278
};
1279
1280
namespace {     // Register classes...
1281
  // GR8 Register Class...
1282
  const MCPhysReg GR8[] = {
1283
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 
1284
  };
1285
1286
  // GR8 Bit set.
1287
  const uint8_t GR8Bits[] = {
1288
    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1289
  };
1290
1291
  // GRH8 Register Class...
1292
  const MCPhysReg GRH8[] = {
1293
    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 
1294
  };
1295
1296
  // GRH8 Bit set.
1297
  const uint8_t GRH8Bits[] = {
1298
    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1299
  };
1300
1301
  // GR8_NOREX Register Class...
1302
  const MCPhysReg GR8_NOREX[] = {
1303
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
1304
  };
1305
1306
  // GR8_NOREX Bit set.
1307
  const uint8_t GR8_NOREXBits[] = {
1308
    0x36, 0x8c, 0x08, 
1309
  };
1310
1311
  // GR8_ABCD_H Register Class...
1312
  const MCPhysReg GR8_ABCD_H[] = {
1313
    X86::AH, X86::CH, X86::DH, X86::BH, 
1314
  };
1315
1316
  // GR8_ABCD_H Bit set.
1317
  const uint8_t GR8_ABCD_HBits[] = {
1318
    0x12, 0x84, 
1319
  };
1320
1321
  // GR8_ABCD_L Register Class...
1322
  const MCPhysReg GR8_ABCD_L[] = {
1323
    X86::AL, X86::CL, X86::DL, X86::BL, 
1324
  };
1325
1326
  // GR8_ABCD_L Bit set.
1327
  const uint8_t GR8_ABCD_LBits[] = {
1328
    0x24, 0x08, 0x08, 
1329
  };
1330
1331
  // GRH16 Register Class...
1332
  const MCPhysReg GRH16[] = {
1333
    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 
1334
  };
1335
1336
  // GRH16 Bit set.
1337
  const uint8_t GRH16Bits[] = {
1338
    0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1339
  };
1340
1341
  // GR16 Register Class...
1342
  const MCPhysReg GR16[] = {
1343
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 
1344
  };
1345
1346
  // GR16 Bit set.
1347
  const uint8_t GR16Bits[] = {
1348
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1349
  };
1350
1351
  // GR16_NOREX Register Class...
1352
  const MCPhysReg GR16_NOREX[] = {
1353
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
1354
  };
1355
1356
  // GR16_NOREX Bit set.
1357
  const uint8_t GR16_NOREXBits[] = {
1358
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 
1359
  };
1360
1361
  // VK1 Register Class...
1362
  const MCPhysReg VK1[] = {
1363
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1364
  };
1365
1366
  // VK1 Bit set.
1367
  const uint8_t VK1Bits[] = {
1368
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1369
  };
1370
1371
  // VK16 Register Class...
1372
  const MCPhysReg VK16[] = {
1373
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1374
  };
1375
1376
  // VK16 Bit set.
1377
  const uint8_t VK16Bits[] = {
1378
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1379
  };
1380
1381
  // VK2 Register Class...
1382
  const MCPhysReg VK2[] = {
1383
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1384
  };
1385
1386
  // VK2 Bit set.
1387
  const uint8_t VK2Bits[] = {
1388
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1389
  };
1390
1391
  // VK4 Register Class...
1392
  const MCPhysReg VK4[] = {
1393
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1394
  };
1395
1396
  // VK4 Bit set.
1397
  const uint8_t VK4Bits[] = {
1398
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1399
  };
1400
1401
  // VK8 Register Class...
1402
  const MCPhysReg VK8[] = {
1403
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1404
  };
1405
1406
  // VK8 Bit set.
1407
  const uint8_t VK8Bits[] = {
1408
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1409
  };
1410
1411
  // VK16WM Register Class...
1412
  const MCPhysReg VK16WM[] = {
1413
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1414
  };
1415
1416
  // VK16WM Bit set.
1417
  const uint8_t VK16WMBits[] = {
1418
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1419
  };
1420
1421
  // VK1WM Register Class...
1422
  const MCPhysReg VK1WM[] = {
1423
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1424
  };
1425
1426
  // VK1WM Bit set.
1427
  const uint8_t VK1WMBits[] = {
1428
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1429
  };
1430
1431
  // VK2WM Register Class...
1432
  const MCPhysReg VK2WM[] = {
1433
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1434
  };
1435
1436
  // VK2WM Bit set.
1437
  const uint8_t VK2WMBits[] = {
1438
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1439
  };
1440
1441
  // VK4WM Register Class...
1442
  const MCPhysReg VK4WM[] = {
1443
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1444
  };
1445
1446
  // VK4WM Bit set.
1447
  const uint8_t VK4WMBits[] = {
1448
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1449
  };
1450
1451
  // VK8WM Register Class...
1452
  const MCPhysReg VK8WM[] = {
1453
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1454
  };
1455
1456
  // VK8WM Bit set.
1457
  const uint8_t VK8WMBits[] = {
1458
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1459
  };
1460
1461
  // SEGMENT_REG Register Class...
1462
  const MCPhysReg SEGMENT_REG[] = {
1463
    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 
1464
  };
1465
1466
  // SEGMENT_REG Bit set.
1467
  const uint8_t SEGMENT_REGBits[] = {
1468
    0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80, 
1469
  };
1470
1471
  // GR16_ABCD Register Class...
1472
  const MCPhysReg GR16_ABCD[] = {
1473
    X86::AX, X86::CX, X86::DX, X86::BX, 
1474
  };
1475
1476
  // GR16_ABCD Bit set.
1477
  const uint8_t GR16_ABCDBits[] = {
1478
    0x08, 0x22, 0x20, 
1479
  };
1480
1481
  // FPCCR Register Class...
1482
  const MCPhysReg FPCCR[] = {
1483
    X86::FPSW, 
1484
  };
1485
1486
  // FPCCR Bit set.
1487
  const uint8_t FPCCRBits[] = {
1488
    0x00, 0x00, 0x00, 0x00, 0x04, 
1489
  };
1490
1491
  // FR32X Register Class...
1492
  const MCPhysReg FR32X[] = {
1493
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1494
  };
1495
1496
  // FR32X Bit set.
1497
  const uint8_t FR32XBits[] = {
1498
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1499
  };
1500
1501
  // LOW32_ADDR_ACCESS_RBP Register Class...
1502
  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1503
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 
1504
  };
1505
1506
  // LOW32_ADDR_ACCESS_RBP Bit set.
1507
  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1508
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1509
  };
1510
1511
  // LOW32_ADDR_ACCESS Register Class...
1512
  const MCPhysReg LOW32_ADDR_ACCESS[] = {
1513
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 
1514
  };
1515
1516
  // LOW32_ADDR_ACCESS Bit set.
1517
  const uint8_t LOW32_ADDR_ACCESSBits[] = {
1518
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1519
  };
1520
1521
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1522
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1523
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 
1524
  };
1525
1526
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1527
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1528
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1529
  };
1530
1531
  // DEBUG_REG Register Class...
1532
  const MCPhysReg DEBUG_REG[] = {
1533
    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 
1534
  };
1535
1536
  // DEBUG_REG Bit set.
1537
  const uint8_t DEBUG_REGBits[] = {
1538
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1539
  };
1540
1541
  // FR32 Register Class...
1542
  const MCPhysReg FR32[] = {
1543
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1544
  };
1545
1546
  // FR32 Bit set.
1547
  const uint8_t FR32Bits[] = {
1548
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1549
  };
1550
1551
  // GR32 Register Class...
1552
  const MCPhysReg GR32[] = {
1553
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1554
  };
1555
1556
  // GR32 Bit set.
1557
  const uint8_t GR32Bits[] = {
1558
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1559
  };
1560
1561
  // GR32_NOSP Register Class...
1562
  const MCPhysReg GR32_NOSP[] = {
1563
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1564
  };
1565
1566
  // GR32_NOSP Bit set.
1567
  const uint8_t GR32_NOSPBits[] = {
1568
    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1569
  };
1570
1571
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1572
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1573
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 
1574
  };
1575
1576
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1577
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1578
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 
1579
  };
1580
1581
  // GR32_NOREX Register Class...
1582
  const MCPhysReg GR32_NOREX[] = {
1583
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
1584
  };
1585
1586
  // GR32_NOREX Bit set.
1587
  const uint8_t GR32_NOREXBits[] = {
1588
    0x00, 0x00, 0xc0, 0x0f, 0x03, 
1589
  };
1590
1591
  // VK32 Register Class...
1592
  const MCPhysReg VK32[] = {
1593
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1594
  };
1595
1596
  // VK32 Bit set.
1597
  const uint8_t VK32Bits[] = {
1598
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1599
  };
1600
1601
  // GR32_NOREX_NOSP Register Class...
1602
  const MCPhysReg GR32_NOREX_NOSP[] = {
1603
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 
1604
  };
1605
1606
  // GR32_NOREX_NOSP Bit set.
1607
  const uint8_t GR32_NOREX_NOSPBits[] = {
1608
    0x00, 0x00, 0xc0, 0x0f, 0x01, 
1609
  };
1610
1611
  // RFP32 Register Class...
1612
  const MCPhysReg RFP32[] = {
1613
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1614
  };
1615
1616
  // RFP32 Bit set.
1617
  const uint8_t RFP32Bits[] = {
1618
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1619
  };
1620
1621
  // VK32WM Register Class...
1622
  const MCPhysReg VK32WM[] = {
1623
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1624
  };
1625
1626
  // VK32WM Bit set.
1627
  const uint8_t VK32WMBits[] = {
1628
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1629
  };
1630
1631
  // GR32_ABCD Register Class...
1632
  const MCPhysReg GR32_ABCD[] = {
1633
    X86::EAX, X86::ECX, X86::EDX, X86::EBX, 
1634
  };
1635
1636
  // GR32_ABCD Bit set.
1637
  const uint8_t GR32_ABCDBits[] = {
1638
    0x00, 0x00, 0x40, 0x0b, 
1639
  };
1640
1641
  // GR32_TC Register Class...
1642
  const MCPhysReg GR32_TC[] = {
1643
    X86::EAX, X86::ECX, X86::EDX, X86::ESP, 
1644
  };
1645
1646
  // GR32_TC Bit set.
1647
  const uint8_t GR32_TCBits[] = {
1648
    0x00, 0x00, 0x40, 0x0a, 0x02, 
1649
  };
1650
1651
  // GR32_ABCD_and_GR32_TC Register Class...
1652
  const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1653
    X86::EAX, X86::ECX, X86::EDX, 
1654
  };
1655
1656
  // GR32_ABCD_and_GR32_TC Bit set.
1657
  const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
1658
    0x00, 0x00, 0x40, 0x0a, 
1659
  };
1660
1661
  // GR32_AD Register Class...
1662
  const MCPhysReg GR32_AD[] = {
1663
    X86::EAX, X86::EDX, 
1664
  };
1665
1666
  // GR32_AD Bit set.
1667
  const uint8_t GR32_ADBits[] = {
1668
    0x00, 0x00, 0x40, 0x08, 
1669
  };
1670
1671
  // GR32_BPSP Register Class...
1672
  const MCPhysReg GR32_BPSP[] = {
1673
    X86::EBP, X86::ESP, 
1674
  };
1675
1676
  // GR32_BPSP Bit set.
1677
  const uint8_t GR32_BPSPBits[] = {
1678
    0x00, 0x00, 0x80, 0x00, 0x02, 
1679
  };
1680
1681
  // GR32_BSI Register Class...
1682
  const MCPhysReg GR32_BSI[] = {
1683
    X86::EBX, X86::ESI, 
1684
  };
1685
1686
  // GR32_BSI Bit set.
1687
  const uint8_t GR32_BSIBits[] = {
1688
    0x00, 0x00, 0x00, 0x01, 0x01, 
1689
  };
1690
1691
  // GR32_CB Register Class...
1692
  const MCPhysReg GR32_CB[] = {
1693
    X86::ECX, X86::EBX, 
1694
  };
1695
1696
  // GR32_CB Bit set.
1697
  const uint8_t GR32_CBBits[] = {
1698
    0x00, 0x00, 0x00, 0x03, 
1699
  };
1700
1701
  // GR32_DC Register Class...
1702
  const MCPhysReg GR32_DC[] = {
1703
    X86::EDX, X86::ECX, 
1704
  };
1705
1706
  // GR32_DC Bit set.
1707
  const uint8_t GR32_DCBits[] = {
1708
    0x00, 0x00, 0x00, 0x0a, 
1709
  };
1710
1711
  // GR32_DIBP Register Class...
1712
  const MCPhysReg GR32_DIBP[] = {
1713
    X86::EDI, X86::EBP, 
1714
  };
1715
1716
  // GR32_DIBP Bit set.
1717
  const uint8_t GR32_DIBPBits[] = {
1718
    0x00, 0x00, 0x80, 0x04, 
1719
  };
1720
1721
  // GR32_SIDI Register Class...
1722
  const MCPhysReg GR32_SIDI[] = {
1723
    X86::ESI, X86::EDI, 
1724
  };
1725
1726
  // GR32_SIDI Bit set.
1727
  const uint8_t GR32_SIDIBits[] = {
1728
    0x00, 0x00, 0x00, 0x04, 0x01, 
1729
  };
1730
1731
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1732
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1733
    X86::RIP, X86::RBP, 
1734
  };
1735
1736
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1737
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1738
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
1739
  };
1740
1741
  // CCR Register Class...
1742
  const MCPhysReg CCR[] = {
1743
    X86::EFLAGS, 
1744
  };
1745
1746
  // CCR Bit set.
1747
  const uint8_t CCRBits[] = {
1748
    0x00, 0x00, 0x00, 0x10, 
1749
  };
1750
1751
  // DFCCR Register Class...
1752
  const MCPhysReg DFCCR[] = {
1753
    X86::DF, 
1754
  };
1755
1756
  // DFCCR Bit set.
1757
  const uint8_t DFCCRBits[] = {
1758
    0x00, 0x40, 
1759
  };
1760
1761
  // GR32_ABCD_and_GR32_BSI Register Class...
1762
  const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1763
    X86::EBX, 
1764
  };
1765
1766
  // GR32_ABCD_and_GR32_BSI Bit set.
1767
  const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1768
    0x00, 0x00, 0x00, 0x01, 
1769
  };
1770
1771
  // GR32_AD_and_GR32_DC Register Class...
1772
  const MCPhysReg GR32_AD_and_GR32_DC[] = {
1773
    X86::EDX, 
1774
  };
1775
1776
  // GR32_AD_and_GR32_DC Bit set.
1777
  const uint8_t GR32_AD_and_GR32_DCBits[] = {
1778
    0x00, 0x00, 0x00, 0x08, 
1779
  };
1780
1781
  // GR32_BPSP_and_GR32_DIBP Register Class...
1782
  const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1783
    X86::EBP, 
1784
  };
1785
1786
  // GR32_BPSP_and_GR32_DIBP Bit set.
1787
  const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1788
    0x00, 0x00, 0x80, 
1789
  };
1790
1791
  // GR32_BPSP_and_GR32_TC Register Class...
1792
  const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1793
    X86::ESP, 
1794
  };
1795
1796
  // GR32_BPSP_and_GR32_TC Bit set.
1797
  const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
1798
    0x00, 0x00, 0x00, 0x00, 0x02, 
1799
  };
1800
1801
  // GR32_BSI_and_GR32_SIDI Register Class...
1802
  const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1803
    X86::ESI, 
1804
  };
1805
1806
  // GR32_BSI_and_GR32_SIDI Bit set.
1807
  const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
1808
    0x00, 0x00, 0x00, 0x00, 0x01, 
1809
  };
1810
1811
  // GR32_CB_and_GR32_DC Register Class...
1812
  const MCPhysReg GR32_CB_and_GR32_DC[] = {
1813
    X86::ECX, 
1814
  };
1815
1816
  // GR32_CB_and_GR32_DC Bit set.
1817
  const uint8_t GR32_CB_and_GR32_DCBits[] = {
1818
    0x00, 0x00, 0x00, 0x02, 
1819
  };
1820
1821
  // GR32_DIBP_and_GR32_SIDI Register Class...
1822
  const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1823
    X86::EDI, 
1824
  };
1825
1826
  // GR32_DIBP_and_GR32_SIDI Bit set.
1827
  const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
1828
    0x00, 0x00, 0x00, 0x04, 
1829
  };
1830
1831
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1832
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1833
    X86::RBP, 
1834
  };
1835
1836
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1837
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1838
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1839
  };
1840
1841
  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1842
  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1843
    X86::RIP, 
1844
  };
1845
1846
  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1847
  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1848
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
1849
  };
1850
1851
  // RFP64 Register Class...
1852
  const MCPhysReg RFP64[] = {
1853
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1854
  };
1855
1856
  // RFP64 Bit set.
1857
  const uint8_t RFP64Bits[] = {
1858
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1859
  };
1860
1861
  // FR64X Register Class...
1862
  const MCPhysReg FR64X[] = {
1863
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1864
  };
1865
1866
  // FR64X Bit set.
1867
  const uint8_t FR64XBits[] = {
1868
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1869
  };
1870
1871
  // GR64 Register Class...
1872
  const MCPhysReg GR64[] = {
1873
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 
1874
  };
1875
1876
  // GR64 Bit set.
1877
  const uint8_t GR64Bits[] = {
1878
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1879
  };
1880
1881
  // CONTROL_REG Register Class...
1882
  const MCPhysReg CONTROL_REG[] = {
1883
    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 
1884
  };
1885
1886
  // CONTROL_REG Bit set.
1887
  const uint8_t CONTROL_REGBits[] = {
1888
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1889
  };
1890
1891
  // FR64 Register Class...
1892
  const MCPhysReg FR64[] = {
1893
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1894
  };
1895
1896
  // FR64 Bit set.
1897
  const uint8_t FR64Bits[] = {
1898
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1899
  };
1900
1901
  // GR64_with_sub_8bit Register Class...
1902
  const MCPhysReg GR64_with_sub_8bit[] = {
1903
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 
1904
  };
1905
1906
  // GR64_with_sub_8bit Bit set.
1907
  const uint8_t GR64_with_sub_8bitBits[] = {
1908
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1909
  };
1910
1911
  // GR64_NOSP Register Class...
1912
  const MCPhysReg GR64_NOSP[] = {
1913
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 
1914
  };
1915
1916
  // GR64_NOSP Bit set.
1917
  const uint8_t GR64_NOSPBits[] = {
1918
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1919
  };
1920
1921
  // GR64_TC Register Class...
1922
  const MCPhysReg GR64_TC[] = {
1923
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
1924
  };
1925
1926
  // GR64_TC Bit set.
1927
  const uint8_t GR64_TCBits[] = {
1928
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1929
  };
1930
1931
  // GR64_NOREX Register Class...
1932
  const MCPhysReg GR64_NOREX[] = {
1933
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 
1934
  };
1935
1936
  // GR64_NOREX Bit set.
1937
  const uint8_t GR64_NOREXBits[] = {
1938
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 
1939
  };
1940
1941
  // GR64_TCW64 Register Class...
1942
  const MCPhysReg GR64_TCW64[] = {
1943
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP, 
1944
  };
1945
1946
  // GR64_TCW64 Bit set.
1947
  const uint8_t GR64_TCW64Bits[] = {
1948
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1949
  };
1950
1951
  // GR64_TC_with_sub_8bit Register Class...
1952
  const MCPhysReg GR64_TC_with_sub_8bit[] = {
1953
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP, 
1954
  };
1955
1956
  // GR64_TC_with_sub_8bit Bit set.
1957
  const uint8_t GR64_TC_with_sub_8bitBits[] = {
1958
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1959
  };
1960
1961
  // GR64_NOSP_and_GR64_TC Register Class...
1962
  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
1963
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 
1964
  };
1965
1966
  // GR64_NOSP_and_GR64_TC Bit set.
1967
  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
1968
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1969
  };
1970
1971
  // GR64_TCW64_with_sub_8bit Register Class...
1972
  const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
1973
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP, 
1974
  };
1975
1976
  // GR64_TCW64_with_sub_8bit Bit set.
1977
  const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
1978
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1979
  };
1980
1981
  // GR64_TC_and_GR64_TCW64 Register Class...
1982
  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1983
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
1984
  };
1985
1986
  // GR64_TC_and_GR64_TCW64 Bit set.
1987
  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1988
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1989
  };
1990
1991
  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1992
  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1993
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 
1994
  };
1995
1996
  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1997
  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1998
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 
1999
  };
2000
2001
  // VK64 Register Class...
2002
  const MCPhysReg VK64[] = {
2003
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
2004
  };
2005
2006
  // VK64 Bit set.
2007
  const uint8_t VK64Bits[] = {
2008
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2009
  };
2010
2011
  // VR64 Register Class...
2012
  const MCPhysReg VR64[] = {
2013
    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
2014
  };
2015
2016
  // VR64 Bit set.
2017
  const uint8_t VR64Bits[] = {
2018
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2019
  };
2020
2021
  // GR64_NOREX_NOSP Register Class...
2022
  const MCPhysReg GR64_NOREX_NOSP[] = {
2023
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 
2024
  };
2025
2026
  // GR64_NOREX_NOSP Bit set.
2027
  const uint8_t GR64_NOREX_NOSPBits[] = {
2028
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 
2029
  };
2030
2031
  // GR64_NOREX_and_GR64_TC Register Class...
2032
  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2033
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP, 
2034
  };
2035
2036
  // GR64_NOREX_and_GR64_TC Bit set.
2037
  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2038
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x01, 
2039
  };
2040
2041
  // GR64_NOSP_and_GR64_TCW64 Register Class...
2042
  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
2043
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 
2044
  };
2045
2046
  // GR64_NOSP_and_GR64_TCW64 Bit set.
2047
  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
2048
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
2049
  };
2050
2051
  // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2052
  const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2053
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP, 
2054
  };
2055
2056
  // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2057
  const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2058
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
2059
  };
2060
2061
  // VK64WM Register Class...
2062
  const MCPhysReg VK64WM[] = {
2063
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
2064
  };
2065
2066
  // VK64WM Bit set.
2067
  const uint8_t VK64WMBits[] = {
2068
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
2069
  };
2070
2071
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
2072
  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
2073
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 
2074
  };
2075
2076
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
2077
  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
2078
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
2079
  };
2080
2081
  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2082
  const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2083
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, 
2084
  };
2085
2086
  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2087
  const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2088
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x01, 
2089
  };
2090
2091
  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
2092
  const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
2093
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 
2094
  };
2095
2096
  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
2097
  const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
2098
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 
2099
  };
2100
2101
  // GR64_NOREX_and_GR64_TCW64 Register Class...
2102
  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2103
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP, 
2104
  };
2105
2106
  // GR64_NOREX_and_GR64_TCW64 Bit set.
2107
  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2108
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x01, 
2109
  };
2110
2111
  // GR64_ABCD Register Class...
2112
  const MCPhysReg GR64_ABCD[] = {
2113
    X86::RAX, X86::RCX, X86::RDX, X86::RBX, 
2114
  };
2115
2116
  // GR64_ABCD Bit set.
2117
  const uint8_t GR64_ABCDBits[] = {
2118
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, 
2119
  };
2120
2121
  // GR64_with_sub_32bit_in_GR32_TC Register Class...
2122
  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2123
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, 
2124
  };
2125
2126
  // GR64_with_sub_32bit_in_GR32_TC Bit set.
2127
  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2128
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x01, 
2129
  };
2130
2131
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2132
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2133
    X86::RAX, X86::RCX, X86::RDX, 
2134
  };
2135
2136
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2137
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2138
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 
2139
  };
2140
2141
  // GR64_AD Register Class...
2142
  const MCPhysReg GR64_AD[] = {
2143
    X86::RAX, X86::RDX, 
2144
  };
2145
2146
  // GR64_AD Bit set.
2147
  const uint8_t GR64_ADBits[] = {
2148
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10, 
2149
  };
2150
2151
  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2152
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2153
    X86::RBP, X86::RIP, 
2154
  };
2155
2156
  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2157
  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2158
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
2159
  };
2160
2161
  // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2162
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2163
    X86::RBP, X86::RSP, 
2164
  };
2165
2166
  // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2167
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2168
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 
2169
  };
2170
2171
  // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2172
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2173
    X86::RSI, X86::RBX, 
2174
  };
2175
2176
  // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2177
  const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2178
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 
2179
  };
2180
2181
  // GR64_with_sub_32bit_in_GR32_CB Register Class...
2182
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2183
    X86::RCX, X86::RBX, 
2184
  };
2185
2186
  // GR64_with_sub_32bit_in_GR32_CB Bit set.
2187
  const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2188
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
2189
  };
2190
2191
  // GR64_with_sub_32bit_in_GR32_DC Register Class...
2192
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
2193
    X86::RCX, X86::RDX, 
2194
  };
2195
2196
  // GR64_with_sub_32bit_in_GR32_DC Bit set.
2197
  const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
2198
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
2199
  };
2200
2201
  // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2202
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2203
    X86::RDI, X86::RBP, 
2204
  };
2205
2206
  // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2207
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2208
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 
2209
  };
2210
2211
  // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2212
  const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2213
    X86::RSI, X86::RDI, 
2214
  };
2215
2216
  // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2217
  const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2218
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 
2219
  };
2220
2221
  // GR64_and_LOW32_ADDR_ACCESS Register Class...
2222
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2223
    X86::RIP, 
2224
  };
2225
2226
  // GR64_and_LOW32_ADDR_ACCESS Bit set.
2227
  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2228
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2229
  };
2230
2231
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2232
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2233
    X86::RBX, 
2234
  };
2235
2236
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2237
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2238
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
2239
  };
2240
2241
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
2242
  const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
2243
    X86::RDX, 
2244
  };
2245
2246
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
2247
  const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
2248
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2249
  };
2250
2251
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2252
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2253
    X86::RBP, 
2254
  };
2255
2256
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2257
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2258
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
2259
  };
2260
2261
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2262
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2263
    X86::RSP, 
2264
  };
2265
2266
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2267
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2268
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
2269
  };
2270
2271
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2272
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2273
    X86::RSI, 
2274
  };
2275
2276
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2277
  const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2278
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
2279
  };
2280
2281
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
2282
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
2283
    X86::RCX, 
2284
  };
2285
2286
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
2287
  const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
2288
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
2289
  };
2290
2291
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2292
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2293
    X86::RDI, 
2294
  };
2295
2296
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2297
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2298
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
2299
  };
2300
2301
  // RST Register Class...
2302
  const MCPhysReg RST[] = {
2303
    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
2304
  };
2305
2306
  // RST Bit set.
2307
  const uint8_t RSTBits[] = {
2308
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2309
  };
2310
2311
  // RFP80 Register Class...
2312
  const MCPhysReg RFP80[] = {
2313
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
2314
  };
2315
2316
  // RFP80 Bit set.
2317
  const uint8_t RFP80Bits[] = {
2318
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2319
  };
2320
2321
  // VR128X Register Class...
2322
  const MCPhysReg VR128X[] = {
2323
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
2324
  };
2325
2326
  // VR128X Bit set.
2327
  const uint8_t VR128XBits[] = {
2328
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2329
  };
2330
2331
  // VR128 Register Class...
2332
  const MCPhysReg VR128[] = {
2333
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2334
  };
2335
2336
  // VR128 Bit set.
2337
  const uint8_t VR128Bits[] = {
2338
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2339
  };
2340
2341
  // VR128H Register Class...
2342
  const MCPhysReg VR128H[] = {
2343
    X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2344
  };
2345
2346
  // VR128H Bit set.
2347
  const uint8_t VR128HBits[] = {
2348
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2349
  };
2350
2351
  // VR128L Register Class...
2352
  const MCPhysReg VR128L[] = {
2353
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
2354
  };
2355
2356
  // VR128L Bit set.
2357
  const uint8_t VR128LBits[] = {
2358
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2359
  };
2360
2361
  // BNDR Register Class...
2362
  const MCPhysReg BNDR[] = {
2363
    X86::BND0, X86::BND1, X86::BND2, X86::BND3, 
2364
  };
2365
2366
  // BNDR Bit set.
2367
  const uint8_t BNDRBits[] = {
2368
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
2369
  };
2370
2371
  // VR256X Register Class...
2372
  const MCPhysReg VR256X[] = {
2373
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 
2374
  };
2375
2376
  // VR256X Bit set.
2377
  const uint8_t VR256XBits[] = {
2378
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2379
  };
2380
2381
  // VR256 Register Class...
2382
  const MCPhysReg VR256[] = {
2383
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2384
  };
2385
2386
  // VR256 Bit set.
2387
  const uint8_t VR256Bits[] = {
2388
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2389
  };
2390
2391
  // VR256H Register Class...
2392
  const MCPhysReg VR256H[] = {
2393
    X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2394
  };
2395
2396
  // VR256H Bit set.
2397
  const uint8_t VR256HBits[] = {
2398
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2399
  };
2400
2401
  // VR256L Register Class...
2402
  const MCPhysReg VR256L[] = {
2403
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 
2404
  };
2405
2406
  // VR256L Bit set.
2407
  const uint8_t VR256LBits[] = {
2408
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2409
  };
2410
2411
  // VR512 Register Class...
2412
  const MCPhysReg VR512[] = {
2413
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 
2414
  };
2415
2416
  // VR512 Bit set.
2417
  const uint8_t VR512Bits[] = {
2418
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2419
  };
2420
2421
  // VR512_with_sub_xmm_in_FR32 Register Class...
2422
  const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
2423
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2424
  };
2425
2426
  // VR512_with_sub_xmm_in_FR32 Bit set.
2427
  const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
2428
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2429
  };
2430
2431
  // VR512_with_sub_xmm_in_VR128H Register Class...
2432
  const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = {
2433
    X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2434
  };
2435
2436
  // VR512_with_sub_xmm_in_VR128H Bit set.
2437
  const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = {
2438
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2439
  };
2440
2441
  // VR512_with_sub_xmm_in_VR128L Register Class...
2442
  const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = {
2443
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, 
2444
  };
2445
2446
  // VR512_with_sub_xmm_in_VR128L Bit set.
2447
  const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = {
2448
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2449
  };
2450
2451
} // end anonymous namespace
2452
2453
extern const char X86RegClassStrings[] = {
2454
  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
2455
  /* 6 */ 'V', 'K', '1', 0,
2456
  /* 10 */ 'V', 'R', '5', '1', '2', 0,
2457
  /* 16 */ 'V', 'K', '3', '2', 0,
2458
  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
2459
  /* 27 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'F', 'R', '3', '2', 0,
2460
  /* 54 */ 'G', 'R', '3', '2', 0,
2461
  /* 59 */ 'V', 'K', '2', 0,
2462
  /* 63 */ 'V', 'K', '6', '4', 0,
2463
  /* 68 */ 'R', 'F', 'P', '6', '4', 0,
2464
  /* 74 */ 'F', 'R', '6', '4', 0,
2465
  /* 79 */ 'G', 'R', '6', '4', 0,
2466
  /* 84 */ 'V', 'R', '6', '4', 0,
2467
  /* 89 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2468
  /* 112 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2469
  /* 149 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2470
  /* 175 */ 'V', 'K', '4', 0,
2471
  /* 179 */ 'G', 'R', 'H', '1', '6', 0,
2472
  /* 185 */ 'V', 'K', '1', '6', 0,
2473
  /* 190 */ 'G', 'R', '1', '6', 0,
2474
  /* 195 */ 'V', 'R', '2', '5', '6', 0,
2475
  /* 201 */ 'V', 'R', '1', '2', '8', 0,
2476
  /* 207 */ 'G', 'R', 'H', '8', 0,
2477
  /* 212 */ 'V', 'K', '8', 0,
2478
  /* 216 */ 'G', 'R', '8', 0,
2479
  /* 220 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
2480
  /* 251 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2481
  /* 294 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2482
  /* 337 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2483
  /* 368 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2484
  /* 413 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2485
  /* 458 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2486
  /* 489 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2487
  /* 511 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2488
  /* 539 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2489
  /* 562 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
2490
  /* 570 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
2491
  /* 578 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
2492
  /* 588 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
2493
  /* 598 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
2494
  /* 608 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
2495
  /* 618 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
2496
  /* 630 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
2497
  /* 642 */ 'V', 'R', '2', '5', '6', 'H', 0,
2498
  /* 649 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'H', 0,
2499
  /* 678 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
2500
  /* 689 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2501
  /* 735 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2502
  /* 782 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2503
  /* 815 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2504
  /* 861 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2505
  /* 893 */ 'V', 'R', '2', '5', '6', 'L', 0,
2506
  /* 900 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'L', 0,
2507
  /* 929 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
2508
  /* 940 */ 'V', 'K', '1', 'W', 'M', 0,
2509
  /* 946 */ 'V', 'K', '3', '2', 'W', 'M', 0,
2510
  /* 953 */ 'V', 'K', '2', 'W', 'M', 0,
2511
  /* 959 */ 'V', 'K', '6', '4', 'W', 'M', 0,
2512
  /* 966 */ 'V', 'K', '4', 'W', 'M', 0,
2513
  /* 972 */ 'V', 'K', '1', '6', 'W', 'M', 0,
2514
  /* 979 */ 'V', 'K', '8', 'W', 'M', 0,
2515
  /* 985 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2516
  /* 1032 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2517
  /* 1065 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2518
  /* 1096 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
2519
  /* 1106 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
2520
  /* 1116 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2521
  /* 1132 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2522
  /* 1148 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
2523
  /* 1181 */ 'D', 'F', 'C', 'C', 'R', 0,
2524
  /* 1187 */ 'F', 'P', 'C', 'C', 'R', 0,
2525
  /* 1193 */ 'B', 'N', 'D', 'R', 0,
2526
  /* 1198 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
2527
  /* 1225 */ 'R', 'S', 'T', 0,
2528
  /* 1229 */ 'F', 'R', '3', '2', 'X', 0,
2529
  /* 1235 */ 'F', 'R', '6', '4', 'X', 0,
2530
  /* 1241 */ 'V', 'R', '2', '5', '6', 'X', 0,
2531
  /* 1248 */ 'V', 'R', '1', '2', '8', 'X', 0,
2532
  /* 1255 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
2533
  /* 1266 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
2534
  /* 1277 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2535
  /* 1323 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2536
  /* 1374 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
2537
  /* 1384 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2538
  /* 1421 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2539
  /* 1454 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2540
  /* 1505 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2541
  /* 1524 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2542
  /* 1549 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2543
  /* 1586 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2544
};
2545
2546
extern const MCRegisterClass X86MCRegisterClasses[] = {
2547
  { GR8, GR8Bits, 216, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true },
2548
  { GRH8, GRH8Bits, 207, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, false },
2549
  { GR8_NOREX, GR8_NOREXBits, 1374, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, true },
2550
  { GR8_ABCD_H, GR8_ABCD_HBits, 678, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, true },
2551
  { GR8_ABCD_L, GR8_ABCD_LBits, 929, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, true },
2552
  { GRH16, GRH16Bits, 179, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 1, false },
2553
  { GR16, GR16Bits, 190, 16, sizeof(GR16Bits), X86::GR16RegClassID, 1, true },
2554
  { GR16_NOREX, GR16_NOREXBits, 1312, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 1, true },
2555
  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 1, true },
2556
  { VK16, VK16Bits, 185, 8, sizeof(VK16Bits), X86::VK16RegClassID, 1, true },
2557
  { VK2, VK2Bits, 59, 8, sizeof(VK2Bits), X86::VK2RegClassID, 1, true },
2558
  { VK4, VK4Bits, 175, 8, sizeof(VK4Bits), X86::VK4RegClassID, 1, true },
2559
  { VK8, VK8Bits, 212, 8, sizeof(VK8Bits), X86::VK8RegClassID, 1, true },
2560
  { VK16WM, VK16WMBits, 972, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 1, true },
2561
  { VK1WM, VK1WMBits, 940, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 1, true },
2562
  { VK2WM, VK2WMBits, 953, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 1, true },
2563
  { VK4WM, VK4WMBits, 966, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 1, true },
2564
  { VK8WM, VK8WMBits, 979, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 1, true },
2565
  { SEGMENT_REG, SEGMENT_REGBits, 630, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 1, true },
2566
  { GR16_ABCD, GR16_ABCDBits, 598, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 1, true },
2567
  { FPCCR, FPCCRBits, 1187, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, -1, false },
2568
  { FR32X, FR32XBits, 1229, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 1, true },
2569
  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1074, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2570
  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1207, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 1, true },
2571
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1586, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 1, true },
2572
  { DEBUG_REG, DEBUG_REGBits, 608, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 1, true },
2573
  { FR32, FR32Bits, 49, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true },
2574
  { GR32, GR32Bits, 54, 16, sizeof(GR32Bits), X86::GR32RegClassID, 1, true },
2575
  { GR32_NOSP, GR32_NOSPBits, 1096, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 1, true },
2576
  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1323, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2577
  { GR32_NOREX, GR32_NOREXBits, 1255, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 1, true },
2578
  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 1, true },
2579
  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1116, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 1, true },
2580
  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 1, true },
2581
  { VK32WM, VK32WMBits, 946, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 1, true },
2582
  { GR32_ABCD, GR32_ABCDBits, 578, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 1, true },
2583
  { GR32_TC, GR32_TCBits, 405, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 1, true },
2584
  { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 391, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 1, true },
2585
  { GR32_AD, GR32_ADBits, 562, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 1, true },
2586
  { GR32_BPSP, GR32_BPSPBits, 1171, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 1, true },
2587
  { GR32_BSI, GR32_BSIBits, 852, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 1, true },
2588
  { GR32_CB, GR32_CBBits, 243, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 1, true },
2589
  { GR32_DC, GR32_DCBits, 286, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 1, true },
2590
  { GR32_DIBP, GR32_DIBPBits, 1022, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 1, true },
2591
  { GR32_SIDI, GR32_SIDIBits, 725, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 1, true },
2592
  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1384, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 1, true },
2593
  { CCR, CCRBits, 1183, 1, sizeof(CCRBits), X86::CCRRegClassID, -1, false },
2594
  { DFCCR, DFCCRBits, 1181, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, -1, false },
2595
  { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 838, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2596
  { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 317, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 1, true },
2597
  { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1008, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2598
  { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 436, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 1, true },
2599
  { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 712, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2600
  { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 274, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 1, true },
2601
  { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 758, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2602
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1454, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 1, true },
2603
  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1421, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 1, true },
2604
  { RFP64, RFP64Bits, 68, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 1, true },
2605
  { FR64X, FR64XBits, 1235, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true },
2606
  { GR64, GR64Bits, 79, 17, sizeof(GR64Bits), X86::GR64RegClassID, 1, true },
2607
  { CONTROL_REG, CONTROL_REGBits, 618, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 1, true },
2608
  { FR64, FR64Bits, 74, 16, sizeof(FR64Bits), X86::FR64RegClassID, 1, true },
2609
  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1505, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 1, true },
2610
  { GR64_NOSP, GR64_NOSPBits, 1106, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 1, true },
2611
  { GR64_TC, GR64_TCBits, 503, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 1, true },
2612
  { GR64_NOREX, GR64_NOREXBits, 1266, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 1, true },
2613
  { GR64_TCW64, GR64_TCW64Bits, 101, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 1, true },
2614
  { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1564, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 1, true },
2615
  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 489, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 1, true },
2616
  { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1524, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 1, true },
2617
  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 89, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 1, true },
2618
  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1289, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2619
  { VK64, VK64Bits, 63, 8, sizeof(VK64Bits), X86::VK64RegClassID, 1, true },
2620
  { VR64, VR64Bits, 84, 8, sizeof(VR64Bits), X86::VR64RegClassID, 1, true },
2621
  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1132, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 1, true },
2622
  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 539, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 1, true },
2623
  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 124, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2624
  { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1549, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 1, true },
2625
  { VK64WM, VK64WMBits, 959, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 1, true },
2626
  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 112, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2627
  { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1277, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2628
  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 511, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 1, true },
2629
  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 149, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 1, true },
2630
  { GR64_ABCD, GR64_ABCDBits, 588, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 1, true },
2631
  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 458, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 1, true },
2632
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 368, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 1, true },
2633
  { GR64_AD, GR64_ADBits, 570, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 1, true },
2634
  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1065, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2635
  { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1148, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 1, true },
2636
  { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 861, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 1, true },
2637
  { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 220, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 1, true },
2638
  { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 337, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 1, true },
2639
  { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1032, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 1, true },
2640
  { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 782, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 1, true },
2641
  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1198, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 1, true },
2642
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 815, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2643
  { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 294, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 1, true },
2644
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 985, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2645
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 413, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 1, true },
2646
  { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 689, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2647
  { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 251, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 1, true },
2648
  { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 735, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2649
  { RST, RSTBits, 1225, 8, sizeof(RSTBits), X86::RSTRegClassID, 1, false },
2650
  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 1, true },
2651
  { VR128X, VR128XBits, 1248, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 1, true },
2652
  { VR128, VR128Bits, 201, 16, sizeof(VR128Bits), X86::VR128RegClassID, 1, true },
2653
  { VR128H, VR128HBits, 671, 8, sizeof(VR128HBits), X86::VR128HRegClassID, 1, true },
2654
  { VR128L, VR128LBits, 922, 8, sizeof(VR128LBits), X86::VR128LRegClassID, 1, true },
2655
  { BNDR, BNDRBits, 1193, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 1, true },
2656
  { VR256X, VR256XBits, 1241, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 1, true },
2657
  { VR256, VR256Bits, 195, 16, sizeof(VR256Bits), X86::VR256RegClassID, 1, true },
2658
  { VR256H, VR256HBits, 642, 8, sizeof(VR256HBits), X86::VR256HRegClassID, 1, true },
2659
  { VR256L, VR256LBits, 893, 8, sizeof(VR256LBits), X86::VR256LRegClassID, 1, true },
2660
  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 1, true },
2661
  { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, 27, 16, sizeof(VR512_with_sub_xmm_in_FR32Bits), X86::VR512_with_sub_xmm_in_FR32RegClassID, 1, true },
2662
  { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, 649, 8, sizeof(VR512_with_sub_xmm_in_VR128HBits), X86::VR512_with_sub_xmm_in_VR128HRegClassID, 1, true },
2663
  { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, 900, 8, sizeof(VR512_with_sub_xmm_in_VR128LBits), X86::VR512_with_sub_xmm_in_VR128LRegClassID, 1, true },
2664
};
2665
2666
// X86 Dwarf<->LLVM register mappings.
2667
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2668
  { 0U, X86::RAX },
2669
  { 1U, X86::RDX },
2670
  { 2U, X86::RCX },
2671
  { 3U, X86::RBX },
2672
  { 4U, X86::RSI },
2673
  { 5U, X86::RDI },
2674
  { 6U, X86::RBP },
2675
  { 7U, X86::RSP },
2676
  { 8U, X86::R8 },
2677
  { 9U, X86::R9 },
2678
  { 10U, X86::R10 },
2679
  { 11U, X86::R11 },
2680
  { 12U, X86::R12 },
2681
  { 13U, X86::R13 },
2682
  { 14U, X86::R14 },
2683
  { 15U, X86::R15 },
2684
  { 16U, X86::RIP },
2685
  { 17U, X86::XMM0 },
2686
  { 18U, X86::XMM1 },
2687
  { 19U, X86::XMM2 },
2688
  { 20U, X86::XMM3 },
2689
  { 21U, X86::XMM4 },
2690
  { 22U, X86::XMM5 },
2691
  { 23U, X86::XMM6 },
2692
  { 24U, X86::XMM7 },
2693
  { 25U, X86::XMM8 },
2694
  { 26U, X86::XMM9 },
2695
  { 27U, X86::XMM10 },
2696
  { 28U, X86::XMM11 },
2697
  { 29U, X86::XMM12 },
2698
  { 30U, X86::XMM13 },
2699
  { 31U, X86::XMM14 },
2700
  { 32U, X86::XMM15 },
2701
  { 33U, X86::ST0 },
2702
  { 34U, X86::ST1 },
2703
  { 35U, X86::ST2 },
2704
  { 36U, X86::ST3 },
2705
  { 37U, X86::ST4 },
2706
  { 38U, X86::ST5 },
2707
  { 39U, X86::ST6 },
2708
  { 40U, X86::ST7 },
2709
  { 41U, X86::MM0 },
2710
  { 42U, X86::MM1 },
2711
  { 43U, X86::MM2 },
2712
  { 44U, X86::MM3 },
2713
  { 45U, X86::MM4 },
2714
  { 46U, X86::MM5 },
2715
  { 47U, X86::MM6 },
2716
  { 48U, X86::MM7 },
2717
  { 67U, X86::XMM16 },
2718
  { 68U, X86::XMM17 },
2719
  { 69U, X86::XMM18 },
2720
  { 70U, X86::XMM19 },
2721
  { 71U, X86::XMM20 },
2722
  { 72U, X86::XMM21 },
2723
  { 73U, X86::XMM22 },
2724
  { 74U, X86::XMM23 },
2725
  { 75U, X86::XMM24 },
2726
  { 76U, X86::XMM25 },
2727
  { 77U, X86::XMM26 },
2728
  { 78U, X86::XMM27 },
2729
  { 79U, X86::XMM28 },
2730
  { 80U, X86::XMM29 },
2731
  { 81U, X86::XMM30 },
2732
  { 82U, X86::XMM31 },
2733
  { 118U, X86::K0 },
2734
  { 119U, X86::K1 },
2735
  { 120U, X86::K2 },
2736
  { 121U, X86::K3 },
2737
  { 122U, X86::K4 },
2738
  { 123U, X86::K5 },
2739
  { 124U, X86::K6 },
2740
  { 125U, X86::K7 },
2741
};
2742
extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L);
2743
2744
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2745
  { 0U, X86::EAX },
2746
  { 1U, X86::ECX },
2747
  { 2U, X86::EDX },
2748
  { 3U, X86::EBX },
2749
  { 4U, X86::EBP },
2750
  { 5U, X86::ESP },
2751
  { 6U, X86::ESI },
2752
  { 7U, X86::EDI },
2753
  { 8U, X86::EIP },
2754
  { 12U, X86::ST0 },
2755
  { 13U, X86::ST1 },
2756
  { 14U, X86::ST2 },
2757
  { 15U, X86::ST3 },
2758
  { 16U, X86::ST4 },
2759
  { 17U, X86::ST5 },
2760
  { 18U, X86::ST6 },
2761
  { 19U, X86::ST7 },
2762
  { 21U, X86::XMM0 },
2763
  { 22U, X86::XMM1 },
2764
  { 23U, X86::XMM2 },
2765
  { 24U, X86::XMM3 },
2766
  { 25U, X86::XMM4 },
2767
  { 26U, X86::XMM5 },
2768
  { 27U, X86::XMM6 },
2769
  { 28U, X86::XMM7 },
2770
  { 29U, X86::MM0 },
2771
  { 30U, X86::MM1 },
2772
  { 31U, X86::MM2 },
2773
  { 32U, X86::MM3 },
2774
  { 33U, X86::MM4 },
2775
  { 34U, X86::MM5 },
2776
  { 35U, X86::MM6 },
2777
  { 36U, X86::MM7 },
2778
  { 93U, X86::K0 },
2779
  { 94U, X86::K1 },
2780
  { 95U, X86::K2 },
2781
  { 96U, X86::K3 },
2782
  { 97U, X86::K4 },
2783
  { 98U, X86::K5 },
2784
  { 99U, X86::K6 },
2785
  { 100U, X86::K7 },
2786
};
2787
extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L);
2788
2789
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2790
  { 0U, X86::EAX },
2791
  { 1U, X86::ECX },
2792
  { 2U, X86::EDX },
2793
  { 3U, X86::EBX },
2794
  { 4U, X86::ESP },
2795
  { 5U, X86::EBP },
2796
  { 6U, X86::ESI },
2797
  { 7U, X86::EDI },
2798
  { 8U, X86::EIP },
2799
  { 11U, X86::ST0 },
2800
  { 12U, X86::ST1 },
2801
  { 13U, X86::ST2 },
2802
  { 14U, X86::ST3 },
2803
  { 15U, X86::ST4 },
2804
  { 16U, X86::ST5 },
2805
  { 17U, X86::ST6 },
2806
  { 18U, X86::ST7 },
2807
  { 21U, X86::XMM0 },
2808
  { 22U, X86::XMM1 },
2809
  { 23U, X86::XMM2 },
2810
  { 24U, X86::XMM3 },
2811
  { 25U, X86::XMM4 },
2812
  { 26U, X86::XMM5 },
2813
  { 27U, X86::XMM6 },
2814
  { 28U, X86::XMM7 },
2815
  { 29U, X86::MM0 },
2816
  { 30U, X86::MM1 },
2817
  { 31U, X86::MM2 },
2818
  { 32U, X86::MM3 },
2819
  { 33U, X86::MM4 },
2820
  { 34U, X86::MM5 },
2821
  { 35U, X86::MM6 },
2822
  { 36U, X86::MM7 },
2823
  { 93U, X86::K0 },
2824
  { 94U, X86::K1 },
2825
  { 95U, X86::K2 },
2826
  { 96U, X86::K3 },
2827
  { 97U, X86::K4 },
2828
  { 98U, X86::K5 },
2829
  { 99U, X86::K6 },
2830
  { 100U, X86::K7 },
2831
};
2832
extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L);
2833
2834
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2835
  { 0U, X86::RAX },
2836
  { 1U, X86::RDX },
2837
  { 2U, X86::RCX },
2838
  { 3U, X86::RBX },
2839
  { 4U, X86::RSI },
2840
  { 5U, X86::RDI },
2841
  { 6U, X86::RBP },
2842
  { 7U, X86::RSP },
2843
  { 8U, X86::R8 },
2844
  { 9U, X86::R9 },
2845
  { 10U, X86::R10 },
2846
  { 11U, X86::R11 },
2847
  { 12U, X86::R12 },
2848
  { 13U, X86::R13 },
2849
  { 14U, X86::R14 },
2850
  { 15U, X86::R15 },
2851
  { 16U, X86::RIP },
2852
  { 17U, X86::XMM0 },
2853
  { 18U, X86::XMM1 },
2854
  { 19U, X86::XMM2 },
2855
  { 20U, X86::XMM3 },
2856
  { 21U, X86::XMM4 },
2857
  { 22U, X86::XMM5 },
2858
  { 23U, X86::XMM6 },
2859
  { 24U, X86::XMM7 },
2860
  { 25U, X86::XMM8 },
2861
  { 26U, X86::XMM9 },
2862
  { 27U, X86::XMM10 },
2863
  { 28U, X86::XMM11 },
2864
  { 29U, X86::XMM12 },
2865
  { 30U, X86::XMM13 },
2866
  { 31U, X86::XMM14 },
2867
  { 32U, X86::XMM15 },
2868
  { 33U, X86::ST0 },
2869
  { 34U, X86::ST1 },
2870
  { 35U, X86::ST2 },
2871
  { 36U, X86::ST3 },
2872
  { 37U, X86::ST4 },
2873
  { 38U, X86::ST5 },
2874
  { 39U, X86::ST6 },
2875
  { 40U, X86::ST7 },
2876
  { 41U, X86::MM0 },
2877
  { 42U, X86::MM1 },
2878
  { 43U, X86::MM2 },
2879
  { 44U, X86::MM3 },
2880
  { 45U, X86::MM4 },
2881
  { 46U, X86::MM5 },
2882
  { 47U, X86::MM6 },
2883
  { 48U, X86::MM7 },
2884
  { 67U, X86::XMM16 },
2885
  { 68U, X86::XMM17 },
2886
  { 69U, X86::XMM18 },
2887
  { 70U, X86::XMM19 },
2888
  { 71U, X86::XMM20 },
2889
  { 72U, X86::XMM21 },
2890
  { 73U, X86::XMM22 },
2891
  { 74U, X86::XMM23 },
2892
  { 75U, X86::XMM24 },
2893
  { 76U, X86::XMM25 },
2894
  { 77U, X86::XMM26 },
2895
  { 78U, X86::XMM27 },
2896
  { 79U, X86::XMM28 },
2897
  { 80U, X86::XMM29 },
2898
  { 81U, X86::XMM30 },
2899
  { 82U, X86::XMM31 },
2900
  { 118U, X86::K0 },
2901
  { 119U, X86::K1 },
2902
  { 120U, X86::K2 },
2903
  { 121U, X86::K3 },
2904
  { 122U, X86::K4 },
2905
  { 123U, X86::K5 },
2906
  { 124U, X86::K6 },
2907
  { 125U, X86::K7 },
2908
};
2909
extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L);
2910
2911
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2912
  { 0U, X86::EAX },
2913
  { 1U, X86::ECX },
2914
  { 2U, X86::EDX },
2915
  { 3U, X86::EBX },
2916
  { 4U, X86::EBP },
2917
  { 5U, X86::ESP },
2918
  { 6U, X86::ESI },
2919
  { 7U, X86::EDI },
2920
  { 8U, X86::EIP },
2921
  { 12U, X86::ST0 },
2922
  { 13U, X86::ST1 },
2923
  { 14U, X86::ST2 },
2924
  { 15U, X86::ST3 },
2925
  { 16U, X86::ST4 },
2926
  { 17U, X86::ST5 },
2927
  { 18U, X86::ST6 },
2928
  { 19U, X86::ST7 },
2929
  { 21U, X86::XMM0 },
2930
  { 22U, X86::XMM1 },
2931
  { 23U, X86::XMM2 },
2932
  { 24U, X86::XMM3 },
2933
  { 25U, X86::XMM4 },
2934
  { 26U, X86::XMM5 },
2935
  { 27U, X86::XMM6 },
2936
  { 28U, X86::XMM7 },
2937
  { 29U, X86::MM0 },
2938
  { 30U, X86::MM1 },
2939
  { 31U, X86::MM2 },
2940
  { 32U, X86::MM3 },
2941
  { 33U, X86::MM4 },
2942
  { 34U, X86::MM5 },
2943
  { 35U, X86::MM6 },
2944
  { 36U, X86::MM7 },
2945
  { 93U, X86::K0 },
2946
  { 94U, X86::K1 },
2947
  { 95U, X86::K2 },
2948
  { 96U, X86::K3 },
2949
  { 97U, X86::K4 },
2950
  { 98U, X86::K5 },
2951
  { 99U, X86::K6 },
2952
  { 100U, X86::K7 },
2953
};
2954
extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L);
2955
2956
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
2957
  { 0U, X86::EAX },
2958
  { 1U, X86::ECX },
2959
  { 2U, X86::EDX },
2960
  { 3U, X86::EBX },
2961
  { 4U, X86::ESP },
2962
  { 5U, X86::EBP },
2963
  { 6U, X86::ESI },
2964
  { 7U, X86::EDI },
2965
  { 8U, X86::EIP },
2966
  { 11U, X86::ST0 },
2967
  { 12U, X86::ST1 },
2968
  { 13U, X86::ST2 },
2969
  { 14U, X86::ST3 },
2970
  { 15U, X86::ST4 },
2971
  { 16U, X86::ST5 },
2972
  { 17U, X86::ST6 },
2973
  { 18U, X86::ST7 },
2974
  { 21U, X86::XMM0 },
2975
  { 22U, X86::XMM1 },
2976
  { 23U, X86::XMM2 },
2977
  { 24U, X86::XMM3 },
2978
  { 25U, X86::XMM4 },
2979
  { 26U, X86::XMM5 },
2980
  { 27U, X86::XMM6 },
2981
  { 28U, X86::XMM7 },
2982
  { 29U, X86::MM0 },
2983
  { 30U, X86::MM1 },
2984
  { 31U, X86::MM2 },
2985
  { 32U, X86::MM3 },
2986
  { 33U, X86::MM4 },
2987
  { 34U, X86::MM5 },
2988
  { 35U, X86::MM6 },
2989
  { 36U, X86::MM7 },
2990
  { 93U, X86::K0 },
2991
  { 94U, X86::K1 },
2992
  { 95U, X86::K2 },
2993
  { 96U, X86::K3 },
2994
  { 97U, X86::K4 },
2995
  { 98U, X86::K5 },
2996
  { 99U, X86::K6 },
2997
  { 100U, X86::K7 },
2998
};
2999
extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L);
3000
3001
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3002
  { X86::EAX, -2U },
3003
  { X86::EBP, -2U },
3004
  { X86::EBX, -2U },
3005
  { X86::ECX, -2U },
3006
  { X86::EDI, -2U },
3007
  { X86::EDX, -2U },
3008
  { X86::EIP, -2U },
3009
  { X86::ESI, -2U },
3010
  { X86::ESP, -2U },
3011
  { X86::RAX, 0U },
3012
  { X86::RBP, 6U },
3013
  { X86::RBX, 3U },
3014
  { X86::RCX, 2U },
3015
  { X86::RDI, 5U },
3016
  { X86::RDX, 1U },
3017
  { X86::RIP, 16U },
3018
  { X86::RSI, 4U },
3019
  { X86::RSP, 7U },
3020
  { X86::K0, 118U },
3021
  { X86::K1, 119U },
3022
  { X86::K2, 120U },
3023
  { X86::K3, 121U },
3024
  { X86::K4, 122U },
3025
  { X86::K5, 123U },
3026
  { X86::K6, 124U },
3027
  { X86::K7, 125U },
3028
  { X86::MM0, 41U },
3029
  { X86::MM1, 42U },
3030
  { X86::MM2, 43U },
3031
  { X86::MM3, 44U },
3032
  { X86::MM4, 45U },
3033
  { X86::MM5, 46U },
3034
  { X86::MM6, 47U },
3035
  { X86::MM7, 48U },
3036
  { X86::R8, 8U },
3037
  { X86::R9, 9U },
3038
  { X86::R10, 10U },
3039
  { X86::R11, 11U },
3040
  { X86::R12, 12U },
3041
  { X86::R13, 13U },
3042
  { X86::R14, 14U },
3043
  { X86::R15, 15U },
3044
  { X86::ST0, 33U },
3045
  { X86::ST1, 34U },
3046
  { X86::ST2, 35U },
3047
  { X86::ST3, 36U },
3048
  { X86::ST4, 37U },
3049
  { X86::ST5, 38U },
3050
  { X86::ST6, 39U },
3051
  { X86::ST7, 40U },
3052
  { X86::XMM0, 17U },
3053
  { X86::XMM1, 18U },
3054
  { X86::XMM2, 19U },
3055
  { X86::XMM3, 20U },
3056
  { X86::XMM4, 21U },
3057
  { X86::XMM5, 22U },
3058
  { X86::XMM6, 23U },
3059
  { X86::XMM7, 24U },
3060
  { X86::XMM8, 25U },
3061
  { X86::XMM9, 26U },
3062
  { X86::XMM10, 27U },
3063
  { X86::XMM11, 28U },
3064
  { X86::XMM12, 29U },
3065
  { X86::XMM13, 30U },
3066
  { X86::XMM14, 31U },
3067
  { X86::XMM15, 32U },
3068
  { X86::XMM16, 67U },
3069
  { X86::XMM17, 68U },
3070
  { X86::XMM18, 69U },
3071
  { X86::XMM19, 70U },
3072
  { X86::XMM20, 71U },
3073
  { X86::XMM21, 72U },
3074
  { X86::XMM22, 73U },
3075
  { X86::XMM23, 74U },
3076
  { X86::XMM24, 75U },
3077
  { X86::XMM25, 76U },
3078
  { X86::XMM26, 77U },
3079
  { X86::XMM27, 78U },
3080
  { X86::XMM28, 79U },
3081
  { X86::XMM29, 80U },
3082
  { X86::XMM30, 81U },
3083
  { X86::XMM31, 82U },
3084
  { X86::YMM0, 17U },
3085
  { X86::YMM1, 18U },
3086
  { X86::YMM2, 19U },
3087
  { X86::YMM3, 20U },
3088
  { X86::YMM4, 21U },
3089
  { X86::YMM5, 22U },
3090
  { X86::YMM6, 23U },
3091
  { X86::YMM7, 24U },
3092
  { X86::YMM8, 25U },
3093
  { X86::YMM9, 26U },
3094
  { X86::YMM10, 27U },
3095
  { X86::YMM11, 28U },
3096
  { X86::YMM12, 29U },
3097
  { X86::YMM13, 30U },
3098
  { X86::YMM14, 31U },
3099
  { X86::YMM15, 32U },
3100
  { X86::YMM16, 67U },
3101
  { X86::YMM17, 68U },
3102
  { X86::YMM18, 69U },
3103
  { X86::YMM19, 70U },
3104
  { X86::YMM20, 71U },
3105
  { X86::YMM21, 72U },
3106
  { X86::YMM22, 73U },
3107
  { X86::YMM23, 74U },
3108
  { X86::YMM24, 75U },
3109
  { X86::YMM25, 76U },
3110
  { X86::YMM26, 77U },
3111
  { X86::YMM27, 78U },
3112
  { X86::YMM28, 79U },
3113
  { X86::YMM29, 80U },
3114
  { X86::YMM30, 81U },
3115
  { X86::YMM31, 82U },
3116
  { X86::ZMM0, 17U },
3117
  { X86::ZMM1, 18U },
3118
  { X86::ZMM2, 19U },
3119
  { X86::ZMM3, 20U },
3120
  { X86::ZMM4, 21U },
3121
  { X86::ZMM5, 22U },
3122
  { X86::ZMM6, 23U },
3123
  { X86::ZMM7, 24U },
3124
  { X86::ZMM8, 25U },
3125
  { X86::ZMM9, 26U },
3126
  { X86::ZMM10, 27U },
3127
  { X86::ZMM11, 28U },
3128
  { X86::ZMM12, 29U },
3129
  { X86::ZMM13, 30U },
3130
  { X86::ZMM14, 31U },
3131
  { X86::ZMM15, 32U },
3132
  { X86::ZMM16, 67U },
3133
  { X86::ZMM17, 68U },
3134
  { X86::ZMM18, 69U },
3135
  { X86::ZMM19, 70U },
3136
  { X86::ZMM20, 71U },
3137
  { X86::ZMM21, 72U },
3138
  { X86::ZMM22, 73U },
3139
  { X86::ZMM23, 74U },
3140
  { X86::ZMM24, 75U },
3141
  { X86::ZMM25, 76U },
3142
  { X86::ZMM26, 77U },
3143
  { X86::ZMM27, 78U },
3144
  { X86::ZMM28, 79U },
3145
  { X86::ZMM29, 80U },
3146
  { X86::ZMM30, 81U },
3147
  { X86::ZMM31, 82U },
3148
};
3149
extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf);
3150
3151
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3152
  { X86::EAX, 0U },
3153
  { X86::EBP, 4U },
3154
  { X86::EBX, 3U },
3155
  { X86::ECX, 1U },
3156
  { X86::EDI, 7U },
3157
  { X86::EDX, 2U },
3158
  { X86::EIP, 8U },
3159
  { X86::ESI, 6U },
3160
  { X86::ESP, 5U },
3161
  { X86::RAX, -2U },
3162
  { X86::RBP, -2U },
3163
  { X86::RBX, -2U },
3164
  { X86::RCX, -2U },
3165
  { X86::RDI, -2U },
3166
  { X86::RDX, -2U },
3167
  { X86::RIP, -2U },
3168
  { X86::RSI, -2U },
3169
  { X86::RSP, -2U },
3170
  { X86::K0, 93U },
3171
  { X86::K1, 94U },
3172
  { X86::K2, 95U },
3173
  { X86::K3, 96U },
3174
  { X86::K4, 97U },
3175
  { X86::K5, 98U },
3176
  { X86::K6, 99U },
3177
  { X86::K7, 100U },
3178
  { X86::MM0, 29U },
3179
  { X86::MM1, 30U },
3180
  { X86::MM2, 31U },
3181
  { X86::MM3, 32U },
3182
  { X86::MM4, 33U },
3183
  { X86::MM5, 34U },
3184
  { X86::MM6, 35U },
3185
  { X86::MM7, 36U },
3186
  { X86::R8, -2U },
3187
  { X86::R9, -2U },
3188
  { X86::R10, -2U },
3189
  { X86::R11, -2U },
3190
  { X86::R12, -2U },
3191
  { X86::R13, -2U },
3192
  { X86::R14, -2U },
3193
  { X86::R15, -2U },
3194
  { X86::ST0, 12U },
3195
  { X86::ST1, 13U },
3196
  { X86::ST2, 14U },
3197
  { X86::ST3, 15U },
3198
  { X86::ST4, 16U },
3199
  { X86::ST5, 17U },
3200
  { X86::ST6, 18U },
3201
  { X86::ST7, 19U },
3202
  { X86::XMM0, 21U },
3203
  { X86::XMM1, 22U },
3204
  { X86::XMM2, 23U },
3205
  { X86::XMM3, 24U },
3206
  { X86::XMM4, 25U },
3207
  { X86::XMM5, 26U },
3208
  { X86::XMM6, 27U },
3209
  { X86::XMM7, 28U },
3210
  { X86::XMM8, -2U },
3211
  { X86::XMM9, -2U },
3212
  { X86::XMM10, -2U },
3213
  { X86::XMM11, -2U },
3214
  { X86::XMM12, -2U },
3215
  { X86::XMM13, -2U },
3216
  { X86::XMM14, -2U },
3217
  { X86::XMM15, -2U },
3218
  { X86::XMM16, -2U },
3219
  { X86::XMM17, -2U },
3220
  { X86::XMM18, -2U },
3221
  { X86::XMM19, -2U },
3222
  { X86::XMM20, -2U },
3223
  { X86::XMM21, -2U },
3224
  { X86::XMM22, -2U },
3225
  { X86::XMM23, -2U },
3226
  { X86::XMM24, -2U },
3227
  { X86::XMM25, -2U },
3228
  { X86::XMM26, -2U },
3229
  { X86::XMM27, -2U },
3230
  { X86::XMM28, -2U },
3231
  { X86::XMM29, -2U },
3232
  { X86::XMM30, -2U },
3233
  { X86::XMM31, -2U },
3234
  { X86::YMM0, 21U },
3235
  { X86::YMM1, 22U },
3236
  { X86::YMM2, 23U },
3237
  { X86::YMM3, 24U },
3238
  { X86::YMM4, 25U },
3239
  { X86::YMM5, 26U },
3240
  { X86::YMM6, 27U },
3241
  { X86::YMM7, 28U },
3242
  { X86::YMM8, -2U },
3243
  { X86::YMM9, -2U },
3244
  { X86::YMM10, -2U },
3245
  { X86::YMM11, -2U },
3246
  { X86::YMM12, -2U },
3247
  { X86::YMM13, -2U },
3248
  { X86::YMM14, -2U },
3249
  { X86::YMM15, -2U },
3250
  { X86::YMM16, -2U },
3251
  { X86::YMM17, -2U },
3252
  { X86::YMM18, -2U },
3253
  { X86::YMM19, -2U },
3254
  { X86::YMM20, -2U },
3255
  { X86::YMM21, -2U },
3256
  { X86::YMM22, -2U },
3257
  { X86::YMM23, -2U },
3258
  { X86::YMM24, -2U },
3259
  { X86::YMM25, -2U },
3260
  { X86::YMM26, -2U },
3261
  { X86::YMM27, -2U },
3262
  { X86::YMM28, -2U },
3263
  { X86::YMM29, -2U },
3264
  { X86::YMM30, -2U },
3265
  { X86::YMM31, -2U },
3266
  { X86::ZMM0, 21U },
3267
  { X86::ZMM1, 22U },
3268
  { X86::ZMM2, 23U },
3269
  { X86::ZMM3, 24U },
3270
  { X86::ZMM4, 25U },
3271
  { X86::ZMM5, 26U },
3272
  { X86::ZMM6, 27U },
3273
  { X86::ZMM7, 28U },
3274
  { X86::ZMM8, -2U },
3275
  { X86::ZMM9, -2U },
3276
  { X86::ZMM10, -2U },
3277
  { X86::ZMM11, -2U },
3278
  { X86::ZMM12, -2U },
3279
  { X86::ZMM13, -2U },
3280
  { X86::ZMM14, -2U },
3281
  { X86::ZMM15, -2U },
3282
  { X86::ZMM16, -2U },
3283
  { X86::ZMM17, -2U },
3284
  { X86::ZMM18, -2U },
3285
  { X86::ZMM19, -2U },
3286
  { X86::ZMM20, -2U },
3287
  { X86::ZMM21, -2U },
3288
  { X86::ZMM22, -2U },
3289
  { X86::ZMM23, -2U },
3290
  { X86::ZMM24, -2U },
3291
  { X86::ZMM25, -2U },
3292
  { X86::ZMM26, -2U },
3293
  { X86::ZMM27, -2U },
3294
  { X86::ZMM28, -2U },
3295
  { X86::ZMM29, -2U },
3296
  { X86::ZMM30, -2U },
3297
  { X86::ZMM31, -2U },
3298
};
3299
extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf);
3300
3301
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3302
  { X86::EAX, 0U },
3303
  { X86::EBP, 5U },
3304
  { X86::EBX, 3U },
3305
  { X86::ECX, 1U },
3306
  { X86::EDI, 7U },
3307
  { X86::EDX, 2U },
3308
  { X86::EIP, 8U },
3309
  { X86::ESI, 6U },
3310
  { X86::ESP, 4U },
3311
  { X86::RAX, -2U },
3312
  { X86::RBP, -2U },
3313
  { X86::RBX, -2U },
3314
  { X86::RCX, -2U },
3315
  { X86::RDI, -2U },
3316
  { X86::RDX, -2U },
3317
  { X86::RIP, -2U },
3318
  { X86::RSI, -2U },
3319
  { X86::RSP, -2U },
3320
  { X86::K0, 93U },
3321
  { X86::K1, 94U },
3322
  { X86::K2, 95U },
3323
  { X86::K3, 96U },
3324
  { X86::K4, 97U },
3325
  { X86::K5, 98U },
3326
  { X86::K6, 99U },
3327
  { X86::K7, 100U },
3328
  { X86::MM0, 29U },
3329
  { X86::MM1, 30U },
3330
  { X86::MM2, 31U },
3331
  { X86::MM3, 32U },
3332
  { X86::MM4, 33U },
3333
  { X86::MM5, 34U },
3334
  { X86::MM6, 35U },
3335
  { X86::MM7, 36U },
3336
  { X86::R8, -2U },
3337
  { X86::R9, -2U },
3338
  { X86::R10, -2U },
3339
  { X86::R11, -2U },
3340
  { X86::R12, -2U },
3341
  { X86::R13, -2U },
3342
  { X86::R14, -2U },
3343
  { X86::R15, -2U },
3344
  { X86::ST0, 11U },
3345
  { X86::ST1, 12U },
3346
  { X86::ST2, 13U },
3347
  { X86::ST3, 14U },
3348
  { X86::ST4, 15U },
3349
  { X86::ST5, 16U },
3350
  { X86::ST6, 17U },
3351
  { X86::ST7, 18U },
3352
  { X86::XMM0, 21U },
3353
  { X86::XMM1, 22U },
3354
  { X86::XMM2, 23U },
3355
  { X86::XMM3, 24U },
3356
  { X86::XMM4, 25U },
3357
  { X86::XMM5, 26U },
3358
  { X86::XMM6, 27U },
3359
  { X86::XMM7, 28U },
3360
  { X86::XMM8, -2U },
3361
  { X86::XMM9, -2U },
3362
  { X86::XMM10, -2U },
3363
  { X86::XMM11, -2U },
3364
  { X86::XMM12, -2U },
3365
  { X86::XMM13, -2U },
3366
  { X86::XMM14, -2U },
3367
  { X86::XMM15, -2U },
3368
  { X86::XMM16, -2U },
3369
  { X86::XMM17, -2U },
3370
  { X86::XMM18, -2U },
3371
  { X86::XMM19, -2U },
3372
  { X86::XMM20, -2U },
3373
  { X86::XMM21, -2U },
3374
  { X86::XMM22, -2U },
3375
  { X86::XMM23, -2U },
3376
  { X86::XMM24, -2U },
3377
  { X86::XMM25, -2U },
3378
  { X86::XMM26, -2U },
3379
  { X86::XMM27, -2U },
3380
  { X86::XMM28, -2U },
3381
  { X86::XMM29, -2U },
3382
  { X86::XMM30, -2U },
3383
  { X86::XMM31, -2U },
3384
  { X86::YMM0, 21U },
3385
  { X86::YMM1, 22U },
3386
  { X86::YMM2, 23U },
3387
  { X86::YMM3, 24U },
3388
  { X86::YMM4, 25U },
3389
  { X86::YMM5, 26U },
3390
  { X86::YMM6, 27U },
3391
  { X86::YMM7, 28U },
3392
  { X86::YMM8, -2U },
3393
  { X86::YMM9, -2U },
3394
  { X86::YMM10, -2U },
3395
  { X86::YMM11, -2U },
3396
  { X86::YMM12, -2U },
3397
  { X86::YMM13, -2U },
3398
  { X86::YMM14, -2U },
3399
  { X86::YMM15, -2U },
3400
  { X86::YMM16, -2U },
3401
  { X86::YMM17, -2U },
3402
  { X86::YMM18, -2U },
3403
  { X86::YMM19, -2U },
3404
  { X86::YMM20, -2U },
3405
  { X86::YMM21, -2U },
3406
  { X86::YMM22, -2U },
3407
  { X86::YMM23, -2U },
3408
  { X86::YMM24, -2U },
3409
  { X86::YMM25, -2U },
3410
  { X86::YMM26, -2U },
3411
  { X86::YMM27, -2U },
3412
  { X86::YMM28, -2U },
3413
  { X86::YMM29, -2U },
3414
  { X86::YMM30, -2U },
3415
  { X86::YMM31, -2U },
3416
  { X86::ZMM0, 21U },
3417
  { X86::ZMM1, 22U },
3418
  { X86::ZMM2, 23U },
3419
  { X86::ZMM3, 24U },
3420
  { X86::ZMM4, 25U },
3421
  { X86::ZMM5, 26U },
3422
  { X86::ZMM6, 27U },
3423
  { X86::ZMM7, 28U },
3424
  { X86::ZMM8, -2U },
3425
  { X86::ZMM9, -2U },
3426
  { X86::ZMM10, -2U },
3427
  { X86::ZMM11, -2U },
3428
  { X86::ZMM12, -2U },
3429
  { X86::ZMM13, -2U },
3430
  { X86::ZMM14, -2U },
3431
  { X86::ZMM15, -2U },
3432
  { X86::ZMM16, -2U },
3433
  { X86::ZMM17, -2U },
3434
  { X86::ZMM18, -2U },
3435
  { X86::ZMM19, -2U },
3436
  { X86::ZMM20, -2U },
3437
  { X86::ZMM21, -2U },
3438
  { X86::ZMM22, -2U },
3439
  { X86::ZMM23, -2U },
3440
  { X86::ZMM24, -2U },
3441
  { X86::ZMM25, -2U },
3442
  { X86::ZMM26, -2U },
3443
  { X86::ZMM27, -2U },
3444
  { X86::ZMM28, -2U },
3445
  { X86::ZMM29, -2U },
3446
  { X86::ZMM30, -2U },
3447
  { X86::ZMM31, -2U },
3448
};
3449
extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf);
3450
3451
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3452
  { X86::EAX, -2U },
3453
  { X86::EBP, -2U },
3454
  { X86::EBX, -2U },
3455
  { X86::ECX, -2U },
3456
  { X86::EDI, -2U },
3457
  { X86::EDX, -2U },
3458
  { X86::EIP, -2U },
3459
  { X86::ESI, -2U },
3460
  { X86::ESP, -2U },
3461
  { X86::RAX, 0U },
3462
  { X86::RBP, 6U },
3463
  { X86::RBX, 3U },
3464
  { X86::RCX, 2U },
3465
  { X86::RDI, 5U },
3466
  { X86::RDX, 1U },
3467
  { X86::RIP, 16U },
3468
  { X86::RSI, 4U },
3469
  { X86::RSP, 7U },
3470
  { X86::K0, 118U },
3471
  { X86::K1, 119U },
3472
  { X86::K2, 120U },
3473
  { X86::K3, 121U },
3474
  { X86::K4, 122U },
3475
  { X86::K5, 123U },
3476
  { X86::K6, 124U },
3477
  { X86::K7, 125U },
3478
  { X86::MM0, 41U },
3479
  { X86::MM1, 42U },
3480
  { X86::MM2, 43U },
3481
  { X86::MM3, 44U },
3482
  { X86::MM4, 45U },
3483
  { X86::MM5, 46U },
3484
  { X86::MM6, 47U },
3485
  { X86::MM7, 48U },
3486
  { X86::R8, 8U },
3487
  { X86::R9, 9U },
3488
  { X86::R10, 10U },
3489
  { X86::R11, 11U },
3490
  { X86::R12, 12U },
3491
  { X86::R13, 13U },
3492
  { X86::R14, 14U },
3493
  { X86::R15, 15U },
3494
  { X86::ST0, 33U },
3495
  { X86::ST1, 34U },
3496
  { X86::ST2, 35U },
3497
  { X86::ST3, 36U },
3498
  { X86::ST4, 37U },
3499
  { X86::ST5, 38U },
3500
  { X86::ST6, 39U },
3501
  { X86::ST7, 40U },
3502
  { X86::XMM0, 17U },
3503
  { X86::XMM1, 18U },
3504
  { X86::XMM2, 19U },
3505
  { X86::XMM3, 20U },
3506
  { X86::XMM4, 21U },
3507
  { X86::XMM5, 22U },
3508
  { X86::XMM6, 23U },
3509
  { X86::XMM7, 24U },
3510
  { X86::XMM8, 25U },
3511
  { X86::XMM9, 26U },
3512
  { X86::XMM10, 27U },
3513
  { X86::XMM11, 28U },
3514
  { X86::XMM12, 29U },
3515
  { X86::XMM13, 30U },
3516
  { X86::XMM14, 31U },
3517
  { X86::XMM15, 32U },
3518
  { X86::XMM16, 67U },
3519
  { X86::XMM17, 68U },
3520
  { X86::XMM18, 69U },
3521
  { X86::XMM19, 70U },
3522
  { X86::XMM20, 71U },
3523
  { X86::XMM21, 72U },
3524
  { X86::XMM22, 73U },
3525
  { X86::XMM23, 74U },
3526
  { X86::XMM24, 75U },
3527
  { X86::XMM25, 76U },
3528
  { X86::XMM26, 77U },
3529
  { X86::XMM27, 78U },
3530
  { X86::XMM28, 79U },
3531
  { X86::XMM29, 80U },
3532
  { X86::XMM30, 81U },
3533
  { X86::XMM31, 82U },
3534
  { X86::YMM0, 17U },
3535
  { X86::YMM1, 18U },
3536
  { X86::YMM2, 19U },
3537
  { X86::YMM3, 20U },
3538
  { X86::YMM4, 21U },
3539
  { X86::YMM5, 22U },
3540
  { X86::YMM6, 23U },
3541
  { X86::YMM7, 24U },
3542
  { X86::YMM8, 25U },
3543
  { X86::YMM9, 26U },
3544
  { X86::YMM10, 27U },
3545
  { X86::YMM11, 28U },
3546
  { X86::YMM12, 29U },
3547
  { X86::YMM13, 30U },
3548
  { X86::YMM14, 31U },
3549
  { X86::YMM15, 32U },
3550
  { X86::YMM16, 67U },
3551
  { X86::YMM17, 68U },
3552
  { X86::YMM18, 69U },
3553
  { X86::YMM19, 70U },
3554
  { X86::YMM20, 71U },
3555
  { X86::YMM21, 72U },
3556
  { X86::YMM22, 73U },
3557
  { X86::YMM23, 74U },
3558
  { X86::YMM24, 75U },
3559
  { X86::YMM25, 76U },
3560
  { X86::YMM26, 77U },
3561
  { X86::YMM27, 78U },
3562
  { X86::YMM28, 79U },
3563
  { X86::YMM29, 80U },
3564
  { X86::YMM30, 81U },
3565
  { X86::YMM31, 82U },
3566
  { X86::ZMM0, 17U },
3567
  { X86::ZMM1, 18U },
3568
  { X86::ZMM2, 19U },
3569
  { X86::ZMM3, 20U },
3570
  { X86::ZMM4, 21U },
3571
  { X86::ZMM5, 22U },
3572
  { X86::ZMM6, 23U },
3573
  { X86::ZMM7, 24U },
3574
  { X86::ZMM8, 25U },
3575
  { X86::ZMM9, 26U },
3576
  { X86::ZMM10, 27U },
3577
  { X86::ZMM11, 28U },
3578
  { X86::ZMM12, 29U },
3579
  { X86::ZMM13, 30U },
3580
  { X86::ZMM14, 31U },
3581
  { X86::ZMM15, 32U },
3582
  { X86::ZMM16, 67U },
3583
  { X86::ZMM17, 68U },
3584
  { X86::ZMM18, 69U },
3585
  { X86::ZMM19, 70U },
3586
  { X86::ZMM20, 71U },
3587
  { X86::ZMM21, 72U },
3588
  { X86::ZMM22, 73U },
3589
  { X86::ZMM23, 74U },
3590
  { X86::ZMM24, 75U },
3591
  { X86::ZMM25, 76U },
3592
  { X86::ZMM26, 77U },
3593
  { X86::ZMM27, 78U },
3594
  { X86::ZMM28, 79U },
3595
  { X86::ZMM29, 80U },
3596
  { X86::ZMM30, 81U },
3597
  { X86::ZMM31, 82U },
3598
};
3599
extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf);
3600
3601
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3602
  { X86::EAX, 0U },
3603
  { X86::EBP, 4U },
3604
  { X86::EBX, 3U },
3605
  { X86::ECX, 1U },
3606
  { X86::EDI, 7U },
3607
  { X86::EDX, 2U },
3608
  { X86::EIP, 8U },
3609
  { X86::ESI, 6U },
3610
  { X86::ESP, 5U },
3611
  { X86::RAX, -2U },
3612
  { X86::RBP, -2U },
3613
  { X86::RBX, -2U },
3614
  { X86::RCX, -2U },
3615
  { X86::RDI, -2U },
3616
  { X86::RDX, -2U },
3617
  { X86::RIP, -2U },
3618
  { X86::RSI, -2U },
3619
  { X86::RSP, -2U },
3620
  { X86::K0, 93U },
3621
  { X86::K1, 94U },
3622
  { X86::K2, 95U },
3623
  { X86::K3, 96U },
3624
  { X86::K4, 97U },
3625
  { X86::K5, 98U },
3626
  { X86::K6, 99U },
3627
  { X86::K7, 100U },
3628
  { X86::MM0, 29U },
3629
  { X86::MM1, 30U },
3630
  { X86::MM2, 31U },
3631
  { X86::MM3, 32U },
3632
  { X86::MM4, 33U },
3633
  { X86::MM5, 34U },
3634
  { X86::MM6, 35U },
3635
  { X86::MM7, 36U },
3636
  { X86::R8, -2U },
3637
  { X86::R9, -2U },
3638
  { X86::R10, -2U },
3639
  { X86::R11, -2U },
3640
  { X86::R12, -2U },
3641
  { X86::R13, -2U },
3642
  { X86::R14, -2U },
3643
  { X86::R15, -2U },
3644
  { X86::ST0, 12U },
3645
  { X86::ST1, 13U },
3646
  { X86::ST2, 14U },
3647
  { X86::ST3, 15U },
3648
  { X86::ST4, 16U },
3649
  { X86::ST5, 17U },
3650
  { X86::ST6, 18U },
3651
  { X86::ST7, 19U },
3652
  { X86::XMM0, 21U },
3653
  { X86::XMM1, 22U },
3654
  { X86::XMM2, 23U },
3655
  { X86::XMM3, 24U },
3656
  { X86::XMM4, 25U },
3657
  { X86::XMM5, 26U },
3658
  { X86::XMM6, 27U },
3659
  { X86::XMM7, 28U },
3660
  { X86::XMM8, -2U },
3661
  { X86::XMM9, -2U },
3662
  { X86::XMM10, -2U },
3663
  { X86::XMM11, -2U },
3664
  { X86::XMM12, -2U },
3665
  { X86::XMM13, -2U },
3666
  { X86::XMM14, -2U },
3667
  { X86::XMM15, -2U },
3668
  { X86::XMM16, -2U },
3669
  { X86::XMM17, -2U },
3670
  { X86::XMM18, -2U },
3671
  { X86::XMM19, -2U },
3672
  { X86::XMM20, -2U },
3673
  { X86::XMM21, -2U },
3674
  { X86::XMM22, -2U },
3675
  { X86::XMM23, -2U },
3676
  { X86::XMM24, -2U },
3677
  { X86::XMM25, -2U },
3678
  { X86::XMM26, -2U },
3679
  { X86::XMM27, -2U },
3680
  { X86::XMM28, -2U },
3681
  { X86::XMM29, -2U },
3682
  { X86::XMM30, -2U },
3683
  { X86::XMM31, -2U },
3684
  { X86::YMM0, 21U },
3685
  { X86::YMM1, 22U },
3686
  { X86::YMM2, 23U },
3687
  { X86::YMM3, 24U },
3688
  { X86::YMM4, 25U },
3689
  { X86::YMM5, 26U },
3690
  { X86::YMM6, 27U },
3691
  { X86::YMM7, 28U },
3692
  { X86::YMM8, -2U },
3693
  { X86::YMM9, -2U },
3694
  { X86::YMM10, -2U },
3695
  { X86::YMM11, -2U },
3696
  { X86::YMM12, -2U },
3697
  { X86::YMM13, -2U },
3698
  { X86::YMM14, -2U },
3699
  { X86::YMM15, -2U },
3700
  { X86::YMM16, -2U },
3701
  { X86::YMM17, -2U },
3702
  { X86::YMM18, -2U },
3703
  { X86::YMM19, -2U },
3704
  { X86::YMM20, -2U },
3705
  { X86::YMM21, -2U },
3706
  { X86::YMM22, -2U },
3707
  { X86::YMM23, -2U },
3708
  { X86::YMM24, -2U },
3709
  { X86::YMM25, -2U },
3710
  { X86::YMM26, -2U },
3711
  { X86::YMM27, -2U },
3712
  { X86::YMM28, -2U },
3713
  { X86::YMM29, -2U },
3714
  { X86::YMM30, -2U },
3715
  { X86::YMM31, -2U },
3716
  { X86::ZMM0, 21U },
3717
  { X86::ZMM1, 22U },
3718
  { X86::ZMM2, 23U },
3719
  { X86::ZMM3, 24U },
3720
  { X86::ZMM4, 25U },
3721
  { X86::ZMM5, 26U },
3722
  { X86::ZMM6, 27U },
3723
  { X86::ZMM7, 28U },
3724
  { X86::ZMM8, -2U },
3725
  { X86::ZMM9, -2U },
3726
  { X86::ZMM10, -2U },
3727
  { X86::ZMM11, -2U },
3728
  { X86::ZMM12, -2U },
3729
  { X86::ZMM13, -2U },
3730
  { X86::ZMM14, -2U },
3731
  { X86::ZMM15, -2U },
3732
  { X86::ZMM16, -2U },
3733
  { X86::ZMM17, -2U },
3734
  { X86::ZMM18, -2U },
3735
  { X86::ZMM19, -2U },
3736
  { X86::ZMM20, -2U },
3737
  { X86::ZMM21, -2U },
3738
  { X86::ZMM22, -2U },
3739
  { X86::ZMM23, -2U },
3740
  { X86::ZMM24, -2U },
3741
  { X86::ZMM25, -2U },
3742
  { X86::ZMM26, -2U },
3743
  { X86::ZMM27, -2U },
3744
  { X86::ZMM28, -2U },
3745
  { X86::ZMM29, -2U },
3746
  { X86::ZMM30, -2U },
3747
  { X86::ZMM31, -2U },
3748
};
3749
extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf);
3750
3751
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3752
  { X86::EAX, 0U },
3753
  { X86::EBP, 5U },
3754
  { X86::EBX, 3U },
3755
  { X86::ECX, 1U },
3756
  { X86::EDI, 7U },
3757
  { X86::EDX, 2U },
3758
  { X86::EIP, 8U },
3759
  { X86::ESI, 6U },
3760
  { X86::ESP, 4U },
3761
  { X86::RAX, -2U },
3762
  { X86::RBP, -2U },
3763
  { X86::RBX, -2U },
3764
  { X86::RCX, -2U },
3765
  { X86::RDI, -2U },
3766
  { X86::RDX, -2U },
3767
  { X86::RIP, -2U },
3768
  { X86::RSI, -2U },
3769
  { X86::RSP, -2U },
3770
  { X86::K0, 93U },
3771
  { X86::K1, 94U },
3772
  { X86::K2, 95U },
3773
  { X86::K3, 96U },
3774
  { X86::K4, 97U },
3775
  { X86::K5, 98U },
3776
  { X86::K6, 99U },
3777
  { X86::K7, 100U },
3778
  { X86::MM0, 29U },
3779
  { X86::MM1, 30U },
3780
  { X86::MM2, 31U },
3781
  { X86::MM3, 32U },
3782
  { X86::MM4, 33U },
3783
  { X86::MM5, 34U },
3784
  { X86::MM6, 35U },
3785
  { X86::MM7, 36U },
3786
  { X86::R8, -2U },
3787
  { X86::R9, -2U },
3788
  { X86::R10, -2U },
3789
  { X86::R11, -2U },
3790
  { X86::R12, -2U },
3791
  { X86::R13, -2U },
3792
  { X86::R14, -2U },
3793
  { X86::R15, -2U },
3794
  { X86::ST0, 11U },
3795
  { X86::ST1, 12U },
3796
  { X86::ST2, 13U },
3797
  { X86::ST3, 14U },
3798
  { X86::ST4, 15U },
3799
  { X86::ST5, 16U },
3800
  { X86::ST6, 17U },
3801
  { X86::ST7, 18U },
3802
  { X86::XMM0, 21U },
3803
  { X86::XMM1, 22U },
3804
  { X86::XMM2, 23U },
3805
  { X86::XMM3, 24U },
3806
  { X86::XMM4, 25U },
3807
  { X86::XMM5, 26U },
3808
  { X86::XMM6, 27U },
3809
  { X86::XMM7, 28U },
3810
  { X86::XMM8, -2U },
3811
  { X86::XMM9, -2U },
3812
  { X86::XMM10, -2U },
3813
  { X86::XMM11, -2U },
3814
  { X86::XMM12, -2U },
3815
  { X86::XMM13, -2U },
3816
  { X86::XMM14, -2U },
3817
  { X86::XMM15, -2U },
3818
  { X86::XMM16, -2U },
3819
  { X86::XMM17, -2U },
3820
  { X86::XMM18, -2U },
3821
  { X86::XMM19, -2U },
3822
  { X86::XMM20, -2U },
3823
  { X86::XMM21, -2U },
3824
  { X86::XMM22, -2U },
3825
  { X86::XMM23, -2U },
3826
  { X86::XMM24, -2U },
3827
  { X86::XMM25, -2U },
3828
  { X86::XMM26, -2U },
3829
  { X86::XMM27, -2U },
3830
  { X86::XMM28, -2U },
3831
  { X86::XMM29, -2U },
3832
  { X86::XMM30, -2U },
3833
  { X86::XMM31, -2U },
3834
  { X86::YMM0, 21U },
3835
  { X86::YMM1, 22U },
3836
  { X86::YMM2, 23U },
3837
  { X86::YMM3, 24U },
3838
  { X86::YMM4, 25U },
3839
  { X86::YMM5, 26U },
3840
  { X86::YMM6, 27U },
3841
  { X86::YMM7, 28U },
3842
  { X86::YMM8, -2U },
3843
  { X86::YMM9, -2U },
3844
  { X86::YMM10, -2U },
3845
  { X86::YMM11, -2U },
3846
  { X86::YMM12, -2U },
3847
  { X86::YMM13, -2U },
3848
  { X86::YMM14, -2U },
3849
  { X86::YMM15, -2U },
3850
  { X86::YMM16, -2U },
3851
  { X86::YMM17, -2U },
3852
  { X86::YMM18, -2U },
3853
  { X86::YMM19, -2U },
3854
  { X86::YMM20, -2U },
3855
  { X86::YMM21, -2U },
3856
  { X86::YMM22, -2U },
3857
  { X86::YMM23, -2U },
3858
  { X86::YMM24, -2U },
3859
  { X86::YMM25, -2U },
3860
  { X86::YMM26, -2U },
3861
  { X86::YMM27, -2U },
3862
  { X86::YMM28, -2U },
3863
  { X86::YMM29, -2U },
3864
  { X86::YMM30, -2U },
3865
  { X86::YMM31, -2U },
3866
  { X86::ZMM0, 21U },
3867
  { X86::ZMM1, 22U },
3868
  { X86::ZMM2, 23U },
3869
  { X86::ZMM3, 24U },
3870
  { X86::ZMM4, 25U },
3871
  { X86::ZMM5, 26U },
3872
  { X86::ZMM6, 27U },
3873
  { X86::ZMM7, 28U },
3874
  { X86::ZMM8, -2U },
3875
  { X86::ZMM9, -2U },
3876
  { X86::ZMM10, -2U },
3877
  { X86::ZMM11, -2U },
3878
  { X86::ZMM12, -2U },
3879
  { X86::ZMM13, -2U },
3880
  { X86::ZMM14, -2U },
3881
  { X86::ZMM15, -2U },
3882
  { X86::ZMM16, -2U },
3883
  { X86::ZMM17, -2U },
3884
  { X86::ZMM18, -2U },
3885
  { X86::ZMM19, -2U },
3886
  { X86::ZMM20, -2U },
3887
  { X86::ZMM21, -2U },
3888
  { X86::ZMM22, -2U },
3889
  { X86::ZMM23, -2U },
3890
  { X86::ZMM24, -2U },
3891
  { X86::ZMM25, -2U },
3892
  { X86::ZMM26, -2U },
3893
  { X86::ZMM27, -2U },
3894
  { X86::ZMM28, -2U },
3895
  { X86::ZMM29, -2U },
3896
  { X86::ZMM30, -2U },
3897
  { X86::ZMM31, -2U },
3898
};
3899
extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf);
3900
3901
extern const uint16_t X86RegEncodingTable[] = {
3902
  0,
3903
  4,
3904
  0,
3905
  0,
3906
  7,
3907
  3,
3908
  5,
3909
  65535,
3910
  5,
3911
  3,
3912
  5,
3913
  1,
3914
  1,
3915
  1,
3916
  0,
3917
  6,
3918
  7,
3919
  65535,
3920
  7,
3921
  2,
3922
  3,
3923
  2,
3924
  0,
3925
  5,
3926
  3,
3927
  1,
3928
  7,
3929
  2,
3930
  0,
3931
  0,
3932
  4,
3933
  0,
3934
  6,
3935
  4,
3936
  0,
3937
  4,
3938
  5,
3939
  65535,
3940
  65535,
3941
  65535,
3942
  65535,
3943
  65535,
3944
  65535,
3945
  65535,
3946
  65535,
3947
  65535,
3948
  0,
3949
  0,
3950
  5,
3951
  3,
3952
  1,
3953
  7,
3954
  2,
3955
  0,
3956
  4,
3957
  6,
3958
  4,
3959
  6,
3960
  65535,
3961
  6,
3962
  4,
3963
  65535,
3964
  4,
3965
  2,
3966
  0,
3967
  0,
3968
  1,
3969
  2,
3970
  3,
3971
  0,
3972
  1,
3973
  2,
3974
  3,
3975
  4,
3976
  5,
3977
  6,
3978
  7,
3979
  8,
3980
  9,
3981
  10,
3982
  11,
3983
  12,
3984
  13,
3985
  14,
3986
  15,
3987
  0,
3988
  1,
3989
  2,
3990
  3,
3991
  4,
3992
  5,
3993
  6,
3994
  7,
3995
  8,
3996
  9,
3997
  10,
3998
  11,
3999
  12,
4000
  13,
4001
  14,
4002
  15,
4003
  0,
4004
  0,
4005
  0,
4006
  0,
4007
  0,
4008
  0,
4009
  0,
4010
  0,
4011
  0,
4012
  1,
4013
  2,
4014
  3,
4015
  4,
4016
  5,
4017
  6,
4018
  7,
4019
  0,
4020
  1,
4021
  2,
4022
  3,
4023
  4,
4024
  5,
4025
  6,
4026
  7,
4027
  8,
4028
  9,
4029
  10,
4030
  11,
4031
  12,
4032
  13,
4033
  14,
4034
  15,
4035
  0,
4036
  1,
4037
  2,
4038
  3,
4039
  4,
4040
  5,
4041
  6,
4042
  7,
4043
  0,
4044
  1,
4045
  2,
4046
  3,
4047
  4,
4048
  5,
4049
  6,
4050
  7,
4051
  8,
4052
  9,
4053
  10,
4054
  11,
4055
  12,
4056
  13,
4057
  14,
4058
  15,
4059
  16,
4060
  17,
4061
  18,
4062
  19,
4063
  20,
4064
  21,
4065
  22,
4066
  23,
4067
  24,
4068
  25,
4069
  26,
4070
  27,
4071
  28,
4072
  29,
4073
  30,
4074
  31,
4075
  0,
4076
  1,
4077
  2,
4078
  3,
4079
  4,
4080
  5,
4081
  6,
4082
  7,
4083
  8,
4084
  9,
4085
  10,
4086
  11,
4087
  12,
4088
  13,
4089
  14,
4090
  15,
4091
  16,
4092
  17,
4093
  18,
4094
  19,
4095
  20,
4096
  21,
4097
  22,
4098
  23,
4099
  24,
4100
  25,
4101
  26,
4102
  27,
4103
  28,
4104
  29,
4105
  30,
4106
  31,
4107
  0,
4108
  1,
4109
  2,
4110
  3,
4111
  4,
4112
  5,
4113
  6,
4114
  7,
4115
  8,
4116
  9,
4117
  10,
4118
  11,
4119
  12,
4120
  13,
4121
  14,
4122
  15,
4123
  16,
4124
  17,
4125
  18,
4126
  19,
4127
  20,
4128
  21,
4129
  22,
4130
  23,
4131
  24,
4132
  25,
4133
  26,
4134
  27,
4135
  28,
4136
  29,
4137
  30,
4138
  31,
4139
  8,
4140
  9,
4141
  10,
4142
  11,
4143
  12,
4144
  13,
4145
  14,
4146
  15,
4147
  65535,
4148
  65535,
4149
  65535,
4150
  65535,
4151
  65535,
4152
  65535,
4153
  65535,
4154
  65535,
4155
  8,
4156
  9,
4157
  10,
4158
  11,
4159
  12,
4160
  13,
4161
  14,
4162
  15,
4163
  8,
4164
  9,
4165
  10,
4166
  11,
4167
  12,
4168
  13,
4169
  14,
4170
  15,
4171
  65535,
4172
  65535,
4173
  65535,
4174
  65535,
4175
  65535,
4176
  65535,
4177
  65535,
4178
  65535,
4179
};
4180
25.8k
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4181
25.8k
  RI->InitMCRegisterInfo(X86RegDesc, 277, RA, PC, X86MCRegisterClasses, 117, X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 9,
4182
25.8k
X86SubRegIdxRanges, X86RegEncodingTable);
4183
25.8k
4184
25.8k
  switch (DwarfFlavour) {
4185
25.8k
  default:
4186
0
    llvm_unreachable("Unknown DWARF flavour");
4187
25.8k
  case 0:
4188
19.2k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
4189
19.2k
    break;
4190
25.8k
  case 1:
4191
0
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
4192
0
    break;
4193
25.8k
  case 2:
4194
6.67k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
4195
6.67k
    break;
4196
25.8k
  }
4197
25.8k
  switch (EHFlavour) {
4198
25.8k
  default:
4199
0
    llvm_unreachable("Unknown DWARF flavour");
4200
25.8k
  case 0:
4201
19.2k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
4202
19.2k
    break;
4203
25.8k
  case 1:
4204
1.98k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
4205
1.98k
    break;
4206
25.8k
  case 2:
4207
4.68k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
4208
4.68k
    break;
4209
25.8k
  }
4210
25.8k
  switch (DwarfFlavour) {
4211
25.8k
  default:
4212
0
    llvm_unreachable("Unknown DWARF flavour");
4213
25.8k
  case 0:
4214
19.2k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
4215
19.2k
    break;
4216
25.8k
  case 1:
4217
0
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
4218
0
    break;
4219
25.8k
  case 2:
4220
6.67k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
4221
6.67k
    break;
4222
25.9k
  }
4223
25.9k
  switch (EHFlavour) {
4224
25.9k
  default:
4225
0
    llvm_unreachable("Unknown DWARF flavour");
4226
25.9k
  case 0:
4227
19.2k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
4228
19.2k
    break;
4229
25.9k
  case 1:
4230
1.98k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
4231
1.98k
    break;
4232
25.9k
  case 2:
4233
4.68k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
4234
4.68k
    break;
4235
25.9k
  }
4236
25.9k
}
4237
4238
} // end namespace llvm
4239
4240
#endif // GET_REGINFO_MC_DESC
4241
4242
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4243
|*                                                                            *|
4244
|* Register Information Header Fragment                                       *|
4245
|*                                                                            *|
4246
|* Automatically generated file, do not edit!                                 *|
4247
|*                                                                            *|
4248
\*===----------------------------------------------------------------------===*/
4249
4250
4251
#ifdef GET_REGINFO_HEADER
4252
#undef GET_REGINFO_HEADER
4253
4254
#include "llvm/CodeGen/TargetRegisterInfo.h"
4255
4256
namespace llvm {
4257
4258
class X86FrameLowering;
4259
4260
struct X86GenRegisterInfo : public TargetRegisterInfo {
4261
  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4262
      unsigned PC = 0, unsigned HwMode = 0);
4263
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4264
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4265
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4266
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4267
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4268
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4269
  unsigned getNumRegPressureSets() const override;
4270
  const char *getRegPressureSetName(unsigned Idx) const override;
4271
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4272
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4273
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4274
  ArrayRef<const char *> getRegMaskNames() const override;
4275
  ArrayRef<const uint32_t *> getRegMasks() const override;
4276
  /// Devirtualized TargetFrameLowering.
4277
  static const X86FrameLowering *getFrameLowering(
4278
      const MachineFunction &MF);
4279
};
4280
4281
namespace X86 { // Register classes
4282
  extern const TargetRegisterClass GR8RegClass;
4283
  extern const TargetRegisterClass GRH8RegClass;
4284
  extern const TargetRegisterClass GR8_NOREXRegClass;
4285
  extern const TargetRegisterClass GR8_ABCD_HRegClass;
4286
  extern const TargetRegisterClass GR8_ABCD_LRegClass;
4287
  extern const TargetRegisterClass GRH16RegClass;
4288
  extern const TargetRegisterClass GR16RegClass;
4289
  extern const TargetRegisterClass GR16_NOREXRegClass;
4290
  extern const TargetRegisterClass VK1RegClass;
4291
  extern const TargetRegisterClass VK16RegClass;
4292
  extern const TargetRegisterClass VK2RegClass;
4293
  extern const TargetRegisterClass VK4RegClass;
4294
  extern const TargetRegisterClass VK8RegClass;
4295
  extern const TargetRegisterClass VK16WMRegClass;
4296
  extern const TargetRegisterClass VK1WMRegClass;
4297
  extern const TargetRegisterClass VK2WMRegClass;
4298
  extern const TargetRegisterClass VK4WMRegClass;
4299
  extern const TargetRegisterClass VK8WMRegClass;
4300
  extern const TargetRegisterClass SEGMENT_REGRegClass;
4301
  extern const TargetRegisterClass GR16_ABCDRegClass;
4302
  extern const TargetRegisterClass FPCCRRegClass;
4303
  extern const TargetRegisterClass FR32XRegClass;
4304
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
4305
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
4306
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
4307
  extern const TargetRegisterClass DEBUG_REGRegClass;
4308
  extern const TargetRegisterClass FR32RegClass;
4309
  extern const TargetRegisterClass GR32RegClass;
4310
  extern const TargetRegisterClass GR32_NOSPRegClass;
4311
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
4312
  extern const TargetRegisterClass GR32_NOREXRegClass;
4313
  extern const TargetRegisterClass VK32RegClass;
4314
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
4315
  extern const TargetRegisterClass RFP32RegClass;
4316
  extern const TargetRegisterClass VK32WMRegClass;
4317
  extern const TargetRegisterClass GR32_ABCDRegClass;
4318
  extern const TargetRegisterClass GR32_TCRegClass;
4319
  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
4320
  extern const TargetRegisterClass GR32_ADRegClass;
4321
  extern const TargetRegisterClass GR32_BPSPRegClass;
4322
  extern const TargetRegisterClass GR32_BSIRegClass;
4323
  extern const TargetRegisterClass GR32_CBRegClass;
4324
  extern const TargetRegisterClass GR32_DCRegClass;
4325
  extern const TargetRegisterClass GR32_DIBPRegClass;
4326
  extern const TargetRegisterClass GR32_SIDIRegClass;
4327
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
4328
  extern const TargetRegisterClass CCRRegClass;
4329
  extern const TargetRegisterClass DFCCRRegClass;
4330
  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
4331
  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
4332
  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
4333
  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
4334
  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
4335
  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
4336
  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
4337
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
4338
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
4339
  extern const TargetRegisterClass RFP64RegClass;
4340
  extern const TargetRegisterClass FR64XRegClass;
4341
  extern const TargetRegisterClass GR64RegClass;
4342
  extern const TargetRegisterClass CONTROL_REGRegClass;
4343
  extern const TargetRegisterClass FR64RegClass;
4344
  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
4345
  extern const TargetRegisterClass GR64_NOSPRegClass;
4346
  extern const TargetRegisterClass GR64_TCRegClass;
4347
  extern const TargetRegisterClass GR64_NOREXRegClass;
4348
  extern const TargetRegisterClass GR64_TCW64RegClass;
4349
  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
4350
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
4351
  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
4352
  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
4353
  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4354
  extern const TargetRegisterClass VK64RegClass;
4355
  extern const TargetRegisterClass VR64RegClass;
4356
  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
4357
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
4358
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
4359
  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
4360
  extern const TargetRegisterClass VK64WMRegClass;
4361
  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
4362
  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4363
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
4364
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
4365
  extern const TargetRegisterClass GR64_ABCDRegClass;
4366
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
4367
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
4368
  extern const TargetRegisterClass GR64_ADRegClass;
4369
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
4370
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
4371
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
4372
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
4373
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
4374
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
4375
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
4376
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
4377
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
4378
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
4379
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
4380
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
4381
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
4382
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
4383
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
4384
  extern const TargetRegisterClass RSTRegClass;
4385
  extern const TargetRegisterClass RFP80RegClass;
4386
  extern const TargetRegisterClass VR128XRegClass;
4387
  extern const TargetRegisterClass VR128RegClass;
4388
  extern const TargetRegisterClass VR128HRegClass;
4389
  extern const TargetRegisterClass VR128LRegClass;
4390
  extern const TargetRegisterClass BNDRRegClass;
4391
  extern const TargetRegisterClass VR256XRegClass;
4392
  extern const TargetRegisterClass VR256RegClass;
4393
  extern const TargetRegisterClass VR256HRegClass;
4394
  extern const TargetRegisterClass VR256LRegClass;
4395
  extern const TargetRegisterClass VR512RegClass;
4396
  extern const TargetRegisterClass VR512_with_sub_xmm_in_FR32RegClass;
4397
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128HRegClass;
4398
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128LRegClass;
4399
} // end namespace X86
4400
4401
} // end namespace llvm
4402
4403
#endif // GET_REGINFO_HEADER
4404
4405
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4406
|*                                                                            *|
4407
|* Target Register and Register Classes Information                           *|
4408
|*                                                                            *|
4409
|* Automatically generated file, do not edit!                                 *|
4410
|*                                                                            *|
4411
\*===----------------------------------------------------------------------===*/
4412
4413
4414
#ifdef GET_REGINFO_TARGET_DESC
4415
#undef GET_REGINFO_TARGET_DESC
4416
4417
namespace llvm {
4418
4419
extern const MCRegisterClass X86MCRegisterClasses[];
4420
4421
static const MVT::SimpleValueType VTLists[] = {
4422
  /* 0 */ MVT::i8, MVT::Other,
4423
  /* 2 */ MVT::i16, MVT::Other,
4424
  /* 4 */ MVT::i32, MVT::Other,
4425
  /* 6 */ MVT::i64, MVT::Other,
4426
  /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
4427
  /* 12 */ MVT::f64, MVT::Other,
4428
  /* 14 */ MVT::f80, MVT::Other,
4429
  /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
4430
  /* 24 */ MVT::v1i1, MVT::Other,
4431
  /* 26 */ MVT::v2i1, MVT::Other,
4432
  /* 28 */ MVT::v4i1, MVT::Other,
4433
  /* 30 */ MVT::v8i1, MVT::Other,
4434
  /* 32 */ MVT::v16i1, MVT::Other,
4435
  /* 34 */ MVT::v32i1, MVT::Other,
4436
  /* 36 */ MVT::v64i1, MVT::Other,
4437
  /* 38 */ MVT::v2i64, MVT::Other,
4438
  /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
4439
  /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4440
  /* 54 */ MVT::x86mmx, MVT::Other,
4441
};
4442
4443
static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_xmm", "sub_ymm", "" };
4444
4445
4446
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4447
  LaneBitmask::getAll(),
4448
  LaneBitmask(0x00000001), // sub_8bit
4449
  LaneBitmask(0x00000002), // sub_8bit_hi
4450
  LaneBitmask(0x00000004), // sub_8bit_hi_phony
4451
  LaneBitmask(0x00000007), // sub_16bit
4452
  LaneBitmask(0x00000008), // sub_16bit_hi
4453
  LaneBitmask(0x0000000F), // sub_32bit
4454
  LaneBitmask(0x00000010), // sub_xmm
4455
  LaneBitmask(0x00000010), // sub_ymm
4456
 };
4457
4458
4459
4460
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4461
  // Mode = 0 (Default)
4462
  { 8, 8, 8, VTLists+0 },    // GR8
4463
  { 8, 8, 8, VTLists+0 },    // GRH8
4464
  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
4465
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
4466
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
4467
  { 16, 16, 16, VTLists+2 },    // GRH16
4468
  { 16, 16, 16, VTLists+2 },    // GR16
4469
  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
4470
  { 16, 16, 16, VTLists+24 },    // VK1
4471
  { 16, 16, 16, VTLists+32 },    // VK16
4472
  { 16, 16, 16, VTLists+26 },    // VK2
4473
  { 16, 16, 16, VTLists+28 },    // VK4
4474
  { 16, 16, 16, VTLists+30 },    // VK8
4475
  { 16, 16, 16, VTLists+32 },    // VK16WM
4476
  { 16, 16, 16, VTLists+24 },    // VK1WM
4477
  { 16, 16, 16, VTLists+26 },    // VK2WM
4478
  { 16, 16, 16, VTLists+28 },    // VK4WM
4479
  { 16, 16, 16, VTLists+30 },    // VK8WM
4480
  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
4481
  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
4482
  { 16, 16, 16, VTLists+2 },    // FPCCR
4483
  { 32, 32, 32, VTLists+10 },    // FR32X
4484
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
4485
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
4486
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4487
  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
4488
  { 32, 32, 32, VTLists+10 },    // FR32
4489
  { 32, 32, 32, VTLists+4 },    // GR32
4490
  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
4491
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4492
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
4493
  { 32, 32, 32, VTLists+34 },    // VK32
4494
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
4495
  { 32, 32, 32, VTLists+10 },    // RFP32
4496
  { 32, 32, 32, VTLists+34 },    // VK32WM
4497
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
4498
  { 32, 32, 32, VTLists+4 },    // GR32_TC
4499
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_TC
4500
  { 32, 32, 32, VTLists+4 },    // GR32_AD
4501
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP
4502
  { 32, 32, 32, VTLists+4 },    // GR32_BSI
4503
  { 32, 32, 32, VTLists+4 },    // GR32_CB
4504
  { 32, 32, 32, VTLists+4 },    // GR32_DC
4505
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP
4506
  { 32, 32, 32, VTLists+4 },    // GR32_SIDI
4507
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4508
  { 32, 32, 32, VTLists+4 },    // CCR
4509
  { 32, 32, 32, VTLists+4 },    // DFCCR
4510
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_BSI
4511
  { 32, 32, 32, VTLists+4 },    // GR32_AD_and_GR32_DC
4512
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_DIBP
4513
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_TC
4514
  { 32, 32, 32, VTLists+4 },    // GR32_BSI_and_GR32_SIDI
4515
  { 32, 32, 32, VTLists+4 },    // GR32_CB_and_GR32_DC
4516
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP_and_GR32_SIDI
4517
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4518
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
4519
  { 64, 64, 32, VTLists+12 },    // RFP64
4520
  { 64, 64, 64, VTLists+12 },    // FR64X
4521
  { 64, 64, 64, VTLists+6 },    // GR64
4522
  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
4523
  { 64, 64, 64, VTLists+12 },    // FR64
4524
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
4525
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
4526
  { 64, 64, 64, VTLists+6 },    // GR64_TC
4527
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
4528
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
4529
  { 64, 64, 64, VTLists+6 },    // GR64_TC_with_sub_8bit
4530
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
4531
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_with_sub_8bit
4532
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
4533
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
4534
  { 64, 64, 64, VTLists+36 },    // VK64
4535
  { 64, 64, 64, VTLists+54 },    // VR64
4536
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
4537
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
4538
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
4539
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_and_GR64_TC_with_sub_8bit
4540
  { 64, 64, 64, VTLists+36 },    // VK64WM
4541
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4542
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4543
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_GR64_TC
4544
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
4545
  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
4546
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
4547
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4548
  { 64, 64, 64, VTLists+6 },    // GR64_AD
4549
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
4550
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP
4551
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI
4552
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB
4553
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DC
4554
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP
4555
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_SIDI
4556
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
4557
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4558
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
4559
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4560
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4561
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4562
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
4563
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4564
  { 80, 80, 32, VTLists+8 },    // RST
4565
  { 80, 80, 32, VTLists+14 },    // RFP80
4566
  { 128, 128, 128, VTLists+16 },    // VR128X
4567
  { 128, 128, 128, VTLists+16 },    // VR128
4568
  { 128, 128, 128, VTLists+16 },    // VR128H
4569
  { 128, 128, 128, VTLists+16 },    // VR128L
4570
  { 128, 128, 128, VTLists+38 },    // BNDR
4571
  { 256, 256, 256, VTLists+40 },    // VR256X
4572
  { 256, 256, 256, VTLists+40 },    // VR256
4573
  { 256, 256, 256, VTLists+40 },    // VR256H
4574
  { 256, 256, 256, VTLists+40 },    // VR256L
4575
  { 512, 512, 512, VTLists+47 },    // VR512
4576
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_FR32
4577
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128H
4578
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128L
4579
};
4580
4581
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4582
4583
static const uint32_t GR8SubClassMask[] = {
4584
  0x0000001d, 0x00000000, 0x00000000, 0x00000000, 
4585
  0x790800c0, 0xc0ff1ff9, 0xbf7bb4b8, 0x0000003f, // sub_8bit
4586
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4587
};
4588
4589
static const uint32_t GRH8SubClassMask[] = {
4590
  0x00000002, 0x00000000, 0x00000000, 0x00000000, 
4591
};
4592
4593
static const uint32_t GR8_NOREXSubClassMask[] = {
4594
  0x0000001c, 0x00000000, 0x00000000, 0x00000000, 
4595
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit
4596
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4597
};
4598
4599
static const uint32_t GR8_ABCD_HSubClassMask[] = {
4600
  0x00000008, 0x00000000, 0x00000000, 0x00000000, 
4601
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4602
};
4603
4604
static const uint32_t GR8_ABCD_LSubClassMask[] = {
4605
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
4606
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit
4607
};
4608
4609
static const uint32_t GRH16SubClassMask[] = {
4610
  0x00000020, 0x00000000, 0x00000000, 0x00000000, 
4611
};
4612
4613
static const uint32_t GR16SubClassMask[] = {
4614
  0x000800c0, 0x00000000, 0x00000000, 0x00000000, 
4615
  0x79000000, 0xc0ff1ff9, 0xbf7bb4b8, 0x0000003f, // sub_16bit
4616
};
4617
4618
static const uint32_t GR16_NOREXSubClassMask[] = {
4619
  0x00080080, 0x00000000, 0x00000000, 0x00000000, 
4620
  0x60000000, 0x00ff1ff9, 0xbf7b0480, 0x0000003f, // sub_16bit
4621
};
4622
4623
static const uint32_t VK1SubClassMask[] = {
4624
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4625
};
4626
4627
static const uint32_t VK16SubClassMask[] = {
4628
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4629
};
4630
4631
static const uint32_t VK2SubClassMask[] = {
4632
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4633
};
4634
4635
static const uint32_t VK4SubClassMask[] = {
4636
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4637
};
4638
4639
static const uint32_t VK8SubClassMask[] = {
4640
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4641
};
4642
4643
static const uint32_t VK16WMSubClassMask[] = {
4644
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4645
};
4646
4647
static const uint32_t VK1WMSubClassMask[] = {
4648
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4649
};
4650
4651
static const uint32_t VK2WMSubClassMask[] = {
4652
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4653
};
4654
4655
static const uint32_t VK4WMSubClassMask[] = {
4656
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4657
};
4658
4659
static const uint32_t VK8WMSubClassMask[] = {
4660
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4661
};
4662
4663
static const uint32_t SEGMENT_REGSubClassMask[] = {
4664
  0x00040000, 0x00000000, 0x00000000, 0x00000000, 
4665
};
4666
4667
static const uint32_t GR16_ABCDSubClassMask[] = {
4668
  0x00080000, 0x00000000, 0x00000000, 0x00000000, 
4669
  0x00000000, 0x00230668, 0x8c680000, 0x00000011, // sub_16bit
4670
};
4671
4672
static const uint32_t FPCCRSubClassMask[] = {
4673
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
4674
};
4675
4676
static const uint32_t FR32XSubClassMask[] = {
4677
  0x04200000, 0x24000000, 0x00000000, 0x00000f00, 
4678
  0x00000000, 0x00000000, 0x00000000, 0x001fe000, // sub_xmm
4679
};
4680
4681
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4682
  0x79c00000, 0x01ff3ff9, 0x40800000, 0x00000002, 
4683
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4684
};
4685
4686
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
4687
  0x58800000, 0x017f1ff9, 0x40000000, 0x00000000, 
4688
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4689
};
4690
4691
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
4692
  0x79000000, 0x00ff1ff9, 0x00000000, 0x00000002, 
4693
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4694
};
4695
4696
static const uint32_t DEBUG_REGSubClassMask[] = {
4697
  0x02000000, 0x00000000, 0x00000000, 0x00000000, 
4698
};
4699
4700
static const uint32_t FR32SubClassMask[] = {
4701
  0x04000000, 0x20000000, 0x00000000, 0x00000e00, 
4702
  0x00000000, 0x00000000, 0x00000000, 0x001dc000, // sub_xmm
4703
};
4704
4705
static const uint32_t GR32SubClassMask[] = {
4706
  0x58000000, 0x007f1ff9, 0x00000000, 0x00000000, 
4707
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4708
};
4709
4710
static const uint32_t GR32_NOSPSubClassMask[] = {
4711
  0x10000000, 0x00771f69, 0x00000000, 0x00000000, 
4712
  0x00000000, 0x80800000, 0xbe6a9410, 0x0000003b, // sub_32bit
4713
};
4714
4715
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4716
  0x60000000, 0x00ff1ff9, 0x00000000, 0x00000002, 
4717
  0x00000000, 0x00800000, 0xbf7b0480, 0x0000003f, // sub_32bit
4718
};
4719
4720
static const uint32_t GR32_NOREXSubClassMask[] = {
4721
  0x40000000, 0x007f1ff9, 0x00000000, 0x00000000, 
4722
  0x00000000, 0x00800000, 0xbf7b0480, 0x0000003f, // sub_32bit
4723
};
4724
4725
static const uint32_t VK32SubClassMask[] = {
4726
  0x80000000, 0x00000004, 0x00004100, 0x00000000, 
4727
};
4728
4729
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
4730
  0x00000000, 0x00771f69, 0x00000000, 0x00000000, 
4731
  0x00000000, 0x00800000, 0xbe6a0400, 0x0000003b, // sub_32bit
4732
};
4733
4734
static const uint32_t RFP32SubClassMask[] = {
4735
  0x00000000, 0x02000002, 0x00000000, 0x00000080, 
4736
};
4737
4738
static const uint32_t VK32WMSubClassMask[] = {
4739
  0x00000000, 0x00000004, 0x00004000, 0x00000000, 
4740
};
4741
4742
static const uint32_t GR32_ABCDSubClassMask[] = {
4743
  0x00000000, 0x00230668, 0x00000000, 0x00000000, 
4744
  0x00000000, 0x00000000, 0x8c680000, 0x00000011, // sub_32bit
4745
};
4746
4747
static const uint32_t GR32_TCSubClassMask[] = {
4748
  0x00000000, 0x002a0470, 0x00000000, 0x00000000, 
4749
  0x00000000, 0x00000000, 0x08700000, 0x00000015, // sub_32bit
4750
};
4751
4752
static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
4753
  0x00000000, 0x00220460, 0x00000000, 0x00000000, 
4754
  0x00000000, 0x00000000, 0x08600000, 0x00000011, // sub_32bit
4755
};
4756
4757
static const uint32_t GR32_ADSubClassMask[] = {
4758
  0x00000000, 0x00020040, 0x00000000, 0x00000000, 
4759
  0x00000000, 0x00000000, 0x00400000, 0x00000001, // sub_32bit
4760
};
4761
4762
static const uint32_t GR32_BPSPSubClassMask[] = {
4763
  0x00000000, 0x000c0080, 0x00000000, 0x00000000, 
4764
  0x00000000, 0x00800000, 0x01000000, 0x00000006, // sub_32bit
4765
};
4766
4767
static const uint32_t GR32_BSISubClassMask[] = {
4768
  0x00000000, 0x00110100, 0x00000000, 0x00000000, 
4769
  0x00000000, 0x00000000, 0x82000000, 0x00000008, // sub_32bit
4770
};
4771
4772
static const uint32_t GR32_CBSubClassMask[] = {
4773
  0x00000000, 0x00210200, 0x00000000, 0x00000000, 
4774
  0x00000000, 0x00000000, 0x84000000, 0x00000010, // sub_32bit
4775
};
4776
4777
static const uint32_t GR32_DCSubClassMask[] = {
4778
  0x00000000, 0x00220400, 0x00000000, 0x00000000, 
4779
  0x00000000, 0x00000000, 0x08000000, 0x00000011, // sub_32bit
4780
};
4781
4782
static const uint32_t GR32_DIBPSubClassMask[] = {
4783
  0x00000000, 0x00440800, 0x00000000, 0x00000000, 
4784
  0x00000000, 0x00800000, 0x10000000, 0x00000022, // sub_32bit
4785
};
4786
4787
static const uint32_t GR32_SIDISubClassMask[] = {
4788
  0x00000000, 0x00501000, 0x00000000, 0x00000000, 
4789
  0x00000000, 0x00000000, 0x20000000, 0x00000028, // sub_32bit
4790
};
4791
4792
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
4793
  0x00000000, 0x01802000, 0x40800000, 0x00000002, 
4794
};
4795
4796
static const uint32_t CCRSubClassMask[] = {
4797
  0x00000000, 0x00004000, 0x00000000, 0x00000000, 
4798
};
4799
4800
static const uint32_t DFCCRSubClassMask[] = {
4801
  0x00000000, 0x00008000, 0x00000000, 0x00000000, 
4802
};
4803
4804
static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
4805
  0x00000000, 0x00010000, 0x00000000, 0x00000000, 
4806
  0x00000000, 0x00000000, 0x80000000, 0x00000000, // sub_32bit
4807
};
4808
4809
static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
4810
  0x00000000, 0x00020000, 0x00000000, 0x00000000, 
4811
  0x00000000, 0x00000000, 0x00000000, 0x00000001, // sub_32bit
4812
};
4813
4814
static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
4815
  0x00000000, 0x00040000, 0x00000000, 0x00000000, 
4816
  0x00000000, 0x00800000, 0x00000000, 0x00000002, // sub_32bit
4817
};
4818
4819
static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
4820
  0x00000000, 0x00080000, 0x00000000, 0x00000000, 
4821
  0x00000000, 0x00000000, 0x00000000, 0x00000004, // sub_32bit
4822
};
4823
4824
static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
4825
  0x00000000, 0x00100000, 0x00000000, 0x00000000, 
4826
  0x00000000, 0x00000000, 0x00000000, 0x00000008, // sub_32bit
4827
};
4828
4829
static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
4830
  0x00000000, 0x00200000, 0x00000000, 0x00000000, 
4831
  0x00000000, 0x00000000, 0x00000000, 0x00000010, // sub_32bit
4832
};
4833
4834
static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
4835
  0x00000000, 0x00400000, 0x00000000, 0x00000000, 
4836
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32bit
4837
};
4838
4839
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
4840
  0x00000000, 0x00800000, 0x00000000, 0x00000002, 
4841
};
4842
4843
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
4844
  0x00000000, 0x01000000, 0x40000000, 0x00000000, 
4845
};
4846
4847
static const uint32_t RFP64SubClassMask[] = {
4848
  0x00000000, 0x02000000, 0x00000000, 0x00000080, 
4849
};
4850
4851
static const uint32_t FR64XSubClassMask[] = {
4852
  0x00000000, 0x24000000, 0x00000000, 0x00000f00, 
4853
  0x00000000, 0x00000000, 0x00000000, 0x001fe000, // sub_xmm
4854
};
4855
4856
static const uint32_t GR64SubClassMask[] = {
4857
  0x00000000, 0xc8000000, 0xffffbcff, 0x0000003f, 
4858
};
4859
4860
static const uint32_t CONTROL_REGSubClassMask[] = {
4861
  0x00000000, 0x10000000, 0x00000000, 0x00000000, 
4862
};
4863
4864
static const uint32_t FR64SubClassMask[] = {
4865
  0x00000000, 0x20000000, 0x00000000, 0x00000e00, 
4866
  0x00000000, 0x00000000, 0x00000000, 0x001dc000, // sub_xmm
4867
};
4868
4869
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
4870
  0x00000000, 0xc0000000, 0xbf7bb4b8, 0x0000003f, 
4871
};
4872
4873
static const uint32_t GR64_NOSPSubClassMask[] = {
4874
  0x00000000, 0x80000000, 0xbe6a9410, 0x0000003b, 
4875
};
4876
4877
static const uint32_t GR64_TCSubClassMask[] = {
4878
  0x00000000, 0x00000000, 0x6877a859, 0x0000003d, 
4879
};
4880
4881
static const uint32_t GR64_NOREXSubClassMask[] = {
4882
  0x00000000, 0x00000000, 0xffff0c82, 0x0000003f, 
4883
};
4884
4885
static const uint32_t GR64_TCW64SubClassMask[] = {
4886
  0x00000000, 0x00000000, 0x4874b064, 0x00000015, 
4887
};
4888
4889
static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
4890
  0x00000000, 0x00000000, 0x2873a018, 0x0000003d, 
4891
};
4892
4893
static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
4894
  0x00000000, 0x00000000, 0x28628010, 0x00000039, 
4895
};
4896
4897
static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
4898
  0x00000000, 0x00000000, 0x0870b020, 0x00000015, 
4899
};
4900
4901
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
4902
  0x00000000, 0x00000000, 0x4874a040, 0x00000015, 
4903
};
4904
4905
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4906
  0x00000000, 0x00000000, 0xbf7b0480, 0x0000003f, 
4907
};
4908
4909
static const uint32_t VK64SubClassMask[] = {
4910
  0x00000000, 0x00000000, 0x00004100, 0x00000000, 
4911
};
4912
4913
static const uint32_t VR64SubClassMask[] = {
4914
  0x00000000, 0x00000000, 0x00000200, 0x00000000, 
4915
};
4916
4917
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
4918
  0x00000000, 0x00000000, 0xbe6a0400, 0x0000003b, 
4919
};
4920
4921
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
4922
  0x00000000, 0x00000000, 0x68770800, 0x0000003d, 
4923
};
4924
4925
static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4926
  0x00000000, 0x00000000, 0x08609000, 0x00000011, 
4927
};
4928
4929
static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
4930
  0x00000000, 0x00000000, 0x0870a000, 0x00000015, 
4931
};
4932
4933
static const uint32_t VK64WMSubClassMask[] = {
4934
  0x00000000, 0x00000000, 0x00004000, 0x00000000, 
4935
};
4936
4937
static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4938
  0x00000000, 0x00000000, 0x08608000, 0x00000011, 
4939
};
4940
4941
static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4942
  0x00000000, 0x00000000, 0x28730000, 0x0000003d, 
4943
};
4944
4945
static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = {
4946
  0x00000000, 0x00000000, 0x28620000, 0x00000039, 
4947
};
4948
4949
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
4950
  0x00000000, 0x00000000, 0x48740000, 0x00000015, 
4951
};
4952
4953
static const uint32_t GR64_ABCDSubClassMask[] = {
4954
  0x00000000, 0x00000000, 0x8c680000, 0x00000011, 
4955
};
4956
4957
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
4958
  0x00000000, 0x00000000, 0x08700000, 0x00000015, 
4959
};
4960
4961
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
4962
  0x00000000, 0x00000000, 0x08600000, 0x00000011, 
4963
};
4964
4965
static const uint32_t GR64_ADSubClassMask[] = {
4966
  0x00000000, 0x00000000, 0x00400000, 0x00000001, 
4967
};
4968
4969
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4970
  0x00000000, 0x00000000, 0x40800000, 0x00000002, 
4971
};
4972
4973
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
4974
  0x00000000, 0x00000000, 0x01000000, 0x00000006, 
4975
};
4976
4977
static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
4978
  0x00000000, 0x00000000, 0x82000000, 0x00000008, 
4979
};
4980
4981
static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
4982
  0x00000000, 0x00000000, 0x84000000, 0x00000010, 
4983
};
4984
4985
static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
4986
  0x00000000, 0x00000000, 0x08000000, 0x00000011, 
4987
};
4988
4989
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
4990
  0x00000000, 0x00000000, 0x10000000, 0x00000022, 
4991
};
4992
4993
static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
4994
  0x00000000, 0x00000000, 0x20000000, 0x00000028, 
4995
};
4996
4997
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
4998
  0x00000000, 0x00000000, 0x40000000, 0x00000000, 
4999
};
5000
5001
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
5002
  0x00000000, 0x00000000, 0x80000000, 0x00000000, 
5003
};
5004
5005
static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
5006
  0x00000000, 0x00000000, 0x00000000, 0x00000001, 
5007
};
5008
5009
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5010
  0x00000000, 0x00000000, 0x00000000, 0x00000002, 
5011
};
5012
5013
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
5014
  0x00000000, 0x00000000, 0x00000000, 0x00000004, 
5015
};
5016
5017
static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
5018
  0x00000000, 0x00000000, 0x00000000, 0x00000008, 
5019
};
5020
5021
static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
5022
  0x00000000, 0x00000000, 0x00000000, 0x00000010, 
5023
};
5024
5025
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
5026
  0x00000000, 0x00000000, 0x00000000, 0x00000020, 
5027
};
5028
5029
static const uint32_t RSTSubClassMask[] = {
5030
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
5031
};
5032
5033
static const uint32_t RFP80SubClassMask[] = {
5034
  0x00000000, 0x00000000, 0x00000000, 0x00000080, 
5035
};
5036
5037
static const uint32_t VR128XSubClassMask[] = {
5038
  0x00000000, 0x00000000, 0x00000000, 0x00000f00, 
5039
  0x00000000, 0x00000000, 0x00000000, 0x001fe000, // sub_xmm
5040
};
5041
5042
static const uint32_t VR128SubClassMask[] = {
5043
  0x00000000, 0x00000000, 0x00000000, 0x00000e00, 
5044
  0x00000000, 0x00000000, 0x00000000, 0x001dc000, // sub_xmm
5045
};
5046
5047
static const uint32_t VR128HSubClassMask[] = {
5048
  0x00000000, 0x00000000, 0x00000000, 0x00000400, 
5049
  0x00000000, 0x00000000, 0x00000000, 0x00088000, // sub_xmm
5050
};
5051
5052
static const uint32_t VR128LSubClassMask[] = {
5053
  0x00000000, 0x00000000, 0x00000000, 0x00000800, 
5054
  0x00000000, 0x00000000, 0x00000000, 0x00110000, // sub_xmm
5055
};
5056
5057
static const uint32_t BNDRSubClassMask[] = {
5058
  0x00000000, 0x00000000, 0x00000000, 0x00001000, 
5059
};
5060
5061
static const uint32_t VR256XSubClassMask[] = {
5062
  0x00000000, 0x00000000, 0x00000000, 0x0001e000, 
5063
  0x00000000, 0x00000000, 0x00000000, 0x001e0000, // sub_ymm
5064
};
5065
5066
static const uint32_t VR256SubClassMask[] = {
5067
  0x00000000, 0x00000000, 0x00000000, 0x0001c000, 
5068
  0x00000000, 0x00000000, 0x00000000, 0x001c0000, // sub_ymm
5069
};
5070
5071
static const uint32_t VR256HSubClassMask[] = {
5072
  0x00000000, 0x00000000, 0x00000000, 0x00008000, 
5073
  0x00000000, 0x00000000, 0x00000000, 0x00080000, // sub_ymm
5074
};
5075
5076
static const uint32_t VR256LSubClassMask[] = {
5077
  0x00000000, 0x00000000, 0x00000000, 0x00010000, 
5078
  0x00000000, 0x00000000, 0x00000000, 0x00100000, // sub_ymm
5079
};
5080
5081
static const uint32_t VR512SubClassMask[] = {
5082
  0x00000000, 0x00000000, 0x00000000, 0x001e0000, 
5083
};
5084
5085
static const uint32_t VR512_with_sub_xmm_in_FR32SubClassMask[] = {
5086
  0x00000000, 0x00000000, 0x00000000, 0x001c0000, 
5087
};
5088
5089
static const uint32_t VR512_with_sub_xmm_in_VR128HSubClassMask[] = {
5090
  0x00000000, 0x00000000, 0x00000000, 0x00080000, 
5091
};
5092
5093
static const uint32_t VR512_with_sub_xmm_in_VR128LSubClassMask[] = {
5094
  0x00000000, 0x00000000, 0x00000000, 0x00100000, 
5095
};
5096
5097
static const uint16_t SuperRegIdxSeqs[] = {
5098
  /* 0 */ 1, 0,
5099
  /* 2 */ 1, 2, 0,
5100
  /* 5 */ 4, 0,
5101
  /* 7 */ 6, 0,
5102
  /* 9 */ 7, 0,
5103
  /* 11 */ 8, 0,
5104
};
5105
5106
static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
5107
  &X86::GR8RegClass,
5108
  nullptr
5109
};
5110
5111
static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
5112
  &X86::GR8RegClass,
5113
  &X86::GR8_NOREXRegClass,
5114
  nullptr
5115
};
5116
5117
static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
5118
  &X86::GR8RegClass,
5119
  &X86::GR8_NOREXRegClass,
5120
  nullptr
5121
};
5122
5123
static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
5124
  &X86::GR16RegClass,
5125
  nullptr
5126
};
5127
5128
static const TargetRegisterClass *const VK1Superclasses[] = {
5129
  &X86::VK16RegClass,
5130
  &X86::VK2RegClass,
5131
  &X86::VK4RegClass,
5132
  &X86::VK8RegClass,
5133
  nullptr
5134
};
5135
5136
static const TargetRegisterClass *const VK16Superclasses[] = {
5137
  &X86::VK1RegClass,
5138
  &X86::VK2RegClass,
5139
  &X86::VK4RegClass,
5140
  &X86::VK8RegClass,
5141
  nullptr
5142
};
5143
5144
static const TargetRegisterClass *const VK2Superclasses[] = {
5145
  &X86::VK1RegClass,
5146
  &X86::VK16RegClass,
5147
  &X86::VK4RegClass,
5148
  &X86::VK8RegClass,
5149
  nullptr
5150
};
5151
5152
static const TargetRegisterClass *const VK4Superclasses[] = {
5153
  &X86::VK1RegClass,
5154
  &X86::VK16RegClass,
5155
  &X86::VK2RegClass,
5156
  &X86::VK8RegClass,
5157
  nullptr
5158
};
5159
5160
static const TargetRegisterClass *const VK8Superclasses[] = {
5161
  &X86::VK1RegClass,
5162
  &X86::VK16RegClass,
5163
  &X86::VK2RegClass,
5164
  &X86::VK4RegClass,
5165
  nullptr
5166
};
5167
5168
static const TargetRegisterClass *const VK16WMSuperclasses[] = {
5169
  &X86::VK1RegClass,
5170
  &X86::VK16RegClass,
5171
  &X86::VK2RegClass,
5172
  &X86::VK4RegClass,
5173
  &X86::VK8RegClass,
5174
  &X86::VK1WMRegClass,
5175
  &X86::VK2WMRegClass,
5176
  &X86::VK4WMRegClass,
5177
  &X86::VK8WMRegClass,
5178
  nullptr
5179
};
5180
5181
static const TargetRegisterClass *const VK1WMSuperclasses[] = {
5182
  &X86::VK1RegClass,
5183
  &X86::VK16RegClass,
5184
  &X86::VK2RegClass,
5185
  &X86::VK4RegClass,
5186
  &X86::VK8RegClass,
5187
  &X86::VK16WMRegClass,
5188
  &X86::VK2WMRegClass,
5189
  &X86::VK4WMRegClass,
5190
  &X86::VK8WMRegClass,
5191
  nullptr
5192
};
5193
5194
static const TargetRegisterClass *const VK2WMSuperclasses[] = {
5195
  &X86::VK1RegClass,
5196
  &X86::VK16RegClass,
5197
  &X86::VK2RegClass,
5198
  &X86::VK4RegClass,
5199
  &X86::VK8RegClass,
5200
  &X86::VK16WMRegClass,
5201
  &X86::VK1WMRegClass,
5202
  &X86::VK4WMRegClass,
5203
  &X86::VK8WMRegClass,
5204
  nullptr
5205
};
5206
5207
static const TargetRegisterClass *const VK4WMSuperclasses[] = {
5208
  &X86::VK1RegClass,
5209
  &X86::VK16RegClass,
5210
  &X86::VK2RegClass,
5211
  &X86::VK4RegClass,
5212
  &X86::VK8RegClass,
5213
  &X86::VK16WMRegClass,
5214
  &X86::VK1WMRegClass,
5215
  &X86::VK2WMRegClass,
5216
  &X86::VK8WMRegClass,
5217
  nullptr
5218
};
5219
5220
static const TargetRegisterClass *const VK8WMSuperclasses[] = {
5221
  &X86::VK1RegClass,
5222
  &X86::VK16RegClass,
5223
  &X86::VK2RegClass,
5224
  &X86::VK4RegClass,
5225
  &X86::VK8RegClass,
5226
  &X86::VK16WMRegClass,
5227
  &X86::VK1WMRegClass,
5228
  &X86::VK2WMRegClass,
5229
  &X86::VK4WMRegClass,
5230
  nullptr
5231
};
5232
5233
static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
5234
  &X86::GR16RegClass,
5235
  &X86::GR16_NOREXRegClass,
5236
  nullptr
5237
};
5238
5239
static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
5240
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5241
  nullptr
5242
};
5243
5244
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
5245
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5246
  nullptr
5247
};
5248
5249
static const TargetRegisterClass *const FR32Superclasses[] = {
5250
  &X86::FR32XRegClass,
5251
  nullptr
5252
};
5253
5254
static const TargetRegisterClass *const GR32Superclasses[] = {
5255
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5256
  &X86::LOW32_ADDR_ACCESSRegClass,
5257
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5258
  nullptr
5259
};
5260
5261
static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
5262
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5263
  &X86::LOW32_ADDR_ACCESSRegClass,
5264
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5265
  &X86::GR32RegClass,
5266
  nullptr
5267
};
5268
5269
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5270
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5271
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5272
  nullptr
5273
};
5274
5275
static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
5276
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5277
  &X86::LOW32_ADDR_ACCESSRegClass,
5278
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5279
  &X86::GR32RegClass,
5280
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5281
  nullptr
5282
};
5283
5284
static const TargetRegisterClass *const VK32Superclasses[] = {
5285
  &X86::VK1RegClass,
5286
  &X86::VK16RegClass,
5287
  &X86::VK2RegClass,
5288
  &X86::VK4RegClass,
5289
  &X86::VK8RegClass,
5290
  nullptr
5291
};
5292
5293
static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
5294
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5295
  &X86::LOW32_ADDR_ACCESSRegClass,
5296
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5297
  &X86::GR32RegClass,
5298
  &X86::GR32_NOSPRegClass,
5299
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5300
  &X86::GR32_NOREXRegClass,
5301
  nullptr
5302
};
5303
5304
static const TargetRegisterClass *const VK32WMSuperclasses[] = {
5305
  &X86::VK1RegClass,
5306
  &X86::VK16RegClass,
5307
  &X86::VK2RegClass,
5308
  &X86::VK4RegClass,
5309
  &X86::VK8RegClass,
5310
  &X86::VK16WMRegClass,
5311
  &X86::VK1WMRegClass,
5312
  &X86::VK2WMRegClass,
5313
  &X86::VK4WMRegClass,
5314
  &X86::VK8WMRegClass,
5315
  &X86::VK32RegClass,
5316
  nullptr
5317
};
5318
5319
static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
5320
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5321
  &X86::LOW32_ADDR_ACCESSRegClass,
5322
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5323
  &X86::GR32RegClass,
5324
  &X86::GR32_NOSPRegClass,
5325
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5326
  &X86::GR32_NOREXRegClass,
5327
  &X86::GR32_NOREX_NOSPRegClass,
5328
  nullptr
5329
};
5330
5331
static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
5332
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5333
  &X86::LOW32_ADDR_ACCESSRegClass,
5334
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5335
  &X86::GR32RegClass,
5336
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5337
  &X86::GR32_NOREXRegClass,
5338
  nullptr
5339
};
5340
5341
static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
5342
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5343
  &X86::LOW32_ADDR_ACCESSRegClass,
5344
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5345
  &X86::GR32RegClass,
5346
  &X86::GR32_NOSPRegClass,
5347
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5348
  &X86::GR32_NOREXRegClass,
5349
  &X86::GR32_NOREX_NOSPRegClass,
5350
  &X86::GR32_ABCDRegClass,
5351
  &X86::GR32_TCRegClass,
5352
  nullptr
5353
};
5354
5355
static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
5356
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5357
  &X86::LOW32_ADDR_ACCESSRegClass,
5358
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5359
  &X86::GR32RegClass,
5360
  &X86::GR32_NOSPRegClass,
5361
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5362
  &X86::GR32_NOREXRegClass,
5363
  &X86::GR32_NOREX_NOSPRegClass,
5364
  &X86::GR32_ABCDRegClass,
5365
  &X86::GR32_TCRegClass,
5366
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5367
  nullptr
5368
};
5369
5370
static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
5371
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5372
  &X86::LOW32_ADDR_ACCESSRegClass,
5373
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5374
  &X86::GR32RegClass,
5375
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5376
  &X86::GR32_NOREXRegClass,
5377
  nullptr
5378
};
5379
5380
static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
5381
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5382
  &X86::LOW32_ADDR_ACCESSRegClass,
5383
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5384
  &X86::GR32RegClass,
5385
  &X86::GR32_NOSPRegClass,
5386
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5387
  &X86::GR32_NOREXRegClass,
5388
  &X86::GR32_NOREX_NOSPRegClass,
5389
  nullptr
5390
};
5391
5392
static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
5393
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5394
  &X86::LOW32_ADDR_ACCESSRegClass,
5395
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5396
  &X86::GR32RegClass,
5397
  &X86::GR32_NOSPRegClass,
5398
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5399
  &X86::GR32_NOREXRegClass,
5400
  &X86::GR32_NOREX_NOSPRegClass,
5401
  &X86::GR32_ABCDRegClass,
5402
  nullptr
5403
};
5404
5405
static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
5406
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5407
  &X86::LOW32_ADDR_ACCESSRegClass,
5408
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5409
  &X86::GR32RegClass,
5410
  &X86::GR32_NOSPRegClass,
5411
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5412
  &X86::GR32_NOREXRegClass,
5413
  &X86::GR32_NOREX_NOSPRegClass,
5414
  &X86::GR32_ABCDRegClass,
5415
  &X86::GR32_TCRegClass,
5416
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5417
  nullptr
5418
};
5419
5420
static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
5421
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5422
  &X86::LOW32_ADDR_ACCESSRegClass,
5423
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5424
  &X86::GR32RegClass,
5425
  &X86::GR32_NOSPRegClass,
5426
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5427
  &X86::GR32_NOREXRegClass,
5428
  &X86::GR32_NOREX_NOSPRegClass,
5429
  nullptr
5430
};
5431
5432
static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
5433
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5434
  &X86::LOW32_ADDR_ACCESSRegClass,
5435
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5436
  &X86::GR32RegClass,
5437
  &X86::GR32_NOSPRegClass,
5438
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5439
  &X86::GR32_NOREXRegClass,
5440
  &X86::GR32_NOREX_NOSPRegClass,
5441
  nullptr
5442
};
5443
5444
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
5445
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5446
  nullptr
5447
};
5448
5449
static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
5450
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5451
  &X86::LOW32_ADDR_ACCESSRegClass,
5452
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5453
  &X86::GR32RegClass,
5454
  &X86::GR32_NOSPRegClass,
5455
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5456
  &X86::GR32_NOREXRegClass,
5457
  &X86::GR32_NOREX_NOSPRegClass,
5458
  &X86::GR32_ABCDRegClass,
5459
  &X86::GR32_BSIRegClass,
5460
  &X86::GR32_CBRegClass,
5461
  nullptr
5462
};
5463
5464
static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
5465
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5466
  &X86::LOW32_ADDR_ACCESSRegClass,
5467
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5468
  &X86::GR32RegClass,
5469
  &X86::GR32_NOSPRegClass,
5470
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5471
  &X86::GR32_NOREXRegClass,
5472
  &X86::GR32_NOREX_NOSPRegClass,
5473
  &X86::GR32_ABCDRegClass,
5474
  &X86::GR32_TCRegClass,
5475
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5476
  &X86::GR32_ADRegClass,
5477
  &X86::GR32_DCRegClass,
5478
  nullptr
5479
};
5480
5481
static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
5482
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5483
  &X86::LOW32_ADDR_ACCESSRegClass,
5484
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5485
  &X86::GR32RegClass,
5486
  &X86::GR32_NOSPRegClass,
5487
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5488
  &X86::GR32_NOREXRegClass,
5489
  &X86::GR32_NOREX_NOSPRegClass,
5490
  &X86::GR32_BPSPRegClass,
5491
  &X86::GR32_DIBPRegClass,
5492
  nullptr
5493
};
5494
5495
static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
5496
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5497
  &X86::LOW32_ADDR_ACCESSRegClass,
5498
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5499
  &X86::GR32RegClass,
5500
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5501
  &X86::GR32_NOREXRegClass,
5502
  &X86::GR32_TCRegClass,
5503
  &X86::GR32_BPSPRegClass,
5504
  nullptr
5505
};
5506
5507
static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
5508
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5509
  &X86::LOW32_ADDR_ACCESSRegClass,
5510
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5511
  &X86::GR32RegClass,
5512
  &X86::GR32_NOSPRegClass,
5513
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5514
  &X86::GR32_NOREXRegClass,
5515
  &X86::GR32_NOREX_NOSPRegClass,
5516
  &X86::GR32_BSIRegClass,
5517
  &X86::GR32_SIDIRegClass,
5518
  nullptr
5519
};
5520
5521
static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
5522
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5523
  &X86::LOW32_ADDR_ACCESSRegClass,
5524
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5525
  &X86::GR32RegClass,
5526
  &X86::GR32_NOSPRegClass,
5527
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5528
  &X86::GR32_NOREXRegClass,
5529
  &X86::GR32_NOREX_NOSPRegClass,
5530
  &X86::GR32_ABCDRegClass,
5531
  &X86::GR32_TCRegClass,
5532
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5533
  &X86::GR32_CBRegClass,
5534
  &X86::GR32_DCRegClass,
5535
  nullptr
5536
};
5537
5538
static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
5539
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5540
  &X86::LOW32_ADDR_ACCESSRegClass,
5541
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5542
  &X86::GR32RegClass,
5543
  &X86::GR32_NOSPRegClass,
5544
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5545
  &X86::GR32_NOREXRegClass,
5546
  &X86::GR32_NOREX_NOSPRegClass,
5547
  &X86::GR32_DIBPRegClass,
5548
  &X86::GR32_SIDIRegClass,
5549
  nullptr
5550
};
5551
5552
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
5553
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5554
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5555
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5556
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5557
  nullptr
5558
};
5559
5560
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
5561
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5562
  &X86::LOW32_ADDR_ACCESSRegClass,
5563
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5564
  nullptr
5565
};
5566
5567
static const TargetRegisterClass *const RFP64Superclasses[] = {
5568
  &X86::RFP32RegClass,
5569
  nullptr
5570
};
5571
5572
static const TargetRegisterClass *const FR64XSuperclasses[] = {
5573
  &X86::FR32XRegClass,
5574
  nullptr
5575
};
5576
5577
static const TargetRegisterClass *const FR64Superclasses[] = {
5578
  &X86::FR32XRegClass,
5579
  &X86::FR32RegClass,
5580
  &X86::FR64XRegClass,
5581
  nullptr
5582
};
5583
5584
static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
5585
  &X86::GR64RegClass,
5586
  nullptr
5587
};
5588
5589
static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
5590
  &X86::GR64RegClass,
5591
  &X86::GR64_with_sub_8bitRegClass,
5592
  nullptr
5593
};
5594
5595
static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
5596
  &X86::GR64RegClass,
5597
  nullptr
5598
};
5599
5600
static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
5601
  &X86::GR64RegClass,
5602
  nullptr
5603
};
5604
5605
static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
5606
  &X86::GR64RegClass,
5607
  nullptr
5608
};
5609
5610
static const TargetRegisterC