Coverage Report

Created: 2018-09-19 20:53

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenRegisterInfo.inc
Line
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
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class MCRegisterClass;
16
extern const MCRegisterClass X86MCRegisterClasses[];
17
18
namespace X86 {
19
enum {
20
  NoRegister,
21
  AH = 1,
22
  AL = 2,
23
  AX = 3,
24
  BH = 4,
25
  BL = 5,
26
  BP = 6,
27
  BPH = 7,
28
  BPL = 8,
29
  BX = 9,
30
  CH = 10,
31
  CL = 11,
32
  CS = 12,
33
  CX = 13,
34
  DF = 14,
35
  DH = 15,
36
  DI = 16,
37
  DIH = 17,
38
  DIL = 18,
39
  DL = 19,
40
  DS = 20,
41
  DX = 21,
42
  EAX = 22,
43
  EBP = 23,
44
  EBX = 24,
45
  ECX = 25,
46
  EDI = 26,
47
  EDX = 27,
48
  EFLAGS = 28,
49
  EIP = 29,
50
  EIZ = 30,
51
  ES = 31,
52
  ESI = 32,
53
  ESP = 33,
54
  FPSW = 34,
55
  FS = 35,
56
  GS = 36,
57
  HAX = 37,
58
  HBP = 38,
59
  HBX = 39,
60
  HCX = 40,
61
  HDI = 41,
62
  HDX = 42,
63
  HIP = 43,
64
  HSI = 44,
65
  HSP = 45,
66
  IP = 46,
67
  RAX = 47,
68
  RBP = 48,
69
  RBX = 49,
70
  RCX = 50,
71
  RDI = 51,
72
  RDX = 52,
73
  RIP = 53,
74
  RIZ = 54,
75
  RSI = 55,
76
  RSP = 56,
77
  SI = 57,
78
  SIH = 58,
79
  SIL = 59,
80
  SP = 60,
81
  SPH = 61,
82
  SPL = 62,
83
  SS = 63,
84
  SSP = 64,
85
  BND0 = 65,
86
  BND1 = 66,
87
  BND2 = 67,
88
  BND3 = 68,
89
  CR0 = 69,
90
  CR1 = 70,
91
  CR2 = 71,
92
  CR3 = 72,
93
  CR4 = 73,
94
  CR5 = 74,
95
  CR6 = 75,
96
  CR7 = 76,
97
  CR8 = 77,
98
  CR9 = 78,
99
  CR10 = 79,
100
  CR11 = 80,
101
  CR12 = 81,
102
  CR13 = 82,
103
  CR14 = 83,
104
  CR15 = 84,
105
  DR0 = 85,
106
  DR1 = 86,
107
  DR2 = 87,
108
  DR3 = 88,
109
  DR4 = 89,
110
  DR5 = 90,
111
  DR6 = 91,
112
  DR7 = 92,
113
  DR8 = 93,
114
  DR9 = 94,
115
  DR10 = 95,
116
  DR11 = 96,
117
  DR12 = 97,
118
  DR13 = 98,
119
  DR14 = 99,
120
  DR15 = 100,
121
  FP0 = 101,
122
  FP1 = 102,
123
  FP2 = 103,
124
  FP3 = 104,
125
  FP4 = 105,
126
  FP5 = 106,
127
  FP6 = 107,
128
  FP7 = 108,
129
  K0 = 109,
130
  K1 = 110,
131
  K2 = 111,
132
  K3 = 112,
133
  K4 = 113,
134
  K5 = 114,
135
  K6 = 115,
136
  K7 = 116,
137
  MM0 = 117,
138
  MM1 = 118,
139
  MM2 = 119,
140
  MM3 = 120,
141
  MM4 = 121,
142
  MM5 = 122,
143
  MM6 = 123,
144
  MM7 = 124,
145
  R8 = 125,
146
  R9 = 126,
147
  R10 = 127,
148
  R11 = 128,
149
  R12 = 129,
150
  R13 = 130,
151
  R14 = 131,
152
  R15 = 132,
153
  ST0 = 133,
154
  ST1 = 134,
155
  ST2 = 135,
156
  ST3 = 136,
157
  ST4 = 137,
158
  ST5 = 138,
159
  ST6 = 139,
160
  ST7 = 140,
161
  XMM0 = 141,
162
  XMM1 = 142,
163
  XMM2 = 143,
164
  XMM3 = 144,
165
  XMM4 = 145,
166
  XMM5 = 146,
167
  XMM6 = 147,
168
  XMM7 = 148,
169
  XMM8 = 149,
170
  XMM9 = 150,
171
  XMM10 = 151,
172
  XMM11 = 152,
173
  XMM12 = 153,
174
  XMM13 = 154,
175
  XMM14 = 155,
176
  XMM15 = 156,
177
  XMM16 = 157,
178
  XMM17 = 158,
179
  XMM18 = 159,
180
  XMM19 = 160,
181
  XMM20 = 161,
182
  XMM21 = 162,
183
  XMM22 = 163,
184
  XMM23 = 164,
185
  XMM24 = 165,
186
  XMM25 = 166,
187
  XMM26 = 167,
188
  XMM27 = 168,
189
  XMM28 = 169,
190
  XMM29 = 170,
191
  XMM30 = 171,
192
  XMM31 = 172,
193
  YMM0 = 173,
194
  YMM1 = 174,
195
  YMM2 = 175,
196
  YMM3 = 176,
197
  YMM4 = 177,
198
  YMM5 = 178,
199
  YMM6 = 179,
200
  YMM7 = 180,
201
  YMM8 = 181,
202
  YMM9 = 182,
203
  YMM10 = 183,
204
  YMM11 = 184,
205
  YMM12 = 185,
206
  YMM13 = 186,
207
  YMM14 = 187,
208
  YMM15 = 188,
209
  YMM16 = 189,
210
  YMM17 = 190,
211
  YMM18 = 191,
212
  YMM19 = 192,
213
  YMM20 = 193,
214
  YMM21 = 194,
215
  YMM22 = 195,
216
  YMM23 = 196,
217
  YMM24 = 197,
218
  YMM25 = 198,
219
  YMM26 = 199,
220
  YMM27 = 200,
221
  YMM28 = 201,
222
  YMM29 = 202,
223
  YMM30 = 203,
224
  YMM31 = 204,
225
  ZMM0 = 205,
226
  ZMM1 = 206,
227
  ZMM2 = 207,
228
  ZMM3 = 208,
229
  ZMM4 = 209,
230
  ZMM5 = 210,
231
  ZMM6 = 211,
232
  ZMM7 = 212,
233
  ZMM8 = 213,
234
  ZMM9 = 214,
235
  ZMM10 = 215,
236
  ZMM11 = 216,
237
  ZMM12 = 217,
238
  ZMM13 = 218,
239
  ZMM14 = 219,
240
  ZMM15 = 220,
241
  ZMM16 = 221,
242
  ZMM17 = 222,
243
  ZMM18 = 223,
244
  ZMM19 = 224,
245
  ZMM20 = 225,
246
  ZMM21 = 226,
247
  ZMM22 = 227,
248
  ZMM23 = 228,
249
  ZMM24 = 229,
250
  ZMM25 = 230,
251
  ZMM26 = 231,
252
  ZMM27 = 232,
253
  ZMM28 = 233,
254
  ZMM29 = 234,
255
  ZMM30 = 235,
256
  ZMM31 = 236,
257
  R8B = 237,
258
  R9B = 238,
259
  R10B = 239,
260
  R11B = 240,
261
  R12B = 241,
262
  R13B = 242,
263
  R14B = 243,
264
  R15B = 244,
265
  R8BH = 245,
266
  R9BH = 246,
267
  R10BH = 247,
268
  R11BH = 248,
269
  R12BH = 249,
270
  R13BH = 250,
271
  R14BH = 251,
272
  R15BH = 252,
273
  R8D = 253,
274
  R9D = 254,
275
  R10D = 255,
276
  R11D = 256,
277
  R12D = 257,
278
  R13D = 258,
279
  R14D = 259,
280
  R15D = 260,
281
  R8W = 261,
282
  R9W = 262,
283
  R10W = 263,
284
  R11W = 264,
285
  R12W = 265,
286
  R13W = 266,
287
  R14W = 267,
288
  R15W = 268,
289
  R8WH = 269,
290
  R9WH = 270,
291
  R10WH = 271,
292
  R11WH = 272,
293
  R12WH = 273,
294
  R13WH = 274,
295
  R14WH = 275,
296
  R15WH = 276,
297
  NUM_TARGET_REGS   // 277
298
};
299
} // end namespace X86
300
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// Register classes
302
303
namespace X86 {
304
enum {
305
  GR8RegClassID = 0,
306
  GRH8RegClassID = 1,
307
  GR8_NOREXRegClassID = 2,
308
  GR8_ABCD_HRegClassID = 3,
309
  GR8_ABCD_LRegClassID = 4,
310
  GRH16RegClassID = 5,
311
  GR16RegClassID = 6,
312
  GR16_NOREXRegClassID = 7,
313
  VK1RegClassID = 8,
314
  VK16RegClassID = 9,
315
  VK2RegClassID = 10,
316
  VK4RegClassID = 11,
317
  VK8RegClassID = 12,
318
  VK16WMRegClassID = 13,
319
  VK1WMRegClassID = 14,
320
  VK2WMRegClassID = 15,
321
  VK4WMRegClassID = 16,
322
  VK8WMRegClassID = 17,
323
  SEGMENT_REGRegClassID = 18,
324
  GR16_ABCDRegClassID = 19,
325
  FPCCRRegClassID = 20,
326
  FR32XRegClassID = 21,
327
  LOW32_ADDR_ACCESS_RBPRegClassID = 22,
328
  LOW32_ADDR_ACCESSRegClassID = 23,
329
  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24,
330
  DEBUG_REGRegClassID = 25,
331
  FR32RegClassID = 26,
332
  GR32RegClassID = 27,
333
  GR32_NOSPRegClassID = 28,
334
  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29,
335
  GR32_NOREXRegClassID = 30,
336
  VK32RegClassID = 31,
337
  GR32_NOREX_NOSPRegClassID = 32,
338
  RFP32RegClassID = 33,
339
  VK32WMRegClassID = 34,
340
  GR32_ABCDRegClassID = 35,
341
  GR32_TCRegClassID = 36,
342
  GR32_ADRegClassID = 37,
343
  GR32_BPSPRegClassID = 38,
344
  GR32_BSIRegClassID = 39,
345
  GR32_CBRegClassID = 40,
346
  GR32_DCRegClassID = 41,
347
  GR32_DIBPRegClassID = 42,
348
  GR32_SIDIRegClassID = 43,
349
  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 44,
350
  CCRRegClassID = 45,
351
  DFCCRRegClassID = 46,
352
  GR32_ABCD_and_GR32_BSIRegClassID = 47,
353
  GR32_AD_and_GR32_DCRegClassID = 48,
354
  GR32_BPSP_and_GR32_DIBPRegClassID = 49,
355
  GR32_BSI_and_GR32_SIDIRegClassID = 50,
356
  GR32_CB_and_GR32_DCRegClassID = 51,
357
  GR32_DIBP_and_GR32_SIDIRegClassID = 52,
358
  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 53,
359
  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 54,
360
  RFP64RegClassID = 55,
361
  FR64XRegClassID = 56,
362
  GR64RegClassID = 57,
363
  CONTROL_REGRegClassID = 58,
364
  FR64RegClassID = 59,
365
  GR64_with_sub_8bitRegClassID = 60,
366
  GR64_NOSPRegClassID = 61,
367
  GR64_NOREXRegClassID = 62,
368
  GR64_TCRegClassID = 63,
369
  GR64_NOSP_and_GR64_TCRegClassID = 64,
370
  GR64_TCW64RegClassID = 65,
371
  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 66,
372
  VK64RegClassID = 67,
373
  VR64RegClassID = 68,
374
  GR64_NOREX_NOSPRegClassID = 69,
375
  GR64_NOSP_and_GR64_TCW64RegClassID = 70,
376
  GR64_TC_and_GR64_TCW64RegClassID = 71,
377
  VK64WMRegClassID = 72,
378
  GR64_NOREX_and_GR64_TCRegClassID = 73,
379
  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 74,
380
  GR64_NOREX_NOSP_and_GR64_TCRegClassID = 75,
381
  GR64_ABCDRegClassID = 76,
382
  GR64_NOREX_and_GR64_TCW64RegClassID = 77,
383
  GR64_with_sub_32bit_in_GR32_TCRegClassID = 78,
384
  GR64_ADRegClassID = 79,
385
  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 80,
386
  GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 81,
387
  GR64_with_sub_32bit_in_GR32_BSIRegClassID = 82,
388
  GR64_with_sub_32bit_in_GR32_CBRegClassID = 83,
389
  GR64_with_sub_32bit_in_GR32_DCRegClassID = 84,
390
  GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 85,
391
  GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 86,
392
  GR64_and_LOW32_ADDR_ACCESSRegClassID = 87,
393
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 88,
394
  GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 89,
395
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 90,
396
  GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 91,
397
  GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 92,
398
  GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 93,
399
  RSTRegClassID = 94,
400
  RFP80RegClassID = 95,
401
  VR128XRegClassID = 96,
402
  VR128RegClassID = 97,
403
  VR128HRegClassID = 98,
404
  VR128LRegClassID = 99,
405
  BNDRRegClassID = 100,
406
  VR256XRegClassID = 101,
407
  VR256RegClassID = 102,
408
  VR256HRegClassID = 103,
409
  VR256LRegClassID = 104,
410
  VR512RegClassID = 105,
411
  VR512_with_sub_xmm_in_FR32RegClassID = 106,
412
  VR512_with_sub_xmm_in_VR128HRegClassID = 107,
413
  VR512_with_sub_xmm_in_VR128LRegClassID = 108,
414
415
  };
416
} // end namespace X86
417
418
419
// Subregister indices
420
421
namespace X86 {
422
enum {
423
  NoSubRegister,
424
  sub_8bit, // 1
425
  sub_8bit_hi,  // 2
426
  sub_8bit_hi_phony,  // 3
427
  sub_16bit,  // 4
428
  sub_16bit_hi, // 5
429
  sub_32bit,  // 6
430
  sub_xmm,  // 7
431
  sub_ymm,  // 8
432
  NUM_TARGET_SUBREGS
433
};
434
} // end namespace X86
435
436
} // end namespace llvm
437
438
#endif // GET_REGINFO_ENUM
439
440
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
441
|*                                                                            *|
442
|* MC Register Information                                                    *|
443
|*                                                                            *|
444
|* Automatically generated file, do not edit!                                 *|
445
|*                                                                            *|
446
\*===----------------------------------------------------------------------===*/
447
448
449
#ifdef GET_REGINFO_MC_DESC
450
#undef GET_REGINFO_MC_DESC
451
452
namespace llvm {
453
454
extern const MCPhysReg X86RegDiffLists[] = {
455
  /* 0 */ 0, 1, 0,
456
  /* 3 */ 64875, 1, 1, 0,
457
  /* 7 */ 65259, 1, 1, 0,
458
  /* 11 */ 65397, 1, 1, 0,
459
  /* 15 */ 65466, 1, 1, 0,
460
  /* 19 */ 2, 1, 0,
461
  /* 22 */ 4, 1, 0,
462
  /* 25 */ 6, 1, 0,
463
  /* 28 */ 11, 1, 0,
464
  /* 31 */ 22, 1, 0,
465
  /* 34 */ 26, 1, 0,
466
  /* 37 */ 29, 1, 0,
467
  /* 40 */ 64851, 1, 0,
468
  /* 43 */ 10, 3, 0,
469
  /* 46 */ 4, 0,
470
  /* 48 */ 5, 0,
471
  /* 50 */ 65292, 1, 7, 0,
472
  /* 54 */ 65417, 1, 7, 0,
473
  /* 58 */ 10, 3, 7, 0,
474
  /* 62 */ 65512, 8, 0,
475
  /* 65 */ 65342, 1, 11, 0,
476
  /* 69 */ 65348, 1, 11, 0,
477
  /* 73 */ 65442, 1, 11, 0,
478
  /* 77 */ 65448, 1, 11, 0,
479
  /* 81 */ 12, 0,
480
  /* 83 */ 65342, 1, 14, 0,
481
  /* 87 */ 65348, 1, 14, 0,
482
  /* 91 */ 65442, 1, 14, 0,
483
  /* 95 */ 65448, 1, 14, 0,
484
  /* 99 */ 21, 0,
485
  /* 101 */ 22, 0,
486
  /* 103 */ 65534, 65509, 23, 0,
487
  /* 107 */ 65535, 65509, 23, 0,
488
  /* 111 */ 65534, 65511, 23, 0,
489
  /* 115 */ 65535, 65511, 23, 0,
490
  /* 119 */ 65524, 23, 0,
491
  /* 122 */ 128, 8, 65512, 8, 24, 0,
492
  /* 128 */ 65519, 24, 0,
493
  /* 131 */ 65522, 24, 0,
494
  /* 134 */ 65511, 65526, 2, 65535, 24, 0,
495
  /* 140 */ 2, 6, 25, 0,
496
  /* 144 */ 6, 6, 25, 0,
497
  /* 148 */ 65534, 10, 25, 0,
498
  /* 152 */ 65535, 10, 25, 0,
499
  /* 156 */ 2, 12, 25, 0,
500
  /* 160 */ 3, 12, 25, 0,
501
  /* 164 */ 4, 15, 25, 0,
502
  /* 168 */ 5, 15, 25, 0,
503
  /* 172 */ 65534, 17, 25, 0,
504
  /* 176 */ 65535, 17, 25, 0,
505
  /* 180 */ 1, 19, 25, 0,
506
  /* 184 */ 2, 19, 25, 0,
507
  /* 188 */ 65521, 25, 0,
508
  /* 191 */ 26, 0,
509
  /* 193 */ 65511, 65530, 65534, 65532, 27, 0,
510
  /* 199 */ 65511, 65524, 65534, 65535, 30, 0,
511
  /* 205 */ 65511, 65519, 2, 65535, 31, 0,
512
  /* 211 */ 32, 32, 0,
513
  /* 214 */ 65511, 65521, 65532, 65535, 35, 0,
514
  /* 220 */ 65511, 65517, 65535, 65535, 36, 0,
515
  /* 226 */ 64829, 0,
516
  /* 228 */ 64900, 0,
517
  /* 230 */ 64923, 0,
518
  /* 232 */ 65131, 0,
519
  /* 234 */ 65520, 65408, 0,
520
  /* 237 */ 16, 65528, 65408, 0,
521
  /* 241 */ 24, 65528, 65408, 0,
522
  /* 245 */ 65430, 0,
523
  /* 247 */ 65432, 0,
524
  /* 249 */ 65461, 0,
525
  /* 251 */ 65493, 0,
526
  /* 253 */ 65504, 65504, 0,
527
  /* 256 */ 65509, 0,
528
  /* 258 */ 65511, 0,
529
  /* 260 */ 65514, 0,
530
  /* 262 */ 65513, 27, 2, 65535, 65520, 0,
531
  /* 268 */ 65513, 25, 2, 65535, 65522, 0,
532
  /* 274 */ 65525, 0,
533
  /* 276 */ 65530, 0,
534
  /* 278 */ 65531, 0,
535
  /* 280 */ 65534, 65532, 0,
536
  /* 283 */ 65512, 17, 65533, 0,
537
  /* 287 */ 65534, 0,
538
  /* 289 */ 2, 65535, 0,
539
  /* 292 */ 65532, 65535, 0,
540
  /* 295 */ 65534, 65535, 0,
541
  /* 298 */ 65535, 65535, 0,
542
};
543
544
extern const LaneBitmask X86LaneMaskLists[] = {
545
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
546
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
547
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(),
548
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(),
549
  /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
550
  /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(),
551
  /* 19 */ LaneBitmask(0x00000010), LaneBitmask::getAll(),
552
};
553
554
extern const uint16_t X86SubRegIdxLists[] = {
555
  /* 0 */ 1, 2, 0,
556
  /* 3 */ 1, 3, 0,
557
  /* 6 */ 6, 4, 1, 2, 5, 0,
558
  /* 12 */ 6, 4, 1, 3, 5, 0,
559
  /* 18 */ 6, 4, 5, 0,
560
  /* 22 */ 8, 7, 0,
561
};
562
563
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
564
  { 65535, 65535 },
565
  { 0, 8 }, // sub_8bit
566
  { 8, 8 }, // sub_8bit_hi
567
  { 8, 8 }, // sub_8bit_hi_phony
568
  { 0, 16 },  // sub_16bit
569
  { 16, 16 }, // sub_16bit_hi
570
  { 0, 32 },  // sub_32bit
571
  { 0, 128 }, // sub_xmm
572
  { 0, 256 }, // sub_ymm
573
};
574
575
extern const char X86RegStrings[] = {
576
  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
577
  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
578
  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
579
  /* 18 */ 'C', 'R', '1', '0', 0,
580
  /* 23 */ 'D', 'R', '1', '0', 0,
581
  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
582
  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
583
  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
584
  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
585
  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
586
  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
587
  /* 64 */ 'B', 'N', 'D', '0', 0,
588
  /* 69 */ 'K', '0', 0,
589
  /* 72 */ 'X', 'M', 'M', '0', 0,
590
  /* 77 */ 'Y', 'M', 'M', '0', 0,
591
  /* 82 */ 'Z', 'M', 'M', '0', 0,
592
  /* 87 */ 'F', 'P', '0', 0,
593
  /* 91 */ 'C', 'R', '0', 0,
594
  /* 95 */ 'D', 'R', '0', 0,
595
  /* 99 */ 'S', 'T', '0', 0,
596
  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
597
  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
598
  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
599
  /* 121 */ 'C', 'R', '1', '1', 0,
600
  /* 126 */ 'D', 'R', '1', '1', 0,
601
  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
602
  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
603
  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
604
  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
605
  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
606
  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
607
  /* 167 */ 'B', 'N', 'D', '1', 0,
608
  /* 172 */ 'K', '1', 0,
609
  /* 175 */ 'X', 'M', 'M', '1', 0,
610
  /* 180 */ 'Y', 'M', 'M', '1', 0,
611
  /* 185 */ 'Z', 'M', 'M', '1', 0,
612
  /* 190 */ 'F', 'P', '1', 0,
613
  /* 194 */ 'C', 'R', '1', 0,
614
  /* 198 */ 'D', 'R', '1', 0,
615
  /* 202 */ 'S', 'T', '1', 0,
616
  /* 206 */ 'X', 'M', 'M', '1', '2', 0,
617
  /* 212 */ 'Y', 'M', 'M', '1', '2', 0,
618
  /* 218 */ 'Z', 'M', 'M', '1', '2', 0,
619
  /* 224 */ 'C', 'R', '1', '2', 0,
620
  /* 229 */ 'D', 'R', '1', '2', 0,
621
  /* 234 */ 'X', 'M', 'M', '2', '2', 0,
622
  /* 240 */ 'Y', 'M', 'M', '2', '2', 0,
623
  /* 246 */ 'Z', 'M', 'M', '2', '2', 0,
624
  /* 252 */ 'B', 'N', 'D', '2', 0,
625
  /* 257 */ 'K', '2', 0,
626
  /* 260 */ 'X', 'M', 'M', '2', 0,
627
  /* 265 */ 'Y', 'M', 'M', '2', 0,
628
  /* 270 */ 'Z', 'M', 'M', '2', 0,
629
  /* 275 */ 'F', 'P', '2', 0,
630
  /* 279 */ 'C', 'R', '2', 0,
631
  /* 283 */ 'D', 'R', '2', 0,
632
  /* 287 */ 'S', 'T', '2', 0,
633
  /* 291 */ 'X', 'M', 'M', '1', '3', 0,
634
  /* 297 */ 'Y', 'M', 'M', '1', '3', 0,
635
  /* 303 */ 'Z', 'M', 'M', '1', '3', 0,
636
  /* 309 */ 'C', 'R', '1', '3', 0,
637
  /* 314 */ 'D', 'R', '1', '3', 0,
638
  /* 319 */ 'X', 'M', 'M', '2', '3', 0,
639
  /* 325 */ 'Y', 'M', 'M', '2', '3', 0,
640
  /* 331 */ 'Z', 'M', 'M', '2', '3', 0,
641
  /* 337 */ 'B', 'N', 'D', '3', 0,
642
  /* 342 */ 'K', '3', 0,
643
  /* 345 */ 'X', 'M', 'M', '3', 0,
644
  /* 350 */ 'Y', 'M', 'M', '3', 0,
645
  /* 355 */ 'Z', 'M', 'M', '3', 0,
646
  /* 360 */ 'F', 'P', '3', 0,
647
  /* 364 */ 'C', 'R', '3', 0,
648
  /* 368 */ 'D', 'R', '3', 0,
649
  /* 372 */ 'S', 'T', '3', 0,
650
  /* 376 */ 'X', 'M', 'M', '1', '4', 0,
651
  /* 382 */ 'Y', 'M', 'M', '1', '4', 0,
652
  /* 388 */ 'Z', 'M', 'M', '1', '4', 0,
653
  /* 394 */ 'C', 'R', '1', '4', 0,
654
  /* 399 */ 'D', 'R', '1', '4', 0,
655
  /* 404 */ 'X', 'M', 'M', '2', '4', 0,
656
  /* 410 */ 'Y', 'M', 'M', '2', '4', 0,
657
  /* 416 */ 'Z', 'M', 'M', '2', '4', 0,
658
  /* 422 */ 'K', '4', 0,
659
  /* 425 */ 'X', 'M', 'M', '4', 0,
660
  /* 430 */ 'Y', 'M', 'M', '4', 0,
661
  /* 435 */ 'Z', 'M', 'M', '4', 0,
662
  /* 440 */ 'F', 'P', '4', 0,
663
  /* 444 */ 'C', 'R', '4', 0,
664
  /* 448 */ 'D', 'R', '4', 0,
665
  /* 452 */ 'S', 'T', '4', 0,
666
  /* 456 */ 'X', 'M', 'M', '1', '5', 0,
667
  /* 462 */ 'Y', 'M', 'M', '1', '5', 0,
668
  /* 468 */ 'Z', 'M', 'M', '1', '5', 0,
669
  /* 474 */ 'C', 'R', '1', '5', 0,
670
  /* 479 */ 'D', 'R', '1', '5', 0,
671
  /* 484 */ 'X', 'M', 'M', '2', '5', 0,
672
  /* 490 */ 'Y', 'M', 'M', '2', '5', 0,
673
  /* 496 */ 'Z', 'M', 'M', '2', '5', 0,
674
  /* 502 */ 'K', '5', 0,
675
  /* 505 */ 'X', 'M', 'M', '5', 0,
676
  /* 510 */ 'Y', 'M', 'M', '5', 0,
677
  /* 515 */ 'Z', 'M', 'M', '5', 0,
678
  /* 520 */ 'F', 'P', '5', 0,
679
  /* 524 */ 'C', 'R', '5', 0,
680
  /* 528 */ 'D', 'R', '5', 0,
681
  /* 532 */ 'S', 'T', '5', 0,
682
  /* 536 */ 'X', 'M', 'M', '1', '6', 0,
683
  /* 542 */ 'Y', 'M', 'M', '1', '6', 0,
684
  /* 548 */ 'Z', 'M', 'M', '1', '6', 0,
685
  /* 554 */ 'X', 'M', 'M', '2', '6', 0,
686
  /* 560 */ 'Y', 'M', 'M', '2', '6', 0,
687
  /* 566 */ 'Z', 'M', 'M', '2', '6', 0,
688
  /* 572 */ 'K', '6', 0,
689
  /* 575 */ 'X', 'M', 'M', '6', 0,
690
  /* 580 */ 'Y', 'M', 'M', '6', 0,
691
  /* 585 */ 'Z', 'M', 'M', '6', 0,
692
  /* 590 */ 'F', 'P', '6', 0,
693
  /* 594 */ 'C', 'R', '6', 0,
694
  /* 598 */ 'D', 'R', '6', 0,
695
  /* 602 */ 'S', 'T', '6', 0,
696
  /* 606 */ 'X', 'M', 'M', '1', '7', 0,
697
  /* 612 */ 'Y', 'M', 'M', '1', '7', 0,
698
  /* 618 */ 'Z', 'M', 'M', '1', '7', 0,
699
  /* 624 */ 'X', 'M', 'M', '2', '7', 0,
700
  /* 630 */ 'Y', 'M', 'M', '2', '7', 0,
701
  /* 636 */ 'Z', 'M', 'M', '2', '7', 0,
702
  /* 642 */ 'K', '7', 0,
703
  /* 645 */ 'X', 'M', 'M', '7', 0,
704
  /* 650 */ 'Y', 'M', 'M', '7', 0,
705
  /* 655 */ 'Z', 'M', 'M', '7', 0,
706
  /* 660 */ 'F', 'P', '7', 0,
707
  /* 664 */ 'C', 'R', '7', 0,
708
  /* 668 */ 'D', 'R', '7', 0,
709
  /* 672 */ 'S', 'T', '7', 0,
710
  /* 676 */ 'X', 'M', 'M', '1', '8', 0,
711
  /* 682 */ 'Y', 'M', 'M', '1', '8', 0,
712
  /* 688 */ 'Z', 'M', 'M', '1', '8', 0,
713
  /* 694 */ 'X', 'M', 'M', '2', '8', 0,
714
  /* 700 */ 'Y', 'M', 'M', '2', '8', 0,
715
  /* 706 */ 'Z', 'M', 'M', '2', '8', 0,
716
  /* 712 */ 'X', 'M', 'M', '8', 0,
717
  /* 717 */ 'Y', 'M', 'M', '8', 0,
718
  /* 722 */ 'Z', 'M', 'M', '8', 0,
719
  /* 727 */ 'C', 'R', '8', 0,
720
  /* 731 */ 'D', 'R', '8', 0,
721
  /* 735 */ 'X', 'M', 'M', '1', '9', 0,
722
  /* 741 */ 'Y', 'M', 'M', '1', '9', 0,
723
  /* 747 */ 'Z', 'M', 'M', '1', '9', 0,
724
  /* 753 */ 'X', 'M', 'M', '2', '9', 0,
725
  /* 759 */ 'Y', 'M', 'M', '2', '9', 0,
726
  /* 765 */ 'Z', 'M', 'M', '2', '9', 0,
727
  /* 771 */ 'X', 'M', 'M', '9', 0,
728
  /* 776 */ 'Y', 'M', 'M', '9', 0,
729
  /* 781 */ 'Z', 'M', 'M', '9', 0,
730
  /* 786 */ 'C', 'R', '9', 0,
731
  /* 790 */ 'D', 'R', '9', 0,
732
  /* 794 */ 'R', '1', '0', 'B', 0,
733
  /* 799 */ 'R', '1', '1', 'B', 0,
734
  /* 804 */ 'R', '1', '2', 'B', 0,
735
  /* 809 */ 'R', '1', '3', 'B', 0,
736
  /* 814 */ 'R', '1', '4', 'B', 0,
737
  /* 819 */ 'R', '1', '5', 'B', 0,
738
  /* 824 */ 'R', '8', 'B', 0,
739
  /* 828 */ 'R', '9', 'B', 0,
740
  /* 832 */ 'R', '1', '0', 'D', 0,
741
  /* 837 */ 'R', '1', '1', 'D', 0,
742
  /* 842 */ 'R', '1', '2', 'D', 0,
743
  /* 847 */ 'R', '1', '3', 'D', 0,
744
  /* 852 */ 'R', '1', '4', 'D', 0,
745
  /* 857 */ 'R', '1', '5', 'D', 0,
746
  /* 862 */ 'R', '8', 'D', 0,
747
  /* 866 */ 'R', '9', 'D', 0,
748
  /* 870 */ 'D', 'F', 0,
749
  /* 873 */ 'A', 'H', 0,
750
  /* 876 */ 'R', '1', '0', 'B', 'H', 0,
751
  /* 882 */ 'R', '1', '1', 'B', 'H', 0,
752
  /* 888 */ 'R', '1', '2', 'B', 'H', 0,
753
  /* 894 */ 'R', '1', '3', 'B', 'H', 0,
754
  /* 900 */ 'R', '1', '4', 'B', 'H', 0,
755
  /* 906 */ 'R', '1', '5', 'B', 'H', 0,
756
  /* 912 */ 'R', '8', 'B', 'H', 0,
757
  /* 917 */ 'R', '9', 'B', 'H', 0,
758
  /* 922 */ 'C', 'H', 0,
759
  /* 925 */ 'D', 'H', 0,
760
  /* 928 */ 'D', 'I', 'H', 0,
761
  /* 932 */ 'S', 'I', 'H', 0,
762
  /* 936 */ 'B', 'P', 'H', 0,
763
  /* 940 */ 'S', 'P', 'H', 0,
764
  /* 944 */ 'R', '1', '0', 'W', 'H', 0,
765
  /* 950 */ 'R', '1', '1', 'W', 'H', 0,
766
  /* 956 */ 'R', '1', '2', 'W', 'H', 0,
767
  /* 962 */ 'R', '1', '3', 'W', 'H', 0,
768
  /* 968 */ 'R', '1', '4', 'W', 'H', 0,
769
  /* 974 */ 'R', '1', '5', 'W', 'H', 0,
770
  /* 980 */ 'R', '8', 'W', 'H', 0,
771
  /* 985 */ 'R', '9', 'W', 'H', 0,
772
  /* 990 */ 'E', 'D', 'I', 0,
773
  /* 994 */ 'H', 'D', 'I', 0,
774
  /* 998 */ 'R', 'D', 'I', 0,
775
  /* 1002 */ 'E', 'S', 'I', 0,
776
  /* 1006 */ 'H', 'S', 'I', 0,
777
  /* 1010 */ 'R', 'S', 'I', 0,
778
  /* 1014 */ 'A', 'L', 0,
779
  /* 1017 */ 'B', 'L', 0,
780
  /* 1020 */ 'C', 'L', 0,
781
  /* 1023 */ 'D', 'L', 0,
782
  /* 1026 */ 'D', 'I', 'L', 0,
783
  /* 1030 */ 'S', 'I', 'L', 0,
784
  /* 1034 */ 'B', 'P', 'L', 0,
785
  /* 1038 */ 'S', 'P', 'L', 0,
786
  /* 1042 */ 'E', 'B', 'P', 0,
787
  /* 1046 */ 'H', 'B', 'P', 0,
788
  /* 1050 */ 'R', 'B', 'P', 0,
789
  /* 1054 */ 'E', 'I', 'P', 0,
790
  /* 1058 */ 'H', 'I', 'P', 0,
791
  /* 1062 */ 'R', 'I', 'P', 0,
792
  /* 1066 */ 'E', 'S', 'P', 0,
793
  /* 1070 */ 'H', 'S', 'P', 0,
794
  /* 1074 */ 'R', 'S', 'P', 0,
795
  /* 1078 */ 'S', 'S', 'P', 0,
796
  /* 1082 */ 'C', 'S', 0,
797
  /* 1085 */ 'D', 'S', 0,
798
  /* 1088 */ 'E', 'S', 0,
799
  /* 1091 */ 'F', 'S', 0,
800
  /* 1094 */ 'E', 'F', 'L', 'A', 'G', 'S', 0,
801
  /* 1101 */ 'S', 'S', 0,
802
  /* 1104 */ 'R', '1', '0', 'W', 0,
803
  /* 1109 */ 'R', '1', '1', 'W', 0,
804
  /* 1114 */ 'R', '1', '2', 'W', 0,
805
  /* 1119 */ 'R', '1', '3', 'W', 0,
806
  /* 1124 */ 'R', '1', '4', 'W', 0,
807
  /* 1129 */ 'R', '1', '5', 'W', 0,
808
  /* 1134 */ 'R', '8', 'W', 0,
809
  /* 1138 */ 'R', '9', 'W', 0,
810
  /* 1142 */ 'F', 'P', 'S', 'W', 0,
811
  /* 1147 */ 'E', 'A', 'X', 0,
812
  /* 1151 */ 'H', 'A', 'X', 0,
813
  /* 1155 */ 'R', 'A', 'X', 0,
814
  /* 1159 */ 'E', 'B', 'X', 0,
815
  /* 1163 */ 'H', 'B', 'X', 0,
816
  /* 1167 */ 'R', 'B', 'X', 0,
817
  /* 1171 */ 'E', 'C', 'X', 0,
818
  /* 1175 */ 'H', 'C', 'X', 0,
819
  /* 1179 */ 'R', 'C', 'X', 0,
820
  /* 1183 */ 'E', 'D', 'X', 0,
821
  /* 1187 */ 'H', 'D', 'X', 0,
822
  /* 1191 */ 'R', 'D', 'X', 0,
823
  /* 1195 */ 'E', 'I', 'Z', 0,
824
  /* 1199 */ 'R', 'I', 'Z', 0,
825
};
826
827
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
828
  { 5, 0, 0, 0, 0, 0 },
829
  { 873, 2, 184, 2, 4641, 0 },
830
  { 1014, 2, 180, 2, 4641, 0 },
831
  { 1148, 298, 181, 0, 0, 2 },
832
  { 879, 2, 168, 2, 4593, 0 },
833
  { 1017, 2, 164, 2, 4593, 0 },
834
  { 1043, 289, 173, 3, 352, 5 },
835
  { 936, 2, 176, 2, 768, 0 },
836
  { 1034, 2, 172, 2, 736, 0 },
837
  { 1160, 292, 165, 0, 304, 2 },
838
  { 922, 2, 160, 2, 4497, 0 },
839
  { 1020, 2, 156, 2, 4497, 0 },
840
  { 1082, 2, 2, 2, 4497, 0 },
841
  { 1172, 295, 157, 0, 400, 2 },
842
  { 870, 2, 2, 2, 4449, 0 },
843
  { 925, 2, 144, 2, 4449, 0 },
844
  { 991, 289, 149, 3, 448, 5 },
845
  { 928, 2, 152, 2, 1296, 0 },
846
  { 1026, 2, 148, 2, 4130, 0 },
847
  { 1023, 2, 140, 2, 4417, 0 },
848
  { 1085, 2, 2, 2, 4417, 0 },
849
  { 1184, 280, 141, 0, 688, 2 },
850
  { 1147, 221, 142, 7, 1524, 8 },
851
  { 1042, 206, 142, 13, 1236, 12 },
852
  { 1159, 215, 142, 7, 1460, 8 },
853
  { 1171, 200, 142, 7, 1172, 8 },
854
  { 990, 135, 142, 13, 869, 12 },
855
  { 1183, 194, 142, 7, 928, 8 },
856
  { 1094, 2, 2, 2, 1584, 0 },
857
  { 1054, 284, 126, 19, 496, 16 },
858
  { 1195, 2, 2, 2, 4417, 0 },
859
  { 1088, 2, 2, 2, 4417, 0 },
860
  { 1002, 269, 105, 13, 243, 12 },
861
  { 1066, 263, 105, 13, 243, 12 },
862
  { 1142, 2, 2, 2, 4593, 0 },
863
  { 1091, 2, 2, 2, 4593, 0 },
864
  { 1098, 2, 2, 2, 4593, 0 },
865
  { 1151, 2, 188, 2, 4161, 0 },
866
  { 1046, 2, 188, 2, 4161, 0 },
867
  { 1163, 2, 188, 2, 4161, 0 },
868
  { 1175, 2, 188, 2, 4161, 0 },
869
  { 994, 2, 188, 2, 4161, 0 },
870
  { 1187, 2, 188, 2, 4161, 0 },
871
  { 1058, 2, 131, 2, 3923, 0 },
872
  { 1006, 2, 119, 2, 3955, 0 },
873
  { 1070, 2, 119, 2, 3955, 0 },
874
  { 1055, 2, 128, 2, 1616, 0 },
875
  { 1155, 220, 2, 6, 1396, 8 },
876
  { 1050, 205, 2, 12, 1108, 12 },
877
  { 1167, 214, 2, 6, 1332, 8 },
878
  { 1179, 199, 2, 6, 1044, 8 },
879
  { 998, 134, 2, 12, 805, 12 },
880
  { 1191, 193, 2, 6, 928, 8 },
881
  { 1062, 283, 2, 18, 496, 16 },
882
  { 1199, 2, 2, 2, 3488, 0 },
883
  { 1010, 268, 2, 12, 179, 12 },
884
  { 1074, 262, 2, 12, 179, 12 },
885
  { 1003, 289, 112, 3, 544, 5 },
886
  { 932, 2, 115, 2, 3152, 0 },
887
  { 1030, 2, 111, 2, 3056, 0 },
888
  { 1067, 289, 104, 3, 592, 5 },
889
  { 940, 2, 107, 2, 3248, 0 },
890
  { 1038, 2, 103, 2, 3719, 0 },
891
  { 1101, 2, 2, 2, 4097, 0 },
892
  { 1078, 2, 2, 2, 4097, 0 },
893
  { 64, 2, 2, 2, 4097, 0 },
894
  { 167, 2, 2, 2, 4097, 0 },
895
  { 252, 2, 2, 2, 4097, 0 },
896
  { 337, 2, 2, 2, 4097, 0 },
897
  { 91, 2, 2, 2, 4097, 0 },
898
  { 194, 2, 2, 2, 4097, 0 },
899
  { 279, 2, 2, 2, 4097, 0 },
900
  { 364, 2, 2, 2, 4097, 0 },
901
  { 444, 2, 2, 2, 4097, 0 },
902
  { 524, 2, 2, 2, 4097, 0 },
903
  { 594, 2, 2, 2, 4097, 0 },
904
  { 664, 2, 2, 2, 4097, 0 },
905
  { 727, 2, 2, 2, 4097, 0 },
906
  { 786, 2, 2, 2, 4097, 0 },
907
  { 18, 2, 2, 2, 4097, 0 },
908
  { 121, 2, 2, 2, 4097, 0 },
909
  { 224, 2, 2, 2, 4097, 0 },
910
  { 309, 2, 2, 2, 4097, 0 },
911
  { 394, 2, 2, 2, 4097, 0 },
912
  { 474, 2, 2, 2, 4097, 0 },
913
  { 95, 2, 2, 2, 4097, 0 },
914
  { 198, 2, 2, 2, 4097, 0 },
915
  { 283, 2, 2, 2, 4097, 0 },
916
  { 368, 2, 2, 2, 4097, 0 },
917
  { 448, 2, 2, 2, 4097, 0 },
918
  { 528, 2, 2, 2, 4097, 0 },
919
  { 598, 2, 2, 2, 4097, 0 },
920
  { 668, 2, 2, 2, 4097, 0 },
921
  { 731, 2, 2, 2, 4097, 0 },
922
  { 790, 2, 2, 2, 4097, 0 },
923
  { 23, 2, 2, 2, 4097, 0 },
924
  { 126, 2, 2, 2, 4097, 0 },
925
  { 229, 2, 2, 2, 4097, 0 },
926
  { 314, 2, 2, 2, 4097, 0 },
927
  { 399, 2, 2, 2, 4097, 0 },
928
  { 479, 2, 2, 2, 4097, 0 },
929
  { 87, 2, 2, 2, 4097, 0 },
930
  { 190, 2, 2, 2, 4097, 0 },
931
  { 275, 2, 2, 2, 4097, 0 },
932
  { 360, 2, 2, 2, 4097, 0 },
933
  { 440, 2, 2, 2, 4097, 0 },
934
  { 520, 2, 2, 2, 4097, 0 },
935
  { 590, 2, 2, 2, 4097, 0 },
936
  { 660, 2, 2, 2, 4097, 0 },
937
  { 69, 2, 2, 2, 4097, 0 },
938
  { 172, 2, 2, 2, 4097, 0 },
939
  { 257, 2, 2, 2, 4097, 0 },
940
  { 342, 2, 2, 2, 4097, 0 },
941
  { 422, 2, 2, 2, 4097, 0 },
942
  { 502, 2, 2, 2, 4097, 0 },
943
  { 572, 2, 2, 2, 4097, 0 },
944
  { 642, 2, 2, 2, 4097, 0 },
945
  { 73, 2, 2, 2, 4097, 0 },
946
  { 176, 2, 2, 2, 4097, 0 },
947
  { 261, 2, 2, 2, 4097, 0 },
948
  { 346, 2, 2, 2, 4097, 0 },
949
  { 426, 2, 2, 2, 4097, 0 },
950
  { 506, 2, 2, 2, 4097, 0 },
951
  { 576, 2, 2, 2, 4097, 0 },
952
  { 646, 2, 2, 2, 4097, 0 },
953
  { 728, 122, 2, 12, 115, 12 },
954
  { 787, 122, 2, 12, 115, 12 },
955
  { 19, 122, 2, 12, 115, 12 },
956
  { 122, 122, 2, 12, 115, 12 },
957
  { 225, 122, 2, 12, 115, 12 },
958
  { 310, 122, 2, 12, 115, 12 },
959
  { 395, 122, 2, 12, 115, 12 },
960
  { 475, 122, 2, 12, 115, 12 },
961
  { 99, 2, 2, 2, 4385, 0 },
962
  { 202, 2, 2, 2, 4385, 0 },
963
  { 287, 2, 2, 2, 4385, 0 },
964
  { 372, 2, 2, 2, 4385, 0 },
965
  { 452, 2, 2, 2, 4385, 0 },
966
  { 532, 2, 2, 2, 4385, 0 },
967
  { 602, 2, 2, 2, 4385, 0 },
968
  { 672, 2, 2, 2, 4385, 0 },
969
  { 72, 2, 211, 2, 4385, 0 },
970
  { 175, 2, 211, 2, 4385, 0 },
971
  { 260, 2, 211, 2, 4385, 0 },
972
  { 345, 2, 211, 2, 4385, 0 },
973
  { 425, 2, 211, 2, 4385, 0 },
974
  { 505, 2, 211, 2, 4385, 0 },
975
  { 575, 2, 211, 2, 4385, 0 },
976
  { 645, 2, 211, 2, 4385, 0 },
977
  { 712, 2, 211, 2, 4385, 0 },
978
  { 771, 2, 211, 2, 4385, 0 },
979
  { 0, 2, 211, 2, 4385, 0 },
980
  { 103, 2, 211, 2, 4385, 0 },
981
  { 206, 2, 211, 2, 4385, 0 },
982
  { 291, 2, 211, 2, 4385, 0 },
983
  { 376, 2, 211, 2, 4385, 0 },
984
  { 456, 2, 211, 2, 4385, 0 },
985
  { 536, 2, 211, 2, 4385, 0 },
986
  { 606, 2, 211, 2, 4385, 0 },
987
  { 676, 2, 211, 2, 4385, 0 },
988
  { 735, 2, 211, 2, 4385, 0 },
989
  { 28, 2, 211, 2, 4385, 0 },
990
  { 131, 2, 211, 2, 4385, 0 },
991
  { 234, 2, 211, 2, 4385, 0 },
992
  { 319, 2, 211, 2, 4385, 0 },
993
  { 404, 2, 211, 2, 4385, 0 },
994
  { 484, 2, 211, 2, 4385, 0 },
995
  { 554, 2, 211, 2, 4385, 0 },
996
  { 624, 2, 211, 2, 4385, 0 },
997
  { 694, 2, 211, 2, 4385, 0 },
998
  { 753, 2, 211, 2, 4385, 0 },
999
  { 46, 2, 211, 2, 4385, 0 },
1000
  { 149, 2, 211, 2, 4385, 0 },
1001
  { 77, 254, 212, 23, 4017, 19 },
1002
  { 180, 254, 212, 23, 4017, 19 },
1003
  { 265, 254, 212, 23, 4017, 19 },
1004
  { 350, 254, 212, 23, 4017, 19 },
1005
  { 430, 254, 212, 23, 4017, 19 },
1006
  { 510, 254, 212, 23, 4017, 19 },
1007
  { 580, 254, 212, 23, 4017, 19 },
1008
  { 650, 254, 212, 23, 4017, 19 },
1009
  { 717, 254, 212, 23, 4017, 19 },
1010
  { 776, 254, 212, 23, 4017, 19 },
1011
  { 6, 254, 212, 23, 4017, 19 },
1012
  { 109, 254, 212, 23, 4017, 19 },
1013
  { 212, 254, 212, 23, 4017, 19 },
1014
  { 297, 254, 212, 23, 4017, 19 },
1015
  { 382, 254, 212, 23, 4017, 19 },
1016
  { 462, 254, 212, 23, 4017, 19 },
1017
  { 542, 254, 212, 23, 4017, 19 },
1018
  { 612, 254, 212, 23, 4017, 19 },
1019
  { 682, 254, 212, 23, 4017, 19 },
1020
  { 741, 254, 212, 23, 4017, 19 },
1021
  { 34, 254, 212, 23, 4017, 19 },
1022
  { 137, 254, 212, 23, 4017, 19 },
1023
  { 240, 254, 212, 23, 4017, 19 },
1024
  { 325, 254, 212, 23, 4017, 19 },
1025
  { 410, 254, 212, 23, 4017, 19 },
1026
  { 490, 254, 212, 23, 4017, 19 },
1027
  { 560, 254, 212, 23, 4017, 19 },
1028
  { 630, 254, 212, 23, 4017, 19 },
1029
  { 700, 254, 212, 23, 4017, 19 },
1030
  { 759, 254, 212, 23, 4017, 19 },
1031
  { 52, 254, 212, 23, 4017, 19 },
1032
  { 155, 254, 212, 23, 4017, 19 },
1033
  { 82, 253, 2, 22, 3985, 19 },
1034
  { 185, 253, 2, 22, 3985, 19 },
1035
  { 270, 253, 2, 22, 3985, 19 },
1036
  { 355, 253, 2, 22, 3985, 19 },
1037
  { 435, 253, 2, 22, 3985, 19 },
1038
  { 515, 253, 2, 22, 3985, 19 },
1039
  { 585, 253, 2, 22, 3985, 19 },
1040
  { 655, 253, 2, 22, 3985, 19 },
1041
  { 722, 253, 2, 22, 3985, 19 },
1042
  { 781, 253, 2, 22, 3985, 19 },
1043
  { 12, 253, 2, 22, 3985, 19 },
1044
  { 115, 253, 2, 22, 3985, 19 },
1045
  { 218, 253, 2, 22, 3985, 19 },
1046
  { 303, 253, 2, 22, 3985, 19 },
1047
  { 388, 253, 2, 22, 3985, 19 },
1048
  { 468, 253, 2, 22, 3985, 19 },
1049
  { 548, 253, 2, 22, 3985, 19 },
1050
  { 618, 253, 2, 22, 3985, 19 },
1051
  { 688, 253, 2, 22, 3985, 19 },
1052
  { 747, 253, 2, 22, 3985, 19 },
1053
  { 40, 253, 2, 22, 3985, 19 },
1054
  { 143, 253, 2, 22, 3985, 19 },
1055
  { 246, 253, 2, 22, 3985, 19 },
1056
  { 331, 253, 2, 22, 3985, 19 },
1057
  { 416, 253, 2, 22, 3985, 19 },
1058
  { 496, 253, 2, 22, 3985, 19 },
1059
  { 566, 253, 2, 22, 3985, 19 },
1060
  { 636, 253, 2, 22, 3985, 19 },
1061
  { 706, 253, 2, 22, 3985, 19 },
1062
  { 765, 253, 2, 22, 3985, 19 },
1063
  { 58, 253, 2, 22, 3985, 19 },
1064
  { 161, 253, 2, 22, 3985, 19 },
1065
  { 824, 2, 241, 2, 3683, 0 },
1066
  { 828, 2, 241, 2, 3683, 0 },
1067
  { 794, 2, 241, 2, 3683, 0 },
1068
  { 799, 2, 241, 2, 3683, 0 },
1069
  { 804, 2, 241, 2, 3683, 0 },
1070
  { 809, 2, 241, 2, 3683, 0 },
1071
  { 814, 2, 241, 2, 3683, 0 },
1072
  { 819, 2, 241, 2, 3683, 0 },
1073
  { 912, 2, 237, 2, 3651, 0 },
1074
  { 917, 2, 237, 2, 3651, 0 },
1075
  { 876, 2, 237, 2, 3651, 0 },
1076
  { 882, 2, 237, 2, 3651, 0 },
1077
  { 888, 2, 237, 2, 3651, 0 },
1078
  { 894, 2, 237, 2, 3651, 0 },
1079
  { 900, 2, 237, 2, 3651, 0 },
1080
  { 906, 2, 237, 2, 3651, 0 },
1081
  { 862, 123, 235, 13, 51, 12 },
1082
  { 866, 123, 235, 13, 51, 12 },
1083
  { 832, 123, 235, 13, 51, 12 },
1084
  { 837, 123, 235, 13, 51, 12 },
1085
  { 842, 123, 235, 13, 51, 12 },
1086
  { 847, 123, 235, 13, 51, 12 },
1087
  { 852, 123, 235, 13, 51, 12 },
1088
  { 857, 123, 235, 13, 51, 12 },
1089
  { 1134, 62, 238, 3, 643, 5 },
1090
  { 1138, 62, 238, 3, 643, 5 },
1091
  { 1104, 62, 238, 3, 643, 5 },
1092
  { 1109, 62, 238, 3, 643, 5 },
1093
  { 1114, 62, 238, 3, 643, 5 },
1094
  { 1119, 62, 238, 3, 643, 5 },
1095
  { 1124, 62, 238, 3, 643, 5 },
1096
  { 1129, 62, 238, 3, 643, 5 },
1097
  { 980, 2, 234, 2, 3619, 0 },
1098
  { 985, 2, 234, 2, 3619, 0 },
1099
  { 944, 2, 234, 2, 3619, 0 },
1100
  { 950, 2, 234, 2, 3619, 0 },
1101
  { 956, 2, 234, 2, 3619, 0 },
1102
  { 962, 2, 234, 2, 3619, 0 },
1103
  { 968, 2, 234, 2, 3619, 0 },
1104
  { 974, 2, 234, 2, 3619, 0 },
1105
};
1106
1107
extern const MCPhysReg X86RegUnitRoots[][2] = {
1108
  { X86::AH },
1109
  { X86::AL },
1110
  { X86::BH },
1111
  { X86::BL },
1112
  { X86::BPL },
1113
  { X86::BPH },
1114
  { X86::CH },
1115
  { X86::CL },
1116
  { X86::CS },
1117
  { X86::DF },
1118
  { X86::DH },
1119
  { X86::DIL },
1120
  { X86::DIH },
1121
  { X86::DL },
1122
  { X86::DS },
1123
  { X86::HAX },
1124
  { X86::HBP },
1125
  { X86::HBX },
1126
  { X86::HCX },
1127
  { X86::HDI },
1128
  { X86::HDX },
1129
  { X86::EFLAGS },
1130
  { X86::IP },
1131
  { X86::HIP },
1132
  { X86::EIZ },
1133
  { X86::ES },
1134
  { X86::SIL },
1135
  { X86::SIH },
1136
  { X86::HSI },
1137
  { X86::SPL },
1138
  { X86::SPH },
1139
  { X86::HSP },
1140
  { X86::FPSW },
1141
  { X86::FS },
1142
  { X86::GS },
1143
  { X86::RIZ },
1144
  { X86::SS },
1145
  { X86::SSP },
1146
  { X86::BND0 },
1147
  { X86::BND1 },
1148
  { X86::BND2 },
1149
  { X86::BND3 },
1150
  { X86::CR0 },
1151
  { X86::CR1 },
1152
  { X86::CR2 },
1153
  { X86::CR3 },
1154
  { X86::CR4 },
1155
  { X86::CR5 },
1156
  { X86::CR6 },
1157
  { X86::CR7 },
1158
  { X86::CR8 },
1159
  { X86::CR9 },
1160
  { X86::CR10 },
1161
  { X86::CR11 },
1162
  { X86::CR12 },
1163
  { X86::CR13 },
1164
  { X86::CR14 },
1165
  { X86::CR15 },
1166
  { X86::DR0 },
1167
  { X86::DR1 },
1168
  { X86::DR2 },
1169
  { X86::DR3 },
1170
  { X86::DR4 },
1171
  { X86::DR5 },
1172
  { X86::DR6 },
1173
  { X86::DR7 },
1174
  { X86::DR8 },
1175
  { X86::DR9 },
1176
  { X86::DR10 },
1177
  { X86::DR11 },
1178
  { X86::DR12 },
1179
  { X86::DR13 },
1180
  { X86::DR14 },
1181
  { X86::DR15 },
1182
  { X86::FP0 },
1183
  { X86::FP1 },
1184
  { X86::FP2 },
1185
  { X86::FP3 },
1186
  { X86::FP4 },
1187
  { X86::FP5 },
1188
  { X86::FP6 },
1189
  { X86::FP7 },
1190
  { X86::K0 },
1191
  { X86::K1 },
1192
  { X86::K2 },
1193
  { X86::K3 },
1194
  { X86::K4 },
1195
  { X86::K5 },
1196
  { X86::K6 },
1197
  { X86::K7 },
1198
  { X86::MM0 },
1199
  { X86::MM1 },
1200
  { X86::MM2 },
1201
  { X86::MM3 },
1202
  { X86::MM4 },
1203
  { X86::MM5 },
1204
  { X86::MM6 },
1205
  { X86::MM7 },
1206
  { X86::R8B },
1207
  { X86::R8BH },
1208
  { X86::R8WH },
1209
  { X86::R9B },
1210
  { X86::R9BH },
1211
  { X86::R9WH },
1212
  { X86::R10B },
1213
  { X86::R10BH },
1214
  { X86::R10WH },
1215
  { X86::R11B },
1216
  { X86::R11BH },
1217
  { X86::R11WH },
1218
  { X86::R12B },
1219
  { X86::R12BH },
1220
  { X86::R12WH },
1221
  { X86::R13B },
1222
  { X86::R13BH },
1223
  { X86::R13WH },
1224
  { X86::R14B },
1225
  { X86::R14BH },
1226
  { X86::R14WH },
1227
  { X86::R15B },
1228
  { X86::R15BH },
1229
  { X86::R15WH },
1230
  { X86::ST0 },
1231
  { X86::ST1 },
1232
  { X86::ST2 },
1233
  { X86::ST3 },
1234
  { X86::ST4 },
1235
  { X86::ST5 },
1236
  { X86::ST6 },
1237
  { X86::ST7 },
1238
  { X86::XMM0 },
1239
  { X86::XMM1 },
1240
  { X86::XMM2 },
1241
  { X86::XMM3 },
1242
  { X86::XMM4 },
1243
  { X86::XMM5 },
1244
  { X86::XMM6 },
1245
  { X86::XMM7 },
1246
  { X86::XMM8 },
1247
  { X86::XMM9 },
1248
  { X86::XMM10 },
1249
  { X86::XMM11 },
1250
  { X86::XMM12 },
1251
  { X86::XMM13 },
1252
  { X86::XMM14 },
1253
  { X86::XMM15 },
1254
  { X86::XMM16 },
1255
  { X86::XMM17 },
1256
  { X86::XMM18 },
1257
  { X86::XMM19 },
1258
  { X86::XMM20 },
1259
  { X86::XMM21 },
1260
  { X86::XMM22 },
1261
  { X86::XMM23 },
1262
  { X86::XMM24 },
1263
  { X86::XMM25 },
1264
  { X86::XMM26 },
1265
  { X86::XMM27 },
1266
  { X86::XMM28 },
1267
  { X86::XMM29 },
1268
  { X86::XMM30 },
1269
  { X86::XMM31 },
1270
};
1271
1272
namespace {     // Register classes...
1273
  // GR8 Register Class...
1274
  const MCPhysReg GR8[] = {
1275
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 
1276
  };
1277
1278
  // GR8 Bit set.
1279
  const uint8_t GR8Bits[] = {
1280
    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1281
  };
1282
1283
  // GRH8 Register Class...
1284
  const MCPhysReg GRH8[] = {
1285
    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 
1286
  };
1287
1288
  // GRH8 Bit set.
1289
  const uint8_t GRH8Bits[] = {
1290
    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1291
  };
1292
1293
  // GR8_NOREX Register Class...
1294
  const MCPhysReg GR8_NOREX[] = {
1295
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
1296
  };
1297
1298
  // GR8_NOREX Bit set.
1299
  const uint8_t GR8_NOREXBits[] = {
1300
    0x36, 0x8c, 0x08, 
1301
  };
1302
1303
  // GR8_ABCD_H Register Class...
1304
  const MCPhysReg GR8_ABCD_H[] = {
1305
    X86::AH, X86::CH, X86::DH, X86::BH, 
1306
  };
1307
1308
  // GR8_ABCD_H Bit set.
1309
  const uint8_t GR8_ABCD_HBits[] = {
1310
    0x12, 0x84, 
1311
  };
1312
1313
  // GR8_ABCD_L Register Class...
1314
  const MCPhysReg GR8_ABCD_L[] = {
1315
    X86::AL, X86::CL, X86::DL, X86::BL, 
1316
  };
1317
1318
  // GR8_ABCD_L Bit set.
1319
  const uint8_t GR8_ABCD_LBits[] = {
1320
    0x24, 0x08, 0x08, 
1321
  };
1322
1323
  // GRH16 Register Class...
1324
  const MCPhysReg GRH16[] = {
1325
    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 
1326
  };
1327
1328
  // GRH16 Bit set.
1329
  const uint8_t GRH16Bits[] = {
1330
    0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1331
  };
1332
1333
  // GR16 Register Class...
1334
  const MCPhysReg GR16[] = {
1335
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 
1336
  };
1337
1338
  // GR16 Bit set.
1339
  const uint8_t GR16Bits[] = {
1340
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1341
  };
1342
1343
  // GR16_NOREX Register Class...
1344
  const MCPhysReg GR16_NOREX[] = {
1345
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
1346
  };
1347
1348
  // GR16_NOREX Bit set.
1349
  const uint8_t GR16_NOREXBits[] = {
1350
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 
1351
  };
1352
1353
  // VK1 Register Class...
1354
  const MCPhysReg VK1[] = {
1355
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1356
  };
1357
1358
  // VK1 Bit set.
1359
  const uint8_t VK1Bits[] = {
1360
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1361
  };
1362
1363
  // VK16 Register Class...
1364
  const MCPhysReg VK16[] = {
1365
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1366
  };
1367
1368
  // VK16 Bit set.
1369
  const uint8_t VK16Bits[] = {
1370
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1371
  };
1372
1373
  // VK2 Register Class...
1374
  const MCPhysReg VK2[] = {
1375
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1376
  };
1377
1378
  // VK2 Bit set.
1379
  const uint8_t VK2Bits[] = {
1380
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1381
  };
1382
1383
  // VK4 Register Class...
1384
  const MCPhysReg VK4[] = {
1385
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1386
  };
1387
1388
  // VK4 Bit set.
1389
  const uint8_t VK4Bits[] = {
1390
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1391
  };
1392
1393
  // VK8 Register Class...
1394
  const MCPhysReg VK8[] = {
1395
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1396
  };
1397
1398
  // VK8 Bit set.
1399
  const uint8_t VK8Bits[] = {
1400
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1401
  };
1402
1403
  // VK16WM Register Class...
1404
  const MCPhysReg VK16WM[] = {
1405
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1406
  };
1407
1408
  // VK16WM Bit set.
1409
  const uint8_t VK16WMBits[] = {
1410
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1411
  };
1412
1413
  // VK1WM Register Class...
1414
  const MCPhysReg VK1WM[] = {
1415
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1416
  };
1417
1418
  // VK1WM Bit set.
1419
  const uint8_t VK1WMBits[] = {
1420
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1421
  };
1422
1423
  // VK2WM Register Class...
1424
  const MCPhysReg VK2WM[] = {
1425
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1426
  };
1427
1428
  // VK2WM Bit set.
1429
  const uint8_t VK2WMBits[] = {
1430
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1431
  };
1432
1433
  // VK4WM Register Class...
1434
  const MCPhysReg VK4WM[] = {
1435
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1436
  };
1437
1438
  // VK4WM Bit set.
1439
  const uint8_t VK4WMBits[] = {
1440
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1441
  };
1442
1443
  // VK8WM Register Class...
1444
  const MCPhysReg VK8WM[] = {
1445
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1446
  };
1447
1448
  // VK8WM Bit set.
1449
  const uint8_t VK8WMBits[] = {
1450
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1451
  };
1452
1453
  // SEGMENT_REG Register Class...
1454
  const MCPhysReg SEGMENT_REG[] = {
1455
    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 
1456
  };
1457
1458
  // SEGMENT_REG Bit set.
1459
  const uint8_t SEGMENT_REGBits[] = {
1460
    0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80, 
1461
  };
1462
1463
  // GR16_ABCD Register Class...
1464
  const MCPhysReg GR16_ABCD[] = {
1465
    X86::AX, X86::CX, X86::DX, X86::BX, 
1466
  };
1467
1468
  // GR16_ABCD Bit set.
1469
  const uint8_t GR16_ABCDBits[] = {
1470
    0x08, 0x22, 0x20, 
1471
  };
1472
1473
  // FPCCR Register Class...
1474
  const MCPhysReg FPCCR[] = {
1475
    X86::FPSW, 
1476
  };
1477
1478
  // FPCCR Bit set.
1479
  const uint8_t FPCCRBits[] = {
1480
    0x00, 0x00, 0x00, 0x00, 0x04, 
1481
  };
1482
1483
  // FR32X Register Class...
1484
  const MCPhysReg FR32X[] = {
1485
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1486
  };
1487
1488
  // FR32X Bit set.
1489
  const uint8_t FR32XBits[] = {
1490
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1491
  };
1492
1493
  // LOW32_ADDR_ACCESS_RBP Register Class...
1494
  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1495
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 
1496
  };
1497
1498
  // LOW32_ADDR_ACCESS_RBP Bit set.
1499
  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1500
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1501
  };
1502
1503
  // LOW32_ADDR_ACCESS Register Class...
1504
  const MCPhysReg LOW32_ADDR_ACCESS[] = {
1505
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 
1506
  };
1507
1508
  // LOW32_ADDR_ACCESS Bit set.
1509
  const uint8_t LOW32_ADDR_ACCESSBits[] = {
1510
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1511
  };
1512
1513
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1514
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1515
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 
1516
  };
1517
1518
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1519
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1520
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1521
  };
1522
1523
  // DEBUG_REG Register Class...
1524
  const MCPhysReg DEBUG_REG[] = {
1525
    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 
1526
  };
1527
1528
  // DEBUG_REG Bit set.
1529
  const uint8_t DEBUG_REGBits[] = {
1530
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1531
  };
1532
1533
  // FR32 Register Class...
1534
  const MCPhysReg FR32[] = {
1535
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1536
  };
1537
1538
  // FR32 Bit set.
1539
  const uint8_t FR32Bits[] = {
1540
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1541
  };
1542
1543
  // GR32 Register Class...
1544
  const MCPhysReg GR32[] = {
1545
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1546
  };
1547
1548
  // GR32 Bit set.
1549
  const uint8_t GR32Bits[] = {
1550
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1551
  };
1552
1553
  // GR32_NOSP Register Class...
1554
  const MCPhysReg GR32_NOSP[] = {
1555
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1556
  };
1557
1558
  // GR32_NOSP Bit set.
1559
  const uint8_t GR32_NOSPBits[] = {
1560
    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1561
  };
1562
1563
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1564
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1565
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 
1566
  };
1567
1568
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1569
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1570
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 
1571
  };
1572
1573
  // GR32_NOREX Register Class...
1574
  const MCPhysReg GR32_NOREX[] = {
1575
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
1576
  };
1577
1578
  // GR32_NOREX Bit set.
1579
  const uint8_t GR32_NOREXBits[] = {
1580
    0x00, 0x00, 0xc0, 0x0f, 0x03, 
1581
  };
1582
1583
  // VK32 Register Class...
1584
  const MCPhysReg VK32[] = {
1585
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1586
  };
1587
1588
  // VK32 Bit set.
1589
  const uint8_t VK32Bits[] = {
1590
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1591
  };
1592
1593
  // GR32_NOREX_NOSP Register Class...
1594
  const MCPhysReg GR32_NOREX_NOSP[] = {
1595
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 
1596
  };
1597
1598
  // GR32_NOREX_NOSP Bit set.
1599
  const uint8_t GR32_NOREX_NOSPBits[] = {
1600
    0x00, 0x00, 0xc0, 0x0f, 0x01, 
1601
  };
1602
1603
  // RFP32 Register Class...
1604
  const MCPhysReg RFP32[] = {
1605
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1606
  };
1607
1608
  // RFP32 Bit set.
1609
  const uint8_t RFP32Bits[] = {
1610
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1611
  };
1612
1613
  // VK32WM Register Class...
1614
  const MCPhysReg VK32WM[] = {
1615
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1616
  };
1617
1618
  // VK32WM Bit set.
1619
  const uint8_t VK32WMBits[] = {
1620
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1621
  };
1622
1623
  // GR32_ABCD Register Class...
1624
  const MCPhysReg GR32_ABCD[] = {
1625
    X86::EAX, X86::ECX, X86::EDX, X86::EBX, 
1626
  };
1627
1628
  // GR32_ABCD Bit set.
1629
  const uint8_t GR32_ABCDBits[] = {
1630
    0x00, 0x00, 0x40, 0x0b, 
1631
  };
1632
1633
  // GR32_TC Register Class...
1634
  const MCPhysReg GR32_TC[] = {
1635
    X86::EAX, X86::ECX, X86::EDX, 
1636
  };
1637
1638
  // GR32_TC Bit set.
1639
  const uint8_t GR32_TCBits[] = {
1640
    0x00, 0x00, 0x40, 0x0a, 
1641
  };
1642
1643
  // GR32_AD Register Class...
1644
  const MCPhysReg GR32_AD[] = {
1645
    X86::EAX, X86::EDX, 
1646
  };
1647
1648
  // GR32_AD Bit set.
1649
  const uint8_t GR32_ADBits[] = {
1650
    0x00, 0x00, 0x40, 0x08, 
1651
  };
1652
1653
  // GR32_BPSP Register Class...
1654
  const MCPhysReg GR32_BPSP[] = {
1655
    X86::EBP, X86::ESP, 
1656
  };
1657
1658
  // GR32_BPSP Bit set.
1659
  const uint8_t GR32_BPSPBits[] = {
1660
    0x00, 0x00, 0x80, 0x00, 0x02, 
1661
  };
1662
1663
  // GR32_BSI Register Class...
1664
  const MCPhysReg GR32_BSI[] = {
1665
    X86::EBX, X86::ESI, 
1666
  };
1667
1668
  // GR32_BSI Bit set.
1669
  const uint8_t GR32_BSIBits[] = {
1670
    0x00, 0x00, 0x00, 0x01, 0x01, 
1671
  };
1672
1673
  // GR32_CB Register Class...
1674
  const MCPhysReg GR32_CB[] = {
1675
    X86::ECX, X86::EBX, 
1676
  };
1677
1678
  // GR32_CB Bit set.
1679
  const uint8_t GR32_CBBits[] = {
1680
    0x00, 0x00, 0x00, 0x03, 
1681
  };
1682
1683
  // GR32_DC Register Class...
1684
  const MCPhysReg GR32_DC[] = {
1685
    X86::EDX, X86::ECX, 
1686
  };
1687
1688
  // GR32_DC Bit set.
1689
  const uint8_t GR32_DCBits[] = {
1690
    0x00, 0x00, 0x00, 0x0a, 
1691
  };
1692
1693
  // GR32_DIBP Register Class...
1694
  const MCPhysReg GR32_DIBP[] = {
1695
    X86::EDI, X86::EBP, 
1696
  };
1697
1698
  // GR32_DIBP Bit set.
1699
  const uint8_t GR32_DIBPBits[] = {
1700
    0x00, 0x00, 0x80, 0x04, 
1701
  };
1702
1703
  // GR32_SIDI Register Class...
1704
  const MCPhysReg GR32_SIDI[] = {
1705
    X86::ESI, X86::EDI, 
1706
  };
1707
1708
  // GR32_SIDI Bit set.
1709
  const uint8_t GR32_SIDIBits[] = {
1710
    0x00, 0x00, 0x00, 0x04, 0x01, 
1711
  };
1712
1713
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1714
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1715
    X86::RIP, X86::RBP, 
1716
  };
1717
1718
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1719
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1720
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
1721
  };
1722
1723
  // CCR Register Class...
1724
  const MCPhysReg CCR[] = {
1725
    X86::EFLAGS, 
1726
  };
1727
1728
  // CCR Bit set.
1729
  const uint8_t CCRBits[] = {
1730
    0x00, 0x00, 0x00, 0x10, 
1731
  };
1732
1733
  // DFCCR Register Class...
1734
  const MCPhysReg DFCCR[] = {
1735
    X86::DF, 
1736
  };
1737
1738
  // DFCCR Bit set.
1739
  const uint8_t DFCCRBits[] = {
1740
    0x00, 0x40, 
1741
  };
1742
1743
  // GR32_ABCD_and_GR32_BSI Register Class...
1744
  const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1745
    X86::EBX, 
1746
  };
1747
1748
  // GR32_ABCD_and_GR32_BSI Bit set.
1749
  const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1750
    0x00, 0x00, 0x00, 0x01, 
1751
  };
1752
1753
  // GR32_AD_and_GR32_DC Register Class...
1754
  const MCPhysReg GR32_AD_and_GR32_DC[] = {
1755
    X86::EDX, 
1756
  };
1757
1758
  // GR32_AD_and_GR32_DC Bit set.
1759
  const uint8_t GR32_AD_and_GR32_DCBits[] = {
1760
    0x00, 0x00, 0x00, 0x08, 
1761
  };
1762
1763
  // GR32_BPSP_and_GR32_DIBP Register Class...
1764
  const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1765
    X86::EBP, 
1766
  };
1767
1768
  // GR32_BPSP_and_GR32_DIBP Bit set.
1769
  const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1770
    0x00, 0x00, 0x80, 
1771
  };
1772
1773
  // GR32_BSI_and_GR32_SIDI Register Class...
1774
  const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1775
    X86::ESI, 
1776
  };
1777
1778
  // GR32_BSI_and_GR32_SIDI Bit set.
1779
  const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
1780
    0x00, 0x00, 0x00, 0x00, 0x01, 
1781
  };
1782
1783
  // GR32_CB_and_GR32_DC Register Class...
1784
  const MCPhysReg GR32_CB_and_GR32_DC[] = {
1785
    X86::ECX, 
1786
  };
1787
1788
  // GR32_CB_and_GR32_DC Bit set.
1789
  const uint8_t GR32_CB_and_GR32_DCBits[] = {
1790
    0x00, 0x00, 0x00, 0x02, 
1791
  };
1792
1793
  // GR32_DIBP_and_GR32_SIDI Register Class...
1794
  const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1795
    X86::EDI, 
1796
  };
1797
1798
  // GR32_DIBP_and_GR32_SIDI Bit set.
1799
  const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
1800
    0x00, 0x00, 0x00, 0x04, 
1801
  };
1802
1803
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1804
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1805
    X86::RBP, 
1806
  };
1807
1808
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1809
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1810
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1811
  };
1812
1813
  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1814
  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1815
    X86::RIP, 
1816
  };
1817
1818
  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1819
  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1820
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
1821
  };
1822
1823
  // RFP64 Register Class...
1824
  const MCPhysReg RFP64[] = {
1825
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1826
  };
1827
1828
  // RFP64 Bit set.
1829
  const uint8_t RFP64Bits[] = {
1830
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1831
  };
1832
1833
  // FR64X Register Class...
1834
  const MCPhysReg FR64X[] = {
1835
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1836
  };
1837
1838
  // FR64X Bit set.
1839
  const uint8_t FR64XBits[] = {
1840
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1841
  };
1842
1843
  // GR64 Register Class...
1844
  const MCPhysReg GR64[] = {
1845
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 
1846
  };
1847
1848
  // GR64 Bit set.
1849
  const uint8_t GR64Bits[] = {
1850
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1851
  };
1852
1853
  // CONTROL_REG Register Class...
1854
  const MCPhysReg CONTROL_REG[] = {
1855
    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 
1856
  };
1857
1858
  // CONTROL_REG Bit set.
1859
  const uint8_t CONTROL_REGBits[] = {
1860
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1861
  };
1862
1863
  // FR64 Register Class...
1864
  const MCPhysReg FR64[] = {
1865
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1866
  };
1867
1868
  // FR64 Bit set.
1869
  const uint8_t FR64Bits[] = {
1870
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1871
  };
1872
1873
  // GR64_with_sub_8bit Register Class...
1874
  const MCPhysReg GR64_with_sub_8bit[] = {
1875
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 
1876
  };
1877
1878
  // GR64_with_sub_8bit Bit set.
1879
  const uint8_t GR64_with_sub_8bitBits[] = {
1880
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1881
  };
1882
1883
  // GR64_NOSP Register Class...
1884
  const MCPhysReg GR64_NOSP[] = {
1885
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 
1886
  };
1887
1888
  // GR64_NOSP Bit set.
1889
  const uint8_t GR64_NOSPBits[] = {
1890
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1891
  };
1892
1893
  // GR64_NOREX Register Class...
1894
  const MCPhysReg GR64_NOREX[] = {
1895
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 
1896
  };
1897
1898
  // GR64_NOREX Bit set.
1899
  const uint8_t GR64_NOREXBits[] = {
1900
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 
1901
  };
1902
1903
  // GR64_TC Register Class...
1904
  const MCPhysReg GR64_TC[] = {
1905
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, 
1906
  };
1907
1908
  // GR64_TC Bit set.
1909
  const uint8_t GR64_TCBits[] = {
1910
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1911
  };
1912
1913
  // GR64_NOSP_and_GR64_TC Register Class...
1914
  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
1915
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 
1916
  };
1917
1918
  // GR64_NOSP_and_GR64_TC Bit set.
1919
  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
1920
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1921
  };
1922
1923
  // GR64_TCW64 Register Class...
1924
  const MCPhysReg GR64_TCW64[] = {
1925
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, 
1926
  };
1927
1928
  // GR64_TCW64 Bit set.
1929
  const uint8_t GR64_TCW64Bits[] = {
1930
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1931
  };
1932
1933
  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1934
  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1935
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 
1936
  };
1937
1938
  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1939
  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1940
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 
1941
  };
1942
1943
  // VK64 Register Class...
1944
  const MCPhysReg VK64[] = {
1945
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1946
  };
1947
1948
  // VK64 Bit set.
1949
  const uint8_t VK64Bits[] = {
1950
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1951
  };
1952
1953
  // VR64 Register Class...
1954
  const MCPhysReg VR64[] = {
1955
    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
1956
  };
1957
1958
  // VR64 Bit set.
1959
  const uint8_t VR64Bits[] = {
1960
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1961
  };
1962
1963
  // GR64_NOREX_NOSP Register Class...
1964
  const MCPhysReg GR64_NOREX_NOSP[] = {
1965
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 
1966
  };
1967
1968
  // GR64_NOREX_NOSP Bit set.
1969
  const uint8_t GR64_NOREX_NOSPBits[] = {
1970
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 
1971
  };
1972
1973
  // GR64_NOSP_and_GR64_TCW64 Register Class...
1974
  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
1975
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 
1976
  };
1977
1978
  // GR64_NOSP_and_GR64_TCW64 Bit set.
1979
  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
1980
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1981
  };
1982
1983
  // GR64_TC_and_GR64_TCW64 Register Class...
1984
  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1985
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, 
1986
  };
1987
1988
  // GR64_TC_and_GR64_TCW64 Bit set.
1989
  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1990
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1991
  };
1992
1993
  // VK64WM Register Class...
1994
  const MCPhysReg VK64WM[] = {
1995
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1996
  };
1997
1998
  // VK64WM Bit set.
1999
  const uint8_t VK64WMBits[] = {
2000
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
2001
  };
2002
2003
  // GR64_NOREX_and_GR64_TC Register Class...
2004
  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2005
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RIP, 
2006
  };
2007
2008
  // GR64_NOREX_and_GR64_TC Bit set.
2009
  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2010
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 
2011
  };
2012
2013
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
2014
  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
2015
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 
2016
  };
2017
2018
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
2019
  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
2020
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
2021
  };
2022
2023
  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
2024
  const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
2025
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 
2026
  };
2027
2028
  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
2029
  const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
2030
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 
2031
  };
2032
2033
  // GR64_ABCD Register Class...
2034
  const MCPhysReg GR64_ABCD[] = {
2035
    X86::RAX, X86::RCX, X86::RDX, X86::RBX, 
2036
  };
2037
2038
  // GR64_ABCD Bit set.
2039
  const uint8_t GR64_ABCDBits[] = {
2040
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, 
2041
  };
2042
2043
  // GR64_NOREX_and_GR64_TCW64 Register Class...
2044
  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2045
    X86::RAX, X86::RCX, X86::RDX, X86::RIP, 
2046
  };
2047
2048
  // GR64_NOREX_and_GR64_TCW64 Bit set.
2049
  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2050
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 
2051
  };
2052
2053
  // GR64_with_sub_32bit_in_GR32_TC Register Class...
2054
  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2055
    X86::RAX, X86::RCX, X86::RDX, 
2056
  };
2057
2058
  // GR64_with_sub_32bit_in_GR32_TC Bit set.
2059
  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2060
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 
2061
  };
2062
2063
  // GR64_AD Register Class...
2064
  const MCPhysReg GR64_AD[] = {
2065
    X86::RAX, X86::RDX, 
2066
  };
2067
2068
  // GR64_AD Bit set.
2069
  const uint8_t GR64_ADBits[] = {
2070
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10, 
2071
  };
2072
2073
  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2074
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2075
    X86::RBP, X86::RIP, 
2076
  };
2077
2078
  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2079
  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2080
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
2081
  };
2082
2083
  // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2084
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2085
    X86::RBP, X86::RSP, 
2086
  };
2087
2088
  // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2089
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2090
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 
2091
  };
2092
2093
  // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2094
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2095
    X86::RSI, X86::RBX, 
2096
  };
2097
2098
  // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2099
  const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2100
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 
2101
  };
2102
2103
  // GR64_with_sub_32bit_in_GR32_CB Register Class...
2104
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2105
    X86::RCX, X86::RBX, 
2106
  };
2107
2108
  // GR64_with_sub_32bit_in_GR32_CB Bit set.
2109
  const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2110
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
2111
  };
2112
2113
  // GR64_with_sub_32bit_in_GR32_DC Register Class...
2114
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
2115
    X86::RCX, X86::RDX, 
2116
  };
2117
2118
  // GR64_with_sub_32bit_in_GR32_DC Bit set.
2119
  const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
2120
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
2121
  };
2122
2123
  // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2124
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2125
    X86::RDI, X86::RBP, 
2126
  };
2127
2128
  // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2129
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2130
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 
2131
  };
2132
2133
  // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2134
  const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2135
    X86::RSI, X86::RDI, 
2136
  };
2137
2138
  // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2139
  const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2140
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 
2141
  };
2142
2143
  // GR64_and_LOW32_ADDR_ACCESS Register Class...
2144
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2145
    X86::RIP, 
2146
  };
2147
2148
  // GR64_and_LOW32_ADDR_ACCESS Bit set.
2149
  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2150
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2151
  };
2152
2153
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2154
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2155
    X86::RBX, 
2156
  };
2157
2158
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2159
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2160
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
2161
  };
2162
2163
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
2164
  const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
2165
    X86::RDX, 
2166
  };
2167
2168
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
2169
  const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
2170
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2171
  };
2172
2173
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2174
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2175
    X86::RBP, 
2176
  };
2177
2178
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2179
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2180
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
2181
  };
2182
2183
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2184
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2185
    X86::RSI, 
2186
  };
2187
2188
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2189
  const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2190
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
2191
  };
2192
2193
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
2194
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
2195
    X86::RCX, 
2196
  };
2197
2198
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
2199
  const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
2200
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
2201
  };
2202
2203
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2204
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2205
    X86::RDI, 
2206
  };
2207
2208
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2209
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2210
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
2211
  };
2212
2213
  // RST Register Class...
2214
  const MCPhysReg RST[] = {
2215
    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
2216
  };
2217
2218
  // RST Bit set.
2219
  const uint8_t RSTBits[] = {
2220
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2221
  };
2222
2223
  // RFP80 Register Class...
2224
  const MCPhysReg RFP80[] = {
2225
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
2226
  };
2227
2228
  // RFP80 Bit set.
2229
  const uint8_t RFP80Bits[] = {
2230
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
2231
  };
2232
2233
  // VR128X Register Class...
2234
  const MCPhysReg VR128X[] = {
2235
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
2236
  };
2237
2238
  // VR128X Bit set.
2239
  const uint8_t VR128XBits[] = {
2240
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2241
  };
2242
2243
  // VR128 Register Class...
2244
  const MCPhysReg VR128[] = {
2245
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2246
  };
2247
2248
  // VR128 Bit set.
2249
  const uint8_t VR128Bits[] = {
2250
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2251
  };
2252
2253
  // VR128H Register Class...
2254
  const MCPhysReg VR128H[] = {
2255
    X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2256
  };
2257
2258
  // VR128H Bit set.
2259
  const uint8_t VR128HBits[] = {
2260
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2261
  };
2262
2263
  // VR128L Register Class...
2264
  const MCPhysReg VR128L[] = {
2265
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
2266
  };
2267
2268
  // VR128L Bit set.
2269
  const uint8_t VR128LBits[] = {
2270
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2271
  };
2272
2273
  // BNDR Register Class...
2274
  const MCPhysReg BNDR[] = {
2275
    X86::BND0, X86::BND1, X86::BND2, X86::BND3, 
2276
  };
2277
2278
  // BNDR Bit set.
2279
  const uint8_t BNDRBits[] = {
2280
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
2281
  };
2282
2283
  // VR256X Register Class...
2284
  const MCPhysReg VR256X[] = {
2285
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 
2286
  };
2287
2288
  // VR256X Bit set.
2289
  const uint8_t VR256XBits[] = {
2290
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2291
  };
2292
2293
  // VR256 Register Class...
2294
  const MCPhysReg VR256[] = {
2295
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2296
  };
2297
2298
  // VR256 Bit set.
2299
  const uint8_t VR256Bits[] = {
2300
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2301
  };
2302
2303
  // VR256H Register Class...
2304
  const MCPhysReg VR256H[] = {
2305
    X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2306
  };
2307
2308
  // VR256H Bit set.
2309
  const uint8_t VR256HBits[] = {
2310
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2311
  };
2312
2313
  // VR256L Register Class...
2314
  const MCPhysReg VR256L[] = {
2315
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 
2316
  };
2317
2318
  // VR256L Bit set.
2319
  const uint8_t VR256LBits[] = {
2320
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2321
  };
2322
2323
  // VR512 Register Class...
2324
  const MCPhysReg VR512[] = {
2325
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 
2326
  };
2327
2328
  // VR512 Bit set.
2329
  const uint8_t VR512Bits[] = {
2330
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2331
  };
2332
2333
  // VR512_with_sub_xmm_in_FR32 Register Class...
2334
  const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
2335
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2336
  };
2337
2338
  // VR512_with_sub_xmm_in_FR32 Bit set.
2339
  const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
2340
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2341
  };
2342
2343
  // VR512_with_sub_xmm_in_VR128H Register Class...
2344
  const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = {
2345
    X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2346
  };
2347
2348
  // VR512_with_sub_xmm_in_VR128H Bit set.
2349
  const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = {
2350
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2351
  };
2352
2353
  // VR512_with_sub_xmm_in_VR128L Register Class...
2354
  const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = {
2355
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, 
2356
  };
2357
2358
  // VR512_with_sub_xmm_in_VR128L Bit set.
2359
  const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = {
2360
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2361
  };
2362
2363
} // end anonymous namespace
2364
2365
extern const char X86RegClassStrings[] = {
2366
  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
2367
  /* 6 */ 'V', 'K', '1', 0,
2368
  /* 10 */ 'V', 'R', '5', '1', '2', 0,
2369
  /* 16 */ 'V', 'K', '3', '2', 0,
2370
  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
2371
  /* 27 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'F', 'R', '3', '2', 0,
2372
  /* 54 */ 'G', 'R', '3', '2', 0,
2373
  /* 59 */ 'V', 'K', '2', 0,
2374
  /* 63 */ 'V', 'K', '6', '4', 0,
2375
  /* 68 */ 'R', 'F', 'P', '6', '4', 0,
2376
  /* 74 */ 'F', 'R', '6', '4', 0,
2377
  /* 79 */ 'G', 'R', '6', '4', 0,
2378
  /* 84 */ 'V', 'R', '6', '4', 0,
2379
  /* 89 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2380
  /* 112 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2381
  /* 149 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2382
  /* 175 */ 'V', 'K', '4', 0,
2383
  /* 179 */ 'G', 'R', 'H', '1', '6', 0,
2384
  /* 185 */ 'V', 'K', '1', '6', 0,
2385
  /* 190 */ 'G', 'R', '1', '6', 0,
2386
  /* 195 */ 'V', 'R', '2', '5', '6', 0,
2387
  /* 201 */ 'V', 'R', '1', '2', '8', 0,
2388
  /* 207 */ 'G', 'R', 'H', '8', 0,
2389
  /* 212 */ 'V', 'K', '8', 0,
2390
  /* 216 */ 'G', 'R', '8', 0,
2391
  /* 220 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
2392
  /* 251 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2393
  /* 294 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2394
  /* 337 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2395
  /* 368 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2396
  /* 399 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2397
  /* 421 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2398
  /* 449 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2399
  /* 472 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
2400
  /* 480 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
2401
  /* 488 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
2402
  /* 498 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
2403
  /* 508 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
2404
  /* 518 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
2405
  /* 528 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
2406
  /* 540 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
2407
  /* 552 */ 'V', 'R', '2', '5', '6', 'H', 0,
2408
  /* 559 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'H', 0,
2409
  /* 588 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
2410
  /* 599 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2411
  /* 645 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2412
  /* 692 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2413
  /* 725 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2414
  /* 771 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2415
  /* 803 */ 'V', 'R', '2', '5', '6', 'L', 0,
2416
  /* 810 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'L', 0,
2417
  /* 839 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
2418
  /* 850 */ 'V', 'K', '1', 'W', 'M', 0,
2419
  /* 856 */ 'V', 'K', '3', '2', 'W', 'M', 0,
2420
  /* 863 */ 'V', 'K', '2', 'W', 'M', 0,
2421
  /* 869 */ 'V', 'K', '6', '4', 'W', 'M', 0,
2422
  /* 876 */ 'V', 'K', '4', 'W', 'M', 0,
2423
  /* 882 */ 'V', 'K', '1', '6', 'W', 'M', 0,
2424
  /* 889 */ 'V', 'K', '8', 'W', 'M', 0,
2425
  /* 895 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2426
  /* 942 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2427
  /* 975 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2428
  /* 1006 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
2429
  /* 1016 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
2430
  /* 1026 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2431
  /* 1042 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2432
  /* 1058 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
2433
  /* 1091 */ 'D', 'F', 'C', 'C', 'R', 0,
2434
  /* 1097 */ 'F', 'P', 'C', 'C', 'R', 0,
2435
  /* 1103 */ 'B', 'N', 'D', 'R', 0,
2436
  /* 1108 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
2437
  /* 1135 */ 'R', 'S', 'T', 0,
2438
  /* 1139 */ 'F', 'R', '3', '2', 'X', 0,
2439
  /* 1145 */ 'F', 'R', '6', '4', 'X', 0,
2440
  /* 1151 */ 'V', 'R', '2', '5', '6', 'X', 0,
2441
  /* 1158 */ 'V', 'R', '1', '2', '8', 'X', 0,
2442
  /* 1165 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
2443
  /* 1176 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
2444
  /* 1187 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2445
  /* 1221 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2446
  /* 1272 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
2447
  /* 1282 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2448
  /* 1319 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2449
  /* 1352 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2450
  /* 1403 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2451
  /* 1422 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2452
};
2453
2454
extern const MCRegisterClass X86MCRegisterClasses[] = {
2455
  { GR8, GR8Bits, 216, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true },
2456
  { GRH8, GRH8Bits, 207, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, false },
2457
  { GR8_NOREX, GR8_NOREXBits, 1272, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, true },
2458
  { GR8_ABCD_H, GR8_ABCD_HBits, 588, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, true },
2459
  { GR8_ABCD_L, GR8_ABCD_LBits, 839, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, true },
2460
  { GRH16, GRH16Bits, 179, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 1, false },
2461
  { GR16, GR16Bits, 190, 16, sizeof(GR16Bits), X86::GR16RegClassID, 1, true },
2462
  { GR16_NOREX, GR16_NOREXBits, 1210, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 1, true },
2463
  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 1, true },
2464
  { VK16, VK16Bits, 185, 8, sizeof(VK16Bits), X86::VK16RegClassID, 1, true },
2465
  { VK2, VK2Bits, 59, 8, sizeof(VK2Bits), X86::VK2RegClassID, 1, true },
2466
  { VK4, VK4Bits, 175, 8, sizeof(VK4Bits), X86::VK4RegClassID, 1, true },
2467
  { VK8, VK8Bits, 212, 8, sizeof(VK8Bits), X86::VK8RegClassID, 1, true },
2468
  { VK16WM, VK16WMBits, 882, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 1, true },
2469
  { VK1WM, VK1WMBits, 850, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 1, true },
2470
  { VK2WM, VK2WMBits, 863, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 1, true },
2471
  { VK4WM, VK4WMBits, 876, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 1, true },
2472
  { VK8WM, VK8WMBits, 889, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 1, true },
2473
  { SEGMENT_REG, SEGMENT_REGBits, 540, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 1, true },
2474
  { GR16_ABCD, GR16_ABCDBits, 508, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 1, true },
2475
  { FPCCR, FPCCRBits, 1097, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, -1, false },
2476
  { FR32X, FR32XBits, 1139, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 1, true },
2477
  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 984, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2478
  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1117, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 1, true },
2479
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1422, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 1, true },
2480
  { DEBUG_REG, DEBUG_REGBits, 518, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 1, true },
2481
  { FR32, FR32Bits, 49, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true },
2482
  { GR32, GR32Bits, 54, 16, sizeof(GR32Bits), X86::GR32RegClassID, 1, true },
2483
  { GR32_NOSP, GR32_NOSPBits, 1006, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 1, true },
2484
  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1221, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2485
  { GR32_NOREX, GR32_NOREXBits, 1165, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 1, true },
2486
  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 1, true },
2487
  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1026, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 1, true },
2488
  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 1, true },
2489
  { VK32WM, VK32WMBits, 856, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 1, true },
2490
  { GR32_ABCD, GR32_ABCDBits, 488, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 1, true },
2491
  { GR32_TC, GR32_TCBits, 391, 3, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 1, true },
2492
  { GR32_AD, GR32_ADBits, 472, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 1, true },
2493
  { GR32_BPSP, GR32_BPSPBits, 1081, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 1, true },
2494
  { GR32_BSI, GR32_BSIBits, 762, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 1, true },
2495
  { GR32_CB, GR32_CBBits, 243, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 1, true },
2496
  { GR32_DC, GR32_DCBits, 286, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 1, true },
2497
  { GR32_DIBP, GR32_DIBPBits, 932, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 1, true },
2498
  { GR32_SIDI, GR32_SIDIBits, 635, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 1, true },
2499
  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1282, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 1, true },
2500
  { CCR, CCRBits, 1093, 1, sizeof(CCRBits), X86::CCRRegClassID, -1, false },
2501
  { DFCCR, DFCCRBits, 1091, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, -1, false },
2502
  { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 748, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2503
  { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 317, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 1, true },
2504
  { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 918, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2505
  { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 622, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2506
  { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 274, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 1, true },
2507
  { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 668, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2508
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1352, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 1, true },
2509
  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1319, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 1, true },
2510
  { RFP64, RFP64Bits, 68, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 1, true },
2511
  { FR64X, FR64XBits, 1145, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true },
2512
  { GR64, GR64Bits, 79, 17, sizeof(GR64Bits), X86::GR64RegClassID, 1, true },
2513
  { CONTROL_REG, CONTROL_REGBits, 528, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 1, true },
2514
  { FR64, FR64Bits, 74, 16, sizeof(FR64Bits), X86::FR64RegClassID, 1, true },
2515
  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1403, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 1, true },
2516
  { GR64_NOSP, GR64_NOSPBits, 1016, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 1, true },
2517
  { GR64_NOREX, GR64_NOREXBits, 1176, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 1, true },
2518
  { GR64_TC, GR64_TCBits, 413, 9, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 1, true },
2519
  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 399, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 1, true },
2520
  { GR64_TCW64, GR64_TCW64Bits, 101, 8, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 1, true },
2521
  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1187, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2522
  { VK64, VK64Bits, 63, 8, sizeof(VK64Bits), X86::VK64RegClassID, 1, true },
2523
  { VR64, VR64Bits, 84, 8, sizeof(VR64Bits), X86::VR64RegClassID, 1, true },
2524
  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1042, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 1, true },
2525
  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 124, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2526
  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 89, 7, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 1, true },
2527
  { VK64WM, VK64WMBits, 869, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 1, true },
2528
  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 449, 6, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 1, true },
2529
  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 112, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2530
  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 421, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 1, true },
2531
  { GR64_ABCD, GR64_ABCDBits, 498, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 1, true },
2532
  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 149, 4, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 1, true },
2533
  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 368, 3, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 1, true },
2534
  { GR64_AD, GR64_ADBits, 480, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 1, true },
2535
  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 975, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2536
  { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1058, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 1, true },
2537
  { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 771, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 1, true },
2538
  { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 220, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 1, true },
2539
  { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 337, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 1, true },
2540
  { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 942, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 1, true },
2541
  { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 692, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 1, true },
2542
  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1108, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 1, true },
2543
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 725, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2544
  { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 294, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 1, true },
2545
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 895, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2546
  { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 599, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2547
  { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 251, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 1, true },
2548
  { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 645, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2549
  { RST, RSTBits, 1135, 8, sizeof(RSTBits), X86::RSTRegClassID, 1, false },
2550
  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 1, true },
2551
  { VR128X, VR128XBits, 1158, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 1, true },
2552
  { VR128, VR128Bits, 201, 16, sizeof(VR128Bits), X86::VR128RegClassID, 1, true },
2553
  { VR128H, VR128HBits, 581, 8, sizeof(VR128HBits), X86::VR128HRegClassID, 1, true },
2554
  { VR128L, VR128LBits, 832, 8, sizeof(VR128LBits), X86::VR128LRegClassID, 1, true },
2555
  { BNDR, BNDRBits, 1103, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 1, true },
2556
  { VR256X, VR256XBits, 1151, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 1, true },
2557
  { VR256, VR256Bits, 195, 16, sizeof(VR256Bits), X86::VR256RegClassID, 1, true },
2558
  { VR256H, VR256HBits, 552, 8, sizeof(VR256HBits), X86::VR256HRegClassID, 1, true },
2559
  { VR256L, VR256LBits, 803, 8, sizeof(VR256LBits), X86::VR256LRegClassID, 1, true },
2560
  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 1, true },
2561
  { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, 27, 16, sizeof(VR512_with_sub_xmm_in_FR32Bits), X86::VR512_with_sub_xmm_in_FR32RegClassID, 1, true },
2562
  { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, 559, 8, sizeof(VR512_with_sub_xmm_in_VR128HBits), X86::VR512_with_sub_xmm_in_VR128HRegClassID, 1, true },
2563
  { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, 810, 8, sizeof(VR512_with_sub_xmm_in_VR128LBits), X86::VR512_with_sub_xmm_in_VR128LRegClassID, 1, true },
2564
};
2565
2566
// X86 Dwarf<->LLVM register mappings.
2567
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2568
  { 0U, X86::RAX },
2569
  { 1U, X86::RDX },
2570
  { 2U, X86::RCX },
2571
  { 3U, X86::RBX },
2572
  { 4U, X86::RSI },
2573
  { 5U, X86::RDI },
2574
  { 6U, X86::RBP },
2575
  { 7U, X86::RSP },
2576
  { 8U, X86::R8 },
2577
  { 9U, X86::R9 },
2578
  { 10U, X86::R10 },
2579
  { 11U, X86::R11 },
2580
  { 12U, X86::R12 },
2581
  { 13U, X86::R13 },
2582
  { 14U, X86::R14 },
2583
  { 15U, X86::R15 },
2584
  { 16U, X86::RIP },
2585
  { 17U, X86::XMM0 },
2586
  { 18U, X86::XMM1 },
2587
  { 19U, X86::XMM2 },
2588
  { 20U, X86::XMM3 },
2589
  { 21U, X86::XMM4 },
2590
  { 22U, X86::XMM5 },
2591
  { 23U, X86::XMM6 },
2592
  { 24U, X86::XMM7 },
2593
  { 25U, X86::XMM8 },
2594
  { 26U, X86::XMM9 },
2595
  { 27U, X86::XMM10 },
2596
  { 28U, X86::XMM11 },
2597
  { 29U, X86::XMM12 },
2598
  { 30U, X86::XMM13 },
2599
  { 31U, X86::XMM14 },
2600
  { 32U, X86::XMM15 },
2601
  { 33U, X86::ST0 },
2602
  { 34U, X86::ST1 },
2603
  { 35U, X86::ST2 },
2604
  { 36U, X86::ST3 },
2605
  { 37U, X86::ST4 },
2606
  { 38U, X86::ST5 },
2607
  { 39U, X86::ST6 },
2608
  { 40U, X86::ST7 },
2609
  { 41U, X86::MM0 },
2610
  { 42U, X86::MM1 },
2611
  { 43U, X86::MM2 },
2612
  { 44U, X86::MM3 },
2613
  { 45U, X86::MM4 },
2614
  { 46U, X86::MM5 },
2615
  { 47U, X86::MM6 },
2616
  { 48U, X86::MM7 },
2617
  { 67U, X86::XMM16 },
2618
  { 68U, X86::XMM17 },
2619
  { 69U, X86::XMM18 },
2620
  { 70U, X86::XMM19 },
2621
  { 71U, X86::XMM20 },
2622
  { 72U, X86::XMM21 },
2623
  { 73U, X86::XMM22 },
2624
  { 74U, X86::XMM23 },
2625
  { 75U, X86::XMM24 },
2626
  { 76U, X86::XMM25 },
2627
  { 77U, X86::XMM26 },
2628
  { 78U, X86::XMM27 },
2629
  { 79U, X86::XMM28 },
2630
  { 80U, X86::XMM29 },
2631
  { 81U, X86::XMM30 },
2632
  { 82U, X86::XMM31 },
2633
  { 118U, X86::K0 },
2634
  { 119U, X86::K1 },
2635
  { 120U, X86::K2 },
2636
  { 121U, X86::K3 },
2637
  { 122U, X86::K4 },
2638
  { 123U, X86::K5 },
2639
  { 124U, X86::K6 },
2640
  { 125U, X86::K7 },
2641
};
2642
extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L);
2643
2644
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2645
  { 0U, X86::EAX },
2646
  { 1U, X86::ECX },
2647
  { 2U, X86::EDX },
2648
  { 3U, X86::EBX },
2649
  { 4U, X86::EBP },
2650
  { 5U, X86::ESP },
2651
  { 6U, X86::ESI },
2652
  { 7U, X86::EDI },
2653
  { 8U, X86::EIP },
2654
  { 12U, X86::ST0 },
2655
  { 13U, X86::ST1 },
2656
  { 14U, X86::ST2 },
2657
  { 15U, X86::ST3 },
2658
  { 16U, X86::ST4 },
2659
  { 17U, X86::ST5 },
2660
  { 18U, X86::ST6 },
2661
  { 19U, X86::ST7 },
2662
  { 21U, X86::XMM0 },
2663
  { 22U, X86::XMM1 },
2664
  { 23U, X86::XMM2 },
2665
  { 24U, X86::XMM3 },
2666
  { 25U, X86::XMM4 },
2667
  { 26U, X86::XMM5 },
2668
  { 27U, X86::XMM6 },
2669
  { 28U, X86::XMM7 },
2670
  { 29U, X86::MM0 },
2671
  { 30U, X86::MM1 },
2672
  { 31U, X86::MM2 },
2673
  { 32U, X86::MM3 },
2674
  { 33U, X86::MM4 },
2675
  { 34U, X86::MM5 },
2676
  { 35U, X86::MM6 },
2677
  { 36U, X86::MM7 },
2678
  { 93U, X86::K0 },
2679
  { 94U, X86::K1 },
2680
  { 95U, X86::K2 },
2681
  { 96U, X86::K3 },
2682
  { 97U, X86::K4 },
2683
  { 98U, X86::K5 },
2684
  { 99U, X86::K6 },
2685
  { 100U, X86::K7 },
2686
};
2687
extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L);
2688
2689
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2690
  { 0U, X86::EAX },
2691
  { 1U, X86::ECX },
2692
  { 2U, X86::EDX },
2693
  { 3U, X86::EBX },
2694
  { 4U, X86::ESP },
2695
  { 5U, X86::EBP },
2696
  { 6U, X86::ESI },
2697
  { 7U, X86::EDI },
2698
  { 8U, X86::EIP },
2699
  { 11U, X86::ST0 },
2700
  { 12U, X86::ST1 },
2701
  { 13U, X86::ST2 },
2702
  { 14U, X86::ST3 },
2703
  { 15U, X86::ST4 },
2704
  { 16U, X86::ST5 },
2705
  { 17U, X86::ST6 },
2706
  { 18U, X86::ST7 },
2707
  { 21U, X86::XMM0 },
2708
  { 22U, X86::XMM1 },
2709
  { 23U, X86::XMM2 },
2710
  { 24U, X86::XMM3 },
2711
  { 25U, X86::XMM4 },
2712
  { 26U, X86::XMM5 },
2713
  { 27U, X86::XMM6 },
2714
  { 28U, X86::XMM7 },
2715
  { 29U, X86::MM0 },
2716
  { 30U, X86::MM1 },
2717
  { 31U, X86::MM2 },
2718
  { 32U, X86::MM3 },
2719
  { 33U, X86::MM4 },
2720
  { 34U, X86::MM5 },
2721
  { 35U, X86::MM6 },
2722
  { 36U, X86::MM7 },
2723
  { 93U, X86::K0 },
2724
  { 94U, X86::K1 },
2725
  { 95U, X86::K2 },
2726
  { 96U, X86::K3 },
2727
  { 97U, X86::K4 },
2728
  { 98U, X86::K5 },
2729
  { 99U, X86::K6 },
2730
  { 100U, X86::K7 },
2731
};
2732
extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L);
2733
2734
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2735
  { 0U, X86::RAX },
2736
  { 1U, X86::RDX },
2737
  { 2U, X86::RCX },
2738
  { 3U, X86::RBX },
2739
  { 4U, X86::RSI },
2740
  { 5U, X86::RDI },
2741
  { 6U, X86::RBP },
2742
  { 7U, X86::RSP },
2743
  { 8U, X86::R8 },
2744
  { 9U, X86::R9 },
2745
  { 10U, X86::R10 },
2746
  { 11U, X86::R11 },
2747
  { 12U, X86::R12 },
2748
  { 13U, X86::R13 },
2749
  { 14U, X86::R14 },
2750
  { 15U, X86::R15 },
2751
  { 16U, X86::RIP },
2752
  { 17U, X86::XMM0 },
2753
  { 18U, X86::XMM1 },
2754
  { 19U, X86::XMM2 },
2755
  { 20U, X86::XMM3 },
2756
  { 21U, X86::XMM4 },
2757
  { 22U, X86::XMM5 },
2758
  { 23U, X86::XMM6 },
2759
  { 24U, X86::XMM7 },
2760
  { 25U, X86::XMM8 },
2761
  { 26U, X86::XMM9 },
2762
  { 27U, X86::XMM10 },
2763
  { 28U, X86::XMM11 },
2764
  { 29U, X86::XMM12 },
2765
  { 30U, X86::XMM13 },
2766
  { 31U, X86::XMM14 },
2767
  { 32U, X86::XMM15 },
2768
  { 33U, X86::ST0 },
2769
  { 34U, X86::ST1 },
2770
  { 35U, X86::ST2 },
2771
  { 36U, X86::ST3 },
2772
  { 37U, X86::ST4 },
2773
  { 38U, X86::ST5 },
2774
  { 39U, X86::ST6 },
2775
  { 40U, X86::ST7 },
2776
  { 41U, X86::MM0 },
2777
  { 42U, X86::MM1 },
2778
  { 43U, X86::MM2 },
2779
  { 44U, X86::MM3 },
2780
  { 45U, X86::MM4 },
2781
  { 46U, X86::MM5 },
2782
  { 47U, X86::MM6 },
2783
  { 48U, X86::MM7 },
2784
  { 67U, X86::XMM16 },
2785
  { 68U, X86::XMM17 },
2786
  { 69U, X86::XMM18 },
2787
  { 70U, X86::XMM19 },
2788
  { 71U, X86::XMM20 },
2789
  { 72U, X86::XMM21 },
2790
  { 73U, X86::XMM22 },
2791
  { 74U, X86::XMM23 },
2792
  { 75U, X86::XMM24 },
2793
  { 76U, X86::XMM25 },
2794
  { 77U, X86::XMM26 },
2795
  { 78U, X86::XMM27 },
2796
  { 79U, X86::XMM28 },
2797
  { 80U, X86::XMM29 },
2798
  { 81U, X86::XMM30 },
2799
  { 82U, X86::XMM31 },
2800
  { 118U, X86::K0 },
2801
  { 119U, X86::K1 },
2802
  { 120U, X86::K2 },
2803
  { 121U, X86::K3 },
2804
  { 122U, X86::K4 },
2805
  { 123U, X86::K5 },
2806
  { 124U, X86::K6 },
2807
  { 125U, X86::K7 },
2808
};
2809
extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L);
2810
2811
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2812
  { 0U, X86::EAX },
2813
  { 1U, X86::ECX },
2814
  { 2U, X86::EDX },
2815
  { 3U, X86::EBX },
2816
  { 4U, X86::EBP },
2817
  { 5U, X86::ESP },
2818
  { 6U, X86::ESI },
2819
  { 7U, X86::EDI },
2820
  { 8U, X86::EIP },
2821
  { 12U, X86::ST0 },
2822
  { 13U, X86::ST1 },
2823
  { 14U, X86::ST2 },
2824
  { 15U, X86::ST3 },
2825
  { 16U, X86::ST4 },
2826
  { 17U, X86::ST5 },
2827
  { 18U, X86::ST6 },
2828
  { 19U, X86::ST7 },
2829
  { 21U, X86::XMM0 },
2830
  { 22U, X86::XMM1 },
2831
  { 23U, X86::XMM2 },
2832
  { 24U, X86::XMM3 },
2833
  { 25U, X86::XMM4 },
2834
  { 26U, X86::XMM5 },
2835
  { 27U, X86::XMM6 },
2836
  { 28U, X86::XMM7 },
2837
  { 29U, X86::MM0 },
2838
  { 30U, X86::MM1 },
2839
  { 31U, X86::MM2 },
2840
  { 32U, X86::MM3 },
2841
  { 33U, X86::MM4 },
2842
  { 34U, X86::MM5 },
2843
  { 35U, X86::MM6 },
2844
  { 36U, X86::MM7 },
2845
  { 93U, X86::K0 },
2846
  { 94U, X86::K1 },
2847
  { 95U, X86::K2 },
2848
  { 96U, X86::K3 },
2849
  { 97U, X86::K4 },
2850
  { 98U, X86::K5 },
2851
  { 99U, X86::K6 },
2852
  { 100U, X86::K7 },
2853
};
2854
extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L);
2855
2856
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
2857
  { 0U, X86::EAX },
2858
  { 1U, X86::ECX },
2859
  { 2U, X86::EDX },
2860
  { 3U, X86::EBX },
2861
  { 4U, X86::ESP },
2862
  { 5U, X86::EBP },
2863
  { 6U, X86::ESI },
2864
  { 7U, X86::EDI },
2865
  { 8U, X86::EIP },
2866
  { 11U, X86::ST0 },
2867
  { 12U, X86::ST1 },
2868
  { 13U, X86::ST2 },
2869
  { 14U, X86::ST3 },
2870
  { 15U, X86::ST4 },
2871
  { 16U, X86::ST5 },
2872
  { 17U, X86::ST6 },
2873
  { 18U, X86::ST7 },
2874
  { 21U, X86::XMM0 },
2875
  { 22U, X86::XMM1 },
2876
  { 23U, X86::XMM2 },
2877
  { 24U, X86::XMM3 },
2878
  { 25U, X86::XMM4 },
2879
  { 26U, X86::XMM5 },
2880
  { 27U, X86::XMM6 },
2881
  { 28U, X86::XMM7 },
2882
  { 29U, X86::MM0 },
2883
  { 30U, X86::MM1 },
2884
  { 31U, X86::MM2 },
2885
  { 32U, X86::MM3 },
2886
  { 33U, X86::MM4 },
2887
  { 34U, X86::MM5 },
2888
  { 35U, X86::MM6 },
2889
  { 36U, X86::MM7 },
2890
  { 93U, X86::K0 },
2891
  { 94U, X86::K1 },
2892
  { 95U, X86::K2 },
2893
  { 96U, X86::K3 },
2894
  { 97U, X86::K4 },
2895
  { 98U, X86::K5 },
2896
  { 99U, X86::K6 },
2897
  { 100U, X86::K7 },
2898
};
2899
extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L);
2900
2901
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
2902
  { X86::EAX, -2U },
2903
  { X86::EBP, -2U },
2904
  { X86::EBX, -2U },
2905
  { X86::ECX, -2U },
2906
  { X86::EDI, -2U },
2907
  { X86::EDX, -2U },
2908
  { X86::EIP, -2U },
2909
  { X86::ESI, -2U },
2910
  { X86::ESP, -2U },
2911
  { X86::RAX, 0U },
2912
  { X86::RBP, 6U },
2913
  { X86::RBX, 3U },
2914
  { X86::RCX, 2U },
2915
  { X86::RDI, 5U },
2916
  { X86::RDX, 1U },
2917
  { X86::RIP, 16U },
2918
  { X86::RSI, 4U },
2919
  { X86::RSP, 7U },
2920
  { X86::K0, 118U },
2921
  { X86::K1, 119U },
2922
  { X86::K2, 120U },
2923
  { X86::K3, 121U },
2924
  { X86::K4, 122U },
2925
  { X86::K5, 123U },
2926
  { X86::K6, 124U },
2927
  { X86::K7, 125U },
2928
  { X86::MM0, 41U },
2929
  { X86::MM1, 42U },
2930
  { X86::MM2, 43U },
2931
  { X86::MM3, 44U },
2932
  { X86::MM4, 45U },
2933
  { X86::MM5, 46U },
2934
  { X86::MM6, 47U },
2935
  { X86::MM7, 48U },
2936
  { X86::R8, 8U },
2937
  { X86::R9, 9U },
2938
  { X86::R10, 10U },
2939
  { X86::R11, 11U },
2940
  { X86::R12, 12U },
2941
  { X86::R13, 13U },
2942
  { X86::R14, 14U },
2943
  { X86::R15, 15U },
2944
  { X86::ST0, 33U },
2945
  { X86::ST1, 34U },
2946
  { X86::ST2, 35U },
2947
  { X86::ST3, 36U },
2948
  { X86::ST4, 37U },
2949
  { X86::ST5, 38U },
2950
  { X86::ST6, 39U },
2951
  { X86::ST7, 40U },
2952
  { X86::XMM0, 17U },
2953
  { X86::XMM1, 18U },
2954
  { X86::XMM2, 19U },
2955
  { X86::XMM3, 20U },
2956
  { X86::XMM4, 21U },
2957
  { X86::XMM5, 22U },
2958
  { X86::XMM6, 23U },
2959
  { X86::XMM7, 24U },
2960
  { X86::XMM8, 25U },
2961
  { X86::XMM9, 26U },
2962
  { X86::XMM10, 27U },
2963
  { X86::XMM11, 28U },
2964
  { X86::XMM12, 29U },
2965
  { X86::XMM13, 30U },
2966
  { X86::XMM14, 31U },
2967
  { X86::XMM15, 32U },
2968
  { X86::XMM16, 67U },
2969
  { X86::XMM17, 68U },
2970
  { X86::XMM18, 69U },
2971
  { X86::XMM19, 70U },
2972
  { X86::XMM20, 71U },
2973
  { X86::XMM21, 72U },
2974
  { X86::XMM22, 73U },
2975
  { X86::XMM23, 74U },
2976
  { X86::XMM24, 75U },
2977
  { X86::XMM25, 76U },
2978
  { X86::XMM26, 77U },
2979
  { X86::XMM27, 78U },
2980
  { X86::XMM28, 79U },
2981
  { X86::XMM29, 80U },
2982
  { X86::XMM30, 81U },
2983
  { X86::XMM31, 82U },
2984
  { X86::YMM0, 17U },
2985
  { X86::YMM1, 18U },
2986
  { X86::YMM2, 19U },
2987
  { X86::YMM3, 20U },
2988
  { X86::YMM4, 21U },
2989
  { X86::YMM5, 22U },
2990
  { X86::YMM6, 23U },
2991
  { X86::YMM7, 24U },
2992
  { X86::YMM8, 25U },
2993
  { X86::YMM9, 26U },
2994
  { X86::YMM10, 27U },
2995
  { X86::YMM11, 28U },
2996
  { X86::YMM12, 29U },
2997
  { X86::YMM13, 30U },
2998
  { X86::YMM14, 31U },
2999
  { X86::YMM15, 32U },
3000
  { X86::YMM16, 67U },
3001
  { X86::YMM17, 68U },
3002
  { X86::YMM18, 69U },
3003
  { X86::YMM19, 70U },
3004
  { X86::YMM20, 71U },
3005
  { X86::YMM21, 72U },
3006
  { X86::YMM22, 73U },
3007
  { X86::YMM23, 74U },
3008
  { X86::YMM24, 75U },
3009
  { X86::YMM25, 76U },
3010
  { X86::YMM26, 77U },
3011
  { X86::YMM27, 78U },
3012
  { X86::YMM28, 79U },
3013
  { X86::YMM29, 80U },
3014
  { X86::YMM30, 81U },
3015
  { X86::YMM31, 82U },
3016
  { X86::ZMM0, 17U },
3017
  { X86::ZMM1, 18U },
3018
  { X86::ZMM2, 19U },
3019
  { X86::ZMM3, 20U },
3020
  { X86::ZMM4, 21U },
3021
  { X86::ZMM5, 22U },
3022
  { X86::ZMM6, 23U },
3023
  { X86::ZMM7, 24U },
3024
  { X86::ZMM8, 25U },
3025
  { X86::ZMM9, 26U },
3026
  { X86::ZMM10, 27U },
3027
  { X86::ZMM11, 28U },
3028
  { X86::ZMM12, 29U },
3029
  { X86::ZMM13, 30U },
3030
  { X86::ZMM14, 31U },
3031
  { X86::ZMM15, 32U },
3032
  { X86::ZMM16, 67U },
3033
  { X86::ZMM17, 68U },
3034
  { X86::ZMM18, 69U },
3035
  { X86::ZMM19, 70U },
3036
  { X86::ZMM20, 71U },
3037
  { X86::ZMM21, 72U },
3038
  { X86::ZMM22, 73U },
3039
  { X86::ZMM23, 74U },
3040
  { X86::ZMM24, 75U },
3041
  { X86::ZMM25, 76U },
3042
  { X86::ZMM26, 77U },
3043
  { X86::ZMM27, 78U },
3044
  { X86::ZMM28, 79U },
3045
  { X86::ZMM29, 80U },
3046
  { X86::ZMM30, 81U },
3047
  { X86::ZMM31, 82U },
3048
};
3049
extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf);
3050
3051
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3052
  { X86::EAX, 0U },
3053
  { X86::EBP, 4U },
3054
  { X86::EBX, 3U },
3055
  { X86::ECX, 1U },
3056
  { X86::EDI, 7U },
3057
  { X86::EDX, 2U },
3058
  { X86::EIP, 8U },
3059
  { X86::ESI, 6U },
3060
  { X86::ESP, 5U },
3061
  { X86::RAX, -2U },
3062
  { X86::RBP, -2U },
3063
  { X86::RBX, -2U },
3064
  { X86::RCX, -2U },
3065
  { X86::RDI, -2U },
3066
  { X86::RDX, -2U },
3067
  { X86::RIP, -2U },
3068
  { X86::RSI, -2U },
3069
  { X86::RSP, -2U },
3070
  { X86::K0, 93U },
3071
  { X86::K1, 94U },
3072
  { X86::K2, 95U },
3073
  { X86::K3, 96U },
3074
  { X86::K4, 97U },
3075
  { X86::K5, 98U },
3076
  { X86::K6, 99U },
3077
  { X86::K7, 100U },
3078
  { X86::MM0, 29U },
3079
  { X86::MM1, 30U },
3080
  { X86::MM2, 31U },
3081
  { X86::MM3, 32U },
3082
  { X86::MM4, 33U },
3083
  { X86::MM5, 34U },
3084
  { X86::MM6, 35U },
3085
  { X86::MM7, 36U },
3086
  { X86::R8, -2U },
3087
  { X86::R9, -2U },
3088
  { X86::R10, -2U },
3089
  { X86::R11, -2U },
3090
  { X86::R12, -2U },
3091
  { X86::R13, -2U },
3092
  { X86::R14, -2U },
3093
  { X86::R15, -2U },
3094
  { X86::ST0, 12U },
3095
  { X86::ST1, 13U },
3096
  { X86::ST2, 14U },
3097
  { X86::ST3, 15U },
3098
  { X86::ST4, 16U },
3099
  { X86::ST5, 17U },
3100
  { X86::ST6, 18U },
3101
  { X86::ST7, 19U },
3102
  { X86::XMM0, 21U },
3103
  { X86::XMM1, 22U },
3104
  { X86::XMM2, 23U },
3105
  { X86::XMM3, 24U },
3106
  { X86::XMM4, 25U },
3107
  { X86::XMM5, 26U },
3108
  { X86::XMM6, 27U },
3109
  { X86::XMM7, 28U },
3110
  { X86::XMM8, -2U },
3111
  { X86::XMM9, -2U },
3112
  { X86::XMM10, -2U },
3113
  { X86::XMM11, -2U },
3114
  { X86::XMM12, -2U },
3115
  { X86::XMM13, -2U },
3116
  { X86::XMM14, -2U },
3117
  { X86::XMM15, -2U },
3118
  { X86::XMM16, -2U },
3119
  { X86::XMM17, -2U },
3120
  { X86::XMM18, -2U },
3121
  { X86::XMM19, -2U },
3122
  { X86::XMM20, -2U },
3123
  { X86::XMM21, -2U },
3124
  { X86::XMM22, -2U },
3125
  { X86::XMM23, -2U },
3126
  { X86::XMM24, -2U },
3127
  { X86::XMM25, -2U },
3128
  { X86::XMM26, -2U },
3129
  { X86::XMM27, -2U },
3130
  { X86::XMM28, -2U },
3131
  { X86::XMM29, -2U },
3132
  { X86::XMM30, -2U },
3133
  { X86::XMM31, -2U },
3134
  { X86::YMM0, 21U },
3135
  { X86::YMM1, 22U },
3136
  { X86::YMM2, 23U },
3137
  { X86::YMM3, 24U },
3138
  { X86::YMM4, 25U },
3139
  { X86::YMM5, 26U },
3140
  { X86::YMM6, 27U },
3141
  { X86::YMM7, 28U },
3142
  { X86::YMM8, -2U },
3143
  { X86::YMM9, -2U },
3144
  { X86::YMM10, -2U },
3145
  { X86::YMM11, -2U },
3146
  { X86::YMM12, -2U },
3147
  { X86::YMM13, -2U },
3148
  { X86::YMM14, -2U },
3149
  { X86::YMM15, -2U },
3150
  { X86::YMM16, -2U },
3151
  { X86::YMM17, -2U },
3152
  { X86::YMM18, -2U },
3153
  { X86::YMM19, -2U },
3154
  { X86::YMM20, -2U },
3155
  { X86::YMM21, -2U },
3156
  { X86::YMM22, -2U },
3157
  { X86::YMM23, -2U },
3158
  { X86::YMM24, -2U },
3159
  { X86::YMM25, -2U },
3160
  { X86::YMM26, -2U },
3161
  { X86::YMM27, -2U },
3162
  { X86::YMM28, -2U },
3163
  { X86::YMM29, -2U },
3164
  { X86::YMM30, -2U },
3165
  { X86::YMM31, -2U },
3166
  { X86::ZMM0, 21U },
3167
  { X86::ZMM1, 22U },
3168
  { X86::ZMM2, 23U },
3169
  { X86::ZMM3, 24U },
3170
  { X86::ZMM4, 25U },
3171
  { X86::ZMM5, 26U },
3172
  { X86::ZMM6, 27U },
3173
  { X86::ZMM7, 28U },
3174
  { X86::ZMM8, -2U },
3175
  { X86::ZMM9, -2U },
3176
  { X86::ZMM10, -2U },
3177
  { X86::ZMM11, -2U },
3178
  { X86::ZMM12, -2U },
3179
  { X86::ZMM13, -2U },
3180
  { X86::ZMM14, -2U },
3181
  { X86::ZMM15, -2U },
3182
  { X86::ZMM16, -2U },
3183
  { X86::ZMM17, -2U },
3184
  { X86::ZMM18, -2U },
3185
  { X86::ZMM19, -2U },
3186
  { X86::ZMM20, -2U },
3187
  { X86::ZMM21, -2U },
3188
  { X86::ZMM22, -2U },
3189
  { X86::ZMM23, -2U },
3190
  { X86::ZMM24, -2U },
3191
  { X86::ZMM25, -2U },
3192
  { X86::ZMM26, -2U },
3193
  { X86::ZMM27, -2U },
3194
  { X86::ZMM28, -2U },
3195
  { X86::ZMM29, -2U },
3196
  { X86::ZMM30, -2U },
3197
  { X86::ZMM31, -2U },
3198
};
3199
extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf);
3200
3201
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3202
  { X86::EAX, 0U },
3203
  { X86::EBP, 5U },
3204
  { X86::EBX, 3U },
3205
  { X86::ECX, 1U },
3206
  { X86::EDI, 7U },
3207
  { X86::EDX, 2U },
3208
  { X86::EIP, 8U },
3209
  { X86::ESI, 6U },
3210
  { X86::ESP, 4U },
3211
  { X86::RAX, -2U },
3212
  { X86::RBP, -2U },
3213
  { X86::RBX, -2U },
3214
  { X86::RCX, -2U },
3215
  { X86::RDI, -2U },
3216
  { X86::RDX, -2U },
3217
  { X86::RIP, -2U },
3218
  { X86::RSI, -2U },
3219
  { X86::RSP, -2U },
3220
  { X86::K0, 93U },
3221
  { X86::K1, 94U },
3222
  { X86::K2, 95U },
3223
  { X86::K3, 96U },
3224
  { X86::K4, 97U },
3225
  { X86::K5, 98U },
3226
  { X86::K6, 99U },
3227
  { X86::K7, 100U },
3228
  { X86::MM0, 29U },
3229
  { X86::MM1, 30U },
3230
  { X86::MM2, 31U },
3231
  { X86::MM3, 32U },
3232
  { X86::MM4, 33U },
3233
  { X86::MM5, 34U },
3234
  { X86::MM6, 35U },
3235
  { X86::MM7, 36U },
3236
  { X86::R8, -2U },
3237
  { X86::R9, -2U },
3238
  { X86::R10, -2U },
3239
  { X86::R11, -2U },
3240
  { X86::R12, -2U },
3241
  { X86::R13, -2U },
3242
  { X86::R14, -2U },
3243
  { X86::R15, -2U },
3244
  { X86::ST0, 11U },
3245
  { X86::ST1, 12U },
3246
  { X86::ST2, 13U },
3247
  { X86::ST3, 14U },
3248
  { X86::ST4, 15U },
3249
  { X86::ST5, 16U },
3250
  { X86::ST6, 17U },
3251
  { X86::ST7, 18U },
3252
  { X86::XMM0, 21U },
3253
  { X86::XMM1, 22U },
3254
  { X86::XMM2, 23U },
3255
  { X86::XMM3, 24U },
3256
  { X86::XMM4, 25U },
3257
  { X86::XMM5, 26U },
3258
  { X86::XMM6, 27U },
3259
  { X86::XMM7, 28U },
3260
  { X86::XMM8, -2U },
3261
  { X86::XMM9, -2U },
3262
  { X86::XMM10, -2U },
3263
  { X86::XMM11, -2U },
3264
  { X86::XMM12, -2U },
3265
  { X86::XMM13, -2U },
3266
  { X86::XMM14, -2U },
3267
  { X86::XMM15, -2U },
3268
  { X86::XMM16, -2U },
3269
  { X86::XMM17, -2U },
3270
  { X86::XMM18, -2U },
3271
  { X86::XMM19, -2U },
3272
  { X86::XMM20, -2U },
3273
  { X86::XMM21, -2U },
3274
  { X86::XMM22, -2U },
3275
  { X86::XMM23, -2U },
3276
  { X86::XMM24, -2U },
3277
  { X86::XMM25, -2U },
3278
  { X86::XMM26, -2U },
3279
  { X86::XMM27, -2U },
3280
  { X86::XMM28, -2U },
3281
  { X86::XMM29, -2U },
3282
  { X86::XMM30, -2U },
3283
  { X86::XMM31, -2U },
3284
  { X86::YMM0, 21U },
3285
  { X86::YMM1, 22U },
3286
  { X86::YMM2, 23U },
3287
  { X86::YMM3, 24U },
3288
  { X86::YMM4, 25U },
3289
  { X86::YMM5, 26U },
3290
  { X86::YMM6, 27U },
3291
  { X86::YMM7, 28U },
3292
  { X86::YMM8, -2U },
3293
  { X86::YMM9, -2U },
3294
  { X86::YMM10, -2U },
3295
  { X86::YMM11, -2U },
3296
  { X86::YMM12, -2U },
3297
  { X86::YMM13, -2U },
3298
  { X86::YMM14, -2U },
3299
  { X86::YMM15, -2U },
3300
  { X86::YMM16, -2U },
3301
  { X86::YMM17, -2U },
3302
  { X86::YMM18, -2U },
3303
  { X86::YMM19, -2U },
3304
  { X86::YMM20, -2U },
3305
  { X86::YMM21, -2U },
3306
  { X86::YMM22, -2U },
3307
  { X86::YMM23, -2U },
3308
  { X86::YMM24, -2U },
3309
  { X86::YMM25, -2U },
3310
  { X86::YMM26, -2U },
3311
  { X86::YMM27, -2U },
3312
  { X86::YMM28, -2U },
3313
  { X86::YMM29, -2U },
3314
  { X86::YMM30, -2U },
3315
  { X86::YMM31, -2U },
3316
  { X86::ZMM0, 21U },
3317
  { X86::ZMM1, 22U },
3318
  { X86::ZMM2, 23U },
3319
  { X86::ZMM3, 24U },
3320
  { X86::ZMM4, 25U },
3321
  { X86::ZMM5, 26U },
3322
  { X86::ZMM6, 27U },
3323
  { X86::ZMM7, 28U },
3324
  { X86::ZMM8, -2U },
3325
  { X86::ZMM9, -2U },
3326
  { X86::ZMM10, -2U },
3327
  { X86::ZMM11, -2U },
3328
  { X86::ZMM12, -2U },
3329
  { X86::ZMM13, -2U },
3330
  { X86::ZMM14, -2U },
3331
  { X86::ZMM15, -2U },
3332
  { X86::ZMM16, -2U },
3333
  { X86::ZMM17, -2U },
3334
  { X86::ZMM18, -2U },
3335
  { X86::ZMM19, -2U },
3336
  { X86::ZMM20, -2U },
3337
  { X86::ZMM21, -2U },
3338
  { X86::ZMM22, -2U },
3339
  { X86::ZMM23, -2U },
3340
  { X86::ZMM24, -2U },
3341
  { X86::ZMM25, -2U },
3342
  { X86::ZMM26, -2U },
3343
  { X86::ZMM27, -2U },
3344
  { X86::ZMM28, -2U },
3345
  { X86::ZMM29, -2U },
3346
  { X86::ZMM30, -2U },
3347
  { X86::ZMM31, -2U },
3348
};
3349
extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf);
3350
3351
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3352
  { X86::EAX, -2U },
3353
  { X86::EBP, -2U },
3354
  { X86::EBX, -2U },
3355
  { X86::ECX, -2U },
3356
  { X86::EDI, -2U },
3357
  { X86::EDX, -2U },
3358
  { X86::EIP, -2U },
3359
  { X86::ESI, -2U },
3360
  { X86::ESP, -2U },
3361
  { X86::RAX, 0U },
3362
  { X86::RBP, 6U },
3363
  { X86::RBX, 3U },
3364
  { X86::RCX, 2U },
3365
  { X86::RDI, 5U },
3366
  { X86::RDX, 1U },
3367
  { X86::RIP, 16U },
3368
  { X86::RSI, 4U },
3369
  { X86::RSP, 7U },
3370
  { X86::K0, 118U },
3371
  { X86::K1, 119U },
3372
  { X86::K2, 120U },
3373
  { X86::K3, 121U },
3374
  { X86::K4, 122U },
3375
  { X86::K5, 123U },
3376
  { X86::K6, 124U },
3377
  { X86::K7, 125U },
3378
  { X86::MM0, 41U },
3379
  { X86::MM1, 42U },
3380
  { X86::MM2, 43U },
3381
  { X86::MM3, 44U },
3382
  { X86::MM4, 45U },
3383
  { X86::MM5, 46U },
3384
  { X86::MM6, 47U },
3385
  { X86::MM7, 48U },
3386
  { X86::R8, 8U },
3387
  { X86::R9, 9U },
3388
  { X86::R10, 10U },
3389
  { X86::R11, 11U },
3390
  { X86::R12, 12U },
3391
  { X86::R13, 13U },
3392
  { X86::R14, 14U },
3393
  { X86::R15, 15U },
3394
  { X86::ST0, 33U },
3395
  { X86::ST1, 34U },
3396
  { X86::ST2, 35U },
3397
  { X86::ST3, 36U },
3398
  { X86::ST4, 37U },
3399
  { X86::ST5, 38U },
3400
  { X86::ST6, 39U },
3401
  { X86::ST7, 40U },
3402
  { X86::XMM0, 17U },
3403
  { X86::XMM1, 18U },
3404
  { X86::XMM2, 19U },
3405
  { X86::XMM3, 20U },
3406
  { X86::XMM4, 21U },
3407
  { X86::XMM5, 22U },
3408
  { X86::XMM6, 23U },
3409
  { X86::XMM7, 24U },
3410
  { X86::XMM8, 25U },
3411
  { X86::XMM9, 26U },
3412
  { X86::XMM10, 27U },
3413
  { X86::XMM11, 28U },
3414
  { X86::XMM12, 29U },
3415
  { X86::XMM13, 30U },
3416
  { X86::XMM14, 31U },
3417
  { X86::XMM15, 32U },
3418
  { X86::XMM16, 67U },
3419
  { X86::XMM17, 68U },
3420
  { X86::XMM18, 69U },
3421
  { X86::XMM19, 70U },
3422
  { X86::XMM20, 71U },
3423
  { X86::XMM21, 72U },
3424
  { X86::XMM22, 73U },
3425
  { X86::XMM23, 74U },
3426
  { X86::XMM24, 75U },
3427
  { X86::XMM25, 76U },
3428
  { X86::XMM26, 77U },
3429
  { X86::XMM27, 78U },
3430
  { X86::XMM28, 79U },
3431
  { X86::XMM29, 80U },
3432
  { X86::XMM30, 81U },
3433
  { X86::XMM31, 82U },
3434
  { X86::YMM0, 17U },
3435
  { X86::YMM1, 18U },
3436
  { X86::YMM2, 19U },
3437
  { X86::YMM3, 20U },
3438
  { X86::YMM4, 21U },
3439
  { X86::YMM5, 22U },
3440
  { X86::YMM6, 23U },
3441
  { X86::YMM7, 24U },
3442
  { X86::YMM8, 25U },
3443
  { X86::YMM9, 26U },
3444
  { X86::YMM10, 27U },
3445
  { X86::YMM11, 28U },
3446
  { X86::YMM12, 29U },
3447
  { X86::YMM13, 30U },
3448
  { X86::YMM14, 31U },
3449
  { X86::YMM15, 32U },
3450
  { X86::YMM16, 67U },
3451
  { X86::YMM17, 68U },
3452
  { X86::YMM18, 69U },
3453
  { X86::YMM19, 70U },
3454
  { X86::YMM20, 71U },
3455
  { X86::YMM21, 72U },
3456
  { X86::YMM22, 73U },
3457
  { X86::YMM23, 74U },
3458
  { X86::YMM24, 75U },
3459
  { X86::YMM25, 76U },
3460
  { X86::YMM26, 77U },
3461
  { X86::YMM27, 78U },
3462
  { X86::YMM28, 79U },
3463
  { X86::YMM29, 80U },
3464
  { X86::YMM30, 81U },
3465
  { X86::YMM31, 82U },
3466
  { X86::ZMM0, 17U },
3467
  { X86::ZMM1, 18U },
3468
  { X86::ZMM2, 19U },
3469
  { X86::ZMM3, 20U },
3470
  { X86::ZMM4, 21U },
3471
  { X86::ZMM5, 22U },
3472
  { X86::ZMM6, 23U },
3473
  { X86::ZMM7, 24U },
3474
  { X86::ZMM8, 25U },
3475
  { X86::ZMM9, 26U },
3476
  { X86::ZMM10, 27U },
3477
  { X86::ZMM11, 28U },
3478
  { X86::ZMM12, 29U },
3479
  { X86::ZMM13, 30U },
3480
  { X86::ZMM14, 31U },
3481
  { X86::ZMM15, 32U },
3482
  { X86::ZMM16, 67U },
3483
  { X86::ZMM17, 68U },
3484
  { X86::ZMM18, 69U },
3485
  { X86::ZMM19, 70U },
3486
  { X86::ZMM20, 71U },
3487
  { X86::ZMM21, 72U },
3488
  { X86::ZMM22, 73U },
3489
  { X86::ZMM23, 74U },
3490
  { X86::ZMM24, 75U },
3491
  { X86::ZMM25, 76U },
3492
  { X86::ZMM26, 77U },
3493
  { X86::ZMM27, 78U },
3494
  { X86::ZMM28, 79U },
3495
  { X86::ZMM29, 80U },
3496
  { X86::ZMM30, 81U },
3497
  { X86::ZMM31, 82U },
3498
};
3499
extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf);
3500
3501
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3502
  { X86::EAX, 0U },
3503
  { X86::EBP, 4U },
3504
  { X86::EBX, 3U },
3505
  { X86::ECX, 1U },
3506
  { X86::EDI, 7U },
3507
  { X86::EDX, 2U },
3508
  { X86::EIP, 8U },
3509
  { X86::ESI, 6U },
3510
  { X86::ESP, 5U },
3511
  { X86::RAX, -2U },
3512
  { X86::RBP, -2U },
3513
  { X86::RBX, -2U },
3514
  { X86::RCX, -2U },
3515
  { X86::RDI, -2U },
3516
  { X86::RDX, -2U },
3517
  { X86::RIP, -2U },
3518
  { X86::RSI, -2U },
3519
  { X86::RSP, -2U },
3520
  { X86::K0, 93U },
3521
  { X86::K1, 94U },
3522
  { X86::K2, 95U },
3523
  { X86::K3, 96U },
3524
  { X86::K4, 97U },
3525
  { X86::K5, 98U },
3526
  { X86::K6, 99U },
3527
  { X86::K7, 100U },
3528
  { X86::MM0, 29U },
3529
  { X86::MM1, 30U },
3530
  { X86::MM2, 31U },
3531
  { X86::MM3, 32U },
3532
  { X86::MM4, 33U },
3533
  { X86::MM5, 34U },
3534
  { X86::MM6, 35U },
3535
  { X86::MM7, 36U },
3536
  { X86::R8, -2U },
3537
  { X86::R9, -2U },
3538
  { X86::R10, -2U },
3539
  { X86::R11, -2U },
3540
  { X86::R12, -2U },
3541
  { X86::R13, -2U },
3542
  { X86::R14, -2U },
3543
  { X86::R15, -2U },
3544
  { X86::ST0, 12U },
3545
  { X86::ST1, 13U },
3546
  { X86::ST2, 14U },
3547
  { X86::ST3, 15U },
3548
  { X86::ST4, 16U },
3549
  { X86::ST5, 17U },
3550
  { X86::ST6, 18U },
3551
  { X86::ST7, 19U },
3552
  { X86::XMM0, 21U },
3553
  { X86::XMM1, 22U },
3554
  { X86::XMM2, 23U },
3555
  { X86::XMM3, 24U },
3556
  { X86::XMM4, 25U },
3557
  { X86::XMM5, 26U },
3558
  { X86::XMM6, 27U },
3559
  { X86::XMM7, 28U },
3560
  { X86::XMM8, -2U },
3561
  { X86::XMM9, -2U },
3562
  { X86::XMM10, -2U },
3563
  { X86::XMM11, -2U },
3564
  { X86::XMM12, -2U },
3565
  { X86::XMM13, -2U },
3566
  { X86::XMM14, -2U },
3567
  { X86::XMM15, -2U },
3568
  { X86::XMM16, -2U },
3569
  { X86::XMM17, -2U },
3570
  { X86::XMM18, -2U },
3571
  { X86::XMM19, -2U },
3572
  { X86::XMM20, -2U },
3573
  { X86::XMM21, -2U },
3574
  { X86::XMM22, -2U },
3575
  { X86::XMM23, -2U },
3576
  { X86::XMM24, -2U },
3577
  { X86::XMM25, -2U },
3578
  { X86::XMM26, -2U },
3579
  { X86::XMM27, -2U },
3580
  { X86::XMM28, -2U },
3581
  { X86::XMM29, -2U },
3582
  { X86::XMM30, -2U },
3583
  { X86::XMM31, -2U },
3584
  { X86::YMM0, 21U },
3585
  { X86::YMM1, 22U },
3586
  { X86::YMM2, 23U },
3587
  { X86::YMM3, 24U },
3588
  { X86::YMM4, 25U },
3589
  { X86::YMM5, 26U },
3590
  { X86::YMM6, 27U },
3591
  { X86::YMM7, 28U },
3592
  { X86::YMM8, -2U },
3593
  { X86::YMM9, -2U },
3594
  { X86::YMM10, -2U },
3595
  { X86::YMM11, -2U },
3596
  { X86::YMM12, -2U },
3597
  { X86::YMM13, -2U },
3598
  { X86::YMM14, -2U },
3599
  { X86::YMM15, -2U },
3600
  { X86::YMM16, -2U },
3601
  { X86::YMM17, -2U },
3602
  { X86::YMM18, -2U },
3603
  { X86::YMM19, -2U },
3604
  { X86::YMM20, -2U },
3605
  { X86::YMM21, -2U },
3606
  { X86::YMM22, -2U },
3607
  { X86::YMM23, -2U },
3608
  { X86::YMM24, -2U },
3609
  { X86::YMM25, -2U },
3610
  { X86::YMM26, -2U },
3611
  { X86::YMM27, -2U },
3612
  { X86::YMM28, -2U },
3613
  { X86::YMM29, -2U },
3614
  { X86::YMM30, -2U },
3615
  { X86::YMM31, -2U },
3616
  { X86::ZMM0, 21U },
3617
  { X86::ZMM1, 22U },
3618
  { X86::ZMM2, 23U },
3619
  { X86::ZMM3, 24U },
3620
  { X86::ZMM4, 25U },
3621
  { X86::ZMM5, 26U },
3622
  { X86::ZMM6, 27U },
3623
  { X86::ZMM7, 28U },
3624
  { X86::ZMM8, -2U },
3625
  { X86::ZMM9, -2U },
3626
  { X86::ZMM10, -2U },
3627
  { X86::ZMM11, -2U },
3628
  { X86::ZMM12, -2U },
3629
  { X86::ZMM13, -2U },
3630
  { X86::ZMM14, -2U },
3631
  { X86::ZMM15, -2U },
3632
  { X86::ZMM16, -2U },
3633
  { X86::ZMM17, -2U },
3634
  { X86::ZMM18, -2U },
3635
  { X86::ZMM19, -2U },
3636
  { X86::ZMM20, -2U },
3637
  { X86::ZMM21, -2U },
3638
  { X86::ZMM22, -2U },
3639
  { X86::ZMM23, -2U },
3640
  { X86::ZMM24, -2U },
3641
  { X86::ZMM25, -2U },
3642
  { X86::ZMM26, -2U },
3643
  { X86::ZMM27, -2U },
3644
  { X86::ZMM28, -2U },
3645
  { X86::ZMM29, -2U },
3646
  { X86::ZMM30, -2U },
3647
  { X86::ZMM31, -2U },
3648
};
3649
extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf);
3650
3651
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3652
  { X86::EAX, 0U },
3653
  { X86::EBP, 5U },
3654
  { X86::EBX, 3U },
3655
  { X86::ECX, 1U },
3656
  { X86::EDI, 7U },
3657
  { X86::EDX, 2U },
3658
  { X86::EIP, 8U },
3659
  { X86::ESI, 6U },
3660
  { X86::ESP, 4U },
3661
  { X86::RAX, -2U },
3662
  { X86::RBP, -2U },
3663
  { X86::RBX, -2U },
3664
  { X86::RCX, -2U },
3665
  { X86::RDI, -2U },
3666
  { X86::RDX, -2U },
3667
  { X86::RIP, -2U },
3668
  { X86::RSI, -2U },
3669
  { X86::RSP, -2U },
3670
  { X86::K0, 93U },
3671
  { X86::K1, 94U },
3672
  { X86::K2, 95U },
3673
  { X86::K3, 96U },
3674
  { X86::K4, 97U },
3675
  { X86::K5, 98U },
3676
  { X86::K6, 99U },
3677
  { X86::K7, 100U },
3678
  { X86::MM0, 29U },
3679
  { X86::MM1, 30U },
3680
  { X86::MM2, 31U },
3681
  { X86::MM3, 32U },
3682
  { X86::MM4, 33U },
3683
  { X86::MM5, 34U },
3684
  { X86::MM6, 35U },
3685
  { X86::MM7, 36U },
3686
  { X86::R8, -2U },
3687
  { X86::R9, -2U },
3688
  { X86::R10, -2U },
3689
  { X86::R11, -2U },
3690
  { X86::R12, -2U },
3691
  { X86::R13, -2U },
3692
  { X86::R14, -2U },
3693
  { X86::R15, -2U },
3694
  { X86::ST0, 11U },
3695
  { X86::ST1, 12U },
3696
  { X86::ST2, 13U },
3697
  { X86::ST3, 14U },
3698
  { X86::ST4, 15U },
3699
  { X86::ST5, 16U },
3700
  { X86::ST6, 17U },
3701
  { X86::ST7, 18U },
3702
  { X86::XMM0, 21U },
3703
  { X86::XMM1, 22U },
3704
  { X86::XMM2, 23U },
3705
  { X86::XMM3, 24U },
3706
  { X86::XMM4, 25U },
3707
  { X86::XMM5, 26U },
3708
  { X86::XMM6, 27U },
3709
  { X86::XMM7, 28U },
3710
  { X86::XMM8, -2U },
3711
  { X86::XMM9, -2U },
3712
  { X86::XMM10, -2U },
3713
  { X86::XMM11, -2U },
3714
  { X86::XMM12, -2U },
3715
  { X86::XMM13, -2U },
3716
  { X86::XMM14, -2U },
3717
  { X86::XMM15, -2U },
3718
  { X86::XMM16, -2U },
3719
  { X86::XMM17, -2U },
3720
  { X86::XMM18, -2U },
3721
  { X86::XMM19, -2U },
3722
  { X86::XMM20, -2U },
3723
  { X86::XMM21, -2U },
3724
  { X86::XMM22, -2U },
3725
  { X86::XMM23, -2U },
3726
  { X86::XMM24, -2U },
3727
  { X86::XMM25, -2U },
3728
  { X86::XMM26, -2U },
3729
  { X86::XMM27, -2U },
3730
  { X86::XMM28, -2U },
3731
  { X86::XMM29, -2U },
3732
  { X86::XMM30, -2U },
3733
  { X86::XMM31, -2U },
3734
  { X86::YMM0, 21U },
3735
  { X86::YMM1, 22U },
3736
  { X86::YMM2, 23U },
3737
  { X86::YMM3, 24U },
3738
  { X86::YMM4, 25U },
3739
  { X86::YMM5, 26U },
3740
  { X86::YMM6, 27U },
3741
  { X86::YMM7, 28U },
3742
  { X86::YMM8, -2U },
3743
  { X86::YMM9, -2U },
3744
  { X86::YMM10, -2U },
3745
  { X86::YMM11, -2U },
3746
  { X86::YMM12, -2U },
3747
  { X86::YMM13, -2U },
3748
  { X86::YMM14, -2U },
3749
  { X86::YMM15, -2U },
3750
  { X86::YMM16, -2U },
3751
  { X86::YMM17, -2U },
3752
  { X86::YMM18, -2U },
3753
  { X86::YMM19, -2U },
3754
  { X86::YMM20, -2U },
3755
  { X86::YMM21, -2U },
3756
  { X86::YMM22, -2U },
3757
  { X86::YMM23, -2U },
3758
  { X86::YMM24, -2U },
3759
  { X86::YMM25, -2U },
3760
  { X86::YMM26, -2U },
3761
  { X86::YMM27, -2U },
3762
  { X86::YMM28, -2U },
3763
  { X86::YMM29, -2U },
3764
  { X86::YMM30, -2U },
3765
  { X86::YMM31, -2U },
3766
  { X86::ZMM0, 21U },
3767
  { X86::ZMM1, 22U },
3768
  { X86::ZMM2, 23U },
3769
  { X86::ZMM3, 24U },
3770
  { X86::ZMM4, 25U },
3771
  { X86::ZMM5, 26U },
3772
  { X86::ZMM6, 27U },
3773
  { X86::ZMM7, 28U },
3774
  { X86::ZMM8, -2U },
3775
  { X86::ZMM9, -2U },
3776
  { X86::ZMM10, -2U },
3777
  { X86::ZMM11, -2U },
3778
  { X86::ZMM12, -2U },
3779
  { X86::ZMM13, -2U },
3780
  { X86::ZMM14, -2U },
3781
  { X86::ZMM15, -2U },
3782
  { X86::ZMM16, -2U },
3783
  { X86::ZMM17, -2U },
3784
  { X86::ZMM18, -2U },
3785
  { X86::ZMM19, -2U },
3786
  { X86::ZMM20, -2U },
3787
  { X86::ZMM21, -2U },
3788
  { X86::ZMM22, -2U },
3789
  { X86::ZMM23, -2U },
3790
  { X86::ZMM24, -2U },
3791
  { X86::ZMM25, -2U },
3792
  { X86::ZMM26, -2U },
3793
  { X86::ZMM27, -2U },
3794
  { X86::ZMM28, -2U },
3795
  { X86::ZMM29, -2U },
3796
  { X86::ZMM30, -2U },
3797
  { X86::ZMM31, -2U },
3798
};
3799
extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf);
3800
3801
extern const uint16_t X86RegEncodingTable[] = {
3802
  0,
3803
  4,
3804
  0,
3805
  0,
3806
  7,
3807
  3,
3808
  5,
3809
  65535,
3810
  5,
3811
  3,
3812
  5,
3813
  1,
3814
  1,
3815
  1,
3816
  0,
3817
  6,
3818
  7,
3819
  65535,
3820
  7,
3821
  2,
3822
  3,
3823
  2,
3824
  0,
3825
  5,
3826
  3,
3827
  1,
3828
  7,
3829
  2,
3830
  0,
3831
  0,
3832
  4,
3833
  0,
3834
  6,
3835
  4,
3836
  0,
3837
  4,
3838
  5,
3839
  65535,
3840
  65535,
3841
  65535,
3842
  65535,
3843
  65535,
3844
  65535,
3845
  65535,
3846
  65535,
3847
  65535,
3848
  0,
3849
  0,
3850
  5,
3851
  3,
3852
  1,
3853
  7,
3854
  2,
3855
  0,
3856
  4,
3857
  6,
3858
  4,
3859
  6,
3860
  65535,
3861
  6,
3862
  4,
3863
  65535,
3864
  4,
3865
  2,
3866
  0,
3867
  0,
3868
  1,
3869
  2,
3870
  3,
3871
  0,
3872
  1,
3873
  2,
3874
  3,
3875
  4,
3876
  5,
3877
  6,
3878
  7,
3879
  8,
3880
  9,
3881
  10,
3882
  11,
3883
  12,
3884
  13,
3885
  14,
3886
  15,
3887
  0,
3888
  1,
3889
  2,
3890
  3,
3891
  4,
3892
  5,
3893
  6,
3894
  7,
3895
  8,
3896
  9,
3897
  10,
3898
  11,
3899
  12,
3900
  13,
3901
  14,
3902
  15,
3903
  0,
3904
  0,
3905
  0,
3906
  0,
3907
  0,
3908
  0,
3909
  0,
3910
  0,
3911
  0,
3912
  1,
3913
  2,
3914
  3,
3915
  4,
3916
  5,
3917
  6,
3918
  7,
3919
  0,
3920
  1,
3921
  2,
3922
  3,
3923
  4,
3924
  5,
3925
  6,
3926
  7,
3927
  8,
3928
  9,
3929
  10,
3930
  11,
3931
  12,
3932
  13,
3933
  14,
3934
  15,
3935
  0,
3936
  1,
3937
  2,
3938
  3,
3939
  4,
3940
  5,
3941
  6,
3942
  7,
3943
  0,
3944
  1,
3945
  2,
3946
  3,
3947
  4,
3948
  5,
3949
  6,
3950
  7,
3951
  8,
3952
  9,
3953
  10,
3954
  11,
3955
  12,
3956
  13,
3957
  14,
3958
  15,
3959
  16,
3960
  17,
3961
  18,
3962
  19,
3963
  20,
3964
  21,
3965
  22,
3966
  23,
3967
  24,
3968
  25,
3969
  26,
3970
  27,
3971
  28,
3972
  29,
3973
  30,
3974
  31,
3975
  0,
3976
  1,
3977
  2,
3978
  3,
3979
  4,
3980
  5,
3981
  6,
3982
  7,
3983
  8,
3984
  9,
3985
  10,
3986
  11,
3987
  12,
3988
  13,
3989
  14,
3990
  15,
3991
  16,
3992
  17,
3993
  18,
3994
  19,
3995
  20,
3996
  21,
3997
  22,
3998
  23,
3999
  24,
4000
  25,
4001
  26,
4002
  27,
4003
  28,
4004
  29,
4005
  30,
4006
  31,
4007
  0,
4008
  1,
4009
  2,
4010
  3,
4011
  4,
4012
  5,
4013
  6,
4014
  7,
4015
  8,
4016
  9,
4017
  10,
4018
  11,
4019
  12,
4020
  13,
4021
  14,
4022
  15,
4023
  16,
4024
  17,
4025
  18,
4026
  19,
4027
  20,
4028
  21,
4029
  22,
4030
  23,
4031
  24,
4032
  25,
4033
  26,
4034
  27,
4035
  28,
4036
  29,
4037
  30,
4038
  31,
4039
  8,
4040
  9,
4041
  10,
4042
  11,
4043
  12,
4044
  13,
4045
  14,
4046
  15,
4047
  65535,
4048
  65535,
4049
  65535,
4050
  65535,
4051
  65535,
4052
  65535,
4053
  65535,
4054
  65535,
4055
  8,
4056
  9,
4057
  10,
4058
  11,
4059
  12,
4060
  13,
4061
  14,
4062
  15,
4063
  8,
4064
  9,
4065
  10,
4066
  11,
4067
  12,
4068
  13,
4069
  14,
4070
  15,
4071
  65535,
4072
  65535,
4073
  65535,
4074
  65535,
4075
  65535,
4076
  65535,
4077
  65535,
4078
  65535,
4079
};
4080
4.79k
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4081
4.79k
  RI->InitMCRegisterInfo(X86RegDesc, 277, RA, PC, X86MCRegisterClasses, 109, X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 9,
4082
4.79k
X86SubRegIdxRanges, X86RegEncodingTable);
4083
4.79k
4084
4.79k
  switch (DwarfFlavour) {
4085
4.79k
  default:
4086
0
    llvm_unreachable("Unknown DWARF flavour");
4087
4.79k
  case 0:
4088
3.68k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
4089
3.68k
    break;
4090
4.79k
  case 1:
4091
0
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
4092
0
    break;
4093
4.79k
  case 2:
4094
1.11k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
4095
1.11k
    break;
4096
4.78k
  }
4097
4.78k
  switch (EHFlavour) {
4098
4.78k
  default:
4099
0
    llvm_unreachable("Unknown DWARF flavour");
4100
4.78k
  case 0:
4101
3.67k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
4102
3.67k
    break;
4103
4.78k
  case 1:
4104
955
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
4105
955
    break;
4106
4.78k
  case 2:
4107
156
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
4108
156
    break;
4109
4.78k
  }
4110
4.78k
  switch (DwarfFlavour) {
4111
4.78k
  default:
4112
0
    llvm_unreachable("Unknown DWARF flavour");
4113
4.78k
  case 0:
4114
3.67k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
4115
3.67k
    break;
4116
4.78k
  case 1:
4117
0
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
4118
0
    break;
4119
4.78k
  case 2:
4120
1.11k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
4121
1.11k
    break;
4122
4.79k
  }
4123
4.79k
  switch (EHFlavour) {
4124
4.79k
  default:
4125
0
    llvm_unreachable("Unknown DWARF flavour");
4126
4.79k
  case 0:
4127
3.68k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
4128
3.68k
    break;
4129
4.79k
  case 1:
4130
955
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
4131
955
    break;
4132
4.79k
  case 2:
4133
156
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
4134
156
    break;
4135
4.79k
  }
4136
4.79k
}
4137
4138
} // end namespace llvm
4139
4140
#endif // GET_REGINFO_MC_DESC
4141
4142
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4143
|*                                                                            *|
4144
|* Register Information Header Fragment                                       *|
4145
|*                                                                            *|
4146
|* Automatically generated file, do not edit!                                 *|
4147
|*                                                                            *|
4148
\*===----------------------------------------------------------------------===*/
4149
4150
4151
#ifdef GET_REGINFO_HEADER
4152
#undef GET_REGINFO_HEADER
4153
4154
#include "llvm/CodeGen/TargetRegisterInfo.h"
4155
4156
namespace llvm {
4157
4158
class X86FrameLowering;
4159
4160
struct X86GenRegisterInfo : public TargetRegisterInfo {
4161
  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4162
      unsigned PC = 0, unsigned HwMode = 0);
4163
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4164
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4165
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4166
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4167
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4168
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4169
  unsigned getNumRegPressureSets() const override;
4170
  const char *getRegPressureSetName(unsigned Idx) const override;
4171
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4172
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4173
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4174
  ArrayRef<const char *> getRegMaskNames() const override;
4175
  ArrayRef<const uint32_t *> getRegMasks() const override;
4176
  /// Devirtualized TargetFrameLowering.
4177
  static const X86FrameLowering *getFrameLowering(
4178
      const MachineFunction &MF);
4179
};
4180
4181
namespace X86 { // Register classes
4182
  extern const TargetRegisterClass GR8RegClass;
4183
  extern const TargetRegisterClass GRH8RegClass;
4184
  extern const TargetRegisterClass GR8_NOREXRegClass;
4185
  extern const TargetRegisterClass GR8_ABCD_HRegClass;
4186
  extern const TargetRegisterClass GR8_ABCD_LRegClass;
4187
  extern const TargetRegisterClass GRH16RegClass;
4188
  extern const TargetRegisterClass GR16RegClass;
4189
  extern const TargetRegisterClass GR16_NOREXRegClass;
4190
  extern const TargetRegisterClass VK1RegClass;
4191
  extern const TargetRegisterClass VK16RegClass;
4192
  extern const TargetRegisterClass VK2RegClass;
4193
  extern const TargetRegisterClass VK4RegClass;
4194
  extern const TargetRegisterClass VK8RegClass;
4195
  extern const TargetRegisterClass VK16WMRegClass;
4196
  extern const TargetRegisterClass VK1WMRegClass;
4197
  extern const TargetRegisterClass VK2WMRegClass;
4198
  extern const TargetRegisterClass VK4WMRegClass;
4199
  extern const TargetRegisterClass VK8WMRegClass;
4200
  extern const TargetRegisterClass SEGMENT_REGRegClass;
4201
  extern const TargetRegisterClass GR16_ABCDRegClass;
4202
  extern const TargetRegisterClass FPCCRRegClass;
4203
  extern const TargetRegisterClass FR32XRegClass;
4204
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
4205
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
4206
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
4207
  extern const TargetRegisterClass DEBUG_REGRegClass;
4208
  extern const TargetRegisterClass FR32RegClass;
4209
  extern const TargetRegisterClass GR32RegClass;
4210
  extern const TargetRegisterClass GR32_NOSPRegClass;
4211
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
4212
  extern const TargetRegisterClass GR32_NOREXRegClass;
4213
  extern const TargetRegisterClass VK32RegClass;
4214
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
4215
  extern const TargetRegisterClass RFP32RegClass;
4216
  extern const TargetRegisterClass VK32WMRegClass;
4217
  extern const TargetRegisterClass GR32_ABCDRegClass;
4218
  extern const TargetRegisterClass GR32_TCRegClass;
4219
  extern const TargetRegisterClass GR32_ADRegClass;
4220
  extern const TargetRegisterClass GR32_BPSPRegClass;
4221
  extern const TargetRegisterClass GR32_BSIRegClass;
4222
  extern const TargetRegisterClass GR32_CBRegClass;
4223
  extern const TargetRegisterClass GR32_DCRegClass;
4224
  extern const TargetRegisterClass GR32_DIBPRegClass;
4225
  extern const TargetRegisterClass GR32_SIDIRegClass;
4226
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
4227
  extern const TargetRegisterClass CCRRegClass;
4228
  extern const TargetRegisterClass DFCCRRegClass;
4229
  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
4230
  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
4231
  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
4232
  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
4233
  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
4234
  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
4235
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
4236
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
4237
  extern const TargetRegisterClass RFP64RegClass;
4238
  extern const TargetRegisterClass FR64XRegClass;
4239
  extern const TargetRegisterClass GR64RegClass;
4240
  extern const TargetRegisterClass CONTROL_REGRegClass;
4241
  extern const TargetRegisterClass FR64RegClass;
4242
  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
4243
  extern const TargetRegisterClass GR64_NOSPRegClass;
4244
  extern const TargetRegisterClass GR64_NOREXRegClass;
4245
  extern const TargetRegisterClass GR64_TCRegClass;
4246
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
4247
  extern const TargetRegisterClass GR64_TCW64RegClass;
4248
  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4249
  extern const TargetRegisterClass VK64RegClass;
4250
  extern const TargetRegisterClass VR64RegClass;
4251
  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
4252
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
4253
  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
4254
  extern const TargetRegisterClass VK64WMRegClass;
4255
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
4256
  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
4257
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
4258
  extern const TargetRegisterClass GR64_ABCDRegClass;
4259
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
4260
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
4261
  extern const TargetRegisterClass GR64_ADRegClass;
4262
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
4263
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
4264
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
4265
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
4266
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
4267
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
4268
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
4269
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
4270
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
4271
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
4272
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
4273
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
4274
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
4275
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
4276
  extern const TargetRegisterClass RSTRegClass;
4277
  extern const TargetRegisterClass RFP80RegClass;
4278
  extern const TargetRegisterClass VR128XRegClass;
4279
  extern const TargetRegisterClass VR128RegClass;
4280
  extern const TargetRegisterClass VR128HRegClass;
4281
  extern const TargetRegisterClass VR128LRegClass;
4282
  extern const TargetRegisterClass BNDRRegClass;
4283
  extern const TargetRegisterClass VR256XRegClass;
4284
  extern const TargetRegisterClass VR256RegClass;
4285
  extern const TargetRegisterClass VR256HRegClass;
4286
  extern const TargetRegisterClass VR256LRegClass;
4287
  extern const TargetRegisterClass VR512RegClass;
4288
  extern const TargetRegisterClass VR512_with_sub_xmm_in_FR32RegClass;
4289
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128HRegClass;
4290
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128LRegClass;
4291
} // end namespace X86
4292
4293
} // end namespace llvm
4294
4295
#endif // GET_REGINFO_HEADER
4296
4297
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4298
|*                                                                            *|
4299
|* Target Register and Register Classes Information                           *|
4300
|*                                                                            *|
4301
|* Automatically generated file, do not edit!                                 *|
4302
|*                                                                            *|
4303
\*===----------------------------------------------------------------------===*/
4304
4305
4306
#ifdef GET_REGINFO_TARGET_DESC
4307
#undef GET_REGINFO_TARGET_DESC
4308
4309
namespace llvm {
4310
4311
extern const MCRegisterClass X86MCRegisterClasses[];
4312
4313
static const MVT::SimpleValueType VTLists[] = {
4314
  /* 0 */ MVT::i8, MVT::Other,
4315
  /* 2 */ MVT::i16, MVT::Other,
4316
  /* 4 */ MVT::i32, MVT::Other,
4317
  /* 6 */ MVT::i64, MVT::Other,
4318
  /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
4319
  /* 12 */ MVT::f64, MVT::Other,
4320
  /* 14 */ MVT::f80, MVT::Other,
4321
  /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
4322
  /* 24 */ MVT::v1i1, MVT::Other,
4323
  /* 26 */ MVT::v2i1, MVT::Other,
4324
  /* 28 */ MVT::v4i1, MVT::Other,
4325
  /* 30 */ MVT::v8i1, MVT::Other,
4326
  /* 32 */ MVT::v16i1, MVT::Other,
4327
  /* 34 */ MVT::v32i1, MVT::Other,
4328
  /* 36 */ MVT::v64i1, MVT::Other,
4329
  /* 38 */ MVT::v2i64, MVT::Other,
4330
  /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
4331
  /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4332
  /* 54 */ MVT::x86mmx, MVT::Other,
4333
};
4334
4335
static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_xmm", "sub_ymm", "" };
4336
4337
4338
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4339
  LaneBitmask::getAll(),
4340
  LaneBitmask(0x00000001), // sub_8bit
4341
  LaneBitmask(0x00000002), // sub_8bit_hi
4342
  LaneBitmask(0x00000004), // sub_8bit_hi_phony
4343
  LaneBitmask(0x00000007), // sub_16bit
4344
  LaneBitmask(0x00000008), // sub_16bit_hi
4345
  LaneBitmask(0x0000000F), // sub_32bit
4346
  LaneBitmask(0x00000010), // sub_xmm
4347
  LaneBitmask(0x00000010), // sub_ymm
4348
 };
4349
4350
4351
4352
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4353
  // Mode = 0 (Default)
4354
  { 8, 8, 8, VTLists+0 },    // GR8
4355
  { 8, 8, 8, VTLists+0 },    // GRH8
4356
  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
4357
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
4358
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
4359
  { 16, 16, 16, VTLists+2 },    // GRH16
4360
  { 16, 16, 16, VTLists+2 },    // GR16
4361
  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
4362
  { 16, 16, 16, VTLists+24 },    // VK1
4363
  { 16, 16, 16, VTLists+32 },    // VK16
4364
  { 16, 16, 16, VTLists+26 },    // VK2
4365
  { 16, 16, 16, VTLists+28 },    // VK4
4366
  { 16, 16, 16, VTLists+30 },    // VK8
4367
  { 16, 16, 16, VTLists+32 },    // VK16WM
4368
  { 16, 16, 16, VTLists+24 },    // VK1WM
4369
  { 16, 16, 16, VTLists+26 },    // VK2WM
4370
  { 16, 16, 16, VTLists+28 },    // VK4WM
4371
  { 16, 16, 16, VTLists+30 },    // VK8WM
4372
  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
4373
  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
4374
  { 16, 16, 16, VTLists+2 },    // FPCCR
4375
  { 32, 32, 32, VTLists+10 },    // FR32X
4376
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
4377
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
4378
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4379
  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
4380
  { 32, 32, 32, VTLists+10 },    // FR32
4381
  { 32, 32, 32, VTLists+4 },    // GR32
4382
  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
4383
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4384
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
4385
  { 32, 32, 32, VTLists+34 },    // VK32
4386
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
4387
  { 32, 32, 32, VTLists+10 },    // RFP32
4388
  { 32, 32, 32, VTLists+34 },    // VK32WM
4389
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
4390
  { 32, 32, 32, VTLists+4 },    // GR32_TC
4391
  { 32, 32, 32, VTLists+4 },    // GR32_AD
4392
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP
4393
  { 32, 32, 32, VTLists+4 },    // GR32_BSI
4394
  { 32, 32, 32, VTLists+4 },    // GR32_CB
4395
  { 32, 32, 32, VTLists+4 },    // GR32_DC
4396
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP
4397
  { 32, 32, 32, VTLists+4 },    // GR32_SIDI
4398
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4399
  { 32, 32, 32, VTLists+4 },    // CCR
4400
  { 32, 32, 32, VTLists+4 },    // DFCCR
4401
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_BSI
4402
  { 32, 32, 32, VTLists+4 },    // GR32_AD_and_GR32_DC
4403
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_DIBP
4404
  { 32, 32, 32, VTLists+4 },    // GR32_BSI_and_GR32_SIDI
4405
  { 32, 32, 32, VTLists+4 },    // GR32_CB_and_GR32_DC
4406
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP_and_GR32_SIDI
4407
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4408
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
4409
  { 64, 64, 32, VTLists+12 },    // RFP64
4410
  { 64, 64, 64, VTLists+12 },    // FR64X
4411
  { 64, 64, 64, VTLists+6 },    // GR64
4412
  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
4413
  { 64, 64, 64, VTLists+12 },    // FR64
4414
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
4415
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
4416
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
4417
  { 64, 64, 64, VTLists+6 },    // GR64_TC
4418
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
4419
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
4420
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
4421
  { 64, 64, 64, VTLists+36 },    // VK64
4422
  { 64, 64, 64, VTLists+54 },    // VR64
4423
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
4424
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
4425
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
4426
  { 64, 64, 64, VTLists+36 },    // VK64WM
4427
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
4428
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4429
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_GR64_TC
4430
  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
4431
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
4432
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
4433
  { 64, 64, 64, VTLists+6 },    // GR64_AD
4434
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
4435
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP
4436
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI
4437
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB
4438
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DC
4439
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP
4440
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_SIDI
4441
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
4442
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4443
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
4444
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4445
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4446
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
4447
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4448
  { 80, 80, 32, VTLists+8 },    // RST
4449
  { 80, 80, 32, VTLists+14 },    // RFP80
4450
  { 128, 128, 128, VTLists+16 },    // VR128X
4451
  { 128, 128, 128, VTLists+16 },    // VR128
4452
  { 128, 128, 128, VTLists+16 },    // VR128H
4453
  { 128, 128, 128, VTLists+16 },    // VR128L
4454
  { 128, 128, 128, VTLists+38 },    // BNDR
4455
  { 256, 256, 256, VTLists+40 },    // VR256X
4456
  { 256, 256, 256, VTLists+40 },    // VR256
4457
  { 256, 256, 256, VTLists+40 },    // VR256H
4458
  { 256, 256, 256, VTLists+40 },    // VR256L
4459
  { 512, 512, 512, VTLists+47 },    // VR512
4460
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_FR32
4461
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128H
4462
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128L
4463
};
4464
4465
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4466
4467
static const uint32_t GR8SubClassMask[] = {
4468
  0x0000001d, 0x00000000, 0x00000000, 0x00000000, 
4469
  0x790800c0, 0x303f8ff9, 0x3f7edc65, 0x00000000, // sub_8bit
4470
  0x00080000, 0x00098338, 0x1318d000, 0x00000000, // sub_8bit_hi
4471
};
4472
4473
static const uint32_t GRH8SubClassMask[] = {
4474
  0x00000002, 0x00000000, 0x00000000, 0x00000000, 
4475
};
4476
4477
static const uint32_t GR8_NOREXSubClassMask[] = {
4478
  0x0000001c, 0x00000000, 0x00000000, 0x00000000, 
4479
  0x00080000, 0x00098338, 0x1318d000, 0x00000000, // sub_8bit
4480
  0x00080000, 0x00098338, 0x1318d000, 0x00000000, // sub_8bit_hi
4481
};
4482
4483
static const uint32_t GR8_ABCD_HSubClassMask[] = {
4484
  0x00000008, 0x00000000, 0x00000000, 0x00000000, 
4485
  0x00080000, 0x00098338, 0x1318d000, 0x00000000, // sub_8bit_hi
4486
};
4487
4488
static const uint32_t GR8_ABCD_LSubClassMask[] = {
4489
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
4490
  0x00080000, 0x00098338, 0x1318d000, 0x00000000, // sub_8bit
4491
};
4492
4493
static const uint32_t GRH16SubClassMask[] = {
4494
  0x00000020, 0x00000000, 0x00000000, 0x00000000, 
4495
};
4496
4497
static const uint32_t GR16SubClassMask[] = {
4498
  0x000800c0, 0x00000000, 0x00000000, 0x00000000, 
4499
  0x79000000, 0x303f8ff9, 0x3f7edc65, 0x00000000, // sub_16bit
4500
};
4501
4502
static const uint32_t GR16_NOREXSubClassMask[] = {
4503
  0x00080080, 0x00000000, 0x00000000, 0x00000000, 
4504
  0x60000000, 0x003f8ff9, 0x3f7ed824, 0x00000000, // sub_16bit
4505
};
4506
4507
static const uint32_t VK1SubClassMask[] = {
4508
  0x8003ff00, 0x00000004, 0x00000108, 0x00000000, 
4509
};
4510
4511
static const uint32_t VK16SubClassMask[] = {
4512
  0x8003ff00, 0x00000004, 0x00000108, 0x00000000, 
4513
};
4514
4515
static const uint32_t VK2SubClassMask[] = {
4516
  0x8003ff00, 0x00000004, 0x00000108, 0x00000000, 
4517
};
4518
4519
static const uint32_t VK4SubClassMask[] = {
4520
  0x8003ff00, 0x00000004, 0x00000108, 0x00000000, 
4521
};
4522
4523
static const uint32_t VK8SubClassMask[] = {
4524
  0x8003ff00, 0x00000004, 0x00000108, 0x00000000, 
4525
};
4526
4527
static const uint32_t VK16WMSubClassMask[] = {
4528
  0x0003e000, 0x00000004, 0x00000100, 0x00000000, 
4529
};
4530
4531
static const uint32_t VK1WMSubClassMask[] = {
4532
  0x0003e000, 0x00000004, 0x00000100, 0x00000000, 
4533
};
4534
4535
static const uint32_t VK2WMSubClassMask[] = {
4536
  0x0003e000, 0x00000004, 0x00000100, 0x00000000, 
4537
};
4538
4539
static const uint32_t VK4WMSubClassMask[] = {
4540
  0x0003e000, 0x00000004, 0x00000100, 0x00000000, 
4541
};
4542
4543
static const uint32_t VK8WMSubClassMask[] = {
4544
  0x0003e000, 0x00000004, 0x00000100, 0x00000000, 
4545
};
4546
4547
static const uint32_t SEGMENT_REGSubClassMask[] = {
4548
  0x00040000, 0x00000000, 0x00000000, 0x00000000, 
4549
};
4550
4551
static const uint32_t GR16_ABCDSubClassMask[] = {
4552
  0x00080000, 0x00000000, 0x00000000, 0x00000000, 
4553
  0x00000000, 0x00098338, 0x1318d000, 0x00000000, // sub_16bit
4554
};
4555
4556
static const uint32_t FPCCRSubClassMask[] = {
4557
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
4558
};
4559
4560
static const uint32_t FR32XSubClassMask[] = {
4561
  0x04200000, 0x09000000, 0x00000000, 0x0000000f, 
4562
  0x00000000, 0x00000000, 0x00000000, 0x00001fe0, // sub_xmm
4563
};
4564
4565
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4566
  0x79c00000, 0x007f9ff9, 0x04810000, 0x00000000, 
4567
  0x00000000, 0x30200000, 0x3f7edc65, 0x00000000, // sub_32bit
4568
};
4569
4570
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
4571
  0x58800000, 0x005f8ff9, 0x00800000, 0x00000000, 
4572
  0x00000000, 0x30200000, 0x3f7edc65, 0x00000000, // sub_32bit
4573
};
4574
4575
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
4576
  0x79000000, 0x003f8ff9, 0x04000000, 0x00000000, 
4577
  0x00000000, 0x30200000, 0x3f7edc65, 0x00000000, // sub_32bit
4578
};
4579
4580
static const uint32_t DEBUG_REGSubClassMask[] = {
4581
  0x02000000, 0x00000000, 0x00000000, 0x00000000, 
4582
};
4583
4584
static const uint32_t FR32SubClassMask[] = {
4585
  0x04000000, 0x08000000, 0x00000000, 0x0000000e, 
4586
  0x00000000, 0x00000000, 0x00000000, 0x00001dc0, // sub_xmm
4587
};
4588
4589
static const uint32_t GR32SubClassMask[] = {
4590
  0x58000000, 0x001f8ff9, 0x00000000, 0x00000000, 
4591
  0x00000000, 0x30200000, 0x3f7edc65, 0x00000000, // sub_32bit
4592
};
4593
4594
static const uint32_t GR32_NOSPSubClassMask[] = {
4595
  0x10000000, 0x001f8fb9, 0x00000000, 0x00000000, 
4596
  0x00000000, 0x20200000, 0x3f7cdc61, 0x00000000, // sub_32bit
4597
};
4598
4599
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4600
  0x60000000, 0x003f8ff9, 0x04000000, 0x00000000, 
4601
  0x00000000, 0x00200000, 0x3f7ed824, 0x00000000, // sub_32bit
4602
};
4603
4604
static const uint32_t GR32_NOREXSubClassMask[] = {
4605
  0x40000000, 0x001f8ff9, 0x00000000, 0x00000000, 
4606
  0x00000000, 0x00200000, 0x3f7ed824, 0x00000000, // sub_32bit
4607
};
4608
4609
static const uint32_t VK32SubClassMask[] = {
4610
  0x80000000, 0x00000004, 0x00000108, 0x00000000, 
4611
};
4612
4613
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
4614
  0x00000000, 0x001f8fb9, 0x00000000, 0x00000000, 
4615
  0x00000000, 0x00200000, 0x3f7cd820, 0x00000000, // sub_32bit
4616
};
4617
4618
static const uint32_t RFP32SubClassMask[] = {
4619
  0x00000000, 0x00800002, 0x80000000, 0x00000000, 
4620
};
4621
4622
static const uint32_t VK32WMSubClassMask[] = {
4623
  0x00000000, 0x00000004, 0x00000100, 0x00000000, 
4624
};
4625
4626
static const uint32_t GR32_ABCDSubClassMask[] = {
4627
  0x00000000, 0x00098338, 0x00000000, 0x00000000, 
4628
  0x00000000, 0x00000000, 0x1318d000, 0x00000000, // sub_32bit
4629
};
4630
4631
static const uint32_t GR32_TCSubClassMask[] = {
4632
  0x00000000, 0x00090230, 0x00000000, 0x00000000, 
4633
  0x00000000, 0x00000000, 0x1210c000, 0x00000000, // sub_32bit
4634
};
4635
4636
static const uint32_t GR32_ADSubClassMask[] = {
4637
  0x00000000, 0x00010020, 0x00000000, 0x00000000, 
4638
  0x00000000, 0x00000000, 0x02008000, 0x00000000, // sub_32bit
4639
};
4640
4641
static const uint32_t GR32_BPSPSubClassMask[] = {
4642
  0x00000000, 0x00020040, 0x00000000, 0x00000000, 
4643
  0x00000000, 0x00200000, 0x04020000, 0x00000000, // sub_32bit
4644
};
4645
4646
static const uint32_t GR32_BSISubClassMask[] = {
4647
  0x00000000, 0x00048080, 0x00000000, 0x00000000, 
4648
  0x00000000, 0x00000000, 0x09040000, 0x00000000, // sub_32bit
4649
};
4650
4651
static const uint32_t GR32_CBSubClassMask[] = {
4652
  0x00000000, 0x00088100, 0x00000000, 0x00000000, 
4653
  0x00000000, 0x00000000, 0x11080000, 0x00000000, // sub_32bit
4654
};
4655
4656
static const uint32_t GR32_DCSubClassMask[] = {
4657
  0x00000000, 0x00090200, 0x00000000, 0x00000000, 
4658
  0x00000000, 0x00000000, 0x12100000, 0x00000000, // sub_32bit
4659
};
4660
4661
static const uint32_t GR32_DIBPSubClassMask[] = {
4662
  0x00000000, 0x00120400, 0x00000000, 0x00000000, 
4663
  0x00000000, 0x00200000, 0x24200000, 0x00000000, // sub_32bit
4664
};
4665
4666
static const uint32_t GR32_SIDISubClassMask[] = {
4667
  0x00000000, 0x00140800, 0x00000000, 0x00000000, 
4668
  0x00000000, 0x00000000, 0x28400000, 0x00000000, // sub_32bit
4669
};
4670
4671
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
4672
  0x00000000, 0x00601000, 0x04810000, 0x00000000, 
4673
};
4674
4675
static const uint32_t CCRSubClassMask[] = {
4676
  0x00000000, 0x00002000, 0x00000000, 0x00000000, 
4677
};
4678
4679
static const uint32_t DFCCRSubClassMask[] = {
4680
  0x00000000, 0x00004000, 0x00000000, 0x00000000, 
4681
};
4682
4683
static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
4684
  0x00000000, 0x00008000, 0x00000000, 0x00000000, 
4685
  0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32bit
4686
};
4687
4688
static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
4689
  0x00000000, 0x00010000, 0x00000000, 0x00000000, 
4690
  0x00000000, 0x00000000, 0x02000000, 0x00000000, // sub_32bit
4691
};
4692
4693
static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
4694
  0x00000000, 0x00020000, 0x00000000, 0x00000000, 
4695
  0x00000000, 0x00200000, 0x04000000, 0x00000000, // sub_32bit
4696
};
4697
4698
static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
4699
  0x00000000, 0x00040000, 0x00000000, 0x00000000, 
4700
  0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
4701
};
4702
4703
static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
4704
  0x00000000, 0x00080000, 0x00000000, 0x00000000, 
4705
  0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32bit
4706
};
4707
4708
static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
4709
  0x00000000, 0x00100000, 0x00000000, 0x00000000, 
4710
  0x00000000, 0x00000000, 0x20000000, 0x00000000, // sub_32bit
4711
};
4712
4713
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
4714
  0x00000000, 0x00200000, 0x04000000, 0x00000000, 
4715
};
4716
4717
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
4718
  0x00000000, 0x00400000, 0x00800000, 0x00000000, 
4719
};
4720
4721
static const uint32_t RFP64SubClassMask[] = {
4722
  0x00000000, 0x00800000, 0x80000000, 0x00000000, 
4723
};
4724
4725
static const uint32_t FR64XSubClassMask[] = {
4726
  0x00000000, 0x09000000, 0x00000000, 0x0000000f, 
4727
  0x00000000, 0x00000000, 0x00000000, 0x00001fe0, // sub_xmm
4728
};
4729
4730
static const uint32_t GR64SubClassMask[] = {
4731
  0x00000000, 0xf2000000, 0x3ffffee7, 0x00000000, 
4732
};
4733
4734
static const uint32_t CONTROL_REGSubClassMask[] = {
4735
  0x00000000, 0x04000000, 0x00000000, 0x00000000, 
4736
};
4737
4738
static const uint32_t FR64SubClassMask[] = {
4739
  0x00000000, 0x08000000, 0x00000000, 0x0000000e, 
4740
  0x00000000, 0x00000000, 0x00000000, 0x00001dc0, // sub_xmm
4741
};
4742
4743
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
4744
  0x00000000, 0x30000000, 0x3f7edc65, 0x00000000, 
4745
};
4746
4747
static const uint32_t GR64_NOSPSubClassMask[] = {
4748
  0x00000000, 0x20000000, 0x3f7cdc61, 0x00000000, 
4749
};
4750
4751
static const uint32_t GR64_NOREXSubClassMask[] = {
4752
  0x00000000, 0x40000000, 0x3ffffa24, 0x00000000, 
4753
};
4754
4755
static const uint32_t GR64_TCSubClassMask[] = {
4756
  0x00000000, 0x80000000, 0x3ad0ee81, 0x00000000, 
4757
};
4758
4759
static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
4760
  0x00000000, 0x00000000, 0x3a50cc01, 0x00000000, 
4761
};
4762
4763
static const uint32_t GR64_TCW64SubClassMask[] = {
4764
  0x00000000, 0x00000000, 0x1290e4c2, 0x00000000, 
4765
};
4766
4767
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4768
  0x00000000, 0x00000000, 0x3f7ed824, 0x00000000, 
4769
};
4770
4771
static const uint32_t VK64SubClassMask[] = {
4772
  0x00000000, 0x00000000, 0x00000108, 0x00000000, 
4773
};
4774
4775
static const uint32_t VR64SubClassMask[] = {
4776
  0x00000000, 0x00000000, 0x00000010, 0x00000000, 
4777
};
4778
4779
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
4780
  0x00000000, 0x00000000, 0x3f7cd820, 0x00000000, 
4781
};
4782
4783
static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4784
  0x00000000, 0x00000000, 0x1210c440, 0x00000000, 
4785
};
4786
4787
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
4788
  0x00000000, 0x00000000, 0x1290e480, 0x00000000, 
4789
};
4790
4791
static const uint32_t VK64WMSubClassMask[] = {
4792
  0x00000000, 0x00000000, 0x00000100, 0x00000000, 
4793
};
4794
4795
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
4796
  0x00000000, 0x00000000, 0x3ad0ea00, 0x00000000, 
4797
};
4798
4799
static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4800
  0x00000000, 0x00000000, 0x1210c400, 0x00000000, 
4801
};
4802
4803
static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = {
4804
  0x00000000, 0x00000000, 0x3a50c800, 0x00000000, 
4805
};
4806
4807
static const uint32_t GR64_ABCDSubClassMask[] = {
4808
  0x00000000, 0x00000000, 0x1318d000, 0x00000000, 
4809
};
4810
4811
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
4812
  0x00000000, 0x00000000, 0x1290e000, 0x00000000, 
4813
};
4814
4815
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
4816
  0x00000000, 0x00000000, 0x1210c000, 0x00000000, 
4817
};
4818
4819
static const uint32_t GR64_ADSubClassMask[] = {
4820
  0x00000000, 0x00000000, 0x02008000, 0x00000000, 
4821
};
4822
4823
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4824
  0x00000000, 0x00000000, 0x04810000, 0x00000000, 
4825
};
4826
4827
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
4828
  0x00000000, 0x00000000, 0x04020000, 0x00000000, 
4829
};
4830
4831
static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
4832
  0x00000000, 0x00000000, 0x09040000, 0x00000000, 
4833
};
4834
4835
static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
4836
  0x00000000, 0x00000000, 0x11080000, 0x00000000, 
4837
};
4838
4839
static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
4840
  0x00000000, 0x00000000, 0x12100000, 0x00000000, 
4841
};
4842
4843
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
4844
  0x00000000, 0x00000000, 0x24200000, 0x00000000, 
4845
};
4846
4847
static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
4848
  0x00000000, 0x00000000, 0x28400000, 0x00000000, 
4849
};
4850
4851
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
4852
  0x00000000, 0x00000000, 0x00800000, 0x00000000, 
4853
};
4854
4855
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
4856
  0x00000000, 0x00000000, 0x01000000, 0x00000000, 
4857
};
4858
4859
static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
4860
  0x00000000, 0x00000000, 0x02000000, 0x00000000, 
4861
};
4862
4863
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
4864
  0x00000000, 0x00000000, 0x04000000, 0x00000000, 
4865
};
4866
4867
static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
4868
  0x00000000, 0x00000000, 0x08000000, 0x00000000, 
4869
};
4870
4871
static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
4872
  0x00000000, 0x00000000, 0x10000000, 0x00000000, 
4873
};
4874
4875
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
4876
  0x00000000, 0x00000000, 0x20000000, 0x00000000, 
4877
};
4878
4879
static const uint32_t RSTSubClassMask[] = {
4880
  0x00000000, 0x00000000, 0x40000000, 0x00000000, 
4881
};
4882
4883
static const uint32_t RFP80SubClassMask[] = {
4884
  0x00000000, 0x00000000, 0x80000000, 0x00000000, 
4885
};
4886
4887
static const uint32_t VR128XSubClassMask[] = {
4888
  0x00000000, 0x00000000, 0x00000000, 0x0000000f, 
4889
  0x00000000, 0x00000000, 0x00000000, 0x00001fe0, // sub_xmm
4890
};
4891
4892
static const uint32_t VR128SubClassMask[] = {
4893
  0x00000000, 0x00000000, 0x00000000, 0x0000000e, 
4894
  0x00000000, 0x00000000, 0x00000000, 0x00001dc0, // sub_xmm
4895
};
4896
4897
static const uint32_t VR128HSubClassMask[] = {
4898
  0x00000000, 0x00000000, 0x00000000, 0x00000004, 
4899
  0x00000000, 0x00000000, 0x00000000, 0x00000880, // sub_xmm
4900
};
4901
4902
static const uint32_t VR128LSubClassMask[] = {
4903
  0x00000000, 0x00000000, 0x00000000, 0x00000008, 
4904
  0x00000000, 0x00000000, 0x00000000, 0x00001100, // sub_xmm
4905
};
4906
4907
static const uint32_t BNDRSubClassMask[] = {
4908
  0x00000000, 0x00000000, 0x00000000, 0x00000010, 
4909
};
4910
4911
static const uint32_t VR256XSubClassMask[] = {
4912
  0x00000000, 0x00000000, 0x00000000, 0x000001e0, 
4913
  0x00000000, 0x00000000, 0x00000000, 0x00001e00, // sub_ymm
4914
};
4915
4916
static const uint32_t VR256SubClassMask[] = {
4917
  0x00000000, 0x00000000, 0x00000000, 0x000001c0, 
4918
  0x00000000, 0x00000000, 0x00000000, 0x00001c00, // sub_ymm
4919
};
4920
4921
static const uint32_t VR256HSubClassMask[] = {
4922
  0x00000000, 0x00000000, 0x00000000, 0x00000080, 
4923
  0x00000000, 0x00000000, 0x00000000, 0x00000800, // sub_ymm
4924
};
4925
4926
static const uint32_t VR256LSubClassMask[] = {
4927
  0x00000000, 0x00000000, 0x00000000, 0x00000100, 
4928
  0x00000000, 0x00000000, 0x00000000, 0x00001000, // sub_ymm
4929
};
4930
4931
static const uint32_t VR512SubClassMask[] = {
4932
  0x00000000, 0x00000000, 0x00000000, 0x00001e00, 
4933
};
4934
4935
static const uint32_t VR512_with_sub_xmm_in_FR32SubClassMask[] = {
4936
  0x00000000, 0x00000000, 0x00000000, 0x00001c00, 
4937
};
4938
4939
static const uint32_t VR512_with_sub_xmm_in_VR128HSubClassMask[] = {
4940
  0x00000000, 0x00000000, 0x00000000, 0x00000800, 
4941
};
4942
4943
static const uint32_t VR512_with_sub_xmm_in_VR128LSubClassMask[] = {
4944
  0x00000000, 0x00000000, 0x00000000, 0x00001000, 
4945
};
4946
4947
static const uint16_t SuperRegIdxSeqs[] = {
4948
  /* 0 */ 1, 0,
4949
  /* 2 */ 1, 2, 0,
4950
  /* 5 */ 4, 0,
4951
  /* 7 */ 6, 0,
4952
  /* 9 */ 7, 0,
4953
  /* 11 */ 8, 0,
4954
};
4955
4956
static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
4957
  &X86::GR8RegClass,
4958
  nullptr
4959
};
4960
4961
static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
4962
  &X86::GR8RegClass,
4963
  &X86::GR8_NOREXRegClass,
4964
  nullptr
4965
};
4966
4967
static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
4968
  &X86::GR8RegClass,
4969
  &X86::GR8_NOREXRegClass,
4970
  nullptr
4971
};
4972
4973
static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
4974
  &X86::GR16RegClass,
4975
  nullptr
4976
};
4977
4978
static const TargetRegisterClass *const VK1Superclasses[] = {
4979
  &X86::VK16RegClass,
4980
  &X86::VK2RegClass,
4981
  &X86::VK4RegClass,
4982
  &X86::VK8RegClass,
4983
  nullptr
4984
};
4985
4986
static const TargetRegisterClass *const VK16Superclasses[] = {
4987
  &X86::VK1RegClass,
4988
  &X86::VK2RegClass,
4989
  &X86::VK4RegClass,
4990
  &X86::VK8RegClass,
4991
  nullptr
4992
};
4993
4994
static const TargetRegisterClass *const VK2Superclasses[] = {
4995
  &X86::VK1RegClass,
4996
  &X86::VK16RegClass,
4997
  &X86::VK4RegClass,
4998
  &X86::VK8RegClass,
4999
  nullptr
5000
};
5001
5002
static const TargetRegisterClass *const VK4Superclasses[] = {
5003
  &X86::VK1RegClass,
5004
  &X86::VK16RegClass,
5005
  &X86::VK2RegClass,
5006
  &X86::VK8RegClass,
5007
  nullptr
5008
};
5009
5010
static const TargetRegisterClass *const VK8Superclasses[] = {
5011
  &X86::VK1RegClass,
5012
  &X86::VK16RegClass,
5013
  &X86::VK2RegClass,
5014
  &X86::VK4RegClass,
5015
  nullptr
5016
};
5017
5018
static const TargetRegisterClass *const VK16WMSuperclasses[] = {
5019
  &X86::VK1RegClass,
5020
  &X86::VK16RegClass,
5021
  &X86::VK2RegClass,
5022
  &X86::VK4RegClass,
5023
  &X86::VK8RegClass,
5024
  &X86::VK1WMRegClass,
5025
  &X86::VK2WMRegClass,
5026
  &X86::VK4WMRegClass,
5027
  &X86::VK8WMRegClass,
5028
  nullptr
5029
};
5030
5031
static const TargetRegisterClass *const VK1WMSuperclasses[] = {
5032
  &X86::VK1RegClass,
5033
  &X86::VK16RegClass,
5034
  &X86::VK2RegClass,
5035
  &X86::VK4RegClass,
5036
  &X86::VK8RegClass,
5037
  &X86::VK16WMRegClass,
5038
  &X86::VK2WMRegClass,
5039
  &X86::VK4WMRegClass,
5040
  &X86::VK8WMRegClass,
5041
  nullptr
5042
};
5043
5044
static const TargetRegisterClass *const VK2WMSuperclasses[] = {
5045
  &X86::VK1RegClass,
5046
  &X86::VK16RegClass,
5047
  &X86::VK2RegClass,
5048
  &X86::VK4RegClass,
5049
  &X86::VK8RegClass,
5050
  &X86::VK16WMRegClass,
5051
  &X86::VK1WMRegClass,
5052
  &X86::VK4WMRegClass,
5053
  &X86::VK8WMRegClass,
5054
  nullptr
5055
};
5056
5057
static const TargetRegisterClass *const VK4WMSuperclasses[] = {
5058
  &X86::VK1RegClass,
5059
  &X86::VK16RegClass,
5060
  &X86::VK2RegClass,
5061
  &X86::VK4RegClass,
5062
  &X86::VK8RegClass,
5063
  &X86::VK16WMRegClass,
5064
  &X86::VK1WMRegClass,
5065
  &X86::VK2WMRegClass,
5066
  &X86::VK8WMRegClass,
5067
  nullptr
5068
};
5069
5070
static const TargetRegisterClass *const VK8WMSuperclasses[] = {
5071
  &X86::VK1RegClass,
5072
  &X86::VK16RegClass,
5073
  &X86::VK2RegClass,
5074
  &X86::VK4RegClass,
5075
  &X86::VK8RegClass,
5076
  &X86::VK16WMRegClass,
5077
  &X86::VK1WMRegClass,
5078
  &X86::VK2WMRegClass,
5079
  &X86::VK4WMRegClass,
5080
  nullptr
5081
};
5082
5083
static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
5084
  &X86::GR16RegClass,
5085
  &X86::GR16_NOREXRegClass,
5086
  nullptr
5087
};
5088
5089
static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
5090
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5091
  nullptr
5092
};
5093
5094
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
5095
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5096
  nullptr
5097
};
5098
5099
static const TargetRegisterClass *const FR32Superclasses[] = {
5100
  &X86::FR32XRegClass,
5101
  nullptr
5102
};
5103
5104
static const TargetRegisterClass *const GR32Superclasses[] = {
5105
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5106
  &X86::LOW32_ADDR_ACCESSRegClass,
5107
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5108
  nullptr
5109
};
5110
5111
static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
5112
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5113
  &X86::LOW32_ADDR_ACCESSRegClass,
5114
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5115
  &X86::GR32RegClass,
5116
  nullptr
5117
};
5118
5119
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5120
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5121
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5122
  nullptr
5123
};
5124
5125
static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
5126
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5127
  &X86::LOW32_ADDR_ACCESSRegClass,
5128
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5129
  &X86::GR32RegClass,
5130
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5131
  nullptr
5132
};
5133
5134
static const TargetRegisterClass *const VK32Superclasses[] = {
5135
  &X86::VK1RegClass,
5136
  &X86::VK16RegClass,
5137
  &X86::VK2RegClass,
5138
  &X86::VK4RegClass,
5139
  &X86::VK8RegClass,
5140
  nullptr
5141
};
5142
5143
static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
5144
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5145
  &X86::LOW32_ADDR_ACCESSRegClass,
5146
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5147
  &X86::GR32RegClass,
5148
  &X86::GR32_NOSPRegClass,
5149
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5150
  &X86::GR32_NOREXRegClass,
5151
  nullptr
5152
};
5153
5154
static const TargetRegisterClass *const VK32WMSuperclasses[] = {
5155
  &X86::VK1RegClass,
5156
  &X86::VK16RegClass,
5157
  &X86::VK2RegClass,
5158
  &X86::VK4RegClass,
5159
  &X86::VK8RegClass,
5160
  &X86::VK16WMRegClass,
5161
  &X86::VK1WMRegClass,
5162
  &X86::VK2WMRegClass,
5163
  &X86::VK4WMRegClass,
5164
  &X86::VK8WMRegClass,
5165
  &X86::VK32RegClass,
5166
  nullptr
5167
};
5168
5169
static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
5170
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5171
  &X86::LOW32_ADDR_ACCESSRegClass,
5172
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5173
  &X86::GR32RegClass,
5174
  &X86::GR32_NOSPRegClass,
5175
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5176
  &X86::GR32_NOREXRegClass,
5177
  &X86::GR32_NOREX_NOSPRegClass,
5178
  nullptr
5179
};
5180
5181
static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
5182
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5183
  &X86::LOW32_ADDR_ACCESSRegClass,
5184
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5185
  &X86::GR32RegClass,
5186
  &X86::GR32_NOSPRegClass,
5187
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5188
  &X86::GR32_NOREXRegClass,
5189
  &X86::GR32_NOREX_NOSPRegClass,
5190
  &X86::GR32_ABCDRegClass,
5191
  nullptr
5192
};
5193
5194
static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
5195
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5196
  &X86::LOW32_ADDR_ACCESSRegClass,
5197
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5198
  &X86::GR32RegClass,
5199
  &X86::GR32_NOSPRegClass,
5200
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5201
  &X86::GR32_NOREXRegClass,
5202
  &X86::GR32_NOREX_NOSPRegClass,
5203
  &X86::GR32_ABCDRegClass,
5204
  &X86::GR32_TCRegClass,
5205
  nullptr
5206
};
5207
5208
static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
5209
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5210
  &X86::LOW32_ADDR_ACCESSRegClass,
5211
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5212
  &X86::GR32RegClass,
5213
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5214
  &X86::GR32_NOREXRegClass,
5215
  nullptr
5216
};
5217
5218
static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
5219
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5220
  &X86::LOW32_ADDR_ACCESSRegClass,
5221
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5222
  &X86::GR32RegClass,
5223
  &X86::GR32_NOSPRegClass,
5224
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5225
  &X86::GR32_NOREXRegClass,
5226
  &X86::GR32_NOREX_NOSPRegClass,
5227
  nullptr
5228
};
5229
5230
static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
5231
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5232
  &X86::LOW32_ADDR_ACCESSRegClass,
5233
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5234
  &X86::GR32RegClass,
5235
  &X86::GR32_NOSPRegClass,
5236
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5237
  &X86::GR32_NOREXRegClass,
5238
  &X86::GR32_NOREX_NOSPRegClass,
5239
  &X86::GR32_ABCDRegClass,
5240
  nullptr
5241
};
5242
5243
static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
5244
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5245
  &X86::LOW32_ADDR_ACCESSRegClass,
5246
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5247
  &X86::GR32RegClass,
5248
  &X86::GR32_NOSPRegClass,
5249
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5250
  &X86::GR32_NOREXRegClass,
5251
  &X86::GR32_NOREX_NOSPRegClass,
5252
  &X86::GR32_ABCDRegClass,
5253
  &X86::GR32_TCRegClass,
5254
  nullptr
5255
};
5256
5257
static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
5258
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5259
  &X86::LOW32_ADDR_ACCESSRegClass,
5260
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5261
  &X86::GR32RegClass,
5262
  &X86::GR32_NOSPRegClass,
5263
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5264
  &X86::GR32_NOREXRegClass,
5265
  &X86::GR32_NOREX_NOSPRegClass,
5266
  nullptr
5267
};
5268
5269
static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
5270
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5271
  &X86::LOW32_ADDR_ACCESSRegClass,
5272
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5273
  &X86::GR32RegClass,
5274
  &X86::GR32_NOSPRegClass,
5275
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5276
  &X86::GR32_NOREXRegClass,
5277
  &X86::GR32_NOREX_NOSPRegClass,
5278
  nullptr
5279
};
5280
5281
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
5282
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5283
  nullptr
5284
};
5285
5286
static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
5287
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5288
  &X86::LOW32_ADDR_ACCESSRegClass,
5289
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5290
  &X86::GR32RegClass,
5291
  &X86::GR32_NOSPRegClass,
5292
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5293
  &X86::GR32_NOREXRegClass,
5294
  &X86::GR32_NOREX_NOSPRegClass,
5295
  &X86::GR32_ABCDRegClass,
5296
  &X86::GR32_BSIRegClass,
5297
  &X86::GR32_CBRegClass,
5298
  nullptr
5299
};
5300
5301
static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
5302
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5303
  &X86::LOW32_ADDR_ACCESSRegClass,
5304
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5305
  &X86::GR32RegClass,
5306
  &X86::GR32_NOSPRegClass,
5307
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5308
  &X86::GR32_NOREXRegClass,
5309
  &X86::GR32_NOREX_NOSPRegClass,
5310
  &X86::GR32_ABCDRegClass,
5311
  &X86::GR32_TCRegClass,
5312
  &X86::GR32_ADRegClass,
5313
  &X86::GR32_DCRegClass,
5314
  nullptr
5315
};
5316
5317
static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
5318
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5319
  &X86::LOW32_ADDR_ACCESSRegClass,
5320
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5321
  &X86::GR32RegClass,
5322
  &X86::GR32_NOSPRegClass,
5323
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5324
  &X86::GR32_NOREXRegClass,
5325
  &X86::GR32_NOREX_NOSPRegClass,
5326
  &X86::GR32_BPSPRegClass,
5327
  &X86::GR32_DIBPRegClass,
5328
  nullptr
5329
};
5330
5331
static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
5332
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5333
  &X86::LOW32_ADDR_ACCESSRegClass,
5334
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5335
  &X86::GR32RegClass,
5336
  &X86::GR32_NOSPRegClass,
5337
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5338
  &X86::GR32_NOREXRegClass,
5339
  &X86::GR32_NOREX_NOSPRegClass,
5340
  &X86::GR32_BSIRegClass,
5341
  &X86::GR32_SIDIRegClass,
5342
  nullptr
5343
};
5344
5345
static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
5346
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5347
  &X86::LOW32_ADDR_ACCESSRegClass,
5348
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5349
  &X86::GR32RegClass,
5350
  &X86::GR32_NOSPRegClass,
5351
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5352
  &X86::GR32_NOREXRegClass,
5353
  &X86::GR32_NOREX_NOSPRegClass,
5354
  &X86::GR32_ABCDRegClass,
5355
  &X86::GR32_TCRegClass,
5356
  &X86::GR32_CBRegClass,
5357
  &X86::GR32_DCRegClass,
5358
  nullptr
5359
};
5360
5361
static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
5362
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5363
  &X86::LOW32_ADDR_ACCESSRegClass,
5364
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5365
  &X86::GR32RegClass,
5366
  &X86::GR32_NOSPRegClass,
5367
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5368
  &X86::GR32_NOREXRegClass,
5369
  &X86::GR32_NOREX_NOSPRegClass,
5370
  &X86::GR32_DIBPRegClass,
5371
  &X86::GR32_SIDIRegClass,
5372
  nullptr
5373
};
5374
5375
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
5376
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5377
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5378
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5379
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5380
  nullptr
5381
};
5382
5383
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
5384
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5385
  &X86::LOW32_ADDR_ACCESSRegClass,
5386
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5387
  nullptr
5388
};
5389
5390
static const TargetRegisterClass *const RFP64Superclasses[] = {
5391
  &X86::RFP32RegClass,
5392
  nullptr
5393
};
5394
5395
static const TargetRegisterClass *const FR64XSuperclasses[] = {
5396
  &X86::FR32XRegClass,
5397
  nullptr
5398
};
5399
5400
static const TargetRegisterClass *const FR64Superclasses[] = {
5401
  &X86::FR32XRegClass,
5402
  &X86::FR32RegClass,
5403
  &X86::FR64XRegClass,
5404
  nullptr
5405
};
5406
5407
static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
5408
  &X86::GR64RegClass,
5409
  nullptr
5410
};
5411
5412
static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
5413
  &X86::GR64RegClass,
5414
  &X86::GR64_with_sub_8bitRegClass,
5415
  nullptr
5416
};
5417
5418
static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
5419
  &X86::GR64RegClass,
5420
  nullptr
5421
};
5422
5423
static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
5424
  &X86::GR64RegClass,
5425
  nullptr
5426
};
5427
5428
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
5429
  &X86::GR64RegClass,
5430
  &X86::GR64_with_sub_8bitRegClass,
5431
  &X86::GR64_NOSPRegClass,
5432
  &X86::GR64_TCRegClass,
5433
  nullptr
5434
};
5435
5436
static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
5437
  &X86::GR64RegClass,
5438
  nullptr
5439
};
5440
5441
static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5442
  &X86::GR64RegClass,
5443
  &X86::GR64_with_sub_8bitRegClass,
5444
  &X86::GR64_NOREXRegClass,
5445
  nullptr
5446
};
5447
5448
static const TargetRegisterClass *const VK64Superclasses[] = {
5449
  &X86::VK1RegClass,
5450
  &X86::VK16RegClass,
5451
  &X86::VK2RegClass,
5452
  &X86::VK4RegClass,
5453
  &X86::VK8RegClass,
5454
  &X86::VK32RegClass,
5455
  nullptr
5456
};
5457
5458
static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
5459
  &X86::GR64RegClass,
5460
  &X86::GR64_with_sub_8bitRegClass,
5461
  &X86::GR64_NOSPRegClass,
5462
  &X86::GR64_NOREXRegClass,
5463
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5464
  nullptr
5465
};
5466
5467
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
5468
  &X86::GR64RegClass,
5469
  &X86::GR64_with_sub_8bitRegClass,
5470
  &X86::GR64_NOSPRegClass,
5471
  &X86::GR64_TCW64RegClass,
5472
  nullptr
5473
};
5474
5475
static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
5476
  &X86::GR64RegClass,
5477
  &X86::GR64_TCRegClass,
5478
  &X86::GR64_TCW64RegClass,
5479
  nullptr
5480
};
5481
5482
static const TargetRegisterClass *const VK64WMSuperclasses[] = {
5483
  &X86::VK1RegClass,
5484
  &X86::VK16RegClass,
5485
  &X86::VK2RegClass,
5486
  &X86::VK4RegClass,
5487
  &X86::VK8RegClass,
5488
  &X86::VK16WMRegClass,
5489
  &X86::VK1WMRegClass,
5490
  &X86::VK2WMRegClass,
5491
  &X86::VK4WMRegClass,
5492
  &X86::VK8WMRegClass,
5493
  &X86::VK32RegClass,
5494
  &X86::VK32WMRegClass,
5495
  &X86::VK64RegClass,
5496
  nullptr
5497
};
5498
5499
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
5500
  &X86::GR64RegClass,
5501
  &X86::GR64_NOREXRegClass,
5502
  &X86::GR64_TCRegClass,
5503
  nullptr
5504
};
5505
5506
static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
5507
  &X86::GR64RegClass,
5508
  &X86::GR64_with_sub_8bitRegClass,
5509
  &X86::GR64_NOSPRegClass,
5510
  &X86::GR64_TCRegClass,
5511
  &X86::GR64_NOSP_and_GR64_TCRegClass,
5512
  &X86::GR64_TCW64RegClass,
5513
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
5514
  &X86::GR64_TC_and_GR64_TCW64RegClass,
5515
  nullptr
5516
};
5517
5518
static const TargetRegisterClass *const GR64_NOREX_NOSP_and_GR64_TCSuperclasses[] = {
5519
  &X86::GR64RegClass,
5520
  &X86::GR64_with_sub_8bitRegClass,
5521
  &X86::GR64_NOSPRegClass,
5522
  &X86::GR64_NOREXRegClass,
5523
  &X86::GR64_TCRegClass,
5524
  &X86::GR64_NOSP_and_GR64_TCRegClass,
5525
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5526
  &X86::GR64_NOREX_NOSPRegClass,
5527
  &X86::GR64_NOREX_and_GR64_TCRegClass,
5528
  nullptr
5529
};
5530
5531
static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
5532
  &X86::GR64RegClass,
5533
  &X86::GR64_with_sub_8bitRegClass,
5534
  &X86::GR64_NOSPRegClass,
5535
  &X86::GR64_NOREXRegClass,
5536
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5537
  &X86::GR64_NOREX_NOSPRegClass,
5538
  nullptr
5539
};
5540
5541
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
5542
  &X86::GR64RegClass,
5543
  &X86::GR64_NOREXRegClass,
5544
  &X86::GR64_TCRegClass,
5545
  &X86::GR64_TCW64RegClass,
5546
  &X86::GR64_TC_and_GR64_TCW64RegClass,
5547
  &X86::GR64_NOREX_and_GR64_TCRegClass,
5548
  nullptr
5549
};
5550
5551
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
5552
  &X86::GR64RegClass,
5553
  &X86::GR64_with_sub_8bitRegClass,
5554
  &X86::GR64_NOSPRegClass,
5555
  &X86::GR64_NOREXRegClass,
5556
  &X86::GR64_TCRegClass,
5557
  &X86::GR64_NOSP_and_GR64_TCRegClass,
5558
  &X86::GR64_TCW64RegClass,
5559
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5560
  &X86::GR64_NOREX_NOSPRegClass,
5561
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
5562
  &X86::GR64_TC_and_GR64_TCW64RegClass,
5563
  &X86::GR64_NOREX_and_GR64_TCRegClass,
5564
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
5565
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
5566
  &X86::GR64_ABCDRegClass,
5567
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
5568
  nullptr
5569
};
5570
5571
static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
5572
  &X86::GR64RegClass,
5573
  &X86::GR64_with_sub_8bitRegClass,
5574
  &X86::GR64_NOSPRegClass,
5575
  &X86::GR64_NOREXRegClass,
5576
  &X86::GR64_TCRegClass,
5577
  &X86::GR64_NOSP_and_GR64_TCRegClass,
5578
  &X86::GR64_TCW64RegClass,
5579
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5580
  &X86::GR64_NOREX_NOSPRegClass,
5581
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
5582
  &X86::GR64_TC_and_GR64_TCW64RegClass,
5583
  &X86::GR64_NOREX_and_GR64_TCRegClass,
5584
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
5585
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
5586
  &X86::GR64_ABCDRegClass,
5587
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
5588
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
5589
  nullptr
5590
};
5591
5592
static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
5593
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5594
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5595
  &X86::GR64RegClass,
5596
  &X86::GR64_NOREXRegClass,
5597
  nullptr
5598
};
5599
5600
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
5601
  &X86::GR64RegClass,
5602
  &X86::GR64_with_sub_8bitRegClass,
5603
  &X86::GR64_NOREXRegClass,
5604
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5605
  nullptr
5606
};
5607
5608
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
5609
  &X86::GR64RegClass,
5610
  &X86::GR64_with_sub_8bitRegClass,
5611
  &X86::GR64_NOSPRegClass,
5612
  &X86::GR64_NOREXRegClass,
5613
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5614
  &X86::GR64_NOREX_NOSPRegClass,
5615
  nullptr
5616
};
5617
5618
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
5619
  &X86::GR64RegClass,
5620
  &X86::GR64_with_sub_8bitRegClass,
5621
  &X86::GR64_NOSPRegClass,
5622
  &X86::GR64_NOREXRegClass,
5623
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5624
  &X86::GR64_NOREX_NOSPRegClass,
5625
  &X86::GR64_ABCDRegClass,
5626
  nullptr
5627
};
5628
5629
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = {
5630
  &X86::GR64RegClass,
5631
  &X86::GR64_with_sub_8bitRegClass,
5632
  &X86::GR64_NOSPRegClass,
5633
  &X86::GR64_NOREXRegClass,
5634
  &X86::GR64_TCRegClass,
5635
  &X86::GR64_NOSP_and_GR64_TCRegClass,
5636
  &X86::GR64_TCW64RegClass,
5637
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5638