Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass X86MCRegisterClasses[];
17
18
namespace X86 {
19
enum {
20
  NoRegister,
21
  AH = 1,
22
  AL = 2,
23
  AX = 3,
24
  BH = 4,
25
  BL = 5,
26
  BP = 6,
27
  BPH = 7,
28
  BPL = 8,
29
  BX = 9,
30
  CH = 10,
31
  CL = 11,
32
  CS = 12,
33
  CX = 13,
34
  DF = 14,
35
  DH = 15,
36
  DI = 16,
37
  DIH = 17,
38
  DIL = 18,
39
  DL = 19,
40
  DS = 20,
41
  DX = 21,
42
  EAX = 22,
43
  EBP = 23,
44
  EBX = 24,
45
  ECX = 25,
46
  EDI = 26,
47
  EDX = 27,
48
  EFLAGS = 28,
49
  EIP = 29,
50
  EIZ = 30,
51
  ES = 31,
52
  ESI = 32,
53
  ESP = 33,
54
  FPSW = 34,
55
  FS = 35,
56
  GS = 36,
57
  HAX = 37,
58
  HBP = 38,
59
  HBX = 39,
60
  HCX = 40,
61
  HDI = 41,
62
  HDX = 42,
63
  HIP = 43,
64
  HSI = 44,
65
  HSP = 45,
66
  IP = 46,
67
  RAX = 47,
68
  RBP = 48,
69
  RBX = 49,
70
  RCX = 50,
71
  RDI = 51,
72
  RDX = 52,
73
  RIP = 53,
74
  RIZ = 54,
75
  RSI = 55,
76
  RSP = 56,
77
  SI = 57,
78
  SIH = 58,
79
  SIL = 59,
80
  SP = 60,
81
  SPH = 61,
82
  SPL = 62,
83
  SS = 63,
84
  SSP = 64,
85
  BND0 = 65,
86
  BND1 = 66,
87
  BND2 = 67,
88
  BND3 = 68,
89
  CR0 = 69,
90
  CR1 = 70,
91
  CR2 = 71,
92
  CR3 = 72,
93
  CR4 = 73,
94
  CR5 = 74,
95
  CR6 = 75,
96
  CR7 = 76,
97
  CR8 = 77,
98
  CR9 = 78,
99
  CR10 = 79,
100
  CR11 = 80,
101
  CR12 = 81,
102
  CR13 = 82,
103
  CR14 = 83,
104
  CR15 = 84,
105
  DR0 = 85,
106
  DR1 = 86,
107
  DR2 = 87,
108
  DR3 = 88,
109
  DR4 = 89,
110
  DR5 = 90,
111
  DR6 = 91,
112
  DR7 = 92,
113
  DR8 = 93,
114
  DR9 = 94,
115
  DR10 = 95,
116
  DR11 = 96,
117
  DR12 = 97,
118
  DR13 = 98,
119
  DR14 = 99,
120
  DR15 = 100,
121
  FP0 = 101,
122
  FP1 = 102,
123
  FP2 = 103,
124
  FP3 = 104,
125
  FP4 = 105,
126
  FP5 = 106,
127
  FP6 = 107,
128
  FP7 = 108,
129
  K0 = 109,
130
  K1 = 110,
131
  K2 = 111,
132
  K3 = 112,
133
  K4 = 113,
134
  K5 = 114,
135
  K6 = 115,
136
  K7 = 116,
137
  MM0 = 117,
138
  MM1 = 118,
139
  MM2 = 119,
140
  MM3 = 120,
141
  MM4 = 121,
142
  MM5 = 122,
143
  MM6 = 123,
144
  MM7 = 124,
145
  R8 = 125,
146
  R9 = 126,
147
  R10 = 127,
148
  R11 = 128,
149
  R12 = 129,
150
  R13 = 130,
151
  R14 = 131,
152
  R15 = 132,
153
  ST0 = 133,
154
  ST1 = 134,
155
  ST2 = 135,
156
  ST3 = 136,
157
  ST4 = 137,
158
  ST5 = 138,
159
  ST6 = 139,
160
  ST7 = 140,
161
  XMM0 = 141,
162
  XMM1 = 142,
163
  XMM2 = 143,
164
  XMM3 = 144,
165
  XMM4 = 145,
166
  XMM5 = 146,
167
  XMM6 = 147,
168
  XMM7 = 148,
169
  XMM8 = 149,
170
  XMM9 = 150,
171
  XMM10 = 151,
172
  XMM11 = 152,
173
  XMM12 = 153,
174
  XMM13 = 154,
175
  XMM14 = 155,
176
  XMM15 = 156,
177
  XMM16 = 157,
178
  XMM17 = 158,
179
  XMM18 = 159,
180
  XMM19 = 160,
181
  XMM20 = 161,
182
  XMM21 = 162,
183
  XMM22 = 163,
184
  XMM23 = 164,
185
  XMM24 = 165,
186
  XMM25 = 166,
187
  XMM26 = 167,
188
  XMM27 = 168,
189
  XMM28 = 169,
190
  XMM29 = 170,
191
  XMM30 = 171,
192
  XMM31 = 172,
193
  YMM0 = 173,
194
  YMM1 = 174,
195
  YMM2 = 175,
196
  YMM3 = 176,
197
  YMM4 = 177,
198
  YMM5 = 178,
199
  YMM6 = 179,
200
  YMM7 = 180,
201
  YMM8 = 181,
202
  YMM9 = 182,
203
  YMM10 = 183,
204
  YMM11 = 184,
205
  YMM12 = 185,
206
  YMM13 = 186,
207
  YMM14 = 187,
208
  YMM15 = 188,
209
  YMM16 = 189,
210
  YMM17 = 190,
211
  YMM18 = 191,
212
  YMM19 = 192,
213
  YMM20 = 193,
214
  YMM21 = 194,
215
  YMM22 = 195,
216
  YMM23 = 196,
217
  YMM24 = 197,
218
  YMM25 = 198,
219
  YMM26 = 199,
220
  YMM27 = 200,
221
  YMM28 = 201,
222
  YMM29 = 202,
223
  YMM30 = 203,
224
  YMM31 = 204,
225
  ZMM0 = 205,
226
  ZMM1 = 206,
227
  ZMM2 = 207,
228
  ZMM3 = 208,
229
  ZMM4 = 209,
230
  ZMM5 = 210,
231
  ZMM6 = 211,
232
  ZMM7 = 212,
233
  ZMM8 = 213,
234
  ZMM9 = 214,
235
  ZMM10 = 215,
236
  ZMM11 = 216,
237
  ZMM12 = 217,
238
  ZMM13 = 218,
239
  ZMM14 = 219,
240
  ZMM15 = 220,
241
  ZMM16 = 221,
242
  ZMM17 = 222,
243
  ZMM18 = 223,
244
  ZMM19 = 224,
245
  ZMM20 = 225,
246
  ZMM21 = 226,
247
  ZMM22 = 227,
248
  ZMM23 = 228,
249
  ZMM24 = 229,
250
  ZMM25 = 230,
251
  ZMM26 = 231,
252
  ZMM27 = 232,
253
  ZMM28 = 233,
254
  ZMM29 = 234,
255
  ZMM30 = 235,
256
  ZMM31 = 236,
257
  R8B = 237,
258
  R9B = 238,
259
  R10B = 239,
260
  R11B = 240,
261
  R12B = 241,
262
  R13B = 242,
263
  R14B = 243,
264
  R15B = 244,
265
  R8BH = 245,
266
  R9BH = 246,
267
  R10BH = 247,
268
  R11BH = 248,
269
  R12BH = 249,
270
  R13BH = 250,
271
  R14BH = 251,
272
  R15BH = 252,
273
  R8D = 253,
274
  R9D = 254,
275
  R10D = 255,
276
  R11D = 256,
277
  R12D = 257,
278
  R13D = 258,
279
  R14D = 259,
280
  R15D = 260,
281
  R8W = 261,
282
  R9W = 262,
283
  R10W = 263,
284
  R11W = 264,
285
  R12W = 265,
286
  R13W = 266,
287
  R14W = 267,
288
  R15W = 268,
289
  R8WH = 269,
290
  R9WH = 270,
291
  R10WH = 271,
292
  R11WH = 272,
293
  R12WH = 273,
294
  R13WH = 274,
295
  R14WH = 275,
296
  R15WH = 276,
297
  NUM_TARGET_REGS   // 277
298
};
299
} // end namespace X86
300
301
// Register classes
302
303
namespace X86 {
304
enum {
305
  GR8RegClassID = 0,
306
  GRH8RegClassID = 1,
307
  GR8_NOREXRegClassID = 2,
308
  GR8_ABCD_HRegClassID = 3,
309
  GR8_ABCD_LRegClassID = 4,
310
  GRH16RegClassID = 5,
311
  GR16RegClassID = 6,
312
  GR16_NOREXRegClassID = 7,
313
  VK1RegClassID = 8,
314
  VK16RegClassID = 9,
315
  VK2RegClassID = 10,
316
  VK4RegClassID = 11,
317
  VK8RegClassID = 12,
318
  VK16WMRegClassID = 13,
319
  VK1WMRegClassID = 14,
320
  VK2WMRegClassID = 15,
321
  VK4WMRegClassID = 16,
322
  VK8WMRegClassID = 17,
323
  SEGMENT_REGRegClassID = 18,
324
  GR16_ABCDRegClassID = 19,
325
  FPCCRRegClassID = 20,
326
  FR32XRegClassID = 21,
327
  LOW32_ADDR_ACCESS_RBPRegClassID = 22,
328
  LOW32_ADDR_ACCESSRegClassID = 23,
329
  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24,
330
  DEBUG_REGRegClassID = 25,
331
  FR32RegClassID = 26,
332
  GR32RegClassID = 27,
333
  GR32_NOSPRegClassID = 28,
334
  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29,
335
  GR32_NOREXRegClassID = 30,
336
  VK32RegClassID = 31,
337
  GR32_NOREX_NOSPRegClassID = 32,
338
  RFP32RegClassID = 33,
339
  VK32WMRegClassID = 34,
340
  GR32_ABCDRegClassID = 35,
341
  GR32_TCRegClassID = 36,
342
  GR32_ADRegClassID = 37,
343
  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 38,
344
  CCRRegClassID = 39,
345
  DFCCRRegClassID = 40,
346
  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 41,
347
  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 42,
348
  RFP64RegClassID = 43,
349
  FR64XRegClassID = 44,
350
  GR64RegClassID = 45,
351
  CONTROL_REGRegClassID = 46,
352
  FR64RegClassID = 47,
353
  GR64_with_sub_8bitRegClassID = 48,
354
  GR64_NOSPRegClassID = 49,
355
  GR64_NOREXRegClassID = 50,
356
  GR64_TCRegClassID = 51,
357
  GR64_NOSP_and_GR64_TCRegClassID = 52,
358
  GR64_TCW64RegClassID = 53,
359
  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 54,
360
  VK64RegClassID = 55,
361
  VR64RegClassID = 56,
362
  GR64_NOREX_NOSPRegClassID = 57,
363
  GR64_NOSP_and_GR64_TCW64RegClassID = 58,
364
  GR64_TC_and_GR64_TCW64RegClassID = 59,
365
  VK64WMRegClassID = 60,
366
  GR64_NOREX_and_GR64_TCRegClassID = 61,
367
  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 62,
368
  GR64_NOREX_NOSP_and_GR64_TCRegClassID = 63,
369
  GR64_ABCDRegClassID = 64,
370
  GR64_NOREX_and_GR64_TCW64RegClassID = 65,
371
  GR64_with_sub_32bit_in_GR32_TCRegClassID = 66,
372
  GR64_ADRegClassID = 67,
373
  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 68,
374
  GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID = 69,
375
  GR64_and_LOW32_ADDR_ACCESSRegClassID = 70,
376
  RSTRegClassID = 71,
377
  RFP80RegClassID = 72,
378
  VR128XRegClassID = 73,
379
  VR128RegClassID = 74,
380
  VR128HRegClassID = 75,
381
  VR128LRegClassID = 76,
382
  BNDRRegClassID = 77,
383
  VR256XRegClassID = 78,
384
  VR256RegClassID = 79,
385
  VR256HRegClassID = 80,
386
  VR256LRegClassID = 81,
387
  VR512RegClassID = 82,
388
  VR512_with_sub_xmm_in_FR32RegClassID = 83,
389
  VR512_with_sub_xmm_in_VR128HRegClassID = 84,
390
  VR512_with_sub_xmm_in_VR128LRegClassID = 85,
391
392
  };
393
} // end namespace X86
394
395
396
// Subregister indices
397
398
namespace X86 {
399
enum {
400
  NoSubRegister,
401
  sub_8bit, // 1
402
  sub_8bit_hi,  // 2
403
  sub_8bit_hi_phony,  // 3
404
  sub_16bit,  // 4
405
  sub_16bit_hi, // 5
406
  sub_32bit,  // 6
407
  sub_xmm,  // 7
408
  sub_ymm,  // 8
409
  NUM_TARGET_SUBREGS
410
};
411
} // end namespace X86
412
413
} // end namespace llvm
414
415
#endif // GET_REGINFO_ENUM
416
417
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
418
|*                                                                            *|
419
|* MC Register Information                                                    *|
420
|*                                                                            *|
421
|* Automatically generated file, do not edit!                                 *|
422
|*                                                                            *|
423
\*===----------------------------------------------------------------------===*/
424
425
426
#ifdef GET_REGINFO_MC_DESC
427
#undef GET_REGINFO_MC_DESC
428
429
namespace llvm {
430
431
extern const MCPhysReg X86RegDiffLists[] = {
432
  /* 0 */ 0, 1, 0,
433
  /* 3 */ 64875, 1, 1, 0,
434
  /* 7 */ 65259, 1, 1, 0,
435
  /* 11 */ 65397, 1, 1, 0,
436
  /* 15 */ 65466, 1, 1, 0,
437
  /* 19 */ 2, 1, 0,
438
  /* 22 */ 4, 1, 0,
439
  /* 25 */ 6, 1, 0,
440
  /* 28 */ 11, 1, 0,
441
  /* 31 */ 22, 1, 0,
442
  /* 34 */ 26, 1, 0,
443
  /* 37 */ 29, 1, 0,
444
  /* 40 */ 64851, 1, 0,
445
  /* 43 */ 10, 3, 0,
446
  /* 46 */ 4, 0,
447
  /* 48 */ 5, 0,
448
  /* 50 */ 65292, 1, 7, 0,
449
  /* 54 */ 65417, 1, 7, 0,
450
  /* 58 */ 10, 3, 7, 0,
451
  /* 62 */ 65512, 8, 0,
452
  /* 65 */ 65342, 1, 11, 0,
453
  /* 69 */ 65348, 1, 11, 0,
454
  /* 73 */ 65442, 1, 11, 0,
455
  /* 77 */ 65448, 1, 11, 0,
456
  /* 81 */ 12, 0,
457
  /* 83 */ 65342, 1, 14, 0,
458
  /* 87 */ 65348, 1, 14, 0,
459
  /* 91 */ 65442, 1, 14, 0,
460
  /* 95 */ 65448, 1, 14, 0,
461
  /* 99 */ 21, 0,
462
  /* 101 */ 22, 0,
463
  /* 103 */ 65534, 65509, 23, 0,
464
  /* 107 */ 65535, 65509, 23, 0,
465
  /* 111 */ 65534, 65511, 23, 0,
466
  /* 115 */ 65535, 65511, 23, 0,
467
  /* 119 */ 65524, 23, 0,
468
  /* 122 */ 128, 8, 65512, 8, 24, 0,
469
  /* 128 */ 65519, 24, 0,
470
  /* 131 */ 65522, 24, 0,
471
  /* 134 */ 65511, 65526, 2, 65535, 24, 0,
472
  /* 140 */ 2, 6, 25, 0,
473
  /* 144 */ 6, 6, 25, 0,
474
  /* 148 */ 65534, 10, 25, 0,
475
  /* 152 */ 65535, 10, 25, 0,
476
  /* 156 */ 2, 12, 25, 0,
477
  /* 160 */ 3, 12, 25, 0,
478
  /* 164 */ 4, 15, 25, 0,
479
  /* 168 */ 5, 15, 25, 0,
480
  /* 172 */ 65534, 17, 25, 0,
481
  /* 176 */ 65535, 17, 25, 0,
482
  /* 180 */ 1, 19, 25, 0,
483
  /* 184 */ 2, 19, 25, 0,
484
  /* 188 */ 65521, 25, 0,
485
  /* 191 */ 26, 0,
486
  /* 193 */ 65511, 65530, 65534, 65532, 27, 0,
487
  /* 199 */ 65511, 65524, 65534, 65535, 30, 0,
488
  /* 205 */ 65511, 65519, 2, 65535, 31, 0,
489
  /* 211 */ 32, 32, 0,
490
  /* 214 */ 65511, 65521, 65532, 65535, 35, 0,
491
  /* 220 */ 65511, 65517, 65535, 65535, 36, 0,
492
  /* 226 */ 64829, 0,
493
  /* 228 */ 64900, 0,
494
  /* 230 */ 64923, 0,
495
  /* 232 */ 65131, 0,
496
  /* 234 */ 65520, 65408, 0,
497
  /* 237 */ 16, 65528, 65408, 0,
498
  /* 241 */ 24, 65528, 65408, 0,
499
  /* 245 */ 65430, 0,
500
  /* 247 */ 65432, 0,
501
  /* 249 */ 65461, 0,
502
  /* 251 */ 65493, 0,
503
  /* 253 */ 65504, 65504, 0,
504
  /* 256 */ 65509, 0,
505
  /* 258 */ 65511, 0,
506
  /* 260 */ 65514, 0,
507
  /* 262 */ 65513, 27, 2, 65535, 65520, 0,
508
  /* 268 */ 65513, 25, 2, 65535, 65522, 0,
509
  /* 274 */ 65525, 0,
510
  /* 276 */ 65530, 0,
511
  /* 278 */ 65531, 0,
512
  /* 280 */ 65534, 65532, 0,
513
  /* 283 */ 65512, 17, 65533, 0,
514
  /* 287 */ 65534, 0,
515
  /* 289 */ 2, 65535, 0,
516
  /* 292 */ 65532, 65535, 0,
517
  /* 295 */ 65534, 65535, 0,
518
  /* 298 */ 65535, 65535, 0,
519
};
520
521
extern const LaneBitmask X86LaneMaskLists[] = {
522
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
523
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
524
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(),
525
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(),
526
  /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
527
  /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(),
528
  /* 19 */ LaneBitmask(0x00000010), LaneBitmask::getAll(),
529
};
530
531
extern const uint16_t X86SubRegIdxLists[] = {
532
  /* 0 */ 1, 2, 0,
533
  /* 3 */ 1, 3, 0,
534
  /* 6 */ 6, 4, 1, 2, 5, 0,
535
  /* 12 */ 6, 4, 1, 3, 5, 0,
536
  /* 18 */ 6, 4, 5, 0,
537
  /* 22 */ 8, 7, 0,
538
};
539
540
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
541
  { 65535, 65535 },
542
  { 0, 8 }, // sub_8bit
543
  { 8, 8 }, // sub_8bit_hi
544
  { 8, 8 }, // sub_8bit_hi_phony
545
  { 0, 16 },  // sub_16bit
546
  { 16, 16 }, // sub_16bit_hi
547
  { 0, 32 },  // sub_32bit
548
  { 0, 128 }, // sub_xmm
549
  { 0, 256 }, // sub_ymm
550
};
551
552
extern const char X86RegStrings[] = {
553
  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
554
  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
555
  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
556
  /* 18 */ 'C', 'R', '1', '0', 0,
557
  /* 23 */ 'D', 'R', '1', '0', 0,
558
  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
559
  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
560
  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
561
  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
562
  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
563
  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
564
  /* 64 */ 'B', 'N', 'D', '0', 0,
565
  /* 69 */ 'K', '0', 0,
566
  /* 72 */ 'X', 'M', 'M', '0', 0,
567
  /* 77 */ 'Y', 'M', 'M', '0', 0,
568
  /* 82 */ 'Z', 'M', 'M', '0', 0,
569
  /* 87 */ 'F', 'P', '0', 0,
570
  /* 91 */ 'C', 'R', '0', 0,
571
  /* 95 */ 'D', 'R', '0', 0,
572
  /* 99 */ 'S', 'T', '0', 0,
573
  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
574
  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
575
  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
576
  /* 121 */ 'C', 'R', '1', '1', 0,
577
  /* 126 */ 'D', 'R', '1', '1', 0,
578
  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
579
  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
580
  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
581
  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
582
  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
583
  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
584
  /* 167 */ 'B', 'N', 'D', '1', 0,
585
  /* 172 */ 'K', '1', 0,
586
  /* 175 */ 'X', 'M', 'M', '1', 0,
587
  /* 180 */ 'Y', 'M', 'M', '1', 0,
588
  /* 185 */ 'Z', 'M', 'M', '1', 0,
589
  /* 190 */ 'F', 'P', '1', 0,
590
  /* 194 */ 'C', 'R', '1', 0,
591
  /* 198 */ 'D', 'R', '1', 0,
592
  /* 202 */ 'S', 'T', '1', 0,
593
  /* 206 */ 'X', 'M', 'M', '1', '2', 0,
594
  /* 212 */ 'Y', 'M', 'M', '1', '2', 0,
595
  /* 218 */ 'Z', 'M', 'M', '1', '2', 0,
596
  /* 224 */ 'C', 'R', '1', '2', 0,
597
  /* 229 */ 'D', 'R', '1', '2', 0,
598
  /* 234 */ 'X', 'M', 'M', '2', '2', 0,
599
  /* 240 */ 'Y', 'M', 'M', '2', '2', 0,
600
  /* 246 */ 'Z', 'M', 'M', '2', '2', 0,
601
  /* 252 */ 'B', 'N', 'D', '2', 0,
602
  /* 257 */ 'K', '2', 0,
603
  /* 260 */ 'X', 'M', 'M', '2', 0,
604
  /* 265 */ 'Y', 'M', 'M', '2', 0,
605
  /* 270 */ 'Z', 'M', 'M', '2', 0,
606
  /* 275 */ 'F', 'P', '2', 0,
607
  /* 279 */ 'C', 'R', '2', 0,
608
  /* 283 */ 'D', 'R', '2', 0,
609
  /* 287 */ 'S', 'T', '2', 0,
610
  /* 291 */ 'X', 'M', 'M', '1', '3', 0,
611
  /* 297 */ 'Y', 'M', 'M', '1', '3', 0,
612
  /* 303 */ 'Z', 'M', 'M', '1', '3', 0,
613
  /* 309 */ 'C', 'R', '1', '3', 0,
614
  /* 314 */ 'D', 'R', '1', '3', 0,
615
  /* 319 */ 'X', 'M', 'M', '2', '3', 0,
616
  /* 325 */ 'Y', 'M', 'M', '2', '3', 0,
617
  /* 331 */ 'Z', 'M', 'M', '2', '3', 0,
618
  /* 337 */ 'B', 'N', 'D', '3', 0,
619
  /* 342 */ 'K', '3', 0,
620
  /* 345 */ 'X', 'M', 'M', '3', 0,
621
  /* 350 */ 'Y', 'M', 'M', '3', 0,
622
  /* 355 */ 'Z', 'M', 'M', '3', 0,
623
  /* 360 */ 'F', 'P', '3', 0,
624
  /* 364 */ 'C', 'R', '3', 0,
625
  /* 368 */ 'D', 'R', '3', 0,
626
  /* 372 */ 'S', 'T', '3', 0,
627
  /* 376 */ 'X', 'M', 'M', '1', '4', 0,
628
  /* 382 */ 'Y', 'M', 'M', '1', '4', 0,
629
  /* 388 */ 'Z', 'M', 'M', '1', '4', 0,
630
  /* 394 */ 'C', 'R', '1', '4', 0,
631
  /* 399 */ 'D', 'R', '1', '4', 0,
632
  /* 404 */ 'X', 'M', 'M', '2', '4', 0,
633
  /* 410 */ 'Y', 'M', 'M', '2', '4', 0,
634
  /* 416 */ 'Z', 'M', 'M', '2', '4', 0,
635
  /* 422 */ 'K', '4', 0,
636
  /* 425 */ 'X', 'M', 'M', '4', 0,
637
  /* 430 */ 'Y', 'M', 'M', '4', 0,
638
  /* 435 */ 'Z', 'M', 'M', '4', 0,
639
  /* 440 */ 'F', 'P', '4', 0,
640
  /* 444 */ 'C', 'R', '4', 0,
641
  /* 448 */ 'D', 'R', '4', 0,
642
  /* 452 */ 'S', 'T', '4', 0,
643
  /* 456 */ 'X', 'M', 'M', '1', '5', 0,
644
  /* 462 */ 'Y', 'M', 'M', '1', '5', 0,
645
  /* 468 */ 'Z', 'M', 'M', '1', '5', 0,
646
  /* 474 */ 'C', 'R', '1', '5', 0,
647
  /* 479 */ 'D', 'R', '1', '5', 0,
648
  /* 484 */ 'X', 'M', 'M', '2', '5', 0,
649
  /* 490 */ 'Y', 'M', 'M', '2', '5', 0,
650
  /* 496 */ 'Z', 'M', 'M', '2', '5', 0,
651
  /* 502 */ 'K', '5', 0,
652
  /* 505 */ 'X', 'M', 'M', '5', 0,
653
  /* 510 */ 'Y', 'M', 'M', '5', 0,
654
  /* 515 */ 'Z', 'M', 'M', '5', 0,
655
  /* 520 */ 'F', 'P', '5', 0,
656
  /* 524 */ 'C', 'R', '5', 0,
657
  /* 528 */ 'D', 'R', '5', 0,
658
  /* 532 */ 'S', 'T', '5', 0,
659
  /* 536 */ 'X', 'M', 'M', '1', '6', 0,
660
  /* 542 */ 'Y', 'M', 'M', '1', '6', 0,
661
  /* 548 */ 'Z', 'M', 'M', '1', '6', 0,
662
  /* 554 */ 'X', 'M', 'M', '2', '6', 0,
663
  /* 560 */ 'Y', 'M', 'M', '2', '6', 0,
664
  /* 566 */ 'Z', 'M', 'M', '2', '6', 0,
665
  /* 572 */ 'K', '6', 0,
666
  /* 575 */ 'X', 'M', 'M', '6', 0,
667
  /* 580 */ 'Y', 'M', 'M', '6', 0,
668
  /* 585 */ 'Z', 'M', 'M', '6', 0,
669
  /* 590 */ 'F', 'P', '6', 0,
670
  /* 594 */ 'C', 'R', '6', 0,
671
  /* 598 */ 'D', 'R', '6', 0,
672
  /* 602 */ 'S', 'T', '6', 0,
673
  /* 606 */ 'X', 'M', 'M', '1', '7', 0,
674
  /* 612 */ 'Y', 'M', 'M', '1', '7', 0,
675
  /* 618 */ 'Z', 'M', 'M', '1', '7', 0,
676
  /* 624 */ 'X', 'M', 'M', '2', '7', 0,
677
  /* 630 */ 'Y', 'M', 'M', '2', '7', 0,
678
  /* 636 */ 'Z', 'M', 'M', '2', '7', 0,
679
  /* 642 */ 'K', '7', 0,
680
  /* 645 */ 'X', 'M', 'M', '7', 0,
681
  /* 650 */ 'Y', 'M', 'M', '7', 0,
682
  /* 655 */ 'Z', 'M', 'M', '7', 0,
683
  /* 660 */ 'F', 'P', '7', 0,
684
  /* 664 */ 'C', 'R', '7', 0,
685
  /* 668 */ 'D', 'R', '7', 0,
686
  /* 672 */ 'S', 'T', '7', 0,
687
  /* 676 */ 'X', 'M', 'M', '1', '8', 0,
688
  /* 682 */ 'Y', 'M', 'M', '1', '8', 0,
689
  /* 688 */ 'Z', 'M', 'M', '1', '8', 0,
690
  /* 694 */ 'X', 'M', 'M', '2', '8', 0,
691
  /* 700 */ 'Y', 'M', 'M', '2', '8', 0,
692
  /* 706 */ 'Z', 'M', 'M', '2', '8', 0,
693
  /* 712 */ 'X', 'M', 'M', '8', 0,
694
  /* 717 */ 'Y', 'M', 'M', '8', 0,
695
  /* 722 */ 'Z', 'M', 'M', '8', 0,
696
  /* 727 */ 'C', 'R', '8', 0,
697
  /* 731 */ 'D', 'R', '8', 0,
698
  /* 735 */ 'X', 'M', 'M', '1', '9', 0,
699
  /* 741 */ 'Y', 'M', 'M', '1', '9', 0,
700
  /* 747 */ 'Z', 'M', 'M', '1', '9', 0,
701
  /* 753 */ 'X', 'M', 'M', '2', '9', 0,
702
  /* 759 */ 'Y', 'M', 'M', '2', '9', 0,
703
  /* 765 */ 'Z', 'M', 'M', '2', '9', 0,
704
  /* 771 */ 'X', 'M', 'M', '9', 0,
705
  /* 776 */ 'Y', 'M', 'M', '9', 0,
706
  /* 781 */ 'Z', 'M', 'M', '9', 0,
707
  /* 786 */ 'C', 'R', '9', 0,
708
  /* 790 */ 'D', 'R', '9', 0,
709
  /* 794 */ 'R', '1', '0', 'B', 0,
710
  /* 799 */ 'R', '1', '1', 'B', 0,
711
  /* 804 */ 'R', '1', '2', 'B', 0,
712
  /* 809 */ 'R', '1', '3', 'B', 0,
713
  /* 814 */ 'R', '1', '4', 'B', 0,
714
  /* 819 */ 'R', '1', '5', 'B', 0,
715
  /* 824 */ 'R', '8', 'B', 0,
716
  /* 828 */ 'R', '9', 'B', 0,
717
  /* 832 */ 'R', '1', '0', 'D', 0,
718
  /* 837 */ 'R', '1', '1', 'D', 0,
719
  /* 842 */ 'R', '1', '2', 'D', 0,
720
  /* 847 */ 'R', '1', '3', 'D', 0,
721
  /* 852 */ 'R', '1', '4', 'D', 0,
722
  /* 857 */ 'R', '1', '5', 'D', 0,
723
  /* 862 */ 'R', '8', 'D', 0,
724
  /* 866 */ 'R', '9', 'D', 0,
725
  /* 870 */ 'D', 'F', 0,
726
  /* 873 */ 'A', 'H', 0,
727
  /* 876 */ 'R', '1', '0', 'B', 'H', 0,
728
  /* 882 */ 'R', '1', '1', 'B', 'H', 0,
729
  /* 888 */ 'R', '1', '2', 'B', 'H', 0,
730
  /* 894 */ 'R', '1', '3', 'B', 'H', 0,
731
  /* 900 */ 'R', '1', '4', 'B', 'H', 0,
732
  /* 906 */ 'R', '1', '5', 'B', 'H', 0,
733
  /* 912 */ 'R', '8', 'B', 'H', 0,
734
  /* 917 */ 'R', '9', 'B', 'H', 0,
735
  /* 922 */ 'C', 'H', 0,
736
  /* 925 */ 'D', 'H', 0,
737
  /* 928 */ 'D', 'I', 'H', 0,
738
  /* 932 */ 'S', 'I', 'H', 0,
739
  /* 936 */ 'B', 'P', 'H', 0,
740
  /* 940 */ 'S', 'P', 'H', 0,
741
  /* 944 */ 'R', '1', '0', 'W', 'H', 0,
742
  /* 950 */ 'R', '1', '1', 'W', 'H', 0,
743
  /* 956 */ 'R', '1', '2', 'W', 'H', 0,
744
  /* 962 */ 'R', '1', '3', 'W', 'H', 0,
745
  /* 968 */ 'R', '1', '4', 'W', 'H', 0,
746
  /* 974 */ 'R', '1', '5', 'W', 'H', 0,
747
  /* 980 */ 'R', '8', 'W', 'H', 0,
748
  /* 985 */ 'R', '9', 'W', 'H', 0,
749
  /* 990 */ 'E', 'D', 'I', 0,
750
  /* 994 */ 'H', 'D', 'I', 0,
751
  /* 998 */ 'R', 'D', 'I', 0,
752
  /* 1002 */ 'E', 'S', 'I', 0,
753
  /* 1006 */ 'H', 'S', 'I', 0,
754
  /* 1010 */ 'R', 'S', 'I', 0,
755
  /* 1014 */ 'A', 'L', 0,
756
  /* 1017 */ 'B', 'L', 0,
757
  /* 1020 */ 'C', 'L', 0,
758
  /* 1023 */ 'D', 'L', 0,
759
  /* 1026 */ 'D', 'I', 'L', 0,
760
  /* 1030 */ 'S', 'I', 'L', 0,
761
  /* 1034 */ 'B', 'P', 'L', 0,
762
  /* 1038 */ 'S', 'P', 'L', 0,
763
  /* 1042 */ 'E', 'B', 'P', 0,
764
  /* 1046 */ 'H', 'B', 'P', 0,
765
  /* 1050 */ 'R', 'B', 'P', 0,
766
  /* 1054 */ 'E', 'I', 'P', 0,
767
  /* 1058 */ 'H', 'I', 'P', 0,
768
  /* 1062 */ 'R', 'I', 'P', 0,
769
  /* 1066 */ 'E', 'S', 'P', 0,
770
  /* 1070 */ 'H', 'S', 'P', 0,
771
  /* 1074 */ 'R', 'S', 'P', 0,
772
  /* 1078 */ 'S', 'S', 'P', 0,
773
  /* 1082 */ 'C', 'S', 0,
774
  /* 1085 */ 'D', 'S', 0,
775
  /* 1088 */ 'E', 'S', 0,
776
  /* 1091 */ 'F', 'S', 0,
777
  /* 1094 */ 'E', 'F', 'L', 'A', 'G', 'S', 0,
778
  /* 1101 */ 'S', 'S', 0,
779
  /* 1104 */ 'R', '1', '0', 'W', 0,
780
  /* 1109 */ 'R', '1', '1', 'W', 0,
781
  /* 1114 */ 'R', '1', '2', 'W', 0,
782
  /* 1119 */ 'R', '1', '3', 'W', 0,
783
  /* 1124 */ 'R', '1', '4', 'W', 0,
784
  /* 1129 */ 'R', '1', '5', 'W', 0,
785
  /* 1134 */ 'R', '8', 'W', 0,
786
  /* 1138 */ 'R', '9', 'W', 0,
787
  /* 1142 */ 'F', 'P', 'S', 'W', 0,
788
  /* 1147 */ 'E', 'A', 'X', 0,
789
  /* 1151 */ 'H', 'A', 'X', 0,
790
  /* 1155 */ 'R', 'A', 'X', 0,
791
  /* 1159 */ 'E', 'B', 'X', 0,
792
  /* 1163 */ 'H', 'B', 'X', 0,
793
  /* 1167 */ 'R', 'B', 'X', 0,
794
  /* 1171 */ 'E', 'C', 'X', 0,
795
  /* 1175 */ 'H', 'C', 'X', 0,
796
  /* 1179 */ 'R', 'C', 'X', 0,
797
  /* 1183 */ 'E', 'D', 'X', 0,
798
  /* 1187 */ 'H', 'D', 'X', 0,
799
  /* 1191 */ 'R', 'D', 'X', 0,
800
  /* 1195 */ 'E', 'I', 'Z', 0,
801
  /* 1199 */ 'R', 'I', 'Z', 0,
802
};
803
804
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
805
  { 5, 0, 0, 0, 0, 0 },
806
  { 873, 2, 184, 2, 4641, 0 },
807
  { 1014, 2, 180, 2, 4641, 0 },
808
  { 1148, 298, 181, 0, 0, 2 },
809
  { 879, 2, 168, 2, 4593, 0 },
810
  { 1017, 2, 164, 2, 4593, 0 },
811
  { 1043, 289, 173, 3, 352, 5 },
812
  { 936, 2, 176, 2, 768, 0 },
813
  { 1034, 2, 172, 2, 736, 0 },
814
  { 1160, 292, 165, 0, 304, 2 },
815
  { 922, 2, 160, 2, 4497, 0 },
816
  { 1020, 2, 156, 2, 4497, 0 },
817
  { 1082, 2, 2, 2, 4497, 0 },
818
  { 1172, 295, 157, 0, 400, 2 },
819
  { 870, 2, 2, 2, 4449, 0 },
820
  { 925, 2, 144, 2, 4449, 0 },
821
  { 991, 289, 149, 3, 448, 5 },
822
  { 928, 2, 152, 2, 1296, 0 },
823
  { 1026, 2, 148, 2, 4130, 0 },
824
  { 1023, 2, 140, 2, 4417, 0 },
825
  { 1085, 2, 2, 2, 4417, 0 },
826
  { 1184, 280, 141, 0, 688, 2 },
827
  { 1147, 221, 142, 7, 1524, 8 },
828
  { 1042, 206, 142, 13, 1236, 12 },
829
  { 1159, 215, 142, 7, 1460, 8 },
830
  { 1171, 200, 142, 7, 1172, 8 },
831
  { 990, 135, 142, 13, 869, 12 },
832
  { 1183, 194, 142, 7, 928, 8 },
833
  { 1094, 2, 2, 2, 1584, 0 },
834
  { 1054, 284, 126, 19, 496, 16 },
835
  { 1195, 2, 2, 2, 4417, 0 },
836
  { 1088, 2, 2, 2, 4417, 0 },
837
  { 1002, 269, 105, 13, 243, 12 },
838
  { 1066, 263, 105, 13, 243, 12 },
839
  { 1142, 2, 2, 2, 4593, 0 },
840
  { 1091, 2, 2, 2, 4593, 0 },
841
  { 1098, 2, 2, 2, 4593, 0 },
842
  { 1151, 2, 188, 2, 4161, 0 },
843
  { 1046, 2, 188, 2, 4161, 0 },
844
  { 1163, 2, 188, 2, 4161, 0 },
845
  { 1175, 2, 188, 2, 4161, 0 },
846
  { 994, 2, 188, 2, 4161, 0 },
847
  { 1187, 2, 188, 2, 4161, 0 },
848
  { 1058, 2, 131, 2, 3923, 0 },
849
  { 1006, 2, 119, 2, 3955, 0 },
850
  { 1070, 2, 119, 2, 3955, 0 },
851
  { 1055, 2, 128, 2, 1616, 0 },
852
  { 1155, 220, 2, 6, 1396, 8 },
853
  { 1050, 205, 2, 12, 1108, 12 },
854
  { 1167, 214, 2, 6, 1332, 8 },
855
  { 1179, 199, 2, 6, 1044, 8 },
856
  { 998, 134, 2, 12, 805, 12 },
857
  { 1191, 193, 2, 6, 928, 8 },
858
  { 1062, 283, 2, 18, 496, 16 },
859
  { 1199, 2, 2, 2, 3488, 0 },
860
  { 1010, 268, 2, 12, 179, 12 },
861
  { 1074, 262, 2, 12, 179, 12 },
862
  { 1003, 289, 112, 3, 544, 5 },
863
  { 932, 2, 115, 2, 3152, 0 },
864
  { 1030, 2, 111, 2, 3056, 0 },
865
  { 1067, 289, 104, 3, 592, 5 },
866
  { 940, 2, 107, 2, 3248, 0 },
867
  { 1038, 2, 103, 2, 3719, 0 },
868
  { 1101, 2, 2, 2, 4097, 0 },
869
  { 1078, 2, 2, 2, 4097, 0 },
870
  { 64, 2, 2, 2, 4097, 0 },
871
  { 167, 2, 2, 2, 4097, 0 },
872
  { 252, 2, 2, 2, 4097, 0 },
873
  { 337, 2, 2, 2, 4097, 0 },
874
  { 91, 2, 2, 2, 4097, 0 },
875
  { 194, 2, 2, 2, 4097, 0 },
876
  { 279, 2, 2, 2, 4097, 0 },
877
  { 364, 2, 2, 2, 4097, 0 },
878
  { 444, 2, 2, 2, 4097, 0 },
879
  { 524, 2, 2, 2, 4097, 0 },
880
  { 594, 2, 2, 2, 4097, 0 },
881
  { 664, 2, 2, 2, 4097, 0 },
882
  { 727, 2, 2, 2, 4097, 0 },
883
  { 786, 2, 2, 2, 4097, 0 },
884
  { 18, 2, 2, 2, 4097, 0 },
885
  { 121, 2, 2, 2, 4097, 0 },
886
  { 224, 2, 2, 2, 4097, 0 },
887
  { 309, 2, 2, 2, 4097, 0 },
888
  { 394, 2, 2, 2, 4097, 0 },
889
  { 474, 2, 2, 2, 4097, 0 },
890
  { 95, 2, 2, 2, 4097, 0 },
891
  { 198, 2, 2, 2, 4097, 0 },
892
  { 283, 2, 2, 2, 4097, 0 },
893
  { 368, 2, 2, 2, 4097, 0 },
894
  { 448, 2, 2, 2, 4097, 0 },
895
  { 528, 2, 2, 2, 4097, 0 },
896
  { 598, 2, 2, 2, 4097, 0 },
897
  { 668, 2, 2, 2, 4097, 0 },
898
  { 731, 2, 2, 2, 4097, 0 },
899
  { 790, 2, 2, 2, 4097, 0 },
900
  { 23, 2, 2, 2, 4097, 0 },
901
  { 126, 2, 2, 2, 4097, 0 },
902
  { 229, 2, 2, 2, 4097, 0 },
903
  { 314, 2, 2, 2, 4097, 0 },
904
  { 399, 2, 2, 2, 4097, 0 },
905
  { 479, 2, 2, 2, 4097, 0 },
906
  { 87, 2, 2, 2, 4097, 0 },
907
  { 190, 2, 2, 2, 4097, 0 },
908
  { 275, 2, 2, 2, 4097, 0 },
909
  { 360, 2, 2, 2, 4097, 0 },
910
  { 440, 2, 2, 2, 4097, 0 },
911
  { 520, 2, 2, 2, 4097, 0 },
912
  { 590, 2, 2, 2, 4097, 0 },
913
  { 660, 2, 2, 2, 4097, 0 },
914
  { 69, 2, 2, 2, 4097, 0 },
915
  { 172, 2, 2, 2, 4097, 0 },
916
  { 257, 2, 2, 2, 4097, 0 },
917
  { 342, 2, 2, 2, 4097, 0 },
918
  { 422, 2, 2, 2, 4097, 0 },
919
  { 502, 2, 2, 2, 4097, 0 },
920
  { 572, 2, 2, 2, 4097, 0 },
921
  { 642, 2, 2, 2, 4097, 0 },
922
  { 73, 2, 2, 2, 4097, 0 },
923
  { 176, 2, 2, 2, 4097, 0 },
924
  { 261, 2, 2, 2, 4097, 0 },
925
  { 346, 2, 2, 2, 4097, 0 },
926
  { 426, 2, 2, 2, 4097, 0 },
927
  { 506, 2, 2, 2, 4097, 0 },
928
  { 576, 2, 2, 2, 4097, 0 },
929
  { 646, 2, 2, 2, 4097, 0 },
930
  { 728, 122, 2, 12, 115, 12 },
931
  { 787, 122, 2, 12, 115, 12 },
932
  { 19, 122, 2, 12, 115, 12 },
933
  { 122, 122, 2, 12, 115, 12 },
934
  { 225, 122, 2, 12, 115, 12 },
935
  { 310, 122, 2, 12, 115, 12 },
936
  { 395, 122, 2, 12, 115, 12 },
937
  { 475, 122, 2, 12, 115, 12 },
938
  { 99, 2, 2, 2, 4385, 0 },
939
  { 202, 2, 2, 2, 4385, 0 },
940
  { 287, 2, 2, 2, 4385, 0 },
941
  { 372, 2, 2, 2, 4385, 0 },
942
  { 452, 2, 2, 2, 4385, 0 },
943
  { 532, 2, 2, 2, 4385, 0 },
944
  { 602, 2, 2, 2, 4385, 0 },
945
  { 672, 2, 2, 2, 4385, 0 },
946
  { 72, 2, 211, 2, 4385, 0 },
947
  { 175, 2, 211, 2, 4385, 0 },
948
  { 260, 2, 211, 2, 4385, 0 },
949
  { 345, 2, 211, 2, 4385, 0 },
950
  { 425, 2, 211, 2, 4385, 0 },
951
  { 505, 2, 211, 2, 4385, 0 },
952
  { 575, 2, 211, 2, 4385, 0 },
953
  { 645, 2, 211, 2, 4385, 0 },
954
  { 712, 2, 211, 2, 4385, 0 },
955
  { 771, 2, 211, 2, 4385, 0 },
956
  { 0, 2, 211, 2, 4385, 0 },
957
  { 103, 2, 211, 2, 4385, 0 },
958
  { 206, 2, 211, 2, 4385, 0 },
959
  { 291, 2, 211, 2, 4385, 0 },
960
  { 376, 2, 211, 2, 4385, 0 },
961
  { 456, 2, 211, 2, 4385, 0 },
962
  { 536, 2, 211, 2, 4385, 0 },
963
  { 606, 2, 211, 2, 4385, 0 },
964
  { 676, 2, 211, 2, 4385, 0 },
965
  { 735, 2, 211, 2, 4385, 0 },
966
  { 28, 2, 211, 2, 4385, 0 },
967
  { 131, 2, 211, 2, 4385, 0 },
968
  { 234, 2, 211, 2, 4385, 0 },
969
  { 319, 2, 211, 2, 4385, 0 },
970
  { 404, 2, 211, 2, 4385, 0 },
971
  { 484, 2, 211, 2, 4385, 0 },
972
  { 554, 2, 211, 2, 4385, 0 },
973
  { 624, 2, 211, 2, 4385, 0 },
974
  { 694, 2, 211, 2, 4385, 0 },
975
  { 753, 2, 211, 2, 4385, 0 },
976
  { 46, 2, 211, 2, 4385, 0 },
977
  { 149, 2, 211, 2, 4385, 0 },
978
  { 77, 254, 212, 23, 4017, 19 },
979
  { 180, 254, 212, 23, 4017, 19 },
980
  { 265, 254, 212, 23, 4017, 19 },
981
  { 350, 254, 212, 23, 4017, 19 },
982
  { 430, 254, 212, 23, 4017, 19 },
983
  { 510, 254, 212, 23, 4017, 19 },
984
  { 580, 254, 212, 23, 4017, 19 },
985
  { 650, 254, 212, 23, 4017, 19 },
986
  { 717, 254, 212, 23, 4017, 19 },
987
  { 776, 254, 212, 23, 4017, 19 },
988
  { 6, 254, 212, 23, 4017, 19 },
989
  { 109, 254, 212, 23, 4017, 19 },
990
  { 212, 254, 212, 23, 4017, 19 },
991
  { 297, 254, 212, 23, 4017, 19 },
992
  { 382, 254, 212, 23, 4017, 19 },
993
  { 462, 254, 212, 23, 4017, 19 },
994
  { 542, 254, 212, 23, 4017, 19 },
995
  { 612, 254, 212, 23, 4017, 19 },
996
  { 682, 254, 212, 23, 4017, 19 },
997
  { 741, 254, 212, 23, 4017, 19 },
998
  { 34, 254, 212, 23, 4017, 19 },
999
  { 137, 254, 212, 23, 4017, 19 },
1000
  { 240, 254, 212, 23, 4017, 19 },
1001
  { 325, 254, 212, 23, 4017, 19 },
1002
  { 410, 254, 212, 23, 4017, 19 },
1003
  { 490, 254, 212, 23, 4017, 19 },
1004
  { 560, 254, 212, 23, 4017, 19 },
1005
  { 630, 254, 212, 23, 4017, 19 },
1006
  { 700, 254, 212, 23, 4017, 19 },
1007
  { 759, 254, 212, 23, 4017, 19 },
1008
  { 52, 254, 212, 23, 4017, 19 },
1009
  { 155, 254, 212, 23, 4017, 19 },
1010
  { 82, 253, 2, 22, 3985, 19 },
1011
  { 185, 253, 2, 22, 3985, 19 },
1012
  { 270, 253, 2, 22, 3985, 19 },
1013
  { 355, 253, 2, 22, 3985, 19 },
1014
  { 435, 253, 2, 22, 3985, 19 },
1015
  { 515, 253, 2, 22, 3985, 19 },
1016
  { 585, 253, 2, 22, 3985, 19 },
1017
  { 655, 253, 2, 22, 3985, 19 },
1018
  { 722, 253, 2, 22, 3985, 19 },
1019
  { 781, 253, 2, 22, 3985, 19 },
1020
  { 12, 253, 2, 22, 3985, 19 },
1021
  { 115, 253, 2, 22, 3985, 19 },
1022
  { 218, 253, 2, 22, 3985, 19 },
1023
  { 303, 253, 2, 22, 3985, 19 },
1024
  { 388, 253, 2, 22, 3985, 19 },
1025
  { 468, 253, 2, 22, 3985, 19 },
1026
  { 548, 253, 2, 22, 3985, 19 },
1027
  { 618, 253, 2, 22, 3985, 19 },
1028
  { 688, 253, 2, 22, 3985, 19 },
1029
  { 747, 253, 2, 22, 3985, 19 },
1030
  { 40, 253, 2, 22, 3985, 19 },
1031
  { 143, 253, 2, 22, 3985, 19 },
1032
  { 246, 253, 2, 22, 3985, 19 },
1033
  { 331, 253, 2, 22, 3985, 19 },
1034
  { 416, 253, 2, 22, 3985, 19 },
1035
  { 496, 253, 2, 22, 3985, 19 },
1036
  { 566, 253, 2, 22, 3985, 19 },
1037
  { 636, 253, 2, 22, 3985, 19 },
1038
  { 706, 253, 2, 22, 3985, 19 },
1039
  { 765, 253, 2, 22, 3985, 19 },
1040
  { 58, 253, 2, 22, 3985, 19 },
1041
  { 161, 253, 2, 22, 3985, 19 },
1042
  { 824, 2, 241, 2, 3683, 0 },
1043
  { 828, 2, 241, 2, 3683, 0 },
1044
  { 794, 2, 241, 2, 3683, 0 },
1045
  { 799, 2, 241, 2, 3683, 0 },
1046
  { 804, 2, 241, 2, 3683, 0 },
1047
  { 809, 2, 241, 2, 3683, 0 },
1048
  { 814, 2, 241, 2, 3683, 0 },
1049
  { 819, 2, 241, 2, 3683, 0 },
1050
  { 912, 2, 237, 2, 3651, 0 },
1051
  { 917, 2, 237, 2, 3651, 0 },
1052
  { 876, 2, 237, 2, 3651, 0 },
1053
  { 882, 2, 237, 2, 3651, 0 },
1054
  { 888, 2, 237, 2, 3651, 0 },
1055
  { 894, 2, 237, 2, 3651, 0 },
1056
  { 900, 2, 237, 2, 3651, 0 },
1057
  { 906, 2, 237, 2, 3651, 0 },
1058
  { 862, 123, 235, 13, 51, 12 },
1059
  { 866, 123, 235, 13, 51, 12 },
1060
  { 832, 123, 235, 13, 51, 12 },
1061
  { 837, 123, 235, 13, 51, 12 },
1062
  { 842, 123, 235, 13, 51, 12 },
1063
  { 847, 123, 235, 13, 51, 12 },
1064
  { 852, 123, 235, 13, 51, 12 },
1065
  { 857, 123, 235, 13, 51, 12 },
1066
  { 1134, 62, 238, 3, 643, 5 },
1067
  { 1138, 62, 238, 3, 643, 5 },
1068
  { 1104, 62, 238, 3, 643, 5 },
1069
  { 1109, 62, 238, 3, 643, 5 },
1070
  { 1114, 62, 238, 3, 643, 5 },
1071
  { 1119, 62, 238, 3, 643, 5 },
1072
  { 1124, 62, 238, 3, 643, 5 },
1073
  { 1129, 62, 238, 3, 643, 5 },
1074
  { 980, 2, 234, 2, 3619, 0 },
1075
  { 985, 2, 234, 2, 3619, 0 },
1076
  { 944, 2, 234, 2, 3619, 0 },
1077
  { 950, 2, 234, 2, 3619, 0 },
1078
  { 956, 2, 234, 2, 3619, 0 },
1079
  { 962, 2, 234, 2, 3619, 0 },
1080
  { 968, 2, 234, 2, 3619, 0 },
1081
  { 974, 2, 234, 2, 3619, 0 },
1082
};
1083
1084
extern const MCPhysReg X86RegUnitRoots[][2] = {
1085
  { X86::AH },
1086
  { X86::AL },
1087
  { X86::BH },
1088
  { X86::BL },
1089
  { X86::BPL },
1090
  { X86::BPH },
1091
  { X86::CH },
1092
  { X86::CL },
1093
  { X86::CS },
1094
  { X86::DF },
1095
  { X86::DH },
1096
  { X86::DIL },
1097
  { X86::DIH },
1098
  { X86::DL },
1099
  { X86::DS },
1100
  { X86::HAX },
1101
  { X86::HBP },
1102
  { X86::HBX },
1103
  { X86::HCX },
1104
  { X86::HDI },
1105
  { X86::HDX },
1106
  { X86::EFLAGS },
1107
  { X86::IP },
1108
  { X86::HIP },
1109
  { X86::EIZ },
1110
  { X86::ES },
1111
  { X86::SIL },
1112
  { X86::SIH },
1113
  { X86::HSI },
1114
  { X86::SPL },
1115
  { X86::SPH },
1116
  { X86::HSP },
1117
  { X86::FPSW },
1118
  { X86::FS },
1119
  { X86::GS },
1120
  { X86::RIZ },
1121
  { X86::SS },
1122
  { X86::SSP },
1123
  { X86::BND0 },
1124
  { X86::BND1 },
1125
  { X86::BND2 },
1126
  { X86::BND3 },
1127
  { X86::CR0 },
1128
  { X86::CR1 },
1129
  { X86::CR2 },
1130
  { X86::CR3 },
1131
  { X86::CR4 },
1132
  { X86::CR5 },
1133
  { X86::CR6 },
1134
  { X86::CR7 },
1135
  { X86::CR8 },
1136
  { X86::CR9 },
1137
  { X86::CR10 },
1138
  { X86::CR11 },
1139
  { X86::CR12 },
1140
  { X86::CR13 },
1141
  { X86::CR14 },
1142
  { X86::CR15 },
1143
  { X86::DR0 },
1144
  { X86::DR1 },
1145
  { X86::DR2 },
1146
  { X86::DR3 },
1147
  { X86::DR4 },
1148
  { X86::DR5 },
1149
  { X86::DR6 },
1150
  { X86::DR7 },
1151
  { X86::DR8 },
1152
  { X86::DR9 },
1153
  { X86::DR10 },
1154
  { X86::DR11 },
1155
  { X86::DR12 },
1156
  { X86::DR13 },
1157
  { X86::DR14 },
1158
  { X86::DR15 },
1159
  { X86::FP0 },
1160
  { X86::FP1 },
1161
  { X86::FP2 },
1162
  { X86::FP3 },
1163
  { X86::FP4 },
1164
  { X86::FP5 },
1165
  { X86::FP6 },
1166
  { X86::FP7 },
1167
  { X86::K0 },
1168
  { X86::K1 },
1169
  { X86::K2 },
1170
  { X86::K3 },
1171
  { X86::K4 },
1172
  { X86::K5 },
1173
  { X86::K6 },
1174
  { X86::K7 },
1175
  { X86::MM0 },
1176
  { X86::MM1 },
1177
  { X86::MM2 },
1178
  { X86::MM3 },
1179
  { X86::MM4 },
1180
  { X86::MM5 },
1181
  { X86::MM6 },
1182
  { X86::MM7 },
1183
  { X86::R8B },
1184
  { X86::R8BH },
1185
  { X86::R8WH },
1186
  { X86::R9B },
1187
  { X86::R9BH },
1188
  { X86::R9WH },
1189
  { X86::R10B },
1190
  { X86::R10BH },
1191
  { X86::R10WH },
1192
  { X86::R11B },
1193
  { X86::R11BH },
1194
  { X86::R11WH },
1195
  { X86::R12B },
1196
  { X86::R12BH },
1197
  { X86::R12WH },
1198
  { X86::R13B },
1199
  { X86::R13BH },
1200
  { X86::R13WH },
1201
  { X86::R14B },
1202
  { X86::R14BH },
1203
  { X86::R14WH },
1204
  { X86::R15B },
1205
  { X86::R15BH },
1206
  { X86::R15WH },
1207
  { X86::ST0 },
1208
  { X86::ST1 },
1209
  { X86::ST2 },
1210
  { X86::ST3 },
1211
  { X86::ST4 },
1212
  { X86::ST5 },
1213
  { X86::ST6 },
1214
  { X86::ST7 },
1215
  { X86::XMM0 },
1216
  { X86::XMM1 },
1217
  { X86::XMM2 },
1218
  { X86::XMM3 },
1219
  { X86::XMM4 },
1220
  { X86::XMM5 },
1221
  { X86::XMM6 },
1222
  { X86::XMM7 },
1223
  { X86::XMM8 },
1224
  { X86::XMM9 },
1225
  { X86::XMM10 },
1226
  { X86::XMM11 },
1227
  { X86::XMM12 },
1228
  { X86::XMM13 },
1229
  { X86::XMM14 },
1230
  { X86::XMM15 },
1231
  { X86::XMM16 },
1232
  { X86::XMM17 },
1233
  { X86::XMM18 },
1234
  { X86::XMM19 },
1235
  { X86::XMM20 },
1236
  { X86::XMM21 },
1237
  { X86::XMM22 },
1238
  { X86::XMM23 },
1239
  { X86::XMM24 },
1240
  { X86::XMM25 },
1241
  { X86::XMM26 },
1242
  { X86::XMM27 },
1243
  { X86::XMM28 },
1244
  { X86::XMM29 },
1245
  { X86::XMM30 },
1246
  { X86::XMM31 },
1247
};
1248
1249
namespace {     // Register classes...
1250
  // GR8 Register Class...
1251
  const MCPhysReg GR8[] = {
1252
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 
1253
  };
1254
1255
  // GR8 Bit set.
1256
  const uint8_t GR8Bits[] = {
1257
    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1258
  };
1259
1260
  // GRH8 Register Class...
1261
  const MCPhysReg GRH8[] = {
1262
    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 
1263
  };
1264
1265
  // GRH8 Bit set.
1266
  const uint8_t GRH8Bits[] = {
1267
    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1268
  };
1269
1270
  // GR8_NOREX Register Class...
1271
  const MCPhysReg GR8_NOREX[] = {
1272
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
1273
  };
1274
1275
  // GR8_NOREX Bit set.
1276
  const uint8_t GR8_NOREXBits[] = {
1277
    0x36, 0x8c, 0x08, 
1278
  };
1279
1280
  // GR8_ABCD_H Register Class...
1281
  const MCPhysReg GR8_ABCD_H[] = {
1282
    X86::AH, X86::CH, X86::DH, X86::BH, 
1283
  };
1284
1285
  // GR8_ABCD_H Bit set.
1286
  const uint8_t GR8_ABCD_HBits[] = {
1287
    0x12, 0x84, 
1288
  };
1289
1290
  // GR8_ABCD_L Register Class...
1291
  const MCPhysReg GR8_ABCD_L[] = {
1292
    X86::AL, X86::CL, X86::DL, X86::BL, 
1293
  };
1294
1295
  // GR8_ABCD_L Bit set.
1296
  const uint8_t GR8_ABCD_LBits[] = {
1297
    0x24, 0x08, 0x08, 
1298
  };
1299
1300
  // GRH16 Register Class...
1301
  const MCPhysReg GRH16[] = {
1302
    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 
1303
  };
1304
1305
  // GRH16 Bit set.
1306
  const uint8_t GRH16Bits[] = {
1307
    0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1308
  };
1309
1310
  // GR16 Register Class...
1311
  const MCPhysReg GR16[] = {
1312
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 
1313
  };
1314
1315
  // GR16 Bit set.
1316
  const uint8_t GR16Bits[] = {
1317
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1318
  };
1319
1320
  // GR16_NOREX Register Class...
1321
  const MCPhysReg GR16_NOREX[] = {
1322
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
1323
  };
1324
1325
  // GR16_NOREX Bit set.
1326
  const uint8_t GR16_NOREXBits[] = {
1327
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 
1328
  };
1329
1330
  // VK1 Register Class...
1331
  const MCPhysReg VK1[] = {
1332
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1333
  };
1334
1335
  // VK1 Bit set.
1336
  const uint8_t VK1Bits[] = {
1337
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1338
  };
1339
1340
  // VK16 Register Class...
1341
  const MCPhysReg VK16[] = {
1342
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1343
  };
1344
1345
  // VK16 Bit set.
1346
  const uint8_t VK16Bits[] = {
1347
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1348
  };
1349
1350
  // VK2 Register Class...
1351
  const MCPhysReg VK2[] = {
1352
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1353
  };
1354
1355
  // VK2 Bit set.
1356
  const uint8_t VK2Bits[] = {
1357
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1358
  };
1359
1360
  // VK4 Register Class...
1361
  const MCPhysReg VK4[] = {
1362
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1363
  };
1364
1365
  // VK4 Bit set.
1366
  const uint8_t VK4Bits[] = {
1367
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1368
  };
1369
1370
  // VK8 Register Class...
1371
  const MCPhysReg VK8[] = {
1372
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1373
  };
1374
1375
  // VK8 Bit set.
1376
  const uint8_t VK8Bits[] = {
1377
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1378
  };
1379
1380
  // VK16WM Register Class...
1381
  const MCPhysReg VK16WM[] = {
1382
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1383
  };
1384
1385
  // VK16WM Bit set.
1386
  const uint8_t VK16WMBits[] = {
1387
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1388
  };
1389
1390
  // VK1WM Register Class...
1391
  const MCPhysReg VK1WM[] = {
1392
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1393
  };
1394
1395
  // VK1WM Bit set.
1396
  const uint8_t VK1WMBits[] = {
1397
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1398
  };
1399
1400
  // VK2WM Register Class...
1401
  const MCPhysReg VK2WM[] = {
1402
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1403
  };
1404
1405
  // VK2WM Bit set.
1406
  const uint8_t VK2WMBits[] = {
1407
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1408
  };
1409
1410
  // VK4WM Register Class...
1411
  const MCPhysReg VK4WM[] = {
1412
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1413
  };
1414
1415
  // VK4WM Bit set.
1416
  const uint8_t VK4WMBits[] = {
1417
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1418
  };
1419
1420
  // VK8WM Register Class...
1421
  const MCPhysReg VK8WM[] = {
1422
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1423
  };
1424
1425
  // VK8WM Bit set.
1426
  const uint8_t VK8WMBits[] = {
1427
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1428
  };
1429
1430
  // SEGMENT_REG Register Class...
1431
  const MCPhysReg SEGMENT_REG[] = {
1432
    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 
1433
  };
1434
1435
  // SEGMENT_REG Bit set.
1436
  const uint8_t SEGMENT_REGBits[] = {
1437
    0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80, 
1438
  };
1439
1440
  // GR16_ABCD Register Class...
1441
  const MCPhysReg GR16_ABCD[] = {
1442
    X86::AX, X86::CX, X86::DX, X86::BX, 
1443
  };
1444
1445
  // GR16_ABCD Bit set.
1446
  const uint8_t GR16_ABCDBits[] = {
1447
    0x08, 0x22, 0x20, 
1448
  };
1449
1450
  // FPCCR Register Class...
1451
  const MCPhysReg FPCCR[] = {
1452
    X86::FPSW, 
1453
  };
1454
1455
  // FPCCR Bit set.
1456
  const uint8_t FPCCRBits[] = {
1457
    0x00, 0x00, 0x00, 0x00, 0x04, 
1458
  };
1459
1460
  // FR32X Register Class...
1461
  const MCPhysReg FR32X[] = {
1462
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1463
  };
1464
1465
  // FR32X Bit set.
1466
  const uint8_t FR32XBits[] = {
1467
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1468
  };
1469
1470
  // LOW32_ADDR_ACCESS_RBP Register Class...
1471
  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1472
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 
1473
  };
1474
1475
  // LOW32_ADDR_ACCESS_RBP Bit set.
1476
  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1477
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1478
  };
1479
1480
  // LOW32_ADDR_ACCESS Register Class...
1481
  const MCPhysReg LOW32_ADDR_ACCESS[] = {
1482
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 
1483
  };
1484
1485
  // LOW32_ADDR_ACCESS Bit set.
1486
  const uint8_t LOW32_ADDR_ACCESSBits[] = {
1487
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1488
  };
1489
1490
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1491
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1492
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 
1493
  };
1494
1495
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1496
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1497
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1498
  };
1499
1500
  // DEBUG_REG Register Class...
1501
  const MCPhysReg DEBUG_REG[] = {
1502
    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 
1503
  };
1504
1505
  // DEBUG_REG Bit set.
1506
  const uint8_t DEBUG_REGBits[] = {
1507
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1508
  };
1509
1510
  // FR32 Register Class...
1511
  const MCPhysReg FR32[] = {
1512
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1513
  };
1514
1515
  // FR32 Bit set.
1516
  const uint8_t FR32Bits[] = {
1517
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1518
  };
1519
1520
  // GR32 Register Class...
1521
  const MCPhysReg GR32[] = {
1522
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1523
  };
1524
1525
  // GR32 Bit set.
1526
  const uint8_t GR32Bits[] = {
1527
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1528
  };
1529
1530
  // GR32_NOSP Register Class...
1531
  const MCPhysReg GR32_NOSP[] = {
1532
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1533
  };
1534
1535
  // GR32_NOSP Bit set.
1536
  const uint8_t GR32_NOSPBits[] = {
1537
    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1538
  };
1539
1540
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1541
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1542
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 
1543
  };
1544
1545
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1546
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1547
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 
1548
  };
1549
1550
  // GR32_NOREX Register Class...
1551
  const MCPhysReg GR32_NOREX[] = {
1552
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
1553
  };
1554
1555
  // GR32_NOREX Bit set.
1556
  const uint8_t GR32_NOREXBits[] = {
1557
    0x00, 0x00, 0xc0, 0x0f, 0x03, 
1558
  };
1559
1560
  // VK32 Register Class...
1561
  const MCPhysReg VK32[] = {
1562
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1563
  };
1564
1565
  // VK32 Bit set.
1566
  const uint8_t VK32Bits[] = {
1567
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1568
  };
1569
1570
  // GR32_NOREX_NOSP Register Class...
1571
  const MCPhysReg GR32_NOREX_NOSP[] = {
1572
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 
1573
  };
1574
1575
  // GR32_NOREX_NOSP Bit set.
1576
  const uint8_t GR32_NOREX_NOSPBits[] = {
1577
    0x00, 0x00, 0xc0, 0x0f, 0x01, 
1578
  };
1579
1580
  // RFP32 Register Class...
1581
  const MCPhysReg RFP32[] = {
1582
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1583
  };
1584
1585
  // RFP32 Bit set.
1586
  const uint8_t RFP32Bits[] = {
1587
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1588
  };
1589
1590
  // VK32WM Register Class...
1591
  const MCPhysReg VK32WM[] = {
1592
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1593
  };
1594
1595
  // VK32WM Bit set.
1596
  const uint8_t VK32WMBits[] = {
1597
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1598
  };
1599
1600
  // GR32_ABCD Register Class...
1601
  const MCPhysReg GR32_ABCD[] = {
1602
    X86::EAX, X86::ECX, X86::EDX, X86::EBX, 
1603
  };
1604
1605
  // GR32_ABCD Bit set.
1606
  const uint8_t GR32_ABCDBits[] = {
1607
    0x00, 0x00, 0x40, 0x0b, 
1608
  };
1609
1610
  // GR32_TC Register Class...
1611
  const MCPhysReg GR32_TC[] = {
1612
    X86::EAX, X86::ECX, X86::EDX, 
1613
  };
1614
1615
  // GR32_TC Bit set.
1616
  const uint8_t GR32_TCBits[] = {
1617
    0x00, 0x00, 0x40, 0x0a, 
1618
  };
1619
1620
  // GR32_AD Register Class...
1621
  const MCPhysReg GR32_AD[] = {
1622
    X86::EAX, X86::EDX, 
1623
  };
1624
1625
  // GR32_AD Bit set.
1626
  const uint8_t GR32_ADBits[] = {
1627
    0x00, 0x00, 0x40, 0x08, 
1628
  };
1629
1630
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1631
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1632
    X86::RIP, X86::RBP, 
1633
  };
1634
1635
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1636
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1637
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
1638
  };
1639
1640
  // CCR Register Class...
1641
  const MCPhysReg CCR[] = {
1642
    X86::EFLAGS, 
1643
  };
1644
1645
  // CCR Bit set.
1646
  const uint8_t CCRBits[] = {
1647
    0x00, 0x00, 0x00, 0x10, 
1648
  };
1649
1650
  // DFCCR Register Class...
1651
  const MCPhysReg DFCCR[] = {
1652
    X86::DF, 
1653
  };
1654
1655
  // DFCCR Bit set.
1656
  const uint8_t DFCCRBits[] = {
1657
    0x00, 0x40, 
1658
  };
1659
1660
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1661
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1662
    X86::RBP, 
1663
  };
1664
1665
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1666
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1667
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1668
  };
1669
1670
  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1671
  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1672
    X86::RIP, 
1673
  };
1674
1675
  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1676
  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1677
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
1678
  };
1679
1680
  // RFP64 Register Class...
1681
  const MCPhysReg RFP64[] = {
1682
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1683
  };
1684
1685
  // RFP64 Bit set.
1686
  const uint8_t RFP64Bits[] = {
1687
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1688
  };
1689
1690
  // FR64X Register Class...
1691
  const MCPhysReg FR64X[] = {
1692
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1693
  };
1694
1695
  // FR64X Bit set.
1696
  const uint8_t FR64XBits[] = {
1697
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1698
  };
1699
1700
  // GR64 Register Class...
1701
  const MCPhysReg GR64[] = {
1702
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 
1703
  };
1704
1705
  // GR64 Bit set.
1706
  const uint8_t GR64Bits[] = {
1707
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1708
  };
1709
1710
  // CONTROL_REG Register Class...
1711
  const MCPhysReg CONTROL_REG[] = {
1712
    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 
1713
  };
1714
1715
  // CONTROL_REG Bit set.
1716
  const uint8_t CONTROL_REGBits[] = {
1717
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1718
  };
1719
1720
  // FR64 Register Class...
1721
  const MCPhysReg FR64[] = {
1722
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1723
  };
1724
1725
  // FR64 Bit set.
1726
  const uint8_t FR64Bits[] = {
1727
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1728
  };
1729
1730
  // GR64_with_sub_8bit Register Class...
1731
  const MCPhysReg GR64_with_sub_8bit[] = {
1732
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 
1733
  };
1734
1735
  // GR64_with_sub_8bit Bit set.
1736
  const uint8_t GR64_with_sub_8bitBits[] = {
1737
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1738
  };
1739
1740
  // GR64_NOSP Register Class...
1741
  const MCPhysReg GR64_NOSP[] = {
1742
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 
1743
  };
1744
1745
  // GR64_NOSP Bit set.
1746
  const uint8_t GR64_NOSPBits[] = {
1747
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1748
  };
1749
1750
  // GR64_NOREX Register Class...
1751
  const MCPhysReg GR64_NOREX[] = {
1752
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 
1753
  };
1754
1755
  // GR64_NOREX Bit set.
1756
  const uint8_t GR64_NOREXBits[] = {
1757
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 
1758
  };
1759
1760
  // GR64_TC Register Class...
1761
  const MCPhysReg GR64_TC[] = {
1762
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, 
1763
  };
1764
1765
  // GR64_TC Bit set.
1766
  const uint8_t GR64_TCBits[] = {
1767
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1768
  };
1769
1770
  // GR64_NOSP_and_GR64_TC Register Class...
1771
  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
1772
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 
1773
  };
1774
1775
  // GR64_NOSP_and_GR64_TC Bit set.
1776
  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
1777
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1778
  };
1779
1780
  // GR64_TCW64 Register Class...
1781
  const MCPhysReg GR64_TCW64[] = {
1782
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, 
1783
  };
1784
1785
  // GR64_TCW64 Bit set.
1786
  const uint8_t GR64_TCW64Bits[] = {
1787
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1788
  };
1789
1790
  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1791
  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1792
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 
1793
  };
1794
1795
  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1796
  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1797
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 
1798
  };
1799
1800
  // VK64 Register Class...
1801
  const MCPhysReg VK64[] = {
1802
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1803
  };
1804
1805
  // VK64 Bit set.
1806
  const uint8_t VK64Bits[] = {
1807
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1808
  };
1809
1810
  // VR64 Register Class...
1811
  const MCPhysReg VR64[] = {
1812
    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
1813
  };
1814
1815
  // VR64 Bit set.
1816
  const uint8_t VR64Bits[] = {
1817
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1818
  };
1819
1820
  // GR64_NOREX_NOSP Register Class...
1821
  const MCPhysReg GR64_NOREX_NOSP[] = {
1822
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 
1823
  };
1824
1825
  // GR64_NOREX_NOSP Bit set.
1826
  const uint8_t GR64_NOREX_NOSPBits[] = {
1827
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 
1828
  };
1829
1830
  // GR64_NOSP_and_GR64_TCW64 Register Class...
1831
  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
1832
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 
1833
  };
1834
1835
  // GR64_NOSP_and_GR64_TCW64 Bit set.
1836
  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
1837
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
1838
  };
1839
1840
  // GR64_TC_and_GR64_TCW64 Register Class...
1841
  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1842
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, 
1843
  };
1844
1845
  // GR64_TC_and_GR64_TCW64 Bit set.
1846
  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1847
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1848
  };
1849
1850
  // VK64WM Register Class...
1851
  const MCPhysReg VK64WM[] = {
1852
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1853
  };
1854
1855
  // VK64WM Bit set.
1856
  const uint8_t VK64WMBits[] = {
1857
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1858
  };
1859
1860
  // GR64_NOREX_and_GR64_TC Register Class...
1861
  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
1862
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RIP, 
1863
  };
1864
1865
  // GR64_NOREX_and_GR64_TC Bit set.
1866
  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
1867
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 
1868
  };
1869
1870
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
1871
  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
1872
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 
1873
  };
1874
1875
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
1876
  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
1877
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 
1878
  };
1879
1880
  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
1881
  const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
1882
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 
1883
  };
1884
1885
  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
1886
  const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
1887
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 
1888
  };
1889
1890
  // GR64_ABCD Register Class...
1891
  const MCPhysReg GR64_ABCD[] = {
1892
    X86::RAX, X86::RCX, X86::RDX, X86::RBX, 
1893
  };
1894
1895
  // GR64_ABCD Bit set.
1896
  const uint8_t GR64_ABCDBits[] = {
1897
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, 
1898
  };
1899
1900
  // GR64_NOREX_and_GR64_TCW64 Register Class...
1901
  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
1902
    X86::RAX, X86::RCX, X86::RDX, X86::RIP, 
1903
  };
1904
1905
  // GR64_NOREX_and_GR64_TCW64 Bit set.
1906
  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
1907
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 
1908
  };
1909
1910
  // GR64_with_sub_32bit_in_GR32_TC Register Class...
1911
  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
1912
    X86::RAX, X86::RCX, X86::RDX, 
1913
  };
1914
1915
  // GR64_with_sub_32bit_in_GR32_TC Bit set.
1916
  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
1917
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 
1918
  };
1919
1920
  // GR64_AD Register Class...
1921
  const MCPhysReg GR64_AD[] = {
1922
    X86::RAX, X86::RDX, 
1923
  };
1924
1925
  // GR64_AD Bit set.
1926
  const uint8_t GR64_ADBits[] = {
1927
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10, 
1928
  };
1929
1930
  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
1931
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
1932
    X86::RBP, X86::RIP, 
1933
  };
1934
1935
  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
1936
  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
1937
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
1938
  };
1939
1940
  // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Register Class...
1941
  const MCPhysReg GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP[] = {
1942
    X86::RBP, 
1943
  };
1944
1945
  // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Bit set.
1946
  const uint8_t GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits[] = {
1947
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1948
  };
1949
1950
  // GR64_and_LOW32_ADDR_ACCESS Register Class...
1951
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
1952
    X86::RIP, 
1953
  };
1954
1955
  // GR64_and_LOW32_ADDR_ACCESS Bit set.
1956
  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
1957
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
1958
  };
1959
1960
  // RST Register Class...
1961
  const MCPhysReg RST[] = {
1962
    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
1963
  };
1964
1965
  // RST Bit set.
1966
  const uint8_t RSTBits[] = {
1967
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1968
  };
1969
1970
  // RFP80 Register Class...
1971
  const MCPhysReg RFP80[] = {
1972
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1973
  };
1974
1975
  // RFP80 Bit set.
1976
  const uint8_t RFP80Bits[] = {
1977
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1978
  };
1979
1980
  // VR128X Register Class...
1981
  const MCPhysReg VR128X[] = {
1982
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1983
  };
1984
1985
  // VR128X Bit set.
1986
  const uint8_t VR128XBits[] = {
1987
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1988
  };
1989
1990
  // VR128 Register Class...
1991
  const MCPhysReg VR128[] = {
1992
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1993
  };
1994
1995
  // VR128 Bit set.
1996
  const uint8_t VR128Bits[] = {
1997
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1998
  };
1999
2000
  // VR128H Register Class...
2001
  const MCPhysReg VR128H[] = {
2002
    X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2003
  };
2004
2005
  // VR128H Bit set.
2006
  const uint8_t VR128HBits[] = {
2007
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2008
  };
2009
2010
  // VR128L Register Class...
2011
  const MCPhysReg VR128L[] = {
2012
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
2013
  };
2014
2015
  // VR128L Bit set.
2016
  const uint8_t VR128LBits[] = {
2017
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2018
  };
2019
2020
  // BNDR Register Class...
2021
  const MCPhysReg BNDR[] = {
2022
    X86::BND0, X86::BND1, X86::BND2, X86::BND3, 
2023
  };
2024
2025
  // BNDR Bit set.
2026
  const uint8_t BNDRBits[] = {
2027
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
2028
  };
2029
2030
  // VR256X Register Class...
2031
  const MCPhysReg VR256X[] = {
2032
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 
2033
  };
2034
2035
  // VR256X Bit set.
2036
  const uint8_t VR256XBits[] = {
2037
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2038
  };
2039
2040
  // VR256 Register Class...
2041
  const MCPhysReg VR256[] = {
2042
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2043
  };
2044
2045
  // VR256 Bit set.
2046
  const uint8_t VR256Bits[] = {
2047
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2048
  };
2049
2050
  // VR256H Register Class...
2051
  const MCPhysReg VR256H[] = {
2052
    X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2053
  };
2054
2055
  // VR256H Bit set.
2056
  const uint8_t VR256HBits[] = {
2057
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2058
  };
2059
2060
  // VR256L Register Class...
2061
  const MCPhysReg VR256L[] = {
2062
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 
2063
  };
2064
2065
  // VR256L Bit set.
2066
  const uint8_t VR256LBits[] = {
2067
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2068
  };
2069
2070
  // VR512 Register Class...
2071
  const MCPhysReg VR512[] = {
2072
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 
2073
  };
2074
2075
  // VR512 Bit set.
2076
  const uint8_t VR512Bits[] = {
2077
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
2078
  };
2079
2080
  // VR512_with_sub_xmm_in_FR32 Register Class...
2081
  const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
2082
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2083
  };
2084
2085
  // VR512_with_sub_xmm_in_FR32 Bit set.
2086
  const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
2087
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
2088
  };
2089
2090
  // VR512_with_sub_xmm_in_VR128H Register Class...
2091
  const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = {
2092
    X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2093
  };
2094
2095
  // VR512_with_sub_xmm_in_VR128H Bit set.
2096
  const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = {
2097
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2098
  };
2099
2100
  // VR512_with_sub_xmm_in_VR128L Register Class...
2101
  const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = {
2102
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, 
2103
  };
2104
2105
  // VR512_with_sub_xmm_in_VR128L Bit set.
2106
  const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = {
2107
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
2108
  };
2109
2110
} // end anonymous namespace
2111
2112
extern const char X86RegClassStrings[] = {
2113
  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
2114
  /* 6 */ 'V', 'K', '1', 0,
2115
  /* 10 */ 'V', 'R', '5', '1', '2', 0,
2116
  /* 16 */ 'V', 'K', '3', '2', 0,
2117
  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
2118
  /* 27 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'F', 'R', '3', '2', 0,
2119
  /* 54 */ 'G', 'R', '3', '2', 0,
2120
  /* 59 */ 'V', 'K', '2', 0,
2121
  /* 63 */ 'V', 'K', '6', '4', 0,
2122
  /* 68 */ 'R', 'F', 'P', '6', '4', 0,
2123
  /* 74 */ 'F', 'R', '6', '4', 0,
2124
  /* 79 */ 'G', 'R', '6', '4', 0,
2125
  /* 84 */ 'V', 'R', '6', '4', 0,
2126
  /* 89 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2127
  /* 112 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2128
  /* 149 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2129
  /* 175 */ 'V', 'K', '4', 0,
2130
  /* 179 */ 'G', 'R', 'H', '1', '6', 0,
2131
  /* 185 */ 'V', 'K', '1', '6', 0,
2132
  /* 190 */ 'G', 'R', '1', '6', 0,
2133
  /* 195 */ 'V', 'R', '2', '5', '6', 0,
2134
  /* 201 */ 'V', 'R', '1', '2', '8', 0,
2135
  /* 207 */ 'G', 'R', 'H', '8', 0,
2136
  /* 212 */ 'V', 'K', '8', 0,
2137
  /* 216 */ 'G', 'R', '8', 0,
2138
  /* 220 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2139
  /* 251 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2140
  /* 273 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2141
  /* 301 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2142
  /* 324 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
2143
  /* 332 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
2144
  /* 340 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
2145
  /* 350 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
2146
  /* 360 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
2147
  /* 370 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
2148
  /* 380 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
2149
  /* 392 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
2150
  /* 404 */ 'V', 'R', '2', '5', '6', 'H', 0,
2151
  /* 411 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'H', 0,
2152
  /* 440 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
2153
  /* 451 */ 'V', 'R', '2', '5', '6', 'L', 0,
2154
  /* 458 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'L', 0,
2155
  /* 487 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
2156
  /* 498 */ 'V', 'K', '1', 'W', 'M', 0,
2157
  /* 504 */ 'V', 'K', '3', '2', 'W', 'M', 0,
2158
  /* 511 */ 'V', 'K', '2', 'W', 'M', 0,
2159
  /* 517 */ 'V', 'K', '6', '4', 'W', 'M', 0,
2160
  /* 524 */ 'V', 'K', '4', 'W', 'M', 0,
2161
  /* 530 */ 'V', 'K', '1', '6', 'W', 'M', 0,
2162
  /* 537 */ 'V', 'K', '8', 'W', 'M', 0,
2163
  /* 543 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2164
  /* 574 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2165
  /* 616 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
2166
  /* 626 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
2167
  /* 636 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2168
  /* 652 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2169
  /* 668 */ 'D', 'F', 'C', 'C', 'R', 0,
2170
  /* 674 */ 'F', 'P', 'C', 'C', 'R', 0,
2171
  /* 680 */ 'B', 'N', 'D', 'R', 0,
2172
  /* 685 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
2173
  /* 712 */ 'R', 'S', 'T', 0,
2174
  /* 716 */ 'F', 'R', '3', '2', 'X', 0,
2175
  /* 722 */ 'F', 'R', '6', '4', 'X', 0,
2176
  /* 728 */ 'V', 'R', '2', '5', '6', 'X', 0,
2177
  /* 735 */ 'V', 'R', '1', '2', '8', 'X', 0,
2178
  /* 742 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
2179
  /* 753 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
2180
  /* 764 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2181
  /* 798 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2182
  /* 849 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
2183
  /* 859 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2184
  /* 896 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2185
  /* 929 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2186
  /* 980 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2187
  /* 999 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2188
};
2189
2190
extern const MCRegisterClass X86MCRegisterClasses[] = {
2191
  { GR8, GR8Bits, 216, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, 1, true },
2192
  { GRH8, GRH8Bits, 207, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, 1, false },
2193
  { GR8_NOREX, GR8_NOREXBits, 849, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, 1, true },
2194
  { GR8_ABCD_H, GR8_ABCD_HBits, 440, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, 1, true },
2195
  { GR8_ABCD_L, GR8_ABCD_LBits, 487, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, 1, true },
2196
  { GRH16, GRH16Bits, 179, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 2, 1, false },
2197
  { GR16, GR16Bits, 190, 16, sizeof(GR16Bits), X86::GR16RegClassID, 2, 1, true },
2198
  { GR16_NOREX, GR16_NOREXBits, 787, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 2, 1, true },
2199
  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 2, 1, true },
2200
  { VK16, VK16Bits, 185, 8, sizeof(VK16Bits), X86::VK16RegClassID, 2, 1, true },
2201
  { VK2, VK2Bits, 59, 8, sizeof(VK2Bits), X86::VK2RegClassID, 2, 1, true },
2202
  { VK4, VK4Bits, 175, 8, sizeof(VK4Bits), X86::VK4RegClassID, 2, 1, true },
2203
  { VK8, VK8Bits, 212, 8, sizeof(VK8Bits), X86::VK8RegClassID, 2, 1, true },
2204
  { VK16WM, VK16WMBits, 530, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 2, 1, true },
2205
  { VK1WM, VK1WMBits, 498, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 2, 1, true },
2206
  { VK2WM, VK2WMBits, 511, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 2, 1, true },
2207
  { VK4WM, VK4WMBits, 524, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 2, 1, true },
2208
  { VK8WM, VK8WMBits, 537, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 2, 1, true },
2209
  { SEGMENT_REG, SEGMENT_REGBits, 392, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 2, 1, true },
2210
  { GR16_ABCD, GR16_ABCDBits, 360, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 2, 1, true },
2211
  { FPCCR, FPCCRBits, 674, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 2, -1, false },
2212
  { FR32X, FR32XBits, 716, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 4, 1, true },
2213
  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 552, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 4, 1, true },
2214
  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 694, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 4, 1, true },
2215
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 999, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 4, 1, true },
2216
  { DEBUG_REG, DEBUG_REGBits, 370, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 4, 1, true },
2217
  { FR32, FR32Bits, 49, 16, sizeof(FR32Bits), X86::FR32RegClassID, 4, 1, true },
2218
  { GR32, GR32Bits, 54, 16, sizeof(GR32Bits), X86::GR32RegClassID, 4, 1, true },
2219
  { GR32_NOSP, GR32_NOSPBits, 616, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 4, 1, true },
2220
  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 798, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 4, 1, true },
2221
  { GR32_NOREX, GR32_NOREXBits, 742, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 4, 1, true },
2222
  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 4, 1, true },
2223
  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 636, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 4, 1, true },
2224
  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 4, 1, true },
2225
  { VK32WM, VK32WMBits, 504, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 4, 1, true },
2226
  { GR32_ABCD, GR32_ABCDBits, 340, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 4, 1, true },
2227
  { GR32_TC, GR32_TCBits, 243, 3, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 4, 1, true },
2228
  { GR32_AD, GR32_ADBits, 324, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 4, 1, true },
2229
  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 859, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 4, 1, true },
2230
  { CCR, CCRBits, 670, 1, sizeof(CCRBits), X86::CCRRegClassID, 4, -1, false },
2231
  { DFCCR, DFCCRBits, 668, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 4, -1, false },
2232
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 929, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 4, 1, true },
2233
  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 896, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 4, 1, true },
2234
  { RFP64, RFP64Bits, 68, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 8, 1, true },
2235
  { FR64X, FR64XBits, 722, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 8, 1, true },
2236
  { GR64, GR64Bits, 79, 17, sizeof(GR64Bits), X86::GR64RegClassID, 8, 1, true },
2237
  { CONTROL_REG, CONTROL_REGBits, 380, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 8, 1, true },
2238
  { FR64, FR64Bits, 74, 16, sizeof(FR64Bits), X86::FR64RegClassID, 8, 1, true },
2239
  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 980, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 8, 1, true },
2240
  { GR64_NOSP, GR64_NOSPBits, 626, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 8, 1, true },
2241
  { GR64_NOREX, GR64_NOREXBits, 753, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 8, 1, true },
2242
  { GR64_TC, GR64_TCBits, 265, 9, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 8, 1, true },
2243
  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 251, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 8, 1, true },
2244
  { GR64_TCW64, GR64_TCW64Bits, 101, 8, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 8, 1, true },
2245
  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 764, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 8, 1, true },
2246
  { VK64, VK64Bits, 63, 8, sizeof(VK64Bits), X86::VK64RegClassID, 8, 1, true },
2247
  { VR64, VR64Bits, 84, 8, sizeof(VR64Bits), X86::VR64RegClassID, 8, 1, true },
2248
  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 652, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 8, 1, true },
2249
  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 124, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 8, 1, true },
2250
  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 89, 7, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 8, 1, true },
2251
  { VK64WM, VK64WMBits, 517, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 8, 1, true },
2252
  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 301, 6, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 8, 1, true },
2253
  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 112, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 8, 1, true },
2254
  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 273, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 8, 1, true },
2255
  { GR64_ABCD, GR64_ABCDBits, 350, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 8, 1, true },
2256
  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 149, 4, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 8, 1, true },
2257
  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 220, 3, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 8, 1, true },
2258
  { GR64_AD, GR64_ADBits, 332, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 8, 1, true },
2259
  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 543, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 8, 1, true },
2260
  { GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP, GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits, 574, 1, sizeof(GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID, 8, 1, true },
2261
  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 685, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 8, 1, true },
2262
  { RST, RSTBits, 712, 8, sizeof(RSTBits), X86::RSTRegClassID, 10, 1, false },
2263
  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 10, 1, true },
2264
  { VR128X, VR128XBits, 735, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 16, 1, true },
2265
  { VR128, VR128Bits, 201, 16, sizeof(VR128Bits), X86::VR128RegClassID, 16, 1, true },
2266
  { VR128H, VR128HBits, 433, 8, sizeof(VR128HBits), X86::VR128HRegClassID, 16, 1, true },
2267
  { VR128L, VR128LBits, 480, 8, sizeof(VR128LBits), X86::VR128LRegClassID, 16, 1, true },
2268
  { BNDR, BNDRBits, 680, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 16, 1, true },
2269
  { VR256X, VR256XBits, 728, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 32, 1, true },
2270
  { VR256, VR256Bits, 195, 16, sizeof(VR256Bits), X86::VR256RegClassID, 32, 1, true },
2271
  { VR256H, VR256HBits, 404, 8, sizeof(VR256HBits), X86::VR256HRegClassID, 32, 1, true },
2272
  { VR256L, VR256LBits, 451, 8, sizeof(VR256LBits), X86::VR256LRegClassID, 32, 1, true },
2273
  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 64, 1, true },
2274
  { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, 27, 16, sizeof(VR512_with_sub_xmm_in_FR32Bits), X86::VR512_with_sub_xmm_in_FR32RegClassID, 64, 1, true },
2275
  { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, 411, 8, sizeof(VR512_with_sub_xmm_in_VR128HBits), X86::VR512_with_sub_xmm_in_VR128HRegClassID, 64, 1, true },
2276
  { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, 458, 8, sizeof(VR512_with_sub_xmm_in_VR128LBits), X86::VR512_with_sub_xmm_in_VR128LRegClassID, 64, 1, true },
2277
};
2278
2279
// X86 Dwarf<->LLVM register mappings.
2280
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2281
  { 0U, X86::RAX },
2282
  { 1U, X86::RDX },
2283
  { 2U, X86::RCX },
2284
  { 3U, X86::RBX },
2285
  { 4U, X86::RSI },
2286
  { 5U, X86::RDI },
2287
  { 6U, X86::RBP },
2288
  { 7U, X86::RSP },
2289
  { 8U, X86::R8 },
2290
  { 9U, X86::R9 },
2291
  { 10U, X86::R10 },
2292
  { 11U, X86::R11 },
2293
  { 12U, X86::R12 },
2294
  { 13U, X86::R13 },
2295
  { 14U, X86::R14 },
2296
  { 15U, X86::R15 },
2297
  { 16U, X86::RIP },
2298
  { 17U, X86::XMM0 },
2299
  { 18U, X86::XMM1 },
2300
  { 19U, X86::XMM2 },
2301
  { 20U, X86::XMM3 },
2302
  { 21U, X86::XMM4 },
2303
  { 22U, X86::XMM5 },
2304
  { 23U, X86::XMM6 },
2305
  { 24U, X86::XMM7 },
2306
  { 25U, X86::XMM8 },
2307
  { 26U, X86::XMM9 },
2308
  { 27U, X86::XMM10 },
2309
  { 28U, X86::XMM11 },
2310
  { 29U, X86::XMM12 },
2311
  { 30U, X86::XMM13 },
2312
  { 31U, X86::XMM14 },
2313
  { 32U, X86::XMM15 },
2314
  { 33U, X86::ST0 },
2315
  { 34U, X86::ST1 },
2316
  { 35U, X86::ST2 },
2317
  { 36U, X86::ST3 },
2318
  { 37U, X86::ST4 },
2319
  { 38U, X86::ST5 },
2320
  { 39U, X86::ST6 },
2321
  { 40U, X86::ST7 },
2322
  { 41U, X86::MM0 },
2323
  { 42U, X86::MM1 },
2324
  { 43U, X86::MM2 },
2325
  { 44U, X86::MM3 },
2326
  { 45U, X86::MM4 },
2327
  { 46U, X86::MM5 },
2328
  { 47U, X86::MM6 },
2329
  { 48U, X86::MM7 },
2330
  { 67U, X86::XMM16 },
2331
  { 68U, X86::XMM17 },
2332
  { 69U, X86::XMM18 },
2333
  { 70U, X86::XMM19 },
2334
  { 71U, X86::XMM20 },
2335
  { 72U, X86::XMM21 },
2336
  { 73U, X86::XMM22 },
2337
  { 74U, X86::XMM23 },
2338
  { 75U, X86::XMM24 },
2339
  { 76U, X86::XMM25 },
2340
  { 77U, X86::XMM26 },
2341
  { 78U, X86::XMM27 },
2342
  { 79U, X86::XMM28 },
2343
  { 80U, X86::XMM29 },
2344
  { 81U, X86::XMM30 },
2345
  { 82U, X86::XMM31 },
2346
  { 118U, X86::K0 },
2347
  { 119U, X86::K1 },
2348
  { 120U, X86::K2 },
2349
  { 121U, X86::K3 },
2350
  { 122U, X86::K4 },
2351
  { 123U, X86::K5 },
2352
  { 124U, X86::K6 },
2353
  { 125U, X86::K7 },
2354
};
2355
extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L);
2356
2357
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2358
  { 0U, X86::EAX },
2359
  { 1U, X86::ECX },
2360
  { 2U, X86::EDX },
2361
  { 3U, X86::EBX },
2362
  { 4U, X86::EBP },
2363
  { 5U, X86::ESP },
2364
  { 6U, X86::ESI },
2365
  { 7U, X86::EDI },
2366
  { 8U, X86::EIP },
2367
  { 12U, X86::ST0 },
2368
  { 13U, X86::ST1 },
2369
  { 14U, X86::ST2 },
2370
  { 15U, X86::ST3 },
2371
  { 16U, X86::ST4 },
2372
  { 17U, X86::ST5 },
2373
  { 18U, X86::ST6 },
2374
  { 19U, X86::ST7 },
2375
  { 21U, X86::XMM0 },
2376
  { 22U, X86::XMM1 },
2377
  { 23U, X86::XMM2 },
2378
  { 24U, X86::XMM3 },
2379
  { 25U, X86::XMM4 },
2380
  { 26U, X86::XMM5 },
2381
  { 27U, X86::XMM6 },
2382
  { 28U, X86::XMM7 },
2383
  { 29U, X86::MM0 },
2384
  { 30U, X86::MM1 },
2385
  { 31U, X86::MM2 },
2386
  { 32U, X86::MM3 },
2387
  { 33U, X86::MM4 },
2388
  { 34U, X86::MM5 },
2389
  { 35U, X86::MM6 },
2390
  { 36U, X86::MM7 },
2391
  { 93U, X86::K0 },
2392
  { 94U, X86::K1 },
2393
  { 95U, X86::K2 },
2394
  { 96U, X86::K3 },
2395
  { 97U, X86::K4 },
2396
  { 98U, X86::K5 },
2397
  { 99U, X86::K6 },
2398
  { 100U, X86::K7 },
2399
};
2400
extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L);
2401
2402
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2403
  { 0U, X86::EAX },
2404
  { 1U, X86::ECX },
2405
  { 2U, X86::EDX },
2406
  { 3U, X86::EBX },
2407
  { 4U, X86::ESP },
2408
  { 5U, X86::EBP },
2409
  { 6U, X86::ESI },
2410
  { 7U, X86::EDI },
2411
  { 8U, X86::EIP },
2412
  { 11U, X86::ST0 },
2413
  { 12U, X86::ST1 },
2414
  { 13U, X86::ST2 },
2415
  { 14U, X86::ST3 },
2416
  { 15U, X86::ST4 },
2417
  { 16U, X86::ST5 },
2418
  { 17U, X86::ST6 },
2419
  { 18U, X86::ST7 },
2420
  { 21U, X86::XMM0 },
2421
  { 22U, X86::XMM1 },
2422
  { 23U, X86::XMM2 },
2423
  { 24U, X86::XMM3 },
2424
  { 25U, X86::XMM4 },
2425
  { 26U, X86::XMM5 },
2426
  { 27U, X86::XMM6 },
2427
  { 28U, X86::XMM7 },
2428
  { 29U, X86::MM0 },
2429
  { 30U, X86::MM1 },
2430
  { 31U, X86::MM2 },
2431
  { 32U, X86::MM3 },
2432
  { 33U, X86::MM4 },
2433
  { 34U, X86::MM5 },
2434
  { 35U, X86::MM6 },
2435
  { 36U, X86::MM7 },
2436
  { 93U, X86::K0 },
2437
  { 94U, X86::K1 },
2438
  { 95U, X86::K2 },
2439
  { 96U, X86::K3 },
2440
  { 97U, X86::K4 },
2441
  { 98U, X86::K5 },
2442
  { 99U, X86::K6 },
2443
  { 100U, X86::K7 },
2444
};
2445
extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L);
2446
2447
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2448
  { 0U, X86::RAX },
2449
  { 1U, X86::RDX },
2450
  { 2U, X86::RCX },
2451
  { 3U, X86::RBX },
2452
  { 4U, X86::RSI },
2453
  { 5U, X86::RDI },
2454
  { 6U, X86::RBP },
2455
  { 7U, X86::RSP },
2456
  { 8U, X86::R8 },
2457
  { 9U, X86::R9 },
2458
  { 10U, X86::R10 },
2459
  { 11U, X86::R11 },
2460
  { 12U, X86::R12 },
2461
  { 13U, X86::R13 },
2462
  { 14U, X86::R14 },
2463
  { 15U, X86::R15 },
2464
  { 16U, X86::RIP },
2465
  { 17U, X86::XMM0 },
2466
  { 18U, X86::XMM1 },
2467
  { 19U, X86::XMM2 },
2468
  { 20U, X86::XMM3 },
2469
  { 21U, X86::XMM4 },
2470
  { 22U, X86::XMM5 },
2471
  { 23U, X86::XMM6 },
2472
  { 24U, X86::XMM7 },
2473
  { 25U, X86::XMM8 },
2474
  { 26U, X86::XMM9 },
2475
  { 27U, X86::XMM10 },
2476
  { 28U, X86::XMM11 },
2477
  { 29U, X86::XMM12 },
2478
  { 30U, X86::XMM13 },
2479
  { 31U, X86::XMM14 },
2480
  { 32U, X86::XMM15 },
2481
  { 33U, X86::ST0 },
2482
  { 34U, X86::ST1 },
2483
  { 35U, X86::ST2 },
2484
  { 36U, X86::ST3 },
2485
  { 37U, X86::ST4 },
2486
  { 38U, X86::ST5 },
2487
  { 39U, X86::ST6 },
2488
  { 40U, X86::ST7 },
2489
  { 41U, X86::MM0 },
2490
  { 42U, X86::MM1 },
2491
  { 43U, X86::MM2 },
2492
  { 44U, X86::MM3 },
2493
  { 45U, X86::MM4 },
2494
  { 46U, X86::MM5 },
2495
  { 47U, X86::MM6 },
2496
  { 48U, X86::MM7 },
2497
  { 67U, X86::XMM16 },
2498
  { 68U, X86::XMM17 },
2499
  { 69U, X86::XMM18 },
2500
  { 70U, X86::XMM19 },
2501
  { 71U, X86::XMM20 },
2502
  { 72U, X86::XMM21 },
2503
  { 73U, X86::XMM22 },
2504
  { 74U, X86::XMM23 },
2505
  { 75U, X86::XMM24 },
2506
  { 76U, X86::XMM25 },
2507
  { 77U, X86::XMM26 },
2508
  { 78U, X86::XMM27 },
2509
  { 79U, X86::XMM28 },
2510
  { 80U, X86::XMM29 },
2511
  { 81U, X86::XMM30 },
2512
  { 82U, X86::XMM31 },
2513
  { 118U, X86::K0 },
2514
  { 119U, X86::K1 },
2515
  { 120U, X86::K2 },
2516
  { 121U, X86::K3 },
2517
  { 122U, X86::K4 },
2518
  { 123U, X86::K5 },
2519
  { 124U, X86::K6 },
2520
  { 125U, X86::K7 },
2521
};
2522
extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L);
2523
2524
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2525
  { 0U, X86::EAX },
2526
  { 1U, X86::ECX },
2527
  { 2U, X86::EDX },
2528
  { 3U, X86::EBX },
2529
  { 4U, X86::EBP },
2530
  { 5U, X86::ESP },
2531
  { 6U, X86::ESI },
2532
  { 7U, X86::EDI },
2533
  { 8U, X86::EIP },
2534
  { 12U, X86::ST0 },
2535
  { 13U, X86::ST1 },
2536
  { 14U, X86::ST2 },
2537
  { 15U, X86::ST3 },
2538
  { 16U, X86::ST4 },
2539
  { 17U, X86::ST5 },
2540
  { 18U, X86::ST6 },
2541
  { 19U, X86::ST7 },
2542
  { 21U, X86::XMM0 },
2543
  { 22U, X86::XMM1 },
2544
  { 23U, X86::XMM2 },
2545
  { 24U, X86::XMM3 },
2546
  { 25U, X86::XMM4 },
2547
  { 26U, X86::XMM5 },
2548
  { 27U, X86::XMM6 },
2549
  { 28U, X86::XMM7 },
2550
  { 29U, X86::MM0 },
2551
  { 30U, X86::MM1 },
2552
  { 31U, X86::MM2 },
2553
  { 32U, X86::MM3 },
2554
  { 33U, X86::MM4 },
2555
  { 34U, X86::MM5 },
2556
  { 35U, X86::MM6 },
2557
  { 36U, X86::MM7 },
2558
  { 93U, X86::K0 },
2559
  { 94U, X86::K1 },
2560
  { 95U, X86::K2 },
2561
  { 96U, X86::K3 },
2562
  { 97U, X86::K4 },
2563
  { 98U, X86::K5 },
2564
  { 99U, X86::K6 },
2565
  { 100U, X86::K7 },
2566
};
2567
extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L);
2568
2569
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
2570
  { 0U, X86::EAX },
2571
  { 1U, X86::ECX },
2572
  { 2U, X86::EDX },
2573
  { 3U, X86::EBX },
2574
  { 4U, X86::ESP },
2575
  { 5U, X86::EBP },
2576
  { 6U, X86::ESI },
2577
  { 7U, X86::EDI },
2578
  { 8U, X86::EIP },
2579
  { 11U, X86::ST0 },
2580
  { 12U, X86::ST1 },
2581
  { 13U, X86::ST2 },
2582
  { 14U, X86::ST3 },
2583
  { 15U, X86::ST4 },
2584
  { 16U, X86::ST5 },
2585
  { 17U, X86::ST6 },
2586
  { 18U, X86::ST7 },
2587
  { 21U, X86::XMM0 },
2588
  { 22U, X86::XMM1 },
2589
  { 23U, X86::XMM2 },
2590
  { 24U, X86::XMM3 },
2591
  { 25U, X86::XMM4 },
2592
  { 26U, X86::XMM5 },
2593
  { 27U, X86::XMM6 },
2594
  { 28U, X86::XMM7 },
2595
  { 29U, X86::MM0 },
2596
  { 30U, X86::MM1 },
2597
  { 31U, X86::MM2 },
2598
  { 32U, X86::MM3 },
2599
  { 33U, X86::MM4 },
2600
  { 34U, X86::MM5 },
2601
  { 35U, X86::MM6 },
2602
  { 36U, X86::MM7 },
2603
  { 93U, X86::K0 },
2604
  { 94U, X86::K1 },
2605
  { 95U, X86::K2 },
2606
  { 96U, X86::K3 },
2607
  { 97U, X86::K4 },
2608
  { 98U, X86::K5 },
2609
  { 99U, X86::K6 },
2610
  { 100U, X86::K7 },
2611
};
2612
extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L);
2613
2614
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
2615
  { X86::EAX, -2U },
2616
  { X86::EBP, -2U },
2617
  { X86::EBX, -2U },
2618
  { X86::ECX, -2U },
2619
  { X86::EDI, -2U },
2620
  { X86::EDX, -2U },
2621
  { X86::EIP, -2U },
2622
  { X86::ESI, -2U },
2623
  { X86::ESP, -2U },
2624
  { X86::RAX, 0U },
2625
  { X86::RBP, 6U },
2626
  { X86::RBX, 3U },
2627
  { X86::RCX, 2U },
2628
  { X86::RDI, 5U },
2629
  { X86::RDX, 1U },
2630
  { X86::RIP, 16U },
2631
  { X86::RSI, 4U },
2632
  { X86::RSP, 7U },
2633
  { X86::K0, 118U },
2634
  { X86::K1, 119U },
2635
  { X86::K2, 120U },
2636
  { X86::K3, 121U },
2637
  { X86::K4, 122U },
2638
  { X86::K5, 123U },
2639
  { X86::K6, 124U },
2640
  { X86::K7, 125U },
2641
  { X86::MM0, 41U },
2642
  { X86::MM1, 42U },
2643
  { X86::MM2, 43U },
2644
  { X86::MM3, 44U },
2645
  { X86::MM4, 45U },
2646
  { X86::MM5, 46U },
2647
  { X86::MM6, 47U },
2648
  { X86::MM7, 48U },
2649
  { X86::R8, 8U },
2650
  { X86::R9, 9U },
2651
  { X86::R10, 10U },
2652
  { X86::R11, 11U },
2653
  { X86::R12, 12U },
2654
  { X86::R13, 13U },
2655
  { X86::R14, 14U },
2656
  { X86::R15, 15U },
2657
  { X86::ST0, 33U },
2658
  { X86::ST1, 34U },
2659
  { X86::ST2, 35U },
2660
  { X86::ST3, 36U },
2661
  { X86::ST4, 37U },
2662
  { X86::ST5, 38U },
2663
  { X86::ST6, 39U },
2664
  { X86::ST7, 40U },
2665
  { X86::XMM0, 17U },
2666
  { X86::XMM1, 18U },
2667
  { X86::XMM2, 19U },
2668
  { X86::XMM3, 20U },
2669
  { X86::XMM4, 21U },
2670
  { X86::XMM5, 22U },
2671
  { X86::XMM6, 23U },
2672
  { X86::XMM7, 24U },
2673
  { X86::XMM8, 25U },
2674
  { X86::XMM9, 26U },
2675
  { X86::XMM10, 27U },
2676
  { X86::XMM11, 28U },
2677
  { X86::XMM12, 29U },
2678
  { X86::XMM13, 30U },
2679
  { X86::XMM14, 31U },
2680
  { X86::XMM15, 32U },
2681
  { X86::XMM16, 67U },
2682
  { X86::XMM17, 68U },
2683
  { X86::XMM18, 69U },
2684
  { X86::XMM19, 70U },
2685
  { X86::XMM20, 71U },
2686
  { X86::XMM21, 72U },
2687
  { X86::XMM22, 73U },
2688
  { X86::XMM23, 74U },
2689
  { X86::XMM24, 75U },
2690
  { X86::XMM25, 76U },
2691
  { X86::XMM26, 77U },
2692
  { X86::XMM27, 78U },
2693
  { X86::XMM28, 79U },
2694
  { X86::XMM29, 80U },
2695
  { X86::XMM30, 81U },
2696
  { X86::XMM31, 82U },
2697
  { X86::YMM0, 17U },
2698
  { X86::YMM1, 18U },
2699
  { X86::YMM2, 19U },
2700
  { X86::YMM3, 20U },
2701
  { X86::YMM4, 21U },
2702
  { X86::YMM5, 22U },
2703
  { X86::YMM6, 23U },
2704
  { X86::YMM7, 24U },
2705
  { X86::YMM8, 25U },
2706
  { X86::YMM9, 26U },
2707
  { X86::YMM10, 27U },
2708
  { X86::YMM11, 28U },
2709
  { X86::YMM12, 29U },
2710
  { X86::YMM13, 30U },
2711
  { X86::YMM14, 31U },
2712
  { X86::YMM15, 32U },
2713
  { X86::YMM16, 67U },
2714
  { X86::YMM17, 68U },
2715
  { X86::YMM18, 69U },
2716
  { X86::YMM19, 70U },
2717
  { X86::YMM20, 71U },
2718
  { X86::YMM21, 72U },
2719
  { X86::YMM22, 73U },
2720
  { X86::YMM23, 74U },
2721
  { X86::YMM24, 75U },
2722
  { X86::YMM25, 76U },
2723
  { X86::YMM26, 77U },
2724
  { X86::YMM27, 78U },
2725
  { X86::YMM28, 79U },
2726
  { X86::YMM29, 80U },
2727
  { X86::YMM30, 81U },
2728
  { X86::YMM31, 82U },
2729
  { X86::ZMM0, 17U },
2730
  { X86::ZMM1, 18U },
2731
  { X86::ZMM2, 19U },
2732
  { X86::ZMM3, 20U },
2733
  { X86::ZMM4, 21U },
2734
  { X86::ZMM5, 22U },
2735
  { X86::ZMM6, 23U },
2736
  { X86::ZMM7, 24U },
2737
  { X86::ZMM8, 25U },
2738
  { X86::ZMM9, 26U },
2739
  { X86::ZMM10, 27U },
2740
  { X86::ZMM11, 28U },
2741
  { X86::ZMM12, 29U },
2742
  { X86::ZMM13, 30U },
2743
  { X86::ZMM14, 31U },
2744
  { X86::ZMM15, 32U },
2745
  { X86::ZMM16, 67U },
2746
  { X86::ZMM17, 68U },
2747
  { X86::ZMM18, 69U },
2748
  { X86::ZMM19, 70U },
2749
  { X86::ZMM20, 71U },
2750
  { X86::ZMM21, 72U },
2751
  { X86::ZMM22, 73U },
2752
  { X86::ZMM23, 74U },
2753
  { X86::ZMM24, 75U },
2754
  { X86::ZMM25, 76U },
2755
  { X86::ZMM26, 77U },
2756
  { X86::ZMM27, 78U },
2757
  { X86::ZMM28, 79U },
2758
  { X86::ZMM29, 80U },
2759
  { X86::ZMM30, 81U },
2760
  { X86::ZMM31, 82U },
2761
};
2762
extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf);
2763
2764
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
2765
  { X86::EAX, 0U },
2766
  { X86::EBP, 4U },
2767
  { X86::EBX, 3U },
2768
  { X86::ECX, 1U },
2769
  { X86::EDI, 7U },
2770
  { X86::EDX, 2U },
2771
  { X86::EIP, 8U },
2772
  { X86::ESI, 6U },
2773
  { X86::ESP, 5U },
2774
  { X86::RAX, -2U },
2775
  { X86::RBP, -2U },
2776
  { X86::RBX, -2U },
2777
  { X86::RCX, -2U },
2778
  { X86::RDI, -2U },
2779
  { X86::RDX, -2U },
2780
  { X86::RIP, -2U },
2781
  { X86::RSI, -2U },
2782
  { X86::RSP, -2U },
2783
  { X86::K0, 93U },
2784
  { X86::K1, 94U },
2785
  { X86::K2, 95U },
2786
  { X86::K3, 96U },
2787
  { X86::K4, 97U },
2788
  { X86::K5, 98U },
2789
  { X86::K6, 99U },
2790
  { X86::K7, 100U },
2791
  { X86::MM0, 29U },
2792
  { X86::MM1, 30U },
2793
  { X86::MM2, 31U },
2794
  { X86::MM3, 32U },
2795
  { X86::MM4, 33U },
2796
  { X86::MM5, 34U },
2797
  { X86::MM6, 35U },
2798
  { X86::MM7, 36U },
2799
  { X86::R8, -2U },
2800
  { X86::R9, -2U },
2801
  { X86::R10, -2U },
2802
  { X86::R11, -2U },
2803
  { X86::R12, -2U },
2804
  { X86::R13, -2U },
2805
  { X86::R14, -2U },
2806
  { X86::R15, -2U },
2807
  { X86::ST0, 12U },
2808
  { X86::ST1, 13U },
2809
  { X86::ST2, 14U },
2810
  { X86::ST3, 15U },
2811
  { X86::ST4, 16U },
2812
  { X86::ST5, 17U },
2813
  { X86::ST6, 18U },
2814
  { X86::ST7, 19U },
2815
  { X86::XMM0, 21U },
2816
  { X86::XMM1, 22U },
2817
  { X86::XMM2, 23U },
2818
  { X86::XMM3, 24U },
2819
  { X86::XMM4, 25U },
2820
  { X86::XMM5, 26U },
2821
  { X86::XMM6, 27U },
2822
  { X86::XMM7, 28U },
2823
  { X86::XMM8, -2U },
2824
  { X86::XMM9, -2U },
2825
  { X86::XMM10, -2U },
2826
  { X86::XMM11, -2U },
2827
  { X86::XMM12, -2U },
2828
  { X86::XMM13, -2U },
2829
  { X86::XMM14, -2U },
2830
  { X86::XMM15, -2U },
2831
  { X86::XMM16, -2U },
2832
  { X86::XMM17, -2U },
2833
  { X86::XMM18, -2U },
2834
  { X86::XMM19, -2U },
2835
  { X86::XMM20, -2U },
2836
  { X86::XMM21, -2U },
2837
  { X86::XMM22, -2U },
2838
  { X86::XMM23, -2U },
2839
  { X86::XMM24, -2U },
2840
  { X86::XMM25, -2U },
2841
  { X86::XMM26, -2U },
2842
  { X86::XMM27, -2U },
2843
  { X86::XMM28, -2U },
2844
  { X86::XMM29, -2U },
2845
  { X86::XMM30, -2U },
2846
  { X86::XMM31, -2U },
2847
  { X86::YMM0, 21U },
2848
  { X86::YMM1, 22U },
2849
  { X86::YMM2, 23U },
2850
  { X86::YMM3, 24U },
2851
  { X86::YMM4, 25U },
2852
  { X86::YMM5, 26U },
2853
  { X86::YMM6, 27U },
2854
  { X86::YMM7, 28U },
2855
  { X86::YMM8, -2U },
2856
  { X86::YMM9, -2U },
2857
  { X86::YMM10, -2U },
2858
  { X86::YMM11, -2U },
2859
  { X86::YMM12, -2U },
2860
  { X86::YMM13, -2U },
2861
  { X86::YMM14, -2U },
2862
  { X86::YMM15, -2U },
2863
  { X86::YMM16, -2U },
2864
  { X86::YMM17, -2U },
2865
  { X86::YMM18, -2U },
2866
  { X86::YMM19, -2U },
2867
  { X86::YMM20, -2U },
2868
  { X86::YMM21, -2U },
2869
  { X86::YMM22, -2U },
2870
  { X86::YMM23, -2U },
2871
  { X86::YMM24, -2U },
2872
  { X86::YMM25, -2U },
2873
  { X86::YMM26, -2U },
2874
  { X86::YMM27, -2U },
2875
  { X86::YMM28, -2U },
2876
  { X86::YMM29, -2U },
2877
  { X86::YMM30, -2U },
2878
  { X86::YMM31, -2U },
2879
  { X86::ZMM0, 21U },
2880
  { X86::ZMM1, 22U },
2881
  { X86::ZMM2, 23U },
2882
  { X86::ZMM3, 24U },
2883
  { X86::ZMM4, 25U },
2884
  { X86::ZMM5, 26U },
2885
  { X86::ZMM6, 27U },
2886
  { X86::ZMM7, 28U },
2887
  { X86::ZMM8, -2U },
2888
  { X86::ZMM9, -2U },
2889
  { X86::ZMM10, -2U },
2890
  { X86::ZMM11, -2U },
2891
  { X86::ZMM12, -2U },
2892
  { X86::ZMM13, -2U },
2893
  { X86::ZMM14, -2U },
2894
  { X86::ZMM15, -2U },
2895
  { X86::ZMM16, -2U },
2896
  { X86::ZMM17, -2U },
2897
  { X86::ZMM18, -2U },
2898
  { X86::ZMM19, -2U },
2899
  { X86::ZMM20, -2U },
2900
  { X86::ZMM21, -2U },
2901
  { X86::ZMM22, -2U },
2902
  { X86::ZMM23, -2U },
2903
  { X86::ZMM24, -2U },
2904
  { X86::ZMM25, -2U },
2905
  { X86::ZMM26, -2U },
2906
  { X86::ZMM27, -2U },
2907
  { X86::ZMM28, -2U },
2908
  { X86::ZMM29, -2U },
2909
  { X86::ZMM30, -2U },
2910
  { X86::ZMM31, -2U },
2911
};
2912
extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf);
2913
2914
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
2915
  { X86::EAX, 0U },
2916
  { X86::EBP, 5U },
2917
  { X86::EBX, 3U },
2918
  { X86::ECX, 1U },
2919
  { X86::EDI, 7U },
2920
  { X86::EDX, 2U },
2921
  { X86::EIP, 8U },
2922
  { X86::ESI, 6U },
2923
  { X86::ESP, 4U },
2924
  { X86::RAX, -2U },
2925
  { X86::RBP, -2U },
2926
  { X86::RBX, -2U },
2927
  { X86::RCX, -2U },
2928
  { X86::RDI, -2U },
2929
  { X86::RDX, -2U },
2930
  { X86::RIP, -2U },
2931
  { X86::RSI, -2U },
2932
  { X86::RSP, -2U },
2933
  { X86::K0, 93U },
2934
  { X86::K1, 94U },
2935
  { X86::K2, 95U },
2936
  { X86::K3, 96U },
2937
  { X86::K4, 97U },
2938
  { X86::K5, 98U },
2939
  { X86::K6, 99U },
2940
  { X86::K7, 100U },
2941
  { X86::MM0, 29U },
2942
  { X86::MM1, 30U },
2943
  { X86::MM2, 31U },
2944
  { X86::MM3, 32U },
2945
  { X86::MM4, 33U },
2946
  { X86::MM5, 34U },
2947
  { X86::MM6, 35U },
2948
  { X86::MM7, 36U },
2949
  { X86::R8, -2U },
2950
  { X86::R9, -2U },
2951
  { X86::R10, -2U },
2952
  { X86::R11, -2U },
2953
  { X86::R12, -2U },
2954
  { X86::R13, -2U },
2955
  { X86::R14, -2U },
2956
  { X86::R15, -2U },
2957
  { X86::ST0, 11U },
2958
  { X86::ST1, 12U },
2959
  { X86::ST2, 13U },
2960
  { X86::ST3, 14U },
2961
  { X86::ST4, 15U },
2962
  { X86::ST5, 16U },
2963
  { X86::ST6, 17U },
2964
  { X86::ST7, 18U },
2965
  { X86::XMM0, 21U },
2966
  { X86::XMM1, 22U },
2967
  { X86::XMM2, 23U },
2968
  { X86::XMM3, 24U },
2969
  { X86::XMM4, 25U },
2970
  { X86::XMM5, 26U },
2971
  { X86::XMM6, 27U },
2972
  { X86::XMM7, 28U },
2973
  { X86::XMM8, -2U },
2974
  { X86::XMM9, -2U },
2975
  { X86::XMM10, -2U },
2976
  { X86::XMM11, -2U },
2977
  { X86::XMM12, -2U },
2978
  { X86::XMM13, -2U },
2979
  { X86::XMM14, -2U },
2980
  { X86::XMM15, -2U },
2981
  { X86::XMM16, -2U },
2982
  { X86::XMM17, -2U },
2983
  { X86::XMM18, -2U },
2984
  { X86::XMM19, -2U },
2985
  { X86::XMM20, -2U },
2986
  { X86::XMM21, -2U },
2987
  { X86::XMM22, -2U },
2988
  { X86::XMM23, -2U },
2989
  { X86::XMM24, -2U },
2990
  { X86::XMM25, -2U },
2991
  { X86::XMM26, -2U },
2992
  { X86::XMM27, -2U },
2993
  { X86::XMM28, -2U },
2994
  { X86::XMM29, -2U },
2995
  { X86::XMM30, -2U },
2996
  { X86::XMM31, -2U },
2997
  { X86::YMM0, 21U },
2998
  { X86::YMM1, 22U },
2999
  { X86::YMM2, 23U },
3000
  { X86::YMM3, 24U },
3001
  { X86::YMM4, 25U },
3002
  { X86::YMM5, 26U },
3003
  { X86::YMM6, 27U },
3004
  { X86::YMM7, 28U },
3005
  { X86::YMM8, -2U },
3006
  { X86::YMM9, -2U },
3007
  { X86::YMM10, -2U },
3008
  { X86::YMM11, -2U },
3009
  { X86::YMM12, -2U },
3010
  { X86::YMM13, -2U },
3011
  { X86::YMM14, -2U },
3012
  { X86::YMM15, -2U },
3013
  { X86::YMM16, -2U },
3014
  { X86::YMM17, -2U },
3015
  { X86::YMM18, -2U },
3016
  { X86::YMM19, -2U },
3017
  { X86::YMM20, -2U },
3018
  { X86::YMM21, -2U },
3019
  { X86::YMM22, -2U },
3020
  { X86::YMM23, -2U },
3021
  { X86::YMM24, -2U },
3022
  { X86::YMM25, -2U },
3023
  { X86::YMM26, -2U },
3024
  { X86::YMM27, -2U },
3025
  { X86::YMM28, -2U },
3026
  { X86::YMM29, -2U },
3027
  { X86::YMM30, -2U },
3028
  { X86::YMM31, -2U },
3029
  { X86::ZMM0, 21U },
3030
  { X86::ZMM1, 22U },
3031
  { X86::ZMM2, 23U },
3032
  { X86::ZMM3, 24U },
3033
  { X86::ZMM4, 25U },
3034
  { X86::ZMM5, 26U },
3035
  { X86::ZMM6, 27U },
3036
  { X86::ZMM7, 28U },
3037
  { X86::ZMM8, -2U },
3038
  { X86::ZMM9, -2U },
3039
  { X86::ZMM10, -2U },
3040
  { X86::ZMM11, -2U },
3041
  { X86::ZMM12, -2U },
3042
  { X86::ZMM13, -2U },
3043
  { X86::ZMM14, -2U },
3044
  { X86::ZMM15, -2U },
3045
  { X86::ZMM16, -2U },
3046
  { X86::ZMM17, -2U },
3047
  { X86::ZMM18, -2U },
3048
  { X86::ZMM19, -2U },
3049
  { X86::ZMM20, -2U },
3050
  { X86::ZMM21, -2U },
3051
  { X86::ZMM22, -2U },
3052
  { X86::ZMM23, -2U },
3053
  { X86::ZMM24, -2U },
3054
  { X86::ZMM25, -2U },
3055
  { X86::ZMM26, -2U },
3056
  { X86::ZMM27, -2U },
3057
  { X86::ZMM28, -2U },
3058
  { X86::ZMM29, -2U },
3059
  { X86::ZMM30, -2U },
3060
  { X86::ZMM31, -2U },
3061
};
3062
extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf);
3063
3064
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3065
  { X86::EAX, -2U },
3066
  { X86::EBP, -2U },
3067
  { X86::EBX, -2U },
3068
  { X86::ECX, -2U },
3069
  { X86::EDI, -2U },
3070
  { X86::EDX, -2U },
3071
  { X86::EIP, -2U },
3072
  { X86::ESI, -2U },
3073
  { X86::ESP, -2U },
3074
  { X86::RAX, 0U },
3075
  { X86::RBP, 6U },
3076
  { X86::RBX, 3U },
3077
  { X86::RCX, 2U },
3078
  { X86::RDI, 5U },
3079
  { X86::RDX, 1U },
3080
  { X86::RIP, 16U },
3081
  { X86::RSI, 4U },
3082
  { X86::RSP, 7U },
3083
  { X86::K0, 118U },
3084
  { X86::K1, 119U },
3085
  { X86::K2, 120U },
3086
  { X86::K3, 121U },
3087
  { X86::K4, 122U },
3088
  { X86::K5, 123U },
3089
  { X86::K6, 124U },
3090
  { X86::K7, 125U },
3091
  { X86::MM0, 41U },
3092
  { X86::MM1, 42U },
3093
  { X86::MM2, 43U },
3094
  { X86::MM3, 44U },
3095
  { X86::MM4, 45U },
3096
  { X86::MM5, 46U },
3097
  { X86::MM6, 47U },
3098
  { X86::MM7, 48U },
3099
  { X86::R8, 8U },
3100
  { X86::R9, 9U },
3101
  { X86::R10, 10U },
3102
  { X86::R11, 11U },
3103
  { X86::R12, 12U },
3104
  { X86::R13, 13U },
3105
  { X86::R14, 14U },
3106
  { X86::R15, 15U },
3107
  { X86::ST0, 33U },
3108
  { X86::ST1, 34U },
3109
  { X86::ST2, 35U },
3110
  { X86::ST3, 36U },
3111
  { X86::ST4, 37U },
3112
  { X86::ST5, 38U },
3113
  { X86::ST6, 39U },
3114
  { X86::ST7, 40U },
3115
  { X86::XMM0, 17U },
3116
  { X86::XMM1, 18U },
3117
  { X86::XMM2, 19U },
3118
  { X86::XMM3, 20U },
3119
  { X86::XMM4, 21U },
3120
  { X86::XMM5, 22U },
3121
  { X86::XMM6, 23U },
3122
  { X86::XMM7, 24U },
3123
  { X86::XMM8, 25U },
3124
  { X86::XMM9, 26U },
3125
  { X86::XMM10, 27U },
3126
  { X86::XMM11, 28U },
3127
  { X86::XMM12, 29U },
3128
  { X86::XMM13, 30U },
3129
  { X86::XMM14, 31U },
3130
  { X86::XMM15, 32U },
3131
  { X86::XMM16, 67U },
3132
  { X86::XMM17, 68U },
3133
  { X86::XMM18, 69U },
3134
  { X86::XMM19, 70U },
3135
  { X86::XMM20, 71U },
3136
  { X86::XMM21, 72U },
3137
  { X86::XMM22, 73U },
3138
  { X86::XMM23, 74U },
3139
  { X86::XMM24, 75U },
3140
  { X86::XMM25, 76U },
3141
  { X86::XMM26, 77U },
3142
  { X86::XMM27, 78U },
3143
  { X86::XMM28, 79U },
3144
  { X86::XMM29, 80U },
3145
  { X86::XMM30, 81U },
3146
  { X86::XMM31, 82U },
3147
  { X86::YMM0, 17U },
3148
  { X86::YMM1, 18U },
3149
  { X86::YMM2, 19U },
3150
  { X86::YMM3, 20U },
3151
  { X86::YMM4, 21U },
3152
  { X86::YMM5, 22U },
3153
  { X86::YMM6, 23U },
3154
  { X86::YMM7, 24U },
3155
  { X86::YMM8, 25U },
3156
  { X86::YMM9, 26U },
3157
  { X86::YMM10, 27U },
3158
  { X86::YMM11, 28U },
3159
  { X86::YMM12, 29U },
3160
  { X86::YMM13, 30U },
3161
  { X86::YMM14, 31U },
3162
  { X86::YMM15, 32U },
3163
  { X86::YMM16, 67U },
3164
  { X86::YMM17, 68U },
3165
  { X86::YMM18, 69U },
3166
  { X86::YMM19, 70U },
3167
  { X86::YMM20, 71U },
3168
  { X86::YMM21, 72U },
3169
  { X86::YMM22, 73U },
3170
  { X86::YMM23, 74U },
3171
  { X86::YMM24, 75U },
3172
  { X86::YMM25, 76U },
3173
  { X86::YMM26, 77U },
3174
  { X86::YMM27, 78U },
3175
  { X86::YMM28, 79U },
3176
  { X86::YMM29, 80U },
3177
  { X86::YMM30, 81U },
3178
  { X86::YMM31, 82U },
3179
  { X86::ZMM0, 17U },
3180
  { X86::ZMM1, 18U },
3181
  { X86::ZMM2, 19U },
3182
  { X86::ZMM3, 20U },
3183
  { X86::ZMM4, 21U },
3184
  { X86::ZMM5, 22U },
3185
  { X86::ZMM6, 23U },
3186
  { X86::ZMM7, 24U },
3187
  { X86::ZMM8, 25U },
3188
  { X86::ZMM9, 26U },
3189
  { X86::ZMM10, 27U },
3190
  { X86::ZMM11, 28U },
3191
  { X86::ZMM12, 29U },
3192
  { X86::ZMM13, 30U },
3193
  { X86::ZMM14, 31U },
3194
  { X86::ZMM15, 32U },
3195
  { X86::ZMM16, 67U },
3196
  { X86::ZMM17, 68U },
3197
  { X86::ZMM18, 69U },
3198
  { X86::ZMM19, 70U },
3199
  { X86::ZMM20, 71U },
3200
  { X86::ZMM21, 72U },
3201
  { X86::ZMM22, 73U },
3202
  { X86::ZMM23, 74U },
3203
  { X86::ZMM24, 75U },
3204
  { X86::ZMM25, 76U },
3205
  { X86::ZMM26, 77U },
3206
  { X86::ZMM27, 78U },
3207
  { X86::ZMM28, 79U },
3208
  { X86::ZMM29, 80U },
3209
  { X86::ZMM30, 81U },
3210
  { X86::ZMM31, 82U },
3211
};
3212
extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf);
3213
3214
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3215
  { X86::EAX, 0U },
3216
  { X86::EBP, 4U },
3217
  { X86::EBX, 3U },
3218
  { X86::ECX, 1U },
3219
  { X86::EDI, 7U },
3220
  { X86::EDX, 2U },
3221
  { X86::EIP, 8U },
3222
  { X86::ESI, 6U },
3223
  { X86::ESP, 5U },
3224
  { X86::RAX, -2U },
3225
  { X86::RBP, -2U },
3226
  { X86::RBX, -2U },
3227
  { X86::RCX, -2U },
3228
  { X86::RDI, -2U },
3229
  { X86::RDX, -2U },
3230
  { X86::RIP, -2U },
3231
  { X86::RSI, -2U },
3232
  { X86::RSP, -2U },
3233
  { X86::K0, 93U },
3234
  { X86::K1, 94U },
3235
  { X86::K2, 95U },
3236
  { X86::K3, 96U },
3237
  { X86::K4, 97U },
3238
  { X86::K5, 98U },
3239
  { X86::K6, 99U },
3240
  { X86::K7, 100U },
3241
  { X86::MM0, 29U },
3242
  { X86::MM1, 30U },
3243
  { X86::MM2, 31U },
3244
  { X86::MM3, 32U },
3245
  { X86::MM4, 33U },
3246
  { X86::MM5, 34U },
3247
  { X86::MM6, 35U },
3248
  { X86::MM7, 36U },
3249
  { X86::R8, -2U },
3250
  { X86::R9, -2U },
3251
  { X86::R10, -2U },
3252
  { X86::R11, -2U },
3253
  { X86::R12, -2U },
3254
  { X86::R13, -2U },
3255
  { X86::R14, -2U },
3256
  { X86::R15, -2U },
3257
  { X86::ST0, 12U },
3258
  { X86::ST1, 13U },
3259
  { X86::ST2, 14U },
3260
  { X86::ST3, 15U },
3261
  { X86::ST4, 16U },
3262
  { X86::ST5, 17U },
3263
  { X86::ST6, 18U },
3264
  { X86::ST7, 19U },
3265
  { X86::XMM0, 21U },
3266
  { X86::XMM1, 22U },
3267
  { X86::XMM2, 23U },
3268
  { X86::XMM3, 24U },
3269
  { X86::XMM4, 25U },
3270
  { X86::XMM5, 26U },
3271
  { X86::XMM6, 27U },
3272
  { X86::XMM7, 28U },
3273
  { X86::XMM8, -2U },
3274
  { X86::XMM9, -2U },
3275
  { X86::XMM10, -2U },
3276
  { X86::XMM11, -2U },
3277
  { X86::XMM12, -2U },
3278
  { X86::XMM13, -2U },
3279
  { X86::XMM14, -2U },
3280
  { X86::XMM15, -2U },
3281
  { X86::XMM16, -2U },
3282
  { X86::XMM17, -2U },
3283
  { X86::XMM18, -2U },
3284
  { X86::XMM19, -2U },
3285
  { X86::XMM20, -2U },
3286
  { X86::XMM21, -2U },
3287
  { X86::XMM22, -2U },
3288
  { X86::XMM23, -2U },
3289
  { X86::XMM24, -2U },
3290
  { X86::XMM25, -2U },
3291
  { X86::XMM26, -2U },
3292
  { X86::XMM27, -2U },
3293
  { X86::XMM28, -2U },
3294
  { X86::XMM29, -2U },
3295
  { X86::XMM30, -2U },
3296
  { X86::XMM31, -2U },
3297
  { X86::YMM0, 21U },
3298
  { X86::YMM1, 22U },
3299
  { X86::YMM2, 23U },
3300
  { X86::YMM3, 24U },
3301
  { X86::YMM4, 25U },
3302
  { X86::YMM5, 26U },
3303
  { X86::YMM6, 27U },
3304
  { X86::YMM7, 28U },
3305
  { X86::YMM8, -2U },
3306
  { X86::YMM9, -2U },
3307
  { X86::YMM10, -2U },
3308
  { X86::YMM11, -2U },
3309
  { X86::YMM12, -2U },
3310
  { X86::YMM13, -2U },
3311
  { X86::YMM14, -2U },
3312
  { X86::YMM15, -2U },
3313
  { X86::YMM16, -2U },
3314
  { X86::YMM17, -2U },
3315
  { X86::YMM18, -2U },
3316
  { X86::YMM19, -2U },
3317
  { X86::YMM20, -2U },
3318
  { X86::YMM21, -2U },
3319
  { X86::YMM22, -2U },
3320
  { X86::YMM23, -2U },
3321
  { X86::YMM24, -2U },
3322
  { X86::YMM25, -2U },
3323
  { X86::YMM26, -2U },
3324
  { X86::YMM27, -2U },
3325
  { X86::YMM28, -2U },
3326
  { X86::YMM29, -2U },
3327
  { X86::YMM30, -2U },
3328
  { X86::YMM31, -2U },
3329
  { X86::ZMM0, 21U },
3330
  { X86::ZMM1, 22U },
3331
  { X86::ZMM2, 23U },
3332
  { X86::ZMM3, 24U },
3333
  { X86::ZMM4, 25U },
3334
  { X86::ZMM5, 26U },
3335
  { X86::ZMM6, 27U },
3336
  { X86::ZMM7, 28U },
3337
  { X86::ZMM8, -2U },
3338
  { X86::ZMM9, -2U },
3339
  { X86::ZMM10, -2U },
3340
  { X86::ZMM11, -2U },
3341
  { X86::ZMM12, -2U },
3342
  { X86::ZMM13, -2U },
3343
  { X86::ZMM14, -2U },
3344
  { X86::ZMM15, -2U },
3345
  { X86::ZMM16, -2U },
3346
  { X86::ZMM17, -2U },
3347
  { X86::ZMM18, -2U },
3348
  { X86::ZMM19, -2U },
3349
  { X86::ZMM20, -2U },
3350
  { X86::ZMM21, -2U },
3351
  { X86::ZMM22, -2U },
3352
  { X86::ZMM23, -2U },
3353
  { X86::ZMM24, -2U },
3354
  { X86::ZMM25, -2U },
3355
  { X86::ZMM26, -2U },
3356
  { X86::ZMM27, -2U },
3357
  { X86::ZMM28, -2U },
3358
  { X86::ZMM29, -2U },
3359
  { X86::ZMM30, -2U },
3360
  { X86::ZMM31, -2U },
3361
};
3362
extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf);
3363
3364
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3365
  { X86::EAX, 0U },
3366
  { X86::EBP, 5U },
3367
  { X86::EBX, 3U },
3368
  { X86::ECX, 1U },
3369
  { X86::EDI, 7U },
3370
  { X86::EDX, 2U },
3371
  { X86::EIP, 8U },
3372
  { X86::ESI, 6U },
3373
  { X86::ESP, 4U },
3374
  { X86::RAX, -2U },
3375
  { X86::RBP, -2U },
3376
  { X86::RBX, -2U },
3377
  { X86::RCX, -2U },
3378
  { X86::RDI, -2U },
3379
  { X86::RDX, -2U },
3380
  { X86::RIP, -2U },
3381
  { X86::RSI, -2U },
3382
  { X86::RSP, -2U },
3383
  { X86::K0, 93U },
3384
  { X86::K1, 94U },
3385
  { X86::K2, 95U },
3386
  { X86::K3, 96U },
3387
  { X86::K4, 97U },
3388
  { X86::K5, 98U },
3389
  { X86::K6, 99U },
3390
  { X86::K7, 100U },
3391
  { X86::MM0, 29U },
3392
  { X86::MM1, 30U },
3393
  { X86::MM2, 31U },
3394
  { X86::MM3, 32U },
3395
  { X86::MM4, 33U },
3396
  { X86::MM5, 34U },
3397
  { X86::MM6, 35U },
3398
  { X86::MM7, 36U },
3399
  { X86::R8, -2U },
3400
  { X86::R9, -2U },
3401
  { X86::R10, -2U },
3402
  { X86::R11, -2U },
3403
  { X86::R12, -2U },
3404
  { X86::R13, -2U },
3405
  { X86::R14, -2U },
3406
  { X86::R15, -2U },
3407
  { X86::ST0, 11U },
3408
  { X86::ST1, 12U },
3409
  { X86::ST2, 13U },
3410
  { X86::ST3, 14U },
3411
  { X86::ST4, 15U },
3412
  { X86::ST5, 16U },
3413
  { X86::ST6, 17U },
3414
  { X86::ST7, 18U },
3415
  { X86::XMM0, 21U },
3416
  { X86::XMM1, 22U },
3417
  { X86::XMM2, 23U },
3418
  { X86::XMM3, 24U },
3419
  { X86::XMM4, 25U },
3420
  { X86::XMM5, 26U },
3421
  { X86::XMM6, 27U },
3422
  { X86::XMM7, 28U },
3423
  { X86::XMM8, -2U },
3424
  { X86::XMM9, -2U },
3425
  { X86::XMM10, -2U },
3426
  { X86::XMM11, -2U },
3427
  { X86::XMM12, -2U },
3428
  { X86::XMM13, -2U },
3429
  { X86::XMM14, -2U },
3430
  { X86::XMM15, -2U },
3431
  { X86::XMM16, -2U },
3432
  { X86::XMM17, -2U },
3433
  { X86::XMM18, -2U },
3434
  { X86::XMM19, -2U },
3435
  { X86::XMM20, -2U },
3436
  { X86::XMM21, -2U },
3437
  { X86::XMM22, -2U },
3438
  { X86::XMM23, -2U },
3439
  { X86::XMM24, -2U },
3440
  { X86::XMM25, -2U },
3441
  { X86::XMM26, -2U },
3442
  { X86::XMM27, -2U },
3443
  { X86::XMM28, -2U },
3444
  { X86::XMM29, -2U },
3445
  { X86::XMM30, -2U },
3446
  { X86::XMM31, -2U },
3447
  { X86::YMM0, 21U },
3448
  { X86::YMM1, 22U },
3449
  { X86::YMM2, 23U },
3450
  { X86::YMM3, 24U },
3451
  { X86::YMM4, 25U },
3452
  { X86::YMM5, 26U },
3453
  { X86::YMM6, 27U },
3454
  { X86::YMM7, 28U },
3455
  { X86::YMM8, -2U },
3456
  { X86::YMM9, -2U },
3457
  { X86::YMM10, -2U },
3458
  { X86::YMM11, -2U },
3459
  { X86::YMM12, -2U },
3460
  { X86::YMM13, -2U },
3461
  { X86::YMM14, -2U },
3462
  { X86::YMM15, -2U },
3463
  { X86::YMM16, -2U },
3464
  { X86::YMM17, -2U },
3465
  { X86::YMM18, -2U },
3466
  { X86::YMM19, -2U },
3467
  { X86::YMM20, -2U },
3468
  { X86::YMM21, -2U },
3469
  { X86::YMM22, -2U },
3470
  { X86::YMM23, -2U },
3471
  { X86::YMM24, -2U },
3472
  { X86::YMM25, -2U },
3473
  { X86::YMM26, -2U },
3474
  { X86::YMM27, -2U },
3475
  { X86::YMM28, -2U },
3476
  { X86::YMM29, -2U },
3477
  { X86::YMM30, -2U },
3478
  { X86::YMM31, -2U },
3479
  { X86::ZMM0, 21U },
3480
  { X86::ZMM1, 22U },
3481
  { X86::ZMM2, 23U },
3482
  { X86::ZMM3, 24U },
3483
  { X86::ZMM4, 25U },
3484
  { X86::ZMM5, 26U },
3485
  { X86::ZMM6, 27U },
3486
  { X86::ZMM7, 28U },
3487
  { X86::ZMM8, -2U },
3488
  { X86::ZMM9, -2U },
3489
  { X86::ZMM10, -2U },
3490
  { X86::ZMM11, -2U },
3491
  { X86::ZMM12, -2U },
3492
  { X86::ZMM13, -2U },
3493
  { X86::ZMM14, -2U },
3494
  { X86::ZMM15, -2U },
3495
  { X86::ZMM16, -2U },
3496
  { X86::ZMM17, -2U },
3497
  { X86::ZMM18, -2U },
3498
  { X86::ZMM19, -2U },
3499
  { X86::ZMM20, -2U },
3500
  { X86::ZMM21, -2U },
3501
  { X86::ZMM22, -2U },
3502
  { X86::ZMM23, -2U },
3503
  { X86::ZMM24, -2U },
3504
  { X86::ZMM25, -2U },
3505
  { X86::ZMM26, -2U },
3506
  { X86::ZMM27, -2U },
3507
  { X86::ZMM28, -2U },
3508
  { X86::ZMM29, -2U },
3509
  { X86::ZMM30, -2U },
3510
  { X86::ZMM31, -2U },
3511
};
3512
extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf);
3513
3514
extern const uint16_t X86RegEncodingTable[] = {
3515
  0,
3516
  4,
3517
  0,
3518
  0,
3519
  7,
3520
  3,
3521
  5,
3522
  65535,
3523
  5,
3524
  3,
3525
  5,
3526
  1,
3527
  1,
3528
  1,
3529
  0,
3530
  6,
3531
  7,
3532
  65535,
3533
  7,
3534
  2,
3535
  3,
3536
  2,
3537
  0,
3538
  5,
3539
  3,
3540
  1,
3541
  7,
3542
  2,
3543
  0,
3544
  0,
3545
  4,
3546
  0,
3547
  6,
3548
  4,
3549
  0,
3550
  4,
3551
  5,
3552
  65535,
3553
  65535,
3554
  65535,
3555
  65535,
3556
  65535,
3557
  65535,
3558
  65535,
3559
  65535,
3560
  65535,
3561
  0,
3562
  0,
3563
  5,
3564
  3,
3565
  1,
3566
  7,
3567
  2,
3568
  0,
3569
  4,
3570
  6,
3571
  4,
3572
  6,
3573
  65535,
3574
  6,
3575
  4,
3576
  65535,
3577
  4,
3578
  2,
3579
  0,
3580
  0,
3581
  1,
3582
  2,
3583
  3,
3584
  0,
3585
  1,
3586
  2,
3587
  3,
3588
  4,
3589
  5,
3590
  6,
3591
  7,
3592
  8,
3593
  9,
3594
  10,
3595
  11,
3596
  12,
3597
  13,
3598
  14,
3599
  15,
3600
  0,
3601
  1,
3602
  2,
3603
  3,
3604
  4,
3605
  5,
3606
  6,
3607
  7,
3608
  8,
3609
  9,
3610
  10,
3611
  11,
3612
  12,
3613
  13,
3614
  14,
3615
  15,
3616
  0,
3617
  0,
3618
  0,
3619
  0,
3620
  0,
3621
  0,
3622
  0,
3623
  0,
3624
  0,
3625
  1,
3626
  2,
3627
  3,
3628
  4,
3629
  5,
3630
  6,
3631
  7,
3632
  0,
3633
  1,
3634
  2,
3635
  3,
3636
  4,
3637
  5,
3638
  6,
3639
  7,
3640
  8,
3641
  9,
3642
  10,
3643
  11,
3644
  12,
3645
  13,
3646
  14,
3647
  15,
3648
  0,
3649
  1,
3650
  2,
3651
  3,
3652
  4,
3653
  5,
3654
  6,
3655
  7,
3656
  0,
3657
  1,
3658
  2,
3659
  3,
3660
  4,
3661
  5,
3662
  6,
3663
  7,
3664
  8,
3665
  9,
3666
  10,
3667
  11,
3668
  12,
3669
  13,
3670
  14,
3671
  15,
3672
  16,
3673
  17,
3674
  18,
3675
  19,
3676
  20,
3677
  21,
3678
  22,
3679
  23,
3680
  24,
3681
  25,
3682
  26,
3683
  27,
3684
  28,
3685
  29,
3686
  30,
3687
  31,
3688
  0,
3689
  1,
3690
  2,
3691
  3,
3692
  4,
3693
  5,
3694
  6,
3695
  7,
3696
  8,
3697
  9,
3698
  10,
3699
  11,
3700
  12,
3701
  13,
3702
  14,
3703
  15,
3704
  16,
3705
  17,
3706
  18,
3707
  19,
3708
  20,
3709
  21,
3710
  22,
3711
  23,
3712
  24,
3713
  25,
3714
  26,
3715
  27,
3716
  28,
3717
  29,
3718
  30,
3719
  31,
3720
  0,
3721
  1,
3722
  2,
3723
  3,
3724
  4,
3725
  5,
3726
  6,
3727
  7,
3728
  8,
3729
  9,
3730
  10,
3731
  11,
3732
  12,
3733
  13,
3734
  14,
3735
  15,
3736
  16,
3737
  17,
3738
  18,
3739
  19,
3740
  20,
3741
  21,
3742
  22,
3743
  23,
3744
  24,
3745
  25,
3746
  26,
3747
  27,
3748
  28,
3749
  29,
3750
  30,
3751
  31,
3752
  8,
3753
  9,
3754
  10,
3755
  11,
3756
  12,
3757
  13,
3758
  14,
3759
  15,
3760
  65535,
3761
  65535,
3762
  65535,
3763
  65535,
3764
  65535,
3765
  65535,
3766
  65535,
3767
  65535,
3768
  8,
3769
  9,
3770
  10,
3771
  11,
3772
  12,
3773
  13,
3774
  14,
3775
  15,
3776
  8,
3777
  9,
3778
  10,
3779
  11,
3780
  12,
3781
  13,
3782
  14,
3783
  15,
3784
  65535,
3785
  65535,
3786
  65535,
3787
  65535,
3788
  65535,
3789
  65535,
3790
  65535,
3791
  65535,
3792
};
3793
24.4k
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3794
24.4k
  RI->InitMCRegisterInfo(X86RegDesc, 277, RA, PC, X86MCRegisterClasses, 86, X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 9,
3795
24.4k
X86SubRegIdxRanges, X86RegEncodingTable);
3796
24.4k
3797
24.4k
  switch (DwarfFlavour) {
3798
24.4k
  default:
3799
0
    llvm_unreachable("Unknown DWARF flavour");
3800
24.4k
  case 0:
3801
17.9k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
3802
17.9k
    break;
3803
24.4k
  case 1:
3804
0
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
3805
0
    break;
3806
24.4k
  case 2:
3807
6.51k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
3808
6.51k
    break;
3809
24.4k
  }
3810
24.4k
  switch (EHFlavour) {
3811
24.4k
  default:
3812
0
    llvm_unreachable("Unknown DWARF flavour");
3813
24.4k
  case 0:
3814
17.9k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
3815
17.9k
    break;
3816
24.4k
  case 1:
3817
1.98k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
3818
1.98k
    break;
3819
24.4k
  case 2:
3820
4.52k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
3821
4.52k
    break;
3822
24.4k
  }
3823
24.4k
  switch (DwarfFlavour) {
3824
24.4k
  default:
3825
0
    llvm_unreachable("Unknown DWARF flavour");
3826
24.4k
  case 0:
3827
17.9k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
3828
17.9k
    break;
3829
24.4k
  case 1:
3830
0
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
3831
0
    break;
3832
24.4k
  case 2:
3833
6.51k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
3834
6.51k
    break;
3835
24.4k
  }
3836
24.4k
  switch (EHFlavour) {
3837
24.4k
  default:
3838
0
    llvm_unreachable("Unknown DWARF flavour");
3839
24.4k
  case 0:
3840
17.9k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
3841
17.9k
    break;
3842
24.4k
  case 1:
3843
1.98k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
3844
1.98k
    break;
3845
24.4k
  case 2:
3846
4.52k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
3847
4.52k
    break;
3848
24.4k
  }
3849
24.4k
}
3850
3851
} // end namespace llvm
3852
3853
#endif // GET_REGINFO_MC_DESC
3854
3855
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3856
|*                                                                            *|
3857
|* Register Information Header Fragment                                       *|
3858
|*                                                                            *|
3859
|* Automatically generated file, do not edit!                                 *|
3860
|*                                                                            *|
3861
\*===----------------------------------------------------------------------===*/
3862
3863
3864
#ifdef GET_REGINFO_HEADER
3865
#undef GET_REGINFO_HEADER
3866
3867
#include "llvm/CodeGen/TargetRegisterInfo.h"
3868
3869
namespace llvm {
3870
3871
class X86FrameLowering;
3872
3873
struct X86GenRegisterInfo : public TargetRegisterInfo {
3874
  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3875
      unsigned PC = 0, unsigned HwMode = 0);
3876
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3877
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3878
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3879
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3880
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3881
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3882
  unsigned getNumRegPressureSets() const override;
3883
  const char *getRegPressureSetName(unsigned Idx) const override;
3884
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3885
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3886
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3887
  ArrayRef<const char *> getRegMaskNames() const override;
3888
  ArrayRef<const uint32_t *> getRegMasks() const override;
3889
  /// Devirtualized TargetFrameLowering.
3890
  static const X86FrameLowering *getFrameLowering(
3891
      const MachineFunction &MF);
3892
};
3893
3894
namespace X86 { // Register classes
3895
  extern const TargetRegisterClass GR8RegClass;
3896
  extern const TargetRegisterClass GRH8RegClass;
3897
  extern const TargetRegisterClass GR8_NOREXRegClass;
3898
  extern const TargetRegisterClass GR8_ABCD_HRegClass;
3899
  extern const TargetRegisterClass GR8_ABCD_LRegClass;
3900
  extern const TargetRegisterClass GRH16RegClass;
3901
  extern const TargetRegisterClass GR16RegClass;
3902
  extern const TargetRegisterClass GR16_NOREXRegClass;
3903
  extern const TargetRegisterClass VK1RegClass;
3904
  extern const TargetRegisterClass VK16RegClass;
3905
  extern const TargetRegisterClass VK2RegClass;
3906
  extern const TargetRegisterClass VK4RegClass;
3907
  extern const TargetRegisterClass VK8RegClass;
3908
  extern const TargetRegisterClass VK16WMRegClass;
3909
  extern const TargetRegisterClass VK1WMRegClass;
3910
  extern const TargetRegisterClass VK2WMRegClass;
3911
  extern const TargetRegisterClass VK4WMRegClass;
3912
  extern const TargetRegisterClass VK8WMRegClass;
3913
  extern const TargetRegisterClass SEGMENT_REGRegClass;
3914
  extern const TargetRegisterClass GR16_ABCDRegClass;
3915
  extern const TargetRegisterClass FPCCRRegClass;
3916
  extern const TargetRegisterClass FR32XRegClass;
3917
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
3918
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
3919
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
3920
  extern const TargetRegisterClass DEBUG_REGRegClass;
3921
  extern const TargetRegisterClass FR32RegClass;
3922
  extern const TargetRegisterClass GR32RegClass;
3923
  extern const TargetRegisterClass GR32_NOSPRegClass;
3924
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
3925
  extern const TargetRegisterClass GR32_NOREXRegClass;
3926
  extern const TargetRegisterClass VK32RegClass;
3927
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
3928
  extern const TargetRegisterClass RFP32RegClass;
3929
  extern const TargetRegisterClass VK32WMRegClass;
3930
  extern const TargetRegisterClass GR32_ABCDRegClass;
3931
  extern const TargetRegisterClass GR32_TCRegClass;
3932
  extern const TargetRegisterClass GR32_ADRegClass;
3933
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
3934
  extern const TargetRegisterClass CCRRegClass;
3935
  extern const TargetRegisterClass DFCCRRegClass;
3936
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
3937
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
3938
  extern const TargetRegisterClass RFP64RegClass;
3939
  extern const TargetRegisterClass FR64XRegClass;
3940
  extern const TargetRegisterClass GR64RegClass;
3941
  extern const TargetRegisterClass CONTROL_REGRegClass;
3942
  extern const TargetRegisterClass FR64RegClass;
3943
  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
3944
  extern const TargetRegisterClass GR64_NOSPRegClass;
3945
  extern const TargetRegisterClass GR64_NOREXRegClass;
3946
  extern const TargetRegisterClass GR64_TCRegClass;
3947
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
3948
  extern const TargetRegisterClass GR64_TCW64RegClass;
3949
  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
3950
  extern const TargetRegisterClass VK64RegClass;
3951
  extern const TargetRegisterClass VR64RegClass;
3952
  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
3953
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
3954
  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
3955
  extern const TargetRegisterClass VK64WMRegClass;
3956
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
3957
  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
3958
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
3959
  extern const TargetRegisterClass GR64_ABCDRegClass;
3960
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
3961
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
3962
  extern const TargetRegisterClass GR64_ADRegClass;
3963
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
3964
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClass;
3965
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
3966
  extern const TargetRegisterClass RSTRegClass;
3967
  extern const TargetRegisterClass RFP80RegClass;
3968
  extern const TargetRegisterClass VR128XRegClass;
3969
  extern const TargetRegisterClass VR128RegClass;
3970
  extern const TargetRegisterClass VR128HRegClass;
3971
  extern const TargetRegisterClass VR128LRegClass;
3972
  extern const TargetRegisterClass BNDRRegClass;
3973
  extern const TargetRegisterClass VR256XRegClass;
3974
  extern const TargetRegisterClass VR256RegClass;
3975
  extern const TargetRegisterClass VR256HRegClass;
3976
  extern const TargetRegisterClass VR256LRegClass;
3977
  extern const TargetRegisterClass VR512RegClass;
3978
  extern const TargetRegisterClass VR512_with_sub_xmm_in_FR32RegClass;
3979
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128HRegClass;
3980
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128LRegClass;
3981
} // end namespace X86
3982
3983
} // end namespace llvm
3984
3985
#endif // GET_REGINFO_HEADER
3986
3987
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3988
|*                                                                            *|
3989
|* Target Register and Register Classes Information                           *|
3990
|*                                                                            *|
3991
|* Automatically generated file, do not edit!                                 *|
3992
|*                                                                            *|
3993
\*===----------------------------------------------------------------------===*/
3994
3995
3996
#ifdef GET_REGINFO_TARGET_DESC
3997
#undef GET_REGINFO_TARGET_DESC
3998
3999
namespace llvm {
4000
4001
extern const MCRegisterClass X86MCRegisterClasses[];
4002
4003
static const MVT::SimpleValueType VTLists[] = {
4004
  /* 0 */ MVT::i8, MVT::Other,
4005
  /* 2 */ MVT::i16, MVT::Other,
4006
  /* 4 */ MVT::i32, MVT::Other,
4007
  /* 6 */ MVT::i64, MVT::Other,
4008
  /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
4009
  /* 12 */ MVT::f64, MVT::Other,
4010
  /* 14 */ MVT::f80, MVT::Other,
4011
  /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
4012
  /* 24 */ MVT::v1i1, MVT::Other,
4013
  /* 26 */ MVT::v2i1, MVT::Other,
4014
  /* 28 */ MVT::v4i1, MVT::Other,
4015
  /* 30 */ MVT::v8i1, MVT::Other,
4016
  /* 32 */ MVT::v16i1, MVT::Other,
4017
  /* 34 */ MVT::v32i1, MVT::Other,
4018
  /* 36 */ MVT::v64i1, MVT::Other,
4019
  /* 38 */ MVT::v2i64, MVT::Other,
4020
  /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
4021
  /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4022
  /* 54 */ MVT::x86mmx, MVT::Other,
4023
};
4024
4025
static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_xmm", "sub_ymm", "" };
4026
4027
4028
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4029
  LaneBitmask::getAll(),
4030
  LaneBitmask(0x00000001), // sub_8bit
4031
  LaneBitmask(0x00000002), // sub_8bit_hi
4032
  LaneBitmask(0x00000004), // sub_8bit_hi_phony
4033
  LaneBitmask(0x00000007), // sub_16bit
4034
  LaneBitmask(0x00000008), // sub_16bit_hi
4035
  LaneBitmask(0x0000000F), // sub_32bit
4036
  LaneBitmask(0x00000010), // sub_xmm
4037
  LaneBitmask(0x00000010), // sub_ymm
4038
 };
4039
4040
4041
4042
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4043
  // Mode = 0 (Default)
4044
  { 8, 8, 8, VTLists+0 },    // GR8
4045
  { 8, 8, 8, VTLists+0 },    // GRH8
4046
  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
4047
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
4048
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
4049
  { 16, 16, 16, VTLists+2 },    // GRH16
4050
  { 16, 16, 16, VTLists+2 },    // GR16
4051
  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
4052
  { 16, 16, 16, VTLists+24 },    // VK1
4053
  { 16, 16, 16, VTLists+32 },    // VK16
4054
  { 16, 16, 16, VTLists+26 },    // VK2
4055
  { 16, 16, 16, VTLists+28 },    // VK4
4056
  { 16, 16, 16, VTLists+30 },    // VK8
4057
  { 16, 16, 16, VTLists+32 },    // VK16WM
4058
  { 16, 16, 16, VTLists+24 },    // VK1WM
4059
  { 16, 16, 16, VTLists+26 },    // VK2WM
4060
  { 16, 16, 16, VTLists+28 },    // VK4WM
4061
  { 16, 16, 16, VTLists+30 },    // VK8WM
4062
  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
4063
  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
4064
  { 16, 16, 16, VTLists+2 },    // FPCCR
4065
  { 32, 32, 32, VTLists+10 },    // FR32X
4066
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
4067
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
4068
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4069
  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
4070
  { 32, 32, 32, VTLists+10 },    // FR32
4071
  { 32, 32, 32, VTLists+4 },    // GR32
4072
  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
4073
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4074
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
4075
  { 32, 32, 32, VTLists+34 },    // VK32
4076
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
4077
  { 32, 32, 32, VTLists+10 },    // RFP32
4078
  { 32, 32, 32, VTLists+34 },    // VK32WM
4079
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
4080
  { 32, 32, 32, VTLists+4 },    // GR32_TC
4081
  { 32, 32, 32, VTLists+4 },    // GR32_AD
4082
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4083
  { 32, 32, 32, VTLists+4 },    // CCR
4084
  { 32, 32, 32, VTLists+4 },    // DFCCR
4085
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4086
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
4087
  { 64, 64, 32, VTLists+12 },    // RFP64
4088
  { 64, 64, 64, VTLists+12 },    // FR64X
4089
  { 64, 64, 64, VTLists+6 },    // GR64
4090
  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
4091
  { 64, 64, 64, VTLists+12 },    // FR64
4092
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
4093
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
4094
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
4095
  { 64, 64, 64, VTLists+6 },    // GR64_TC
4096
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
4097
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
4098
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
4099
  { 64, 64, 64, VTLists+36 },    // VK64
4100
  { 64, 64, 64, VTLists+54 },    // VR64
4101
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
4102
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
4103
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
4104
  { 64, 64, 64, VTLists+36 },    // VK64WM
4105
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
4106
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4107
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_GR64_TC
4108
  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
4109
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
4110
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
4111
  { 64, 64, 64, VTLists+6 },    // GR64_AD
4112
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
4113
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP
4114
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
4115
  { 80, 80, 32, VTLists+8 },    // RST
4116
  { 80, 80, 32, VTLists+14 },    // RFP80
4117
  { 128, 128, 128, VTLists+16 },    // VR128X
4118
  { 128, 128, 128, VTLists+16 },    // VR128
4119
  { 128, 128, 128, VTLists+16 },    // VR128H
4120
  { 128, 128, 128, VTLists+16 },    // VR128L
4121
  { 128, 128, 128, VTLists+38 },    // BNDR
4122
  { 256, 256, 256, VTLists+40 },    // VR256X
4123
  { 256, 256, 256, VTLists+40 },    // VR256
4124
  { 256, 256, 256, VTLists+40 },    // VR256H
4125
  { 256, 256, 256, VTLists+40 },    // VR256L
4126
  { 512, 512, 512, VTLists+47 },    // VR512
4127
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_FR32
4128
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128H
4129
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128L
4130
};
4131
4132
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4133
4134
static const uint32_t GR8SubClassMask[] = {
4135
  0x0000001d, 0x00000000, 0x00000000, 
4136
  0x790800c0, 0xc6530239, 0x0000002d, // sub_8bit
4137
  0x00080000, 0x00000038, 0x0000000d, // sub_8bit_hi
4138
};
4139
4140
static const uint32_t GRH8SubClassMask[] = {
4141
  0x00000002, 0x00000000, 0x00000000, 
4142
};
4143
4144
static const uint32_t GR8_NOREXSubClassMask[] = {
4145
  0x0000001c, 0x00000000, 0x00000000, 
4146
  0x00080000, 0x00000038, 0x0000000d, // sub_8bit
4147
  0x00080000, 0x00000038, 0x0000000d, // sub_8bit_hi
4148
};
4149
4150
static const uint32_t GR8_ABCD_HSubClassMask[] = {
4151
  0x00000008, 0x00000000, 0x00000000, 
4152
  0x00080000, 0x00000038, 0x0000000d, // sub_8bit_hi
4153
};
4154
4155
static const uint32_t GR8_ABCD_LSubClassMask[] = {
4156
  0x00000010, 0x00000000, 0x00000000, 
4157
  0x00080000, 0x00000038, 0x0000000d, // sub_8bit
4158
};
4159
4160
static const uint32_t GRH16SubClassMask[] = {
4161
  0x00000020, 0x00000000, 0x00000000, 
4162
};
4163
4164
static const uint32_t GR16SubClassMask[] = {
4165
  0x000800c0, 0x00000000, 0x00000000, 
4166
  0x79000000, 0xc6530239, 0x0000002d, // sub_16bit
4167
};
4168
4169
static const uint32_t GR16_NOREXSubClassMask[] = {
4170
  0x00080080, 0x00000000, 0x00000000, 
4171
  0x60000000, 0x82400239, 0x0000002d, // sub_16bit
4172
};
4173
4174
static const uint32_t VK1SubClassMask[] = {
4175
  0x8003ff00, 0x10800004, 0x00000000, 
4176
};
4177
4178
static const uint32_t VK16SubClassMask[] = {
4179
  0x8003ff00, 0x10800004, 0x00000000, 
4180
};
4181
4182
static const uint32_t VK2SubClassMask[] = {
4183
  0x8003ff00, 0x10800004, 0x00000000, 
4184
};
4185
4186
static const uint32_t VK4SubClassMask[] = {
4187
  0x8003ff00, 0x10800004, 0x00000000, 
4188
};
4189
4190
static const uint32_t VK8SubClassMask[] = {
4191
  0x8003ff00, 0x10800004, 0x00000000, 
4192
};
4193
4194
static const uint32_t VK16WMSubClassMask[] = {
4195
  0x0003e000, 0x10000004, 0x00000000, 
4196
};
4197
4198
static const uint32_t VK1WMSubClassMask[] = {
4199
  0x0003e000, 0x10000004, 0x00000000, 
4200
};
4201
4202
static const uint32_t VK2WMSubClassMask[] = {
4203
  0x0003e000, 0x10000004, 0x00000000, 
4204
};
4205
4206
static const uint32_t VK4WMSubClassMask[] = {
4207
  0x0003e000, 0x10000004, 0x00000000, 
4208
};
4209
4210
static const uint32_t VK8WMSubClassMask[] = {
4211
  0x0003e000, 0x10000004, 0x00000000, 
4212
};
4213
4214
static const uint32_t SEGMENT_REGSubClassMask[] = {
4215
  0x00040000, 0x00000000, 0x00000000, 
4216
};
4217
4218
static const uint32_t GR16_ABCDSubClassMask[] = {
4219
  0x00080000, 0x00000000, 0x00000000, 
4220
  0x00000000, 0x00000038, 0x0000000d, // sub_16bit
4221
};
4222
4223
static const uint32_t FPCCRSubClassMask[] = {
4224
  0x00100000, 0x00000000, 0x00000000, 
4225
};
4226
4227
static const uint32_t FR32XSubClassMask[] = {
4228
  0x04200000, 0x00009000, 0x00001e00, 
4229
  0x00000000, 0x00000000, 0x003fc000, // sub_xmm
4230
};
4231
4232
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4233
  0x79c00000, 0x00000679, 0x00000070, 
4234
  0x00000000, 0xc6530200, 0x0000002d, // sub_32bit
4235
};
4236
4237
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
4238
  0x58800000, 0x00000439, 0x00000040, 
4239
  0x00000000, 0xc6530200, 0x0000002d, // sub_32bit
4240
};
4241
4242
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
4243
  0x79000000, 0x00000239, 0x00000020, 
4244
  0x00000000, 0xc6530200, 0x0000002d, // sub_32bit
4245
};
4246
4247
static const uint32_t DEBUG_REGSubClassMask[] = {
4248
  0x02000000, 0x00000000, 0x00000000, 
4249
};
4250
4251
static const uint32_t FR32SubClassMask[] = {
4252
  0x04000000, 0x00008000, 0x00001c00, 
4253
  0x00000000, 0x00000000, 0x003b8000, // sub_xmm
4254
};
4255
4256
static const uint32_t GR32SubClassMask[] = {
4257
  0x58000000, 0x00000039, 0x00000000, 
4258
  0x00000000, 0xc6530200, 0x0000002d, // sub_32bit
4259
};
4260
4261
static const uint32_t GR32_NOSPSubClassMask[] = {
4262
  0x10000000, 0x00000039, 0x00000000, 
4263
  0x00000000, 0xc6120200, 0x0000002d, // sub_32bit
4264
};
4265
4266
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4267
  0x60000000, 0x00000239, 0x00000020, 
4268
  0x00000000, 0x82400200, 0x0000002d, // sub_32bit
4269
};
4270
4271
static const uint32_t GR32_NOREXSubClassMask[] = {
4272
  0x40000000, 0x00000039, 0x00000000, 
4273
  0x00000000, 0x82400200, 0x0000002d, // sub_32bit
4274
};
4275
4276
static const uint32_t VK32SubClassMask[] = {
4277
  0x80000000, 0x10800004, 0x00000000, 
4278
};
4279
4280
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
4281
  0x00000000, 0x00000039, 0x00000000, 
4282
  0x00000000, 0x82000200, 0x0000002d, // sub_32bit
4283
};
4284
4285
static const uint32_t RFP32SubClassMask[] = {
4286
  0x00000000, 0x00000802, 0x00000100, 
4287
};
4288
4289
static const uint32_t VK32WMSubClassMask[] = {
4290
  0x00000000, 0x10000004, 0x00000000, 
4291
};
4292
4293
static const uint32_t GR32_ABCDSubClassMask[] = {
4294
  0x00000000, 0x00000038, 0x00000000, 
4295
  0x00000000, 0x00000000, 0x0000000d, // sub_32bit
4296
};
4297
4298
static const uint32_t GR32_TCSubClassMask[] = {
4299
  0x00000000, 0x00000030, 0x00000000, 
4300
  0x00000000, 0x00000000, 0x0000000c, // sub_32bit
4301
};
4302
4303
static const uint32_t GR32_ADSubClassMask[] = {
4304
  0x00000000, 0x00000020, 0x00000000, 
4305
  0x00000000, 0x00000000, 0x00000008, // sub_32bit
4306
};
4307
4308
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
4309
  0x00000000, 0x00000640, 0x00000070, 
4310
};
4311
4312
static const uint32_t CCRSubClassMask[] = {
4313
  0x00000000, 0x00000080, 0x00000000, 
4314
};
4315
4316
static const uint32_t DFCCRSubClassMask[] = {
4317
  0x00000000, 0x00000100, 0x00000000, 
4318
};
4319
4320
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
4321
  0x00000000, 0x00000200, 0x00000020, 
4322
};
4323
4324
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
4325
  0x00000000, 0x00000400, 0x00000040, 
4326
};
4327
4328
static const uint32_t RFP64SubClassMask[] = {
4329
  0x00000000, 0x00000800, 0x00000100, 
4330
};
4331
4332
static const uint32_t FR64XSubClassMask[] = {
4333
  0x00000000, 0x00009000, 0x00001e00, 
4334
  0x00000000, 0x00000000, 0x003fc000, // sub_xmm
4335
};
4336
4337
static const uint32_t GR64SubClassMask[] = {
4338
  0x00000000, 0xee7f2000, 0x0000007f, 
4339
};
4340
4341
static const uint32_t CONTROL_REGSubClassMask[] = {
4342
  0x00000000, 0x00004000, 0x00000000, 
4343
};
4344
4345
static const uint32_t FR64SubClassMask[] = {
4346
  0x00000000, 0x00008000, 0x00001c00, 
4347
  0x00000000, 0x00000000, 0x003b8000, // sub_xmm
4348
};
4349
4350
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
4351
  0x00000000, 0xc6530000, 0x0000002d, 
4352
};
4353
4354
static const uint32_t GR64_NOSPSubClassMask[] = {
4355
  0x00000000, 0xc6120000, 0x0000002d, 
4356
};
4357
4358
static const uint32_t GR64_NOREXSubClassMask[] = {
4359
  0x00000000, 0xa2440000, 0x0000007f, 
4360
};
4361
4362
static const uint32_t GR64_TCSubClassMask[] = {
4363
  0x00000000, 0xe8180000, 0x0000004e, 
4364
};
4365
4366
static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
4367
  0x00000000, 0xc0100000, 0x0000000c, 
4368
};
4369
4370
static const uint32_t GR64_TCW64SubClassMask[] = {
4371
  0x00000000, 0x4c200000, 0x0000004e, 
4372
};
4373
4374
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4375
  0x00000000, 0x82400000, 0x0000002d, 
4376
};
4377
4378
static const uint32_t VK64SubClassMask[] = {
4379
  0x00000000, 0x10800000, 0x00000000, 
4380
};
4381
4382
static const uint32_t VR64SubClassMask[] = {
4383
  0x00000000, 0x01000000, 0x00000000, 
4384
};
4385
4386
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
4387
  0x00000000, 0x82000000, 0x0000002d, 
4388
};
4389
4390
static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4391
  0x00000000, 0x44000000, 0x0000000c, 
4392
};
4393
4394
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
4395
  0x00000000, 0x48000000, 0x0000004e, 
4396
};
4397
4398
static const uint32_t VK64WMSubClassMask[] = {
4399
  0x00000000, 0x10000000, 0x00000000, 
4400
};
4401
4402
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
4403
  0x00000000, 0xa0000000, 0x0000004e, 
4404
};
4405
4406
static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4407
  0x00000000, 0x40000000, 0x0000000c, 
4408
};
4409
4410
static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = {
4411
  0x00000000, 0x80000000, 0x0000000c, 
4412
};
4413
4414
static const uint32_t GR64_ABCDSubClassMask[] = {
4415
  0x00000000, 0x00000000, 0x0000000d, 
4416
};
4417
4418
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
4419
  0x00000000, 0x00000000, 0x0000004e, 
4420
};
4421
4422
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
4423
  0x00000000, 0x00000000, 0x0000000c, 
4424
};
4425
4426
static const uint32_t GR64_ADSubClassMask[] = {
4427
  0x00000000, 0x00000000, 0x00000008, 
4428
};
4429
4430
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4431
  0x00000000, 0x00000000, 0x00000070, 
4432
};
4433
4434
static const uint32_t GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4435
  0x00000000, 0x00000000, 0x00000020, 
4436
};
4437
4438
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
4439
  0x00000000, 0x00000000, 0x00000040, 
4440
};
4441
4442
static const uint32_t RSTSubClassMask[] = {
4443
  0x00000000, 0x00000000, 0x00000080, 
4444
};
4445
4446
static const uint32_t RFP80SubClassMask[] = {
4447
  0x00000000, 0x00000000, 0x00000100, 
4448
};
4449
4450
static const uint32_t VR128XSubClassMask[] = {
4451
  0x00000000, 0x00000000, 0x00001e00, 
4452
  0x00000000, 0x00000000, 0x003fc000, // sub_xmm
4453
};
4454
4455
static const uint32_t VR128SubClassMask[] = {
4456
  0x00000000, 0x00000000, 0x00001c00, 
4457
  0x00000000, 0x00000000, 0x003b8000, // sub_xmm
4458
};
4459
4460
static const uint32_t VR128HSubClassMask[] = {
4461
  0x00000000, 0x00000000, 0x00000800, 
4462
  0x00000000, 0x00000000, 0x00110000, // sub_xmm
4463
};
4464
4465
static const uint32_t VR128LSubClassMask[] = {
4466
  0x00000000, 0x00000000, 0x00001000, 
4467
  0x00000000, 0x00000000, 0x00220000, // sub_xmm
4468
};
4469
4470
static const uint32_t BNDRSubClassMask[] = {
4471
  0x00000000, 0x00000000, 0x00002000, 
4472
};
4473
4474
static const uint32_t VR256XSubClassMask[] = {
4475
  0x00000000, 0x00000000, 0x0003c000, 
4476
  0x00000000, 0x00000000, 0x003c0000, // sub_ymm
4477
};
4478
4479
static const uint32_t VR256SubClassMask[] = {
4480
  0x00000000, 0x00000000, 0x00038000, 
4481
  0x00000000, 0x00000000, 0x00380000, // sub_ymm
4482
};
4483
4484
static const uint32_t VR256HSubClassMask[] = {
4485
  0x00000000, 0x00000000, 0x00010000, 
4486
  0x00000000, 0x00000000, 0x00100000, // sub_ymm
4487
};
4488
4489
static const uint32_t VR256LSubClassMask[] = {
4490
  0x00000000, 0x00000000, 0x00020000, 
4491
  0x00000000, 0x00000000, 0x00200000, // sub_ymm
4492
};
4493
4494
static const uint32_t VR512SubClassMask[] = {
4495
  0x00000000, 0x00000000, 0x003c0000, 
4496
};
4497
4498
static const uint32_t VR512_with_sub_xmm_in_FR32SubClassMask[] = {
4499
  0x00000000, 0x00000000, 0x00380000, 
4500
};
4501
4502
static const uint32_t VR512_with_sub_xmm_in_VR128HSubClassMask[] = {
4503
  0x00000000, 0x00000000, 0x00100000, 
4504
};
4505
4506
static const uint32_t VR512_with_sub_xmm_in_VR128LSubClassMask[] = {
4507
  0x00000000, 0x00000000, 0x00200000, 
4508
};
4509
4510
static const uint16_t SuperRegIdxSeqs[] = {
4511
  /* 0 */ 1, 0,
4512
  /* 2 */ 1, 2, 0,
4513
  /* 5 */ 4, 0,
4514
  /* 7 */ 6, 0,
4515
  /* 9 */ 7, 0,
4516
  /* 11 */ 8, 0,
4517
};
4518
4519
static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
4520
  &X86::GR8RegClass,
4521
  nullptr
4522
};
4523
4524
static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
4525
  &X86::GR8RegClass,
4526
  &X86::GR8_NOREXRegClass,
4527
  nullptr
4528
};
4529
4530
static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
4531
  &X86::GR8RegClass,
4532
  &X86::GR8_NOREXRegClass,
4533
  nullptr
4534
};
4535
4536
static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
4537
  &X86::GR16RegClass,
4538
  nullptr
4539
};
4540
4541
static const TargetRegisterClass *const VK1Superclasses[] = {
4542
  &X86::VK16RegClass,
4543
  &X86::VK2RegClass,
4544
  &X86::VK4RegClass,
4545
  &X86::VK8RegClass,
4546
  nullptr
4547
};
4548
4549
static const TargetRegisterClass *const VK16Superclasses[] = {
4550
  &X86::VK1RegClass,
4551
  &X86::VK2RegClass,
4552
  &X86::VK4RegClass,
4553
  &X86::VK8RegClass,
4554
  nullptr
4555
};
4556
4557
static const TargetRegisterClass *const VK2Superclasses[] = {
4558
  &X86::VK1RegClass,
4559
  &X86::VK16RegClass,
4560
  &X86::VK4RegClass,
4561
  &X86::VK8RegClass,
4562
  nullptr
4563
};
4564
4565
static const TargetRegisterClass *const VK4Superclasses[] = {
4566
  &X86::VK1RegClass,
4567
  &X86::VK16RegClass,
4568
  &X86::VK2RegClass,
4569
  &X86::VK8RegClass,
4570
  nullptr
4571
};
4572
4573
static const TargetRegisterClass *const VK8Superclasses[] = {
4574
  &X86::VK1RegClass,
4575
  &X86::VK16RegClass,
4576
  &X86::VK2RegClass,
4577
  &X86::VK4RegClass,
4578
  nullptr
4579
};
4580
4581
static const TargetRegisterClass *const VK16WMSuperclasses[] = {
4582
  &X86::VK1RegClass,
4583
  &X86::VK16RegClass,
4584
  &X86::VK2RegClass,
4585
  &X86::VK4RegClass,
4586
  &X86::VK8RegClass,
4587
  &X86::VK1WMRegClass,
4588
  &X86::VK2WMRegClass,
4589
  &X86::VK4WMRegClass,
4590
  &X86::VK8WMRegClass,
4591
  nullptr
4592
};
4593
4594
static const TargetRegisterClass *const VK1WMSuperclasses[] = {
4595
  &X86::VK1RegClass,
4596
  &X86::VK16RegClass,
4597
  &X86::VK2RegClass,
4598
  &X86::VK4RegClass,
4599
  &X86::VK8RegClass,
4600
  &X86::VK16WMRegClass,
4601
  &X86::VK2WMRegClass,
4602
  &X86::VK4WMRegClass,
4603
  &X86::VK8WMRegClass,
4604
  nullptr
4605
};
4606
4607
static const TargetRegisterClass *const VK2WMSuperclasses[] = {
4608
  &X86::VK1RegClass,
4609
  &X86::VK16RegClass,
4610
  &X86::VK2RegClass,
4611
  &X86::VK4RegClass,
4612
  &X86::VK8RegClass,
4613
  &X86::VK16WMRegClass,
4614
  &X86::VK1WMRegClass,
4615
  &X86::VK4WMRegClass,
4616
  &X86::VK8WMRegClass,
4617
  nullptr
4618
};
4619
4620
static const TargetRegisterClass *const VK4WMSuperclasses[] = {
4621
  &X86::VK1RegClass,
4622
  &X86::VK16RegClass,
4623
  &X86::VK2RegClass,
4624
  &X86::VK4RegClass,
4625
  &X86::VK8RegClass,
4626
  &X86::VK16WMRegClass,
4627
  &X86::VK1WMRegClass,
4628
  &X86::VK2WMRegClass,
4629
  &X86::VK8WMRegClass,
4630
  nullptr
4631
};
4632
4633
static const TargetRegisterClass *const VK8WMSuperclasses[] = {
4634
  &X86::VK1RegClass,
4635
  &X86::VK16RegClass,
4636
  &X86::VK2RegClass,
4637
  &X86::VK4RegClass,
4638
  &X86::VK8RegClass,
4639
  &X86::VK16WMRegClass,
4640
  &X86::VK1WMRegClass,
4641
  &X86::VK2WMRegClass,
4642
  &X86::VK4WMRegClass,
4643
  nullptr
4644
};
4645
4646
static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
4647
  &X86::GR16RegClass,
4648
  &X86::GR16_NOREXRegClass,
4649
  nullptr
4650
};
4651
4652
static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
4653
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4654
  nullptr
4655
};
4656
4657
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
4658
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4659
  nullptr
4660
};
4661
4662
static const TargetRegisterClass *const FR32Superclasses[] = {
4663
  &X86::FR32XRegClass,
4664
  nullptr
4665
};
4666
4667
static const TargetRegisterClass *const GR32Superclasses[] = {
4668
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4669
  &X86::LOW32_ADDR_ACCESSRegClass,
4670
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4671
  nullptr
4672
};
4673
4674
static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
4675
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4676
  &X86::LOW32_ADDR_ACCESSRegClass,
4677
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4678
  &X86::GR32RegClass,
4679
  nullptr
4680
};
4681
4682
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
4683
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4684
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4685
  nullptr
4686
};
4687
4688
static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
4689
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4690
  &X86::LOW32_ADDR_ACCESSRegClass,
4691
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4692
  &X86::GR32RegClass,
4693
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4694
  nullptr
4695
};
4696
4697
static const TargetRegisterClass *const VK32Superclasses[] = {
4698
  &X86::VK1RegClass,
4699
  &X86::VK16RegClass,
4700
  &X86::VK2RegClass,
4701
  &X86::VK4RegClass,
4702
  &X86::VK8RegClass,
4703
  nullptr
4704
};
4705
4706
static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
4707
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4708
  &X86::LOW32_ADDR_ACCESSRegClass,
4709
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4710
  &X86::GR32RegClass,
4711
  &X86::GR32_NOSPRegClass,
4712
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4713
  &X86::GR32_NOREXRegClass,
4714
  nullptr
4715
};
4716
4717
static const TargetRegisterClass *const VK32WMSuperclasses[] = {
4718
  &X86::VK1RegClass,
4719
  &X86::VK16RegClass,
4720
  &X86::VK2RegClass,
4721
  &X86::VK4RegClass,
4722
  &X86::VK8RegClass,
4723
  &X86::VK16WMRegClass,
4724
  &X86::VK1WMRegClass,
4725
  &X86::VK2WMRegClass,
4726
  &X86::VK4WMRegClass,
4727
  &X86::VK8WMRegClass,
4728
  &X86::VK32RegClass,
4729
  nullptr
4730
};
4731
4732
static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
4733
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4734
  &X86::LOW32_ADDR_ACCESSRegClass,
4735
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4736
  &X86::GR32RegClass,
4737
  &X86::GR32_NOSPRegClass,
4738
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4739
  &X86::GR32_NOREXRegClass,
4740
  &X86::GR32_NOREX_NOSPRegClass,
4741
  nullptr
4742
};
4743
4744
static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
4745
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4746
  &X86::LOW32_ADDR_ACCESSRegClass,
4747
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4748
  &X86::GR32RegClass,
4749
  &X86::GR32_NOSPRegClass,
4750
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4751
  &X86::GR32_NOREXRegClass,
4752
  &X86::GR32_NOREX_NOSPRegClass,
4753
  &X86::GR32_ABCDRegClass,
4754
  nullptr
4755
};
4756
4757
static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
4758
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4759
  &X86::LOW32_ADDR_ACCESSRegClass,
4760
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4761
  &X86::GR32RegClass,
4762
  &X86::GR32_NOSPRegClass,
4763
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4764
  &X86::GR32_NOREXRegClass,
4765
  &X86::GR32_NOREX_NOSPRegClass,
4766
  &X86::GR32_ABCDRegClass,
4767
  &X86::GR32_TCRegClass,
4768
  nullptr
4769
};
4770
4771
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
4772
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4773
  nullptr
4774
};
4775
4776
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
4777
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4778
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
4779
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
4780
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4781
  nullptr
4782
};
4783
4784
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
4785
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4786
  &X86::LOW32_ADDR_ACCESSRegClass,
4787
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4788
  nullptr
4789
};
4790
4791
static const TargetRegisterClass *const RFP64Superclasses[] = {
4792
  &X86::RFP32RegClass,
4793
  nullptr
4794
};
4795
4796
static const TargetRegisterClass *const FR64XSuperclasses[] = {
4797
  &X86::FR32XRegClass,
4798
  nullptr
4799
};
4800
4801
static const TargetRegisterClass *const FR64Superclasses[] = {
4802
  &X86::FR32XRegClass,
4803
  &X86::FR32RegClass,
4804
  &X86::FR64XRegClass,
4805
  nullptr
4806
};
4807
4808
static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
4809
  &X86::GR64RegClass,
4810
  nullptr
4811
};
4812
4813
static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
4814
  &X86::GR64RegClass,
4815
  &X86::GR64_with_sub_8bitRegClass,
4816
  nullptr
4817
};
4818
4819
static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
4820
  &X86::GR64RegClass,
4821
  nullptr
4822
};
4823
4824
static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
4825
  &X86::GR64RegClass,
4826
  nullptr
4827
};
4828
4829
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
4830
  &X86::GR64RegClass,
4831
  &X86::GR64_with_sub_8bitRegClass,
4832
  &X86::GR64_NOSPRegClass,
4833
  &X86::GR64_TCRegClass,
4834
  nullptr
4835
};
4836
4837
static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
4838
  &X86::GR64RegClass,
4839
  nullptr
4840
};
4841
4842
static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
4843
  &X86::GR64RegClass,
4844
  &X86::GR64_with_sub_8bitRegClass,
4845
  &X86::GR64_NOREXRegClass,
4846
  nullptr
4847
};
4848
4849
static const TargetRegisterClass *const VK64Superclasses[] = {
4850
  &X86::VK1RegClass,
4851
  &X86::VK16RegClass,
4852
  &X86::VK2RegClass,
4853
  &X86::VK4RegClass,
4854
  &X86::VK8RegClass,
4855
  &X86::VK32RegClass,
4856
  nullptr
4857
};
4858
4859
static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
4860
  &X86::GR64RegClass,
4861
  &X86::GR64_with_sub_8bitRegClass,
4862
  &X86::GR64_NOSPRegClass,
4863
  &X86::GR64_NOREXRegClass,
4864
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4865
  nullptr
4866
};
4867
4868
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
4869
  &X86::GR64RegClass,
4870
  &X86::GR64_with_sub_8bitRegClass,
4871
  &X86::GR64_NOSPRegClass,
4872
  &X86::GR64_TCW64RegClass,
4873
  nullptr
4874
};
4875
4876
static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
4877
  &X86::GR64RegClass,
4878
  &X86::GR64_TCRegClass,
4879
  &X86::GR64_TCW64RegClass,
4880
  nullptr
4881
};
4882
4883
static const TargetRegisterClass *const VK64WMSuperclasses[] = {
4884
  &X86::VK1RegClass,
4885
  &X86::VK16RegClass,
4886
  &X86::VK2RegClass,
4887
  &X86::VK4RegClass,
4888
  &X86::VK8RegClass,
4889
  &X86::VK16WMRegClass,
4890
  &X86::VK1WMRegClass,
4891
  &X86::VK2WMRegClass,
4892
  &X86::VK4WMRegClass,
4893
  &X86::VK8WMRegClass,
4894
  &X86::VK32RegClass,
4895
  &X86::VK32WMRegClass,
4896
  &X86::VK64RegClass,
4897
  nullptr
4898
};
4899
4900
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
4901
  &X86::GR64RegClass,
4902
  &X86::GR64_NOREXRegClass,
4903
  &X86::GR64_TCRegClass,
4904
  nullptr
4905
};
4906
4907
static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
4908
  &X86::GR64RegClass,
4909
  &X86::GR64_with_sub_8bitRegClass,
4910
  &X86::GR64_NOSPRegClass,
4911
  &X86::GR64_TCRegClass,
4912
  &X86::GR64_NOSP_and_GR64_TCRegClass,
4913
  &X86::GR64_TCW64RegClass,
4914
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
4915
  &X86::GR64_TC_and_GR64_TCW64RegClass,
4916
  nullptr
4917
};
4918
4919
static const TargetRegisterClass *const GR64_NOREX_NOSP_and_GR64_TCSuperclasses[] = {
4920
  &X86::GR64RegClass,
4921
  &X86::GR64_with_sub_8bitRegClass,
4922
  &X86::GR64_NOSPRegClass,
4923
  &X86::GR64_NOREXRegClass,
4924
  &X86::GR64_TCRegClass,
4925
  &X86::GR64_NOSP_and_GR64_TCRegClass,
4926
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4927
  &X86::GR64_NOREX_NOSPRegClass,
4928
  &X86::GR64_NOREX_and_GR64_TCRegClass,
4929
  nullptr
4930
};
4931
4932
static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
4933
  &X86::GR64RegClass,
4934
  &X86::GR64_with_sub_8bitRegClass,
4935
  &X86::GR64_NOSPRegClass,
4936
  &X86::GR64_NOREXRegClass,
4937
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4938
  &X86::GR64_NOREX_NOSPRegClass,
4939
  nullptr
4940
};
4941
4942
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
4943
  &X86::GR64RegClass,
4944
  &X86::GR64_NOREXRegClass,
4945
  &X86::GR64_TCRegClass,
4946
  &X86::GR64_TCW64RegClass,
4947
  &X86::GR64_TC_and_GR64_TCW64RegClass,
4948
  &X86::GR64_NOREX_and_GR64_TCRegClass,
4949
  nullptr
4950
};
4951
4952
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
4953
  &X86::GR64RegClass,
4954
  &X86::GR64_with_sub_8bitRegClass,
4955
  &X86::GR64_NOSPRegClass,
4956
  &X86::GR64_NOREXRegClass,
4957
  &X86::GR64_TCRegClass,
4958
  &X86::GR64_NOSP_and_GR64_TCRegClass,
4959
  &X86::GR64_TCW64RegClass,
4960
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4961
  &X86::GR64_NOREX_NOSPRegClass,
4962
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
4963
  &X86::GR64_TC_and_GR64_TCW64RegClass,
4964
  &X86::GR64_NOREX_and_GR64_TCRegClass,
4965
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
4966
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
4967
  &X86::GR64_ABCDRegClass,
4968
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
4969
  nullptr
4970
};
4971
4972
static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
4973
  &X86::GR64RegClass,
4974
  &X86::GR64_with_sub_8bitRegClass,
4975
  &X86::GR64_NOSPRegClass,
4976
  &X86::GR64_NOREXRegClass,
4977
  &X86::GR64_TCRegClass,
4978
  &X86::GR64_NOSP_and_GR64_TCRegClass,
4979
  &X86::GR64_TCW64RegClass,
4980
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
4981
  &X86::GR64_NOREX_NOSPRegClass,
4982
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
4983
  &X86::GR64_TC_and_GR64_TCW64RegClass,
4984
  &X86::GR64_NOREX_and_GR64_TCRegClass,
4985
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
4986
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
4987
  &X86::GR64_ABCDRegClass,
4988
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
4989
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
4990
  nullptr
4991
};
4992
4993
static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
4994
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
4995
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
4996
  &X86::GR64RegClass,
4997
  &X86::GR64_NOREXRegClass,
4998
  nullptr
4999
};
5000
5001
static const TargetRegisterClass *const GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
5002
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5003
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5004
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5005
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5006
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
5007
  &X86::GR64RegClass,
5008
  &X86::GR64_with_sub_8bitRegClass,
5009
  &X86::GR64_NOSPRegClass,
5010
  &X86::GR64_NOREXRegClass,
5011
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
5012
  &X86::GR64_NOREX_NOSPRegClass,
5013
  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
5014
  nullptr
5015
};
5016
5017
static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
5018
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5019
  &X86::LOW32_ADDR_ACCESSRegClass,
5020
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5021
  &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
5022
  &X86::GR64RegClass,
5023
  &X86::GR64_NOREXRegClass,
5024
  &X86::GR64_TCRegClass,
5025
  &X86::GR64_TCW64RegClass,
5026
  &X86::GR64_TC_and_GR64_TCW64RegClass,
5027
  &X86::GR64_NOREX_and_GR64_TCRegClass,
5028
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
5029
  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
5030
  nullptr
5031
};
5032
5033
static const TargetRegisterClass *const RFP80Superclasses[] = {
5034
  &X86::RFP32RegClass,
5035
  &X86::RFP64RegClass,
5036
  nullptr
5037
};
5038
5039
static const TargetRegisterClass *const VR128XSuperclasses[] = {
5040
  &X86::FR32XRegClass,
5041
  &X86::FR64XRegClass,
5042
  nullptr
5043
};
5044
5045
static const TargetRegisterClass *const VR128Superclasses[] = {
5046
  &X86::FR32XRegClass,
5047
  &X86::FR32RegClass,
5048
  &X86::FR64XRegClass,
5049
  &X86::FR64RegClass,
5050
  &X86::VR128XRegClass,
5051
  nullptr
5052
};
5053
5054
static const TargetRegisterClass *const VR128HSuperclasses[] = {
5055
  &X86::FR32XRegClass,
5056
  &X86::FR32RegClass,
5057
  &X86::FR64XRegClass,
5058
  &X86::FR64RegClass,
5059
  &X86::VR128XRegClass,
5060
  &X86::VR128RegClass,
5061
  nullptr
5062
};
5063
5064
static const TargetRegisterClass *const VR128LSuperclasses[] = {
5065
  &X86::FR32XRegClass,
5066
  &X86::FR32RegClass,
5067
  &X86::FR64XRegClass,
5068
  &X86::FR64RegClass,
5069
  &X86::VR128XRegClass,
5070
  &X86::VR128RegClass,
5071
  nullptr
5072
};
5073
5074
static const TargetRegisterClass *const VR256Superclasses[] = {
5075
  &X86::VR256XRegClass,
5076
  nullptr
5077
};
5078
5079
static const TargetRegisterClass *const VR256HSuperclasses[] = {
5080
  &X86::VR256XRegClass,
5081
  &X86::VR256RegClass,
5082
  nullptr
5083
};
5084
5085
static const TargetRegisterClass *const VR256LSuperclasses[] = {
5086
  &X86::VR256XRegClass,
5087
  &X86::VR256RegClass,
5088
  nullptr
5089
};
5090
5091
static const TargetRegisterClass *const VR512_with_sub_xmm_in_FR32Superclasses[] = {
5092
  &X86::VR512RegClass,
5093
  nullptr
5094
};
5095
5096
static const TargetRegisterClass *const VR512_with_sub_xmm_in_VR128HSuperclasses[] = {
5097
  &X86::VR512RegClass,
5098
  &X86::VR512_with_sub_xmm_in_FR32RegClass,
5099
  nullptr
5100
};
5101
5102
static const TargetRegisterClass *const VR512_with_sub_xmm_in_VR128LSuperclasses[] = {
5103
  &X86::VR512RegClass,
5104
  &X86::VR512_with_sub_xmm_in_FR32RegClass,
5105
  nullptr
5106
};
5107
5108
5109
33.7k
static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
5110
33.7k
    return MF.getSubtarget<X86Subtarget>().is64Bit();
5111
33.7k
  }
5112
5113
33.7k
static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
5114
33.7k
  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
5115
33.7k
  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
5116
33.7k
  const ArrayRef<MCPhysReg> Order[] = {
5117
33.7k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5118
33.7k
    makeArrayRef(AltOrder1)
5119
33.7k
  };
5120
33.7k
  const unsigned Select = GR8AltOrderSelect(MF);
5121
33.7k
  assert(Select < 2);
5122
33.7k
  return Order[Select];
5123
33.7k
}
5124
5125
5.12k
static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
5126
5.12k
    return MF.getSubtarget<X86Subtarget>().is64Bit();
5127
5.12k
  }
5128
5129
5.12k
static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
5130
5.12k
  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
5131
5.12k
  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
5132
5.12k
  const ArrayRef<MCPhysReg> Order[] = {
5133
5.12k
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5134
5.12k
    makeArrayRef(AltOrder1)
5135
5.12k
  };
5136
5.12k
  const unsigned Select = GR8_NOREXAltOrderSelect(MF);
5137
5.12k
  assert(Select < 2);
5138
5.12k
  return Order[Select];
5139
5.12k
}
5140
5141
namespace X86 {   // Register class instances
5142
  extern const TargetRegisterClass GR8RegClass = {
5143
    &X86MCRegisterClasses[GR8RegClassID],
5144
    GR8SubClassMask,
5145
    SuperRegIdxSeqs + 2,
5146
    LaneBitmask(0x00000001),
5147
    0,
5148
    false, /* HasDisjunctSubRegs */
5149
    false, /* CoveredBySubRegs */
5150
    NullRegClasses,
5151
    GR8GetRawAllocationOrder
5152
  };
5153
5154
  extern const TargetRegisterClass GRH8RegClass = {
5155
    &X86MCRegisterClasses[GRH8RegClassID],
5156
    GRH8SubClassMask,
5157
    SuperRegIdxSeqs + 1,
5158
    LaneBitmask(0x00000001),
5159
    0,
5160
    false, /* HasDisjunctSubRegs */
5161
    false, /* CoveredBySubRegs */
5162
    NullRegClasses,
5163
    nullptr
5164
  };
5165
5166
  extern const TargetRegisterClass GR8_NOREXRegClass = {
5167
    &X86MCRegisterClasses[GR8_NOREXRegClassID],
5168
    GR8_NOREXSubClassMask,
5169
    SuperRegIdxSeqs + 2,
5170
    LaneBitmask(0x00000001),
5171
    0,
5172
    false, /* HasDisjunctSubRegs */
5173
    false, /* CoveredBySubRegs */
5174
    GR8_NOREXSuperclasses,
5175
    GR8_NOREXGetRawAllocationOrder
5176
  };
5177
5178
  extern const TargetRegisterClass GR8_ABCD_HRegClass = {
5179
    &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
5180
    GR8_ABCD_HSubClassMask,
5181
    SuperRegIdxSeqs + 3,
5182
    LaneBitmask(0x00000001),
5183
    0,
5184
    false, /* HasDisjunctSubRegs */
5185
    false, /* CoveredBySubRegs */
5186
    GR8_ABCD_HSuperclasses,
5187
    nullptr
5188
  };
5189
5190
  extern const TargetRegisterClass GR8_ABCD_LRegClass = {
5191
    &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
5192
    GR8_ABCD_LSubClassMask,
5193
    SuperRegIdxSeqs + 0,
5194
    LaneBitmask(0x00000001),
5195
    0,
5196
    false, /* HasDisjunctSubRegs */
5197
    false, /* CoveredBySubRegs */
5198
    GR8_ABCD_LSuperclasses,
5199
    nullptr
5200
  };
5201
5202
  extern const TargetRegisterClass GRH16RegClass = {
5203
    &X86MCRegisterClasses[GRH16RegClassID],
5204
    GRH16SubClassMask,
5205
    SuperRegIdxSeqs + 1,
5206
    LaneBitmask(0x00000001),
5207
    0,
5208
    false, /* HasDisjunctSubRegs */
5209
    false, /* CoveredBySubRegs */
5210
    NullRegClasses,
5211
    nullptr
5212
  };
5213
5214
  extern const TargetRegisterClass GR16RegClass = {
5215
    &X86MCRegisterClasses[GR16RegClassID],
5216
    GR16SubClassMask,
5217
    SuperRegIdxSeqs + 5,
5218
    LaneBitmask(0x00000003),
5219
    0,
5220
    true, /* HasDisjunctSubRegs */
5221
    true, /* CoveredBySubRegs */
5222
    NullRegClasses,
5223
    nullptr
5224
  };
5225
5226
  extern const TargetRegisterClass GR16_NOREXRegClass = {
5227
    &X86MCRegisterClasses[GR16_NOREXRegClassID],
5228
    GR16_NOREXSubClassMask,
5229
    SuperRegIdxSeqs + 5,
5230
    LaneBitmask(0x00000003),
5231
    0,
5232
    true, /* HasDisjunctSubRegs */
5233
    true, /* CoveredBySubRegs */
5234
    GR16_NOREXSuperclasses,
5235
    nullptr
5236
  };
5237
5238
  extern const TargetRegisterClass VK1RegClass = {
5239
    &X86MCRegisterClasses[VK1RegClassID],
5240
    VK1SubClassMask,
5241
    SuperRegIdxSeqs + 1,
5242
    LaneBitmask(0x00000001),
5243
    0,
5244
    false, /* HasDisjunctSubRegs */
5245
    false, /* CoveredBySubRegs */
5246
    VK1Superclasses,
5247
    nullptr
5248
  };
5249
5250
  extern const TargetRegisterClass VK16RegClass = {
5251
    &X86MCRegisterClasses[VK16RegClassID],
5252
    VK16SubClassMask,
5253
    SuperRegIdxSeqs + 1,
5254
    LaneBitmask(0x00000001),
5255
    0,
5256
    false, /* HasDisjunctSubRegs */
5257
    false, /* CoveredBySubRegs */
5258
    VK16Superclasses,
5259
    nullptr
5260
  };
5261
5262
  extern const TargetRegisterClass VK2RegClass = {
5263
    &X86MCRegisterClasses[VK2RegClassID],
5264
    VK2SubClassMask,
5265
    SuperRegIdxSeqs + 1,
5266
    LaneBitmask(0x00000001),
5267
    0,
5268
    false, /* HasDisjunctSubRegs */
5269
    false, /* CoveredBySubRegs */
5270
    VK2Superclasses,
5271
    nullptr
5272
  };
5273
5274
  extern const TargetRegisterClass VK4RegClass = {
5275
    &X86MCRegisterClasses[VK4RegClassID],
5276
    VK4SubClassMask,
5277
    SuperRegIdxSeqs + 1,
5278
    LaneBitmask(0x00000001),
5279
    0,
5280
    false, /* HasDisjunctSubRegs */
5281
    false, /* CoveredBySubRegs */
5282
    VK4Superclasses,
5283
    nullptr
5284
  };
5285
5286
  extern const TargetRegisterClass VK8RegClass = {
5287
    &X86MCRegisterClasses[VK8RegClassID],
5288
    VK8SubClassMask,
5289
    SuperRegIdxSeqs + 1,
5290
    LaneBitmask(0x00000001),
5291
    0,
5292
    false, /* HasDisjunctSubRegs */
5293
    false, /* CoveredBySubRegs */
5294
    VK8Superclasses,
5295
    nullptr
5296
  };
5297
5298
  extern const TargetRegisterClass VK16WMRegClass = {
5299
    &X86MCRegisterClasses[VK16WMRegClassID],
5300
    VK16WMSubClassMask,
5301
    SuperRegIdxSeqs + 1,
5302
    LaneBitmask(0x00000001),
5303
    0,
5304
    false, /* HasDisjunctSubRegs */
5305
    false, /* CoveredBySubRegs */
5306
    VK16WMSuperclasses,
5307
    nullptr
5308
  };
5309
5310
  extern const TargetRegisterClass VK1WMRegClass = {
5311
    &X86MCRegisterClasses[VK1WMRegClassID],
5312
    VK1WMSubClassMask,
5313
    SuperRegIdxSeqs + 1,
5314
    LaneBitmask(0x00000001),
5315
    0,
5316
    false, /* HasDisjunctSubRegs */
5317
    false, /* CoveredBySubRegs */
5318
    VK1WMSuperclasses,
5319
    nullptr
5320
  };
5321
5322
  extern const TargetRegisterClass VK2WMRegClass = {
5323
    &X86MCRegisterClasses[VK2WMRegClassID],
5324
    VK2WMSubClassMask,
5325
    SuperRegIdxSeqs + 1,
5326
    LaneBitmask(0x00000001),
5327
    0,
5328
    false, /* HasDisjunctSubRegs */
5329
    false, /* CoveredBySubRegs */
5330
    VK2WMSuperclasses,
5331
    nullptr
5332
  };
5333
5334
  extern const TargetRegisterClass VK4WMRegClass = {
5335
    &X86MCRegisterClasses[VK4WMRegClassID],
5336
    VK4WMSubClassMask,
5337
    SuperRegIdxSeqs + 1,
5338
    LaneBitmask(0x00000001),
5339
    0,
5340
    false, /* HasDisjunctSubRegs */
5341
    false, /* CoveredBySubRegs */
5342
    VK4WMSuperclasses,
5343
    nullptr
5344
  };
5345
5346
  extern const TargetRegisterClass VK8WMRegClass = {
5347
    &X86MCRegisterClasses[VK8WMRegClassID],
5348
    VK8WMSubClassMask,
5349
    SuperRegIdxSeqs + 1,
5350
    LaneBitmask(0x00000001),
5351
    0,
5352
    false, /* HasDisjunctSubRegs */
5353
    false, /* CoveredBySubRegs */
5354
    VK8WMSuperclasses,
5355
    nullptr
5356
  };
5357
5358
  extern const TargetRegisterClass SEGMENT_REGRegClass = {
5359
    &X86MCRegisterClasses[SEGMENT_REGRegClassID],
5360
    SEGMENT_REGSubClassMask,
5361
    SuperRegIdxSeqs + 1,
5362
    LaneBitmask(0x00000001),
5363
    0,
5364
    false, /* HasDisjunctSubRegs */
5365
    false, /* CoveredBySubRegs */
5366
    NullRegClasses,
5367
    nullptr
5368
  };
5369
5370
  extern const TargetRegisterClass GR16_ABCDRegClass = {
5371
    &X86MCRegisterClasses[GR16_ABCDRegClassID],
5372
    GR16_ABCDSubClassMask,
5373
    SuperRegIdxSeqs + 5,
5374
    LaneBitmask(0x00000003),
5375
    0,
5376
    true, /* HasDisjunctSubRegs */
5377
    true, /* CoveredBySubRegs */
5378
    GR16_ABCDSuperclasses,
5379
    nullptr
5380
  };
5381
5382
  extern const TargetRegisterClass FPCCRRegClass = {
5383
    &X86MCRegisterClasses[FPCCRRegClassID],
5384
    FPCCRSubClassMask,
5385
    SuperRegIdxSeqs + 1,
5386
    LaneBitmask(0x00000001),
5387
    0,
5388
    false, /* HasDisjunctSubRegs */
5389
    false, /* CoveredBySubRegs */
5390
    NullRegClasses,
5391
    nullptr
5392
  };
5393
5394
  extern const TargetRegisterClass FR32XRegClass = {
5395
    &X86MCRegisterClasses[FR32XRegClassID],
5396
    FR32XSubClassMask,
5397
    SuperRegIdxSeqs + 9,
5398
    LaneBitmask(0x00000001),
5399
    0,
5400
    false, /* HasDisjunctSubRegs */
5401
    false, /* CoveredBySubRegs */
5402
    NullRegClasses,
5403
    nullptr
5404
  };
5405
5406
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
5407
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
5408
    LOW32_ADDR_ACCESS_RBPSubClassMask,
5409
    SuperRegIdxSeqs + 7,
5410
    LaneBitmask(0x0000000F),
5411
    0,
5412
    true, /* HasDisjunctSubRegs */
5413
    false, /* CoveredBySubRegs */
5414
    NullRegClasses,
5415
    nullptr
5416
  };
5417
5418
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
5419
    &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
5420
    LOW32_ADDR_ACCESSSubClassMask,
5421
    SuperRegIdxSeqs + 7,
5422
    LaneBitmask(0x0000000F),
5423
    0,
5424
    true, /* HasDisjunctSubRegs */
5425
    false, /* CoveredBySubRegs */
5426
    LOW32_ADDR_ACCESSSuperclasses,
5427
    nullptr
5428
  };
5429
5430
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
5431
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
5432
    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
5433
    SuperRegIdxSeqs + 7,
5434
    LaneBitmask(0x0000000F),
5435
    0,
5436
    true, /* HasDisjunctSubRegs */
5437
    false, /* CoveredBySubRegs */
5438
    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses,
5439
    nullptr
5440
  };
5441
5442
  extern const TargetRegisterClass DEBUG_REGRegClass = {
5443
    &X86MCRegisterClasses[DEBUG_REGRegClassID],
5444
    DEBUG_REGSubClassMask,
5445
    SuperRegIdxSeqs + 1,
5446
    LaneBitmask(0x00000001),
5447
    0,
5448
    false, /* HasDisjunctSubRegs */
5449
    false, /* CoveredBySubRegs */
5450
    NullRegClasses,
5451
    nullptr
5452
  };
5453
5454
  extern const TargetRegisterClass FR32RegClass = {
5455
    &X86MCRegisterClasses[FR32RegClassID],
5456
    FR32SubClassMask,
5457
    SuperRegIdxSeqs + 9,
5458
    LaneBitmask(0x00000001),
5459
    0,
5460
    false, /* HasDisjunctSubRegs */
5461
    false, /* CoveredBySubRegs */
5462
    FR32Superclasses,
5463
    nullptr
5464
  };
5465
5466
  extern const TargetRegisterClass GR32RegClass = {
5467
    &X86MCRegisterClasses[GR32RegClassID],
5468
    GR32SubClassMask,
5469
    SuperRegIdxSeqs + 7,
5470
    LaneBitmask(0x00000007),
5471
    0,
5472
    true, /* HasDisjunctSubRegs */
5473
    true, /* CoveredBySubRegs */
5474
    GR32Superclasses,
5475
    nullptr
5476
  };
5477
5478
  extern const TargetRegisterClass GR32_NOSPRegClass = {
5479
    &X86MCRegisterClasses[GR32_NOSPRegClassID],
5480
    GR32_NOSPSubClassMask,
5481
    SuperRegIdxSeqs + 7,
5482
    LaneBitmask(0x00000007),
5483
    0,
5484
    true, /* HasDisjunctSubRegs */
5485
    true, /* CoveredBySubRegs */
5486
    GR32_NOSPSuperclasses,
5487
    nullptr
5488
  };
5489
5490
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
5491
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
5492
    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
5493
    SuperRegIdxSeqs + 7,
5494
    LaneBitmask(0x0000000F),
5495
    0,
5496
    true, /* HasDisjunctSubRegs */
5497
    false, /* CoveredBySubRegs */
5498
    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses,
5499
    nullptr
5500
  };
5501
5502
  extern const TargetRegisterClass GR32_NOREXRegClass = {
5503
    &X86MCRegisterClasses[GR32_NOREXRegClassID],
5504
    GR32_NOREXSubClassMask,
5505
    SuperRegIdxSeqs + 7,
5506
    LaneBitmask(0x00000007),
5507
    0,
5508
    true, /* HasDisjunctSubRegs */
5509
    true, /* CoveredBySubRegs */
5510
    GR32_NOREXSuperclasses,
5511
    nullptr
5512
  };
5513
5514
  extern const TargetRegisterClass VK32RegClass = {
5515
    &X86MCRegisterClasses[VK32RegClassID],
5516
    VK32SubClassMask,
5517
    SuperRegIdxSeqs + 1,
5518
    LaneBitmask(0x00000001),
5519
    0,
5520
    false, /* HasDisjunctSubRegs */
5521
    false, /* CoveredBySubRegs */
5522
    VK32Superclasses,
5523
    nullptr
5524
  };
5525
5526
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
5527
    &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
5528
    GR32_NOREX_NOSPSubClassMask,
5529
    SuperRegIdxSeqs + 7,
5530
    LaneBitmask(0x00000007),
5531
    0,
5532
    true, /* HasDisjunctSubRegs */
5533
    true, /* CoveredBySubRegs */
5534
    GR32_NOREX_NOSPSuperclasses,
5535
    nullptr
5536
  };
5537
5538
  extern const TargetRegisterClass RFP32RegClass = {
5539
    &X86MCRegisterClasses[RFP32RegClassID],
5540
    RFP32SubClassMask,
5541
    SuperRegIdxSeqs + 1,
5542
    LaneBitmask(0x00000001),
5543
    0,
5544
    false, /* HasDisjunctSubRegs */
5545
    false, /* CoveredBySubRegs */
5546
    NullRegClasses,
5547
    nullptr
5548
  };
5549
5550
  extern const TargetRegisterClass VK32WMRegClass = {
5551
    &X86MCRegisterClasses[VK32WMRegClassID],
5552
    VK32WMSubClassMask,
5553
    SuperRegIdxSeqs + 1,
5554
    LaneBitmask(0x00000001),
5555
    0,
5556
    false, /* HasDisjunctSubRegs */
5557
    false, /* CoveredBySubRegs */
5558
    VK32WMSuperclasses,
5559
    nullptr
5560
  };
5561
5562
  extern const TargetRegisterClass GR32_ABCDRegClass = {
5563
    &X86MCRegisterClasses[GR32_ABCDRegClassID],
5564
    GR32_ABCDSubClassMask,
5565
    SuperRegIdxSeqs + 7,
5566
    LaneBitmask(0x00000007),
5567
    0,
5568
    true, /* HasDisjunctSubRegs */
5569
    true, /* CoveredBySubRegs */
5570
    GR32_ABCDSuperclasses,
5571
    nullptr
5572
  };
5573
5574
  extern const TargetRegisterClass GR32_TCRegClass = {
5575
    &X86MCRegisterClasses[GR32_TCRegClassID],
5576
    GR32_TCSubClassMask,
5577
    SuperRegIdxSeqs + 7,
5578
    LaneBitmask(0x00000007),
5579
    0,
5580
    true, /* HasDisjunctSubRegs */
5581
    true, /* CoveredBySubRegs */
5582
    GR32_TCSuperclasses,
5583
    nullptr
5584
  };
5585
5586
  extern const TargetRegisterClass GR32_ADRegClass = {
5587
    &X86MCRegisterClasses[GR32_ADRegClassID],
5588
    GR32_ADSubClassMask,
5589
    SuperRegIdxSeqs + 7,
5590
    LaneBitmask(0x00000007),
5591
    0,
5592
    true, /* HasDisjunctSubRegs */
5593
    true, /* CoveredBySubRegs */
5594
    GR32_ADSuperclasses,
5595
    nullptr
5596
  };
5597
5598
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
5599
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
5600
    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
5601
    SuperRegIdxSeqs + 1,
5602
    LaneBitmask(0x0000000F),
5603
    0,
5604
    true, /* HasDisjunctSubRegs */
5605
    false, /* CoveredBySubRegs */
5606
    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses,
5607
    nullptr
5608
  };
5609
5610
  extern const TargetRegisterClass CCRRegClass = {
5611
    &X86MCRegisterClasses[CCRRegClassID],
5612
    CCRSubClassMask,
5613
    SuperRegIdxSeqs + 1,
5614
    LaneBitmask(0x00000001),
5615
    0,
5616
    false, /* HasDisjunctSubRegs */
5617
    false, /* CoveredBySubRegs */
5618
    NullRegClasses,
5619
    nullptr
5620
  };
5621
5622
  extern const TargetRegisterClass DFCCRRegClass = {
5623
    &X86MCRegisterClasses[DFCCRRegClassID],
5624
    DFCCRSubClassMask,
5625
    SuperRegIdxSeqs + 1,
5626
    LaneBitmask(0x00000001),
5627
    0,
5628
    false, /* HasDisjunctSubRegs */
5629
    false, /* CoveredBySubRegs */
5630
    NullRegClasses,
5631
    nullptr
5632
  };
5633
5634
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
5635
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
5636
    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
5637
    SuperRegIdxSeqs + 1,
5638
    LaneBitmask(0x0000000F),
5639
    0,
5640
    true, /* HasDisjunctSubRegs */
5641
    false, /* CoveredBySubRegs */
5642
    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses,
5643
    nullptr
5644
  };
5645
5646
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
5647
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
5648
    LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
5649
    SuperRegIdxSeqs + 1,
5650
    LaneBitmask(0x0000000F),
5651
    0,
5652
    true, /* HasDisjunctSubRegs */
5653
    false, /* CoveredBySubRegs */
5654
    LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses,
5655
    nullptr
5656
  };
5657
5658
  extern const TargetRegisterClass RFP64RegClass = {
5659
    &X86MCRegisterClasses[RFP64RegClassID],
5660
    RFP64SubClassMask,
5661
    SuperRegIdxSeqs + 1,
5662
    LaneBitmask(0x00000001),
5663
    0,
5664
    false, /* HasDisjunctSubRegs */
5665
    false, /* CoveredBySubRegs */
5666
    RFP64Superclasses,
5667
    nullptr
5668
  };
5669
5670
  extern const TargetRegisterClass FR64XRegClass = {
5671
    &X86MCRegisterClasses[FR64XRegClassID],
5672
    FR64XSubClassMask,
5673
    SuperRegIdxSeqs + 9,
5674
    LaneBitmask(0x00000001),
5675
    0,
5676
    false, /* HasDisjunctSubRegs */
5677
    false, /* CoveredBySubRegs */
5678
    FR64XSuperclasses,
5679
    nullptr
5680
  };
5681
5682
  extern const TargetRegisterClass GR64RegClass = {
5683
    &X86MCRegisterClasses[GR64RegClassID],
5684
    GR64SubClassMask,
5685
    SuperRegIdxSeqs + 1,
5686
    LaneBitmask(0x0000000F),
5687
    0,
5688
    true, /* HasDisjunctSubRegs */
5689
    false, /* CoveredBySubRegs */
5690
    NullRegClasses,
5691
    nullptr
5692
  };
5693
5694
  extern const TargetRegisterClass CONTROL_REGRegClass = {
5695
    &X86MCRegisterClasses[CONTROL_REGRegClassID],
5696
    CONTROL_REGSubClassMask,
5697
    SuperRegIdxSeqs + 1,
5698
    LaneBitmask(0x00000001),
5699
    0,
5700
    false, /* HasDisjunctSubRegs */
5701
    false, /* CoveredBySubRegs */
5702
    NullRegClasses,
5703
    nullptr
5704
  };
5705
5706
  extern const TargetRegisterClass FR64RegClass = {
5707
    &X86MCRegisterClasses[FR64RegClassID],
5708
    FR64SubClassMask,
5709
    SuperRegIdxSeqs + 9,
5710
    LaneBitmask(0x00000001),
5711
    0,
5712
    false, /* HasDisjunctSubRegs */
5713
    false, /* CoveredBySubRegs */
5714
    FR64Superclasses,
5715
    nullptr
5716
  };