Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass X86MCRegisterClasses[];
17
18
namespace X86 {
19
enum {
20
  NoRegister,
21
  AH = 1,
22
  AL = 2,
23
  AX = 3,
24
  BH = 4,
25
  BL = 5,
26
  BP = 6,
27
  BPH = 7,
28
  BPL = 8,
29
  BX = 9,
30
  CH = 10,
31
  CL = 11,
32
  CS = 12,
33
  CX = 13,
34
  DF = 14,
35
  DH = 15,
36
  DI = 16,
37
  DIH = 17,
38
  DIL = 18,
39
  DL = 19,
40
  DS = 20,
41
  DX = 21,
42
  EAX = 22,
43
  EBP = 23,
44
  EBX = 24,
45
  ECX = 25,
46
  EDI = 26,
47
  EDX = 27,
48
  EFLAGS = 28,
49
  EIP = 29,
50
  EIZ = 30,
51
  ES = 31,
52
  ESI = 32,
53
  ESP = 33,
54
  FPCW = 34,
55
  FPSW = 35,
56
  FS = 36,
57
  GS = 37,
58
  HAX = 38,
59
  HBP = 39,
60
  HBX = 40,
61
  HCX = 41,
62
  HDI = 42,
63
  HDX = 43,
64
  HIP = 44,
65
  HSI = 45,
66
  HSP = 46,
67
  IP = 47,
68
  RAX = 48,
69
  RBP = 49,
70
  RBX = 50,
71
  RCX = 51,
72
  RDI = 52,
73
  RDX = 53,
74
  RIP = 54,
75
  RIZ = 55,
76
  RSI = 56,
77
  RSP = 57,
78
  SI = 58,
79
  SIH = 59,
80
  SIL = 60,
81
  SP = 61,
82
  SPH = 62,
83
  SPL = 63,
84
  SS = 64,
85
  SSP = 65,
86
  BND0 = 66,
87
  BND1 = 67,
88
  BND2 = 68,
89
  BND3 = 69,
90
  CR0 = 70,
91
  CR1 = 71,
92
  CR2 = 72,
93
  CR3 = 73,
94
  CR4 = 74,
95
  CR5 = 75,
96
  CR6 = 76,
97
  CR7 = 77,
98
  CR8 = 78,
99
  CR9 = 79,
100
  CR10 = 80,
101
  CR11 = 81,
102
  CR12 = 82,
103
  CR13 = 83,
104
  CR14 = 84,
105
  CR15 = 85,
106
  DR0 = 86,
107
  DR1 = 87,
108
  DR2 = 88,
109
  DR3 = 89,
110
  DR4 = 90,
111
  DR5 = 91,
112
  DR6 = 92,
113
  DR7 = 93,
114
  DR8 = 94,
115
  DR9 = 95,
116
  DR10 = 96,
117
  DR11 = 97,
118
  DR12 = 98,
119
  DR13 = 99,
120
  DR14 = 100,
121
  DR15 = 101,
122
  FP0 = 102,
123
  FP1 = 103,
124
  FP2 = 104,
125
  FP3 = 105,
126
  FP4 = 106,
127
  FP5 = 107,
128
  FP6 = 108,
129
  FP7 = 109,
130
  K0 = 110,
131
  K1 = 111,
132
  K2 = 112,
133
  K3 = 113,
134
  K4 = 114,
135
  K5 = 115,
136
  K6 = 116,
137
  K7 = 117,
138
  MM0 = 118,
139
  MM1 = 119,
140
  MM2 = 120,
141
  MM3 = 121,
142
  MM4 = 122,
143
  MM5 = 123,
144
  MM6 = 124,
145
  MM7 = 125,
146
  R8 = 126,
147
  R9 = 127,
148
  R10 = 128,
149
  R11 = 129,
150
  R12 = 130,
151
  R13 = 131,
152
  R14 = 132,
153
  R15 = 133,
154
  ST0 = 134,
155
  ST1 = 135,
156
  ST2 = 136,
157
  ST3 = 137,
158
  ST4 = 138,
159
  ST5 = 139,
160
  ST6 = 140,
161
  ST7 = 141,
162
  XMM0 = 142,
163
  XMM1 = 143,
164
  XMM2 = 144,
165
  XMM3 = 145,
166
  XMM4 = 146,
167
  XMM5 = 147,
168
  XMM6 = 148,
169
  XMM7 = 149,
170
  XMM8 = 150,
171
  XMM9 = 151,
172
  XMM10 = 152,
173
  XMM11 = 153,
174
  XMM12 = 154,
175
  XMM13 = 155,
176
  XMM14 = 156,
177
  XMM15 = 157,
178
  XMM16 = 158,
179
  XMM17 = 159,
180
  XMM18 = 160,
181
  XMM19 = 161,
182
  XMM20 = 162,
183
  XMM21 = 163,
184
  XMM22 = 164,
185
  XMM23 = 165,
186
  XMM24 = 166,
187
  XMM25 = 167,
188
  XMM26 = 168,
189
  XMM27 = 169,
190
  XMM28 = 170,
191
  XMM29 = 171,
192
  XMM30 = 172,
193
  XMM31 = 173,
194
  YMM0 = 174,
195
  YMM1 = 175,
196
  YMM2 = 176,
197
  YMM3 = 177,
198
  YMM4 = 178,
199
  YMM5 = 179,
200
  YMM6 = 180,
201
  YMM7 = 181,
202
  YMM8 = 182,
203
  YMM9 = 183,
204
  YMM10 = 184,
205
  YMM11 = 185,
206
  YMM12 = 186,
207
  YMM13 = 187,
208
  YMM14 = 188,
209
  YMM15 = 189,
210
  YMM16 = 190,
211
  YMM17 = 191,
212
  YMM18 = 192,
213
  YMM19 = 193,
214
  YMM20 = 194,
215
  YMM21 = 195,
216
  YMM22 = 196,
217
  YMM23 = 197,
218
  YMM24 = 198,
219
  YMM25 = 199,
220
  YMM26 = 200,
221
  YMM27 = 201,
222
  YMM28 = 202,
223
  YMM29 = 203,
224
  YMM30 = 204,
225
  YMM31 = 205,
226
  ZMM0 = 206,
227
  ZMM1 = 207,
228
  ZMM2 = 208,
229
  ZMM3 = 209,
230
  ZMM4 = 210,
231
  ZMM5 = 211,
232
  ZMM6 = 212,
233
  ZMM7 = 213,
234
  ZMM8 = 214,
235
  ZMM9 = 215,
236
  ZMM10 = 216,
237
  ZMM11 = 217,
238
  ZMM12 = 218,
239
  ZMM13 = 219,
240
  ZMM14 = 220,
241
  ZMM15 = 221,
242
  ZMM16 = 222,
243
  ZMM17 = 223,
244
  ZMM18 = 224,
245
  ZMM19 = 225,
246
  ZMM20 = 226,
247
  ZMM21 = 227,
248
  ZMM22 = 228,
249
  ZMM23 = 229,
250
  ZMM24 = 230,
251
  ZMM25 = 231,
252
  ZMM26 = 232,
253
  ZMM27 = 233,
254
  ZMM28 = 234,
255
  ZMM29 = 235,
256
  ZMM30 = 236,
257
  ZMM31 = 237,
258
  R8B = 238,
259
  R9B = 239,
260
  R10B = 240,
261
  R11B = 241,
262
  R12B = 242,
263
  R13B = 243,
264
  R14B = 244,
265
  R15B = 245,
266
  R8BH = 246,
267
  R9BH = 247,
268
  R10BH = 248,
269
  R11BH = 249,
270
  R12BH = 250,
271
  R13BH = 251,
272
  R14BH = 252,
273
  R15BH = 253,
274
  R8D = 254,
275
  R9D = 255,
276
  R10D = 256,
277
  R11D = 257,
278
  R12D = 258,
279
  R13D = 259,
280
  R14D = 260,
281
  R15D = 261,
282
  R8W = 262,
283
  R9W = 263,
284
  R10W = 264,
285
  R11W = 265,
286
  R12W = 266,
287
  R13W = 267,
288
  R14W = 268,
289
  R15W = 269,
290
  R8WH = 270,
291
  R9WH = 271,
292
  R10WH = 272,
293
  R11WH = 273,
294
  R12WH = 274,
295
  R13WH = 275,
296
  R14WH = 276,
297
  R15WH = 277,
298
  NUM_TARGET_REGS   // 278
299
};
300
} // end namespace X86
301
302
// Register classes
303
304
namespace X86 {
305
enum {
306
  GR8RegClassID = 0,
307
  GRH8RegClassID = 1,
308
  GR8_NOREXRegClassID = 2,
309
  GR8_ABCD_HRegClassID = 3,
310
  GR8_ABCD_LRegClassID = 4,
311
  GRH16RegClassID = 5,
312
  GR16RegClassID = 6,
313
  GR16_NOREXRegClassID = 7,
314
  VK1RegClassID = 8,
315
  VK16RegClassID = 9,
316
  VK2RegClassID = 10,
317
  VK4RegClassID = 11,
318
  VK8RegClassID = 12,
319
  VK16WMRegClassID = 13,
320
  VK1WMRegClassID = 14,
321
  VK2WMRegClassID = 15,
322
  VK4WMRegClassID = 16,
323
  VK8WMRegClassID = 17,
324
  SEGMENT_REGRegClassID = 18,
325
  GR16_ABCDRegClassID = 19,
326
  FPCCRRegClassID = 20,
327
  FR32XRegClassID = 21,
328
  LOW32_ADDR_ACCESS_RBPRegClassID = 22,
329
  LOW32_ADDR_ACCESSRegClassID = 23,
330
  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24,
331
  DEBUG_REGRegClassID = 25,
332
  FR32RegClassID = 26,
333
  GR32RegClassID = 27,
334
  GR32_NOSPRegClassID = 28,
335
  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29,
336
  GR32_NOREXRegClassID = 30,
337
  VK32RegClassID = 31,
338
  GR32_NOREX_NOSPRegClassID = 32,
339
  RFP32RegClassID = 33,
340
  VK32WMRegClassID = 34,
341
  GR32_ABCDRegClassID = 35,
342
  GR32_TCRegClassID = 36,
343
  GR32_ABCD_and_GR32_TCRegClassID = 37,
344
  GR32_ADRegClassID = 38,
345
  GR32_BPSPRegClassID = 39,
346
  GR32_BSIRegClassID = 40,
347
  GR32_CBRegClassID = 41,
348
  GR32_DCRegClassID = 42,
349
  GR32_DIBPRegClassID = 43,
350
  GR32_SIDIRegClassID = 44,
351
  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 45,
352
  CCRRegClassID = 46,
353
  DFCCRRegClassID = 47,
354
  GR32_ABCD_and_GR32_BSIRegClassID = 48,
355
  GR32_AD_and_GR32_DCRegClassID = 49,
356
  GR32_BPSP_and_GR32_DIBPRegClassID = 50,
357
  GR32_BPSP_and_GR32_TCRegClassID = 51,
358
  GR32_BSI_and_GR32_SIDIRegClassID = 52,
359
  GR32_CB_and_GR32_DCRegClassID = 53,
360
  GR32_DIBP_and_GR32_SIDIRegClassID = 54,
361
  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 55,
362
  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 56,
363
  RFP64RegClassID = 57,
364
  FR64XRegClassID = 58,
365
  GR64RegClassID = 59,
366
  CONTROL_REGRegClassID = 60,
367
  FR64RegClassID = 61,
368
  GR64_with_sub_8bitRegClassID = 62,
369
  GR64_NOSPRegClassID = 63,
370
  GR64_TCRegClassID = 64,
371
  GR64_NOREXRegClassID = 65,
372
  GR64_TCW64RegClassID = 66,
373
  GR64_TC_with_sub_8bitRegClassID = 67,
374
  GR64_NOSP_and_GR64_TCRegClassID = 68,
375
  GR64_TCW64_with_sub_8bitRegClassID = 69,
376
  GR64_TC_and_GR64_TCW64RegClassID = 70,
377
  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 71,
378
  VK64RegClassID = 72,
379
  VR64RegClassID = 73,
380
  GR64_NOREX_NOSPRegClassID = 74,
381
  GR64_NOREX_and_GR64_TCRegClassID = 75,
382
  GR64_NOSP_and_GR64_TCW64RegClassID = 76,
383
  GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 77,
384
  VK64WMRegClassID = 78,
385
  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 79,
386
  GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 80,
387
  GR64_NOREX_NOSP_and_GR64_TCRegClassID = 81,
388
  GR64_NOREX_and_GR64_TCW64RegClassID = 82,
389
  GR64_ABCDRegClassID = 83,
390
  GR64_with_sub_32bit_in_GR32_TCRegClassID = 84,
391
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 85,
392
  GR64_ADRegClassID = 86,
393
  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 87,
394
  GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 88,
395
  GR64_with_sub_32bit_in_GR32_BSIRegClassID = 89,
396
  GR64_with_sub_32bit_in_GR32_CBRegClassID = 90,
397
  GR64_with_sub_32bit_in_GR32_DCRegClassID = 91,
398
  GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 92,
399
  GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 93,
400
  GR64_and_LOW32_ADDR_ACCESSRegClassID = 94,
401
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 95,
402
  GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 96,
403
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 97,
404
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 98,
405
  GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 99,
406
  GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 100,
407
  GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 101,
408
  RSTRegClassID = 102,
409
  RFP80RegClassID = 103,
410
  RFP80_7RegClassID = 104,
411
  VR128XRegClassID = 105,
412
  VR128RegClassID = 106,
413
  VR128HRegClassID = 107,
414
  VR128LRegClassID = 108,
415
  BNDRRegClassID = 109,
416
  VR256XRegClassID = 110,
417
  VR256RegClassID = 111,
418
  VR256HRegClassID = 112,
419
  VR256LRegClassID = 113,
420
  VR512RegClassID = 114,
421
  VR512_with_sub_xmm_in_FR32RegClassID = 115,
422
  VR512_with_sub_xmm_in_VR128HRegClassID = 116,
423
  VR512_with_sub_xmm_in_VR128LRegClassID = 117,
424
425
  };
426
} // end namespace X86
427
428
429
// Subregister indices
430
431
namespace X86 {
432
enum {
433
  NoSubRegister,
434
  sub_8bit, // 1
435
  sub_8bit_hi,  // 2
436
  sub_8bit_hi_phony,  // 3
437
  sub_16bit,  // 4
438
  sub_16bit_hi, // 5
439
  sub_32bit,  // 6
440
  sub_xmm,  // 7
441
  sub_ymm,  // 8
442
  NUM_TARGET_SUBREGS
443
};
444
} // end namespace X86
445
446
} // end namespace llvm
447
448
#endif // GET_REGINFO_ENUM
449
450
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
451
|*                                                                            *|
452
|* MC Register Information                                                    *|
453
|*                                                                            *|
454
|* Automatically generated file, do not edit!                                 *|
455
|*                                                                            *|
456
\*===----------------------------------------------------------------------===*/
457
458
459
#ifdef GET_REGINFO_MC_DESC
460
#undef GET_REGINFO_MC_DESC
461
462
namespace llvm {
463
464
extern const MCPhysReg X86RegDiffLists[] = {
465
  /* 0 */ 0, 1, 0,
466
  /* 3 */ 64873, 1, 1, 0,
467
  /* 7 */ 65257, 1, 1, 0,
468
  /* 11 */ 65394, 1, 1, 0,
469
  /* 15 */ 65466, 1, 1, 0,
470
  /* 19 */ 2, 1, 0,
471
  /* 22 */ 4, 1, 0,
472
  /* 25 */ 6, 1, 0,
473
  /* 28 */ 11, 1, 0,
474
  /* 31 */ 22, 1, 0,
475
  /* 34 */ 26, 1, 0,
476
  /* 37 */ 29, 1, 0,
477
  /* 40 */ 64849, 1, 0,
478
  /* 43 */ 10, 3, 0,
479
  /* 46 */ 4, 0,
480
  /* 48 */ 5, 0,
481
  /* 50 */ 65287, 1, 7, 0,
482
  /* 54 */ 65417, 1, 7, 0,
483
  /* 58 */ 10, 3, 7, 0,
484
  /* 62 */ 65512, 8, 0,
485
  /* 65 */ 65338, 1, 11, 0,
486
  /* 69 */ 65344, 1, 11, 0,
487
  /* 73 */ 65442, 1, 11, 0,
488
  /* 77 */ 65448, 1, 11, 0,
489
  /* 81 */ 12, 0,
490
  /* 83 */ 65338, 1, 14, 0,
491
  /* 87 */ 65344, 1, 14, 0,
492
  /* 91 */ 65442, 1, 14, 0,
493
  /* 95 */ 65448, 1, 14, 0,
494
  /* 99 */ 21, 0,
495
  /* 101 */ 22, 0,
496
  /* 103 */ 128, 8, 65512, 8, 24, 0,
497
  /* 109 */ 65534, 65508, 24, 0,
498
  /* 113 */ 65535, 65508, 24, 0,
499
  /* 117 */ 65534, 65510, 24, 0,
500
  /* 121 */ 65535, 65510, 24, 0,
501
  /* 125 */ 65523, 24, 0,
502
  /* 128 */ 65518, 25, 0,
503
  /* 131 */ 65521, 25, 0,
504
  /* 134 */ 65510, 65526, 2, 65535, 25, 0,
505
  /* 140 */ 2, 6, 26, 0,
506
  /* 144 */ 6, 6, 26, 0,
507
  /* 148 */ 65534, 10, 26, 0,
508
  /* 152 */ 65535, 10, 26, 0,
509
  /* 156 */ 2, 12, 26, 0,
510
  /* 160 */ 3, 12, 26, 0,
511
  /* 164 */ 4, 15, 26, 0,
512
  /* 168 */ 5, 15, 26, 0,
513
  /* 172 */ 65534, 17, 26, 0,
514
  /* 176 */ 65535, 17, 26, 0,
515
  /* 180 */ 1, 19, 26, 0,
516
  /* 184 */ 2, 19, 26, 0,
517
  /* 188 */ 65520, 26, 0,
518
  /* 191 */ 27, 0,
519
  /* 193 */ 65510, 65530, 65534, 65532, 28, 0,
520
  /* 199 */ 30, 0,
521
  /* 201 */ 65510, 65524, 65534, 65535, 31, 0,
522
  /* 207 */ 32, 32, 0,
523
  /* 210 */ 65510, 65519, 2, 65535, 32, 0,
524
  /* 216 */ 65510, 65521, 65532, 65535, 36, 0,
525
  /* 222 */ 65510, 65517, 65535, 65535, 37, 0,
526
  /* 228 */ 64827, 0,
527
  /* 230 */ 64898, 0,
528
  /* 232 */ 64921, 0,
529
  /* 234 */ 65061, 0,
530
  /* 236 */ 65520, 65408, 0,
531
  /* 239 */ 16, 65528, 65408, 0,
532
  /* 243 */ 24, 65528, 65408, 0,
533
  /* 247 */ 65427, 0,
534
  /* 249 */ 65429, 0,
535
  /* 251 */ 65461, 0,
536
  /* 253 */ 65493, 0,
537
  /* 255 */ 65504, 65504, 0,
538
  /* 258 */ 65509, 0,
539
  /* 260 */ 65511, 0,
540
  /* 262 */ 65513, 0,
541
  /* 264 */ 65512, 28, 2, 65535, 65520, 0,
542
  /* 270 */ 65512, 26, 2, 65535, 65522, 0,
543
  /* 276 */ 65525, 0,
544
  /* 278 */ 65530, 0,
545
  /* 280 */ 65531, 0,
546
  /* 282 */ 65534, 65532, 0,
547
  /* 285 */ 65511, 18, 65533, 0,
548
  /* 289 */ 65534, 0,
549
  /* 291 */ 2, 65535, 0,
550
  /* 294 */ 65532, 65535, 0,
551
  /* 297 */ 65534, 65535, 0,
552
  /* 300 */ 65535, 65535, 0,
553
};
554
555
extern const LaneBitmask X86LaneMaskLists[] = {
556
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
557
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
558
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(),
559
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(),
560
  /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
561
  /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(),
562
  /* 19 */ LaneBitmask(0x00000010), LaneBitmask::getAll(),
563
};
564
565
extern const uint16_t X86SubRegIdxLists[] = {
566
  /* 0 */ 1, 2, 0,
567
  /* 3 */ 1, 3, 0,
568
  /* 6 */ 6, 4, 1, 2, 5, 0,
569
  /* 12 */ 6, 4, 1, 3, 5, 0,
570
  /* 18 */ 6, 4, 5, 0,
571
  /* 22 */ 8, 7, 0,
572
};
573
574
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
575
  { 65535, 65535 },
576
  { 0, 8 }, // sub_8bit
577
  { 8, 8 }, // sub_8bit_hi
578
  { 8, 8 }, // sub_8bit_hi_phony
579
  { 0, 16 },  // sub_16bit
580
  { 16, 16 }, // sub_16bit_hi
581
  { 0, 32 },  // sub_32bit
582
  { 0, 128 }, // sub_xmm
583
  { 0, 256 }, // sub_ymm
584
};
585
586
extern const char X86RegStrings[] = {
587
  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
588
  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
589
  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
590
  /* 18 */ 'C', 'R', '1', '0', 0,
591
  /* 23 */ 'D', 'R', '1', '0', 0,
592
  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
593
  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
594
  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
595
  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
596
  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
597
  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
598
  /* 64 */ 'B', 'N', 'D', '0', 0,
599
  /* 69 */ 'K', '0', 0,
600
  /* 72 */ 'X', 'M', 'M', '0', 0,
601
  /* 77 */ 'Y', 'M', 'M', '0', 0,
602
  /* 82 */ 'Z', 'M', 'M', '0', 0,
603
  /* 87 */ 'F', 'P', '0', 0,
604
  /* 91 */ 'C', 'R', '0', 0,
605
  /* 95 */ 'D', 'R', '0', 0,
606
  /* 99 */ 'S', 'T', '0', 0,
607
  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
608
  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
609
  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
610
  /* 121 */ 'C', 'R', '1', '1', 0,
611
  /* 126 */ 'D', 'R', '1', '1', 0,
612
  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
613
  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
614
  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
615
  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
616
  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
617
  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
618
  /* 167 */ 'B', 'N', 'D', '1', 0,
619
  /* 172 */ 'K', '1', 0,
620
  /* 175 */ 'X', 'M', 'M', '1', 0,
621
  /* 180 */ 'Y', 'M', 'M', '1', 0,
622
  /* 185 */ 'Z', 'M', 'M', '1', 0,
623
  /* 190 */ 'F', 'P', '1', 0,
624
  /* 194 */ 'C', 'R', '1', 0,
625
  /* 198 */ 'D', 'R', '1', 0,
626
  /* 202 */ 'S', 'T', '1', 0,
627
  /* 206 */ 'X', 'M', 'M', '1', '2', 0,
628
  /* 212 */ 'Y', 'M', 'M', '1', '2', 0,
629
  /* 218 */ 'Z', 'M', 'M', '1', '2', 0,
630
  /* 224 */ 'C', 'R', '1', '2', 0,
631
  /* 229 */ 'D', 'R', '1', '2', 0,
632
  /* 234 */ 'X', 'M', 'M', '2', '2', 0,
633
  /* 240 */ 'Y', 'M', 'M', '2', '2', 0,
634
  /* 246 */ 'Z', 'M', 'M', '2', '2', 0,
635
  /* 252 */ 'B', 'N', 'D', '2', 0,
636
  /* 257 */ 'K', '2', 0,
637
  /* 260 */ 'X', 'M', 'M', '2', 0,
638
  /* 265 */ 'Y', 'M', 'M', '2', 0,
639
  /* 270 */ 'Z', 'M', 'M', '2', 0,
640
  /* 275 */ 'F', 'P', '2', 0,
641
  /* 279 */ 'C', 'R', '2', 0,
642
  /* 283 */ 'D', 'R', '2', 0,
643
  /* 287 */ 'S', 'T', '2', 0,
644
  /* 291 */ 'X', 'M', 'M', '1', '3', 0,
645
  /* 297 */ 'Y', 'M', 'M', '1', '3', 0,
646
  /* 303 */ 'Z', 'M', 'M', '1', '3', 0,
647
  /* 309 */ 'C', 'R', '1', '3', 0,
648
  /* 314 */ 'D', 'R', '1', '3', 0,
649
  /* 319 */ 'X', 'M', 'M', '2', '3', 0,
650
  /* 325 */ 'Y', 'M', 'M', '2', '3', 0,
651
  /* 331 */ 'Z', 'M', 'M', '2', '3', 0,
652
  /* 337 */ 'B', 'N', 'D', '3', 0,
653
  /* 342 */ 'K', '3', 0,
654
  /* 345 */ 'X', 'M', 'M', '3', 0,
655
  /* 350 */ 'Y', 'M', 'M', '3', 0,
656
  /* 355 */ 'Z', 'M', 'M', '3', 0,
657
  /* 360 */ 'F', 'P', '3', 0,
658
  /* 364 */ 'C', 'R', '3', 0,
659
  /* 368 */ 'D', 'R', '3', 0,
660
  /* 372 */ 'S', 'T', '3', 0,
661
  /* 376 */ 'X', 'M', 'M', '1', '4', 0,
662
  /* 382 */ 'Y', 'M', 'M', '1', '4', 0,
663
  /* 388 */ 'Z', 'M', 'M', '1', '4', 0,
664
  /* 394 */ 'C', 'R', '1', '4', 0,
665
  /* 399 */ 'D', 'R', '1', '4', 0,
666
  /* 404 */ 'X', 'M', 'M', '2', '4', 0,
667
  /* 410 */ 'Y', 'M', 'M', '2', '4', 0,
668
  /* 416 */ 'Z', 'M', 'M', '2', '4', 0,
669
  /* 422 */ 'K', '4', 0,
670
  /* 425 */ 'X', 'M', 'M', '4', 0,
671
  /* 430 */ 'Y', 'M', 'M', '4', 0,
672
  /* 435 */ 'Z', 'M', 'M', '4', 0,
673
  /* 440 */ 'F', 'P', '4', 0,
674
  /* 444 */ 'C', 'R', '4', 0,
675
  /* 448 */ 'D', 'R', '4', 0,
676
  /* 452 */ 'S', 'T', '4', 0,
677
  /* 456 */ 'X', 'M', 'M', '1', '5', 0,
678
  /* 462 */ 'Y', 'M', 'M', '1', '5', 0,
679
  /* 468 */ 'Z', 'M', 'M', '1', '5', 0,
680
  /* 474 */ 'C', 'R', '1', '5', 0,
681
  /* 479 */ 'D', 'R', '1', '5', 0,
682
  /* 484 */ 'X', 'M', 'M', '2', '5', 0,
683
  /* 490 */ 'Y', 'M', 'M', '2', '5', 0,
684
  /* 496 */ 'Z', 'M', 'M', '2', '5', 0,
685
  /* 502 */ 'K', '5', 0,
686
  /* 505 */ 'X', 'M', 'M', '5', 0,
687
  /* 510 */ 'Y', 'M', 'M', '5', 0,
688
  /* 515 */ 'Z', 'M', 'M', '5', 0,
689
  /* 520 */ 'F', 'P', '5', 0,
690
  /* 524 */ 'C', 'R', '5', 0,
691
  /* 528 */ 'D', 'R', '5', 0,
692
  /* 532 */ 'S', 'T', '5', 0,
693
  /* 536 */ 'X', 'M', 'M', '1', '6', 0,
694
  /* 542 */ 'Y', 'M', 'M', '1', '6', 0,
695
  /* 548 */ 'Z', 'M', 'M', '1', '6', 0,
696
  /* 554 */ 'X', 'M', 'M', '2', '6', 0,
697
  /* 560 */ 'Y', 'M', 'M', '2', '6', 0,
698
  /* 566 */ 'Z', 'M', 'M', '2', '6', 0,
699
  /* 572 */ 'K', '6', 0,
700
  /* 575 */ 'X', 'M', 'M', '6', 0,
701
  /* 580 */ 'Y', 'M', 'M', '6', 0,
702
  /* 585 */ 'Z', 'M', 'M', '6', 0,
703
  /* 590 */ 'F', 'P', '6', 0,
704
  /* 594 */ 'C', 'R', '6', 0,
705
  /* 598 */ 'D', 'R', '6', 0,
706
  /* 602 */ 'S', 'T', '6', 0,
707
  /* 606 */ 'X', 'M', 'M', '1', '7', 0,
708
  /* 612 */ 'Y', 'M', 'M', '1', '7', 0,
709
  /* 618 */ 'Z', 'M', 'M', '1', '7', 0,
710
  /* 624 */ 'X', 'M', 'M', '2', '7', 0,
711
  /* 630 */ 'Y', 'M', 'M', '2', '7', 0,
712
  /* 636 */ 'Z', 'M', 'M', '2', '7', 0,
713
  /* 642 */ 'K', '7', 0,
714
  /* 645 */ 'X', 'M', 'M', '7', 0,
715
  /* 650 */ 'Y', 'M', 'M', '7', 0,
716
  /* 655 */ 'Z', 'M', 'M', '7', 0,
717
  /* 660 */ 'F', 'P', '7', 0,
718
  /* 664 */ 'C', 'R', '7', 0,
719
  /* 668 */ 'D', 'R', '7', 0,
720
  /* 672 */ 'S', 'T', '7', 0,
721
  /* 676 */ 'X', 'M', 'M', '1', '8', 0,
722
  /* 682 */ 'Y', 'M', 'M', '1', '8', 0,
723
  /* 688 */ 'Z', 'M', 'M', '1', '8', 0,
724
  /* 694 */ 'X', 'M', 'M', '2', '8', 0,
725
  /* 700 */ 'Y', 'M', 'M', '2', '8', 0,
726
  /* 706 */ 'Z', 'M', 'M', '2', '8', 0,
727
  /* 712 */ 'X', 'M', 'M', '8', 0,
728
  /* 717 */ 'Y', 'M', 'M', '8', 0,
729
  /* 722 */ 'Z', 'M', 'M', '8', 0,
730
  /* 727 */ 'C', 'R', '8', 0,
731
  /* 731 */ 'D', 'R', '8', 0,
732
  /* 735 */ 'X', 'M', 'M', '1', '9', 0,
733
  /* 741 */ 'Y', 'M', 'M', '1', '9', 0,
734
  /* 747 */ 'Z', 'M', 'M', '1', '9', 0,
735
  /* 753 */ 'X', 'M', 'M', '2', '9', 0,
736
  /* 759 */ 'Y', 'M', 'M', '2', '9', 0,
737
  /* 765 */ 'Z', 'M', 'M', '2', '9', 0,
738
  /* 771 */ 'X', 'M', 'M', '9', 0,
739
  /* 776 */ 'Y', 'M', 'M', '9', 0,
740
  /* 781 */ 'Z', 'M', 'M', '9', 0,
741
  /* 786 */ 'C', 'R', '9', 0,
742
  /* 790 */ 'D', 'R', '9', 0,
743
  /* 794 */ 'R', '1', '0', 'B', 0,
744
  /* 799 */ 'R', '1', '1', 'B', 0,
745
  /* 804 */ 'R', '1', '2', 'B', 0,
746
  /* 809 */ 'R', '1', '3', 'B', 0,
747
  /* 814 */ 'R', '1', '4', 'B', 0,
748
  /* 819 */ 'R', '1', '5', 'B', 0,
749
  /* 824 */ 'R', '8', 'B', 0,
750
  /* 828 */ 'R', '9', 'B', 0,
751
  /* 832 */ 'R', '1', '0', 'D', 0,
752
  /* 837 */ 'R', '1', '1', 'D', 0,
753
  /* 842 */ 'R', '1', '2', 'D', 0,
754
  /* 847 */ 'R', '1', '3', 'D', 0,
755
  /* 852 */ 'R', '1', '4', 'D', 0,
756
  /* 857 */ 'R', '1', '5', 'D', 0,
757
  /* 862 */ 'R', '8', 'D', 0,
758
  /* 866 */ 'R', '9', 'D', 0,
759
  /* 870 */ 'D', 'F', 0,
760
  /* 873 */ 'A', 'H', 0,
761
  /* 876 */ 'R', '1', '0', 'B', 'H', 0,
762
  /* 882 */ 'R', '1', '1', 'B', 'H', 0,
763
  /* 888 */ 'R', '1', '2', 'B', 'H', 0,
764
  /* 894 */ 'R', '1', '3', 'B', 'H', 0,
765
  /* 900 */ 'R', '1', '4', 'B', 'H', 0,
766
  /* 906 */ 'R', '1', '5', 'B', 'H', 0,
767
  /* 912 */ 'R', '8', 'B', 'H', 0,
768
  /* 917 */ 'R', '9', 'B', 'H', 0,
769
  /* 922 */ 'C', 'H', 0,
770
  /* 925 */ 'D', 'H', 0,
771
  /* 928 */ 'D', 'I', 'H', 0,
772
  /* 932 */ 'S', 'I', 'H', 0,
773
  /* 936 */ 'B', 'P', 'H', 0,
774
  /* 940 */ 'S', 'P', 'H', 0,
775
  /* 944 */ 'R', '1', '0', 'W', 'H', 0,
776
  /* 950 */ 'R', '1', '1', 'W', 'H', 0,
777
  /* 956 */ 'R', '1', '2', 'W', 'H', 0,
778
  /* 962 */ 'R', '1', '3', 'W', 'H', 0,
779
  /* 968 */ 'R', '1', '4', 'W', 'H', 0,
780
  /* 974 */ 'R', '1', '5', 'W', 'H', 0,
781
  /* 980 */ 'R', '8', 'W', 'H', 0,
782
  /* 985 */ 'R', '9', 'W', 'H', 0,
783
  /* 990 */ 'E', 'D', 'I', 0,
784
  /* 994 */ 'H', 'D', 'I', 0,
785
  /* 998 */ 'R', 'D', 'I', 0,
786
  /* 1002 */ 'E', 'S', 'I', 0,
787
  /* 1006 */ 'H', 'S', 'I', 0,
788
  /* 1010 */ 'R', 'S', 'I', 0,
789
  /* 1014 */ 'A', 'L', 0,
790
  /* 1017 */ 'B', 'L', 0,
791
  /* 1020 */ 'C', 'L', 0,
792
  /* 1023 */ 'D', 'L', 0,
793
  /* 1026 */ 'D', 'I', 'L', 0,
794
  /* 1030 */ 'S', 'I', 'L', 0,
795
  /* 1034 */ 'B', 'P', 'L', 0,
796
  /* 1038 */ 'S', 'P', 'L', 0,
797
  /* 1042 */ 'E', 'B', 'P', 0,
798
  /* 1046 */ 'H', 'B', 'P', 0,
799
  /* 1050 */ 'R', 'B', 'P', 0,
800
  /* 1054 */ 'E', 'I', 'P', 0,
801
  /* 1058 */ 'H', 'I', 'P', 0,
802
  /* 1062 */ 'R', 'I', 'P', 0,
803
  /* 1066 */ 'E', 'S', 'P', 0,
804
  /* 1070 */ 'H', 'S', 'P', 0,
805
  /* 1074 */ 'R', 'S', 'P', 0,
806
  /* 1078 */ 'S', 'S', 'P', 0,
807
  /* 1082 */ 'C', 'S', 0,
808
  /* 1085 */ 'D', 'S', 0,
809
  /* 1088 */ 'E', 'S', 0,
810
  /* 1091 */ 'F', 'S', 0,
811
  /* 1094 */ 'E', 'F', 'L', 'A', 'G', 'S', 0,
812
  /* 1101 */ 'S', 'S', 0,
813
  /* 1104 */ 'R', '1', '0', 'W', 0,
814
  /* 1109 */ 'R', '1', '1', 'W', 0,
815
  /* 1114 */ 'R', '1', '2', 'W', 0,
816
  /* 1119 */ 'R', '1', '3', 'W', 0,
817
  /* 1124 */ 'R', '1', '4', 'W', 0,
818
  /* 1129 */ 'R', '1', '5', 'W', 0,
819
  /* 1134 */ 'R', '8', 'W', 0,
820
  /* 1138 */ 'R', '9', 'W', 0,
821
  /* 1142 */ 'F', 'P', 'C', 'W', 0,
822
  /* 1147 */ 'F', 'P', 'S', 'W', 0,
823
  /* 1152 */ 'E', 'A', 'X', 0,
824
  /* 1156 */ 'H', 'A', 'X', 0,
825
  /* 1160 */ 'R', 'A', 'X', 0,
826
  /* 1164 */ 'E', 'B', 'X', 0,
827
  /* 1168 */ 'H', 'B', 'X', 0,
828
  /* 1172 */ 'R', 'B', 'X', 0,
829
  /* 1176 */ 'E', 'C', 'X', 0,
830
  /* 1180 */ 'H', 'C', 'X', 0,
831
  /* 1184 */ 'R', 'C', 'X', 0,
832
  /* 1188 */ 'E', 'D', 'X', 0,
833
  /* 1192 */ 'H', 'D', 'X', 0,
834
  /* 1196 */ 'R', 'D', 'X', 0,
835
  /* 1200 */ 'E', 'I', 'Z', 0,
836
  /* 1204 */ 'R', 'I', 'Z', 0,
837
};
838
839
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
840
  { 5, 0, 0, 0, 0, 0 },
841
  { 873, 2, 184, 2, 4673, 0 },
842
  { 1014, 2, 180, 2, 4673, 0 },
843
  { 1153, 300, 181, 0, 0, 2 },
844
  { 879, 2, 168, 2, 4625, 0 },
845
  { 1017, 2, 164, 2, 4625, 0 },
846
  { 1043, 291, 173, 3, 352, 5 },
847
  { 936, 2, 176, 2, 768, 0 },
848
  { 1034, 2, 172, 2, 736, 0 },
849
  { 1165, 294, 165, 0, 304, 2 },
850
  { 922, 2, 160, 2, 4529, 0 },
851
  { 1020, 2, 156, 2, 4529, 0 },
852
  { 1082, 2, 2, 2, 4529, 0 },
853
  { 1177, 297, 157, 0, 400, 2 },
854
  { 870, 2, 2, 2, 4481, 0 },
855
  { 925, 2, 144, 2, 4481, 0 },
856
  { 991, 291, 149, 3, 448, 5 },
857
  { 928, 2, 152, 2, 1296, 0 },
858
  { 1026, 2, 148, 2, 4162, 0 },
859
  { 1023, 2, 140, 2, 4449, 0 },
860
  { 1085, 2, 2, 2, 4449, 0 },
861
  { 1189, 282, 141, 0, 688, 2 },
862
  { 1152, 223, 142, 7, 1524, 8 },
863
  { 1042, 211, 142, 13, 1236, 12 },
864
  { 1164, 217, 142, 7, 1460, 8 },
865
  { 1176, 202, 142, 7, 1172, 8 },
866
  { 990, 135, 142, 13, 869, 12 },
867
  { 1188, 194, 142, 7, 928, 8 },
868
  { 1094, 2, 2, 2, 1584, 0 },
869
  { 1054, 286, 129, 19, 496, 16 },
870
  { 1200, 2, 2, 2, 4449, 0 },
871
  { 1088, 2, 2, 2, 4449, 0 },
872
  { 1002, 271, 107, 13, 243, 12 },
873
  { 1066, 265, 107, 13, 243, 12 },
874
  { 1142, 2, 2, 2, 4625, 0 },
875
  { 1147, 2, 2, 2, 4625, 0 },
876
  { 1091, 2, 2, 2, 4625, 0 },
877
  { 1098, 2, 2, 2, 4625, 0 },
878
  { 1156, 2, 188, 2, 4193, 0 },
879
  { 1046, 2, 188, 2, 4193, 0 },
880
  { 1168, 2, 188, 2, 4193, 0 },
881
  { 1180, 2, 188, 2, 4193, 0 },
882
  { 994, 2, 188, 2, 4193, 0 },
883
  { 1192, 2, 188, 2, 4193, 0 },
884
  { 1058, 2, 131, 2, 3955, 0 },
885
  { 1006, 2, 125, 2, 3987, 0 },
886
  { 1070, 2, 125, 2, 3987, 0 },
887
  { 1055, 2, 128, 2, 1616, 0 },
888
  { 1160, 222, 2, 6, 1396, 8 },
889
  { 1050, 210, 2, 12, 1108, 12 },
890
  { 1172, 216, 2, 6, 1332, 8 },
891
  { 1184, 201, 2, 6, 1044, 8 },
892
  { 998, 134, 2, 12, 805, 12 },
893
  { 1196, 193, 2, 6, 928, 8 },
894
  { 1062, 285, 2, 18, 496, 16 },
895
  { 1204, 2, 2, 2, 3520, 0 },
896
  { 1010, 270, 2, 12, 179, 12 },
897
  { 1074, 264, 2, 12, 179, 12 },
898
  { 1003, 291, 118, 3, 544, 5 },
899
  { 932, 2, 121, 2, 3056, 0 },
900
  { 1030, 2, 117, 2, 2272, 0 },
901
  { 1067, 291, 110, 3, 592, 5 },
902
  { 940, 2, 113, 2, 3184, 0 },
903
  { 1038, 2, 109, 2, 3752, 0 },
904
  { 1101, 2, 2, 2, 4129, 0 },
905
  { 1078, 2, 2, 2, 4129, 0 },
906
  { 64, 2, 2, 2, 4129, 0 },
907
  { 167, 2, 2, 2, 4129, 0 },
908
  { 252, 2, 2, 2, 4129, 0 },
909
  { 337, 2, 2, 2, 4129, 0 },
910
  { 91, 2, 2, 2, 4129, 0 },
911
  { 194, 2, 2, 2, 4129, 0 },
912
  { 279, 2, 2, 2, 4129, 0 },
913
  { 364, 2, 2, 2, 4129, 0 },
914
  { 444, 2, 2, 2, 4129, 0 },
915
  { 524, 2, 2, 2, 4129, 0 },
916
  { 594, 2, 2, 2, 4129, 0 },
917
  { 664, 2, 2, 2, 4129, 0 },
918
  { 727, 2, 2, 2, 4129, 0 },
919
  { 786, 2, 2, 2, 4129, 0 },
920
  { 18, 2, 2, 2, 4129, 0 },
921
  { 121, 2, 2, 2, 4129, 0 },
922
  { 224, 2, 2, 2, 4129, 0 },
923
  { 309, 2, 2, 2, 4129, 0 },
924
  { 394, 2, 2, 2, 4129, 0 },
925
  { 474, 2, 2, 2, 4129, 0 },
926
  { 95, 2, 2, 2, 4129, 0 },
927
  { 198, 2, 2, 2, 4129, 0 },
928
  { 283, 2, 2, 2, 4129, 0 },
929
  { 368, 2, 2, 2, 4129, 0 },
930
  { 448, 2, 2, 2, 4129, 0 },
931
  { 528, 2, 2, 2, 4129, 0 },
932
  { 598, 2, 2, 2, 4129, 0 },
933
  { 668, 2, 2, 2, 4129, 0 },
934
  { 731, 2, 2, 2, 4129, 0 },
935
  { 790, 2, 2, 2, 4129, 0 },
936
  { 23, 2, 2, 2, 4129, 0 },
937
  { 126, 2, 2, 2, 4129, 0 },
938
  { 229, 2, 2, 2, 4129, 0 },
939
  { 314, 2, 2, 2, 4129, 0 },
940
  { 399, 2, 2, 2, 4129, 0 },
941
  { 479, 2, 2, 2, 4129, 0 },
942
  { 87, 2, 2, 2, 4129, 0 },
943
  { 190, 2, 2, 2, 4129, 0 },
944
  { 275, 2, 2, 2, 4129, 0 },
945
  { 360, 2, 2, 2, 4129, 0 },
946
  { 440, 2, 2, 2, 4129, 0 },
947
  { 520, 2, 2, 2, 4129, 0 },
948
  { 590, 2, 2, 2, 4129, 0 },
949
  { 660, 2, 2, 2, 4129, 0 },
950
  { 69, 2, 2, 2, 4129, 0 },
951
  { 172, 2, 2, 2, 4129, 0 },
952
  { 257, 2, 2, 2, 4129, 0 },
953
  { 342, 2, 2, 2, 4129, 0 },
954
  { 422, 2, 2, 2, 4129, 0 },
955
  { 502, 2, 2, 2, 4129, 0 },
956
  { 572, 2, 2, 2, 4129, 0 },
957
  { 642, 2, 2, 2, 4129, 0 },
958
  { 73, 2, 2, 2, 4129, 0 },
959
  { 176, 2, 2, 2, 4129, 0 },
960
  { 261, 2, 2, 2, 4129, 0 },
961
  { 346, 2, 2, 2, 4129, 0 },
962
  { 426, 2, 2, 2, 4129, 0 },
963
  { 506, 2, 2, 2, 4129, 0 },
964
  { 576, 2, 2, 2, 4129, 0 },
965
  { 646, 2, 2, 2, 4129, 0 },
966
  { 728, 103, 2, 12, 115, 12 },
967
  { 787, 103, 2, 12, 115, 12 },
968
  { 19, 103, 2, 12, 115, 12 },
969
  { 122, 103, 2, 12, 115, 12 },
970
  { 225, 103, 2, 12, 115, 12 },
971
  { 310, 103, 2, 12, 115, 12 },
972
  { 395, 103, 2, 12, 115, 12 },
973
  { 475, 103, 2, 12, 115, 12 },
974
  { 99, 2, 2, 2, 4417, 0 },
975
  { 202, 2, 2, 2, 4417, 0 },
976
  { 287, 2, 2, 2, 4417, 0 },
977
  { 372, 2, 2, 2, 4417, 0 },
978
  { 452, 2, 2, 2, 4417, 0 },
979
  { 532, 2, 2, 2, 4417, 0 },
980
  { 602, 2, 2, 2, 4417, 0 },
981
  { 672, 2, 2, 2, 4417, 0 },
982
  { 72, 2, 207, 2, 4417, 0 },
983
  { 175, 2, 207, 2, 4417, 0 },
984
  { 260, 2, 207, 2, 4417, 0 },
985
  { 345, 2, 207, 2, 4417, 0 },
986
  { 425, 2, 207, 2, 4417, 0 },
987
  { 505, 2, 207, 2, 4417, 0 },
988
  { 575, 2, 207, 2, 4417, 0 },
989
  { 645, 2, 207, 2, 4417, 0 },
990
  { 712, 2, 207, 2, 4417, 0 },
991
  { 771, 2, 207, 2, 4417, 0 },
992
  { 0, 2, 207, 2, 4417, 0 },
993
  { 103, 2, 207, 2, 4417, 0 },
994
  { 206, 2, 207, 2, 4417, 0 },
995
  { 291, 2, 207, 2, 4417, 0 },
996
  { 376, 2, 207, 2, 4417, 0 },
997
  { 456, 2, 207, 2, 4417, 0 },
998
  { 536, 2, 207, 2, 4417, 0 },
999
  { 606, 2, 207, 2, 4417, 0 },
1000
  { 676, 2, 207, 2, 4417, 0 },
1001
  { 735, 2, 207, 2, 4417, 0 },
1002
  { 28, 2, 207, 2, 4417, 0 },
1003
  { 131, 2, 207, 2, 4417, 0 },
1004
  { 234, 2, 207, 2, 4417, 0 },
1005
  { 319, 2, 207, 2, 4417, 0 },
1006
  { 404, 2, 207, 2, 4417, 0 },
1007
  { 484, 2, 207, 2, 4417, 0 },
1008
  { 554, 2, 207, 2, 4417, 0 },
1009
  { 624, 2, 207, 2, 4417, 0 },
1010
  { 694, 2, 207, 2, 4417, 0 },
1011
  { 753, 2, 207, 2, 4417, 0 },
1012
  { 46, 2, 207, 2, 4417, 0 },
1013
  { 149, 2, 207, 2, 4417, 0 },
1014
  { 77, 256, 208, 23, 4049, 19 },
1015
  { 180, 256, 208, 23, 4049, 19 },
1016
  { 265, 256, 208, 23, 4049, 19 },
1017
  { 350, 256, 208, 23, 4049, 19 },
1018
  { 430, 256, 208, 23, 4049, 19 },
1019
  { 510, 256, 208, 23, 4049, 19 },
1020
  { 580, 256, 208, 23, 4049, 19 },
1021
  { 650, 256, 208, 23, 4049, 19 },
1022
  { 717, 256, 208, 23, 4049, 19 },
1023
  { 776, 256, 208, 23, 4049, 19 },
1024
  { 6, 256, 208, 23, 4049, 19 },
1025
  { 109, 256, 208, 23, 4049, 19 },
1026
  { 212, 256, 208, 23, 4049, 19 },
1027
  { 297, 256, 208, 23, 4049, 19 },
1028
  { 382, 256, 208, 23, 4049, 19 },
1029
  { 462, 256, 208, 23, 4049, 19 },
1030
  { 542, 256, 208, 23, 4049, 19 },
1031
  { 612, 256, 208, 23, 4049, 19 },
1032
  { 682, 256, 208, 23, 4049, 19 },
1033
  { 741, 256, 208, 23, 4049, 19 },
1034
  { 34, 256, 208, 23, 4049, 19 },
1035
  { 137, 256, 208, 23, 4049, 19 },
1036
  { 240, 256, 208, 23, 4049, 19 },
1037
  { 325, 256, 208, 23, 4049, 19 },
1038
  { 410, 256, 208, 23, 4049, 19 },
1039
  { 490, 256, 208, 23, 4049, 19 },
1040
  { 560, 256, 208, 23, 4049, 19 },
1041
  { 630, 256, 208, 23, 4049, 19 },
1042
  { 700, 256, 208, 23, 4049, 19 },
1043
  { 759, 256, 208, 23, 4049, 19 },
1044
  { 52, 256, 208, 23, 4049, 19 },
1045
  { 155, 256, 208, 23, 4049, 19 },
1046
  { 82, 255, 2, 22, 4017, 19 },
1047
  { 185, 255, 2, 22, 4017, 19 },
1048
  { 270, 255, 2, 22, 4017, 19 },
1049
  { 355, 255, 2, 22, 4017, 19 },
1050
  { 435, 255, 2, 22, 4017, 19 },
1051
  { 515, 255, 2, 22, 4017, 19 },
1052
  { 585, 255, 2, 22, 4017, 19 },
1053
  { 655, 255, 2, 22, 4017, 19 },
1054
  { 722, 255, 2, 22, 4017, 19 },
1055
  { 781, 255, 2, 22, 4017, 19 },
1056
  { 12, 255, 2, 22, 4017, 19 },
1057
  { 115, 255, 2, 22, 4017, 19 },
1058
  { 218, 255, 2, 22, 4017, 19 },
1059
  { 303, 255, 2, 22, 4017, 19 },
1060
  { 388, 255, 2, 22, 4017, 19 },
1061
  { 468, 255, 2, 22, 4017, 19 },
1062
  { 548, 255, 2, 22, 4017, 19 },
1063
  { 618, 255, 2, 22, 4017, 19 },
1064
  { 688, 255, 2, 22, 4017, 19 },
1065
  { 747, 255, 2, 22, 4017, 19 },
1066
  { 40, 255, 2, 22, 4017, 19 },
1067
  { 143, 255, 2, 22, 4017, 19 },
1068
  { 246, 255, 2, 22, 4017, 19 },
1069
  { 331, 255, 2, 22, 4017, 19 },
1070
  { 416, 255, 2, 22, 4017, 19 },
1071
  { 496, 255, 2, 22, 4017, 19 },
1072
  { 566, 255, 2, 22, 4017, 19 },
1073
  { 636, 255, 2, 22, 4017, 19 },
1074
  { 706, 255, 2, 22, 4017, 19 },
1075
  { 765, 255, 2, 22, 4017, 19 },
1076
  { 58, 255, 2, 22, 4017, 19 },
1077
  { 161, 255, 2, 22, 4017, 19 },
1078
  { 824, 2, 243, 2, 3715, 0 },
1079
  { 828, 2, 243, 2, 3715, 0 },
1080
  { 794, 2, 243, 2, 3715, 0 },
1081
  { 799, 2, 243, 2, 3715, 0 },
1082
  { 804, 2, 243, 2, 3715, 0 },
1083
  { 809, 2, 243, 2, 3715, 0 },
1084
  { 814, 2, 243, 2, 3715, 0 },
1085
  { 819, 2, 243, 2, 3715, 0 },
1086
  { 912, 2, 239, 2, 3683, 0 },
1087
  { 917, 2, 239, 2, 3683, 0 },
1088
  { 876, 2, 239, 2, 3683, 0 },
1089
  { 882, 2, 239, 2, 3683, 0 },
1090
  { 888, 2, 239, 2, 3683, 0 },
1091
  { 894, 2, 239, 2, 3683, 0 },
1092
  { 900, 2, 239, 2, 3683, 0 },
1093
  { 906, 2, 239, 2, 3683, 0 },
1094
  { 862, 104, 237, 13, 51, 12 },
1095
  { 866, 104, 237, 13, 51, 12 },
1096
  { 832, 104, 237, 13, 51, 12 },
1097
  { 837, 104, 237, 13, 51, 12 },
1098
  { 842, 104, 237, 13, 51, 12 },
1099
  { 847, 104, 237, 13, 51, 12 },
1100
  { 852, 104, 237, 13, 51, 12 },
1101
  { 857, 104, 237, 13, 51, 12 },
1102
  { 1134, 62, 240, 3, 643, 5 },
1103
  { 1138, 62, 240, 3, 643, 5 },
1104
  { 1104, 62, 240, 3, 643, 5 },
1105
  { 1109, 62, 240, 3, 643, 5 },
1106
  { 1114, 62, 240, 3, 643, 5 },
1107
  { 1119, 62, 240, 3, 643, 5 },
1108
  { 1124, 62, 240, 3, 643, 5 },
1109
  { 1129, 62, 240, 3, 643, 5 },
1110
  { 980, 2, 236, 2, 3651, 0 },
1111
  { 985, 2, 236, 2, 3651, 0 },
1112
  { 944, 2, 236, 2, 3651, 0 },
1113
  { 950, 2, 236, 2, 3651, 0 },
1114
  { 956, 2, 236, 2, 3651, 0 },
1115
  { 962, 2, 236, 2, 3651, 0 },
1116
  { 968, 2, 236, 2, 3651, 0 },
1117
  { 974, 2, 236, 2, 3651, 0 },
1118
};
1119
1120
extern const MCPhysReg X86RegUnitRoots[][2] = {
1121
  { X86::AH },
1122
  { X86::AL },
1123
  { X86::BH },
1124
  { X86::BL },
1125
  { X86::BPL },
1126
  { X86::BPH },
1127
  { X86::CH },
1128
  { X86::CL },
1129
  { X86::CS },
1130
  { X86::DF },
1131
  { X86::DH },
1132
  { X86::DIL },
1133
  { X86::DIH },
1134
  { X86::DL },
1135
  { X86::DS },
1136
  { X86::HAX },
1137
  { X86::HBP },
1138
  { X86::HBX },
1139
  { X86::HCX },
1140
  { X86::HDI },
1141
  { X86::HDX },
1142
  { X86::EFLAGS },
1143
  { X86::IP },
1144
  { X86::HIP },
1145
  { X86::EIZ },
1146
  { X86::ES },
1147
  { X86::SIL },
1148
  { X86::SIH },
1149
  { X86::HSI },
1150
  { X86::SPL },
1151
  { X86::SPH },
1152
  { X86::HSP },
1153
  { X86::FPCW },
1154
  { X86::FPSW },
1155
  { X86::FS },
1156
  { X86::GS },
1157
  { X86::RIZ },
1158
  { X86::SS },
1159
  { X86::SSP },
1160
  { X86::BND0 },
1161
  { X86::BND1 },
1162
  { X86::BND2 },
1163
  { X86::BND3 },
1164
  { X86::CR0 },
1165
  { X86::CR1 },
1166
  { X86::CR2 },
1167
  { X86::CR3 },
1168
  { X86::CR4 },
1169
  { X86::CR5 },
1170
  { X86::CR6 },
1171
  { X86::CR7 },
1172
  { X86::CR8 },
1173
  { X86::CR9 },
1174
  { X86::CR10 },
1175
  { X86::CR11 },
1176
  { X86::CR12 },
1177
  { X86::CR13 },
1178
  { X86::CR14 },
1179
  { X86::CR15 },
1180
  { X86::DR0 },
1181
  { X86::DR1 },
1182
  { X86::DR2 },
1183
  { X86::DR3 },
1184
  { X86::DR4 },
1185
  { X86::DR5 },
1186
  { X86::DR6 },
1187
  { X86::DR7 },
1188
  { X86::DR8 },
1189
  { X86::DR9 },
1190
  { X86::DR10 },
1191
  { X86::DR11 },
1192
  { X86::DR12 },
1193
  { X86::DR13 },
1194
  { X86::DR14 },
1195
  { X86::DR15 },
1196
  { X86::FP0 },
1197
  { X86::FP1 },
1198
  { X86::FP2 },
1199
  { X86::FP3 },
1200
  { X86::FP4 },
1201
  { X86::FP5 },
1202
  { X86::FP6 },
1203
  { X86::FP7 },
1204
  { X86::K0 },
1205
  { X86::K1 },
1206
  { X86::K2 },
1207
  { X86::K3 },
1208
  { X86::K4 },
1209
  { X86::K5 },
1210
  { X86::K6 },
1211
  { X86::K7 },
1212
  { X86::MM0 },
1213
  { X86::MM1 },
1214
  { X86::MM2 },
1215
  { X86::MM3 },
1216
  { X86::MM4 },
1217
  { X86::MM5 },
1218
  { X86::MM6 },
1219
  { X86::MM7 },
1220
  { X86::R8B },
1221
  { X86::R8BH },
1222
  { X86::R8WH },
1223
  { X86::R9B },
1224
  { X86::R9BH },
1225
  { X86::R9WH },
1226
  { X86::R10B },
1227
  { X86::R10BH },
1228
  { X86::R10WH },
1229
  { X86::R11B },
1230
  { X86::R11BH },
1231
  { X86::R11WH },
1232
  { X86::R12B },
1233
  { X86::R12BH },
1234
  { X86::R12WH },
1235
  { X86::R13B },
1236
  { X86::R13BH },
1237
  { X86::R13WH },
1238
  { X86::R14B },
1239
  { X86::R14BH },
1240
  { X86::R14WH },
1241
  { X86::R15B },
1242
  { X86::R15BH },
1243
  { X86::R15WH },
1244
  { X86::ST0 },
1245
  { X86::ST1 },
1246
  { X86::ST2 },
1247
  { X86::ST3 },
1248
  { X86::ST4 },
1249
  { X86::ST5 },
1250
  { X86::ST6 },
1251
  { X86::ST7 },
1252
  { X86::XMM0 },
1253
  { X86::XMM1 },
1254
  { X86::XMM2 },
1255
  { X86::XMM3 },
1256
  { X86::XMM4 },
1257
  { X86::XMM5 },
1258
  { X86::XMM6 },
1259
  { X86::XMM7 },
1260
  { X86::XMM8 },
1261
  { X86::XMM9 },
1262
  { X86::XMM10 },
1263
  { X86::XMM11 },
1264
  { X86::XMM12 },
1265
  { X86::XMM13 },
1266
  { X86::XMM14 },
1267
  { X86::XMM15 },
1268
  { X86::XMM16 },
1269
  { X86::XMM17 },
1270
  { X86::XMM18 },
1271
  { X86::XMM19 },
1272
  { X86::XMM20 },
1273
  { X86::XMM21 },
1274
  { X86::XMM22 },
1275
  { X86::XMM23 },
1276
  { X86::XMM24 },
1277
  { X86::XMM25 },
1278
  { X86::XMM26 },
1279
  { X86::XMM27 },
1280
  { X86::XMM28 },
1281
  { X86::XMM29 },
1282
  { X86::XMM30 },
1283
  { X86::XMM31 },
1284
};
1285
1286
namespace {     // Register classes...
1287
  // GR8 Register Class...
1288
  const MCPhysReg GR8[] = {
1289
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 
1290
  };
1291
1292
  // GR8 Bit set.
1293
  const uint8_t GR8Bits[] = {
1294
    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1295
  };
1296
1297
  // GRH8 Register Class...
1298
  const MCPhysReg GRH8[] = {
1299
    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 
1300
  };
1301
1302
  // GRH8 Bit set.
1303
  const uint8_t GRH8Bits[] = {
1304
    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1305
  };
1306
1307
  // GR8_NOREX Register Class...
1308
  const MCPhysReg GR8_NOREX[] = {
1309
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
1310
  };
1311
1312
  // GR8_NOREX Bit set.
1313
  const uint8_t GR8_NOREXBits[] = {
1314
    0x36, 0x8c, 0x08, 
1315
  };
1316
1317
  // GR8_ABCD_H Register Class...
1318
  const MCPhysReg GR8_ABCD_H[] = {
1319
    X86::AH, X86::CH, X86::DH, X86::BH, 
1320
  };
1321
1322
  // GR8_ABCD_H Bit set.
1323
  const uint8_t GR8_ABCD_HBits[] = {
1324
    0x12, 0x84, 
1325
  };
1326
1327
  // GR8_ABCD_L Register Class...
1328
  const MCPhysReg GR8_ABCD_L[] = {
1329
    X86::AL, X86::CL, X86::DL, X86::BL, 
1330
  };
1331
1332
  // GR8_ABCD_L Bit set.
1333
  const uint8_t GR8_ABCD_LBits[] = {
1334
    0x24, 0x08, 0x08, 
1335
  };
1336
1337
  // GRH16 Register Class...
1338
  const MCPhysReg GRH16[] = {
1339
    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 
1340
  };
1341
1342
  // GRH16 Bit set.
1343
  const uint8_t GRH16Bits[] = {
1344
    0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1345
  };
1346
1347
  // GR16 Register Class...
1348
  const MCPhysReg GR16[] = {
1349
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 
1350
  };
1351
1352
  // GR16 Bit set.
1353
  const uint8_t GR16Bits[] = {
1354
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1355
  };
1356
1357
  // GR16_NOREX Register Class...
1358
  const MCPhysReg GR16_NOREX[] = {
1359
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
1360
  };
1361
1362
  // GR16_NOREX Bit set.
1363
  const uint8_t GR16_NOREXBits[] = {
1364
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x24, 
1365
  };
1366
1367
  // VK1 Register Class...
1368
  const MCPhysReg VK1[] = {
1369
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1370
  };
1371
1372
  // VK1 Bit set.
1373
  const uint8_t VK1Bits[] = {
1374
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1375
  };
1376
1377
  // VK16 Register Class...
1378
  const MCPhysReg VK16[] = {
1379
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1380
  };
1381
1382
  // VK16 Bit set.
1383
  const uint8_t VK16Bits[] = {
1384
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1385
  };
1386
1387
  // VK2 Register Class...
1388
  const MCPhysReg VK2[] = {
1389
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1390
  };
1391
1392
  // VK2 Bit set.
1393
  const uint8_t VK2Bits[] = {
1394
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1395
  };
1396
1397
  // VK4 Register Class...
1398
  const MCPhysReg VK4[] = {
1399
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1400
  };
1401
1402
  // VK4 Bit set.
1403
  const uint8_t VK4Bits[] = {
1404
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1405
  };
1406
1407
  // VK8 Register Class...
1408
  const MCPhysReg VK8[] = {
1409
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1410
  };
1411
1412
  // VK8 Bit set.
1413
  const uint8_t VK8Bits[] = {
1414
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1415
  };
1416
1417
  // VK16WM Register Class...
1418
  const MCPhysReg VK16WM[] = {
1419
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1420
  };
1421
1422
  // VK16WM Bit set.
1423
  const uint8_t VK16WMBits[] = {
1424
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1425
  };
1426
1427
  // VK1WM Register Class...
1428
  const MCPhysReg VK1WM[] = {
1429
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1430
  };
1431
1432
  // VK1WM Bit set.
1433
  const uint8_t VK1WMBits[] = {
1434
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1435
  };
1436
1437
  // VK2WM Register Class...
1438
  const MCPhysReg VK2WM[] = {
1439
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1440
  };
1441
1442
  // VK2WM Bit set.
1443
  const uint8_t VK2WMBits[] = {
1444
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1445
  };
1446
1447
  // VK4WM Register Class...
1448
  const MCPhysReg VK4WM[] = {
1449
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1450
  };
1451
1452
  // VK4WM Bit set.
1453
  const uint8_t VK4WMBits[] = {
1454
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1455
  };
1456
1457
  // VK8WM Register Class...
1458
  const MCPhysReg VK8WM[] = {
1459
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1460
  };
1461
1462
  // VK8WM Bit set.
1463
  const uint8_t VK8WMBits[] = {
1464
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1465
  };
1466
1467
  // SEGMENT_REG Register Class...
1468
  const MCPhysReg SEGMENT_REG[] = {
1469
    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 
1470
  };
1471
1472
  // SEGMENT_REG Bit set.
1473
  const uint8_t SEGMENT_REGBits[] = {
1474
    0x00, 0x10, 0x10, 0x80, 0x30, 0x00, 0x00, 0x00, 0x01, 
1475
  };
1476
1477
  // GR16_ABCD Register Class...
1478
  const MCPhysReg GR16_ABCD[] = {
1479
    X86::AX, X86::CX, X86::DX, X86::BX, 
1480
  };
1481
1482
  // GR16_ABCD Bit set.
1483
  const uint8_t GR16_ABCDBits[] = {
1484
    0x08, 0x22, 0x20, 
1485
  };
1486
1487
  // FPCCR Register Class...
1488
  const MCPhysReg FPCCR[] = {
1489
    X86::FPSW, 
1490
  };
1491
1492
  // FPCCR Bit set.
1493
  const uint8_t FPCCRBits[] = {
1494
    0x00, 0x00, 0x00, 0x00, 0x08, 
1495
  };
1496
1497
  // FR32X Register Class...
1498
  const MCPhysReg FR32X[] = {
1499
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1500
  };
1501
1502
  // FR32X Bit set.
1503
  const uint8_t FR32XBits[] = {
1504
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
1505
  };
1506
1507
  // LOW32_ADDR_ACCESS_RBP Register Class...
1508
  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
1509
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 
1510
  };
1511
1512
  // LOW32_ADDR_ACCESS_RBP Bit set.
1513
  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
1514
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1515
  };
1516
1517
  // LOW32_ADDR_ACCESS Register Class...
1518
  const MCPhysReg LOW32_ADDR_ACCESS[] = {
1519
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 
1520
  };
1521
1522
  // LOW32_ADDR_ACCESS Bit set.
1523
  const uint8_t LOW32_ADDR_ACCESSBits[] = {
1524
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1525
  };
1526
1527
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
1528
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
1529
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 
1530
  };
1531
1532
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
1533
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
1534
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1535
  };
1536
1537
  // DEBUG_REG Register Class...
1538
  const MCPhysReg DEBUG_REG[] = {
1539
    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 
1540
  };
1541
1542
  // DEBUG_REG Bit set.
1543
  const uint8_t DEBUG_REGBits[] = {
1544
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1545
  };
1546
1547
  // FR32 Register Class...
1548
  const MCPhysReg FR32[] = {
1549
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1550
  };
1551
1552
  // FR32 Bit set.
1553
  const uint8_t FR32Bits[] = {
1554
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1555
  };
1556
1557
  // GR32 Register Class...
1558
  const MCPhysReg GR32[] = {
1559
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1560
  };
1561
1562
  // GR32 Bit set.
1563
  const uint8_t GR32Bits[] = {
1564
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1565
  };
1566
1567
  // GR32_NOSP Register Class...
1568
  const MCPhysReg GR32_NOSP[] = {
1569
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
1570
  };
1571
1572
  // GR32_NOSP Bit set.
1573
  const uint8_t GR32_NOSPBits[] = {
1574
    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1575
  };
1576
1577
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1578
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1579
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 
1580
  };
1581
1582
  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1583
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1584
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x02, 
1585
  };
1586
1587
  // GR32_NOREX Register Class...
1588
  const MCPhysReg GR32_NOREX[] = {
1589
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
1590
  };
1591
1592
  // GR32_NOREX Bit set.
1593
  const uint8_t GR32_NOREXBits[] = {
1594
    0x00, 0x00, 0xc0, 0x0f, 0x03, 
1595
  };
1596
1597
  // VK32 Register Class...
1598
  const MCPhysReg VK32[] = {
1599
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1600
  };
1601
1602
  // VK32 Bit set.
1603
  const uint8_t VK32Bits[] = {
1604
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1605
  };
1606
1607
  // GR32_NOREX_NOSP Register Class...
1608
  const MCPhysReg GR32_NOREX_NOSP[] = {
1609
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 
1610
  };
1611
1612
  // GR32_NOREX_NOSP Bit set.
1613
  const uint8_t GR32_NOREX_NOSPBits[] = {
1614
    0x00, 0x00, 0xc0, 0x0f, 0x01, 
1615
  };
1616
1617
  // RFP32 Register Class...
1618
  const MCPhysReg RFP32[] = {
1619
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1620
  };
1621
1622
  // RFP32 Bit set.
1623
  const uint8_t RFP32Bits[] = {
1624
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1625
  };
1626
1627
  // VK32WM Register Class...
1628
  const MCPhysReg VK32WM[] = {
1629
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
1630
  };
1631
1632
  // VK32WM Bit set.
1633
  const uint8_t VK32WMBits[] = {
1634
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
1635
  };
1636
1637
  // GR32_ABCD Register Class...
1638
  const MCPhysReg GR32_ABCD[] = {
1639
    X86::EAX, X86::ECX, X86::EDX, X86::EBX, 
1640
  };
1641
1642
  // GR32_ABCD Bit set.
1643
  const uint8_t GR32_ABCDBits[] = {
1644
    0x00, 0x00, 0x40, 0x0b, 
1645
  };
1646
1647
  // GR32_TC Register Class...
1648
  const MCPhysReg GR32_TC[] = {
1649
    X86::EAX, X86::ECX, X86::EDX, X86::ESP, 
1650
  };
1651
1652
  // GR32_TC Bit set.
1653
  const uint8_t GR32_TCBits[] = {
1654
    0x00, 0x00, 0x40, 0x0a, 0x02, 
1655
  };
1656
1657
  // GR32_ABCD_and_GR32_TC Register Class...
1658
  const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
1659
    X86::EAX, X86::ECX, X86::EDX, 
1660
  };
1661
1662
  // GR32_ABCD_and_GR32_TC Bit set.
1663
  const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
1664
    0x00, 0x00, 0x40, 0x0a, 
1665
  };
1666
1667
  // GR32_AD Register Class...
1668
  const MCPhysReg GR32_AD[] = {
1669
    X86::EAX, X86::EDX, 
1670
  };
1671
1672
  // GR32_AD Bit set.
1673
  const uint8_t GR32_ADBits[] = {
1674
    0x00, 0x00, 0x40, 0x08, 
1675
  };
1676
1677
  // GR32_BPSP Register Class...
1678
  const MCPhysReg GR32_BPSP[] = {
1679
    X86::EBP, X86::ESP, 
1680
  };
1681
1682
  // GR32_BPSP Bit set.
1683
  const uint8_t GR32_BPSPBits[] = {
1684
    0x00, 0x00, 0x80, 0x00, 0x02, 
1685
  };
1686
1687
  // GR32_BSI Register Class...
1688
  const MCPhysReg GR32_BSI[] = {
1689
    X86::EBX, X86::ESI, 
1690
  };
1691
1692
  // GR32_BSI Bit set.
1693
  const uint8_t GR32_BSIBits[] = {
1694
    0x00, 0x00, 0x00, 0x01, 0x01, 
1695
  };
1696
1697
  // GR32_CB Register Class...
1698
  const MCPhysReg GR32_CB[] = {
1699
    X86::ECX, X86::EBX, 
1700
  };
1701
1702
  // GR32_CB Bit set.
1703
  const uint8_t GR32_CBBits[] = {
1704
    0x00, 0x00, 0x00, 0x03, 
1705
  };
1706
1707
  // GR32_DC Register Class...
1708
  const MCPhysReg GR32_DC[] = {
1709
    X86::EDX, X86::ECX, 
1710
  };
1711
1712
  // GR32_DC Bit set.
1713
  const uint8_t GR32_DCBits[] = {
1714
    0x00, 0x00, 0x00, 0x0a, 
1715
  };
1716
1717
  // GR32_DIBP Register Class...
1718
  const MCPhysReg GR32_DIBP[] = {
1719
    X86::EDI, X86::EBP, 
1720
  };
1721
1722
  // GR32_DIBP Bit set.
1723
  const uint8_t GR32_DIBPBits[] = {
1724
    0x00, 0x00, 0x80, 0x04, 
1725
  };
1726
1727
  // GR32_SIDI Register Class...
1728
  const MCPhysReg GR32_SIDI[] = {
1729
    X86::ESI, X86::EDI, 
1730
  };
1731
1732
  // GR32_SIDI Bit set.
1733
  const uint8_t GR32_SIDIBits[] = {
1734
    0x00, 0x00, 0x00, 0x04, 0x01, 
1735
  };
1736
1737
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1738
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1739
    X86::RIP, X86::RBP, 
1740
  };
1741
1742
  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1743
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1744
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 
1745
  };
1746
1747
  // CCR Register Class...
1748
  const MCPhysReg CCR[] = {
1749
    X86::EFLAGS, 
1750
  };
1751
1752
  // CCR Bit set.
1753
  const uint8_t CCRBits[] = {
1754
    0x00, 0x00, 0x00, 0x10, 
1755
  };
1756
1757
  // DFCCR Register Class...
1758
  const MCPhysReg DFCCR[] = {
1759
    X86::DF, 
1760
  };
1761
1762
  // DFCCR Bit set.
1763
  const uint8_t DFCCRBits[] = {
1764
    0x00, 0x40, 
1765
  };
1766
1767
  // GR32_ABCD_and_GR32_BSI Register Class...
1768
  const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
1769
    X86::EBX, 
1770
  };
1771
1772
  // GR32_ABCD_and_GR32_BSI Bit set.
1773
  const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
1774
    0x00, 0x00, 0x00, 0x01, 
1775
  };
1776
1777
  // GR32_AD_and_GR32_DC Register Class...
1778
  const MCPhysReg GR32_AD_and_GR32_DC[] = {
1779
    X86::EDX, 
1780
  };
1781
1782
  // GR32_AD_and_GR32_DC Bit set.
1783
  const uint8_t GR32_AD_and_GR32_DCBits[] = {
1784
    0x00, 0x00, 0x00, 0x08, 
1785
  };
1786
1787
  // GR32_BPSP_and_GR32_DIBP Register Class...
1788
  const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
1789
    X86::EBP, 
1790
  };
1791
1792
  // GR32_BPSP_and_GR32_DIBP Bit set.
1793
  const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
1794
    0x00, 0x00, 0x80, 
1795
  };
1796
1797
  // GR32_BPSP_and_GR32_TC Register Class...
1798
  const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
1799
    X86::ESP, 
1800
  };
1801
1802
  // GR32_BPSP_and_GR32_TC Bit set.
1803
  const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
1804
    0x00, 0x00, 0x00, 0x00, 0x02, 
1805
  };
1806
1807
  // GR32_BSI_and_GR32_SIDI Register Class...
1808
  const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
1809
    X86::ESI, 
1810
  };
1811
1812
  // GR32_BSI_and_GR32_SIDI Bit set.
1813
  const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
1814
    0x00, 0x00, 0x00, 0x00, 0x01, 
1815
  };
1816
1817
  // GR32_CB_and_GR32_DC Register Class...
1818
  const MCPhysReg GR32_CB_and_GR32_DC[] = {
1819
    X86::ECX, 
1820
  };
1821
1822
  // GR32_CB_and_GR32_DC Bit set.
1823
  const uint8_t GR32_CB_and_GR32_DCBits[] = {
1824
    0x00, 0x00, 0x00, 0x02, 
1825
  };
1826
1827
  // GR32_DIBP_and_GR32_SIDI Register Class...
1828
  const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
1829
    X86::EDI, 
1830
  };
1831
1832
  // GR32_DIBP_and_GR32_SIDI Bit set.
1833
  const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
1834
    0x00, 0x00, 0x00, 0x04, 
1835
  };
1836
1837
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1838
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1839
    X86::RBP, 
1840
  };
1841
1842
  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1843
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1844
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
1845
  };
1846
1847
  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1848
  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1849
    X86::RIP, 
1850
  };
1851
1852
  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1853
  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1854
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
1855
  };
1856
1857
  // RFP64 Register Class...
1858
  const MCPhysReg RFP64[] = {
1859
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
1860
  };
1861
1862
  // RFP64 Bit set.
1863
  const uint8_t RFP64Bits[] = {
1864
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
1865
  };
1866
1867
  // FR64X Register Class...
1868
  const MCPhysReg FR64X[] = {
1869
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
1870
  };
1871
1872
  // FR64X Bit set.
1873
  const uint8_t FR64XBits[] = {
1874
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
1875
  };
1876
1877
  // GR64 Register Class...
1878
  const MCPhysReg GR64[] = {
1879
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 
1880
  };
1881
1882
  // GR64 Bit set.
1883
  const uint8_t GR64Bits[] = {
1884
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1885
  };
1886
1887
  // CONTROL_REG Register Class...
1888
  const MCPhysReg CONTROL_REG[] = {
1889
    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 
1890
  };
1891
1892
  // CONTROL_REG Bit set.
1893
  const uint8_t CONTROL_REGBits[] = {
1894
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1895
  };
1896
1897
  // FR64 Register Class...
1898
  const MCPhysReg FR64[] = {
1899
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
1900
  };
1901
1902
  // FR64 Bit set.
1903
  const uint8_t FR64Bits[] = {
1904
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
1905
  };
1906
1907
  // GR64_with_sub_8bit Register Class...
1908
  const MCPhysReg GR64_with_sub_8bit[] = {
1909
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 
1910
  };
1911
1912
  // GR64_with_sub_8bit Bit set.
1913
  const uint8_t GR64_with_sub_8bitBits[] = {
1914
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1915
  };
1916
1917
  // GR64_NOSP Register Class...
1918
  const MCPhysReg GR64_NOSP[] = {
1919
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 
1920
  };
1921
1922
  // GR64_NOSP Bit set.
1923
  const uint8_t GR64_NOSPBits[] = {
1924
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
1925
  };
1926
1927
  // GR64_TC Register Class...
1928
  const MCPhysReg GR64_TC[] = {
1929
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
1930
  };
1931
1932
  // GR64_TC Bit set.
1933
  const uint8_t GR64_TCBits[] = {
1934
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
1935
  };
1936
1937
  // GR64_NOREX Register Class...
1938
  const MCPhysReg GR64_NOREX[] = {
1939
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 
1940
  };
1941
1942
  // GR64_NOREX Bit set.
1943
  const uint8_t GR64_NOREXBits[] = {
1944
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x03, 
1945
  };
1946
1947
  // GR64_TCW64 Register Class...
1948
  const MCPhysReg GR64_TCW64[] = {
1949
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP, 
1950
  };
1951
1952
  // GR64_TCW64 Bit set.
1953
  const uint8_t GR64_TCW64Bits[] = {
1954
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
1955
  };
1956
1957
  // GR64_TC_with_sub_8bit Register Class...
1958
  const MCPhysReg GR64_TC_with_sub_8bit[] = {
1959
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP, 
1960
  };
1961
1962
  // GR64_TC_with_sub_8bit Bit set.
1963
  const uint8_t GR64_TC_with_sub_8bitBits[] = {
1964
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
1965
  };
1966
1967
  // GR64_NOSP_and_GR64_TC Register Class...
1968
  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
1969
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 
1970
  };
1971
1972
  // GR64_NOSP_and_GR64_TC Bit set.
1973
  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
1974
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
1975
  };
1976
1977
  // GR64_TCW64_with_sub_8bit Register Class...
1978
  const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
1979
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP, 
1980
  };
1981
1982
  // GR64_TCW64_with_sub_8bit Bit set.
1983
  const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
1984
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
1985
  };
1986
1987
  // GR64_TC_and_GR64_TCW64 Register Class...
1988
  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1989
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
1990
  };
1991
1992
  // GR64_TC_and_GR64_TCW64 Bit set.
1993
  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1994
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
1995
  };
1996
1997
  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1998
  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1999
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 
2000
  };
2001
2002
  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2003
  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2004
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x03, 
2005
  };
2006
2007
  // VK64 Register Class...
2008
  const MCPhysReg VK64[] = {
2009
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
2010
  };
2011
2012
  // VK64 Bit set.
2013
  const uint8_t VK64Bits[] = {
2014
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2015
  };
2016
2017
  // VR64 Register Class...
2018
  const MCPhysReg VR64[] = {
2019
    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
2020
  };
2021
2022
  // VR64 Bit set.
2023
  const uint8_t VR64Bits[] = {
2024
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2025
  };
2026
2027
  // GR64_NOREX_NOSP Register Class...
2028
  const MCPhysReg GR64_NOREX_NOSP[] = {
2029
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 
2030
  };
2031
2032
  // GR64_NOREX_NOSP Bit set.
2033
  const uint8_t GR64_NOREX_NOSPBits[] = {
2034
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x01, 
2035
  };
2036
2037
  // GR64_NOREX_and_GR64_TC Register Class...
2038
  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2039
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP, 
2040
  };
2041
2042
  // GR64_NOREX_and_GR64_TC Bit set.
2043
  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2044
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x03, 
2045
  };
2046
2047
  // GR64_NOSP_and_GR64_TCW64 Register Class...
2048
  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
2049
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 
2050
  };
2051
2052
  // GR64_NOSP_and_GR64_TCW64 Bit set.
2053
  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
2054
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
2055
  };
2056
2057
  // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2058
  const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2059
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP, 
2060
  };
2061
2062
  // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2063
  const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2064
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
2065
  };
2066
2067
  // VK64WM Register Class...
2068
  const MCPhysReg VK64WM[] = {
2069
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
2070
  };
2071
2072
  // VK64WM Bit set.
2073
  const uint8_t VK64WMBits[] = {
2074
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
2075
  };
2076
2077
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
2078
  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
2079
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 
2080
  };
2081
2082
  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
2083
  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
2084
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x02, 
2085
  };
2086
2087
  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2088
  const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2089
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, 
2090
  };
2091
2092
  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2093
  const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2094
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39, 0x03, 
2095
  };
2096
2097
  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
2098
  const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
2099
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 
2100
  };
2101
2102
  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
2103
  const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
2104
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39, 0x01, 
2105
  };
2106
2107
  // GR64_NOREX_and_GR64_TCW64 Register Class...
2108
  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2109
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP, 
2110
  };
2111
2112
  // GR64_NOREX_and_GR64_TCW64 Bit set.
2113
  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2114
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x02, 
2115
  };
2116
2117
  // GR64_ABCD Register Class...
2118
  const MCPhysReg GR64_ABCD[] = {
2119
    X86::RAX, X86::RCX, X86::RDX, X86::RBX, 
2120
  };
2121
2122
  // GR64_ABCD Bit set.
2123
  const uint8_t GR64_ABCDBits[] = {
2124
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, 
2125
  };
2126
2127
  // GR64_with_sub_32bit_in_GR32_TC Register Class...
2128
  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2129
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, 
2130
  };
2131
2132
  // GR64_with_sub_32bit_in_GR32_TC Bit set.
2133
  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2134
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0x02, 
2135
  };
2136
2137
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2138
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2139
    X86::RAX, X86::RCX, X86::RDX, 
2140
  };
2141
2142
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2143
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2144
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 
2145
  };
2146
2147
  // GR64_AD Register Class...
2148
  const MCPhysReg GR64_AD[] = {
2149
    X86::RAX, X86::RDX, 
2150
  };
2151
2152
  // GR64_AD Bit set.
2153
  const uint8_t GR64_ADBits[] = {
2154
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 
2155
  };
2156
2157
  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2158
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2159
    X86::RBP, X86::RIP, 
2160
  };
2161
2162
  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2163
  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2164
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 
2165
  };
2166
2167
  // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2168
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2169
    X86::RBP, X86::RSP, 
2170
  };
2171
2172
  // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2173
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2174
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 
2175
  };
2176
2177
  // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2178
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2179
    X86::RSI, X86::RBX, 
2180
  };
2181
2182
  // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2183
  const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2184
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 
2185
  };
2186
2187
  // GR64_with_sub_32bit_in_GR32_CB Register Class...
2188
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2189
    X86::RCX, X86::RBX, 
2190
  };
2191
2192
  // GR64_with_sub_32bit_in_GR32_CB Bit set.
2193
  const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2194
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
2195
  };
2196
2197
  // GR64_with_sub_32bit_in_GR32_DC Register Class...
2198
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
2199
    X86::RCX, X86::RDX, 
2200
  };
2201
2202
  // GR64_with_sub_32bit_in_GR32_DC Bit set.
2203
  const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
2204
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 
2205
  };
2206
2207
  // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2208
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2209
    X86::RDI, X86::RBP, 
2210
  };
2211
2212
  // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2213
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2214
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 
2215
  };
2216
2217
  // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2218
  const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2219
    X86::RSI, X86::RDI, 
2220
  };
2221
2222
  // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2223
  const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2224
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 
2225
  };
2226
2227
  // GR64_and_LOW32_ADDR_ACCESS Register Class...
2228
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2229
    X86::RIP, 
2230
  };
2231
2232
  // GR64_and_LOW32_ADDR_ACCESS Bit set.
2233
  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2234
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
2235
  };
2236
2237
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2238
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2239
    X86::RBX, 
2240
  };
2241
2242
  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2243
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2244
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
2245
  };
2246
2247
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
2248
  const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
2249
    X86::RDX, 
2250
  };
2251
2252
  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
2253
  const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
2254
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2255
  };
2256
2257
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2258
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2259
    X86::RBP, 
2260
  };
2261
2262
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2263
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2264
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
2265
  };
2266
2267
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2268
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2269
    X86::RSP, 
2270
  };
2271
2272
  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2273
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2274
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
2275
  };
2276
2277
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2278
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2279
    X86::RSI, 
2280
  };
2281
2282
  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2283
  const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2284
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
2285
  };
2286
2287
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
2288
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
2289
    X86::RCX, 
2290
  };
2291
2292
  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
2293
  const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
2294
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
2295
  };
2296
2297
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2298
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2299
    X86::RDI, 
2300
  };
2301
2302
  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2303
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2304
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2305
  };
2306
2307
  // RST Register Class...
2308
  const MCPhysReg RST[] = {
2309
    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
2310
  };
2311
2312
  // RST Bit set.
2313
  const uint8_t RSTBits[] = {
2314
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2315
  };
2316
2317
  // RFP80 Register Class...
2318
  const MCPhysReg RFP80[] = {
2319
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
2320
  };
2321
2322
  // RFP80 Bit set.
2323
  const uint8_t RFP80Bits[] = {
2324
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 
2325
  };
2326
2327
  // RFP80_7 Register Class...
2328
  const MCPhysReg RFP80_7[] = {
2329
    X86::FP7, 
2330
  };
2331
2332
  // RFP80_7 Bit set.
2333
  const uint8_t RFP80_7Bits[] = {
2334
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2335
  };
2336
2337
  // VR128X Register Class...
2338
  const MCPhysReg VR128X[] = {
2339
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
2340
  };
2341
2342
  // VR128X Bit set.
2343
  const uint8_t VR128XBits[] = {
2344
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
2345
  };
2346
2347
  // VR128 Register Class...
2348
  const MCPhysReg VR128[] = {
2349
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2350
  };
2351
2352
  // VR128 Bit set.
2353
  const uint8_t VR128Bits[] = {
2354
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2355
  };
2356
2357
  // VR128H Register Class...
2358
  const MCPhysReg VR128H[] = {
2359
    X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
2360
  };
2361
2362
  // VR128H Bit set.
2363
  const uint8_t VR128HBits[] = {
2364
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2365
  };
2366
2367
  // VR128L Register Class...
2368
  const MCPhysReg VR128L[] = {
2369
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
2370
  };
2371
2372
  // VR128L Bit set.
2373
  const uint8_t VR128LBits[] = {
2374
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2375
  };
2376
2377
  // BNDR Register Class...
2378
  const MCPhysReg BNDR[] = {
2379
    X86::BND0, X86::BND1, X86::BND2, X86::BND3, 
2380
  };
2381
2382
  // BNDR Bit set.
2383
  const uint8_t BNDRBits[] = {
2384
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
2385
  };
2386
2387
  // VR256X Register Class...
2388
  const MCPhysReg VR256X[] = {
2389
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 
2390
  };
2391
2392
  // VR256X Bit set.
2393
  const uint8_t VR256XBits[] = {
2394
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
2395
  };
2396
2397
  // VR256 Register Class...
2398
  const MCPhysReg VR256[] = {
2399
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2400
  };
2401
2402
  // VR256 Bit set.
2403
  const uint8_t VR256Bits[] = {
2404
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2405
  };
2406
2407
  // VR256H Register Class...
2408
  const MCPhysReg VR256H[] = {
2409
    X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
2410
  };
2411
2412
  // VR256H Bit set.
2413
  const uint8_t VR256HBits[] = {
2414
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2415
  };
2416
2417
  // VR256L Register Class...
2418
  const MCPhysReg VR256L[] = {
2419
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 
2420
  };
2421
2422
  // VR256L Bit set.
2423
  const uint8_t VR256LBits[] = {
2424
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2425
  };
2426
2427
  // VR512 Register Class...
2428
  const MCPhysReg VR512[] = {
2429
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 
2430
  };
2431
2432
  // VR512 Bit set.
2433
  const uint8_t VR512Bits[] = {
2434
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
2435
  };
2436
2437
  // VR512_with_sub_xmm_in_FR32 Register Class...
2438
  const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
2439
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2440
  };
2441
2442
  // VR512_with_sub_xmm_in_FR32 Bit set.
2443
  const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
2444
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
2445
  };
2446
2447
  // VR512_with_sub_xmm_in_VR128H Register Class...
2448
  const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = {
2449
    X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
2450
  };
2451
2452
  // VR512_with_sub_xmm_in_VR128H Bit set.
2453
  const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = {
2454
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2455
  };
2456
2457
  // VR512_with_sub_xmm_in_VR128L Register Class...
2458
  const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = {
2459
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, 
2460
  };
2461
2462
  // VR512_with_sub_xmm_in_VR128L Bit set.
2463
  const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = {
2464
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
2465
  };
2466
2467
} // end anonymous namespace
2468
2469
extern const char X86RegClassStrings[] = {
2470
  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
2471
  /* 6 */ 'V', 'K', '1', 0,
2472
  /* 10 */ 'V', 'R', '5', '1', '2', 0,
2473
  /* 16 */ 'V', 'K', '3', '2', 0,
2474
  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
2475
  /* 27 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'F', 'R', '3', '2', 0,
2476
  /* 54 */ 'G', 'R', '3', '2', 0,
2477
  /* 59 */ 'V', 'K', '2', 0,
2478
  /* 63 */ 'V', 'K', '6', '4', 0,
2479
  /* 68 */ 'R', 'F', 'P', '6', '4', 0,
2480
  /* 74 */ 'F', 'R', '6', '4', 0,
2481
  /* 79 */ 'G', 'R', '6', '4', 0,
2482
  /* 84 */ 'V', 'R', '6', '4', 0,
2483
  /* 89 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2484
  /* 112 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2485
  /* 149 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
2486
  /* 175 */ 'V', 'K', '4', 0,
2487
  /* 179 */ 'G', 'R', 'H', '1', '6', 0,
2488
  /* 185 */ 'V', 'K', '1', '6', 0,
2489
  /* 190 */ 'G', 'R', '1', '6', 0,
2490
  /* 195 */ 'V', 'R', '2', '5', '6', 0,
2491
  /* 201 */ 'R', 'F', 'P', '8', '0', '_', '7', 0,
2492
  /* 209 */ 'V', 'R', '1', '2', '8', 0,
2493
  /* 215 */ 'G', 'R', 'H', '8', 0,
2494
  /* 220 */ 'V', 'K', '8', 0,
2495
  /* 224 */ 'G', 'R', '8', 0,
2496
  /* 228 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
2497
  /* 259 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2498
  /* 302 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2499
  /* 345 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
2500
  /* 376 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2501
  /* 421 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2502
  /* 466 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
2503
  /* 497 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2504
  /* 519 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2505
  /* 547 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
2506
  /* 570 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
2507
  /* 578 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
2508
  /* 586 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
2509
  /* 596 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
2510
  /* 606 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
2511
  /* 616 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
2512
  /* 626 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
2513
  /* 638 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
2514
  /* 650 */ 'V', 'R', '2', '5', '6', 'H', 0,
2515
  /* 657 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'H', 0,
2516
  /* 686 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
2517
  /* 697 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2518
  /* 743 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2519
  /* 790 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
2520
  /* 823 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2521
  /* 869 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
2522
  /* 901 */ 'V', 'R', '2', '5', '6', 'L', 0,
2523
  /* 908 */ 'V', 'R', '5', '1', '2', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'x', 'm', 'm', '_', 'i', 'n', '_', 'V', 'R', '1', '2', '8', 'L', 0,
2524
  /* 937 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
2525
  /* 948 */ 'V', 'K', '1', 'W', 'M', 0,
2526
  /* 954 */ 'V', 'K', '3', '2', 'W', 'M', 0,
2527
  /* 961 */ 'V', 'K', '2', 'W', 'M', 0,
2528
  /* 967 */ 'V', 'K', '6', '4', 'W', 'M', 0,
2529
  /* 974 */ 'V', 'K', '4', 'W', 'M', 0,
2530
  /* 980 */ 'V', 'K', '1', '6', 'W', 'M', 0,
2531
  /* 987 */ 'V', 'K', '8', 'W', 'M', 0,
2532
  /* 993 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2533
  /* 1040 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
2534
  /* 1073 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
2535
  /* 1104 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
2536
  /* 1114 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
2537
  /* 1124 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2538
  /* 1140 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
2539
  /* 1156 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
2540
  /* 1189 */ 'D', 'F', 'C', 'C', 'R', 0,
2541
  /* 1195 */ 'F', 'P', 'C', 'C', 'R', 0,
2542
  /* 1201 */ 'B', 'N', 'D', 'R', 0,
2543
  /* 1206 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
2544
  /* 1233 */ 'R', 'S', 'T', 0,
2545
  /* 1237 */ 'F', 'R', '3', '2', 'X', 0,
2546
  /* 1243 */ 'F', 'R', '6', '4', 'X', 0,
2547
  /* 1249 */ 'V', 'R', '2', '5', '6', 'X', 0,
2548
  /* 1256 */ 'V', 'R', '1', '2', '8', 'X', 0,
2549
  /* 1263 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
2550
  /* 1274 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
2551
  /* 1285 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2552
  /* 1331 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
2553
  /* 1382 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
2554
  /* 1392 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2555
  /* 1429 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2556
  /* 1462 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
2557
  /* 1513 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2558
  /* 1532 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2559
  /* 1557 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2560
  /* 1594 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
2561
};
2562
2563
extern const MCRegisterClass X86MCRegisterClasses[] = {
2564
  { GR8, GR8Bits, 224, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true },
2565
  { GRH8, GRH8Bits, 215, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, false },
2566
  { GR8_NOREX, GR8_NOREXBits, 1382, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, true },
2567
  { GR8_ABCD_H, GR8_ABCD_HBits, 686, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, true },
2568
  { GR8_ABCD_L, GR8_ABCD_LBits, 937, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, true },
2569
  { GRH16, GRH16Bits, 179, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 1, false },
2570
  { GR16, GR16Bits, 190, 16, sizeof(GR16Bits), X86::GR16RegClassID, 1, true },
2571
  { GR16_NOREX, GR16_NOREXBits, 1320, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 1, true },
2572
  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 1, true },
2573
  { VK16, VK16Bits, 185, 8, sizeof(VK16Bits), X86::VK16RegClassID, 1, true },
2574
  { VK2, VK2Bits, 59, 8, sizeof(VK2Bits), X86::VK2RegClassID, 1, true },
2575
  { VK4, VK4Bits, 175, 8, sizeof(VK4Bits), X86::VK4RegClassID, 1, true },
2576
  { VK8, VK8Bits, 220, 8, sizeof(VK8Bits), X86::VK8RegClassID, 1, true },
2577
  { VK16WM, VK16WMBits, 980, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 1, true },
2578
  { VK1WM, VK1WMBits, 948, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 1, true },
2579
  { VK2WM, VK2WMBits, 961, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 1, true },
2580
  { VK4WM, VK4WMBits, 974, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 1, true },
2581
  { VK8WM, VK8WMBits, 987, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 1, true },
2582
  { SEGMENT_REG, SEGMENT_REGBits, 638, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 1, true },
2583
  { GR16_ABCD, GR16_ABCDBits, 606, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 1, true },
2584
  { FPCCR, FPCCRBits, 1195, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, -1, false },
2585
  { FR32X, FR32XBits, 1237, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 1, true },
2586
  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1082, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2587
  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1215, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 1, true },
2588
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1594, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 1, true },
2589
  { DEBUG_REG, DEBUG_REGBits, 616, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 1, true },
2590
  { FR32, FR32Bits, 49, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true },
2591
  { GR32, GR32Bits, 54, 16, sizeof(GR32Bits), X86::GR32RegClassID, 1, true },
2592
  { GR32_NOSP, GR32_NOSPBits, 1104, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 1, true },
2593
  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1331, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2594
  { GR32_NOREX, GR32_NOREXBits, 1263, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 1, true },
2595
  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 1, true },
2596
  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1124, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 1, true },
2597
  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 1, true },
2598
  { VK32WM, VK32WMBits, 954, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 1, true },
2599
  { GR32_ABCD, GR32_ABCDBits, 586, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 1, true },
2600
  { GR32_TC, GR32_TCBits, 413, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 1, true },
2601
  { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 399, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 1, true },
2602
  { GR32_AD, GR32_ADBits, 570, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 1, true },
2603
  { GR32_BPSP, GR32_BPSPBits, 1179, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 1, true },
2604
  { GR32_BSI, GR32_BSIBits, 860, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 1, true },
2605
  { GR32_CB, GR32_CBBits, 251, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 1, true },
2606
  { GR32_DC, GR32_DCBits, 294, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 1, true },
2607
  { GR32_DIBP, GR32_DIBPBits, 1030, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 1, true },
2608
  { GR32_SIDI, GR32_SIDIBits, 733, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 1, true },
2609
  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1392, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 1, true },
2610
  { CCR, CCRBits, 1191, 1, sizeof(CCRBits), X86::CCRRegClassID, -1, false },
2611
  { DFCCR, DFCCRBits, 1189, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, -1, false },
2612
  { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 846, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2613
  { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 325, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 1, true },
2614
  { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1016, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2615
  { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 444, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 1, true },
2616
  { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 720, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2617
  { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 282, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 1, true },
2618
  { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 766, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2619
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1462, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 1, true },
2620
  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1429, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 1, true },
2621
  { RFP64, RFP64Bits, 68, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 1, true },
2622
  { FR64X, FR64XBits, 1243, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true },
2623
  { GR64, GR64Bits, 79, 17, sizeof(GR64Bits), X86::GR64RegClassID, 1, true },
2624
  { CONTROL_REG, CONTROL_REGBits, 626, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 1, true },
2625
  { FR64, FR64Bits, 74, 16, sizeof(FR64Bits), X86::FR64RegClassID, 1, true },
2626
  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1513, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 1, true },
2627
  { GR64_NOSP, GR64_NOSPBits, 1114, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 1, true },
2628
  { GR64_TC, GR64_TCBits, 511, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 1, true },
2629
  { GR64_NOREX, GR64_NOREXBits, 1274, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 1, true },
2630
  { GR64_TCW64, GR64_TCW64Bits, 101, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 1, true },
2631
  { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1572, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 1, true },
2632
  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 497, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 1, true },
2633
  { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1532, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 1, true },
2634
  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 89, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 1, true },
2635
  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1297, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2636
  { VK64, VK64Bits, 63, 8, sizeof(VK64Bits), X86::VK64RegClassID, 1, true },
2637
  { VR64, VR64Bits, 84, 8, sizeof(VR64Bits), X86::VR64RegClassID, 1, true },
2638
  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1140, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 1, true },
2639
  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 547, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 1, true },
2640
  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 124, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2641
  { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1557, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 1, true },
2642
  { VK64WM, VK64WMBits, 967, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 1, true },
2643
  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 112, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
2644
  { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1285, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
2645
  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 519, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 1, true },
2646
  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 149, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 1, true },
2647
  { GR64_ABCD, GR64_ABCDBits, 596, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 1, true },
2648
  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 466, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 1, true },
2649
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 376, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 1, true },
2650
  { GR64_AD, GR64_ADBits, 578, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 1, true },
2651
  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1073, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
2652
  { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1156, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 1, true },
2653
  { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 869, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 1, true },
2654
  { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 228, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 1, true },
2655
  { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 345, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 1, true },
2656
  { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1040, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 1, true },
2657
  { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 790, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 1, true },
2658
  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1206, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 1, true },
2659
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 823, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
2660
  { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 302, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 1, true },
2661
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 993, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
2662
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 421, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 1, true },
2663
  { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 697, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
2664
  { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 259, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 1, true },
2665
  { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 743, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
2666
  { RST, RSTBits, 1233, 8, sizeof(RSTBits), X86::RSTRegClassID, 1, false },
2667
  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 1, true },
2668
  { RFP80_7, RFP80_7Bits, 201, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 1, false },
2669
  { VR128X, VR128XBits, 1256, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 1, true },
2670
  { VR128, VR128Bits, 209, 16, sizeof(VR128Bits), X86::VR128RegClassID, 1, true },
2671
  { VR128H, VR128HBits, 679, 8, sizeof(VR128HBits), X86::VR128HRegClassID, 1, true },
2672
  { VR128L, VR128LBits, 930, 8, sizeof(VR128LBits), X86::VR128LRegClassID, 1, true },
2673
  { BNDR, BNDRBits, 1201, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 1, true },
2674
  { VR256X, VR256XBits, 1249, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 1, true },
2675
  { VR256, VR256Bits, 195, 16, sizeof(VR256Bits), X86::VR256RegClassID, 1, true },
2676
  { VR256H, VR256HBits, 650, 8, sizeof(VR256HBits), X86::VR256HRegClassID, 1, true },
2677
  { VR256L, VR256LBits, 901, 8, sizeof(VR256LBits), X86::VR256LRegClassID, 1, true },
2678
  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 1, true },
2679
  { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, 27, 16, sizeof(VR512_with_sub_xmm_in_FR32Bits), X86::VR512_with_sub_xmm_in_FR32RegClassID, 1, true },
2680
  { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, 657, 8, sizeof(VR512_with_sub_xmm_in_VR128HBits), X86::VR512_with_sub_xmm_in_VR128HRegClassID, 1, true },
2681
  { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, 908, 8, sizeof(VR512_with_sub_xmm_in_VR128LBits), X86::VR512_with_sub_xmm_in_VR128LRegClassID, 1, true },
2682
};
2683
2684
// X86 Dwarf<->LLVM register mappings.
2685
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2686
  { 0U, X86::RAX },
2687
  { 1U, X86::RDX },
2688
  { 2U, X86::RCX },
2689
  { 3U, X86::RBX },
2690
  { 4U, X86::RSI },
2691
  { 5U, X86::RDI },
2692
  { 6U, X86::RBP },
2693
  { 7U, X86::RSP },
2694
  { 8U, X86::R8 },
2695
  { 9U, X86::R9 },
2696
  { 10U, X86::R10 },
2697
  { 11U, X86::R11 },
2698
  { 12U, X86::R12 },
2699
  { 13U, X86::R13 },
2700
  { 14U, X86::R14 },
2701
  { 15U, X86::R15 },
2702
  { 16U, X86::RIP },
2703
  { 17U, X86::XMM0 },
2704
  { 18U, X86::XMM1 },
2705
  { 19U, X86::XMM2 },
2706
  { 20U, X86::XMM3 },
2707
  { 21U, X86::XMM4 },
2708
  { 22U, X86::XMM5 },
2709
  { 23U, X86::XMM6 },
2710
  { 24U, X86::XMM7 },
2711
  { 25U, X86::XMM8 },
2712
  { 26U, X86::XMM9 },
2713
  { 27U, X86::XMM10 },
2714
  { 28U, X86::XMM11 },
2715
  { 29U, X86::XMM12 },
2716
  { 30U, X86::XMM13 },
2717
  { 31U, X86::XMM14 },
2718
  { 32U, X86::XMM15 },
2719
  { 33U, X86::ST0 },
2720
  { 34U, X86::ST1 },
2721
  { 35U, X86::ST2 },
2722
  { 36U, X86::ST3 },
2723
  { 37U, X86::ST4 },
2724
  { 38U, X86::ST5 },
2725
  { 39U, X86::ST6 },
2726
  { 40U, X86::ST7 },
2727
  { 41U, X86::MM0 },
2728
  { 42U, X86::MM1 },
2729
  { 43U, X86::MM2 },
2730
  { 44U, X86::MM3 },
2731
  { 45U, X86::MM4 },
2732
  { 46U, X86::MM5 },
2733
  { 47U, X86::MM6 },
2734
  { 48U, X86::MM7 },
2735
  { 67U, X86::XMM16 },
2736
  { 68U, X86::XMM17 },
2737
  { 69U, X86::XMM18 },
2738
  { 70U, X86::XMM19 },
2739
  { 71U, X86::XMM20 },
2740
  { 72U, X86::XMM21 },
2741
  { 73U, X86::XMM22 },
2742
  { 74U, X86::XMM23 },
2743
  { 75U, X86::XMM24 },
2744
  { 76U, X86::XMM25 },
2745
  { 77U, X86::XMM26 },
2746
  { 78U, X86::XMM27 },
2747
  { 79U, X86::XMM28 },
2748
  { 80U, X86::XMM29 },
2749
  { 81U, X86::XMM30 },
2750
  { 82U, X86::XMM31 },
2751
  { 118U, X86::K0 },
2752
  { 119U, X86::K1 },
2753
  { 120U, X86::K2 },
2754
  { 121U, X86::K3 },
2755
  { 122U, X86::K4 },
2756
  { 123U, X86::K5 },
2757
  { 124U, X86::K6 },
2758
  { 125U, X86::K7 },
2759
};
2760
extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L);
2761
2762
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2763
  { 0U, X86::EAX },
2764
  { 1U, X86::ECX },
2765
  { 2U, X86::EDX },
2766
  { 3U, X86::EBX },
2767
  { 4U, X86::EBP },
2768
  { 5U, X86::ESP },
2769
  { 6U, X86::ESI },
2770
  { 7U, X86::EDI },
2771
  { 8U, X86::EIP },
2772
  { 12U, X86::ST0 },
2773
  { 13U, X86::ST1 },
2774
  { 14U, X86::ST2 },
2775
  { 15U, X86::ST3 },
2776
  { 16U, X86::ST4 },
2777
  { 17U, X86::ST5 },
2778
  { 18U, X86::ST6 },
2779
  { 19U, X86::ST7 },
2780
  { 21U, X86::XMM0 },
2781
  { 22U, X86::XMM1 },
2782
  { 23U, X86::XMM2 },
2783
  { 24U, X86::XMM3 },
2784
  { 25U, X86::XMM4 },
2785
  { 26U, X86::XMM5 },
2786
  { 27U, X86::XMM6 },
2787
  { 28U, X86::XMM7 },
2788
  { 29U, X86::MM0 },
2789
  { 30U, X86::MM1 },
2790
  { 31U, X86::MM2 },
2791
  { 32U, X86::MM3 },
2792
  { 33U, X86::MM4 },
2793
  { 34U, X86::MM5 },
2794
  { 35U, X86::MM6 },
2795
  { 36U, X86::MM7 },
2796
  { 93U, X86::K0 },
2797
  { 94U, X86::K1 },
2798
  { 95U, X86::K2 },
2799
  { 96U, X86::K3 },
2800
  { 97U, X86::K4 },
2801
  { 98U, X86::K5 },
2802
  { 99U, X86::K6 },
2803
  { 100U, X86::K7 },
2804
};
2805
extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L);
2806
2807
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2808
  { 0U, X86::EAX },
2809
  { 1U, X86::ECX },
2810
  { 2U, X86::EDX },
2811
  { 3U, X86::EBX },
2812
  { 4U, X86::ESP },
2813
  { 5U, X86::EBP },
2814
  { 6U, X86::ESI },
2815
  { 7U, X86::EDI },
2816
  { 8U, X86::EIP },
2817
  { 11U, X86::ST0 },
2818
  { 12U, X86::ST1 },
2819
  { 13U, X86::ST2 },
2820
  { 14U, X86::ST3 },
2821
  { 15U, X86::ST4 },
2822
  { 16U, X86::ST5 },
2823
  { 17U, X86::ST6 },
2824
  { 18U, X86::ST7 },
2825
  { 21U, X86::XMM0 },
2826
  { 22U, X86::XMM1 },
2827
  { 23U, X86::XMM2 },
2828
  { 24U, X86::XMM3 },
2829
  { 25U, X86::XMM4 },
2830
  { 26U, X86::XMM5 },
2831
  { 27U, X86::XMM6 },
2832
  { 28U, X86::XMM7 },
2833
  { 29U, X86::MM0 },
2834
  { 30U, X86::MM1 },
2835
  { 31U, X86::MM2 },
2836
  { 32U, X86::MM3 },
2837
  { 33U, X86::MM4 },
2838
  { 34U, X86::MM5 },
2839
  { 35U, X86::MM6 },
2840
  { 36U, X86::MM7 },
2841
  { 93U, X86::K0 },
2842
  { 94U, X86::K1 },
2843
  { 95U, X86::K2 },
2844
  { 96U, X86::K3 },
2845
  { 97U, X86::K4 },
2846
  { 98U, X86::K5 },
2847
  { 99U, X86::K6 },
2848
  { 100U, X86::K7 },
2849
};
2850
extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L);
2851
2852
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2853
  { 0U, X86::RAX },
2854
  { 1U, X86::RDX },
2855
  { 2U, X86::RCX },
2856
  { 3U, X86::RBX },
2857
  { 4U, X86::RSI },
2858
  { 5U, X86::RDI },
2859
  { 6U, X86::RBP },
2860
  { 7U, X86::RSP },
2861
  { 8U, X86::R8 },
2862
  { 9U, X86::R9 },
2863
  { 10U, X86::R10 },
2864
  { 11U, X86::R11 },
2865
  { 12U, X86::R12 },
2866
  { 13U, X86::R13 },
2867
  { 14U, X86::R14 },
2868
  { 15U, X86::R15 },
2869
  { 16U, X86::RIP },
2870
  { 17U, X86::XMM0 },
2871
  { 18U, X86::XMM1 },
2872
  { 19U, X86::XMM2 },
2873
  { 20U, X86::XMM3 },
2874
  { 21U, X86::XMM4 },
2875
  { 22U, X86::XMM5 },
2876
  { 23U, X86::XMM6 },
2877
  { 24U, X86::XMM7 },
2878
  { 25U, X86::XMM8 },
2879
  { 26U, X86::XMM9 },
2880
  { 27U, X86::XMM10 },
2881
  { 28U, X86::XMM11 },
2882
  { 29U, X86::XMM12 },
2883
  { 30U, X86::XMM13 },
2884
  { 31U, X86::XMM14 },
2885
  { 32U, X86::XMM15 },
2886
  { 33U, X86::ST0 },
2887
  { 34U, X86::ST1 },
2888
  { 35U, X86::ST2 },
2889
  { 36U, X86::ST3 },
2890
  { 37U, X86::ST4 },
2891
  { 38U, X86::ST5 },
2892
  { 39U, X86::ST6 },
2893
  { 40U, X86::ST7 },
2894
  { 41U, X86::MM0 },
2895
  { 42U, X86::MM1 },
2896
  { 43U, X86::MM2 },
2897
  { 44U, X86::MM3 },
2898
  { 45U, X86::MM4 },
2899
  { 46U, X86::MM5 },
2900
  { 47U, X86::MM6 },
2901
  { 48U, X86::MM7 },
2902
  { 67U, X86::XMM16 },
2903
  { 68U, X86::XMM17 },
2904
  { 69U, X86::XMM18 },
2905
  { 70U, X86::XMM19 },
2906
  { 71U, X86::XMM20 },
2907
  { 72U, X86::XMM21 },
2908
  { 73U, X86::XMM22 },
2909
  { 74U, X86::XMM23 },
2910
  { 75U, X86::XMM24 },
2911
  { 76U, X86::XMM25 },
2912
  { 77U, X86::XMM26 },
2913
  { 78U, X86::XMM27 },
2914
  { 79U, X86::XMM28 },
2915
  { 80U, X86::XMM29 },
2916
  { 81U, X86::XMM30 },
2917
  { 82U, X86::XMM31 },
2918
  { 118U, X86::K0 },
2919
  { 119U, X86::K1 },
2920
  { 120U, X86::K2 },
2921
  { 121U, X86::K3 },
2922
  { 122U, X86::K4 },
2923
  { 123U, X86::K5 },
2924
  { 124U, X86::K6 },
2925
  { 125U, X86::K7 },
2926
};
2927
extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L);
2928
2929
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
2930
  { 0U, X86::EAX },
2931
  { 1U, X86::ECX },
2932
  { 2U, X86::EDX },
2933
  { 3U, X86::EBX },
2934
  { 4U, X86::EBP },
2935
  { 5U, X86::ESP },
2936
  { 6U, X86::ESI },
2937
  { 7U, X86::EDI },
2938
  { 8U, X86::EIP },
2939
  { 12U, X86::ST0 },
2940
  { 13U, X86::ST1 },
2941
  { 14U, X86::ST2 },
2942
  { 15U, X86::ST3 },
2943
  { 16U, X86::ST4 },
2944
  { 17U, X86::ST5 },
2945
  { 18U, X86::ST6 },
2946
  { 19U, X86::ST7 },
2947
  { 21U, X86::XMM0 },
2948
  { 22U, X86::XMM1 },
2949
  { 23U, X86::XMM2 },
2950
  { 24U, X86::XMM3 },
2951
  { 25U, X86::XMM4 },
2952
  { 26U, X86::XMM5 },
2953
  { 27U, X86::XMM6 },
2954
  { 28U, X86::XMM7 },
2955
  { 29U, X86::MM0 },
2956
  { 30U, X86::MM1 },
2957
  { 31U, X86::MM2 },
2958
  { 32U, X86::MM3 },
2959
  { 33U, X86::MM4 },
2960
  { 34U, X86::MM5 },
2961
  { 35U, X86::MM6 },
2962
  { 36U, X86::MM7 },
2963
  { 93U, X86::K0 },
2964
  { 94U, X86::K1 },
2965
  { 95U, X86::K2 },
2966
  { 96U, X86::K3 },
2967
  { 97U, X86::K4 },
2968
  { 98U, X86::K5 },
2969
  { 99U, X86::K6 },
2970
  { 100U, X86::K7 },
2971
};
2972
extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L);
2973
2974
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
2975
  { 0U, X86::EAX },
2976
  { 1U, X86::ECX },
2977
  { 2U, X86::EDX },
2978
  { 3U, X86::EBX },
2979
  { 4U, X86::ESP },
2980
  { 5U, X86::EBP },
2981
  { 6U, X86::ESI },
2982
  { 7U, X86::EDI },
2983
  { 8U, X86::EIP },
2984
  { 11U, X86::ST0 },
2985
  { 12U, X86::ST1 },
2986
  { 13U, X86::ST2 },
2987
  { 14U, X86::ST3 },
2988
  { 15U, X86::ST4 },
2989
  { 16U, X86::ST5 },
2990
  { 17U, X86::ST6 },
2991
  { 18U, X86::ST7 },
2992
  { 21U, X86::XMM0 },
2993
  { 22U, X86::XMM1 },
2994
  { 23U, X86::XMM2 },
2995
  { 24U, X86::XMM3 },
2996
  { 25U, X86::XMM4 },
2997
  { 26U, X86::XMM5 },
2998
  { 27U, X86::XMM6 },
2999
  { 28U, X86::XMM7 },
3000
  { 29U, X86::MM0 },
3001
  { 30U, X86::MM1 },
3002
  { 31U, X86::MM2 },
3003
  { 32U, X86::MM3 },
3004
  { 33U, X86::MM4 },
3005
  { 34U, X86::MM5 },
3006
  { 35U, X86::MM6 },
3007
  { 36U, X86::MM7 },
3008
  { 93U, X86::K0 },
3009
  { 94U, X86::K1 },
3010
  { 95U, X86::K2 },
3011
  { 96U, X86::K3 },
3012
  { 97U, X86::K4 },
3013
  { 98U, X86::K5 },
3014
  { 99U, X86::K6 },
3015
  { 100U, X86::K7 },
3016
};
3017
extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L);
3018
3019
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3020
  { X86::EAX, -2U },
3021
  { X86::EBP, -2U },
3022
  { X86::EBX, -2U },
3023
  { X86::ECX, -2U },
3024
  { X86::EDI, -2U },
3025
  { X86::EDX, -2U },
3026
  { X86::EIP, -2U },
3027
  { X86::ESI, -2U },
3028
  { X86::ESP, -2U },
3029
  { X86::RAX, 0U },
3030
  { X86::RBP, 6U },
3031
  { X86::RBX, 3U },
3032
  { X86::RCX, 2U },
3033
  { X86::RDI, 5U },
3034
  { X86::RDX, 1U },
3035
  { X86::RIP, 16U },
3036
  { X86::RSI, 4U },
3037
  { X86::RSP, 7U },
3038
  { X86::K0, 118U },
3039
  { X86::K1, 119U },
3040
  { X86::K2, 120U },
3041
  { X86::K3, 121U },
3042
  { X86::K4, 122U },
3043
  { X86::K5, 123U },
3044
  { X86::K6, 124U },
3045
  { X86::K7, 125U },
3046
  { X86::MM0, 41U },
3047
  { X86::MM1, 42U },
3048
  { X86::MM2, 43U },
3049
  { X86::MM3, 44U },
3050
  { X86::MM4, 45U },
3051
  { X86::MM5, 46U },
3052
  { X86::MM6, 47U },
3053
  { X86::MM7, 48U },
3054
  { X86::R8, 8U },
3055
  { X86::R9, 9U },
3056
  { X86::R10, 10U },
3057
  { X86::R11, 11U },
3058
  { X86::R12, 12U },
3059
  { X86::R13, 13U },
3060
  { X86::R14, 14U },
3061
  { X86::R15, 15U },
3062
  { X86::ST0, 33U },
3063
  { X86::ST1, 34U },
3064
  { X86::ST2, 35U },
3065
  { X86::ST3, 36U },
3066
  { X86::ST4, 37U },
3067
  { X86::ST5, 38U },
3068
  { X86::ST6, 39U },
3069
  { X86::ST7, 40U },
3070
  { X86::XMM0, 17U },
3071
  { X86::XMM1, 18U },
3072
  { X86::XMM2, 19U },
3073
  { X86::XMM3, 20U },
3074
  { X86::XMM4, 21U },
3075
  { X86::XMM5, 22U },
3076
  { X86::XMM6, 23U },
3077
  { X86::XMM7, 24U },
3078
  { X86::XMM8, 25U },
3079
  { X86::XMM9, 26U },
3080
  { X86::XMM10, 27U },
3081
  { X86::XMM11, 28U },
3082
  { X86::XMM12, 29U },
3083
  { X86::XMM13, 30U },
3084
  { X86::XMM14, 31U },
3085
  { X86::XMM15, 32U },
3086
  { X86::XMM16, 67U },
3087
  { X86::XMM17, 68U },
3088
  { X86::XMM18, 69U },
3089
  { X86::XMM19, 70U },
3090
  { X86::XMM20, 71U },
3091
  { X86::XMM21, 72U },
3092
  { X86::XMM22, 73U },
3093
  { X86::XMM23, 74U },
3094
  { X86::XMM24, 75U },
3095
  { X86::XMM25, 76U },
3096
  { X86::XMM26, 77U },
3097
  { X86::XMM27, 78U },
3098
  { X86::XMM28, 79U },
3099
  { X86::XMM29, 80U },
3100
  { X86::XMM30, 81U },
3101
  { X86::XMM31, 82U },
3102
  { X86::YMM0, 17U },
3103
  { X86::YMM1, 18U },
3104
  { X86::YMM2, 19U },
3105
  { X86::YMM3, 20U },
3106
  { X86::YMM4, 21U },
3107
  { X86::YMM5, 22U },
3108
  { X86::YMM6, 23U },
3109
  { X86::YMM7, 24U },
3110
  { X86::YMM8, 25U },
3111
  { X86::YMM9, 26U },
3112
  { X86::YMM10, 27U },
3113
  { X86::YMM11, 28U },
3114
  { X86::YMM12, 29U },
3115
  { X86::YMM13, 30U },
3116
  { X86::YMM14, 31U },
3117
  { X86::YMM15, 32U },
3118
  { X86::YMM16, 67U },
3119
  { X86::YMM17, 68U },
3120
  { X86::YMM18, 69U },
3121
  { X86::YMM19, 70U },
3122
  { X86::YMM20, 71U },
3123
  { X86::YMM21, 72U },
3124
  { X86::YMM22, 73U },
3125
  { X86::YMM23, 74U },
3126
  { X86::YMM24, 75U },
3127
  { X86::YMM25, 76U },
3128
  { X86::YMM26, 77U },
3129
  { X86::YMM27, 78U },
3130
  { X86::YMM28, 79U },
3131
  { X86::YMM29, 80U },
3132
  { X86::YMM30, 81U },
3133
  { X86::YMM31, 82U },
3134
  { X86::ZMM0, 17U },
3135
  { X86::ZMM1, 18U },
3136
  { X86::ZMM2, 19U },
3137
  { X86::ZMM3, 20U },
3138
  { X86::ZMM4, 21U },
3139
  { X86::ZMM5, 22U },
3140
  { X86::ZMM6, 23U },
3141
  { X86::ZMM7, 24U },
3142
  { X86::ZMM8, 25U },
3143
  { X86::ZMM9, 26U },
3144
  { X86::ZMM10, 27U },
3145
  { X86::ZMM11, 28U },
3146
  { X86::ZMM12, 29U },
3147
  { X86::ZMM13, 30U },
3148
  { X86::ZMM14, 31U },
3149
  { X86::ZMM15, 32U },
3150
  { X86::ZMM16, 67U },
3151
  { X86::ZMM17, 68U },
3152
  { X86::ZMM18, 69U },
3153
  { X86::ZMM19, 70U },
3154
  { X86::ZMM20, 71U },
3155
  { X86::ZMM21, 72U },
3156
  { X86::ZMM22, 73U },
3157
  { X86::ZMM23, 74U },
3158
  { X86::ZMM24, 75U },
3159
  { X86::ZMM25, 76U },
3160
  { X86::ZMM26, 77U },
3161
  { X86::ZMM27, 78U },
3162
  { X86::ZMM28, 79U },
3163
  { X86::ZMM29, 80U },
3164
  { X86::ZMM30, 81U },
3165
  { X86::ZMM31, 82U },
3166
};
3167
extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf);
3168
3169
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3170
  { X86::EAX, 0U },
3171
  { X86::EBP, 4U },
3172
  { X86::EBX, 3U },
3173
  { X86::ECX, 1U },
3174
  { X86::EDI, 7U },
3175
  { X86::EDX, 2U },
3176
  { X86::EIP, 8U },
3177
  { X86::ESI, 6U },
3178
  { X86::ESP, 5U },
3179
  { X86::RAX, -2U },
3180
  { X86::RBP, -2U },
3181
  { X86::RBX, -2U },
3182
  { X86::RCX, -2U },
3183
  { X86::RDI, -2U },
3184
  { X86::RDX, -2U },
3185
  { X86::RIP, -2U },
3186
  { X86::RSI, -2U },
3187
  { X86::RSP, -2U },
3188
  { X86::K0, 93U },
3189
  { X86::K1, 94U },
3190
  { X86::K2, 95U },
3191
  { X86::K3, 96U },
3192
  { X86::K4, 97U },
3193
  { X86::K5, 98U },
3194
  { X86::K6, 99U },
3195
  { X86::K7, 100U },
3196
  { X86::MM0, 29U },
3197
  { X86::MM1, 30U },
3198
  { X86::MM2, 31U },
3199
  { X86::MM3, 32U },
3200
  { X86::MM4, 33U },
3201
  { X86::MM5, 34U },
3202
  { X86::MM6, 35U },
3203
  { X86::MM7, 36U },
3204
  { X86::R8, -2U },
3205
  { X86::R9, -2U },
3206
  { X86::R10, -2U },
3207
  { X86::R11, -2U },
3208
  { X86::R12, -2U },
3209
  { X86::R13, -2U },
3210
  { X86::R14, -2U },
3211
  { X86::R15, -2U },
3212
  { X86::ST0, 12U },
3213
  { X86::ST1, 13U },
3214
  { X86::ST2, 14U },
3215
  { X86::ST3, 15U },
3216
  { X86::ST4, 16U },
3217
  { X86::ST5, 17U },
3218
  { X86::ST6, 18U },
3219
  { X86::ST7, 19U },
3220
  { X86::XMM0, 21U },
3221
  { X86::XMM1, 22U },
3222
  { X86::XMM2, 23U },
3223
  { X86::XMM3, 24U },
3224
  { X86::XMM4, 25U },
3225
  { X86::XMM5, 26U },
3226
  { X86::XMM6, 27U },
3227
  { X86::XMM7, 28U },
3228
  { X86::XMM8, -2U },
3229
  { X86::XMM9, -2U },
3230
  { X86::XMM10, -2U },
3231
  { X86::XMM11, -2U },
3232
  { X86::XMM12, -2U },
3233
  { X86::XMM13, -2U },
3234
  { X86::XMM14, -2U },
3235
  { X86::XMM15, -2U },
3236
  { X86::XMM16, -2U },
3237
  { X86::XMM17, -2U },
3238
  { X86::XMM18, -2U },
3239
  { X86::XMM19, -2U },
3240
  { X86::XMM20, -2U },
3241
  { X86::XMM21, -2U },
3242
  { X86::XMM22, -2U },
3243
  { X86::XMM23, -2U },
3244
  { X86::XMM24, -2U },
3245
  { X86::XMM25, -2U },
3246
  { X86::XMM26, -2U },
3247
  { X86::XMM27, -2U },
3248
  { X86::XMM28, -2U },
3249
  { X86::XMM29, -2U },
3250
  { X86::XMM30, -2U },
3251
  { X86::XMM31, -2U },
3252
  { X86::YMM0, 21U },
3253
  { X86::YMM1, 22U },
3254
  { X86::YMM2, 23U },
3255
  { X86::YMM3, 24U },
3256
  { X86::YMM4, 25U },
3257
  { X86::YMM5, 26U },
3258
  { X86::YMM6, 27U },
3259
  { X86::YMM7, 28U },
3260
  { X86::YMM8, -2U },
3261
  { X86::YMM9, -2U },
3262
  { X86::YMM10, -2U },
3263
  { X86::YMM11, -2U },
3264
  { X86::YMM12, -2U },
3265
  { X86::YMM13, -2U },
3266
  { X86::YMM14, -2U },
3267
  { X86::YMM15, -2U },
3268
  { X86::YMM16, -2U },
3269
  { X86::YMM17, -2U },
3270
  { X86::YMM18, -2U },
3271
  { X86::YMM19, -2U },
3272
  { X86::YMM20, -2U },
3273
  { X86::YMM21, -2U },
3274
  { X86::YMM22, -2U },
3275
  { X86::YMM23, -2U },
3276
  { X86::YMM24, -2U },
3277
  { X86::YMM25, -2U },
3278
  { X86::YMM26, -2U },
3279
  { X86::YMM27, -2U },
3280
  { X86::YMM28, -2U },
3281
  { X86::YMM29, -2U },
3282
  { X86::YMM30, -2U },
3283
  { X86::YMM31, -2U },
3284
  { X86::ZMM0, 21U },
3285
  { X86::ZMM1, 22U },
3286
  { X86::ZMM2, 23U },
3287
  { X86::ZMM3, 24U },
3288
  { X86::ZMM4, 25U },
3289
  { X86::ZMM5, 26U },
3290
  { X86::ZMM6, 27U },
3291
  { X86::ZMM7, 28U },
3292
  { X86::ZMM8, -2U },
3293
  { X86::ZMM9, -2U },
3294
  { X86::ZMM10, -2U },
3295
  { X86::ZMM11, -2U },
3296
  { X86::ZMM12, -2U },
3297
  { X86::ZMM13, -2U },
3298
  { X86::ZMM14, -2U },
3299
  { X86::ZMM15, -2U },
3300
  { X86::ZMM16, -2U },
3301
  { X86::ZMM17, -2U },
3302
  { X86::ZMM18, -2U },
3303
  { X86::ZMM19, -2U },
3304
  { X86::ZMM20, -2U },
3305
  { X86::ZMM21, -2U },
3306
  { X86::ZMM22, -2U },
3307
  { X86::ZMM23, -2U },
3308
  { X86::ZMM24, -2U },
3309
  { X86::ZMM25, -2U },
3310
  { X86::ZMM26, -2U },
3311
  { X86::ZMM27, -2U },
3312
  { X86::ZMM28, -2U },
3313
  { X86::ZMM29, -2U },
3314
  { X86::ZMM30, -2U },
3315
  { X86::ZMM31, -2U },
3316
};
3317
extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf);
3318
3319
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3320
  { X86::EAX, 0U },
3321
  { X86::EBP, 5U },
3322
  { X86::EBX, 3U },
3323
  { X86::ECX, 1U },
3324
  { X86::EDI, 7U },
3325
  { X86::EDX, 2U },
3326
  { X86::EIP, 8U },
3327
  { X86::ESI, 6U },
3328
  { X86::ESP, 4U },
3329
  { X86::RAX, -2U },
3330
  { X86::RBP, -2U },
3331
  { X86::RBX, -2U },
3332
  { X86::RCX, -2U },
3333
  { X86::RDI, -2U },
3334
  { X86::RDX, -2U },
3335
  { X86::RIP, -2U },
3336
  { X86::RSI, -2U },
3337
  { X86::RSP, -2U },
3338
  { X86::K0, 93U },
3339
  { X86::K1, 94U },
3340
  { X86::K2, 95U },
3341
  { X86::K3, 96U },
3342
  { X86::K4, 97U },
3343
  { X86::K5, 98U },
3344
  { X86::K6, 99U },
3345
  { X86::K7, 100U },
3346
  { X86::MM0, 29U },
3347
  { X86::MM1, 30U },
3348
  { X86::MM2, 31U },
3349
  { X86::MM3, 32U },
3350
  { X86::MM4, 33U },
3351
  { X86::MM5, 34U },
3352
  { X86::MM6, 35U },
3353
  { X86::MM7, 36U },
3354
  { X86::R8, -2U },
3355
  { X86::R9, -2U },
3356
  { X86::R10, -2U },
3357
  { X86::R11, -2U },
3358
  { X86::R12, -2U },
3359
  { X86::R13, -2U },
3360
  { X86::R14, -2U },
3361
  { X86::R15, -2U },
3362
  { X86::ST0, 11U },
3363
  { X86::ST1, 12U },
3364
  { X86::ST2, 13U },
3365
  { X86::ST3, 14U },
3366
  { X86::ST4, 15U },
3367
  { X86::ST5, 16U },
3368
  { X86::ST6, 17U },
3369
  { X86::ST7, 18U },
3370
  { X86::XMM0, 21U },
3371
  { X86::XMM1, 22U },
3372
  { X86::XMM2, 23U },
3373
  { X86::XMM3, 24U },
3374
  { X86::XMM4, 25U },
3375
  { X86::XMM5, 26U },
3376
  { X86::XMM6, 27U },
3377
  { X86::XMM7, 28U },
3378
  { X86::XMM8, -2U },
3379
  { X86::XMM9, -2U },
3380
  { X86::XMM10, -2U },
3381
  { X86::XMM11, -2U },
3382
  { X86::XMM12, -2U },
3383
  { X86::XMM13, -2U },
3384
  { X86::XMM14, -2U },
3385
  { X86::XMM15, -2U },
3386
  { X86::XMM16, -2U },
3387
  { X86::XMM17, -2U },
3388
  { X86::XMM18, -2U },
3389
  { X86::XMM19, -2U },
3390
  { X86::XMM20, -2U },
3391
  { X86::XMM21, -2U },
3392
  { X86::XMM22, -2U },
3393
  { X86::XMM23, -2U },
3394
  { X86::XMM24, -2U },
3395
  { X86::XMM25, -2U },
3396
  { X86::XMM26, -2U },
3397
  { X86::XMM27, -2U },
3398
  { X86::XMM28, -2U },
3399
  { X86::XMM29, -2U },
3400
  { X86::XMM30, -2U },
3401
  { X86::XMM31, -2U },
3402
  { X86::YMM0, 21U },
3403
  { X86::YMM1, 22U },
3404
  { X86::YMM2, 23U },
3405
  { X86::YMM3, 24U },
3406
  { X86::YMM4, 25U },
3407
  { X86::YMM5, 26U },
3408
  { X86::YMM6, 27U },
3409
  { X86::YMM7, 28U },
3410
  { X86::YMM8, -2U },
3411
  { X86::YMM9, -2U },
3412
  { X86::YMM10, -2U },
3413
  { X86::YMM11, -2U },
3414
  { X86::YMM12, -2U },
3415
  { X86::YMM13, -2U },
3416
  { X86::YMM14, -2U },
3417
  { X86::YMM15, -2U },
3418
  { X86::YMM16, -2U },
3419
  { X86::YMM17, -2U },
3420
  { X86::YMM18, -2U },
3421
  { X86::YMM19, -2U },
3422
  { X86::YMM20, -2U },
3423
  { X86::YMM21, -2U },
3424
  { X86::YMM22, -2U },
3425
  { X86::YMM23, -2U },
3426
  { X86::YMM24, -2U },
3427
  { X86::YMM25, -2U },
3428
  { X86::YMM26, -2U },
3429
  { X86::YMM27, -2U },
3430
  { X86::YMM28, -2U },
3431
  { X86::YMM29, -2U },
3432
  { X86::YMM30, -2U },
3433
  { X86::YMM31, -2U },
3434
  { X86::ZMM0, 21U },
3435
  { X86::ZMM1, 22U },
3436
  { X86::ZMM2, 23U },
3437
  { X86::ZMM3, 24U },
3438
  { X86::ZMM4, 25U },
3439
  { X86::ZMM5, 26U },
3440
  { X86::ZMM6, 27U },
3441
  { X86::ZMM7, 28U },
3442
  { X86::ZMM8, -2U },
3443
  { X86::ZMM9, -2U },
3444
  { X86::ZMM10, -2U },
3445
  { X86::ZMM11, -2U },
3446
  { X86::ZMM12, -2U },
3447
  { X86::ZMM13, -2U },
3448
  { X86::ZMM14, -2U },
3449
  { X86::ZMM15, -2U },
3450
  { X86::ZMM16, -2U },
3451
  { X86::ZMM17, -2U },
3452
  { X86::ZMM18, -2U },
3453
  { X86::ZMM19, -2U },
3454
  { X86::ZMM20, -2U },
3455
  { X86::ZMM21, -2U },
3456
  { X86::ZMM22, -2U },
3457
  { X86::ZMM23, -2U },
3458
  { X86::ZMM24, -2U },
3459
  { X86::ZMM25, -2U },
3460
  { X86::ZMM26, -2U },
3461
  { X86::ZMM27, -2U },
3462
  { X86::ZMM28, -2U },
3463
  { X86::ZMM29, -2U },
3464
  { X86::ZMM30, -2U },
3465
  { X86::ZMM31, -2U },
3466
};
3467
extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf);
3468
3469
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3470
  { X86::EAX, -2U },
3471
  { X86::EBP, -2U },
3472
  { X86::EBX, -2U },
3473
  { X86::ECX, -2U },
3474
  { X86::EDI, -2U },
3475
  { X86::EDX, -2U },
3476
  { X86::EIP, -2U },
3477
  { X86::ESI, -2U },
3478
  { X86::ESP, -2U },
3479
  { X86::RAX, 0U },
3480
  { X86::RBP, 6U },
3481
  { X86::RBX, 3U },
3482
  { X86::RCX, 2U },
3483
  { X86::RDI, 5U },
3484
  { X86::RDX, 1U },
3485
  { X86::RIP, 16U },
3486
  { X86::RSI, 4U },
3487
  { X86::RSP, 7U },
3488
  { X86::K0, 118U },
3489
  { X86::K1, 119U },
3490
  { X86::K2, 120U },
3491
  { X86::K3, 121U },
3492
  { X86::K4, 122U },
3493
  { X86::K5, 123U },
3494
  { X86::K6, 124U },
3495
  { X86::K7, 125U },
3496
  { X86::MM0, 41U },
3497
  { X86::MM1, 42U },
3498
  { X86::MM2, 43U },
3499
  { X86::MM3, 44U },
3500
  { X86::MM4, 45U },
3501
  { X86::MM5, 46U },
3502
  { X86::MM6, 47U },
3503
  { X86::MM7, 48U },
3504
  { X86::R8, 8U },
3505
  { X86::R9, 9U },
3506
  { X86::R10, 10U },
3507
  { X86::R11, 11U },
3508
  { X86::R12, 12U },
3509
  { X86::R13, 13U },
3510
  { X86::R14, 14U },
3511
  { X86::R15, 15U },
3512
  { X86::ST0, 33U },
3513
  { X86::ST1, 34U },
3514
  { X86::ST2, 35U },
3515
  { X86::ST3, 36U },
3516
  { X86::ST4, 37U },
3517
  { X86::ST5, 38U },
3518
  { X86::ST6, 39U },
3519
  { X86::ST7, 40U },
3520
  { X86::XMM0, 17U },
3521
  { X86::XMM1, 18U },
3522
  { X86::XMM2, 19U },
3523
  { X86::XMM3, 20U },
3524
  { X86::XMM4, 21U },
3525
  { X86::XMM5, 22U },
3526
  { X86::XMM6, 23U },
3527
  { X86::XMM7, 24U },
3528
  { X86::XMM8, 25U },
3529
  { X86::XMM9, 26U },
3530
  { X86::XMM10, 27U },
3531
  { X86::XMM11, 28U },
3532
  { X86::XMM12, 29U },
3533
  { X86::XMM13, 30U },
3534
  { X86::XMM14, 31U },
3535
  { X86::XMM15, 32U },
3536
  { X86::XMM16, 67U },
3537
  { X86::XMM17, 68U },
3538
  { X86::XMM18, 69U },
3539
  { X86::XMM19, 70U },
3540
  { X86::XMM20, 71U },
3541
  { X86::XMM21, 72U },
3542
  { X86::XMM22, 73U },
3543
  { X86::XMM23, 74U },
3544
  { X86::XMM24, 75U },
3545
  { X86::XMM25, 76U },
3546
  { X86::XMM26, 77U },
3547
  { X86::XMM27, 78U },
3548
  { X86::XMM28, 79U },
3549
  { X86::XMM29, 80U },
3550
  { X86::XMM30, 81U },
3551
  { X86::XMM31, 82U },
3552
  { X86::YMM0, 17U },
3553
  { X86::YMM1, 18U },
3554
  { X86::YMM2, 19U },
3555
  { X86::YMM3, 20U },
3556
  { X86::YMM4, 21U },
3557
  { X86::YMM5, 22U },
3558
  { X86::YMM6, 23U },
3559
  { X86::YMM7, 24U },
3560
  { X86::YMM8, 25U },
3561
  { X86::YMM9, 26U },
3562
  { X86::YMM10, 27U },
3563
  { X86::YMM11, 28U },
3564
  { X86::YMM12, 29U },
3565
  { X86::YMM13, 30U },
3566
  { X86::YMM14, 31U },
3567
  { X86::YMM15, 32U },
3568
  { X86::YMM16, 67U },
3569
  { X86::YMM17, 68U },
3570
  { X86::YMM18, 69U },
3571
  { X86::YMM19, 70U },
3572
  { X86::YMM20, 71U },
3573
  { X86::YMM21, 72U },
3574
  { X86::YMM22, 73U },
3575
  { X86::YMM23, 74U },
3576
  { X86::YMM24, 75U },
3577
  { X86::YMM25, 76U },
3578
  { X86::YMM26, 77U },
3579
  { X86::YMM27, 78U },
3580
  { X86::YMM28, 79U },
3581
  { X86::YMM29, 80U },
3582
  { X86::YMM30, 81U },
3583
  { X86::YMM31, 82U },
3584
  { X86::ZMM0, 17U },
3585
  { X86::ZMM1, 18U },
3586
  { X86::ZMM2, 19U },
3587
  { X86::ZMM3, 20U },
3588
  { X86::ZMM4, 21U },
3589
  { X86::ZMM5, 22U },
3590
  { X86::ZMM6, 23U },
3591
  { X86::ZMM7, 24U },
3592
  { X86::ZMM8, 25U },
3593
  { X86::ZMM9, 26U },
3594
  { X86::ZMM10, 27U },
3595
  { X86::ZMM11, 28U },
3596
  { X86::ZMM12, 29U },
3597
  { X86::ZMM13, 30U },
3598
  { X86::ZMM14, 31U },
3599
  { X86::ZMM15, 32U },
3600
  { X86::ZMM16, 67U },
3601
  { X86::ZMM17, 68U },
3602
  { X86::ZMM18, 69U },
3603
  { X86::ZMM19, 70U },
3604
  { X86::ZMM20, 71U },
3605
  { X86::ZMM21, 72U },
3606
  { X86::ZMM22, 73U },
3607
  { X86::ZMM23, 74U },
3608
  { X86::ZMM24, 75U },
3609
  { X86::ZMM25, 76U },
3610
  { X86::ZMM26, 77U },
3611
  { X86::ZMM27, 78U },
3612
  { X86::ZMM28, 79U },
3613
  { X86::ZMM29, 80U },
3614
  { X86::ZMM30, 81U },
3615
  { X86::ZMM31, 82U },
3616
};
3617
extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf);
3618
3619
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3620
  { X86::EAX, 0U },
3621
  { X86::EBP, 4U },
3622
  { X86::EBX, 3U },
3623
  { X86::ECX, 1U },
3624
  { X86::EDI, 7U },
3625
  { X86::EDX, 2U },
3626
  { X86::EIP, 8U },
3627
  { X86::ESI, 6U },
3628
  { X86::ESP, 5U },
3629
  { X86::RAX, -2U },
3630
  { X86::RBP, -2U },
3631
  { X86::RBX, -2U },
3632
  { X86::RCX, -2U },
3633
  { X86::RDI, -2U },
3634
  { X86::RDX, -2U },
3635
  { X86::RIP, -2U },
3636
  { X86::RSI, -2U },
3637
  { X86::RSP, -2U },
3638
  { X86::K0, 93U },
3639
  { X86::K1, 94U },
3640
  { X86::K2, 95U },
3641
  { X86::K3, 96U },
3642
  { X86::K4, 97U },
3643
  { X86::K5, 98U },
3644
  { X86::K6, 99U },
3645
  { X86::K7, 100U },
3646
  { X86::MM0, 29U },
3647
  { X86::MM1, 30U },
3648
  { X86::MM2, 31U },
3649
  { X86::MM3, 32U },
3650
  { X86::MM4, 33U },
3651
  { X86::MM5, 34U },
3652
  { X86::MM6, 35U },
3653
  { X86::MM7, 36U },
3654
  { X86::R8, -2U },
3655
  { X86::R9, -2U },
3656
  { X86::R10, -2U },
3657
  { X86::R11, -2U },
3658
  { X86::R12, -2U },
3659
  { X86::R13, -2U },
3660
  { X86::R14, -2U },
3661
  { X86::R15, -2U },
3662
  { X86::ST0, 12U },
3663
  { X86::ST1, 13U },
3664
  { X86::ST2, 14U },
3665
  { X86::ST3, 15U },
3666
  { X86::ST4, 16U },
3667
  { X86::ST5, 17U },
3668
  { X86::ST6, 18U },
3669
  { X86::ST7, 19U },
3670
  { X86::XMM0, 21U },
3671
  { X86::XMM1, 22U },
3672
  { X86::XMM2, 23U },
3673
  { X86::XMM3, 24U },
3674
  { X86::XMM4, 25U },
3675
  { X86::XMM5, 26U },
3676
  { X86::XMM6, 27U },
3677
  { X86::XMM7, 28U },
3678
  { X86::XMM8, -2U },
3679
  { X86::XMM9, -2U },
3680
  { X86::XMM10, -2U },
3681
  { X86::XMM11, -2U },
3682
  { X86::XMM12, -2U },
3683
  { X86::XMM13, -2U },
3684
  { X86::XMM14, -2U },
3685
  { X86::XMM15, -2U },
3686
  { X86::XMM16, -2U },
3687
  { X86::XMM17, -2U },
3688
  { X86::XMM18, -2U },
3689
  { X86::XMM19, -2U },
3690
  { X86::XMM20, -2U },
3691
  { X86::XMM21, -2U },
3692
  { X86::XMM22, -2U },
3693
  { X86::XMM23, -2U },
3694
  { X86::XMM24, -2U },
3695
  { X86::XMM25, -2U },
3696
  { X86::XMM26, -2U },
3697
  { X86::XMM27, -2U },
3698
  { X86::XMM28, -2U },
3699
  { X86::XMM29, -2U },
3700
  { X86::XMM30, -2U },
3701
  { X86::XMM31, -2U },
3702
  { X86::YMM0, 21U },
3703
  { X86::YMM1, 22U },
3704
  { X86::YMM2, 23U },
3705
  { X86::YMM3, 24U },
3706
  { X86::YMM4, 25U },
3707
  { X86::YMM5, 26U },
3708
  { X86::YMM6, 27U },
3709
  { X86::YMM7, 28U },
3710
  { X86::YMM8, -2U },
3711
  { X86::YMM9, -2U },
3712
  { X86::YMM10, -2U },
3713
  { X86::YMM11, -2U },
3714
  { X86::YMM12, -2U },
3715
  { X86::YMM13, -2U },
3716
  { X86::YMM14, -2U },
3717
  { X86::YMM15, -2U },
3718
  { X86::YMM16, -2U },
3719
  { X86::YMM17, -2U },
3720
  { X86::YMM18, -2U },
3721
  { X86::YMM19, -2U },
3722
  { X86::YMM20, -2U },
3723
  { X86::YMM21, -2U },
3724
  { X86::YMM22, -2U },
3725
  { X86::YMM23, -2U },
3726
  { X86::YMM24, -2U },
3727
  { X86::YMM25, -2U },
3728
  { X86::YMM26, -2U },
3729
  { X86::YMM27, -2U },
3730
  { X86::YMM28, -2U },
3731
  { X86::YMM29, -2U },
3732
  { X86::YMM30, -2U },
3733
  { X86::YMM31, -2U },
3734
  { X86::ZMM0, 21U },
3735
  { X86::ZMM1, 22U },
3736
  { X86::ZMM2, 23U },
3737
  { X86::ZMM3, 24U },
3738
  { X86::ZMM4, 25U },
3739
  { X86::ZMM5, 26U },
3740
  { X86::ZMM6, 27U },
3741
  { X86::ZMM7, 28U },
3742
  { X86::ZMM8, -2U },
3743
  { X86::ZMM9, -2U },
3744
  { X86::ZMM10, -2U },
3745
  { X86::ZMM11, -2U },
3746
  { X86::ZMM12, -2U },
3747
  { X86::ZMM13, -2U },
3748
  { X86::ZMM14, -2U },
3749
  { X86::ZMM15, -2U },
3750
  { X86::ZMM16, -2U },
3751
  { X86::ZMM17, -2U },
3752
  { X86::ZMM18, -2U },
3753
  { X86::ZMM19, -2U },
3754
  { X86::ZMM20, -2U },
3755
  { X86::ZMM21, -2U },
3756
  { X86::ZMM22, -2U },
3757
  { X86::ZMM23, -2U },
3758
  { X86::ZMM24, -2U },
3759
  { X86::ZMM25, -2U },
3760
  { X86::ZMM26, -2U },
3761
  { X86::ZMM27, -2U },
3762
  { X86::ZMM28, -2U },
3763
  { X86::ZMM29, -2U },
3764
  { X86::ZMM30, -2U },
3765
  { X86::ZMM31, -2U },
3766
};
3767
extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf);
3768
3769
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
3770
  { X86::EAX, 0U },
3771
  { X86::EBP, 5U },
3772
  { X86::EBX, 3U },
3773
  { X86::ECX, 1U },
3774
  { X86::EDI, 7U },
3775
  { X86::EDX, 2U },
3776
  { X86::EIP, 8U },
3777
  { X86::ESI, 6U },
3778
  { X86::ESP, 4U },
3779
  { X86::RAX, -2U },
3780
  { X86::RBP, -2U },
3781
  { X86::RBX, -2U },
3782
  { X86::RCX, -2U },
3783
  { X86::RDI, -2U },
3784
  { X86::RDX, -2U },
3785
  { X86::RIP, -2U },
3786
  { X86::RSI, -2U },
3787
  { X86::RSP, -2U },
3788
  { X86::K0, 93U },
3789
  { X86::K1, 94U },
3790
  { X86::K2, 95U },
3791
  { X86::K3, 96U },
3792
  { X86::K4, 97U },
3793
  { X86::K5, 98U },
3794
  { X86::K6, 99U },
3795
  { X86::K7, 100U },
3796
  { X86::MM0, 29U },
3797
  { X86::MM1, 30U },
3798
  { X86::MM2, 31U },
3799
  { X86::MM3, 32U },
3800
  { X86::MM4, 33U },
3801
  { X86::MM5, 34U },
3802
  { X86::MM6, 35U },
3803
  { X86::MM7, 36U },
3804
  { X86::R8, -2U },
3805
  { X86::R9, -2U },
3806
  { X86::R10, -2U },
3807
  { X86::R11, -2U },
3808
  { X86::R12, -2U },
3809
  { X86::R13, -2U },
3810
  { X86::R14, -2U },
3811
  { X86::R15, -2U },
3812
  { X86::ST0, 11U },
3813
  { X86::ST1, 12U },
3814
  { X86::ST2, 13U },
3815
  { X86::ST3, 14U },
3816
  { X86::ST4, 15U },
3817
  { X86::ST5, 16U },
3818
  { X86::ST6, 17U },
3819
  { X86::ST7, 18U },
3820
  { X86::XMM0, 21U },
3821
  { X86::XMM1, 22U },
3822
  { X86::XMM2, 23U },
3823
  { X86::XMM3, 24U },
3824
  { X86::XMM4, 25U },
3825
  { X86::XMM5, 26U },
3826
  { X86::XMM6, 27U },
3827
  { X86::XMM7, 28U },
3828
  { X86::XMM8, -2U },
3829
  { X86::XMM9, -2U },
3830
  { X86::XMM10, -2U },
3831
  { X86::XMM11, -2U },
3832
  { X86::XMM12, -2U },
3833
  { X86::XMM13, -2U },
3834
  { X86::XMM14, -2U },
3835
  { X86::XMM15, -2U },
3836
  { X86::XMM16, -2U },
3837
  { X86::XMM17, -2U },
3838
  { X86::XMM18, -2U },
3839
  { X86::XMM19, -2U },
3840
  { X86::XMM20, -2U },
3841
  { X86::XMM21, -2U },
3842
  { X86::XMM22, -2U },
3843
  { X86::XMM23, -2U },
3844
  { X86::XMM24, -2U },
3845
  { X86::XMM25, -2U },
3846
  { X86::XMM26, -2U },
3847
  { X86::XMM27, -2U },
3848
  { X86::XMM28, -2U },
3849
  { X86::XMM29, -2U },
3850
  { X86::XMM30, -2U },
3851
  { X86::XMM31, -2U },
3852
  { X86::YMM0, 21U },
3853
  { X86::YMM1, 22U },
3854
  { X86::YMM2, 23U },
3855
  { X86::YMM3, 24U },
3856
  { X86::YMM4, 25U },
3857
  { X86::YMM5, 26U },
3858
  { X86::YMM6, 27U },
3859
  { X86::YMM7, 28U },
3860
  { X86::YMM8, -2U },
3861
  { X86::YMM9, -2U },
3862
  { X86::YMM10, -2U },
3863
  { X86::YMM11, -2U },
3864
  { X86::YMM12, -2U },
3865
  { X86::YMM13, -2U },
3866
  { X86::YMM14, -2U },
3867
  { X86::YMM15, -2U },
3868
  { X86::YMM16, -2U },
3869
  { X86::YMM17, -2U },
3870
  { X86::YMM18, -2U },
3871
  { X86::YMM19, -2U },
3872
  { X86::YMM20, -2U },
3873
  { X86::YMM21, -2U },
3874
  { X86::YMM22, -2U },
3875
  { X86::YMM23, -2U },
3876
  { X86::YMM24, -2U },
3877
  { X86::YMM25, -2U },
3878
  { X86::YMM26, -2U },
3879
  { X86::YMM27, -2U },
3880
  { X86::YMM28, -2U },
3881
  { X86::YMM29, -2U },
3882
  { X86::YMM30, -2U },
3883
  { X86::YMM31, -2U },
3884
  { X86::ZMM0, 21U },
3885
  { X86::ZMM1, 22U },
3886
  { X86::ZMM2, 23U },
3887
  { X86::ZMM3, 24U },
3888
  { X86::ZMM4, 25U },
3889
  { X86::ZMM5, 26U },
3890
  { X86::ZMM6, 27U },
3891
  { X86::ZMM7, 28U },
3892
  { X86::ZMM8, -2U },
3893
  { X86::ZMM9, -2U },
3894
  { X86::ZMM10, -2U },
3895
  { X86::ZMM11, -2U },
3896
  { X86::ZMM12, -2U },
3897
  { X86::ZMM13, -2U },
3898
  { X86::ZMM14, -2U },
3899
  { X86::ZMM15, -2U },
3900
  { X86::ZMM16, -2U },
3901
  { X86::ZMM17, -2U },
3902
  { X86::ZMM18, -2U },
3903
  { X86::ZMM19, -2U },
3904
  { X86::ZMM20, -2U },
3905
  { X86::ZMM21, -2U },
3906
  { X86::ZMM22, -2U },
3907
  { X86::ZMM23, -2U },
3908
  { X86::ZMM24, -2U },
3909
  { X86::ZMM25, -2U },
3910
  { X86::ZMM26, -2U },
3911
  { X86::ZMM27, -2U },
3912
  { X86::ZMM28, -2U },
3913
  { X86::ZMM29, -2U },
3914
  { X86::ZMM30, -2U },
3915
  { X86::ZMM31, -2U },
3916
};
3917
extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf);
3918
3919
extern const uint16_t X86RegEncodingTable[] = {
3920
  0,
3921
  4,
3922
  0,
3923
  0,
3924
  7,
3925
  3,
3926
  5,
3927
  65535,
3928
  5,
3929
  3,
3930
  5,
3931
  1,
3932
  1,
3933
  1,
3934
  0,
3935
  6,
3936
  7,
3937
  65535,
3938
  7,
3939
  2,
3940
  3,
3941
  2,
3942
  0,
3943
  5,
3944
  3,
3945
  1,
3946
  7,
3947
  2,
3948
  0,
3949
  0,
3950
  4,
3951
  0,
3952
  6,
3953
  4,
3954
  0,
3955
  0,
3956
  4,
3957
  5,
3958
  65535,
3959
  65535,
3960
  65535,
3961
  65535,
3962
  65535,
3963
  65535,
3964
  65535,
3965
  65535,
3966
  65535,
3967
  0,
3968
  0,
3969
  5,
3970
  3,
3971
  1,
3972
  7,
3973
  2,
3974
  0,
3975
  4,
3976
  6,
3977
  4,
3978
  6,
3979
  65535,
3980
  6,
3981
  4,
3982
  65535,
3983
  4,
3984
  2,
3985
  0,
3986
  0,
3987
  1,
3988
  2,
3989
  3,
3990
  0,
3991
  1,
3992
  2,
3993
  3,
3994
  4,
3995
  5,
3996
  6,
3997
  7,
3998
  8,
3999
  9,
4000
  10,
4001
  11,
4002
  12,
4003
  13,
4004
  14,
4005
  15,
4006
  0,
4007
  1,
4008
  2,
4009
  3,
4010
  4,
4011
  5,
4012
  6,
4013
  7,
4014
  8,
4015
  9,
4016
  10,
4017
  11,
4018
  12,
4019
  13,
4020
  14,
4021
  15,
4022
  0,
4023
  0,
4024
  0,
4025
  0,
4026
  0,
4027
  0,
4028
  0,
4029
  0,
4030
  0,
4031
  1,
4032
  2,
4033
  3,
4034
  4,
4035
  5,
4036
  6,
4037
  7,
4038
  0,
4039
  1,
4040
  2,
4041
  3,
4042
  4,
4043
  5,
4044
  6,
4045
  7,
4046
  8,
4047
  9,
4048
  10,
4049
  11,
4050
  12,
4051
  13,
4052
  14,
4053
  15,
4054
  0,
4055
  1,
4056
  2,
4057
  3,
4058
  4,
4059
  5,
4060
  6,
4061
  7,
4062
  0,
4063
  1,
4064
  2,
4065
  3,
4066
  4,
4067
  5,
4068
  6,
4069
  7,
4070
  8,
4071
  9,
4072
  10,
4073
  11,
4074
  12,
4075
  13,
4076
  14,
4077
  15,
4078
  16,
4079
  17,
4080
  18,
4081
  19,
4082
  20,
4083
  21,
4084
  22,
4085
  23,
4086
  24,
4087
  25,
4088
  26,
4089
  27,
4090
  28,
4091
  29,
4092
  30,
4093
  31,
4094
  0,
4095
  1,
4096
  2,
4097
  3,
4098
  4,
4099
  5,
4100
  6,
4101
  7,
4102
  8,
4103
  9,
4104
  10,
4105
  11,
4106
  12,
4107
  13,
4108
  14,
4109
  15,
4110
  16,
4111
  17,
4112
  18,
4113
  19,
4114
  20,
4115
  21,
4116
  22,
4117
  23,
4118
  24,
4119
  25,
4120
  26,
4121
  27,
4122
  28,
4123
  29,
4124
  30,
4125
  31,
4126
  0,
4127
  1,
4128
  2,
4129
  3,
4130
  4,
4131
  5,
4132
  6,
4133
  7,
4134
  8,
4135
  9,
4136
  10,
4137
  11,
4138
  12,
4139
  13,
4140
  14,
4141
  15,
4142
  16,
4143
  17,
4144
  18,
4145
  19,
4146
  20,
4147
  21,
4148
  22,
4149
  23,
4150
  24,
4151
  25,
4152
  26,
4153
  27,
4154
  28,
4155
  29,
4156
  30,
4157
  31,
4158
  8,
4159
  9,
4160
  10,
4161
  11,
4162
  12,
4163
  13,
4164
  14,
4165
  15,
4166
  65535,
4167
  65535,
4168
  65535,
4169
  65535,
4170
  65535,
4171
  65535,
4172
  65535,
4173
  65535,
4174
  8,
4175
  9,
4176
  10,
4177
  11,
4178
  12,
4179
  13,
4180
  14,
4181
  15,
4182
  8,
4183
  9,
4184
  10,
4185
  11,
4186
  12,
4187
  13,
4188
  14,
4189
  15,
4190
  65535,
4191
  65535,
4192
  65535,
4193
  65535,
4194
  65535,
4195
  65535,
4196
  65535,
4197
  65535,
4198
};
4199
26.6k
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4200
26.6k
  RI->InitMCRegisterInfo(X86RegDesc, 278, RA, PC, X86MCRegisterClasses, 118, X86RegUnitRoots, 163, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 9,
4201
26.6k
X86SubRegIdxRanges, X86RegEncodingTable);
4202
26.6k
4203
26.6k
  switch (DwarfFlavour) {
4204
26.6k
  default:
4205
0
    llvm_unreachable("Unknown DWARF flavour");
4206
26.6k
  case 0:
4207
20.2k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
4208
20.2k
    break;
4209
26.6k
  case 1:
4210
0
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
4211
0
    break;
4212
26.6k
  case 2:
4213
6.31k
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
4214
6.31k
    break;
4215
26.6k
  }
4216
26.6k
  switch (EHFlavour) {
4217
26.6k
  default:
4218
0
    llvm_unreachable("Unknown DWARF flavour");
4219
26.6k
  case 0:
4220
20.2k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
4221
20.2k
    break;
4222
26.6k
  case 1:
4223
1.54k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
4224
1.54k
    break;
4225
26.6k
  case 2:
4226
4.76k
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
4227
4.76k
    break;
4228
26.6k
  }
4229
26.6k
  switch (DwarfFlavour) {
4230
26.6k
  default:
4231
0
    llvm_unreachable("Unknown DWARF flavour");
4232
26.6k
  case 0:
4233
20.3k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
4234
20.3k
    break;
4235
26.6k
  case 1:
4236
0
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
4237
0
    break;
4238
26.6k
  case 2:
4239
6.31k
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
4240
6.31k
    break;
4241
26.6k
  }
4242
26.6k
  switch (EHFlavour) {
4243
26.6k
  default:
4244
0
    llvm_unreachable("Unknown DWARF flavour");
4245
26.6k
  case 0:
4246
20.3k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
4247
20.3k
    break;
4248
26.6k
  case 1:
4249
1.54k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
4250
1.54k
    break;
4251
26.6k
  case 2:
4252
4.76k
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
4253
4.76k
    break;
4254
26.6k
  }
4255
26.6k
}
4256
4257
} // end namespace llvm
4258
4259
#endif // GET_REGINFO_MC_DESC
4260
4261
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4262
|*                                                                            *|
4263
|* Register Information Header Fragment                                       *|
4264
|*                                                                            *|
4265
|* Automatically generated file, do not edit!                                 *|
4266
|*                                                                            *|
4267
\*===----------------------------------------------------------------------===*/
4268
4269
4270
#ifdef GET_REGINFO_HEADER
4271
#undef GET_REGINFO_HEADER
4272
4273
#include "llvm/CodeGen/TargetRegisterInfo.h"
4274
4275
namespace llvm {
4276
4277
class X86FrameLowering;
4278
4279
struct X86GenRegisterInfo : public TargetRegisterInfo {
4280
  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4281
      unsigned PC = 0, unsigned HwMode = 0);
4282
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4283
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4284
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4285
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4286
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4287
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
4288
  unsigned getNumRegPressureSets() const override;
4289
  const char *getRegPressureSetName(unsigned Idx) const override;
4290
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4291
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4292
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4293
  ArrayRef<const char *> getRegMaskNames() const override;
4294
  ArrayRef<const uint32_t *> getRegMasks() const override;
4295
  /// Devirtualized TargetFrameLowering.
4296
  static const X86FrameLowering *getFrameLowering(
4297
      const MachineFunction &MF);
4298
};
4299
4300
namespace X86 { // Register classes
4301
  extern const TargetRegisterClass GR8RegClass;
4302
  extern const TargetRegisterClass GRH8RegClass;
4303
  extern const TargetRegisterClass GR8_NOREXRegClass;
4304
  extern const TargetRegisterClass GR8_ABCD_HRegClass;
4305
  extern const TargetRegisterClass GR8_ABCD_LRegClass;
4306
  extern const TargetRegisterClass GRH16RegClass;
4307
  extern const TargetRegisterClass GR16RegClass;
4308
  extern const TargetRegisterClass GR16_NOREXRegClass;
4309
  extern const TargetRegisterClass VK1RegClass;
4310
  extern const TargetRegisterClass VK16RegClass;
4311
  extern const TargetRegisterClass VK2RegClass;
4312
  extern const TargetRegisterClass VK4RegClass;
4313
  extern const TargetRegisterClass VK8RegClass;
4314
  extern const TargetRegisterClass VK16WMRegClass;
4315
  extern const TargetRegisterClass VK1WMRegClass;
4316
  extern const TargetRegisterClass VK2WMRegClass;
4317
  extern const TargetRegisterClass VK4WMRegClass;
4318
  extern const TargetRegisterClass VK8WMRegClass;
4319
  extern const TargetRegisterClass SEGMENT_REGRegClass;
4320
  extern const TargetRegisterClass GR16_ABCDRegClass;
4321
  extern const TargetRegisterClass FPCCRRegClass;
4322
  extern const TargetRegisterClass FR32XRegClass;
4323
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
4324
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
4325
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
4326
  extern const TargetRegisterClass DEBUG_REGRegClass;
4327
  extern const TargetRegisterClass FR32RegClass;
4328
  extern const TargetRegisterClass GR32RegClass;
4329
  extern const TargetRegisterClass GR32_NOSPRegClass;
4330
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
4331
  extern const TargetRegisterClass GR32_NOREXRegClass;
4332
  extern const TargetRegisterClass VK32RegClass;
4333
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
4334
  extern const TargetRegisterClass RFP32RegClass;
4335
  extern const TargetRegisterClass VK32WMRegClass;
4336
  extern const TargetRegisterClass GR32_ABCDRegClass;
4337
  extern const TargetRegisterClass GR32_TCRegClass;
4338
  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
4339
  extern const TargetRegisterClass GR32_ADRegClass;
4340
  extern const TargetRegisterClass GR32_BPSPRegClass;
4341
  extern const TargetRegisterClass GR32_BSIRegClass;
4342
  extern const TargetRegisterClass GR32_CBRegClass;
4343
  extern const TargetRegisterClass GR32_DCRegClass;
4344
  extern const TargetRegisterClass GR32_DIBPRegClass;
4345
  extern const TargetRegisterClass GR32_SIDIRegClass;
4346
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
4347
  extern const TargetRegisterClass CCRRegClass;
4348
  extern const TargetRegisterClass DFCCRRegClass;
4349
  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
4350
  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
4351
  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
4352
  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
4353
  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
4354
  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
4355
  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
4356
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
4357
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
4358
  extern const TargetRegisterClass RFP64RegClass;
4359
  extern const TargetRegisterClass FR64XRegClass;
4360
  extern const TargetRegisterClass GR64RegClass;
4361
  extern const TargetRegisterClass CONTROL_REGRegClass;
4362
  extern const TargetRegisterClass FR64RegClass;
4363
  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
4364
  extern const TargetRegisterClass GR64_NOSPRegClass;
4365
  extern const TargetRegisterClass GR64_TCRegClass;
4366
  extern const TargetRegisterClass GR64_NOREXRegClass;
4367
  extern const TargetRegisterClass GR64_TCW64RegClass;
4368
  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
4369
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
4370
  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
4371
  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
4372
  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4373
  extern const TargetRegisterClass VK64RegClass;
4374
  extern const TargetRegisterClass VR64RegClass;
4375
  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
4376
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
4377
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
4378
  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
4379
  extern const TargetRegisterClass VK64WMRegClass;
4380
  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
4381
  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4382
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
4383
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
4384
  extern const TargetRegisterClass GR64_ABCDRegClass;
4385
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
4386
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
4387
  extern const TargetRegisterClass GR64_ADRegClass;
4388
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
4389
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
4390
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
4391
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
4392
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
4393
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
4394
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
4395
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
4396
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
4397
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
4398
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
4399
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
4400
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
4401
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
4402
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
4403
  extern const TargetRegisterClass RSTRegClass;
4404
  extern const TargetRegisterClass RFP80RegClass;
4405
  extern const TargetRegisterClass RFP80_7RegClass;
4406
  extern const TargetRegisterClass VR128XRegClass;
4407
  extern const TargetRegisterClass VR128RegClass;
4408
  extern const TargetRegisterClass VR128HRegClass;
4409
  extern const TargetRegisterClass VR128LRegClass;
4410
  extern const TargetRegisterClass BNDRRegClass;
4411
  extern const TargetRegisterClass VR256XRegClass;
4412
  extern const TargetRegisterClass VR256RegClass;
4413
  extern const TargetRegisterClass VR256HRegClass;
4414
  extern const TargetRegisterClass VR256LRegClass;
4415
  extern const TargetRegisterClass VR512RegClass;
4416
  extern const TargetRegisterClass VR512_with_sub_xmm_in_FR32RegClass;
4417
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128HRegClass;
4418
  extern const TargetRegisterClass VR512_with_sub_xmm_in_VR128LRegClass;
4419
} // end namespace X86
4420
4421
} // end namespace llvm
4422
4423
#endif // GET_REGINFO_HEADER
4424
4425
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4426
|*                                                                            *|
4427
|* Target Register and Register Classes Information                           *|
4428
|*                                                                            *|
4429
|* Automatically generated file, do not edit!                                 *|
4430
|*                                                                            *|
4431
\*===----------------------------------------------------------------------===*/
4432
4433
4434
#ifdef GET_REGINFO_TARGET_DESC
4435
#undef GET_REGINFO_TARGET_DESC
4436
4437
namespace llvm {
4438
4439
extern const MCRegisterClass X86MCRegisterClasses[];
4440
4441
static const MVT::SimpleValueType VTLists[] = {
4442
  /* 0 */ MVT::i8, MVT::Other,
4443
  /* 2 */ MVT::i16, MVT::Other,
4444
  /* 4 */ MVT::i32, MVT::Other,
4445
  /* 6 */ MVT::i64, MVT::Other,
4446
  /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
4447
  /* 12 */ MVT::f64, MVT::Other,
4448
  /* 14 */ MVT::f80, MVT::Other,
4449
  /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
4450
  /* 24 */ MVT::v1i1, MVT::Other,
4451
  /* 26 */ MVT::v2i1, MVT::Other,
4452
  /* 28 */ MVT::v4i1, MVT::Other,
4453
  /* 30 */ MVT::v8i1, MVT::Other,
4454
  /* 32 */ MVT::v16i1, MVT::Other,
4455
  /* 34 */ MVT::v32i1, MVT::Other,
4456
  /* 36 */ MVT::v64i1, MVT::Other,
4457
  /* 38 */ MVT::v2i64, MVT::Other,
4458
  /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
4459
  /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
4460
  /* 54 */ MVT::x86mmx, MVT::Other,
4461
};
4462
4463
static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_xmm", "sub_ymm", "" };
4464
4465
4466
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4467
  LaneBitmask::getAll(),
4468
  LaneBitmask(0x00000001), // sub_8bit
4469
  LaneBitmask(0x00000002), // sub_8bit_hi
4470
  LaneBitmask(0x00000004), // sub_8bit_hi_phony
4471
  LaneBitmask(0x00000007), // sub_16bit
4472
  LaneBitmask(0x00000008), // sub_16bit_hi
4473
  LaneBitmask(0x0000000F), // sub_32bit
4474
  LaneBitmask(0x00000010), // sub_xmm
4475
  LaneBitmask(0x00000010), // sub_ymm
4476
 };
4477
4478
4479
4480
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4481
  // Mode = 0 (Default)
4482
  { 8, 8, 8, VTLists+0 },    // GR8
4483
  { 8, 8, 8, VTLists+0 },    // GRH8
4484
  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
4485
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
4486
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
4487
  { 16, 16, 16, VTLists+2 },    // GRH16
4488
  { 16, 16, 16, VTLists+2 },    // GR16
4489
  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
4490
  { 16, 16, 16, VTLists+24 },    // VK1
4491
  { 16, 16, 16, VTLists+32 },    // VK16
4492
  { 16, 16, 16, VTLists+26 },    // VK2
4493
  { 16, 16, 16, VTLists+28 },    // VK4
4494
  { 16, 16, 16, VTLists+30 },    // VK8
4495
  { 16, 16, 16, VTLists+32 },    // VK16WM
4496
  { 16, 16, 16, VTLists+24 },    // VK1WM
4497
  { 16, 16, 16, VTLists+26 },    // VK2WM
4498
  { 16, 16, 16, VTLists+28 },    // VK4WM
4499
  { 16, 16, 16, VTLists+30 },    // VK8WM
4500
  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
4501
  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
4502
  { 16, 16, 16, VTLists+2 },    // FPCCR
4503
  { 32, 32, 32, VTLists+10 },    // FR32X
4504
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
4505
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
4506
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4507
  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
4508
  { 32, 32, 32, VTLists+10 },    // FR32
4509
  { 32, 32, 32, VTLists+4 },    // GR32
4510
  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
4511
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4512
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
4513
  { 32, 32, 32, VTLists+34 },    // VK32
4514
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
4515
  { 32, 32, 32, VTLists+10 },    // RFP32
4516
  { 32, 32, 32, VTLists+34 },    // VK32WM
4517
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
4518
  { 32, 32, 32, VTLists+4 },    // GR32_TC
4519
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_TC
4520
  { 32, 32, 32, VTLists+4 },    // GR32_AD
4521
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP
4522
  { 32, 32, 32, VTLists+4 },    // GR32_BSI
4523
  { 32, 32, 32, VTLists+4 },    // GR32_CB
4524
  { 32, 32, 32, VTLists+4 },    // GR32_DC
4525
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP
4526
  { 32, 32, 32, VTLists+4 },    // GR32_SIDI
4527
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4528
  { 32, 32, 32, VTLists+4 },    // CCR
4529
  { 32, 32, 32, VTLists+4 },    // DFCCR
4530
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_BSI
4531
  { 32, 32, 32, VTLists+4 },    // GR32_AD_and_GR32_DC
4532
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_DIBP
4533
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_TC
4534
  { 32, 32, 32, VTLists+4 },    // GR32_BSI_and_GR32_SIDI
4535
  { 32, 32, 32, VTLists+4 },    // GR32_CB_and_GR32_DC
4536
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP_and_GR32_SIDI
4537
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4538
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
4539
  { 64, 64, 32, VTLists+12 },    // RFP64
4540
  { 64, 64, 64, VTLists+12 },    // FR64X
4541
  { 64, 64, 64, VTLists+6 },    // GR64
4542
  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
4543
  { 64, 64, 64, VTLists+12 },    // FR64
4544
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
4545
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
4546
  { 64, 64, 64, VTLists+6 },    // GR64_TC
4547
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
4548
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
4549
  { 64, 64, 64, VTLists+6 },    // GR64_TC_with_sub_8bit
4550
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
4551
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_with_sub_8bit
4552
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
4553
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
4554
  { 64, 64, 64, VTLists+36 },    // VK64
4555
  { 64, 64, 64, VTLists+54 },    // VR64
4556
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
4557
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
4558
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
4559
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_and_GR64_TC_with_sub_8bit
4560
  { 64, 64, 64, VTLists+36 },    // VK64WM
4561
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4562
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4563
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_GR64_TC
4564
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
4565
  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
4566
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
4567
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4568
  { 64, 64, 64, VTLists+6 },    // GR64_AD
4569
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
4570
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP
4571
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI
4572
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB
4573
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DC
4574
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP
4575
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_SIDI
4576
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
4577
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4578
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
4579
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4580
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4581
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4582
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
4583
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4584
  { 80, 80, 32, VTLists+8 },    // RST
4585
  { 80, 80, 32, VTLists+14 },    // RFP80
4586
  { 80, 80, 32, VTLists+14 },    // RFP80_7
4587
  { 128, 128, 128, VTLists+16 },    // VR128X
4588
  { 128, 128, 128, VTLists+16 },    // VR128
4589
  { 128, 128, 128, VTLists+16 },    // VR128H
4590
  { 128, 128, 128, VTLists+16 },    // VR128L
4591
  { 128, 128, 128, VTLists+38 },    // BNDR
4592
  { 256, 256, 256, VTLists+40 },    // VR256X
4593
  { 256, 256, 256, VTLists+40 },    // VR256
4594
  { 256, 256, 256, VTLists+40 },    // VR256H
4595
  { 256, 256, 256, VTLists+40 },    // VR256L
4596
  { 512, 512, 512, VTLists+47 },    // VR512
4597
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_FR32
4598
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128H
4599
  { 512, 512, 512, VTLists+47 },    // VR512_with_sub_xmm_in_VR128L
4600
};
4601
4602
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4603
4604
static const uint32_t GR8SubClassMask[] = {
4605
  0x0000001d, 0x00000000, 0x00000000, 0x00000000, 
4606
  0x790800c0, 0xc0ff1ff9, 0xbf7bb4b8, 0x0000003f, // sub_8bit
4607
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4608
};
4609
4610
static const uint32_t GRH8SubClassMask[] = {
4611
  0x00000002, 0x00000000, 0x00000000, 0x00000000, 
4612
};
4613
4614
static const uint32_t GR8_NOREXSubClassMask[] = {
4615
  0x0000001c, 0x00000000, 0x00000000, 0x00000000, 
4616
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit
4617
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4618
};
4619
4620
static const uint32_t GR8_ABCD_HSubClassMask[] = {
4621
  0x00000008, 0x00000000, 0x00000000, 0x00000000, 
4622
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit_hi
4623
};
4624
4625
static const uint32_t GR8_ABCD_LSubClassMask[] = {
4626
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
4627
  0x00080000, 0x00230668, 0x8c680000, 0x00000011, // sub_8bit
4628
};
4629
4630
static const uint32_t GRH16SubClassMask[] = {
4631
  0x00000020, 0x00000000, 0x00000000, 0x00000000, 
4632
};
4633
4634
static const uint32_t GR16SubClassMask[] = {
4635
  0x000800c0, 0x00000000, 0x00000000, 0x00000000, 
4636
  0x79000000, 0xc0ff1ff9, 0xbf7bb4b8, 0x0000003f, // sub_16bit
4637
};
4638
4639
static const uint32_t GR16_NOREXSubClassMask[] = {
4640
  0x00080080, 0x00000000, 0x00000000, 0x00000000, 
4641
  0x60000000, 0x00ff1ff9, 0xbf7b0480, 0x0000003f, // sub_16bit
4642
};
4643
4644
static const uint32_t VK1SubClassMask[] = {
4645
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4646
};
4647
4648
static const uint32_t VK16SubClassMask[] = {
4649
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4650
};
4651
4652
static const uint32_t VK2SubClassMask[] = {
4653
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4654
};
4655
4656
static const uint32_t VK4SubClassMask[] = {
4657
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4658
};
4659
4660
static const uint32_t VK8SubClassMask[] = {
4661
  0x8003ff00, 0x00000004, 0x00004100, 0x00000000, 
4662
};
4663
4664
static const uint32_t VK16WMSubClassMask[] = {
4665
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4666
};
4667
4668
static const uint32_t VK1WMSubClassMask[] = {
4669
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4670
};
4671
4672
static const uint32_t VK2WMSubClassMask[] = {
4673
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4674
};
4675
4676
static const uint32_t VK4WMSubClassMask[] = {
4677
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4678
};
4679
4680
static const uint32_t VK8WMSubClassMask[] = {
4681
  0x0003e000, 0x00000004, 0x00004000, 0x00000000, 
4682
};
4683
4684
static const uint32_t SEGMENT_REGSubClassMask[] = {
4685
  0x00040000, 0x00000000, 0x00000000, 0x00000000, 
4686
};
4687
4688
static const uint32_t GR16_ABCDSubClassMask[] = {
4689
  0x00080000, 0x00000000, 0x00000000, 0x00000000, 
4690
  0x00000000, 0x00230668, 0x8c680000, 0x00000011, // sub_16bit
4691
};
4692
4693
static const uint32_t FPCCRSubClassMask[] = {
4694
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
4695
};
4696
4697
static const uint32_t FR32XSubClassMask[] = {
4698
  0x04200000, 0x24000000, 0x00000000, 0x00001e00, 
4699
  0x00000000, 0x00000000, 0x00000000, 0x003fc000, // sub_xmm
4700
};
4701
4702
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4703
  0x79c00000, 0x01ff3ff9, 0x40800000, 0x00000002, 
4704
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4705
};
4706
4707
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
4708
  0x58800000, 0x017f1ff9, 0x40000000, 0x00000000, 
4709
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4710
};
4711
4712
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
4713
  0x79000000, 0x00ff1ff9, 0x00000000, 0x00000002, 
4714
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4715
};
4716
4717
static const uint32_t DEBUG_REGSubClassMask[] = {
4718
  0x02000000, 0x00000000, 0x00000000, 0x00000000, 
4719
};
4720
4721
static const uint32_t FR32SubClassMask[] = {
4722
  0x04000000, 0x20000000, 0x00000000, 0x00001c00, 
4723
  0x00000000, 0x00000000, 0x00000000, 0x003b8000, // sub_xmm
4724
};
4725
4726
static const uint32_t GR32SubClassMask[] = {
4727
  0x58000000, 0x007f1ff9, 0x00000000, 0x00000000, 
4728
  0x00000000, 0xc0800000, 0xbf7bb4b8, 0x0000003f, // sub_32bit
4729
};
4730
4731
static const uint32_t GR32_NOSPSubClassMask[] = {
4732
  0x10000000, 0x00771f69, 0x00000000, 0x00000000, 
4733
  0x00000000, 0x80800000, 0xbe6a9410, 0x0000003b, // sub_32bit
4734
};
4735
4736
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4737
  0x60000000, 0x00ff1ff9, 0x00000000, 0x00000002, 
4738
  0x00000000, 0x00800000, 0xbf7b0480, 0x0000003f, // sub_32bit
4739
};
4740
4741
static const uint32_t GR32_NOREXSubClassMask[] = {
4742
  0x40000000, 0x007f1ff9, 0x00000000, 0x00000000, 
4743
  0x00000000, 0x00800000, 0xbf7b0480, 0x0000003f, // sub_32bit
4744
};
4745
4746
static const uint32_t VK32SubClassMask[] = {
4747
  0x80000000, 0x00000004, 0x00004100, 0x00000000, 
4748
};
4749
4750
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
4751
  0x00000000, 0x00771f69, 0x00000000, 0x00000000, 
4752
  0x00000000, 0x00800000, 0xbe6a0400, 0x0000003b, // sub_32bit
4753
};
4754
4755
static const uint32_t RFP32SubClassMask[] = {
4756
  0x00000000, 0x02000002, 0x00000000, 0x00000080, 
4757
};
4758
4759
static const uint32_t VK32WMSubClassMask[] = {
4760
  0x00000000, 0x00000004, 0x00004000, 0x00000000, 
4761
};
4762
4763
static const uint32_t GR32_ABCDSubClassMask[] = {
4764
  0x00000000, 0x00230668, 0x00000000, 0x00000000, 
4765
  0x00000000, 0x00000000, 0x8c680000, 0x00000011, // sub_32bit
4766
};
4767
4768
static const uint32_t GR32_TCSubClassMask[] = {
4769
  0x00000000, 0x002a0470, 0x00000000, 0x00000000, 
4770
  0x00000000, 0x00000000, 0x08700000, 0x00000015, // sub_32bit
4771
};
4772
4773
static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
4774
  0x00000000, 0x00220460, 0x00000000, 0x00000000, 
4775
  0x00000000, 0x00000000, 0x08600000, 0x00000011, // sub_32bit
4776
};
4777
4778
static const uint32_t GR32_ADSubClassMask[] = {
4779
  0x00000000, 0x00020040, 0x00000000, 0x00000000, 
4780
  0x00000000, 0x00000000, 0x00400000, 0x00000001, // sub_32bit
4781
};
4782
4783
static const uint32_t GR32_BPSPSubClassMask[] = {
4784
  0x00000000, 0x000c0080, 0x00000000, 0x00000000, 
4785
  0x00000000, 0x00800000, 0x01000000, 0x00000006, // sub_32bit
4786
};
4787
4788
static const uint32_t GR32_BSISubClassMask[] = {
4789
  0x00000000, 0x00110100, 0x00000000, 0x00000000, 
4790
  0x00000000, 0x00000000, 0x82000000, 0x00000008, // sub_32bit
4791
};
4792
4793
static const uint32_t GR32_CBSubClassMask[] = {
4794
  0x00000000, 0x00210200, 0x00000000, 0x00000000, 
4795
  0x00000000, 0x00000000, 0x84000000, 0x00000010, // sub_32bit
4796
};
4797
4798
static const uint32_t GR32_DCSubClassMask[] = {
4799
  0x00000000, 0x00220400, 0x00000000, 0x00000000, 
4800
  0x00000000, 0x00000000, 0x08000000, 0x00000011, // sub_32bit
4801
};
4802
4803
static const uint32_t GR32_DIBPSubClassMask[] = {
4804
  0x00000000, 0x00440800, 0x00000000, 0x00000000, 
4805
  0x00000000, 0x00800000, 0x10000000, 0x00000022, // sub_32bit
4806
};
4807
4808
static const uint32_t GR32_SIDISubClassMask[] = {
4809
  0x00000000, 0x00501000, 0x00000000, 0x00000000, 
4810
  0x00000000, 0x00000000, 0x20000000, 0x00000028, // sub_32bit
4811
};
4812
4813
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
4814
  0x00000000, 0x01802000, 0x40800000, 0x00000002, 
4815
};
4816
4817
static const uint32_t CCRSubClassMask[] = {
4818
  0x00000000, 0x00004000, 0x00000000, 0x00000000, 
4819
};
4820
4821
static const uint32_t DFCCRSubClassMask[] = {
4822
  0x00000000, 0x00008000, 0x00000000, 0x00000000, 
4823
};
4824
4825
static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
4826
  0x00000000, 0x00010000, 0x00000000, 0x00000000, 
4827
  0x00000000, 0x00000000, 0x80000000, 0x00000000, // sub_32bit
4828
};
4829
4830
static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
4831
  0x00000000, 0x00020000, 0x00000000, 0x00000000, 
4832
  0x00000000, 0x00000000, 0x00000000, 0x00000001, // sub_32bit
4833
};
4834
4835
static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
4836
  0x00000000, 0x00040000, 0x00000000, 0x00000000, 
4837
  0x00000000, 0x00800000, 0x00000000, 0x00000002, // sub_32bit
4838
};
4839
4840
static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
4841
  0x00000000, 0x00080000, 0x00000000, 0x00000000, 
4842
  0x00000000, 0x00000000, 0x00000000, 0x00000004, // sub_32bit
4843
};
4844
4845
static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
4846
  0x00000000, 0x00100000, 0x00000000, 0x00000000, 
4847
  0x00000000, 0x00000000, 0x00000000, 0x00000008, // sub_32bit
4848
};
4849
4850
static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
4851
  0x00000000, 0x00200000, 0x00000000, 0x00000000, 
4852
  0x00000000, 0x00000000, 0x00000000, 0x00000010, // sub_32bit
4853
};
4854
4855
static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
4856
  0x00000000, 0x00400000, 0x00000000, 0x00000000, 
4857
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32bit
4858
};
4859
4860
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
4861
  0x00000000, 0x00800000, 0x00000000, 0x00000002, 
4862
};
4863
4864
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
4865
  0x00000000, 0x01000000, 0x40000000, 0x00000000, 
4866
};
4867
4868
static const uint32_t RFP64SubClassMask[] = {
4869
  0x00000000, 0x02000000, 0x00000000, 0x00000080, 
4870
};
4871
4872
static const uint32_t FR64XSubClassMask[] = {
4873
  0x00000000, 0x24000000, 0x00000000, 0x00001e00, 
4874
  0x00000000, 0x00000000, 0x00000000, 0x003fc000, // sub_xmm
4875
};
4876
4877
static const uint32_t GR64SubClassMask[] = {
4878
  0x00000000, 0xc8000000, 0xffffbcff, 0x0000003f, 
4879
};
4880
4881
static const uint32_t CONTROL_REGSubClassMask[] = {
4882
  0x00000000, 0x10000000, 0x00000000, 0x00000000, 
4883
};
4884
4885
static const uint32_t FR64SubClassMask[] = {
4886
  0x00000000, 0x20000000, 0x00000000, 0x00001c00, 
4887
  0x00000000, 0x00000000, 0x00000000, 0x003b8000, // sub_xmm
4888
};
4889
4890
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
4891
  0x00000000, 0xc0000000, 0xbf7bb4b8, 0x0000003f, 
4892
};
4893
4894
static const uint32_t GR64_NOSPSubClassMask[] = {
4895
  0x00000000, 0x80000000, 0xbe6a9410, 0x0000003b, 
4896
};
4897
4898
static const uint32_t GR64_TCSubClassMask[] = {
4899
  0x00000000, 0x00000000, 0x6877a859, 0x0000003d, 
4900
};
4901
4902
static const uint32_t GR64_NOREXSubClassMask[] = {
4903
  0x00000000, 0x00000000, 0xffff0c82, 0x0000003f, 
4904
};
4905
4906
static const uint32_t GR64_TCW64SubClassMask[] = {
4907
  0x00000000, 0x00000000, 0x4874b064, 0x00000015, 
4908
};
4909
4910
static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
4911
  0x00000000, 0x00000000, 0x2873a018, 0x0000003d, 
4912
};
4913
4914
static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
4915
  0x00000000, 0x00000000, 0x28628010, 0x00000039, 
4916
};
4917
4918
static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
4919
  0x00000000, 0x00000000, 0x0870b020, 0x00000015, 
4920
};
4921
4922
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
4923
  0x00000000, 0x00000000, 0x4874a040, 0x00000015, 
4924
};
4925
4926
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4927
  0x00000000, 0x00000000, 0xbf7b0480, 0x0000003f, 
4928
};
4929
4930
static const uint32_t VK64SubClassMask[] = {
4931
  0x00000000, 0x00000000, 0x00004100, 0x00000000, 
4932
};
4933
4934
static const uint32_t VR64SubClassMask[] = {
4935
  0x00000000, 0x00000000, 0x00000200, 0x00000000, 
4936
};
4937
4938
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
4939
  0x00000000, 0x00000000, 0xbe6a0400, 0x0000003b, 
4940
};
4941
4942
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
4943
  0x00000000, 0x00000000, 0x68770800, 0x0000003d, 
4944
};
4945
4946
static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4947
  0x00000000, 0x00000000, 0x08609000, 0x00000011, 
4948
};
4949
4950
static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
4951
  0x00000000, 0x00000000, 0x0870a000, 0x00000015, 
4952
};
4953
4954
static const uint32_t VK64WMSubClassMask[] = {
4955
  0x00000000, 0x00000000, 0x00004000, 0x00000000, 
4956
};
4957
4958
static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
4959
  0x00000000, 0x00000000, 0x08608000, 0x00000011, 
4960
};
4961
4962
static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
4963
  0x00000000, 0x00000000, 0x28730000, 0x0000003d, 
4964
};
4965
4966
static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = {
4967
  0x00000000, 0x00000000, 0x28620000, 0x00000039, 
4968
};
4969
4970
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
4971
  0x00000000, 0x00000000, 0x48740000, 0x00000015, 
4972
};
4973
4974
static const uint32_t GR64_ABCDSubClassMask[] = {
4975
  0x00000000, 0x00000000, 0x8c680000, 0x00000011, 
4976
};
4977
4978
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
4979
  0x00000000, 0x00000000, 0x08700000, 0x00000015, 
4980
};
4981
4982
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
4983
  0x00000000, 0x00000000, 0x08600000, 0x00000011, 
4984
};
4985
4986
static const uint32_t GR64_ADSubClassMask[] = {
4987
  0x00000000, 0x00000000, 0x00400000, 0x00000001, 
4988
};
4989
4990
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
4991
  0x00000000, 0x00000000, 0x40800000, 0x00000002, 
4992
};
4993
4994
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
4995
  0x00000000, 0x00000000, 0x01000000, 0x00000006, 
4996
};
4997
4998
static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
4999
  0x00000000, 0x00000000, 0x82000000, 0x00000008, 
5000
};
5001
5002
static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
5003
  0x00000000, 0x00000000, 0x84000000, 0x00000010, 
5004
};
5005
5006
static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
5007
  0x00000000, 0x00000000, 0x08000000, 0x00000011, 
5008
};
5009
5010
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
5011
  0x00000000, 0x00000000, 0x10000000, 0x00000022, 
5012
};
5013
5014
static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
5015
  0x00000000, 0x00000000, 0x20000000, 0x00000028, 
5016
};
5017
5018
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
5019
  0x00000000, 0x00000000, 0x40000000, 0x00000000, 
5020
};
5021
5022
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
5023
  0x00000000, 0x00000000, 0x80000000, 0x00000000, 
5024
};
5025
5026
static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
5027
  0x00000000, 0x00000000, 0x00000000, 0x00000001, 
5028
};
5029
5030
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5031
  0x00000000, 0x00000000, 0x00000000, 0x00000002, 
5032
};
5033
5034
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
5035
  0x00000000, 0x00000000, 0x00000000, 0x00000004, 
5036
};
5037
5038
static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
5039
  0x00000000, 0x00000000, 0x00000000, 0x00000008, 
5040
};
5041
5042
static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
5043
  0x00000000, 0x00000000, 0x00000000, 0x00000010, 
5044
};
5045
5046
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
5047
  0x00000000, 0x00000000, 0x00000000, 0x00000020, 
5048
};
5049
5050
static const uint32_t RSTSubClassMask[] = {
5051
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
5052
};
5053
5054
static const uint32_t RFP80SubClassMask[] = {
5055
  0x00000000, 0x00000000, 0x00000000, 0x00000080, 
5056
};
5057
5058
static const uint32_t RFP80_7SubClassMask[] = {
5059
  0x00000000, 0x00000000, 0x00000000, 0x00000100, 
5060
};
5061
5062
static const uint32_t VR128XSubClassMask[] = {
5063
  0x00000000, 0x00000000, 0x00000000, 0x00001e00, 
5064
  0x00000000, 0x00000000, 0x00000000, 0x003fc000, // sub_xmm
5065
};
5066
5067
static const uint32_t VR128SubClassMask[] = {
5068
  0x00000000, 0x00000000, 0x00000000, 0x00001c00, 
5069
  0x00000000, 0x00000000, 0x00000000, 0x003b8000, // sub_xmm
5070
};
5071
5072
static const uint32_t VR128HSubClassMask[] = {
5073
  0x00000000, 0x00000000, 0x00000000, 0x00000800, 
5074
  0x00000000, 0x00000000, 0x00000000, 0x00110000, // sub_xmm
5075
};
5076
5077
static const uint32_t VR128LSubClassMask[] = {
5078
  0x00000000, 0x00000000, 0x00000000, 0x00001000, 
5079
  0x00000000, 0x00000000, 0x00000000, 0x00220000, // sub_xmm
5080
};
5081
5082
static const uint32_t BNDRSubClassMask[] = {
5083
  0x00000000, 0x00000000, 0x00000000, 0x00002000, 
5084
};
5085
5086
static const uint32_t VR256XSubClassMask[] = {
5087
  0x00000000, 0x00000000, 0x00000000, 0x0003c000, 
5088
  0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_ymm
5089
};
5090
5091
static const uint32_t VR256SubClassMask[] = {
5092
  0x00000000, 0x00000000, 0x00000000, 0x00038000, 
5093
  0x00000000, 0x00000000, 0x00000000, 0x00380000, // sub_ymm
5094
};
5095
5096
static const uint32_t VR256HSubClassMask[] = {
5097
  0x00000000, 0x00000000, 0x00000000, 0x00010000, 
5098
  0x00000000, 0x00000000, 0x00000000, 0x00100000, // sub_ymm
5099
};
5100
5101
static const uint32_t VR256LSubClassMask[] = {
5102
  0x00000000, 0x00000000, 0x00000000, 0x00020000, 
5103
  0x00000000, 0x00000000, 0x00000000, 0x00200000, // sub_ymm
5104
};
5105
5106
static const uint32_t VR512SubClassMask[] = {
5107
  0x00000000, 0x00000000, 0x00000000, 0x003c0000, 
5108
};
5109
5110
static const uint32_t VR512_with_sub_xmm_in_FR32SubClassMask[] = {
5111
  0x00000000, 0x00000000, 0x00000000, 0x00380000, 
5112
};
5113
5114
static const uint32_t VR512_with_sub_xmm_in_VR128HSubClassMask[] = {
5115
  0x00000000, 0x00000000, 0x00000000, 0x00100000, 
5116
};
5117
5118
static const uint32_t VR512_with_sub_xmm_in_VR128LSubClassMask[] = {
5119
  0x00000000, 0x00000000, 0x00000000, 0x00200000, 
5120
};
5121
5122
static const uint16_t SuperRegIdxSeqs[] = {
5123
  /* 0 */ 1, 0,
5124
  /* 2 */ 1, 2, 0,
5125
  /* 5 */ 4, 0,
5126
  /* 7 */ 6, 0,
5127
  /* 9 */ 7, 0,
5128
  /* 11 */ 8, 0,
5129
};
5130
5131
static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
5132
  &X86::GR8RegClass,
5133
  nullptr
5134
};
5135
5136
static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
5137
  &X86::GR8RegClass,
5138
  &X86::GR8_NOREXRegClass,
5139
  nullptr
5140
};
5141
5142
static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
5143
  &X86::GR8RegClass,
5144
  &X86::GR8_NOREXRegClass,
5145
  nullptr
5146
};
5147
5148
static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
5149
  &X86::GR16RegClass,
5150
  nullptr
5151
};
5152
5153
static const TargetRegisterClass *const VK1Superclasses[] = {
5154
  &X86::VK16RegClass,
5155
  &X86::VK2RegClass,
5156
  &X86::VK4RegClass,
5157
  &X86::VK8RegClass,
5158
  nullptr
5159
};
5160
5161
static const TargetRegisterClass *const VK16Superclasses[] = {
5162
  &X86::VK1RegClass,
5163
  &X86::VK2RegClass,
5164
  &X86::VK4RegClass,
5165
  &X86::VK8RegClass,
5166
  nullptr
5167
};
5168
5169
static const TargetRegisterClass *const VK2Superclasses[] = {
5170
  &X86::VK1RegClass,
5171
  &X86::VK16RegClass,
5172
  &X86::VK4RegClass,
5173
  &X86::VK8RegClass,
5174
  nullptr
5175
};
5176
5177
static const TargetRegisterClass *const VK4Superclasses[] = {
5178
  &X86::VK1RegClass,
5179
  &X86::VK16RegClass,
5180
  &X86::VK2RegClass,
5181
  &X86::VK8RegClass,
5182
  nullptr
5183
};
5184
5185
static const TargetRegisterClass *const VK8Superclasses[] = {
5186
  &X86::VK1RegClass,
5187
  &X86::VK16RegClass,
5188
  &X86::VK2RegClass,
5189
  &X86::VK4RegClass,
5190
  nullptr
5191
};
5192
5193
static const TargetRegisterClass *const VK16WMSuperclasses[] = {
5194
  &X86::VK1RegClass,
5195
  &X86::VK16RegClass,
5196
  &X86::VK2RegClass,
5197
  &X86::VK4RegClass,
5198
  &X86::VK8RegClass,
5199
  &X86::VK1WMRegClass,
5200
  &X86::VK2WMRegClass,
5201
  &X86::VK4WMRegClass,
5202
  &X86::VK8WMRegClass,
5203
  nullptr
5204
};
5205
5206
static const TargetRegisterClass *const VK1WMSuperclasses[] = {
5207
  &X86::VK1RegClass,
5208
  &X86::VK16RegClass,
5209
  &X86::VK2RegClass,
5210
  &X86::VK4RegClass,
5211
  &X86::VK8RegClass,
5212
  &X86::VK16WMRegClass,
5213
  &X86::VK2WMRegClass,
5214
  &X86::VK4WMRegClass,
5215
  &X86::VK8WMRegClass,
5216
  nullptr
5217
};
5218
5219
static const TargetRegisterClass *const VK2WMSuperclasses[] = {
5220
  &X86::VK1RegClass,
5221
  &X86::VK16RegClass,
5222
  &X86::VK2RegClass,
5223
  &X86::VK4RegClass,
5224
  &X86::VK8RegClass,
5225
  &X86::VK16WMRegClass,
5226
  &X86::VK1WMRegClass,
5227
  &X86::VK4WMRegClass,
5228
  &X86::VK8WMRegClass,
5229
  nullptr
5230
};
5231
5232
static const TargetRegisterClass *const VK4WMSuperclasses[] = {
5233
  &X86::VK1RegClass,
5234
  &X86::VK16RegClass,
5235
  &X86::VK2RegClass,
5236
  &X86::VK4RegClass,
5237
  &X86::VK8RegClass,
5238
  &X86::VK16WMRegClass,
5239
  &X86::VK1WMRegClass,
5240
  &X86::VK2WMRegClass,
5241
  &X86::VK8WMRegClass,
5242
  nullptr
5243
};
5244
5245
static const TargetRegisterClass *const VK8WMSuperclasses[] = {
5246
  &X86::VK1RegClass,
5247
  &X86::VK16RegClass,
5248
  &X86::VK2RegClass,
5249
  &X86::VK4RegClass,
5250
  &X86::VK8RegClass,
5251
  &X86::VK16WMRegClass,
5252
  &X86::VK1WMRegClass,
5253
  &X86::VK2WMRegClass,
5254
  &X86::VK4WMRegClass,
5255
  nullptr
5256
};
5257
5258
static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
5259
  &X86::GR16RegClass,
5260
  &X86::GR16_NOREXRegClass,
5261
  nullptr
5262
};
5263
5264
static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
5265
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5266
  nullptr
5267
};
5268
5269
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
5270
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5271
  nullptr
5272
};
5273
5274
static const TargetRegisterClass *const FR32Superclasses[] = {
5275
  &X86::FR32XRegClass,
5276
  nullptr
5277
};
5278
5279
static const TargetRegisterClass *const GR32Superclasses[] = {
5280
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5281
  &X86::LOW32_ADDR_ACCESSRegClass,
5282
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5283
  nullptr
5284
};
5285
5286
static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
5287
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5288
  &X86::LOW32_ADDR_ACCESSRegClass,
5289
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5290
  &X86::GR32RegClass,
5291
  nullptr
5292
};
5293
5294
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5295
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5296
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5297
  nullptr
5298
};
5299
5300
static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
5301
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5302
  &X86::LOW32_ADDR_ACCESSRegClass,
5303
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5304
  &X86::GR32RegClass,
5305
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5306
  nullptr
5307
};
5308
5309
static const TargetRegisterClass *const VK32Superclasses[] = {
5310
  &X86::VK1RegClass,
5311
  &X86::VK16RegClass,
5312
  &X86::VK2RegClass,
5313
  &X86::VK4RegClass,
5314
  &X86::VK8RegClass,
5315
  nullptr
5316
};
5317
5318
static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
5319
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5320
  &X86::LOW32_ADDR_ACCESSRegClass,
5321
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5322
  &X86::GR32RegClass,
5323
  &X86::GR32_NOSPRegClass,
5324
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5325
  &X86::GR32_NOREXRegClass,
5326
  nullptr
5327
};
5328
5329
static const TargetRegisterClass *const VK32WMSuperclasses[] = {
5330
  &X86::VK1RegClass,
5331
  &X86::VK16RegClass,
5332
  &X86::VK2RegClass,
5333
  &X86::VK4RegClass,
5334
  &X86::VK8RegClass,
5335
  &X86::VK16WMRegClass,
5336
  &X86::VK1WMRegClass,
5337
  &X86::VK2WMRegClass,
5338
  &X86::VK4WMRegClass,
5339
  &X86::VK8WMRegClass,
5340
  &X86::VK32RegClass,
5341
  nullptr
5342
};
5343
5344
static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
5345
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5346
  &X86::LOW32_ADDR_ACCESSRegClass,
5347
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5348
  &X86::GR32RegClass,
5349
  &X86::GR32_NOSPRegClass,
5350
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5351
  &X86::GR32_NOREXRegClass,
5352
  &X86::GR32_NOREX_NOSPRegClass,
5353
  nullptr
5354
};
5355
5356
static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
5357
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5358
  &X86::LOW32_ADDR_ACCESSRegClass,
5359
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5360
  &X86::GR32RegClass,
5361
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5362
  &X86::GR32_NOREXRegClass,
5363
  nullptr
5364
};
5365
5366
static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
5367
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5368
  &X86::LOW32_ADDR_ACCESSRegClass,
5369
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5370
  &X86::GR32RegClass,
5371
  &X86::GR32_NOSPRegClass,
5372
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5373
  &X86::GR32_NOREXRegClass,
5374
  &X86::GR32_NOREX_NOSPRegClass,
5375
  &X86::GR32_ABCDRegClass,
5376
  &X86::GR32_TCRegClass,
5377
  nullptr
5378
};
5379
5380
static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
5381
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5382
  &X86::LOW32_ADDR_ACCESSRegClass,
5383
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5384
  &X86::GR32RegClass,
5385
  &X86::GR32_NOSPRegClass,
5386
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5387
  &X86::GR32_NOREXRegClass,
5388
  &X86::GR32_NOREX_NOSPRegClass,
5389
  &X86::GR32_ABCDRegClass,
5390
  &X86::GR32_TCRegClass,
5391
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5392
  nullptr
5393
};
5394
5395
static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
5396
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5397
  &X86::LOW32_ADDR_ACCESSRegClass,
5398
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5399
  &X86::GR32RegClass,
5400
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5401
  &X86::GR32_NOREXRegClass,
5402
  nullptr
5403
};
5404
5405
static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
5406
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5407
  &X86::LOW32_ADDR_ACCESSRegClass,
5408
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5409
  &X86::GR32RegClass,
5410
  &X86::GR32_NOSPRegClass,
5411
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5412
  &X86::GR32_NOREXRegClass,
5413
  &X86::GR32_NOREX_NOSPRegClass,
5414
  nullptr
5415
};
5416
5417
static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
5418
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5419
  &X86::LOW32_ADDR_ACCESSRegClass,
5420
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5421
  &X86::GR32RegClass,
5422
  &X86::GR32_NOSPRegClass,
5423
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5424
  &X86::GR32_NOREXRegClass,
5425
  &X86::GR32_NOREX_NOSPRegClass,
5426
  &X86::GR32_ABCDRegClass,
5427
  nullptr
5428
};
5429
5430
static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
5431
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5432
  &X86::LOW32_ADDR_ACCESSRegClass,
5433
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5434
  &X86::GR32RegClass,
5435
  &X86::GR32_NOSPRegClass,
5436
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5437
  &X86::GR32_NOREXRegClass,
5438
  &X86::GR32_NOREX_NOSPRegClass,
5439
  &X86::GR32_ABCDRegClass,
5440
  &X86::GR32_TCRegClass,
5441
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5442
  nullptr
5443
};
5444
5445
static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
5446
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5447
  &X86::LOW32_ADDR_ACCESSRegClass,
5448
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5449
  &X86::GR32RegClass,
5450
  &X86::GR32_NOSPRegClass,
5451
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5452
  &X86::GR32_NOREXRegClass,
5453
  &X86::GR32_NOREX_NOSPRegClass,
5454
  nullptr
5455
};
5456
5457
static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
5458
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5459
  &X86::LOW32_ADDR_ACCESSRegClass,
5460
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5461
  &X86::GR32RegClass,
5462
  &X86::GR32_NOSPRegClass,
5463
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5464
  &X86::GR32_NOREXRegClass,
5465
  &X86::GR32_NOREX_NOSPRegClass,
5466
  nullptr
5467
};
5468
5469
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
5470
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5471
  nullptr
5472
};
5473
5474
static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
5475
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5476
  &X86::LOW32_ADDR_ACCESSRegClass,
5477
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5478
  &X86::GR32RegClass,
5479
  &X86::GR32_NOSPRegClass,
5480
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5481
  &X86::GR32_NOREXRegClass,
5482
  &X86::GR32_NOREX_NOSPRegClass,
5483
  &X86::GR32_ABCDRegClass,
5484
  &X86::GR32_BSIRegClass,
5485
  &X86::GR32_CBRegClass,
5486
  nullptr
5487
};
5488
5489
static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
5490
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5491
  &X86::LOW32_ADDR_ACCESSRegClass,
5492
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5493
  &X86::GR32RegClass,
5494
  &X86::GR32_NOSPRegClass,
5495
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5496
  &X86::GR32_NOREXRegClass,
5497
  &X86::GR32_NOREX_NOSPRegClass,
5498
  &X86::GR32_ABCDRegClass,
5499
  &X86::GR32_TCRegClass,
5500
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5501
  &X86::GR32_ADRegClass,
5502
  &X86::GR32_DCRegClass,
5503
  nullptr
5504
};
5505
5506
static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
5507
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5508
  &X86::LOW32_ADDR_ACCESSRegClass,
5509
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5510
  &X86::GR32RegClass,
5511
  &X86::GR32_NOSPRegClass,
5512
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5513
  &X86::GR32_NOREXRegClass,
5514
  &X86::GR32_NOREX_NOSPRegClass,
5515
  &X86::GR32_BPSPRegClass,
5516
  &X86::GR32_DIBPRegClass,
5517
  nullptr
5518
};
5519
5520
static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
5521
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5522
  &X86::LOW32_ADDR_ACCESSRegClass,
5523
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5524
  &X86::GR32RegClass,
5525
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5526
  &X86::GR32_NOREXRegClass,
5527
  &X86::GR32_TCRegClass,
5528
  &X86::GR32_BPSPRegClass,
5529
  nullptr
5530
};
5531
5532
static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
5533
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5534
  &X86::LOW32_ADDR_ACCESSRegClass,
5535
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5536
  &X86::GR32RegClass,
5537
  &X86::GR32_NOSPRegClass,
5538
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5539
  &X86::GR32_NOREXRegClass,
5540
  &X86::GR32_NOREX_NOSPRegClass,
5541
  &X86::GR32_BSIRegClass,
5542
  &X86::GR32_SIDIRegClass,
5543
  nullptr
5544
};
5545
5546
static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
5547
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5548
  &X86::LOW32_ADDR_ACCESSRegClass,
5549
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5550
  &X86::GR32RegClass,
5551
  &X86::GR32_NOSPRegClass,
5552
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5553
  &X86::GR32_NOREXRegClass,
5554
  &X86::GR32_NOREX_NOSPRegClass,
5555
  &X86::GR32_ABCDRegClass,
5556
  &X86::GR32_TCRegClass,
5557
  &X86::GR32_ABCD_and_GR32_TCRegClass,
5558
  &X86::GR32_CBRegClass,
5559
  &X86::GR32_DCRegClass,
5560
  nullptr
5561
};
5562
5563
static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
5564
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5565
  &X86::LOW32_ADDR_ACCESSRegClass,
5566
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5567
  &X86::GR32RegClass,
5568
  &X86::GR32_NOSPRegClass,
5569
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5570
  &X86::GR32_NOREXRegClass,
5571
  &X86::GR32_NOREX_NOSPRegClass,
5572
  &X86::GR32_DIBPRegClass,
5573
  &X86::GR32_SIDIRegClass,
5574
  nullptr
5575
};
5576
5577
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
5578
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5579
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
5580
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
5581
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5582
  nullptr
5583
};
5584
5585
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
5586
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
5587
  &X86::LOW32_ADDR_ACCESSRegClass,
5588
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
5589
  nullptr
5590
};
5591
5592
static const TargetRegisterClass *const RFP64Superclasses[] = {
5593
  &X86::RFP32RegClass,
5594
  nullptr
5595
};
5596
5597
static const TargetRegisterClass *const FR64XSuperclasses[] = {
5598
  &X86::FR32XRegClass,
5599
  nullptr
5600
};
5601
5602
static const TargetRegisterClass *const FR64Superclasses[] = {
5603
  &X86::FR32XRegClass,
5604
  &X86::FR32RegClass,
5605
  &X86::FR64XRegClass,
5606
  nullptr
5607
};
5608