Coverage Report

Created: 2019-04-21 11:35

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/XCore/XCoreGenCallingConv.inc
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Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Calling Convention Implementation Fragment                                 *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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static bool CC_XCore(unsigned ValNo, MVT ValVT,
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                     MVT LocVT, CCValAssign::LocInfo LocInfo,
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                     ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
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                        MVT LocVT, CCValAssign::LocInfo LocInfo,
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                        ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_XCore(unsigned ValNo, MVT ValVT,
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                     MVT LocVT, CCValAssign::LocInfo LocInfo,
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                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i8 ||
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      LocVT == MVT::i16) {
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0
    LocVT = MVT::i32;
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0
    if (ArgFlags.isSExt())
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0
        LocInfo = CCValAssign::SExt;
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0
    else if (ArgFlags.isZExt())
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0
        LocInfo = CCValAssign::ZExt;
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    else
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        LocInfo = CCValAssign::AExt;
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  }
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  if (ArgFlags.isNest()) {
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    if (unsigned Reg = State.AllocateReg(XCore::R11)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  if (LocVT == MVT::i32) {
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    static const MCPhysReg RegList1[] = {
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      XCore::R0, XCore::R1, XCore::R2, XCore::R3
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    };
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    if (unsigned Reg = State.AllocateReg(RegList1)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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1
  }
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1
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  if (LocVT == MVT::i32) {
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1
    unsigned Offset2 = State.AllocateStack(4, 4);
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    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
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    return false;
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  }
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0
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  return true;  // CC didn't match.
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}
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static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
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                        MVT LocVT, CCValAssign::LocInfo LocInfo,
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                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i32) {
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    static const MCPhysReg RegList1[] = {
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      XCore::R0, XCore::R1, XCore::R2, XCore::R3
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    };
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    if (unsigned Reg = State.AllocateReg(RegList1)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  if (LocVT == MVT::i32) {
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    unsigned Offset2 = State.AllocateStack(4, 4);
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    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
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    return false;
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  }
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  return true;  // CC didn't match.
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}