Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/XCore/XCoreGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace XCore {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_BUILD_VECTOR  = 52,
68
    G_BUILD_VECTOR_TRUNC  = 53,
69
    G_CONCAT_VECTORS  = 54,
70
    G_PTRTOINT  = 55,
71
    G_INTTOPTR  = 56,
72
    G_BITCAST = 57,
73
    G_INTRINSIC_TRUNC = 58,
74
    G_INTRINSIC_ROUND = 59,
75
    G_LOAD  = 60,
76
    G_SEXTLOAD  = 61,
77
    G_ZEXTLOAD  = 62,
78
    G_STORE = 63,
79
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 64,
80
    G_ATOMIC_CMPXCHG  = 65,
81
    G_ATOMICRMW_XCHG  = 66,
82
    G_ATOMICRMW_ADD = 67,
83
    G_ATOMICRMW_SUB = 68,
84
    G_ATOMICRMW_AND = 69,
85
    G_ATOMICRMW_NAND  = 70,
86
    G_ATOMICRMW_OR  = 71,
87
    G_ATOMICRMW_XOR = 72,
88
    G_ATOMICRMW_MAX = 73,
89
    G_ATOMICRMW_MIN = 74,
90
    G_ATOMICRMW_UMAX  = 75,
91
    G_ATOMICRMW_UMIN  = 76,
92
    G_BRCOND  = 77,
93
    G_BRINDIRECT  = 78,
94
    G_INTRINSIC = 79,
95
    G_INTRINSIC_W_SIDE_EFFECTS  = 80,
96
    G_ANYEXT  = 81,
97
    G_TRUNC = 82,
98
    G_CONSTANT  = 83,
99
    G_FCONSTANT = 84,
100
    G_VASTART = 85,
101
    G_VAARG = 86,
102
    G_SEXT  = 87,
103
    G_ZEXT  = 88,
104
    G_SHL = 89,
105
    G_LSHR  = 90,
106
    G_ASHR  = 91,
107
    G_ICMP  = 92,
108
    G_FCMP  = 93,
109
    G_SELECT  = 94,
110
    G_UADDO = 95,
111
    G_UADDE = 96,
112
    G_USUBO = 97,
113
    G_USUBE = 98,
114
    G_SADDO = 99,
115
    G_SADDE = 100,
116
    G_SSUBO = 101,
117
    G_SSUBE = 102,
118
    G_UMULO = 103,
119
    G_SMULO = 104,
120
    G_UMULH = 105,
121
    G_SMULH = 106,
122
    G_FADD  = 107,
123
    G_FSUB  = 108,
124
    G_FMUL  = 109,
125
    G_FMA = 110,
126
    G_FDIV  = 111,
127
    G_FREM  = 112,
128
    G_FPOW  = 113,
129
    G_FEXP  = 114,
130
    G_FEXP2 = 115,
131
    G_FLOG  = 116,
132
    G_FLOG2 = 117,
133
    G_FLOG10  = 118,
134
    G_FNEG  = 119,
135
    G_FPEXT = 120,
136
    G_FPTRUNC = 121,
137
    G_FPTOSI  = 122,
138
    G_FPTOUI  = 123,
139
    G_SITOFP  = 124,
140
    G_UITOFP  = 125,
141
    G_FABS  = 126,
142
    G_GEP = 127,
143
    G_PTR_MASK  = 128,
144
    G_BR  = 129,
145
    G_INSERT_VECTOR_ELT = 130,
146
    G_EXTRACT_VECTOR_ELT  = 131,
147
    G_SHUFFLE_VECTOR  = 132,
148
    G_CTTZ  = 133,
149
    G_CTTZ_ZERO_UNDEF = 134,
150
    G_CTLZ  = 135,
151
    G_CTLZ_ZERO_UNDEF = 136,
152
    G_CTPOP = 137,
153
    G_BSWAP = 138,
154
    G_ADDRSPACE_CAST  = 139,
155
    G_BLOCK_ADDR  = 140,
156
    ADJCALLSTACKDOWN  = 141,
157
    ADJCALLSTACKUP  = 142,
158
    BR_JT = 143,
159
    BR_JT32 = 144,
160
    EH_RETURN = 145,
161
    FRAME_TO_ARGS_OFFSET  = 146,
162
    Int_MemBarrier  = 147,
163
    LDAWFI  = 148,
164
    LDWFI = 149,
165
    SELECT_CC = 150,
166
    STWFI = 151,
167
    ADD_2rus  = 152,
168
    ADD_3r  = 153,
169
    ANDNOT_2r = 154,
170
    AND_3r  = 155,
171
    ASHR_l2rus  = 156,
172
    ASHR_l3r  = 157,
173
    BAU_1r  = 158,
174
    BITREV_l2r  = 159,
175
    BLACP_lu10  = 160,
176
    BLACP_u10 = 161,
177
    BLAT_lu6  = 162,
178
    BLAT_u6 = 163,
179
    BLA_1r  = 164,
180
    BLRB_lu10 = 165,
181
    BLRB_u10  = 166,
182
    BLRF_lu10 = 167,
183
    BLRF_u10  = 168,
184
    BRBF_lru6 = 169,
185
    BRBF_ru6  = 170,
186
    BRBT_lru6 = 171,
187
    BRBT_ru6  = 172,
188
    BRBU_lu6  = 173,
189
    BRBU_u6 = 174,
190
    BRFF_lru6 = 175,
191
    BRFF_ru6  = 176,
192
    BRFT_lru6 = 177,
193
    BRFT_ru6  = 178,
194
    BRFU_lu6  = 179,
195
    BRFU_u6 = 180,
196
    BRU_1r  = 181,
197
    BYTEREV_l2r = 182,
198
    CHKCT_2r  = 183,
199
    CHKCT_rus = 184,
200
    CLRE_0R = 185,
201
    CLRPT_1R  = 186,
202
    CLRSR_branch_lu6  = 187,
203
    CLRSR_branch_u6 = 188,
204
    CLRSR_lu6 = 189,
205
    CLRSR_u6  = 190,
206
    CLZ_l2r = 191,
207
    CRC8_l4r  = 192,
208
    CRC_l3r = 193,
209
    DCALL_0R  = 194,
210
    DENTSP_0R = 195,
211
    DGETREG_1r  = 196,
212
    DIVS_l3r  = 197,
213
    DIVU_l3r  = 198,
214
    DRESTSP_0R  = 199,
215
    DRET_0R = 200,
216
    ECALLF_1r = 201,
217
    ECALLT_1r = 202,
218
    EDU_1r  = 203,
219
    EEF_2r  = 204,
220
    EET_2r  = 205,
221
    EEU_1r  = 206,
222
    ENDIN_2r  = 207,
223
    ENTSP_lu6 = 208,
224
    ENTSP_u6  = 209,
225
    EQ_2rus = 210,
226
    EQ_3r = 211,
227
    EXTDP_lu6 = 212,
228
    EXTDP_u6  = 213,
229
    EXTSP_lu6 = 214,
230
    EXTSP_u6  = 215,
231
    FREER_1r  = 216,
232
    FREET_0R  = 217,
233
    GETD_l2r  = 218,
234
    GETED_0R  = 219,
235
    GETET_0R  = 220,
236
    GETID_0R  = 221,
237
    GETKEP_0R = 222,
238
    GETKSP_0R = 223,
239
    GETN_l2r  = 224,
240
    GETPS_l2r = 225,
241
    GETR_rus  = 226,
242
    GETSR_lu6 = 227,
243
    GETSR_u6  = 228,
244
    GETST_2r  = 229,
245
    GETTS_2r  = 230,
246
    INCT_2r = 231,
247
    INITCP_2r = 232,
248
    INITDP_2r = 233,
249
    INITLR_l2r  = 234,
250
    INITPC_2r = 235,
251
    INITSP_2r = 236,
252
    INPW_l2rus  = 237,
253
    INSHR_2r  = 238,
254
    INT_2r  = 239,
255
    IN_2r = 240,
256
    KCALL_1r  = 241,
257
    KCALL_lu6 = 242,
258
    KCALL_u6  = 243,
259
    KENTSP_lu6  = 244,
260
    KENTSP_u6 = 245,
261
    KRESTSP_lu6 = 246,
262
    KRESTSP_u6  = 247,
263
    KRET_0R = 248,
264
    LADD_l5r  = 249,
265
    LD16S_3r  = 250,
266
    LD8U_3r = 251,
267
    LDA16B_l3r  = 252,
268
    LDA16F_l3r  = 253,
269
    LDAPB_lu10  = 254,
270
    LDAPB_u10 = 255,
271
    LDAPF_lu10  = 256,
272
    LDAPF_lu10_ba = 257,
273
    LDAPF_u10 = 258,
274
    LDAWB_l2rus = 259,
275
    LDAWB_l3r = 260,
276
    LDAWCP_lu6  = 261,
277
    LDAWCP_u6 = 262,
278
    LDAWDP_lru6 = 263,
279
    LDAWDP_ru6  = 264,
280
    LDAWF_l2rus = 265,
281
    LDAWF_l3r = 266,
282
    LDAWSP_lru6 = 267,
283
    LDAWSP_ru6  = 268,
284
    LDC_lru6  = 269,
285
    LDC_ru6 = 270,
286
    LDET_0R = 271,
287
    LDIVU_l5r = 272,
288
    LDSED_0R  = 273,
289
    LDSPC_0R  = 274,
290
    LDSSR_0R  = 275,
291
    LDWCP_lru6  = 276,
292
    LDWCP_lu10  = 277,
293
    LDWCP_ru6 = 278,
294
    LDWCP_u10 = 279,
295
    LDWDP_lru6  = 280,
296
    LDWDP_ru6 = 281,
297
    LDWSP_lru6  = 282,
298
    LDWSP_ru6 = 283,
299
    LDW_2rus  = 284,
300
    LDW_3r  = 285,
301
    LMUL_l6r  = 286,
302
    LSS_3r  = 287,
303
    LSUB_l5r  = 288,
304
    LSU_3r  = 289,
305
    MACCS_l4r = 290,
306
    MACCU_l4r = 291,
307
    MJOIN_1r  = 292,
308
    MKMSK_2r  = 293,
309
    MKMSK_rus = 294,
310
    MSYNC_1r  = 295,
311
    MUL_l3r = 296,
312
    NEG = 297,
313
    NOT = 298,
314
    OR_3r = 299,
315
    OUTCT_2r  = 300,
316
    OUTCT_rus = 301,
317
    OUTPW_l2rus = 302,
318
    OUTSHR_2r = 303,
319
    OUTT_2r = 304,
320
    OUT_2r  = 305,
321
    PEEK_2r = 306,
322
    REMS_l3r  = 307,
323
    REMU_l3r  = 308,
324
    RETSP_lu6 = 309,
325
    RETSP_u6  = 310,
326
    SETCLK_l2r  = 311,
327
    SETCP_1r  = 312,
328
    SETC_l2r  = 313,
329
    SETC_lru6 = 314,
330
    SETC_ru6  = 315,
331
    SETDP_1r  = 316,
332
    SETD_2r = 317,
333
    SETEV_1r  = 318,
334
    SETKEP_0R = 319,
335
    SETN_l2r  = 320,
336
    SETPSC_2r = 321,
337
    SETPS_l2r = 322,
338
    SETPT_2r  = 323,
339
    SETRDY_l2r  = 324,
340
    SETSP_1r  = 325,
341
    SETSR_branch_lu6  = 326,
342
    SETSR_branch_u6 = 327,
343
    SETSR_lu6 = 328,
344
    SETSR_u6  = 329,
345
    SETTW_l2r = 330,
346
    SETV_1r = 331,
347
    SEXT_2r = 332,
348
    SEXT_rus  = 333,
349
    SHL_2rus  = 334,
350
    SHL_3r  = 335,
351
    SHR_2rus  = 336,
352
    SHR_3r  = 337,
353
    SSYNC_0r  = 338,
354
    ST16_l3r  = 339,
355
    ST8_l3r = 340,
356
    STET_0R = 341,
357
    STSED_0R  = 342,
358
    STSPC_0R  = 343,
359
    STSSR_0R  = 344,
360
    STWDP_lru6  = 345,
361
    STWDP_ru6 = 346,
362
    STWSP_lru6  = 347,
363
    STWSP_ru6 = 348,
364
    STW_2rus  = 349,
365
    STW_l3r = 350,
366
    SUB_2rus  = 351,
367
    SUB_3r  = 352,
368
    SYNCR_1r  = 353,
369
    TESTCT_2r = 354,
370
    TESTLCL_l2r = 355,
371
    TESTWCT_2r  = 356,
372
    TSETMR_2r = 357,
373
    TSETR_3r  = 358,
374
    TSTART_1R = 359,
375
    WAITEF_1R = 360,
376
    WAITET_1R = 361,
377
    WAITEU_0R = 362,
378
    XOR_l3r = 363,
379
    ZEXT_2r = 364,
380
    ZEXT_rus  = 365,
381
    INSTRUCTION_LIST_END = 366
382
  };
383
384
} // end XCore namespace
385
} // end llvm namespace
386
#endif // GET_INSTRINFO_ENUM
387
388
#ifdef GET_INSTRINFO_SCHED_ENUM
389
#undef GET_INSTRINFO_SCHED_ENUM
390
namespace llvm {
391
392
namespace XCore {
393
namespace Sched {
394
  enum {
395
    NoInstrModel  = 0,
396
    SCHED_LIST_END = 1
397
  };
398
} // end Sched namespace
399
} // end XCore namespace
400
} // end llvm namespace
401
#endif // GET_INSTRINFO_SCHED_ENUM
402
403
#ifdef GET_INSTRINFO_MC_DESC
404
#undef GET_INSTRINFO_MC_DESC
405
namespace llvm {
406
407
static const MCPhysReg ImplicitList1[] = { XCore::SP, 0 };
408
static const MCPhysReg ImplicitList2[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR, 0 };
409
static const MCPhysReg ImplicitList3[] = { XCore::R11, 0 };
410
411
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
412
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
413
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
414
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
415
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
416
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
417
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
418
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
419
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
420
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
421
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
422
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
423
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
424
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
425
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
426
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
427
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
428
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
429
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
430
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
431
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
432
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
433
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
434
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
435
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
436
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
437
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
438
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
439
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
440
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
441
static const MCOperandInfo OperandInfo32[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
442
static const MCOperandInfo OperandInfo33[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
443
static const MCOperandInfo OperandInfo34[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
444
static const MCOperandInfo OperandInfo35[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
445
static const MCOperandInfo OperandInfo36[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
446
static const MCOperandInfo OperandInfo37[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
447
static const MCOperandInfo OperandInfo38[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
448
static const MCOperandInfo OperandInfo39[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
449
static const MCOperandInfo OperandInfo40[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
450
static const MCOperandInfo OperandInfo41[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
451
static const MCOperandInfo OperandInfo42[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
452
static const MCOperandInfo OperandInfo43[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
453
static const MCOperandInfo OperandInfo44[] = { { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
454
static const MCOperandInfo OperandInfo45[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
455
static const MCOperandInfo OperandInfo46[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
456
static const MCOperandInfo OperandInfo47[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
457
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
458
static const MCOperandInfo OperandInfo49[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
459
460
extern const MCInstrDesc XCoreInsts[] = {
461
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
462
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
463
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
464
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
465
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
466
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
467
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
468
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
469
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
470
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
471
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
472
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
473
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
474
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
475
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
476
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
477
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
478
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
479
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
480
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
481
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
482
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
483
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
484
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
485
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
486
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
487
  { 26, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
488
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
489
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
490
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
491
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
492
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
493
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
494
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
495
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
496
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
497
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
498
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
499
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
500
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
501
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
502
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
503
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
504
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
505
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
506
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
507
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
508
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
509
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
510
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
511
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
512
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
513
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_BUILD_VECTOR
514
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR_TRUNC
515
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_CONCAT_VECTORS
516
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_PTRTOINT
517
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_INTTOPTR
518
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_BITCAST
519
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #58 = G_INTRINSIC_TRUNC
520
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_ROUND
521
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_LOAD
522
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_SEXTLOAD
523
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_ZEXTLOAD
524
  { 63, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_STORE
525
  { 64, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #64 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
526
  { 65, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG
527
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_XCHG
528
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_ADD
529
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_SUB
530
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_AND
531
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_NAND
532
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_OR
533
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_XOR
534
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_MAX
535
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MIN
536
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_UMAX
537
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMIN
538
  { 77, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #77 = G_BRCOND
539
  { 78, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #78 = G_BRINDIRECT
540
  { 79, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #79 = G_INTRINSIC
541
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #80 = G_INTRINSIC_W_SIDE_EFFECTS
542
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #81 = G_ANYEXT
543
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_TRUNC
544
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #83 = G_CONSTANT
545
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #84 = G_FCONSTANT
546
  { 85, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #85 = G_VASTART
547
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #86 = G_VAARG
548
  { 87, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #87 = G_SEXT
549
  { 88, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #88 = G_ZEXT
550
  { 89, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #89 = G_SHL
551
  { 90, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #90 = G_LSHR
552
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #91 = G_ASHR
553
  { 92, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_ICMP
554
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #93 = G_FCMP
555
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_SELECT
556
  { 95, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #95 = G_UADDO
557
  { 96, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #96 = G_UADDE
558
  { 97, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #97 = G_USUBO
559
  { 98, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #98 = G_USUBE
560
  { 99, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #99 = G_SADDO
561
  { 100,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #100 = G_SADDE
562
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SSUBO
563
  { 102,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #102 = G_SSUBE
564
  { 103,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #103 = G_UMULO
565
  { 104,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #104 = G_SMULO
566
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_UMULH
567
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_SMULH
568
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_FADD
569
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FSUB
570
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FMUL
571
  { 110,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #110 = G_FMA
572
  { 111,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #111 = G_FDIV
573
  { 112,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #112 = G_FREM
574
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FPOW
575
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FEXP
576
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FEXP2
577
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FLOG
578
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FLOG2
579
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG10
580
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FNEG
581
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_FPEXT
582
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_FPTRUNC
583
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPTOSI
584
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTOUI
585
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_SITOFP
586
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_UITOFP
587
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #126 = G_FABS
588
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #127 = G_GEP
589
  { 128,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #128 = G_PTR_MASK
590
  { 129,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #129 = G_BR
591
  { 130,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #130 = G_INSERT_VECTOR_ELT
592
  { 131,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #131 = G_EXTRACT_VECTOR_ELT
593
  { 132,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #132 = G_SHUFFLE_VECTOR
594
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTTZ
595
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_CTTZ_ZERO_UNDEF
596
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #135 = G_CTLZ
597
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #136 = G_CTLZ_ZERO_UNDEF
598
  { 137,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #137 = G_CTPOP
599
  { 138,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #138 = G_BSWAP
600
  { 139,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #139 = G_ADDRSPACE_CAST
601
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #140 = G_BLOCK_ADDR
602
  { 141,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #141 = ADJCALLSTACKDOWN
603
  { 142,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #142 = ADJCALLSTACKUP
604
  { 143,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #143 = BR_JT
605
  { 144,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #144 = BR_JT32
606
  { 145,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #145 = EH_RETURN
607
  { 146,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #146 = FRAME_TO_ARGS_OFFSET
608
  { 147,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #147 = Int_MemBarrier
609
  { 148,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #148 = LDAWFI
610
  { 149,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #149 = LDWFI
611
  { 150,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #150 = SELECT_CC
612
  { 151,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #151 = STWFI
613
  { 152,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #152 = ADD_2rus
614
  { 153,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #153 = ADD_3r
615
  { 154,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #154 = ANDNOT_2r
616
  { 155,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #155 = AND_3r
617
  { 156,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #156 = ASHR_l2rus
618
  { 157,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #157 = ASHR_l3r
619
  { 158,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #158 = BAU_1r
620
  { 159,  2,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #159 = BITREV_l2r
621
  { 160,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #160 = BLACP_lu10
622
  { 161,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #161 = BLACP_u10
623
  { 162,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #162 = BLAT_lu6
624
  { 163,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #163 = BLAT_u6
625
  { 164,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo33, -1 ,nullptr },  // Inst #164 = BLA_1r
626
  { 165,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #165 = BLRB_lu10
627
  { 166,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #166 = BLRB_u10
628
  { 167,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #167 = BLRF_lu10
629
  { 168,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #168 = BLRF_u10
630
  { 169,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #169 = BRBF_lru6
631
  { 170,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #170 = BRBF_ru6
632
  { 171,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #171 = BRBT_lru6
633
  { 172,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #172 = BRBT_ru6
634
  { 173,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #173 = BRBU_lu6
635
  { 174,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #174 = BRBU_u6
636
  { 175,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #175 = BRFF_lru6
637
  { 176,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #176 = BRFF_ru6
638
  { 177,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #177 = BRFT_lru6
639
  { 178,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #178 = BRFT_ru6
640
  { 179,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #179 = BRFU_lu6
641
  { 180,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #180 = BRFU_u6
642
  { 181,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #181 = BRU_1r
643
  { 182,  2,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #182 = BYTEREV_l2r
644
  { 183,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #183 = CHKCT_2r
645
  { 184,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #184 = CHKCT_rus
646
  { 185,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #185 = CLRE_0R
647
  { 186,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #186 = CLRPT_1R
648
  { 187,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #187 = CLRSR_branch_lu6
649
  { 188,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #188 = CLRSR_branch_u6
650
  { 189,  1,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #189 = CLRSR_lu6
651
  { 190,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #190 = CLRSR_u6
652
  { 191,  2,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #191 = CLZ_l2r
653
  { 192,  5,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #192 = CRC8_l4r
654
  { 193,  4,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #193 = CRC_l3r
655
  { 194,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #194 = DCALL_0R
656
  { 195,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #195 = DENTSP_0R
657
  { 196,  1,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #196 = DGETREG_1r
658
  { 197,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #197 = DIVS_l3r
659
  { 198,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #198 = DIVU_l3r
660
  { 199,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #199 = DRESTSP_0R
661
  { 200,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #200 = DRET_0R
662
  { 201,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #201 = ECALLF_1r
663
  { 202,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #202 = ECALLT_1r
664
  { 203,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #203 = EDU_1r
665
  { 204,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #204 = EEF_2r
666
  { 205,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #205 = EET_2r
667
  { 206,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #206 = EEU_1r
668
  { 207,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #207 = ENDIN_2r
669
  { 208,  1,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #208 = ENTSP_lu6
670
  { 209,  1,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #209 = ENTSP_u6
671
  { 210,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #210 = EQ_2rus
672
  { 211,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #211 = EQ_3r
673
  { 212,  1,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #212 = EXTDP_lu6
674
  { 213,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #213 = EXTDP_u6
675
  { 214,  1,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #214 = EXTSP_lu6
676
  { 215,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #215 = EXTSP_u6
677
  { 216,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #216 = FREER_1r
678
  { 217,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #217 = FREET_0R
679
  { 218,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #218 = GETD_l2r
680
  { 219,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #219 = GETED_0R
681
  { 220,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #220 = GETET_0R
682
  { 221,  0,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #221 = GETID_0R
683
  { 222,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #222 = GETKEP_0R
684
  { 223,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #223 = GETKSP_0R
685
  { 224,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #224 = GETN_l2r
686
  { 225,  2,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #225 = GETPS_l2r
687
  { 226,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #226 = GETR_rus
688
  { 227,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #227 = GETSR_lu6
689
  { 228,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #228 = GETSR_u6
690
  { 229,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #229 = GETST_2r
691
  { 230,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #230 = GETTS_2r
692
  { 231,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #231 = INCT_2r
693
  { 232,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #232 = INITCP_2r
694
  { 233,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #233 = INITDP_2r
695
  { 234,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #234 = INITLR_l2r
696
  { 235,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #235 = INITPC_2r
697
  { 236,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #236 = INITSP_2r
698
  { 237,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #237 = INPW_l2rus
699
  { 238,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #238 = INSHR_2r
700
  { 239,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #239 = INT_2r
701
  { 240,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #240 = IN_2r
702
  { 241,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #241 = KCALL_1r
703
  { 242,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #242 = KCALL_lu6
704
  { 243,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #243 = KCALL_u6
705
  { 244,  1,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #244 = KENTSP_lu6
706
  { 245,  1,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #245 = KENTSP_u6
707
  { 246,  1,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #246 = KRESTSP_lu6
708
  { 247,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #247 = KRESTSP_u6
709
  { 248,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #248 = KRET_0R
710
  { 249,  5,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #249 = LADD_l5r
711
  { 250,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #250 = LD16S_3r
712
  { 251,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #251 = LD8U_3r
713
  { 252,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #252 = LDA16B_l3r
714
  { 253,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #253 = LDA16F_l3r
715
  { 254,  1,  0,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #254 = LDAPB_lu10
716
  { 255,  1,  0,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #255 = LDAPB_u10
717
  { 256,  1,  0,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #256 = LDAPF_lu10
718
  { 257,  1,  0,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #257 = LDAPF_lu10_ba
719
  { 258,  1,  0,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #258 = LDAPF_u10
720
  { 259,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #259 = LDAWB_l2rus
721
  { 260,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #260 = LDAWB_l3r
722
  { 261,  1,  0,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #261 = LDAWCP_lu6
723
  { 262,  1,  0,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #262 = LDAWCP_u6
724
  { 263,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #263 = LDAWDP_lru6
725
  { 264,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #264 = LDAWDP_ru6
726
  { 265,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #265 = LDAWF_l2rus
727
  { 266,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #266 = LDAWF_l3r
728
  { 267,  2,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #267 = LDAWSP_lru6
729
  { 268,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #268 = LDAWSP_ru6
730
  { 269,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #269 = LDC_lru6
731
  { 270,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #270 = LDC_ru6
732
  { 271,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #271 = LDET_0R
733
  { 272,  5,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #272 = LDIVU_l5r
734
  { 273,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #273 = LDSED_0R
735
  { 274,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #274 = LDSPC_0R
736
  { 275,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #275 = LDSSR_0R
737
  { 276,  2,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #276 = LDWCP_lru6
738
  { 277,  1,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #277 = LDWCP_lu10
739
  { 278,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #278 = LDWCP_ru6
740
  { 279,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #279 = LDWCP_u10
741
  { 280,  2,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #280 = LDWDP_lru6
742
  { 281,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #281 = LDWDP_ru6
743
  { 282,  2,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #282 = LDWSP_lru6
744
  { 283,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #283 = LDWSP_ru6
745
  { 284,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #284 = LDW_2rus
746
  { 285,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #285 = LDW_3r
747
  { 286,  6,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #286 = LMUL_l6r
748
  { 287,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #287 = LSS_3r
749
  { 288,  5,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #288 = LSUB_l5r
750
  { 289,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #289 = LSU_3r
751
  { 290,  6,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #290 = MACCS_l4r
752
  { 291,  6,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #291 = MACCU_l4r
753
  { 292,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #292 = MJOIN_1r
754
  { 293,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #293 = MKMSK_2r
755
  { 294,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #294 = MKMSK_rus
756
  { 295,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #295 = MSYNC_1r
757
  { 296,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #296 = MUL_l3r
758
  { 297,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #297 = NEG
759
  { 298,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #298 = NOT
760
  { 299,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #299 = OR_3r
761
  { 300,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #300 = OUTCT_2r
762
  { 301,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #301 = OUTCT_rus
763
  { 302,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #302 = OUTPW_l2rus
764
  { 303,  3,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #303 = OUTSHR_2r
765
  { 304,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #304 = OUTT_2r
766
  { 305,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #305 = OUT_2r
767
  { 306,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #306 = PEEK_2r
768
  { 307,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #307 = REMS_l3r
769
  { 308,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #308 = REMU_l3r
770
  { 309,  1,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #309 = RETSP_lu6
771
  { 310,  1,  0,  2,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #310 = RETSP_u6
772
  { 311,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #311 = SETCLK_l2r
773
  { 312,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #312 = SETCP_1r
774
  { 313,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #313 = SETC_l2r
775
  { 314,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #314 = SETC_lru6
776
  { 315,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #315 = SETC_ru6
777
  { 316,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #316 = SETDP_1r
778
  { 317,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #317 = SETD_2r
779
  { 318,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #318 = SETEV_1r
780
  { 319,  0,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, nullptr, -1 ,nullptr },  // Inst #319 = SETKEP_0R
781
  { 320,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #320 = SETN_l2r
782
  { 321,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #321 = SETPSC_2r
783
  { 322,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #322 = SETPS_l2r
784
  { 323,  2,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #323 = SETPT_2r
785
  { 324,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #324 = SETRDY_l2r
786
  { 325,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #325 = SETSP_1r
787
  { 326,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #326 = SETSR_branch_lu6
788
  { 327,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #327 = SETSR_branch_u6
789
  { 328,  1,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #328 = SETSR_lu6
790
  { 329,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #329 = SETSR_u6
791
  { 330,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #330 = SETTW_l2r
792
  { 331,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #331 = SETV_1r
793
  { 332,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #332 = SEXT_2r
794
  { 333,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #333 = SEXT_rus
795
  { 334,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #334 = SHL_2rus
796
  { 335,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #335 = SHL_3r
797
  { 336,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #336 = SHR_2rus
798
  { 337,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #337 = SHR_3r
799
  { 338,  0,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #338 = SSYNC_0r
800
  { 339,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #339 = ST16_l3r
801
  { 340,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #340 = ST8_l3r
802
  { 341,  0,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #341 = STET_0R
803
  { 342,  0,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #342 = STSED_0R
804
  { 343,  0,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #343 = STSPC_0R
805
  { 344,  0,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #344 = STSSR_0R
806
  { 345,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #345 = STWDP_lru6
807
  { 346,  2,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #346 = STWDP_ru6
808
  { 347,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #347 = STWSP_lru6
809
  { 348,  2,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #348 = STWSP_ru6
810
  { 349,  3,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #349 = STW_2rus
811
  { 350,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #350 = STW_l3r
812
  { 351,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #351 = SUB_2rus
813
  { 352,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #352 = SUB_3r
814
  { 353,  1,  0,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #353 = SYNCR_1r
815
  { 354,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #354 = TESTCT_2r
816
  { 355,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #355 = TESTLCL_l2r
817
  { 356,  2,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #356 = TESTWCT_2r
818
  { 357,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #357 = TSETMR_2r
819
  { 358,  3,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #358 = TSETR_3r
820
  { 359,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #359 = TSTART_1R
821
  { 360,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #360 = WAITEF_1R
822
  { 361,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #361 = WAITET_1R
823
  { 362,  0,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #362 = WAITEU_0R
824
  { 363,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #363 = XOR_l3r
825
  { 364,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #364 = ZEXT_2r
826
  { 365,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #365 = ZEXT_rus
827
};
828
829
extern const char XCoreInstrNameData[] = {
830
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
831
  /* 9 */ 'L', 'D', 'A', 'P', 'B', '_', 'u', '1', '0', 0,
832
  /* 19 */ 'B', 'L', 'R', 'B', '_', 'u', '1', '0', 0,
833
  /* 28 */ 'L', 'D', 'A', 'P', 'F', '_', 'u', '1', '0', 0,
834
  /* 38 */ 'B', 'L', 'R', 'F', '_', 'u', '1', '0', 0,
835
  /* 47 */ 'B', 'L', 'A', 'C', 'P', '_', 'u', '1', '0', 0,
836
  /* 57 */ 'L', 'D', 'W', 'C', 'P', '_', 'u', '1', '0', 0,
837
  /* 67 */ 'L', 'D', 'A', 'P', 'B', '_', 'l', 'u', '1', '0', 0,
838
  /* 78 */ 'B', 'L', 'R', 'B', '_', 'l', 'u', '1', '0', 0,
839
  /* 88 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', 0,
840
  /* 99 */ 'B', 'L', 'R', 'F', '_', 'l', 'u', '1', '0', 0,
841
  /* 109 */ 'B', 'L', 'A', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
842
  /* 120 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
843
  /* 131 */ 'B', 'R', '_', 'J', 'T', '3', '2', 0,
844
  /* 139 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
845
  /* 147 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
846
  /* 155 */ 'K', 'C', 'A', 'L', 'L', '_', 'u', '6', 0,
847
  /* 164 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'u', '6', 0,
848
  /* 174 */ 'E', 'X', 'T', 'D', 'P', '_', 'u', '6', 0,
849
  /* 183 */ 'R', 'E', 'T', 'S', 'P', '_', 'u', '6', 0,
850
  /* 192 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'u', '6', 0,
851
  /* 202 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'u', '6', 0,
852
  /* 213 */ 'E', 'X', 'T', 'S', 'P', '_', 'u', '6', 0,
853
  /* 222 */ 'C', 'L', 'R', 'S', 'R', '_', 'u', '6', 0,
854
  /* 231 */ 'G', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
855
  /* 240 */ 'S', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
856
  /* 249 */ 'B', 'L', 'A', 'T', '_', 'u', '6', 0,
857
  /* 257 */ 'B', 'R', 'B', 'U', '_', 'u', '6', 0,
858
  /* 265 */ 'B', 'R', 'F', 'U', '_', 'u', '6', 0,
859
  /* 273 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
860
  /* 289 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
861
  /* 305 */ 'K', 'C', 'A', 'L', 'L', '_', 'l', 'u', '6', 0,
862
  /* 315 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'l', 'u', '6', 0,
863
  /* 326 */ 'E', 'X', 'T', 'D', 'P', '_', 'l', 'u', '6', 0,
864
  /* 336 */ 'R', 'E', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
865
  /* 346 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
866
  /* 357 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
867
  /* 369 */ 'E', 'X', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
868
  /* 379 */ 'C', 'L', 'R', 'S', 'R', '_', 'l', 'u', '6', 0,
869
  /* 389 */ 'G', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
870
  /* 399 */ 'S', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
871
  /* 409 */ 'B', 'L', 'A', 'T', '_', 'l', 'u', '6', 0,
872
  /* 418 */ 'B', 'R', 'B', 'U', '_', 'l', 'u', '6', 0,
873
  /* 427 */ 'B', 'R', 'F', 'U', '_', 'l', 'u', '6', 0,
874
  /* 436 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
875
  /* 453 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
876
  /* 470 */ 'L', 'D', 'C', '_', 'r', 'u', '6', 0,
877
  /* 478 */ 'S', 'E', 'T', 'C', '_', 'r', 'u', '6', 0,
878
  /* 487 */ 'B', 'R', 'B', 'F', '_', 'r', 'u', '6', 0,
879
  /* 496 */ 'B', 'R', 'F', 'F', '_', 'r', 'u', '6', 0,
880
  /* 505 */ 'L', 'D', 'W', 'C', 'P', '_', 'r', 'u', '6', 0,
881
  /* 515 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
882
  /* 526 */ 'L', 'D', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
883
  /* 536 */ 'S', 'T', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
884
  /* 546 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
885
  /* 557 */ 'L', 'D', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
886
  /* 567 */ 'S', 'T', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
887
  /* 577 */ 'B', 'R', 'B', 'T', '_', 'r', 'u', '6', 0,
888
  /* 586 */ 'B', 'R', 'F', 'T', '_', 'r', 'u', '6', 0,
889
  /* 595 */ 'L', 'D', 'C', '_', 'l', 'r', 'u', '6', 0,
890
  /* 604 */ 'S', 'E', 'T', 'C', '_', 'l', 'r', 'u', '6', 0,
891
  /* 614 */ 'B', 'R', 'B', 'F', '_', 'l', 'r', 'u', '6', 0,
892
  /* 624 */ 'B', 'R', 'F', 'F', '_', 'l', 'r', 'u', '6', 0,
893
  /* 634 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'r', 'u', '6', 0,
894
  /* 645 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
895
  /* 657 */ 'L', 'D', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
896
  /* 668 */ 'S', 'T', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
897
  /* 679 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
898
  /* 691 */ 'L', 'D', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
899
  /* 702 */ 'S', 'T', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
900
  /* 713 */ 'B', 'R', 'B', 'T', '_', 'l', 'r', 'u', '6', 0,
901
  /* 723 */ 'B', 'R', 'F', 'T', '_', 'l', 'r', 'u', '6', 0,
902
  /* 733 */ 'G', '_', 'F', 'M', 'A', 0,
903
  /* 739 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
904
  /* 746 */ 'G', '_', 'S', 'U', 'B', 0,
905
  /* 752 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
906
  /* 768 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 0,
907
  /* 778 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
908
  /* 790 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
909
  /* 800 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
910
  /* 818 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
911
  /* 826 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
912
  /* 847 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
913
  /* 858 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
914
  /* 869 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
915
  /* 876 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
916
  /* 883 */ 'G', '_', 'A', 'D', 'D', 0,
917
  /* 889 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
918
  /* 905 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
919
  /* 922 */ 'G', '_', 'A', 'N', 'D', 0,
920
  /* 928 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
921
  /* 944 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
922
  /* 957 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
923
  /* 966 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
924
  /* 984 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
925
  /* 1001 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
926
  /* 1009 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
927
  /* 1017 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
928
  /* 1030 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
929
  /* 1038 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
930
  /* 1046 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
931
  /* 1053 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
932
  /* 1066 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
933
  /* 1074 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
934
  /* 1084 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
935
  /* 1099 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
936
  /* 1117 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
937
  /* 1135 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
938
  /* 1150 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
939
  /* 1157 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
940
  /* 1172 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
941
  /* 1186 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
942
  /* 1200 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
943
  /* 1217 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
944
  /* 1234 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
945
  /* 1241 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
946
  /* 1249 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
947
  /* 1257 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
948
  /* 1265 */ 'L', 'D', 'A', 'W', 'F', 'I', 0,
949
  /* 1272 */ 'L', 'D', 'W', 'F', 'I', 0,
950
  /* 1278 */ 'S', 'T', 'W', 'F', 'I', 0,
951
  /* 1284 */ 'G', '_', 'P', 'H', 'I', 0,
952
  /* 1290 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
953
  /* 1299 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
954
  /* 1308 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
955
  /* 1319 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
956
  /* 1328 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
957
  /* 1338 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
958
  /* 1347 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
959
  /* 1364 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
960
  /* 1384 */ 'G', '_', 'S', 'H', 'L', 0,
961
  /* 1390 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
962
  /* 1410 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
963
  /* 1437 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
964
  /* 1458 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
965
  /* 1470 */ 'K', 'I', 'L', 'L', 0,
966
  /* 1475 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
967
  /* 1482 */ 'G', '_', 'M', 'U', 'L', 0,
968
  /* 1488 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
969
  /* 1495 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
970
  /* 1502 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
971
  /* 1509 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
972
  /* 1519 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
973
  /* 1536 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
974
  /* 1552 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
975
  /* 1568 */ 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 0,
976
  /* 1578 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
977
  /* 1595 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
978
  /* 1603 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
979
  /* 1611 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
980
  /* 1619 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
981
  /* 1627 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
982
  /* 1635 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
983
  /* 1643 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
984
  /* 1652 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
985
  /* 1660 */ 'G', '_', 'G', 'E', 'P', 0,
986
  /* 1666 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
987
  /* 1675 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
988
  /* 1684 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
989
  /* 1691 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
990
  /* 1698 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
991
  /* 1706 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
992
  /* 1719 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
993
  /* 1731 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
994
  /* 1746 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
995
  /* 1753 */ 'L', 'D', 'S', 'P', 'C', '_', '0', 'R', 0,
996
  /* 1762 */ 'S', 'T', 'S', 'P', 'C', '_', '0', 'R', 0,
997
  /* 1771 */ 'L', 'D', 'S', 'E', 'D', '_', '0', 'R', 0,
998
  /* 1780 */ 'S', 'T', 'S', 'E', 'D', '_', '0', 'R', 0,
999
  /* 1789 */ 'G', 'E', 'T', 'E', 'D', '_', '0', 'R', 0,
1000
  /* 1798 */ 'G', 'E', 'T', 'I', 'D', '_', '0', 'R', 0,
1001
  /* 1807 */ 'C', 'L', 'R', 'E', '_', '0', 'R', 0,
1002
  /* 1815 */ 'D', 'C', 'A', 'L', 'L', '_', '0', 'R', 0,
1003
  /* 1824 */ 'G', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
1004
  /* 1834 */ 'S', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
1005
  /* 1844 */ 'G', 'E', 'T', 'K', 'S', 'P', '_', '0', 'R', 0,
1006
  /* 1854 */ 'D', 'E', 'N', 'T', 'S', 'P', '_', '0', 'R', 0,
1007
  /* 1864 */ 'D', 'R', 'E', 'S', 'T', 'S', 'P', '_', '0', 'R', 0,
1008
  /* 1875 */ 'L', 'D', 'S', 'S', 'R', '_', '0', 'R', 0,
1009
  /* 1884 */ 'S', 'T', 'S', 'S', 'R', '_', '0', 'R', 0,
1010
  /* 1893 */ 'L', 'D', 'E', 'T', '_', '0', 'R', 0,
1011
  /* 1901 */ 'F', 'R', 'E', 'E', 'T', '_', '0', 'R', 0,
1012
  /* 1910 */ 'D', 'R', 'E', 'T', '_', '0', 'R', 0,
1013
  /* 1918 */ 'K', 'R', 'E', 'T', '_', '0', 'R', 0,
1014
  /* 1926 */ 'G', 'E', 'T', 'E', 'T', '_', '0', 'R', 0,
1015
  /* 1935 */ 'S', 'T', 'E', 'T', '_', '0', 'R', 0,
1016
  /* 1943 */ 'W', 'A', 'I', 'T', 'E', 'U', '_', '0', 'R', 0,
1017
  /* 1953 */ 'W', 'A', 'I', 'T', 'E', 'F', '_', '1', 'R', 0,
1018
  /* 1963 */ 'W', 'A', 'I', 'T', 'E', 'T', '_', '1', 'R', 0,
1019
  /* 1973 */ 'C', 'L', 'R', 'P', 'T', '_', '1', 'R', 0,
1020
  /* 1982 */ 'T', 'S', 'T', 'A', 'R', 'T', '_', '1', 'R', 0,
1021
  /* 1992 */ 'G', '_', 'B', 'R', 0,
1022
  /* 1997 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
1023
  /* 2010 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1024
  /* 2035 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1025
  /* 2042 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1026
  /* 2049 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1027
  /* 2064 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1028
  /* 2081 */ 'G', '_', 'X', 'O', 'R', 0,
1029
  /* 2087 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1030
  /* 2103 */ 'G', '_', 'O', 'R', 0,
1031
  /* 2108 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1032
  /* 2123 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1033
  /* 2134 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1034
  /* 2141 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1035
  /* 2158 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1036
  /* 2173 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
1037
  /* 2190 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1038
  /* 2207 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1039
  /* 2237 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1040
  /* 2264 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1041
  /* 2274 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1042
  /* 2283 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1043
  /* 2296 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1044
  /* 2310 */ 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 0,
1045
  /* 2331 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1046
  /* 2355 */ 'B', 'R', '_', 'J', 'T', 0,
1047
  /* 2361 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1048
  /* 2382 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1049
  /* 2402 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1050
  /* 2414 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1051
  /* 2425 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1052
  /* 2436 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1053
  /* 2447 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1054
  /* 2458 */ 'N', 'O', 'T', 0,
1055
  /* 2462 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1056
  /* 2472 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1057
  /* 2487 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1058
  /* 2496 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1059
  /* 2506 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1060
  /* 2523 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1061
  /* 2531 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1062
  /* 2538 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1063
  /* 2547 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1064
  /* 2554 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1065
  /* 2561 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1066
  /* 2568 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1067
  /* 2575 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1068
  /* 2582 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1069
  /* 2599 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1070
  /* 2615 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1071
  /* 2629 */ 'C', 'O', 'P', 'Y', 0,
1072
  /* 2634 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
1073
  /* 2641 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
1074
  /* 2648 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', '_', 'b', 'a', 0,
1075
  /* 2662 */ 'S', 'S', 'Y', 'N', 'C', '_', '0', 'r', 0,
1076
  /* 2671 */ 'B', 'L', 'A', '_', '1', 'r', 0,
1077
  /* 2678 */ 'M', 'S', 'Y', 'N', 'C', '_', '1', 'r', 0,
1078
  /* 2687 */ 'E', 'C', 'A', 'L', 'L', 'F', '_', '1', 'r', 0,
1079
  /* 2697 */ 'D', 'G', 'E', 'T', 'R', 'E', 'G', '_', '1', 'r', 0,
1080
  /* 2708 */ 'K', 'C', 'A', 'L', 'L', '_', '1', 'r', 0,
1081
  /* 2717 */ 'M', 'J', 'O', 'I', 'N', '_', '1', 'r', 0,
1082
  /* 2726 */ 'S', 'E', 'T', 'C', 'P', '_', '1', 'r', 0,
1083
  /* 2735 */ 'S', 'E', 'T', 'D', 'P', '_', '1', 'r', 0,
1084
  /* 2744 */ 'S', 'E', 'T', 'S', 'P', '_', '1', 'r', 0,
1085
  /* 2753 */ 'S', 'Y', 'N', 'C', 'R', '_', '1', 'r', 0,
1086
  /* 2762 */ 'F', 'R', 'E', 'E', 'R', '_', '1', 'r', 0,
1087
  /* 2771 */ 'E', 'C', 'A', 'L', 'L', 'T', '_', '1', 'r', 0,
1088
  /* 2781 */ 'B', 'A', 'U', '_', '1', 'r', 0,
1089
  /* 2788 */ 'E', 'D', 'U', '_', '1', 'r', 0,
1090
  /* 2795 */ 'E', 'E', 'U', '_', '1', 'r', 0,
1091
  /* 2802 */ 'B', 'R', 'U', '_', '1', 'r', 0,
1092
  /* 2809 */ 'S', 'E', 'T', 'E', 'V', '_', '1', 'r', 0,
1093
  /* 2818 */ 'S', 'E', 'T', 'V', '_', '1', 'r', 0,
1094
  /* 2826 */ 'I', 'N', 'I', 'T', 'P', 'C', '_', '2', 'r', 0,
1095
  /* 2836 */ 'S', 'E', 'T', 'P', 'S', 'C', '_', '2', 'r', 0,
1096
  /* 2846 */ 'S', 'E', 'T', 'D', '_', '2', 'r', 0,
1097
  /* 2854 */ 'E', 'E', 'F', '_', '2', 'r', 0,
1098
  /* 2861 */ 'P', 'E', 'E', 'K', '_', '2', 'r', 0,
1099
  /* 2869 */ 'M', 'K', 'M', 'S', 'K', '_', '2', 'r', 0,
1100
  /* 2878 */ 'E', 'N', 'D', 'I', 'N', '_', '2', 'r', 0,
1101
  /* 2887 */ 'I', 'N', 'I', 'T', 'C', 'P', '_', '2', 'r', 0,
1102
  /* 2897 */ 'I', 'N', 'I', 'T', 'D', 'P', '_', '2', 'r', 0,
1103
  /* 2907 */ 'I', 'N', 'I', 'T', 'S', 'P', '_', '2', 'r', 0,
1104
  /* 2917 */ 'I', 'N', 'S', 'H', 'R', '_', '2', 'r', 0,
1105
  /* 2926 */ 'O', 'U', 'T', 'S', 'H', 'R', '_', '2', 'r', 0,
1106
  /* 2936 */ 'T', 'S', 'E', 'T', 'M', 'R', '_', '2', 'r', 0,
1107
  /* 2946 */ 'G', 'E', 'T', 'T', 'S', '_', '2', 'r', 0,
1108
  /* 2955 */ 'C', 'H', 'K', 'C', 'T', '_', '2', 'r', 0,
1109
  /* 2964 */ 'I', 'N', 'C', 'T', '_', '2', 'r', 0,
1110
  /* 2972 */ 'T', 'E', 'S', 'T', 'C', 'T', '_', '2', 'r', 0,
1111
  /* 2982 */ 'O', 'U', 'T', 'C', 'T', '_', '2', 'r', 0,
1112
  /* 2991 */ 'T', 'E', 'S', 'T', 'W', 'C', 'T', '_', '2', 'r', 0,
1113
  /* 3002 */ 'E', 'E', 'T', '_', '2', 'r', 0,
1114
  /* 3009 */ 'I', 'N', 'T', '_', '2', 'r', 0,
1115
  /* 3016 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', '2', 'r', 0,
1116
  /* 3026 */ 'S', 'E', 'T', 'P', 'T', '_', '2', 'r', 0,
1117
  /* 3035 */ 'G', 'E', 'T', 'S', 'T', '_', '2', 'r', 0,
1118
  /* 3044 */ 'O', 'U', 'T', 'T', '_', '2', 'r', 0,
1119
  /* 3052 */ 'O', 'U', 'T', '_', '2', 'r', 0,
1120
  /* 3059 */ 'S', 'E', 'X', 'T', '_', '2', 'r', 0,
1121
  /* 3067 */ 'Z', 'E', 'X', 'T', '_', '2', 'r', 0,
1122
  /* 3075 */ 'S', 'E', 'T', 'C', '_', 'l', '2', 'r', 0,
1123
  /* 3084 */ 'G', 'E', 'T', 'D', '_', 'l', '2', 'r', 0,
1124
  /* 3093 */ 'S', 'E', 'T', 'C', 'L', 'K', '_', 'l', '2', 'r', 0,
1125
  /* 3104 */ 'T', 'E', 'S', 'T', 'L', 'C', 'L', '_', 'l', '2', 'r', 0,
1126
  /* 3116 */ 'G', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
1127
  /* 3125 */ 'S', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
1128
  /* 3134 */ 'I', 'N', 'I', 'T', 'L', 'R', '_', 'l', '2', 'r', 0,
1129
  /* 3145 */ 'G', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
1130
  /* 3155 */ 'S', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
1131
  /* 3165 */ 'B', 'Y', 'T', 'E', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
1132
  /* 3177 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
1133
  /* 3188 */ 'S', 'E', 'T', 'T', 'W', '_', 'l', '2', 'r', 0,
1134
  /* 3198 */ 'S', 'E', 'T', 'R', 'D', 'Y', '_', 'l', '2', 'r', 0,
1135
  /* 3209 */ 'C', 'L', 'Z', '_', 'l', '2', 'r', 0,
1136
  /* 3217 */ 'S', 'U', 'B', '_', '3', 'r', 0,
1137
  /* 3224 */ 'A', 'D', 'D', '_', '3', 'r', 0,
1138
  /* 3231 */ 'A', 'N', 'D', '_', '3', 'r', 0,
1139
  /* 3238 */ 'S', 'H', 'L', '_', '3', 'r', 0,
1140
  /* 3245 */ 'E', 'Q', '_', '3', 'r', 0,
1141
  /* 3251 */ 'S', 'H', 'R', '_', '3', 'r', 0,
1142
  /* 3258 */ 'O', 'R', '_', '3', 'r', 0,
1143
  /* 3264 */ 'T', 'S', 'E', 'T', 'R', '_', '3', 'r', 0,
1144
  /* 3273 */ 'L', 'D', '1', '6', 'S', '_', '3', 'r', 0,
1145
  /* 3282 */ 'L', 'S', 'S', '_', '3', 'r', 0,
1146
  /* 3289 */ 'L', 'D', '8', 'U', '_', '3', 'r', 0,
1147
  /* 3297 */ 'L', 'S', 'U', '_', '3', 'r', 0,
1148
  /* 3304 */ 'L', 'D', 'W', '_', '3', 'r', 0,
1149
  /* 3311 */ 'S', 'T', '1', '6', '_', 'l', '3', 'r', 0,
1150
  /* 3320 */ 'S', 'T', '8', '_', 'l', '3', 'r', 0,
1151
  /* 3328 */ 'L', 'D', 'A', '1', '6', 'B', '_', 'l', '3', 'r', 0,
1152
  /* 3339 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '3', 'r', 0,
1153
  /* 3349 */ 'C', 'R', 'C', '_', 'l', '3', 'r', 0,
1154
  /* 3357 */ 'L', 'D', 'A', '1', '6', 'F', '_', 'l', '3', 'r', 0,
1155
  /* 3368 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '3', 'r', 0,
1156
  /* 3378 */ 'M', 'U', 'L', '_', 'l', '3', 'r', 0,
1157
  /* 3386 */ 'A', 'S', 'H', 'R', '_', 'l', '3', 'r', 0,
1158
  /* 3395 */ 'X', 'O', 'R', '_', 'l', '3', 'r', 0,
1159
  /* 3403 */ 'R', 'E', 'M', 'S', '_', 'l', '3', 'r', 0,
1160
  /* 3412 */ 'D', 'I', 'V', 'S', '_', 'l', '3', 'r', 0,
1161
  /* 3421 */ 'R', 'E', 'M', 'U', '_', 'l', '3', 'r', 0,
1162
  /* 3430 */ 'D', 'I', 'V', 'U', '_', 'l', '3', 'r', 0,
1163
  /* 3439 */ 'S', 'T', 'W', '_', 'l', '3', 'r', 0,
1164
  /* 3447 */ 'C', 'R', 'C', '8', '_', 'l', '4', 'r', 0,
1165
  /* 3456 */ 'M', 'A', 'C', 'C', 'S', '_', 'l', '4', 'r', 0,
1166
  /* 3466 */ 'M', 'A', 'C', 'C', 'U', '_', 'l', '4', 'r', 0,
1167
  /* 3476 */ 'L', 'S', 'U', 'B', '_', 'l', '5', 'r', 0,
1168
  /* 3485 */ 'L', 'A', 'D', 'D', '_', 'l', '5', 'r', 0,
1169
  /* 3494 */ 'L', 'D', 'I', 'V', 'U', '_', 'l', '5', 'r', 0,
1170
  /* 3504 */ 'L', 'M', 'U', 'L', '_', 'l', '6', 'r', 0,
1171
  /* 3513 */ 'I', 'n', 't', '_', 'M', 'e', 'm', 'B', 'a', 'r', 'r', 'i', 'e', 'r', 0,
1172
  /* 3528 */ 'S', 'U', 'B', '_', '2', 'r', 'u', 's', 0,
1173
  /* 3537 */ 'A', 'D', 'D', '_', '2', 'r', 'u', 's', 0,
1174
  /* 3546 */ 'S', 'H', 'L', '_', '2', 'r', 'u', 's', 0,
1175
  /* 3555 */ 'E', 'Q', '_', '2', 'r', 'u', 's', 0,
1176
  /* 3563 */ 'S', 'H', 'R', '_', '2', 'r', 'u', 's', 0,
1177
  /* 3572 */ 'L', 'D', 'W', '_', '2', 'r', 'u', 's', 0,
1178
  /* 3581 */ 'S', 'T', 'W', '_', '2', 'r', 'u', 's', 0,
1179
  /* 3590 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '2', 'r', 'u', 's', 0,
1180
  /* 3602 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '2', 'r', 'u', 's', 0,
1181
  /* 3614 */ 'A', 'S', 'H', 'R', '_', 'l', '2', 'r', 'u', 's', 0,
1182
  /* 3625 */ 'I', 'N', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
1183
  /* 3636 */ 'O', 'U', 'T', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
1184
  /* 3648 */ 'M', 'K', 'M', 'S', 'K', '_', 'r', 'u', 's', 0,
1185
  /* 3658 */ 'G', 'E', 'T', 'R', '_', 'r', 'u', 's', 0,
1186
  /* 3667 */ 'C', 'H', 'K', 'C', 'T', '_', 'r', 'u', 's', 0,
1187
  /* 3677 */ 'O', 'U', 'T', 'C', 'T', '_', 'r', 'u', 's', 0,
1188
  /* 3687 */ 'S', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
1189
  /* 3696 */ 'Z', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
1190
};
1191
1192
extern const unsigned XCoreInstrNameIndices[] = {
1193
    1286U, 1509U, 1552U, 1338U, 1319U, 1347U, 1470U, 1157U, 
1194
    1172U, 1137U, 1186U, 2190U, 1074U, 1328U, 1017U, 2629U, 
1195
    1046U, 2472U, 944U, 1643U, 1458U, 2436U, 984U, 2425U, 
1196
    1053U, 1719U, 1706U, 2010U, 2296U, 2331U, 1390U, 1437U, 
1197
    1410U, 1364U, 883U, 746U, 1482U, 2561U, 2568U, 1495U, 
1198
    1502U, 922U, 2103U, 2081U, 1135U, 1284U, 2615U, 1084U, 
1199
    2264U, 2141U, 2487U, 2158U, 2049U, 826U, 2173U, 2447U, 
1200
    2123U, 2496U, 800U, 966U, 869U, 847U, 858U, 1066U, 
1201
    2207U, 1200U, 1217U, 889U, 752U, 928U, 905U, 2108U, 
1202
    2087U, 2599U, 1536U, 2582U, 1519U, 957U, 2283U, 778U, 
1203
    2237U, 2538U, 818U, 2414U, 2402U, 2462U, 1241U, 2531U, 
1204
    2547U, 1384U, 2042U, 2035U, 1691U, 1684U, 2274U, 1619U, 
1205
    1038U, 1603U, 1009U, 1611U, 1030U, 1595U, 1001U, 1635U, 
1206
    1627U, 1257U, 1249U, 876U, 739U, 1475U, 733U, 2554U, 
1207
    1488U, 2575U, 1746U, 147U, 1234U, 139U, 0U, 1150U, 
1208
    2523U, 790U, 1290U, 1299U, 1666U, 1675U, 2134U, 1660U, 
1209
    1308U, 1992U, 2382U, 2361U, 2064U, 2641U, 1117U, 2634U, 
1210
    1099U, 1698U, 1652U, 2506U, 1997U, 1578U, 1731U, 2355U, 
1211
    131U, 1568U, 2310U, 3513U, 1265U, 1272U, 768U, 1278U, 
1212
    3537U, 3224U, 3016U, 3231U, 3614U, 3386U, 2781U, 3177U, 
1213
    109U, 47U, 409U, 249U, 2671U, 78U, 19U, 99U, 
1214
    38U, 614U, 487U, 713U, 577U, 418U, 257U, 624U, 
1215
    496U, 723U, 586U, 427U, 265U, 2802U, 3165U, 2955U, 
1216
    3667U, 1807U, 1973U, 436U, 273U, 379U, 222U, 3209U, 
1217
    3447U, 3349U, 1815U, 1854U, 2697U, 3412U, 3430U, 1864U, 
1218
    1910U, 2687U, 2771U, 2788U, 2854U, 3002U, 2795U, 2878U, 
1219
    347U, 193U, 3555U, 3245U, 326U, 174U, 369U, 213U, 
1220
    2762U, 1901U, 3084U, 1789U, 1926U, 1798U, 1824U, 1844U, 
1221
    3116U, 3145U, 3658U, 389U, 231U, 3035U, 2946U, 2964U, 
1222
    2887U, 2897U, 3134U, 2826U, 2907U, 3625U, 2917U, 3009U, 
1223
    2881U, 2708U, 305U, 155U, 346U, 192U, 357U, 202U, 
1224
    1918U, 3485U, 3273U, 3289U, 3328U, 3357U, 67U, 9U, 
1225
    88U, 2648U, 28U, 3590U, 3339U, 315U, 164U, 645U, 
1226
    515U, 3602U, 3368U, 679U, 546U, 595U, 470U, 1893U, 
1227
    3494U, 1771U, 1753U, 1875U, 634U, 120U, 505U, 57U, 
1228
    657U, 526U, 691U, 557U, 3572U, 3304U, 3504U, 3282U, 
1229
    3476U, 3297U, 3456U, 3466U, 2717U, 2869U, 3648U, 2678U, 
1230
    3378U, 1153U, 2458U, 3258U, 2982U, 3677U, 3636U, 2926U, 
1231
    3044U, 3052U, 2861U, 3403U, 3421U, 336U, 183U, 3093U, 
1232
    2726U, 3075U, 604U, 478U, 2735U, 2846U, 2809U, 1834U, 
1233
    3125U, 2836U, 3155U, 3026U, 3198U, 2744U, 453U, 289U, 
1234
    399U, 240U, 3188U, 2818U, 3059U, 3687U, 3546U, 3238U, 
1235
    3563U, 3251U, 2662U, 3311U, 3320U, 1935U, 1780U, 1762U, 
1236
    1884U, 668U, 536U, 702U, 567U, 3581U, 3439U, 3528U, 
1237
    3217U, 2753U, 2972U, 3104U, 2991U, 2936U, 3264U, 1982U, 
1238
    1953U, 1963U, 1943U, 3395U, 3067U, 3696U, 
1239
};
1240
1241
81
static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1242
81
  II->InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 366);
1243
81
}
1244
1245
} // end llvm namespace
1246
#endif // GET_INSTRINFO_MC_DESC
1247
1248
#ifdef GET_INSTRINFO_HEADER
1249
#undef GET_INSTRINFO_HEADER
1250
namespace llvm {
1251
struct XCoreGenInstrInfo : public TargetInstrInfo {
1252
  explicit XCoreGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1253
78
  ~XCoreGenInstrInfo() override = default;
1254
1255
};
1256
} // end llvm namespace
1257
#endif // GET_INSTRINFO_HEADER
1258
1259
#ifdef GET_INSTRINFO_HELPER_DECLS
1260
#undef GET_INSTRINFO_HELPER_DECLS
1261
1262
1263
#endif // GET_INSTRINFO_HELPER_DECLS
1264
1265
#ifdef GET_INSTRINFO_HELPERS
1266
#undef GET_INSTRINFO_HELPERS
1267
1268
#endif // GET_INSTRINFO_HELPERS
1269
1270
#ifdef GET_INSTRINFO_CTOR_DTOR
1271
#undef GET_INSTRINFO_CTOR_DTOR
1272
namespace llvm {
1273
extern const MCInstrDesc XCoreInsts[];
1274
extern const unsigned XCoreInstrNameIndices[];
1275
extern const char XCoreInstrNameData[];
1276
XCoreGenInstrInfo::XCoreGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1277
80
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1278
80
  InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 366);
1279
80
}
1280
} // end llvm namespace
1281
#endif // GET_INSTRINFO_CTOR_DTOR
1282
1283
#ifdef GET_INSTRINFO_OPERAND_ENUM
1284
#undef GET_INSTRINFO_OPERAND_ENUM
1285
namespace llvm {
1286
namespace XCore {
1287
namespace OpName {
1288
enum {
1289
OPERAND_LAST
1290
};
1291
} // end namespace OpName
1292
} // end namespace XCore
1293
} // end namespace llvm
1294
#endif //GET_INSTRINFO_OPERAND_ENUM
1295
1296
#ifdef GET_INSTRINFO_NAMED_OPS
1297
#undef GET_INSTRINFO_NAMED_OPS
1298
namespace llvm {
1299
namespace XCore {
1300
LLVM_READONLY
1301
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1302
  return -1;
1303
}
1304
} // end namespace XCore
1305
} // end namespace llvm
1306
#endif //GET_INSTRINFO_NAMED_OPS
1307
1308
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1309
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1310
namespace llvm {
1311
namespace XCore {
1312
namespace OpTypes {
1313
enum OperandType {
1314
  InlineJT = 0,
1315
  InlineJT32 = 1,
1316
  MEMii = 2,
1317
  brtarget = 3,
1318
  brtarget_neg = 4,
1319
  f32imm = 5,
1320
  f64imm = 6,
1321
  i16imm = 7,
1322
  i1imm = 8,
1323
  i32imm = 9,
1324
  i64imm = 10,
1325
  i8imm = 11,
1326
  pcrel_imm = 12,
1327
  pcrel_imm_neg = 13,
1328
  ptype0 = 14,
1329
  ptype1 = 15,
1330
  ptype2 = 16,
1331
  ptype3 = 17,
1332
  ptype4 = 18,
1333
  ptype5 = 19,
1334
  type0 = 20,
1335
  type1 = 21,
1336
  type2 = 22,
1337
  type3 = 23,
1338
  type4 = 24,
1339
  type5 = 25,
1340
  OPERAND_TYPE_LIST_END
1341
};
1342
} // end namespace OpTypes
1343
} // end namespace XCore
1344
} // end namespace llvm
1345
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1346