Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/XCore/XCoreGenRegisterInfo.inc
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Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
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#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
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13
namespace llvm {
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class MCRegisterClass;
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extern const MCRegisterClass XCoreMCRegisterClasses[];
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namespace XCore {
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enum {
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  NoRegister,
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  CP = 1,
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  DP = 2,
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  LR = 3,
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  SP = 4,
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  R0 = 5,
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  R1 = 6,
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  R2 = 7,
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  R3 = 8,
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  R4 = 9,
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  R5 = 10,
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  R6 = 11,
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  R7 = 12,
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  R8 = 13,
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  R9 = 14,
35
  R10 = 15,
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  R11 = 16,
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  NUM_TARGET_REGS   // 17
38
};
39
} // end namespace XCore
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// Register classes
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43
namespace XCore {
44
enum {
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  RRegsRegClassID = 0,
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  GRRegsRegClassID = 1,
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  };
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} // end namespace XCore
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} // end namespace llvm
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* MC Register Information                                                    *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
65
#undef GET_REGINFO_MC_DESC
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namespace llvm {
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extern const MCPhysReg XCoreRegDiffLists[] = {
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  /* 0 */ 65535, 0,
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};
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extern const LaneBitmask XCoreLaneMaskLists[] = {
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  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
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};
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extern const uint16_t XCoreSubRegIdxLists[] = {
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  /* 0 */ 0,
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};
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extern const MCRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRanges[] = {
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  { 65535, 65535 },
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};
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extern const char XCoreRegStrings[] = {
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  /* 0 */ 'R', '1', '0', 0,
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  /* 4 */ 'R', '0', 0,
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  /* 7 */ 'R', '1', '1', 0,
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  /* 11 */ 'R', '1', 0,
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  /* 14 */ 'R', '2', 0,
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  /* 17 */ 'R', '3', 0,
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  /* 20 */ 'R', '4', 0,
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  /* 23 */ 'R', '5', 0,
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  /* 26 */ 'R', '6', 0,
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  /* 29 */ 'R', '7', 0,
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  /* 32 */ 'R', '8', 0,
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  /* 35 */ 'R', '9', 0,
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  /* 38 */ 'C', 'P', 0,
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  /* 41 */ 'D', 'P', 0,
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  /* 44 */ 'S', 'P', 0,
101
  /* 47 */ 'L', 'R', 0,
102
};
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extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
105
  { 3, 0, 0, 0, 0, 0 },
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  { 38, 1, 1, 0, 1, 0 },
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  { 41, 1, 1, 0, 1, 0 },
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  { 47, 1, 1, 0, 1, 0 },
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  { 44, 1, 1, 0, 1, 0 },
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  { 4, 1, 1, 0, 1, 0 },
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  { 11, 1, 1, 0, 1, 0 },
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  { 14, 1, 1, 0, 1, 0 },
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  { 17, 1, 1, 0, 1, 0 },
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  { 20, 1, 1, 0, 1, 0 },
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  { 23, 1, 1, 0, 1, 0 },
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  { 26, 1, 1, 0, 1, 0 },
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  { 29, 1, 1, 0, 1, 0 },
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  { 32, 1, 1, 0, 1, 0 },
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  { 35, 1, 1, 0, 1, 0 },
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  { 0, 1, 1, 0, 1, 0 },
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  { 7, 1, 1, 0, 1, 0 },
122
};
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extern const MCPhysReg XCoreRegUnitRoots[][2] = {
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  { XCore::CP },
126
  { XCore::DP },
127
  { XCore::LR },
128
  { XCore::SP },
129
  { XCore::R0 },
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  { XCore::R1 },
131
  { XCore::R2 },
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  { XCore::R3 },
133
  { XCore::R4 },
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  { XCore::R5 },
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  { XCore::R6 },
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  { XCore::R7 },
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  { XCore::R8 },
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  { XCore::R9 },
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  { XCore::R10 },
140
  { XCore::R11 },
141
};
142
143
namespace {     // Register classes...
144
  // RRegs Register Class...
145
  const MCPhysReg RRegs[] = {
146
    XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR, 
147
  };
148
149
  // RRegs Bit set.
150
  const uint8_t RRegsBits[] = {
151
    0xfe, 0xff, 0x01, 
152
  };
153
154
  // GRRegs Register Class...
155
  const MCPhysReg GRRegs[] = {
156
    XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, 
157
  };
158
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  // GRRegs Bit set.
160
  const uint8_t GRRegsBits[] = {
161
    0xe0, 0xff, 0x01, 
162
  };
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164
} // end anonymous namespace
165
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extern const char XCoreRegClassStrings[] = {
167
  /* 0 */ 'G', 'R', 'R', 'e', 'g', 's', 0,
168
};
169
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extern const MCRegisterClass XCoreMCRegisterClasses[] = {
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  { RRegs, RRegsBits, 1, 16, sizeof(RRegsBits), XCore::RRegsRegClassID, 1, false },
172
  { GRRegs, GRRegsBits, 0, 12, sizeof(GRRegsBits), XCore::GRRegsRegClassID, 1, true },
173
};
174
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// XCore Dwarf<->LLVM register mappings.
176
extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
177
  { 0U, XCore::R0 },
178
  { 1U, XCore::R1 },
179
  { 2U, XCore::R2 },
180
  { 3U, XCore::R3 },
181
  { 4U, XCore::R4 },
182
  { 5U, XCore::R5 },
183
  { 6U, XCore::R6 },
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  { 7U, XCore::R7 },
185
  { 8U, XCore::R8 },
186
  { 9U, XCore::R9 },
187
  { 10U, XCore::R10 },
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  { 11U, XCore::R11 },
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  { 12U, XCore::CP },
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  { 13U, XCore::DP },
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  { 14U, XCore::SP },
192
  { 15U, XCore::LR },
193
};
194
extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = array_lengthof(XCoreDwarfFlavour0Dwarf2L);
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extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
197
  { 0U, XCore::R0 },
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  { 1U, XCore::R1 },
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  { 2U, XCore::R2 },
200
  { 3U, XCore::R3 },
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  { 4U, XCore::R4 },
202
  { 5U, XCore::R5 },
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  { 6U, XCore::R6 },
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  { 7U, XCore::R7 },
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  { 8U, XCore::R8 },
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  { 9U, XCore::R9 },
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  { 10U, XCore::R10 },
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  { 11U, XCore::R11 },
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  { 12U, XCore::CP },
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  { 13U, XCore::DP },
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  { 14U, XCore::SP },
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  { 15U, XCore::LR },
213
};
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extern const unsigned XCoreEHFlavour0Dwarf2LSize = array_lengthof(XCoreEHFlavour0Dwarf2L);
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extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
217
  { XCore::CP, 12U },
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  { XCore::DP, 13U },
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  { XCore::LR, 15U },
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  { XCore::SP, 14U },
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  { XCore::R0, 0U },
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  { XCore::R1, 1U },
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  { XCore::R2, 2U },
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  { XCore::R3, 3U },
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  { XCore::R4, 4U },
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  { XCore::R5, 5U },
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  { XCore::R6, 6U },
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  { XCore::R7, 7U },
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  { XCore::R8, 8U },
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  { XCore::R9, 9U },
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  { XCore::R10, 10U },
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  { XCore::R11, 11U },
233
};
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extern const unsigned XCoreDwarfFlavour0L2DwarfSize = array_lengthof(XCoreDwarfFlavour0L2Dwarf);
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extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
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  { XCore::CP, 12U },
238
  { XCore::DP, 13U },
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  { XCore::LR, 15U },
240
  { XCore::SP, 14U },
241
  { XCore::R0, 0U },
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  { XCore::R1, 1U },
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  { XCore::R2, 2U },
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  { XCore::R3, 3U },
245
  { XCore::R4, 4U },
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  { XCore::R5, 5U },
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  { XCore::R6, 6U },
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  { XCore::R7, 7U },
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  { XCore::R8, 8U },
250
  { XCore::R9, 9U },
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  { XCore::R10, 10U },
252
  { XCore::R11, 11U },
253
};
254
extern const unsigned XCoreEHFlavour0L2DwarfSize = array_lengthof(XCoreEHFlavour0L2Dwarf);
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extern const uint16_t XCoreRegEncodingTable[] = {
257
  0,
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  0,
259
  0,
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  0,
261
  0,
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  0,
263
  0,
264
  0,
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  0,
266
  0,
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  0,
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  0,
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  0,
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  0,
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  0,
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  0,
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  0,
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};
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static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
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  RI->InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, XCoreMCRegisterClasses, 2, XCoreRegUnitRoots, 16, XCoreRegDiffLists, XCoreLaneMaskLists, XCoreRegStrings, XCoreRegClassStrings, XCoreSubRegIdxLists, 1,
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82
XCoreSubRegIdxRanges, XCoreRegEncodingTable);
278
82
279
82
  switch (DwarfFlavour) {
280
82
  default:
281
0
    llvm_unreachable("Unknown DWARF flavour");
282
82
  case 0:
283
82
    RI->mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
284
82
    break;
285
82
  }
286
82
  switch (EHFlavour) {
287
82
  default:
288
0
    llvm_unreachable("Unknown DWARF flavour");
289
82
  case 0:
290
82
    RI->mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
291
82
    break;
292
82
  }
293
82
  switch (DwarfFlavour) {
294
82
  default:
295
0
    llvm_unreachable("Unknown DWARF flavour");
296
82
  case 0:
297
82
    RI->mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
298
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    break;
299
82
  }
300
82
  switch (EHFlavour) {
301
82
  default:
302
0
    llvm_unreachable("Unknown DWARF flavour");
303
82
  case 0:
304
82
    RI->mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
305
82
    break;
306
82
  }
307
82
}
308
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} // end namespace llvm
310
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#endif // GET_REGINFO_MC_DESC
312
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
314
|*                                                                            *|
315
|* Register Information Header Fragment                                       *|
316
|*                                                                            *|
317
|* Automatically generated file, do not edit!                                 *|
318
|*                                                                            *|
319
\*===----------------------------------------------------------------------===*/
320
321
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#ifdef GET_REGINFO_HEADER
323
#undef GET_REGINFO_HEADER
324
325
#include "llvm/CodeGen/TargetRegisterInfo.h"
326
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namespace llvm {
328
329
class XCoreFrameLowering;
330
331
struct XCoreGenRegisterInfo : public TargetRegisterInfo {
332
  explicit XCoreGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
333
      unsigned PC = 0, unsigned HwMode = 0);
334
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
335
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
336
  unsigned getNumRegPressureSets() const override;
337
  const char *getRegPressureSetName(unsigned Idx) const override;
338
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
339
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
340
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
341
  ArrayRef<const char *> getRegMaskNames() const override;
342
  ArrayRef<const uint32_t *> getRegMasks() const override;
343
  /// Devirtualized TargetFrameLowering.
344
  static const XCoreFrameLowering *getFrameLowering(
345
      const MachineFunction &MF);
346
};
347
348
namespace XCore { // Register classes
349
  extern const TargetRegisterClass RRegsRegClass;
350
  extern const TargetRegisterClass GRRegsRegClass;
351
} // end namespace XCore
352
353
} // end namespace llvm
354
355
#endif // GET_REGINFO_HEADER
356
357
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
358
|*                                                                            *|
359
|* Target Register and Register Classes Information                           *|
360
|*                                                                            *|
361
|* Automatically generated file, do not edit!                                 *|
362
|*                                                                            *|
363
\*===----------------------------------------------------------------------===*/
364
365
366
#ifdef GET_REGINFO_TARGET_DESC
367
#undef GET_REGINFO_TARGET_DESC
368
369
namespace llvm {
370
371
extern const MCRegisterClass XCoreMCRegisterClasses[];
372
373
static const MVT::SimpleValueType VTLists[] = {
374
  /* 0 */ MVT::i32, MVT::Other,
375
};
376
377
static const char *const SubRegIndexNameTable[] = { "" };
378
379
380
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
381
  LaneBitmask::getAll(),
382
 };
383
384
385
386
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
387
  // Mode = 0 (Default)
388
  { 32, 32, 32, VTLists+0 },    // RRegs
389
  { 32, 32, 32, VTLists+0 },    // GRRegs
390
};
391
392
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
393
394
static const uint32_t RRegsSubClassMask[] = {
395
  0x00000003, 
396
};
397
398
static const uint32_t GRRegsSubClassMask[] = {
399
  0x00000002, 
400
};
401
402
static const uint16_t SuperRegIdxSeqs[] = {
403
  /* 0 */ 0,
404
};
405
406
static const TargetRegisterClass *const GRRegsSuperclasses[] = {
407
  &XCore::RRegsRegClass,
408
  nullptr
409
};
410
411
412
namespace XCore {   // Register class instances
413
  extern const TargetRegisterClass RRegsRegClass = {
414
    &XCoreMCRegisterClasses[RRegsRegClassID],
415
    RRegsSubClassMask,
416
    SuperRegIdxSeqs + 0,
417
    LaneBitmask(0x00000001),
418
    0,
419
    false, /* HasDisjunctSubRegs */
420
    false, /* CoveredBySubRegs */
421
    NullRegClasses,
422
    nullptr
423
  };
424
425
  extern const TargetRegisterClass GRRegsRegClass = {
426
    &XCoreMCRegisterClasses[GRRegsRegClassID],
427
    GRRegsSubClassMask,
428
    SuperRegIdxSeqs + 0,
429
    LaneBitmask(0x00000001),
430
    0,
431
    false, /* HasDisjunctSubRegs */
432
    false, /* CoveredBySubRegs */
433
    GRRegsSuperclasses,
434
    nullptr
435
  };
436
437
} // end namespace XCore
438
439
namespace {
440
  const TargetRegisterClass* const RegisterClasses[] = {
441
    &XCore::RRegsRegClass,
442
    &XCore::GRRegsRegClass,
443
  };
444
} // end anonymous namespace
445
446
static const TargetRegisterInfoDesc XCoreRegInfoDesc[] = { // Extra Descriptors
447
  { 0, false },
448
  { 0, false },
449
  { 0, false },
450
  { 0, false },
451
  { 0, false },
452
  { 0, true },
453
  { 0, true },
454
  { 0, true },
455
  { 0, true },
456
  { 0, true },
457
  { 0, true },
458
  { 0, true },
459
  { 0, true },
460
  { 0, true },
461
  { 0, true },
462
  { 0, true },
463
  { 0, true },
464
};
465
/// Get the weight in units of pressure for this register class.
466
const RegClassWeight &XCoreGenRegisterInfo::
467
37
getRegClassWeight(const TargetRegisterClass *RC) const {
468
37
  static const RegClassWeight RCWeightTable[] = {
469
37
    {0, 12},    // RRegs
470
37
    {1, 12},    // GRRegs
471
37
  };
472
37
  return RCWeightTable[RC->getID()];
473
37
}
474
475
/// Get the weight in units of pressure for this register unit.
476
unsigned XCoreGenRegisterInfo::
477
0
getRegUnitWeight(unsigned RegUnit) const {
478
0
  assert(RegUnit < 16 && "invalid register unit");
479
0
  // All register units have unit weight.
480
0
  return 1;
481
0
}
482
483
484
// Get the number of dimensions of register pressure.
485
531
unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
486
531
  return 1;
487
531
}
488
489
// Get the name of this register unit pressure set.
490
const char *XCoreGenRegisterInfo::
491
0
getRegPressureSetName(unsigned Idx) const {
492
0
  static const char *const PressureNameTable[] = {
493
0
    "GRRegs",
494
0
  };
495
0
  return PressureNameTable[Idx];
496
0
}
497
498
// Get the register unit pressure limit for this dimension.
499
// This limit must be adjusted dynamically for reserved registers.
500
unsigned XCoreGenRegisterInfo::
501
262
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
502
262
  static const uint8_t PressureLimitTable[] = {
503
262
    12,   // 0: GRRegs
504
262
  };
505
262
  return PressureLimitTable[Idx];
506
262
}
507
508
/// Table of pressure sets per register class or unit.
509
static const int RCSetsTable[] = {
510
  /* 0 */ 0, -1,
511
};
512
513
/// Get the dimensions of register pressure impacted by this register class.
514
/// Returns a -1 terminated array of pressure set IDs
515
const int* XCoreGenRegisterInfo::
516
32
getRegClassPressureSets(const TargetRegisterClass *RC) const {
517
32
  static const uint8_t RCSetStartTable[] = {
518
32
    1,0,};
519
32
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
520
32
}
521
522
/// Get the dimensions of register pressure impacted by this register unit.
523
/// Returns a -1 terminated array of pressure set IDs
524
const int* XCoreGenRegisterInfo::
525
0
getRegUnitPressureSets(unsigned RegUnit) const {
526
0
  assert(RegUnit < 16 && "invalid register unit");
527
0
  static const uint8_t RUSetStartTable[] = {
528
0
    1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
529
0
  return &RCSetsTable[RUSetStartTable[RegUnit]];
530
0
}
531
532
extern const MCRegisterDesc XCoreRegDesc[];
533
extern const MCPhysReg XCoreRegDiffLists[];
534
extern const LaneBitmask XCoreLaneMaskLists[];
535
extern const char XCoreRegStrings[];
536
extern const char XCoreRegClassStrings[];
537
extern const MCPhysReg XCoreRegUnitRoots[][2];
538
extern const uint16_t XCoreSubRegIdxLists[];
539
extern const MCRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRanges[];
540
extern const uint16_t XCoreRegEncodingTable[];
541
// XCore Dwarf<->LLVM register mappings.
542
extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
543
extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
544
545
extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
546
extern const unsigned XCoreEHFlavour0Dwarf2LSize;
547
548
extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
549
extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
550
551
extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
552
extern const unsigned XCoreEHFlavour0L2DwarfSize;
553
554
XCoreGenRegisterInfo::
555
XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
556
      unsigned PC, unsigned HwMode)
557
  : TargetRegisterInfo(XCoreRegInfoDesc, RegisterClasses, RegisterClasses+2,
558
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
559
80
             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
560
80
  InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
561
80
                     XCoreMCRegisterClasses, 2,
562
80
                     XCoreRegUnitRoots,
563
80
                     16,
564
80
                     XCoreRegDiffLists,
565
80
                     XCoreLaneMaskLists,
566
80
                     XCoreRegStrings,
567
80
                     XCoreRegClassStrings,
568
80
                     XCoreSubRegIdxLists,
569
80
                     1,
570
80
                     XCoreSubRegIdxRanges,
571
80
                     XCoreRegEncodingTable);
572
80
573
80
  switch (DwarfFlavour) {
574
80
  default:
575
0
    llvm_unreachable("Unknown DWARF flavour");
576
80
  case 0:
577
80
    mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
578
80
    break;
579
80
  }
580
80
  switch (EHFlavour) {
581
80
  default:
582
0
    llvm_unreachable("Unknown DWARF flavour");
583
80
  case 0:
584
80
    mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
585
80
    break;
586
80
  }
587
80
  switch (DwarfFlavour) {
588
80
  default:
589
0
    llvm_unreachable("Unknown DWARF flavour");
590
80
  case 0:
591
80
    mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
592
80
    break;
593
80
  }
594
80
  switch (EHFlavour) {
595
80
  default:
596
0
    llvm_unreachable("Unknown DWARF flavour");
597
80
  case 0:
598
80
    mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
599
80
    break;
600
80
  }
601
80
}
602
603
604
605
0
ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
606
0
  return None;
607
0
}
608
609
0
ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
610
0
  return None;
611
0
}
612
613
const XCoreFrameLowering *
614
2.84k
XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
615
2.84k
  return static_cast<const XCoreFrameLowering *>(
616
2.84k
      MF.getSubtarget().getFrameLowering());
617
2.84k
}
618
619
} // end namespace llvm
620
621
#endif // GET_REGINFO_TARGET_DESC
622