Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
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//===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating functions from LLVM IR into
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// Machine IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
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#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/KnownBits.h"
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#include <cassert>
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#include <utility>
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#include <vector>
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namespace llvm {
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class Argument;
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class BasicBlock;
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class BranchProbabilityInfo;
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class Function;
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class Instruction;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class MVT;
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class SelectionDAG;
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class TargetLowering;
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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///
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class FunctionLoweringInfo {
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public:
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  const Function *Fn;
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  MachineFunction *MF;
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  const TargetLowering *TLI;
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  MachineRegisterInfo *RegInfo;
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  BranchProbabilityInfo *BPI;
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  const LegacyDivergenceAnalysis *DA;
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  /// CanLowerReturn - true iff the function's return value can be lowered to
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  /// registers.
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  bool CanLowerReturn;
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  /// True if part of the CSRs will be handled via explicit copies.
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  bool SplitCSR;
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  /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
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  /// allocated to hold a pointer to the hidden sret parameter.
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  unsigned DemoteRegister;
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  /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
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  DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
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  /// ValueMap - Since we emit code for the function a basic block at a time,
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  /// we must remember which virtual registers hold the values for
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  /// cross-basic-block values.
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  DenseMap<const Value *, unsigned> ValueMap;
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  /// VirtReg2Value map is needed by the Divergence Analysis driven
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  /// instruction selection. It is reverted ValueMap. It is computed
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  /// in lazy style - on demand. It is used to get the Value corresponding
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  /// to the live in virtual register and is called from the
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  /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
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  DenseMap<unsigned, const Value*> VirtReg2Value;
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  /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
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  /// to get the Value corresponding to the live-in virtual register.
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  const Value * getValueFromVirtualReg(unsigned Vreg);
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  /// Track virtual registers created for exception pointers.
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  DenseMap<const Value *, unsigned> CatchPadExceptionPointers;
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  /// Keep track of frame indices allocated for statepoints as they could be
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  /// used across basic block boundaries.  This struct is more complex than a
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  /// simple map because the stateopint lowering code de-duplicates gc pointers
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  /// based on their SDValue (so %p and (bitcast %p to T) will get the same
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  /// slot), and we track that here.
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  struct StatepointSpillMap {
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    using SlotMapTy = DenseMap<const Value *, Optional<int>>;
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    /// Maps uniqued llvm IR values to the slots they were spilled in.  If a
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    /// value is mapped to None it means we visited the value but didn't spill
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    /// it (because it was a constant, for instance).
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    SlotMapTy SlotMap;
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    /// Maps llvm IR values to the values they were de-duplicated to.
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    DenseMap<const Value *, const Value *> DuplicateMap;
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    SlotMapTy::const_iterator find(const Value *V) const {
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      auto DuplIt = DuplicateMap.find(V);
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      if (DuplIt != DuplicateMap.end())
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        V = DuplIt->second;
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      return SlotMap.find(V);
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    }
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    SlotMapTy::const_iterator end() const { return SlotMap.end(); }
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  };
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  /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
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  /// instances.
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  DenseMap<const Instruction *, StatepointSpillMap> StatepointSpillMaps;
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  /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
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  /// the entry block.  This allows the allocas to be efficiently referenced
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  /// anywhere in the function.
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  DenseMap<const AllocaInst*, int> StaticAllocaMap;
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  /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
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  DenseMap<const Argument*, int> ByValArgFrameIndexMap;
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  /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
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  /// function arguments that are inserted after scheduling is completed.
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  SmallVector<MachineInstr*, 8> ArgDbgValues;
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  /// Bitvector with a bit set if corresponding argument is described in
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  /// ArgDbgValues. Using arg numbers according to Argument numbering.
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  BitVector DescribedArgs;
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  /// RegFixups - Registers which need to be replaced after isel is done.
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  DenseMap<unsigned, unsigned> RegFixups;
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  DenseSet<unsigned> RegsWithFixups;
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  /// StatepointStackSlots - A list of temporary stack slots (frame indices)
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  /// used to spill values at a statepoint.  We store them here to enable
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  /// reuse of the same stack slots across different statepoints in different
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  /// basic blocks.
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  SmallVector<unsigned, 50> StatepointStackSlots;
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  /// MBB - The current block.
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  MachineBasicBlock *MBB;
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  /// MBB - The current insert position inside the current block.
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  MachineBasicBlock::iterator InsertPt;
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  struct LiveOutInfo {
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    unsigned NumSignBits : 31;
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    unsigned IsValid : 1;
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    KnownBits Known = 1;
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    LiveOutInfo() : NumSignBits(0), IsValid(true) {}
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  };
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  /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
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  /// for a value.
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  DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
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  /// VisitedBBs - The set of basic blocks visited thus far by instruction
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  /// selection.
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  SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
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  /// PHINodesToUpdate - A list of phi instructions whose operand list will
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  /// be updated after processing the current basic block.
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  /// TODO: This isn't per-function state, it's per-basic-block state. But
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  /// there's no other convenient place for it to live right now.
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  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
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  unsigned OrigNumPHINodesToUpdate;
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  /// If the current MBB is a landing pad, the exception pointer and exception
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  /// selector registers are copied into these virtual registers by
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  /// SelectionDAGISel::PrepareEHLandingPad().
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  unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
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  /// set - Initialize this FunctionLoweringInfo with the given Function
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  /// and its associated MachineFunction.
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  ///
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  void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
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  /// clear - Clear out all the function-specific state. This returns this
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  /// FunctionLoweringInfo to an empty state, ready to be used for a
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  /// different function.
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  void clear();
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  /// isExportedInst - Return true if the specified value is an instruction
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  /// exported from its block.
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  bool isExportedInst(const Value *V) {
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    return ValueMap.count(V);
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  }
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  unsigned CreateReg(MVT VT, bool isDivergent = false);
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  unsigned CreateRegs(const Value *V);
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  unsigned CreateRegs(Type *Ty, bool isDivergent = false);
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  unsigned InitializeRegForValue(const Value *V) {
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    // Tokens never live in vregs.
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    if (V->getType()->isTokenTy())
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      return 0;
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    unsigned &R = ValueMap[V];
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    assert(R == 0 && "Already initialized this value register!");
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    assert(VirtReg2Value.empty());
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    return R = CreateRegs(V);
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  }
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  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
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  /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
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  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
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    if (!LiveOutRegInfo.inBounds(Reg))
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      return nullptr;
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    const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
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    if (!LOI->IsValid)
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      return nullptr;
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    return LOI;
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  }
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  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
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  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
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  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
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  /// the larger bit width by zero extension. The bit width must be no smaller
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  /// than the LiveOutInfo's existing bit width.
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  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
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  /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
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  void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
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                         const KnownBits &Known) {
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    // Only install this information if it tells us something.
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    if (NumSignBits == 1 && 
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)
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      return;
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    LiveOutRegInfo.grow(Reg);
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    LiveOutInfo &LOI = LiveOutRegInfo[Reg];
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    LOI.NumSignBits = NumSignBits;
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    LOI.Known.One = Known.One;
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    LOI.Known.Zero = Known.Zero;
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  }
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  /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
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  /// register based on the LiveOutInfo of its operands.
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  void ComputePHILiveOutRegInfo(const PHINode*);
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  /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
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  /// called when a block is visited before all of its predecessors.
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  void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
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    // PHIs with no uses have no ValueMap entry.
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    DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
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    if (It == ValueMap.end())
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      return;
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    unsigned Reg = It->second;
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    if (Reg == 0)
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      return;
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    LiveOutRegInfo.grow(Reg);
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    LiveOutRegInfo[Reg].IsValid = false;
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  }
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  /// setArgumentFrameIndex - Record frame index for the byval
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  /// argument.
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  void setArgumentFrameIndex(const Argument *A, int FI);
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  /// getArgumentFrameIndex - Get frame index for the byval argument.
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  int getArgumentFrameIndex(const Argument *A);
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  unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
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                                           const TargetRegisterClass *RC);
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private:
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  void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
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  /// LiveOutRegInfo - Information about live out vregs.
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  IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H