/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===- llvm/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp --------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | #include "DbgValueHistoryCalculator.h" |
11 | | #include "llvm/ADT/BitVector.h" |
12 | | #include "llvm/ADT/STLExtras.h" |
13 | | #include "llvm/ADT/SmallVector.h" |
14 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
15 | | #include "llvm/CodeGen/MachineFunction.h" |
16 | | #include "llvm/CodeGen/MachineInstr.h" |
17 | | #include "llvm/CodeGen/MachineOperand.h" |
18 | | #include "llvm/CodeGen/TargetLowering.h" |
19 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
20 | | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
21 | | #include "llvm/IR/DebugInfoMetadata.h" |
22 | | #include "llvm/IR/DebugLoc.h" |
23 | | #include "llvm/MC/MCRegisterInfo.h" |
24 | | #include "llvm/Support/Debug.h" |
25 | | #include "llvm/Support/raw_ostream.h" |
26 | | #include <cassert> |
27 | | #include <map> |
28 | | #include <utility> |
29 | | |
30 | | using namespace llvm; |
31 | | |
32 | | #define DEBUG_TYPE "dwarfdebug" |
33 | | |
34 | | // If @MI is a DBG_VALUE with debug value described by a |
35 | | // defined register, returns the number of this register. |
36 | | // In the other case, returns 0. |
37 | 1.90k | static unsigned isDescribedByReg(const MachineInstr &MI) { |
38 | 1.90k | assert(MI.isDebugValue()); |
39 | 1.90k | assert(MI.getNumOperands() == 4); |
40 | 1.90k | // If location of variable is described using a register (directly or |
41 | 1.90k | // indirectly), this register is always a first operand. |
42 | 1.90k | return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg()1.76k : 0143 ; |
43 | 1.90k | } |
44 | | |
45 | | void DbgValueHistoryMap::startInstrRange(InlinedVariable Var, |
46 | 1.49k | const MachineInstr &MI) { |
47 | 1.49k | // Instruction range should start with a DBG_VALUE instruction for the |
48 | 1.49k | // variable. |
49 | 1.49k | assert(MI.isDebugValue() && "not a DBG_VALUE"); |
50 | 1.49k | auto &Ranges = VarInstrRanges[Var]; |
51 | 1.49k | if (!Ranges.empty() && Ranges.back().second == nullptr905 && |
52 | 1.49k | Ranges.back().first->isIdenticalTo(MI)413 ) { |
53 | 226 | LLVM_DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n" |
54 | 226 | << "\t" << Ranges.back().first << "\t" << MI << "\n"); |
55 | 226 | return; |
56 | 226 | } |
57 | 1.26k | Ranges.push_back(std::make_pair(&MI, nullptr)); |
58 | 1.26k | } |
59 | | |
60 | | void DbgValueHistoryMap::endInstrRange(InlinedVariable Var, |
61 | 817 | const MachineInstr &MI) { |
62 | 817 | auto &Ranges = VarInstrRanges[Var]; |
63 | 817 | // Verify that the current instruction range is not yet closed. |
64 | 817 | assert(!Ranges.empty() && Ranges.back().second == nullptr); |
65 | 817 | // For now, instruction ranges are not allowed to cross basic block |
66 | 817 | // boundaries. |
67 | 817 | assert(Ranges.back().first->getParent() == MI.getParent()); |
68 | 817 | Ranges.back().second = &MI; |
69 | 817 | } |
70 | | |
71 | 1.49k | unsigned DbgValueHistoryMap::getRegisterForVar(InlinedVariable Var) const { |
72 | 1.49k | const auto &I = VarInstrRanges.find(Var); |
73 | 1.49k | if (I == VarInstrRanges.end()) |
74 | 586 | return 0; |
75 | 905 | const auto &Ranges = I->second; |
76 | 905 | if (Ranges.empty() || Ranges.back().second != nullptr) |
77 | 492 | return 0; |
78 | 413 | return isDescribedByReg(*Ranges.back().first); |
79 | 413 | } |
80 | | |
81 | | namespace { |
82 | | |
83 | | // Maps physreg numbers to the variables they describe. |
84 | | using InlinedVariable = DbgValueHistoryMap::InlinedVariable; |
85 | | using RegDescribedVarsMap = std::map<unsigned, SmallVector<InlinedVariable, 1>>; |
86 | | |
87 | | } // end anonymous namespace |
88 | | |
89 | | // Claim that @Var is not described by @RegNo anymore. |
90 | | static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, |
91 | 357 | InlinedVariable Var) { |
92 | 357 | const auto &I = RegVars.find(RegNo); |
93 | 357 | assert(RegNo != 0U && I != RegVars.end()); |
94 | 357 | auto &VarSet = I->second; |
95 | 357 | const auto &VarPos = llvm::find(VarSet, Var); |
96 | 357 | assert(VarPos != VarSet.end()); |
97 | 357 | VarSet.erase(VarPos); |
98 | 357 | // Don't keep empty sets in a map to keep it as small as possible. |
99 | 357 | if (VarSet.empty()) |
100 | 309 | RegVars.erase(I); |
101 | 357 | } |
102 | | |
103 | | // Claim that @Var is now described by @RegNo. |
104 | | static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, |
105 | 1.35k | InlinedVariable Var) { |
106 | 1.35k | assert(RegNo != 0U); |
107 | 1.35k | auto &VarSet = RegVars[RegNo]; |
108 | 1.35k | assert(!is_contained(VarSet, Var)); |
109 | 1.35k | VarSet.push_back(Var); |
110 | 1.35k | } |
111 | | |
112 | | // Terminate the location range for variables described by register at |
113 | | // @I by inserting @ClobberingInstr to their history. |
114 | | static void clobberRegisterUses(RegDescribedVarsMap &RegVars, |
115 | | RegDescribedVarsMap::iterator I, |
116 | | DbgValueHistoryMap &HistMap, |
117 | 759 | const MachineInstr &ClobberingInstr) { |
118 | 759 | // Iterate over all variables described by this register and add this |
119 | 759 | // instruction to their history, clobbering it. |
120 | 759 | for (const auto &Var : I->second) |
121 | 817 | HistMap.endInstrRange(Var, ClobberingInstr); |
122 | 759 | RegVars.erase(I); |
123 | 759 | } |
124 | | |
125 | | // Terminate the location range for variables described by register |
126 | | // @RegNo by inserting @ClobberingInstr to their history. |
127 | | static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo, |
128 | | DbgValueHistoryMap &HistMap, |
129 | 82.0M | const MachineInstr &ClobberingInstr) { |
130 | 82.0M | const auto &I = RegVars.find(RegNo); |
131 | 82.0M | if (I == RegVars.end()) |
132 | 82.0M | return; |
133 | 303 | clobberRegisterUses(RegVars, I, HistMap, ClobberingInstr); |
134 | 303 | } |
135 | | |
136 | | // Returns the first instruction in @MBB which corresponds to |
137 | | // the function epilogue, or nullptr if @MBB doesn't contain an epilogue. |
138 | 396k | static const MachineInstr *getFirstEpilogueInst(const MachineBasicBlock &MBB) { |
139 | 396k | auto LastMI = MBB.getLastNonDebugInstr(); |
140 | 396k | if (LastMI == MBB.end() || !LastMI->isReturn()396k ) |
141 | 351k | return nullptr; |
142 | 44.6k | // Assume that epilogue starts with instruction having the same debug location |
143 | 44.6k | // as the return instruction. |
144 | 44.6k | DebugLoc LastLoc = LastMI->getDebugLoc(); |
145 | 44.6k | auto Res = LastMI; |
146 | 44.6k | for (MachineBasicBlock::const_reverse_iterator I = LastMI.getReverse(), |
147 | 44.6k | E = MBB.rend(); |
148 | 253k | I != E; ++I208k ) { |
149 | 232k | if (I->getDebugLoc() != LastLoc) |
150 | 24.4k | return &*Res; |
151 | 208k | Res = &*I; |
152 | 208k | } |
153 | 44.6k | // If all instructions have the same debug location, assume whole MBB is |
154 | 44.6k | // an epilogue. |
155 | 44.6k | return &*MBB.begin()20.1k ; |
156 | 44.6k | } |
157 | | |
158 | | // Collect registers that are modified in the function body (their |
159 | | // contents is changed outside of the prologue and epilogue). |
160 | | static void collectChangingRegs(const MachineFunction *MF, |
161 | | const TargetRegisterInfo *TRI, |
162 | 36.1k | BitVector &Regs) { |
163 | 396k | for (const auto &MBB : *MF) { |
164 | 396k | auto FirstEpilogueInst = getFirstEpilogueInst(MBB); |
165 | 396k | |
166 | 2.69M | for (const auto &MI : MBB) { |
167 | 2.69M | // Avoid looking at prologue or epilogue instructions. |
168 | 2.69M | if (&MI == FirstEpilogueInst) |
169 | 44.6k | break; |
170 | 2.64M | if (MI.getFlag(MachineInstr::FrameSetup)) |
171 | 218k | continue; |
172 | 2.43M | |
173 | 2.43M | // Look for register defs and register masks. Register masks are |
174 | 2.43M | // typically on calls and they clobber everything not in the mask. |
175 | 10.4M | for (const MachineOperand &MO : MI.operands())2.43M { |
176 | 10.4M | // Skip virtual registers since they are handled by the parent. |
177 | 10.4M | if (MO.isReg() && MO.isDef()7.17M && MO.getReg()2.50M && |
178 | 10.4M | !TRI->isVirtualRegister(MO.getReg())2.50M ) { |
179 | 17.9M | for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); |
180 | 15.4M | ++AI) |
181 | 15.4M | Regs.set(*AI); |
182 | 7.98M | } else if (MO.isRegMask()) { |
183 | 219k | Regs.setBitsNotInMask(MO.getRegMask()); |
184 | 219k | } |
185 | 10.4M | } |
186 | 2.43M | } |
187 | 396k | } |
188 | 36.1k | } |
189 | | |
190 | | void llvm::calculateDbgValueHistory(const MachineFunction *MF, |
191 | | const TargetRegisterInfo *TRI, |
192 | 36.1k | DbgValueHistoryMap &Result) { |
193 | 36.1k | BitVector ChangingRegs(TRI->getNumRegs()); |
194 | 36.1k | collectChangingRegs(MF, TRI, ChangingRegs); |
195 | 36.1k | |
196 | 36.1k | const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); |
197 | 36.1k | unsigned SP = TLI->getStackPointerRegisterToSaveRestore(); |
198 | 36.1k | RegDescribedVarsMap RegVars; |
199 | 396k | for (const auto &MBB : *MF) { |
200 | 2.85M | for (const auto &MI : MBB) { |
201 | 2.85M | if (!MI.isDebugInstr()) { |
202 | 2.85M | // Not a DBG_VALUE instruction. It may clobber registers which describe |
203 | 2.85M | // some variables. |
204 | 11.7M | for (const MachineOperand &MO : MI.operands()) { |
205 | 11.7M | if (MO.isReg() && MO.isDef()8.23M && MO.getReg()2.98M ) { |
206 | 2.98M | // Ignore call instructions that claim to clobber SP. The AArch64 |
207 | 2.98M | // backend does this for aggregate function arguments. |
208 | 2.98M | if (MI.isCall() && MO.getReg() == SP554k ) |
209 | 221k | continue; |
210 | 2.76M | // If this is a virtual register, only clobber it since it doesn't |
211 | 2.76M | // have aliases. |
212 | 2.76M | if (TRI->isVirtualRegister(MO.getReg())) |
213 | 26 | clobberRegisterUses(RegVars, MO.getReg(), Result, MI); |
214 | 2.76M | // If this is a register def operand, it may end a debug value |
215 | 2.76M | // range. |
216 | 2.76M | else { |
217 | 20.3M | for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); |
218 | 17.6M | ++AI) |
219 | 17.6M | if (ChangingRegs.test(*AI)) |
220 | 16.8M | clobberRegisterUses(RegVars, *AI, Result, MI); |
221 | 2.76M | } |
222 | 8.81M | } else if (MO.isRegMask()) { |
223 | 229k | // If this is a register mask operand, clobber all debug values in |
224 | 229k | // non-CSRs. |
225 | 70.3M | for (unsigned I : ChangingRegs.set_bits()) { |
226 | 70.3M | // Don't consider SP to be clobbered by register masks. |
227 | 70.3M | if (unsigned(I) != SP && TRI->isPhysicalRegister(I)70.0M && |
228 | 70.3M | MO.clobbersPhysReg(I)69.8M ) { |
229 | 65.2M | clobberRegisterUses(RegVars, I, Result, MI); |
230 | 65.2M | } |
231 | 70.3M | } |
232 | 229k | } |
233 | 11.7M | } |
234 | 2.85M | continue; |
235 | 2.85M | } |
236 | 1.49k | |
237 | 1.49k | // Skip DBG_LABEL instructions. |
238 | 1.49k | if (MI.isDebugLabel()) |
239 | 0 | continue; |
240 | 1.49k | |
241 | 1.49k | assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!"); |
242 | 1.49k | // Use the base variable (without any DW_OP_piece expressions) |
243 | 1.49k | // as index into History. The full variables including the |
244 | 1.49k | // piece expressions are attached to the MI. |
245 | 1.49k | const DILocalVariable *RawVar = MI.getDebugVariable(); |
246 | 1.49k | assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) && |
247 | 1.49k | "Expected inlined-at fields to agree"); |
248 | 1.49k | InlinedVariable Var(RawVar, MI.getDebugLoc()->getInlinedAt()); |
249 | 1.49k | |
250 | 1.49k | if (unsigned PrevReg = Result.getRegisterForVar(Var)) |
251 | 357 | dropRegDescribedVar(RegVars, PrevReg, Var); |
252 | 1.49k | |
253 | 1.49k | Result.startInstrRange(Var, MI); |
254 | 1.49k | |
255 | 1.49k | if (unsigned NewReg = isDescribedByReg(MI)) |
256 | 1.35k | addRegDescribedVar(RegVars, NewReg, Var); |
257 | 1.49k | } |
258 | 396k | |
259 | 396k | // Make sure locations for register-described variables are valid only |
260 | 396k | // until the end of the basic block (unless it's the last basic block, in |
261 | 396k | // which case let their liveness run off to the end of the function). |
262 | 396k | if (!MBB.empty() && &MBB != &MF->back()396k ) { |
263 | 360k | for (auto I = RegVars.begin(), E = RegVars.end(); I != E;) { |
264 | 537 | auto CurElem = I++; // CurElem can be erased below. |
265 | 537 | if (TRI->isVirtualRegister(CurElem->first) || |
266 | 537 | ChangingRegs.test(CurElem->first)533 ) |
267 | 456 | clobberRegisterUses(RegVars, CurElem, Result, MBB.back()); |
268 | 537 | } |
269 | 360k | } |
270 | 396k | } |
271 | 36.1k | } |
272 | | |
273 | | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
274 | | LLVM_DUMP_METHOD void DbgValueHistoryMap::dump() const { |
275 | | dbgs() << "DbgValueHistoryMap:\n"; |
276 | | for (const auto &VarRangePair : *this) { |
277 | | const InlinedVariable &Var = VarRangePair.first; |
278 | | const InstrRanges &Ranges = VarRangePair.second; |
279 | | |
280 | | const DILocalVariable *LocalVar = Var.first; |
281 | | const DILocation *Location = Var.second; |
282 | | |
283 | | dbgs() << " - " << LocalVar->getName() << " at "; |
284 | | |
285 | | if (Location) |
286 | | dbgs() << Location->getFilename() << ":" << Location->getLine() << ":" |
287 | | << Location->getColumn(); |
288 | | else |
289 | | dbgs() << "<unknown location>"; |
290 | | |
291 | | dbgs() << " --\n"; |
292 | | |
293 | | for (const InstrRange &Range : Ranges) { |
294 | | dbgs() << " Begin: " << *Range.first; |
295 | | if (Range.second) |
296 | | dbgs() << " End : " << *Range.second; |
297 | | dbgs() << "\n"; |
298 | | } |
299 | | } |
300 | | } |
301 | | #endif |