Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
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//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the InstructionSelector class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
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    : Renderers(MaxRenderers), MIs() {}
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InstructionSelector::InstructionSelector() = default;
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bool InstructionSelector::constrainOperandRegToRegClass(
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    MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
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    const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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    const RegisterBankInfo &RBI) const {
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  MachineBasicBlock &MBB = *I.getParent();
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  MachineFunction &MF = *MBB.getParent();
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  MachineRegisterInfo &MRI = MF.getRegInfo();
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  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC,
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                                  I.getOperand(OpIdx), OpIdx);
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}
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bool InstructionSelector::isOperandImmEqual(
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    const MachineOperand &MO, int64_t Value,
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    const MachineRegisterInfo &MRI) const {
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  if (MO.isReg() && MO.getReg())
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    if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
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      return VRegVal->Value == Value;
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  return false;
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}
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bool InstructionSelector::isBaseWithConstantOffset(
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    const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
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  if (!Root.isReg())
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    return false;
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  MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
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  if (RootI->getOpcode() != TargetOpcode::G_GEP)
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    return false;
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  MachineOperand &RHS = RootI->getOperand(2);
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  MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
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  if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
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    return false;
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  return true;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
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                                                MachineInstr &IntoMI) const {
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  // Immediate neighbours are already folded.
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  if (MI.getParent() == IntoMI.getParent() &&
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std::next(MI.getIterator()) == IntoMI.getIterator()34.4k
)
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    return true;
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  return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
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         !MI.hasUnmodeledSideEffects() && empty(MI.implicit_operands());
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}