/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | /// \file |
10 | | /// This file implements the InstructionSelector class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" |
15 | | #include "llvm/CodeGen/GlobalISel/Utils.h" |
16 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
17 | | #include "llvm/CodeGen/MachineFunction.h" |
18 | | #include "llvm/CodeGen/MachineInstr.h" |
19 | | #include "llvm/CodeGen/MachineOperand.h" |
20 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
21 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
22 | | #include "llvm/MC/MCInstrDesc.h" |
23 | | #include "llvm/Support/Debug.h" |
24 | | #include "llvm/Support/raw_ostream.h" |
25 | | #include <cassert> |
26 | | |
27 | | #define DEBUG_TYPE "instructionselector" |
28 | | |
29 | | using namespace llvm; |
30 | | |
31 | | InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers) |
32 | 46.7k | : Renderers(MaxRenderers), MIs() {} |
33 | | |
34 | 46.7k | InstructionSelector::InstructionSelector() = default; |
35 | | |
36 | | bool InstructionSelector::constrainOperandRegToRegClass( |
37 | | MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, |
38 | | const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, |
39 | 188k | const RegisterBankInfo &RBI) const { |
40 | 188k | MachineBasicBlock &MBB = *I.getParent(); |
41 | 188k | MachineFunction &MF = *MBB.getParent(); |
42 | 188k | MachineRegisterInfo &MRI = MF.getRegInfo(); |
43 | 188k | |
44 | 188k | return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, |
45 | 188k | I.getOperand(OpIdx), OpIdx); |
46 | 188k | } |
47 | | |
48 | | bool InstructionSelector::isOperandImmEqual( |
49 | | const MachineOperand &MO, int64_t Value, |
50 | 559k | const MachineRegisterInfo &MRI) const { |
51 | 559k | if (MO.isReg() && MO.getReg()) |
52 | 559k | if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI)) |
53 | 107k | return VRegVal->Value == Value; |
54 | 451k | return false; |
55 | 451k | } |
56 | | |
57 | | bool InstructionSelector::isBaseWithConstantOffset( |
58 | 1.70M | const MachineOperand &Root, const MachineRegisterInfo &MRI) const { |
59 | 1.70M | if (!Root.isReg()) |
60 | 0 | return false; |
61 | 1.70M | |
62 | 1.70M | MachineInstr *RootI = MRI.getVRegDef(Root.getReg()); |
63 | 1.70M | if (RootI->getOpcode() != TargetOpcode::G_GEP) |
64 | 531k | return false; |
65 | 1.17M | |
66 | 1.17M | MachineOperand &RHS = RootI->getOperand(2); |
67 | 1.17M | MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg()); |
68 | 1.17M | if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT) |
69 | 131k | return false; |
70 | 1.04M | |
71 | 1.04M | return true; |
72 | 1.04M | } |
73 | | |
74 | | bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI, |
75 | 73.3k | MachineInstr &IntoMI) const { |
76 | 73.3k | // Immediate neighbours are already folded. |
77 | 73.3k | if (MI.getParent() == IntoMI.getParent() && |
78 | 73.3k | std::next(MI.getIterator()) == IntoMI.getIterator()34.4k ) |
79 | 18.0k | return true; |
80 | 55.3k | |
81 | 55.3k | return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() && |
82 | 55.3k | !MI.hasUnmodeledSideEffects() && empty(MI.implicit_operands()); |
83 | 55.3k | } |