Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/GlobalISel/Utils.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
/// \file This file implements the utility functions used by the GlobalISel
9
/// pipeline.
10
//===----------------------------------------------------------------------===//
11
12
#include "llvm/CodeGen/GlobalISel/Utils.h"
13
#include "llvm/ADT/APFloat.h"
14
#include "llvm/ADT/Twine.h"
15
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
16
#include "llvm/CodeGen/MachineInstr.h"
17
#include "llvm/CodeGen/MachineInstrBuilder.h"
18
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
19
#include "llvm/CodeGen/MachineRegisterInfo.h"
20
#include "llvm/CodeGen/StackProtector.h"
21
#include "llvm/CodeGen/TargetInstrInfo.h"
22
#include "llvm/CodeGen/TargetPassConfig.h"
23
#include "llvm/CodeGen/TargetRegisterInfo.h"
24
#include "llvm/IR/Constants.h"
25
26
#define DEBUG_TYPE "globalisel-utils"
27
28
using namespace llvm;
29
30
unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
31
                                   const TargetInstrInfo &TII,
32
                                   const RegisterBankInfo &RBI, unsigned Reg,
33
10.1M
                                   const TargetRegisterClass &RegClass) {
34
10.1M
  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
35
24
    return MRI.createVirtualRegister(&RegClass);
36
10.1M
37
10.1M
  return Reg;
38
10.1M
}
39
40
unsigned llvm::constrainOperandRegClass(
41
    const MachineFunction &MF, const TargetRegisterInfo &TRI,
42
    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
43
    const RegisterBankInfo &RBI, MachineInstr &InsertPt,
44
    const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
45
10.1M
    unsigned OpIdx) {
46
10.1M
  unsigned Reg = RegMO.getReg();
47
10.1M
  // Assume physical registers are properly constrained.
48
10.1M
  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
49
10.1M
         "PhysReg not implemented");
50
10.1M
51
10.1M
  unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
52
10.1M
  // If we created a new virtual register because the class is not compatible
53
10.1M
  // then create a copy between the new and the old register.
54
10.1M
  if (ConstrainedReg != Reg) {
55
24
    MachineBasicBlock::iterator InsertIt(&InsertPt);
56
24
    MachineBasicBlock &MBB = *InsertPt.getParent();
57
24
    if (RegMO.isUse()) {
58
24
      BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
59
24
              TII.get(TargetOpcode::COPY), ConstrainedReg)
60
24
          .addReg(Reg);
61
24
    } else {
62
0
      assert(RegMO.isDef() && "Must be a definition");
63
0
      BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
64
0
              TII.get(TargetOpcode::COPY), Reg)
65
0
          .addReg(ConstrainedReg);
66
0
    }
67
24
  }
68
10.1M
  return ConstrainedReg;
69
10.1M
}
70
71
unsigned llvm::constrainOperandRegClass(
72
    const MachineFunction &MF, const TargetRegisterInfo &TRI,
73
    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
74
    const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
75
10.1M
    const MachineOperand &RegMO, unsigned OpIdx) {
76
10.1M
  unsigned Reg = RegMO.getReg();
77
10.1M
  // Assume physical registers are properly constrained.
78
10.1M
  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
79
10.1M
         "PhysReg not implemented");
80
10.1M
81
10.1M
  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
82
10.1M
  // Some of the target independent instructions, like COPY, may not impose any
83
10.1M
  // register class constraints on some of their operands: If it's a use, we can
84
10.1M
  // skip constraining as the instruction defining the register would constrain
85
10.1M
  // it.
86
10.1M
87
10.1M
  // We can't constrain unallocatable register classes, because we can't create
88
10.1M
  // virtual registers for these classes, so we need to let targets handled this
89
10.1M
  // case.
90
10.1M
  if (RegClass && 
!RegClass->isAllocatable()9.96M
)
91
1.08k
    RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
92
10.1M
93
10.1M
  if (!RegClass) {
94
161k
    assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
95
161k
           "Register class constraint is required unless either the "
96
161k
           "instruction is target independent or the operand is a use");
97
161k
    // FIXME: Just bailing out like this here could be not enough, unless we
98
161k
    // expect the users of this function to do the right thing for PHIs and
99
161k
    // COPY:
100
161k
    //   v1 = COPY v0
101
161k
    //   v2 = COPY v1
102
161k
    // v1 here may end up not being constrained at all. Please notice that to
103
161k
    // reproduce the issue we likely need a destination pattern of a selection
104
161k
    // rule producing such extra copies, not just an input GMIR with them as
105
161k
    // every existing target using selectImpl handles copies before calling it
106
161k
    // and they never reach this function.
107
161k
    return Reg;
108
161k
  }
109
9.96M
  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
110
9.96M
                                  RegMO, OpIdx);
111
9.96M
}
112
113
bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
114
                                            const TargetInstrInfo &TII,
115
                                            const TargetRegisterInfo &TRI,
116
5.91M
                                            const RegisterBankInfo &RBI) {
117
5.91M
  assert(!isPreISelGenericOpcode(I.getOpcode()) &&
118
5.91M
         "A selected instruction is expected");
119
5.91M
  MachineBasicBlock &MBB = *I.getParent();
120
5.91M
  MachineFunction &MF = *MBB.getParent();
121
5.91M
  MachineRegisterInfo &MRI = MF.getRegInfo();
122
5.91M
123
22.7M
  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; 
++OpI16.8M
) {
124
16.8M
    MachineOperand &MO = I.getOperand(OpI);
125
16.8M
126
16.8M
    // There's nothing to be done on non-register operands.
127
16.8M
    if (!MO.isReg())
128
5.81M
      continue;
129
11.0M
130
11.0M
    LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
131
11.0M
    assert(MO.isReg() && "Unsupported non-reg operand");
132
11.0M
133
11.0M
    unsigned Reg = MO.getReg();
134
11.0M
    // Physical registers don't need to be constrained.
135
11.0M
    if (TRI.isPhysicalRegister(Reg))
136
951k
      continue;
137
10.0M
138
10.0M
    // Register operands with a value of 0 (e.g. predicate operands) don't need
139
10.0M
    // to be constrained.
140
10.0M
    if (Reg == 0)
141
2.44k
      continue;
142
10.0M
143
10.0M
    // If the operand is a vreg, we should constrain its regclass, and only
144
10.0M
    // insert COPYs if that's impossible.
145
10.0M
    // constrainOperandRegClass does that for us.
146
10.0M
    MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
147
10.0M
                                       MO, OpI));
148
10.0M
149
10.0M
    // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
150
10.0M
    // done.
151
10.0M
    if (MO.isUse()) {
152
6.02M
      int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
153
6.02M
      if (DefIdx != -1 && 
!I.isRegTiedToUseOperand(DefIdx)89.2k
)
154
170
        I.tieOperands(DefIdx, OpI);
155
6.02M
    }
156
10.0M
  }
157
5.91M
  return true;
158
5.91M
}
159
160
bool llvm::isTriviallyDead(const MachineInstr &MI,
161
73.8M
                           const MachineRegisterInfo &MRI) {
162
73.8M
  // If we can move an instruction, we can remove it.  Otherwise, it has
163
73.8M
  // a side-effect of some sort.
164
73.8M
  bool SawStore = false;
165
73.8M
  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && 
!MI.isPHI()22.2M
)
166
20.3M
    return false;
167
53.5M
168
53.5M
  // Instructions without side-effects are dead iff they only define dead vregs.
169
59.4M
  
for (auto &MO : MI.operands())53.5M
{
170
59.4M
    if (!MO.isReg() || 
!MO.isDef()57.6M
)
171
5.93M
      continue;
172
53.4M
173
53.4M
    unsigned Reg = MO.getReg();
174
53.4M
    if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
175
53.4M
        
!MRI.use_nodbg_empty(Reg)45.3M
)
176
49.8M
      return false;
177
53.4M
  }
178
53.5M
  
return true3.69M
;
179
53.5M
}
180
181
void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
182
                              MachineOptimizationRemarkEmitter &MORE,
183
16.3k
                              MachineOptimizationRemarkMissed &R) {
184
16.3k
  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
185
16.3k
186
16.3k
  // Print the function name explicitly if we don't have a debug location (which
187
16.3k
  // makes the diagnostic less useful) or if we're going to emit a raw error.
188
16.3k
  if (!R.getLocation().isValid() || 
TPC.isGlobalISelAbortEnabled()0
)
189
16.3k
    R << (" (in function: " + MF.getName() + ")").str();
190
16.3k
191
16.3k
  if (TPC.isGlobalISelAbortEnabled())
192
6
    report_fatal_error(R.getMsg());
193
16.3k
  else
194
16.3k
    MORE.emit(R);
195
16.3k
}
196
197
void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
198
                              MachineOptimizationRemarkEmitter &MORE,
199
                              const char *PassName, StringRef Msg,
200
16.3k
                              const MachineInstr &MI) {
201
16.3k
  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
202
16.3k
                                    MI.getDebugLoc(), MI.getParent());
203
16.3k
  R << Msg;
204
16.3k
  // Printing MI is expensive;  only do it if expensive remarks are enabled.
205
16.3k
  if (TPC.isGlobalISelAbortEnabled() || 
MORE.allowExtraAnalysis(PassName)16.3k
)
206
305
    R << ": " << ore::MNV("Inst", MI);
207
16.3k
  reportGISelFailure(MF, TPC, MORE, R);
208
16.3k
}
209
210
Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
211
3.57M
                                           const MachineRegisterInfo &MRI) {
212
3.57M
  Optional<ValueAndVReg> ValAndVReg =
213
3.57M
      getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
214
3.57M
  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
215
3.57M
         "Value found while looking through instrs");
216
3.57M
  if (!ValAndVReg)
217
2.14M
    return None;
218
1.43M
  return ValAndVReg->Value;
219
1.43M
}
220
221
Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
222
6.46M
    unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
223
6.46M
  SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes;
224
6.46M
  MachineInstr *MI;
225
6.97M
  while ((MI = MRI.getVRegDef(VReg)) &&
226
6.97M
         MI->getOpcode() != TargetOpcode::G_CONSTANT && 
LookThroughInstrs4.00M
) {
227
1.86M
    switch (MI->getOpcode()) {
228
1.86M
    case TargetOpcode::G_TRUNC:
229
148k
    case TargetOpcode::G_SEXT:
230
148k
    case TargetOpcode::G_ZEXT:
231
148k
      SeenOpcodes.push_back(std::make_pair(
232
148k
          MI->getOpcode(),
233
148k
          MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
234
148k
      VReg = MI->getOperand(1).getReg();
235
148k
      break;
236
194k
    case TargetOpcode::COPY:
237
194k
      VReg = MI->getOperand(1).getReg();
238
194k
      if (TargetRegisterInfo::isPhysicalRegister(VReg))
239
174k
        return None;
240
20.4k
      break;
241
335k
    case TargetOpcode::G_INTTOPTR:
242
335k
      VReg = MI->getOperand(1).getReg();
243
335k
      break;
244
1.18M
    default:
245
1.18M
      return None;
246
1.86M
    }
247
1.86M
  }
248
6.46M
  
if (5.11M
!MI5.11M
||
MI->getOpcode() != TargetOpcode::G_CONSTANT5.11M
||
249
5.11M
      
(2.96M
!MI->getOperand(1).isImm()2.96M
&&
!MI->getOperand(1).isCImm()2.96M
))
250
2.14M
    return None;
251
2.96M
252
2.96M
  const MachineOperand &CstVal = MI->getOperand(1);
253
2.96M
  unsigned BitWidth = MRI.getType(MI->getOperand(0).getReg()).getSizeInBits();
254
2.96M
  APInt Val = CstVal.isImm() ? 
APInt(BitWidth, CstVal.getImm())0
255
2.96M
                             : CstVal.getCImm()->getValue();
256
2.96M
  assert(Val.getBitWidth() == BitWidth &&
257
2.96M
         "Value bitwidth doesn't match definition type");
258
2.99M
  while (!SeenOpcodes.empty()) {
259
28.3k
    std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
260
28.3k
    switch (OpcodeAndSize.first) {
261
28.3k
    case TargetOpcode::G_TRUNC:
262
35
      Val = Val.trunc(OpcodeAndSize.second);
263
35
      break;
264
28.3k
    case TargetOpcode::G_SEXT:
265
28.3k
      Val = Val.sext(OpcodeAndSize.second);
266
28.3k
      break;
267
28.3k
    case TargetOpcode::G_ZEXT:
268
4
      Val = Val.zext(OpcodeAndSize.second);
269
4
      break;
270
28.3k
    }
271
28.3k
  }
272
2.96M
273
2.96M
  if (Val.getBitWidth() > 64)
274
26
    return None;
275
2.96M
276
2.96M
  return ValueAndVReg{Val.getSExtValue(), VReg};
277
2.96M
}
278
279
const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
280
15.9k
                                       const MachineRegisterInfo &MRI) {
281
15.9k
  MachineInstr *MI = MRI.getVRegDef(VReg);
282
15.9k
  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
283
4.50k
    return nullptr;
284
11.4k
  return MI->getOperand(1).getFPImm();
285
11.4k
}
286
287
llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
288
2.14M
                                               const MachineRegisterInfo &MRI) {
289
2.14M
  auto *DefMI = MRI.getVRegDef(Reg);
290
2.14M
  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
291
2.14M
  if (!DstTy.isValid())
292
0
    return nullptr;
293
2.14M
  
while (2.14M
DefMI->getOpcode() == TargetOpcode::COPY) {
294
307k
    unsigned SrcReg = DefMI->getOperand(1).getReg();
295
307k
    auto SrcTy = MRI.getType(SrcReg);
296
307k
    if (!SrcTy.isValid() || 
SrcTy != DstTy4.18k
)
297
303k
      break;
298
4.18k
    DefMI = MRI.getVRegDef(SrcReg);
299
4.18k
  }
300
2.14M
  return DefMI;
301
2.14M
}
302
303
llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg,
304
596k
                                       const MachineRegisterInfo &MRI) {
305
596k
  MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI);
306
596k
  return DefMI && DefMI->getOpcode() == Opcode ? 
DefMI55.2k
:
nullptr541k
;
307
596k
}
308
309
14
APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
310
14
  if (Size == 32)
311
6
    return APFloat(float(Val));
312
8
  if (Size == 64)
313
7
    return APFloat(Val);
314
1
  if (Size != 16)
315
1
    
llvm_unreachable0
("Unsupported FPConstant size");
316
1
  bool Ignored;
317
1
  APFloat APF(Val);
318
1
  APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
319
1
  return APF;
320
1
}
321
322
Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
323
                                        const unsigned Op2,
324
1.09M
                                        const MachineRegisterInfo &MRI) {
325
1.09M
  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
326
1.09M
  auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI);
327
1.09M
  if (MaybeOp1Cst && 
MaybeOp2Cst185k
) {
328
285
    LLT Ty = MRI.getType(Op1);
329
285
    APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
330
285
    APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true);
331
285
    switch (Opcode) {
332
285
    default:
333
0
      break;
334
285
    case TargetOpcode::G_ADD:
335
283
      return C1 + C2;
336
285
    case TargetOpcode::G_AND:
337
0
      return C1 & C2;
338
285
    case TargetOpcode::G_ASHR:
339
0
      return C1.ashr(C2);
340
285
    case TargetOpcode::G_LSHR:
341
0
      return C1.lshr(C2);
342
285
    case TargetOpcode::G_MUL:
343
0
      return C1 * C2;
344
285
    case TargetOpcode::G_OR:
345
0
      return C1 | C2;
346
285
    case TargetOpcode::G_SHL:
347
0
      return C1 << C2;
348
285
    case TargetOpcode::G_SUB:
349
2
      return C1 - C2;
350
285
    case TargetOpcode::G_XOR:
351
0
      return C1 ^ C2;
352
285
    case TargetOpcode::G_UDIV:
353
0
      if (!C2.getBoolValue())
354
0
        break;
355
0
      return C1.udiv(C2);
356
0
    case TargetOpcode::G_SDIV:
357
0
      if (!C2.getBoolValue())
358
0
        break;
359
0
      return C1.sdiv(C2);
360
0
    case TargetOpcode::G_UREM:
361
0
      if (!C2.getBoolValue())
362
0
        break;
363
0
      return C1.urem(C2);
364
0
    case TargetOpcode::G_SREM:
365
0
      if (!C2.getBoolValue())
366
0
        break;
367
0
      return C1.srem(C2);
368
285
    }
369
285
  }
370
1.09M
  return None;
371
1.09M
}
372
373
bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
374
188
                           bool SNaN) {
375
188
  const MachineInstr *DefMI = MRI.getVRegDef(Val);
376
188
  if (!DefMI)
377
0
    return false;
378
188
379
188
  if (DefMI->getFlag(MachineInstr::FmNoNans))
380
24
    return true;
381
164
382
164
  if (SNaN) {
383
164
    // FP operations quiet. For now, just handle the ones inserted during
384
164
    // legalization.
385
164
    switch (DefMI->getOpcode()) {
386
164
    case TargetOpcode::G_FPEXT:
387
40
    case TargetOpcode::G_FPTRUNC:
388
40
    case TargetOpcode::G_FCANONICALIZE:
389
40
      return true;
390
124
    default:
391
124
      return false;
392
0
    }
393
0
  }
394
0
395
0
  return false;
396
0
}
397
398
35.8k
void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) {
399
35.8k
  AU.addPreserved<StackProtector>();
400
35.8k
}