Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/TargetRegisterInfo.cpp
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Count
Source (jump to first uncovered line)
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//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the TargetRegisterInfo interface.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "llvm/CodeGen/TargetRegisterInfo.h"
14
#include "llvm/ADT/ArrayRef.h"
15
#include "llvm/ADT/BitVector.h"
16
#include "llvm/ADT/SmallSet.h"
17
#include "llvm/ADT/STLExtras.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/CodeGen/MachineFrameInfo.h"
20
#include "llvm/CodeGen/MachineFunction.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/CodeGen/TargetFrameLowering.h"
23
#include "llvm/CodeGen/TargetSubtargetInfo.h"
24
#include "llvm/CodeGen/VirtRegMap.h"
25
#include "llvm/Config/llvm-config.h"
26
#include "llvm/IR/Attributes.h"
27
#include "llvm/IR/Function.h"
28
#include "llvm/MC/MCRegisterInfo.h"
29
#include "llvm/Support/Compiler.h"
30
#include "llvm/Support/Debug.h"
31
#include "llvm/Support/MachineValueType.h"
32
#include "llvm/Support/MathExtras.h"
33
#include "llvm/Support/Printable.h"
34
#include "llvm/Support/raw_ostream.h"
35
#include <cassert>
36
#include <utility>
37
38
#define DEBUG_TYPE "target-reg-info"
39
40
using namespace llvm;
41
42
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
43
                             regclass_iterator RCB, regclass_iterator RCE,
44
                             const char *const *SRINames,
45
                             const LaneBitmask *SRILaneMasks,
46
                             LaneBitmask SRICoveringLanes,
47
                             const RegClassInfo *const RCIs,
48
                             unsigned Mode)
49
  : InfoDesc(ID), SubRegIndexNames(SRINames),
50
    SubRegIndexLaneMasks(SRILaneMasks),
51
    RegClassBegin(RCB), RegClassEnd(RCE),
52
    CoveringLanes(SRICoveringLanes),
53
53.2k
    RCInfos(RCIs), HwMode(Mode) {
54
53.2k
}
55
56
40.4k
TargetRegisterInfo::~TargetRegisterInfo() = default;
57
58
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
59
62.6M
    const {
60
284M
  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); 
++AI221M
)
61
221M
    RegisterSet.set(*AI);
62
62.6M
}
63
64
bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
65
0
    ArrayRef<MCPhysReg> Exceptions) const {
66
0
  // Check that all super registers of reserved regs are reserved as well.
67
0
  BitVector Checked(getNumRegs());
68
0
  for (unsigned Reg : RegisterSet.set_bits()) {
69
0
    if (Checked[Reg])
70
0
      continue;
71
0
    for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
72
0
      if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
73
0
        dbgs() << "Error: Super register " << printReg(*SR, this)
74
0
               << " of reserved register " << printReg(Reg, this)
75
0
               << " is not reserved.\n";
76
0
        return false;
77
0
      }
78
0
79
0
      // We transitively check superregs. So we can remember this for later
80
0
      // to avoid compiletime explosion in deep register hierarchies.
81
0
      Checked.set(*SR);
82
0
    }
83
0
  }
84
0
  return true;
85
0
}
86
87
namespace llvm {
88
89
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
90
1.16M
                   unsigned SubIdx, const MachineRegisterInfo *MRI) {
91
1.16M
  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
92
1.16M
    if (!Reg)
93
12.2k
      OS << "$noreg";
94
1.15M
    else if (TargetRegisterInfo::isStackSlot(Reg))
95
0
      OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
96
1.15M
    else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
97
194k
      StringRef Name = MRI ? 
MRI->getVRegName(Reg)190k
:
""3.82k
;
98
194k
      if (Name != "") {
99
203
        OS << '%' << Name;
100
194k
      } else {
101
194k
        OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
102
194k
      }
103
194k
    }
104
960k
    else if (!TRI)
105
1
      OS << '$' << "physreg" << Reg;
106
960k
    else if (Reg < TRI->getNumRegs()) {
107
960k
      OS << '$';
108
960k
      printLowerCase(TRI->getName(Reg), OS);
109
960k
    } else
110
960k
      
llvm_unreachable0
("Register kind is unsupported.");
111
1.16M
112
1.16M
    if (SubIdx) {
113
0
      if (TRI)
114
0
        OS << ':' << TRI->getSubRegIndexName(SubIdx);
115
0
      else
116
0
        OS << ":sub(" << SubIdx << ')';
117
0
    }
118
1.16M
  });
119
1.16M
}
120
121
0
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
122
0
  return Printable([Unit, TRI](raw_ostream &OS) {
123
0
    // Generic printout when TRI is missing.
124
0
    if (!TRI) {
125
0
      OS << "Unit~" << Unit;
126
0
      return;
127
0
    }
128
0
129
0
    // Check for invalid register units.
130
0
    if (Unit >= TRI->getNumRegUnits()) {
131
0
      OS << "BadUnit~" << Unit;
132
0
      return;
133
0
    }
134
0
135
0
    // Normal units have at least one root.
136
0
    MCRegUnitRootIterator Roots(Unit, TRI);
137
0
    assert(Roots.isValid() && "Unit has no roots.");
138
0
    OS << TRI->getName(*Roots);
139
0
    for (++Roots; Roots.isValid(); ++Roots)
140
0
      OS << '~' << TRI->getName(*Roots);
141
0
  });
142
0
}
143
144
0
Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
145
0
  return Printable([Unit, TRI](raw_ostream &OS) {
146
0
    if (TRI && TRI->isVirtualRegister(Unit)) {
147
0
      OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
148
0
    } else {
149
0
      OS << printRegUnit(Unit, TRI);
150
0
    }
151
0
  });
152
0
}
153
154
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
155
193k
                              const TargetRegisterInfo *TRI) {
156
193k
  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
157
193k
    if (RegInfo.getRegClassOrNull(Reg))
158
103k
      OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
159
90.5k
    else if (RegInfo.getRegBankOrNull(Reg))
160
22.8k
      OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
161
67.7k
    else {
162
67.7k
      OS << "_";
163
67.7k
      assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
164
67.7k
             "Generic registers must have a valid type");
165
67.7k
    }
166
193k
  });
167
193k
}
168
169
} // end namespace llvm
170
171
/// getAllocatableClass - Return the maximal subclass of the given register
172
/// class that is alloctable, or NULL.
173
const TargetRegisterClass *
174
7.59M
TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
175
7.59M
  if (!RC || 
RC->isAllocatable()5.75M
)
176
7.46M
    return RC;
177
126k
178
253k
  
for (BitMaskClassIterator It(RC->getSubClassMask(), *this); 126k
It.isValid();
179
127k
       
++It126k
) {
180
127k
    const TargetRegisterClass *SubRC = getRegClass(It.getID());
181
127k
    if (SubRC->isAllocatable())
182
504
      return SubRC;
183
127k
  }
184
126k
  
return nullptr126k
;
185
126k
}
186
187
/// getMinimalPhysRegClass - Returns the Register Class of a physical
188
/// register of the given type, picking the most sub register class of
189
/// the right type that contains this physreg.
190
const TargetRegisterClass *
191
4.93M
TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
192
4.93M
  assert(isPhysicalRegister(reg) && "reg must be a physical register");
193
4.93M
194
4.93M
  // Pick the most sub register class of the right type that contains
195
4.93M
  // this physreg.
196
4.93M
  const TargetRegisterClass* BestRC = nullptr;
197
520M
  for (const TargetRegisterClass* RC : regclasses()) {
198
520M
    if ((VT == MVT::Other || 
isTypeLegalForClass(*RC, VT)129M
) &&
199
520M
        
RC->contains(reg)412M
&&
(26.9M
!BestRC26.9M
||
BestRC->hasSubClass(RC)22.0M
))
200
17.7M
      BestRC = RC;
201
520M
  }
202
4.93M
203
4.93M
  assert(BestRC && "Couldn't find the register class");
204
4.93M
  return BestRC;
205
4.93M
}
206
207
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
208
/// registers for the specific register class.
209
static void getAllocatableSetForRC(const MachineFunction &MF,
210
12.7k
                                   const TargetRegisterClass *RC, BitVector &R){
211
12.7k
  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
212
12.7k
  ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
213
1.78M
  for (unsigned i = 0; i != Order.size(); 
++i1.77M
)
214
1.77M
    R.set(Order[i]);
215
12.7k
}
216
217
BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
218
12.0k
                                          const TargetRegisterClass *RC) const {
219
12.0k
  BitVector Allocatable(getNumRegs());
220
12.0k
  if (RC) {
221
12.0k
    // A register class with no allocatable subclass returns an empty set.
222
12.0k
    const TargetRegisterClass *SubClass = getAllocatableClass(RC);
223
12.0k
    if (SubClass)
224
12.0k
      getAllocatableSetForRC(MF, SubClass, Allocatable);
225
12.0k
  } else {
226
12
    for (const TargetRegisterClass *C : regclasses())
227
770
      if (C->isAllocatable())
228
616
        getAllocatableSetForRC(MF, C, Allocatable);
229
12
  }
230
12.0k
231
12.0k
  // Mask out the reserved registers
232
12.0k
  BitVector Reserved = getReservedRegs(MF);
233
12.0k
  Allocatable &= Reserved.flip();
234
12.0k
235
12.0k
  return Allocatable;
236
12.0k
}
237
238
static inline
239
const TargetRegisterClass *firstCommonClass(const uint32_t *A,
240
                                            const uint32_t *B,
241
                                            const TargetRegisterInfo *TRI,
242
                                            const MVT::SimpleValueType SVT =
243
30.1M
                                            MVT::SimpleValueType::Any) {
244
30.1M
  const MVT VT(SVT);
245
103M
  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; 
I += 3273.3M
)
246
86.6M
    if (unsigned Common = *A++ & *B++) {
247
13.2M
      const TargetRegisterClass *RC =
248
13.2M
          TRI->getRegClass(I + countTrailingZeros(Common));
249
13.2M
      if (SVT == MVT::SimpleValueType::Any || 
TRI->isTypeLegalForClass(*RC, VT)85.8k
)
250
13.2M
        return RC;
251
13.2M
    }
252
30.1M
  
return nullptr16.8M
;
253
30.1M
}
254
255
const TargetRegisterClass *
256
TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
257
                                      const TargetRegisterClass *B,
258
36.2M
                                      const MVT::SimpleValueType SVT) const {
259
36.2M
  // First take care of the trivial cases.
260
36.2M
  if (A == B)
261
11.8M
    return A;
262
24.4M
  if (!A || !B)
263
3
    return nullptr;
264
24.4M
265
24.4M
  // Register classes are ordered topologically, so the largest common
266
24.4M
  // sub-class it the common sub-class with the smallest ID.
267
24.4M
  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
268
24.4M
}
269
270
const TargetRegisterClass *
271
TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
272
                                             const TargetRegisterClass *B,
273
3.58M
                                             unsigned Idx) const {
274
3.58M
  assert(A && B && "Missing register class");
275
3.58M
  assert(Idx && "Bad sub-register index");
276
3.58M
277
3.58M
  // Find Idx in the list of super-register indices.
278
7.12M
  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); 
++RCI3.54M
)
279
7.05M
    if (RCI.getSubReg() == Idx)
280
3.51M
      // The bit mask contains all register classes that are projected into B
281
3.51M
      // by Idx. Find a class that is also a sub-class of A.
282
3.51M
      return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
283
3.58M
  
return nullptr68.8k
;
284
3.58M
}
285
286
const TargetRegisterClass *TargetRegisterInfo::
287
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
288
                       const TargetRegisterClass *RCB, unsigned SubB,
289
129k
                       unsigned &PreA, unsigned &PreB) const {
290
129k
  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
291
129k
292
129k
  // Search all pairs of sub-register indices that project into RCA and RCB
293
129k
  // respectively. This is quadratic, but usually the sets are very small. On
294
129k
  // most targets like X86, there will only be a single sub-register index
295
129k
  // (e.g., sub_16bit projecting into GR16).
296
129k
  //
297
129k
  // The worst case is a register class like DPR on ARM.
298
129k
  // We have indices dsub_0..dsub_7 projecting into that class.
299
129k
  //
300
129k
  // It is very common that one register class is a sub-register of the other.
301
129k
  // Arrange for RCA to be the larger register so the answer will be found in
302
129k
  // the first iteration. This makes the search linear for the most common
303
129k
  // case.
304
129k
  const TargetRegisterClass *BestRC = nullptr;
305
129k
  unsigned *BestPreA = &PreA;
306
129k
  unsigned *BestPreB = &PreB;
307
129k
  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
308
8.89k
    std::swap(RCA, RCB);
309
8.89k
    std::swap(SubA, SubB);
310
8.89k
    std::swap(BestPreA, BestPreB);
311
8.89k
  }
312
129k
313
129k
  // Also terminate the search one we have found a register class as small as
314
129k
  // RCA.
315
129k
  unsigned MinSize = getRegSizeInBits(*RCA);
316
129k
317
232k
  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); 
++IA103k
) {
318
224k
    unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
319
2.23M
    for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); 
++IB2.01M
) {
320
2.13M
      // Check if a common super-register class exists for this index pair.
321
2.13M
      const TargetRegisterClass *RC =
322
2.13M
        firstCommonClass(IA.getMask(), IB.getMask(), this);
323
2.13M
      if (!RC || 
getRegSizeInBits(*RC) < MinSize1.89M
)
324
238k
        continue;
325
1.89M
326
1.89M
      // The indexes must compose identically: PreA+SubA == PreB+SubB.
327
1.89M
      unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
328
1.89M
      if (FinalA != FinalB)
329
1.73M
        continue;
330
165k
331
165k
      // Is RC a better candidate than BestRC?
332
165k
      if (BestRC && 
getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)42.3k
)
333
42.2k
        continue;
334
122k
335
122k
      // Yes, RC is the smallest super-register seen so far.
336
122k
      BestRC = RC;
337
122k
      *BestPreA = IA.getSubReg();
338
122k
      *BestPreB = IB.getSubReg();
339
122k
340
122k
      // Bail early if we reached MinSize. We won't find a better candidate.
341
122k
      if (getRegSizeInBits(*BestRC) == MinSize)
342
121k
        return BestRC;
343
122k
    }
344
224k
  }
345
129k
  
return BestRC8.05k
;
346
129k
}
347
348
/// Check if the registers defined by the pair (RegisterClass, SubReg)
349
/// share the same register file.
350
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
351
                                  const TargetRegisterClass *DefRC,
352
                                  unsigned DefSubReg,
353
                                  const TargetRegisterClass *SrcRC,
354
1.01M
                                  unsigned SrcSubReg) {
355
1.01M
  // Same register class.
356
1.01M
  if (DefRC == SrcRC)
357
182k
    return true;
358
828k
359
828k
  // Both operands are sub registers. Check if they share a register class.
360
828k
  unsigned SrcIdx, DefIdx;
361
828k
  if (SrcSubReg && 
DefSubReg294k
) {
362
1
    return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
363
1
                                      SrcIdx, DefIdx) != nullptr;
364
1
  }
365
828k
366
828k
  // At most one of the register is a sub register, make it Src to avoid
367
828k
  // duplicating the test.
368
828k
  if (!SrcSubReg) {
369
534k
    std::swap(DefSubReg, SrcSubReg);
370
534k
    std::swap(DefRC, SrcRC);
371
534k
  }
372
828k
373
828k
  // One of the register is a sub register, check if we can get a superclass.
374
828k
  if (SrcSubReg)
375
438k
    return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
376
390k
377
390k
  // Plain copy.
378
390k
  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
379
390k
}
380
381
bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
382
                                              unsigned DefSubReg,
383
                                              const TargetRegisterClass *SrcRC,
384
1.01M
                                              unsigned SrcSubReg) const {
385
1.01M
  // If this source does not incur a cross register bank copy, use it.
386
1.01M
  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
387
1.01M
}
388
389
// Compute target-independent register allocator hints to help eliminate copies.
390
bool
391
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
392
                                          ArrayRef<MCPhysReg> Order,
393
                                          SmallVectorImpl<MCPhysReg> &Hints,
394
                                          const MachineFunction &MF,
395
                                          const VirtRegMap *VRM,
396
12.1M
                                          const LiveRegMatrix *Matrix) const {
397
12.1M
  const MachineRegisterInfo &MRI = MF.getRegInfo();
398
12.1M
  const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
399
12.1M
    MRI.getRegAllocationHints(VirtReg);
400
12.1M
401
12.1M
  SmallSet<unsigned, 32> HintedRegs;
402
12.1M
  // First hint may be a target hint.
403
12.1M
  bool Skip = (Hints_MRI.first != 0);
404
12.1M
  for (auto Reg : Hints_MRI.second) {
405
5.10M
    if (Skip) {
406
0
      Skip = false;
407
0
      continue;
408
0
    }
409
5.10M
410
5.10M
    // Target-independent hints are either a physical or a virtual register.
411
5.10M
    unsigned Phys = Reg;
412
5.10M
    if (VRM && 
isVirtualRegister(Phys)5.10M
)
413
1.42M
      Phys = VRM->getPhys(Phys);
414
5.10M
415
5.10M
    // Don't add the same reg twice (Hints_MRI may contain multiple virtual
416
5.10M
    // registers allocated to the same physreg).
417
5.10M
    if (!HintedRegs.insert(Phys).second)
418
189k
      continue;
419
4.91M
    // Check that Phys is a valid hint in VirtReg's register class.
420
4.91M
    if (!isPhysicalRegister(Phys))
421
671k
      continue;
422
4.24M
    if (MRI.isReserved(Phys))
423
0
      continue;
424
4.24M
    // Check that Phys is in the allocation order. We shouldn't heed hints
425
4.24M
    // from VirtReg's register class if they aren't in the allocation order. The
426
4.24M
    // target probably has a reason for removing the register.
427
4.24M
    if (!is_contained(Order, Phys))
428
51.0k
      continue;
429
4.19M
430
4.19M
    // All clear, tell the register allocator to prefer this register.
431
4.19M
    Hints.push_back(Phys);
432
4.19M
  }
433
12.1M
  return false;
434
12.1M
}
435
436
217k
bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
437
217k
  return !MF.getFunction().hasFnAttribute("no-realign-stack");
438
217k
}
439
440
bool TargetRegisterInfo::needsStackRealignment(
441
10.8M
    const MachineFunction &MF) const {
442
10.8M
  const MachineFrameInfo &MFI = MF.getFrameInfo();
443
10.8M
  const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
444
10.8M
  const Function &F = MF.getFunction();
445
10.8M
  unsigned StackAlign = TFI->getStackAlignment();
446
10.8M
  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
447
10.8M
                              
F.hasFnAttribute(Attribute::StackAlignment)10.6M
);
448
10.8M
  if (F.hasFnAttribute("stackrealign") || 
requiresRealignment10.7M
) {
449
200k
    if (canRealignStack(MF))
450
157k
      return true;
451
42.6k
    LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName()
452
42.6k
                      << "\n");
453
42.6k
  }
454
10.8M
  
return false10.6M
;
455
10.8M
}
456
457
bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
458
887
                                            const uint32_t *mask1) const {
459
887
  unsigned N = (getNumRegs()+31) / 32;
460
9.88k
  for (unsigned I = 0; I < N; 
++I8.99k
)
461
9.02k
    if ((mask0[I] & mask1[I]) != mask0[I])
462
25
      return false;
463
887
  
return true862
;
464
887
}
465
466
unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
467
9.27M
                                         const MachineRegisterInfo &MRI) const {
468
9.27M
  const TargetRegisterClass *RC{};
469
9.27M
  if (isPhysicalRegister(Reg)) {
470
1.90M
    // The size is not directly available for physical registers.
471
1.90M
    // Instead, we need to access a register class that contains Reg and
472
1.90M
    // get the size of that register class.
473
1.90M
    RC = getMinimalPhysRegClass(Reg);
474
7.36M
  } else {
475
7.36M
    LLT Ty = MRI.getType(Reg);
476
7.36M
    unsigned RegSize = Ty.isValid() ? 
Ty.getSizeInBits()7.34M
:
015.3k
;
477
7.36M
    // If Reg is not a generic register, query the register class to
478
7.36M
    // get its size.
479
7.36M
    if (RegSize)
480
7.34M
      return RegSize;
481
15.3k
    // Since Reg is not a generic register, it must have a register class.
482
15.3k
    RC = MRI.getRegClass(Reg);
483
15.3k
  }
484
9.27M
  assert(RC && "Unable to deduce the register class");
485
1.92M
  return getRegSizeInBits(*RC);
486
9.27M
}
487
488
unsigned
489
TargetRegisterInfo::lookThruCopyLike(unsigned SrcReg,
490
464k
                                     const MachineRegisterInfo *MRI) const {
491
505k
  while (true) {
492
505k
    const MachineInstr *MI = MRI->getVRegDef(SrcReg);
493
505k
    if (!MI->isCopyLike())
494
406k
      return SrcReg;
495
99.1k
496
99.1k
    unsigned CopySrcReg;
497
99.1k
    if (MI->isCopy())
498
91.7k
      CopySrcReg = MI->getOperand(1).getReg();
499
7.33k
    else {
500
7.33k
      assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
501
7.33k
      CopySrcReg = MI->getOperand(2).getReg();
502
7.33k
    }
503
99.1k
504
99.1k
    if (!isVirtualRegister(CopySrcReg))
505
58.9k
      return CopySrcReg;
506
40.1k
507
40.1k
    SrcReg = CopySrcReg;
508
40.1k
  }
509
464k
}
510
511
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
512
LLVM_DUMP_METHOD
513
void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
514
                                 const TargetRegisterInfo *TRI) {
515
  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
516
}
517
#endif