Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
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//==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file When allowed by the instruction, replace a dead definition of a GPR
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/// with the zero register. This makes the code a bit friendlier towards the
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/// hardware's register renamer.
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-dead-defs"
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STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
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#define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
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namespace {
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class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
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private:
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  const TargetRegisterInfo *TRI;
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  const MachineRegisterInfo *MRI;
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  const TargetInstrInfo *TII;
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  bool Changed;
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  void processMachineBasicBlock(MachineBasicBlock &MBB);
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public:
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  static char ID; // Pass identification, replacement for typeid.
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8.62k
  AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
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8.62k
    initializeAArch64DeadRegisterDefinitionsPass(
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8.62k
        *PassRegistry::getPassRegistry());
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8.62k
  }
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  bool runOnMachineFunction(MachineFunction &F) override;
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265k
  StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
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8.57k
  void getAnalysisUsage(AnalysisUsage &AU) const override {
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8.57k
    AU.setPreservesCFG();
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8.57k
    MachineFunctionPass::getAnalysisUsage(AU);
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8.57k
  }
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};
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char AArch64DeadRegisterDefinitions::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
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                AARCH64_DEAD_REG_DEF_NAME, false, false)
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18.9M
static bool usesFrameIndex(const MachineInstr &MI) {
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18.9M
  for (const MachineOperand &MO : MI.uses())
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47.1M
    if (MO.isFI())
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279k
      return true;
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18.9M
  
return false18.6M
;
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18.9M
}
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// Instructions that lose their 'read' operation for a subesquent fence acquire
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// (DMB LD) once the zero register is used.
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//
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// WARNING: The aquire variants of the instructions are also affected, but they
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// are split out into `atomicBarrierDroppedOnZero()` to support annotations on
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// assembly.
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18.2M
static bool atomicReadDroppedOnZero(unsigned Opcode) {
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18.2M
  switch (Opcode) {
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18.2M
    
case AArch64::LDADDB: 432
case AArch64::LDADDH:
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432
    case AArch64::LDADDW:     case AArch64::LDADDX:
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432
    case AArch64::LDADDLB:    case AArch64::LDADDLH:
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432
    case AArch64::LDADDLW:    case AArch64::LDADDLX:
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432
    case AArch64::LDCLRB:     case AArch64::LDCLRH:
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432
    case AArch64::LDCLRW:     case AArch64::LDCLRX:
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432
    case AArch64::LDCLRLB:    case AArch64::LDCLRLH:
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432
    case AArch64::LDCLRLW:    case AArch64::LDCLRLX:
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432
    case AArch64::LDEORB:     case AArch64::LDEORH:
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432
    case AArch64::LDEORW:     case AArch64::LDEORX:
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432
    case AArch64::LDEORLB:    case AArch64::LDEORLH:
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432
    case AArch64::LDEORLW:    case AArch64::LDEORLX:
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432
    case AArch64::LDSETB:     case AArch64::LDSETH:
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432
    case AArch64::LDSETW:     case AArch64::LDSETX:
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432
    case AArch64::LDSETLB:    case AArch64::LDSETLH:
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432
    case AArch64::LDSETLW:    case AArch64::LDSETLX:
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432
    case AArch64::LDSMAXB:    case AArch64::LDSMAXH:
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432
    case AArch64::LDSMAXW:    case AArch64::LDSMAXX:
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432
    case AArch64::LDSMAXLB:   case AArch64::LDSMAXLH:
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432
    case AArch64::LDSMAXLW:   case AArch64::LDSMAXLX:
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432
    case AArch64::LDSMINB:    case AArch64::LDSMINH:
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432
    case AArch64::LDSMINW:    case AArch64::LDSMINX:
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432
    case AArch64::LDSMINLB:   case AArch64::LDSMINLH:
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432
    case AArch64::LDSMINLW:   case AArch64::LDSMINLX:
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432
    case AArch64::LDUMAXB:    case AArch64::LDUMAXH:
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432
    case AArch64::LDUMAXW:    case AArch64::LDUMAXX:
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432
    case AArch64::LDUMAXLB:   case AArch64::LDUMAXLH:
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432
    case AArch64::LDUMAXLW:   case AArch64::LDUMAXLX:
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432
    case AArch64::LDUMINB:    case AArch64::LDUMINH:
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432
    case AArch64::LDUMINW:    case AArch64::LDUMINX:
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432
    case AArch64::LDUMINLB:   case AArch64::LDUMINLH:
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432
    case AArch64::LDUMINLW:   case AArch64::LDUMINLX:
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    return true;
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18.2M
  }
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  return false;
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}
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void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
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2.08M
    MachineBasicBlock &MBB) {
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  const MachineFunction &MF = *MBB.getParent();
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  for (MachineInstr &MI : MBB) {
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    if (usesFrameIndex(MI)) {
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      // We need to skip this instruction because while it appears to have a
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      // dead def it uses a frame index which might expand into a multi
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      // instruction sequence during EPI.
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      LLVM_DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
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      continue;
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    }
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    if (MI.definesRegister(AArch64::XZR) || 
MI.definesRegister(AArch64::WZR)18.5M
) {
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      // It is not allowed to write to the same register (not even the zero
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      // register) twice in a single instruction.
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      LLVM_DEBUG(
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          dbgs()
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          << "    Ignoring, XZR or WZR already used by the instruction\n");
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      continue;
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    }
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18.2M
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18.2M
    if (atomicBarrierDroppedOnZero(MI.getOpcode()) || 
atomicReadDroppedOnZero(MI.getOpcode())18.2M
) {
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1.45k
      LLVM_DEBUG(dbgs() << "    Ignoring, semantics change with xzr/wzr.\n");
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1.45k
      continue;
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    }
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18.2M
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18.2M
    const MCInstrDesc &Desc = MI.getDesc();
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29.4M
    for (int I = 0, E = Desc.getNumDefs(); I != E; 
++I11.2M
) {
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11.4M
      MachineOperand &MO = MI.getOperand(I);
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11.4M
      if (!MO.isReg() || 
!MO.isDef()11.4M
)
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        continue;
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11.4M
      // We should not have any relevant physreg defs that are replacable by
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11.4M
      // zero before register allocation. So we just check for dead vreg defs.
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11.4M
      unsigned Reg = MO.getReg();
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11.4M
      if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
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11.4M
          
(8.33M
!MO.isDead()8.33M
&&
!MRI->use_nodbg_empty(Reg)8.33M
))
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11.2M
        continue;
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171k
      assert(!MO.isImplicit() && "Unexpected implicit def!");
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      LLVM_DEBUG(dbgs() << "  Dead def operand #" << I << " in:\n    ";
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                 MI.print(dbgs()));
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      // Be careful not to change the register if it's a tied operand.
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      if (MI.isRegTiedToUseOperand(I)) {
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        LLVM_DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
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        continue;
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      }
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      const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
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      unsigned NewReg;
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      if (RC == nullptr) {
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        LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
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        continue;
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      } else if (RC->contains(AArch64::WZR))
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        NewReg = AArch64::WZR;
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      else if (RC->contains(AArch64::XZR))
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        NewReg = AArch64::XZR;
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2.41k
      else {
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        LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
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        continue;
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      }
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      LLVM_DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
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      MO.setReg(NewReg);
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      MO.setIsDead();
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      LLVM_DEBUG(MI.print(dbgs()));
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      ++NumDeadDefsReplaced;
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      Changed = true;
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      // Only replace one dead register, see check for zero register above.
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      break;
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    }
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  }
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2.08M
}
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// Scan the function for instructions that have a dead definition of a
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// register. Replace that register with the zero register when possible.
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257k
bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
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257k
  if (skipFunction(MF.getFunction()))
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16
    return false;
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257k
  TRI = MF.getSubtarget().getRegisterInfo();
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  TII = MF.getSubtarget().getInstrInfo();
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  MRI = &MF.getRegInfo();
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  LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
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  Changed = false;
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257k
  for (auto &MBB : MF)
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2.08M
    processMachineBasicBlock(MBB);
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257k
  return Changed;
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}
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8.62k
FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
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8.62k
  return new AArch64DeadRegisterDefinitions();
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8.62k
}