/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
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1 | | //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | /// \file When allowed by the instruction, replace a dead definition of a GPR |
9 | | /// with the zero register. This makes the code a bit friendlier towards the |
10 | | /// hardware's register renamer. |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "AArch64.h" |
14 | | #include "AArch64RegisterInfo.h" |
15 | | #include "AArch64Subtarget.h" |
16 | | #include "llvm/ADT/Statistic.h" |
17 | | #include "llvm/CodeGen/ISDOpcodes.h" |
18 | | #include "llvm/CodeGen/MachineFunction.h" |
19 | | #include "llvm/CodeGen/MachineFunctionPass.h" |
20 | | #include "llvm/CodeGen/MachineInstr.h" |
21 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
22 | | #include "llvm/CodeGen/TargetInstrInfo.h" |
23 | | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
24 | | #include "llvm/Support/Debug.h" |
25 | | #include "llvm/Support/raw_ostream.h" |
26 | | using namespace llvm; |
27 | | |
28 | | #define DEBUG_TYPE "aarch64-dead-defs" |
29 | | |
30 | | STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced"); |
31 | | |
32 | 265k | #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions" |
33 | | |
34 | | namespace { |
35 | | class AArch64DeadRegisterDefinitions : public MachineFunctionPass { |
36 | | private: |
37 | | const TargetRegisterInfo *TRI; |
38 | | const MachineRegisterInfo *MRI; |
39 | | const TargetInstrInfo *TII; |
40 | | bool Changed; |
41 | | void processMachineBasicBlock(MachineBasicBlock &MBB); |
42 | | public: |
43 | | static char ID; // Pass identification, replacement for typeid. |
44 | 8.62k | AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) { |
45 | 8.62k | initializeAArch64DeadRegisterDefinitionsPass( |
46 | 8.62k | *PassRegistry::getPassRegistry()); |
47 | 8.62k | } |
48 | | |
49 | | bool runOnMachineFunction(MachineFunction &F) override; |
50 | | |
51 | 265k | StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } |
52 | | |
53 | 8.57k | void getAnalysisUsage(AnalysisUsage &AU) const override { |
54 | 8.57k | AU.setPreservesCFG(); |
55 | 8.57k | MachineFunctionPass::getAnalysisUsage(AU); |
56 | 8.57k | } |
57 | | }; |
58 | | char AArch64DeadRegisterDefinitions::ID = 0; |
59 | | } // end anonymous namespace |
60 | | |
61 | | INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs", |
62 | | AARCH64_DEAD_REG_DEF_NAME, false, false) |
63 | | |
64 | 18.9M | static bool usesFrameIndex(const MachineInstr &MI) { |
65 | 18.9M | for (const MachineOperand &MO : MI.uses()) |
66 | 47.1M | if (MO.isFI()) |
67 | 279k | return true; |
68 | 18.9M | return false18.6M ; |
69 | 18.9M | } |
70 | | |
71 | | // Instructions that lose their 'read' operation for a subesquent fence acquire |
72 | | // (DMB LD) once the zero register is used. |
73 | | // |
74 | | // WARNING: The aquire variants of the instructions are also affected, but they |
75 | | // are split out into `atomicBarrierDroppedOnZero()` to support annotations on |
76 | | // assembly. |
77 | 18.2M | static bool atomicReadDroppedOnZero(unsigned Opcode) { |
78 | 18.2M | switch (Opcode) { |
79 | 18.2M | case AArch64::LDADDB: 432 case AArch64::LDADDH: |
80 | 432 | case AArch64::LDADDW: case AArch64::LDADDX: |
81 | 432 | case AArch64::LDADDLB: case AArch64::LDADDLH: |
82 | 432 | case AArch64::LDADDLW: case AArch64::LDADDLX: |
83 | 432 | case AArch64::LDCLRB: case AArch64::LDCLRH: |
84 | 432 | case AArch64::LDCLRW: case AArch64::LDCLRX: |
85 | 432 | case AArch64::LDCLRLB: case AArch64::LDCLRLH: |
86 | 432 | case AArch64::LDCLRLW: case AArch64::LDCLRLX: |
87 | 432 | case AArch64::LDEORB: case AArch64::LDEORH: |
88 | 432 | case AArch64::LDEORW: case AArch64::LDEORX: |
89 | 432 | case AArch64::LDEORLB: case AArch64::LDEORLH: |
90 | 432 | case AArch64::LDEORLW: case AArch64::LDEORLX: |
91 | 432 | case AArch64::LDSETB: case AArch64::LDSETH: |
92 | 432 | case AArch64::LDSETW: case AArch64::LDSETX: |
93 | 432 | case AArch64::LDSETLB: case AArch64::LDSETLH: |
94 | 432 | case AArch64::LDSETLW: case AArch64::LDSETLX: |
95 | 432 | case AArch64::LDSMAXB: case AArch64::LDSMAXH: |
96 | 432 | case AArch64::LDSMAXW: case AArch64::LDSMAXX: |
97 | 432 | case AArch64::LDSMAXLB: case AArch64::LDSMAXLH: |
98 | 432 | case AArch64::LDSMAXLW: case AArch64::LDSMAXLX: |
99 | 432 | case AArch64::LDSMINB: case AArch64::LDSMINH: |
100 | 432 | case AArch64::LDSMINW: case AArch64::LDSMINX: |
101 | 432 | case AArch64::LDSMINLB: case AArch64::LDSMINLH: |
102 | 432 | case AArch64::LDSMINLW: case AArch64::LDSMINLX: |
103 | 432 | case AArch64::LDUMAXB: case AArch64::LDUMAXH: |
104 | 432 | case AArch64::LDUMAXW: case AArch64::LDUMAXX: |
105 | 432 | case AArch64::LDUMAXLB: case AArch64::LDUMAXLH: |
106 | 432 | case AArch64::LDUMAXLW: case AArch64::LDUMAXLX: |
107 | 432 | case AArch64::LDUMINB: case AArch64::LDUMINH: |
108 | 432 | case AArch64::LDUMINW: case AArch64::LDUMINX: |
109 | 432 | case AArch64::LDUMINLB: case AArch64::LDUMINLH: |
110 | 432 | case AArch64::LDUMINLW: case AArch64::LDUMINLX: |
111 | 432 | return true; |
112 | 18.2M | } |
113 | 18.2M | return false; |
114 | 18.2M | } |
115 | | |
116 | | void AArch64DeadRegisterDefinitions::processMachineBasicBlock( |
117 | 2.08M | MachineBasicBlock &MBB) { |
118 | 2.08M | const MachineFunction &MF = *MBB.getParent(); |
119 | 18.9M | for (MachineInstr &MI : MBB) { |
120 | 18.9M | if (usesFrameIndex(MI)) { |
121 | 279k | // We need to skip this instruction because while it appears to have a |
122 | 279k | // dead def it uses a frame index which might expand into a multi |
123 | 279k | // instruction sequence during EPI. |
124 | 279k | LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); |
125 | 279k | continue; |
126 | 279k | } |
127 | 18.6M | if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)18.5M ) { |
128 | 446k | // It is not allowed to write to the same register (not even the zero |
129 | 446k | // register) twice in a single instruction. |
130 | 446k | LLVM_DEBUG( |
131 | 446k | dbgs() |
132 | 446k | << " Ignoring, XZR or WZR already used by the instruction\n"); |
133 | 446k | continue; |
134 | 446k | } |
135 | 18.2M | |
136 | 18.2M | if (atomicBarrierDroppedOnZero(MI.getOpcode()) || atomicReadDroppedOnZero(MI.getOpcode())18.2M ) { |
137 | 1.45k | LLVM_DEBUG(dbgs() << " Ignoring, semantics change with xzr/wzr.\n"); |
138 | 1.45k | continue; |
139 | 1.45k | } |
140 | 18.2M | |
141 | 18.2M | const MCInstrDesc &Desc = MI.getDesc(); |
142 | 29.4M | for (int I = 0, E = Desc.getNumDefs(); I != E; ++I11.2M ) { |
143 | 11.4M | MachineOperand &MO = MI.getOperand(I); |
144 | 11.4M | if (!MO.isReg() || !MO.isDef()11.4M ) |
145 | 39 | continue; |
146 | 11.4M | // We should not have any relevant physreg defs that are replacable by |
147 | 11.4M | // zero before register allocation. So we just check for dead vreg defs. |
148 | 11.4M | unsigned Reg = MO.getReg(); |
149 | 11.4M | if (!TargetRegisterInfo::isVirtualRegister(Reg) || |
150 | 11.4M | (8.33M !MO.isDead()8.33M && !MRI->use_nodbg_empty(Reg)8.33M )) |
151 | 11.2M | continue; |
152 | 171k | assert(!MO.isImplicit() && "Unexpected implicit def!"); |
153 | 171k | LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; |
154 | 171k | MI.print(dbgs())); |
155 | 171k | // Be careful not to change the register if it's a tied operand. |
156 | 171k | if (MI.isRegTiedToUseOperand(I)) { |
157 | 9 | LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); |
158 | 9 | continue; |
159 | 9 | } |
160 | 171k | const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); |
161 | 171k | unsigned NewReg; |
162 | 171k | if (RC == nullptr) { |
163 | 2 | LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); |
164 | 2 | continue; |
165 | 171k | } else if (RC->contains(AArch64::WZR)) |
166 | 95.3k | NewReg = AArch64::WZR; |
167 | 76.0k | else if (RC->contains(AArch64::XZR)) |
168 | 73.5k | NewReg = AArch64::XZR; |
169 | 2.41k | else { |
170 | 2.41k | LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); |
171 | 2.41k | continue; |
172 | 2.41k | } |
173 | 168k | LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "); |
174 | 168k | MO.setReg(NewReg); |
175 | 168k | MO.setIsDead(); |
176 | 168k | LLVM_DEBUG(MI.print(dbgs())); |
177 | 168k | ++NumDeadDefsReplaced; |
178 | 168k | Changed = true; |
179 | 168k | // Only replace one dead register, see check for zero register above. |
180 | 168k | break; |
181 | 168k | } |
182 | 18.2M | } |
183 | 2.08M | } |
184 | | |
185 | | // Scan the function for instructions that have a dead definition of a |
186 | | // register. Replace that register with the zero register when possible. |
187 | 257k | bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { |
188 | 257k | if (skipFunction(MF.getFunction())) |
189 | 16 | return false; |
190 | 257k | |
191 | 257k | TRI = MF.getSubtarget().getRegisterInfo(); |
192 | 257k | TII = MF.getSubtarget().getInstrInfo(); |
193 | 257k | MRI = &MF.getRegInfo(); |
194 | 257k | LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); |
195 | 257k | Changed = false; |
196 | 257k | for (auto &MBB : MF) |
197 | 2.08M | processMachineBasicBlock(MBB); |
198 | 257k | return Changed; |
199 | 257k | } |
200 | | |
201 | 8.62k | FunctionPass *llvm::createAArch64DeadRegisterDefinitions() { |
202 | 8.62k | return new AArch64DeadRegisterDefinitions(); |
203 | 8.62k | } |