Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/SIFrameLowering.h
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//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#include "AMDGPUFrameLowering.h"
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namespace llvm {
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class SIInstrInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class GCNSubtarget;
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class SIFrameLowering final : public AMDGPUFrameLowering {
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public:
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  SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
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                  unsigned TransAl = 1) :
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    AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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  ~SIFrameLowering() override = default;
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  void emitEntryFunctionPrologue(MachineFunction &MF,
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                                 MachineBasicBlock &MBB) const;
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  void emitPrologue(MachineFunction &MF,
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                    MachineBasicBlock &MBB) const override;
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  void emitEpilogue(MachineFunction &MF,
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                    MachineBasicBlock &MBB) const override;
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  int getFrameIndexReference(const MachineFunction &MF, int FI,
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                             unsigned &FrameReg) const override;
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  void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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                            RegScavenger *RS = nullptr) const override;
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  void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs,
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                                RegScavenger *RS = nullptr) const;
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  bool
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  assignCalleeSavedSpillSlots(MachineFunction &MF,
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                              const TargetRegisterInfo *TRI,
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                              std::vector<CalleeSavedInfo> &CSI) const override;
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  bool isSupportedStackID(TargetStackID::Value ID) const override;
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  void processFunctionBeforeFrameFinalized(
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    MachineFunction &MF,
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    RegScavenger *RS = nullptr) const override;
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  MachineBasicBlock::iterator
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  eliminateCallFramePseudoInstr(MachineFunction &MF,
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                                MachineBasicBlock &MBB,
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                                MachineBasicBlock::iterator MI) const override;
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private:
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  void emitFlatScratchInit(const GCNSubtarget &ST,
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                           MachineFunction &MF,
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                           MachineBasicBlock &MBB) const;
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  unsigned getReservedPrivateSegmentBufferReg(
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    const GCNSubtarget &ST,
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    const SIInstrInfo *TII,
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    const SIRegisterInfo *TRI,
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    SIMachineFunctionInfo *MFI,
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    MachineFunction &MF) const;
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  std::pair<unsigned, bool> getReservedPrivateSegmentWaveByteOffsetReg(
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      const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
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      SIMachineFunctionInfo *MFI, MachineFunction &MF) const;
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  // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
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  void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
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      MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
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      MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
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      unsigned ScratchRsrcReg) const;
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public:
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  bool hasFP(const MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H