Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
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1
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the base ARM implementation of TargetRegisterInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
14
#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15
16
#include "MCTargetDesc/ARMBaseInfo.h"
17
#include "llvm/CodeGen/MachineBasicBlock.h"
18
#include "llvm/CodeGen/MachineInstr.h"
19
#include "llvm/CodeGen/TargetRegisterInfo.h"
20
#include "llvm/IR/CallingConv.h"
21
#include "llvm/MC/MCRegisterInfo.h"
22
#include <cstdint>
23
24
#define GET_REGINFO_HEADER
25
#include "ARMGenRegisterInfo.inc"
26
27
namespace llvm {
28
29
class LiveIntervals;
30
31
/// Register allocation hints.
32
namespace ARMRI {
33
34
  enum {
35
    RegPairOdd  = 1,
36
    RegPairEven = 2
37
  };
38
39
} // end namespace ARMRI
40
41
/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
42
/// or a stack/pc register that we should push/pop.
43
103k
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
44
103k
  using namespace ARM;
45
103k
46
103k
  switch (Reg) {
47
103k
    
case R0: 79.0k
case R1: 79.0k
case R2: 79.0k
case R3:
48
79.0k
    case R4:  case R5:  case R6:  case R7:
49
79.0k
    case LR:  case SP:  case PC:
50
79.0k
      return true;
51
79.0k
    
case R8: 20.2k
case R9: 20.2k
case R10: 20.2k
case R11: 20.2k
case R12:
52
20.2k
      // For iOS we want r7 and lr to be next to each other.
53
20.2k
      return !isIOS;
54
20.2k
    default:
55
3.78k
      return false;
56
103k
  }
57
103k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea1Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
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Count
Source
43
103k
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
44
103k
  using namespace ARM;
45
103k
46
103k
  switch (Reg) {
47
103k
    
case R0: 79.0k
case R1: 79.0k
case R2: 79.0k
case R3:
48
79.0k
    case R4:  case R5:  case R6:  case R7:
49
79.0k
    case LR:  case SP:  case PC:
50
79.0k
      return true;
51
79.0k
    
case R8: 20.2k
case R9: 20.2k
case R10: 20.2k
case R11: 20.2k
case R12:
52
20.2k
      // For iOS we want r7 and lr to be next to each other.
53
20.2k
      return !isIOS;
54
20.2k
    default:
55
3.78k
      return false;
56
103k
  }
57
103k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea1Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea1Register(unsigned int, bool)
58
59
103k
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
60
103k
  using namespace ARM;
61
103k
62
103k
  switch (Reg) {
63
103k
    
case R8: 20.2k
case R9: 20.2k
case R10: 20.2k
case R11: 20.2k
case R12:
64
20.2k
      // iOS has this second area.
65
20.2k
      return isIOS;
66
82.8k
    default:
67
82.8k
      return false;
68
103k
  }
69
103k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea2Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Line
Count
Source
59
103k
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
60
103k
  using namespace ARM;
61
103k
62
103k
  switch (Reg) {
63
103k
    
case R8: 20.2k
case R9: 20.2k
case R10: 20.2k
case R11: 20.2k
case R12:
64
20.2k
      // iOS has this second area.
65
20.2k
      return isIOS;
66
82.8k
    default:
67
82.8k
      return false;
68
103k
  }
69
103k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea2Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea2Register(unsigned int, bool)
70
71
103k
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
72
103k
  using namespace ARM;
73
103k
74
103k
  switch (Reg) {
75
103k
    
case D15: 3.83k
case D14: 3.83k
case D13: 3.83k
case D12:
76
3.83k
    case D11: case D10: case D9:  case D8:
77
3.83k
    case D7:  case D6:  case D5:  case D4:
78
3.83k
    case D3:  case D2:  case D1:  case D0:
79
3.83k
    case D31: case D30: case D29: case D28:
80
3.83k
    case D27: case D26: case D25: case D24:
81
3.83k
    case D23: case D22: case D21: case D20:
82
3.83k
    case D19: case D18: case D17: case D16:
83
3.83k
      return true;
84
99.3k
    default:
85
99.3k
      return false;
86
103k
  }
87
103k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMArea3Register(unsigned int, bool)
ARMFrameLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Line
Count
Source
71
103k
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
72
103k
  using namespace ARM;
73
103k
74
103k
  switch (Reg) {
75
103k
    
case D15: 3.83k
case D14: 3.83k
case D13: 3.83k
case D12:
76
3.83k
    case D11: case D10: case D9:  case D8:
77
3.83k
    case D7:  case D6:  case D5:  case D4:
78
3.83k
    case D3:  case D2:  case D1:  case D0:
79
3.83k
    case D31: case D30: case D29: case D28:
80
3.83k
    case D27: case D26: case D25: case D24:
81
3.83k
    case D23: case D22: case D21: case D20:
82
3.83k
    case D19: case D18: case D17: case D16:
83
3.83k
      return true;
84
99.3k
    default:
85
99.3k
      return false;
86
103k
  }
87
103k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isARMArea3Register(unsigned int, bool)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMArea3Register(unsigned int, bool)
88
89
static inline bool isCalleeSavedRegister(unsigned Reg,
90
16.4k
                                         const MCPhysReg *CSRegs) {
91
93.2k
  for (unsigned i = 0; CSRegs[i]; 
++i76.8k
)
92
92.9k
    if (Reg == CSRegs[i])
93
16.1k
      return true;
94
16.4k
  
return false369
;
95
16.4k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
ARMBaseInstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
90
550
                                         const MCPhysReg *CSRegs) {
91
7.05k
  for (unsigned i = 0; CSRegs[i]; 
++i6.50k
)
92
6.69k
    if (Reg == CSRegs[i])
93
195
      return true;
94
550
  
return false355
;
95
550
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
ARMFrameLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
90
15.9k
                                         const MCPhysReg *CSRegs) {
91
85.9k
  for (unsigned i = 0; CSRegs[i]; 
++i70.0k
)
92
85.9k
    if (Reg == CSRegs[i])
93
15.9k
      return true;
94
15.9k
  
return false0
;
95
15.9k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Thumb1FrameLowering.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Line
Count
Source
90
14
                                         const MCPhysReg *CSRegs) {
91
250
  for (unsigned i = 0; CSRegs[i]; 
++i236
)
92
236
    if (Reg == CSRegs[i])
93
0
      return true;
94
14
  return false;
95
14
}
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isCalleeSavedRegister(unsigned int, unsigned short const*)
96
97
class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
98
protected:
99
  /// BasePtr - ARM physical register used as a base ptr in complex stack
100
  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
101
  /// variable size stack objects.
102
  unsigned BasePtr = ARM::R6;
103
104
  // Can be only subclassed.
105
  explicit ARMBaseRegisterInfo();
106
107
  // Return the opcode that implements 'Op', or 0 if no opcode
108
  unsigned getOpcode(int Op) const;
109
110
public:
111
  /// Code Generation virtual methods...
112
  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
113
  const MCPhysReg *
114
  getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
115
  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
116
                                       CallingConv::ID) const override;
117
  const uint32_t *getNoPreservedMask() const override;
118
  const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
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  const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
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  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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  /// case that 'returned' is on an i32 first argument if the calling convention
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  /// is one that can (partially) model this attribute with a preserved mask
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  /// (i.e. it is a calling convention that uses the same register for the first
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  /// i32 argument and an i32 return value)
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  ///
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  /// Should return NULL in the case that the calling convention does not have
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  /// this property
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  const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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                                             CallingConv::ID) const;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  bool isAsmClobberable(const MachineFunction &MF,
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                       unsigned PhysReg) const override;
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  const TargetRegisterClass *
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  getPointerRegClass(const MachineFunction &MF,
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                     unsigned Kind = 0) const override;
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  const TargetRegisterClass *
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  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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  const TargetRegisterClass *
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  getLargestLegalSuperClass(const TargetRegisterClass *RC,
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                            const MachineFunction &MF) const override;
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  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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                               MachineFunction &MF) const override;
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  bool getRegAllocationHints(unsigned VirtReg,
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                             ArrayRef<MCPhysReg> Order,
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                             SmallVectorImpl<MCPhysReg> &Hints,
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                             const MachineFunction &MF,
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                             const VirtRegMap *VRM,
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                             const LiveRegMatrix *Matrix) const override;
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  void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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                          MachineFunction &MF) const override;
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  bool hasBasePointer(const MachineFunction &MF) const;
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  bool canRealignStack(const MachineFunction &MF) const override;
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  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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                                   int Idx) const override;
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  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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                                    unsigned BaseReg, int FrameIdx,
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                                    int64_t Offset) const override;
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  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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                         int64_t Offset) const override;
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  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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                          int64_t Offset) const override;
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  bool cannotEliminateFrame(const MachineFunction &MF) const;
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  // Debug information queries.
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  Register getFrameRegister(const MachineFunction &MF) const override;
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2.13k
  unsigned getBaseRegister() const { return BasePtr; }
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  bool isLowRegister(unsigned Reg) const;
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  /// emitLoadConstPool - Emits a load from constpool to materialize the
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  /// specified immediate.
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  virtual void
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  emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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                    const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
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                    int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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                    unsigned PredReg = 0,
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                    unsigned MIFlags = MachineInstr::NoFlags) const;
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  /// Code Generation virtual methods...
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  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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  void eliminateFrameIndex(MachineBasicBlock::iterator II,
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                           int SPAdj, unsigned FIOperandNum,
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                           RegScavenger *RS = nullptr) const override;
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  /// SrcRC and DstRC will be morphed into NewRC if this returns true
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  bool shouldCoalesce(MachineInstr *MI,
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                      const TargetRegisterClass *SrcRC,
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                      unsigned SubReg,
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                      const TargetRegisterClass *DstRC,
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                      unsigned DstSubReg,
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                      const TargetRegisterClass *NewRC,
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                      LiveIntervals &LIS) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H