/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMCallingConv.cpp
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1 | | //=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains the custom routines for the ARM Calling Convention that |
10 | | // aren't done by tablegen, and includes the table generated implementations. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "ARM.h" |
15 | | #include "ARMCallingConv.h" |
16 | | #include "ARMSubtarget.h" |
17 | | #include "ARMRegisterInfo.h" |
18 | | using namespace llvm; |
19 | | |
20 | | // APCS f64 is in register pairs, possibly split to stack |
21 | | static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
22 | | CCValAssign::LocInfo &LocInfo, |
23 | 1.12k | CCState &State, bool CanFail) { |
24 | 1.12k | static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
25 | 1.12k | |
26 | 1.12k | // Try to get the first register. |
27 | 1.12k | if (unsigned Reg = State.AllocateReg(RegList)) |
28 | 618 | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
29 | 503 | else { |
30 | 503 | // For the 2nd half of a v2f64, do not fail. |
31 | 503 | if (CanFail) |
32 | 498 | return false; |
33 | 5 | |
34 | 5 | // Put the whole thing on the stack. |
35 | 5 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, |
36 | 5 | State.AllocateStack(8, 4), |
37 | 5 | LocVT, LocInfo)); |
38 | 5 | return true; |
39 | 5 | } |
40 | 618 | |
41 | 618 | // Try to get the second register. |
42 | 618 | if (unsigned Reg = State.AllocateReg(RegList)) |
43 | 578 | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
44 | 40 | else |
45 | 40 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, |
46 | 40 | State.AllocateStack(4, 4), |
47 | 40 | LocVT, LocInfo)); |
48 | 618 | return true; |
49 | 618 | } |
50 | | |
51 | | static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
52 | | CCValAssign::LocInfo &LocInfo, |
53 | | ISD::ArgFlagsTy &ArgFlags, |
54 | 1.03k | CCState &State) { |
55 | 1.03k | if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) |
56 | 498 | return false; |
57 | 539 | if (LocVT == MVT::v2f64 && |
58 | 539 | !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)84 ) |
59 | 0 | return false; |
60 | 539 | return true; // we handled it |
61 | 539 | } |
62 | | |
63 | | // AAPCS f64 is in aligned register pairs |
64 | | static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
65 | | CCValAssign::LocInfo &LocInfo, |
66 | 2.57k | CCState &State, bool CanFail) { |
67 | 2.57k | static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; |
68 | 2.57k | static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; |
69 | 2.57k | static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; |
70 | 2.57k | static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
71 | 2.57k | |
72 | 2.57k | unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); |
73 | 2.57k | if (Reg == 0) { |
74 | 565 | |
75 | 565 | // If we had R3 unallocated only, now we still must to waste it. |
76 | 565 | Reg = State.AllocateReg(GPRArgRegs); |
77 | 565 | assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); |
78 | 565 | |
79 | 565 | // For the 2nd half of a v2f64, do not just fail. |
80 | 565 | if (CanFail) |
81 | 546 | return false; |
82 | 19 | |
83 | 19 | // Put the whole thing on the stack. |
84 | 19 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, |
85 | 19 | State.AllocateStack(8, 8), |
86 | 19 | LocVT, LocInfo)); |
87 | 19 | return true; |
88 | 19 | } |
89 | 2.01k | |
90 | 2.01k | unsigned i; |
91 | 2.84k | for (i = 0; i < 2; ++i838 ) |
92 | 2.84k | if (HiRegList[i] == Reg) |
93 | 2.01k | break; |
94 | 2.01k | |
95 | 2.01k | unsigned T = State.AllocateReg(LoRegList[i]); |
96 | 2.01k | (void)T; |
97 | 2.01k | assert(T == LoRegList[i] && "Could not allocate register"); |
98 | 2.01k | |
99 | 2.01k | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
100 | 2.01k | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], |
101 | 2.01k | LocVT, LocInfo)); |
102 | 2.01k | return true; |
103 | 2.01k | } |
104 | | |
105 | | static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
106 | | CCValAssign::LocInfo &LocInfo, |
107 | | ISD::ArgFlagsTy &ArgFlags, |
108 | 2.29k | CCState &State) { |
109 | 2.29k | if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) |
110 | 546 | return false; |
111 | 1.75k | if (LocVT == MVT::v2f64 && |
112 | 1.75k | !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)280 ) |
113 | 0 | return false; |
114 | 1.75k | return true; // we handled it |
115 | 1.75k | } |
116 | | |
117 | | static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
118 | 6.94k | CCValAssign::LocInfo &LocInfo, CCState &State) { |
119 | 6.94k | static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; |
120 | 6.94k | static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; |
121 | 6.94k | |
122 | 6.94k | unsigned Reg = State.AllocateReg(HiRegList, LoRegList); |
123 | 6.94k | if (Reg == 0) |
124 | 61 | return false; // we didn't handle it |
125 | 6.88k | |
126 | 6.88k | unsigned i; |
127 | 8.75k | for (i = 0; i < 2; ++i1.86k ) |
128 | 8.75k | if (HiRegList[i] == Reg) |
129 | 6.88k | break; |
130 | 6.88k | |
131 | 6.88k | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
132 | 6.88k | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], |
133 | 6.88k | LocVT, LocInfo)); |
134 | 6.88k | return true; |
135 | 6.88k | } |
136 | | |
137 | | static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
138 | | CCValAssign::LocInfo &LocInfo, |
139 | | ISD::ArgFlagsTy &ArgFlags, |
140 | 5.12k | CCState &State) { |
141 | 5.12k | if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) |
142 | 61 | return false; |
143 | 5.05k | if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)1.82k ) |
144 | 0 | return false; |
145 | 5.05k | return true; // we handled it |
146 | 5.05k | } |
147 | | |
148 | | static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, |
149 | | CCValAssign::LocInfo &LocInfo, |
150 | | ISD::ArgFlagsTy &ArgFlags, |
151 | 4.46k | CCState &State) { |
152 | 4.46k | return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, |
153 | 4.46k | State); |
154 | 4.46k | } |
155 | | |
156 | | static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
157 | | |
158 | | static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, |
159 | | ARM::S4, ARM::S5, ARM::S6, ARM::S7, |
160 | | ARM::S8, ARM::S9, ARM::S10, ARM::S11, |
161 | | ARM::S12, ARM::S13, ARM::S14, ARM::S15 }; |
162 | | static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, |
163 | | ARM::D4, ARM::D5, ARM::D6, ARM::D7 }; |
164 | | static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 }; |
165 | | |
166 | | |
167 | | // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA |
168 | | // has InConsecutiveRegs set, and that the last member also has |
169 | | // InConsecutiveRegsLast set. We must process all members of the HA before |
170 | | // we can allocate it, as we need to know the total number of registers that |
171 | | // will be needed in order to (attempt to) allocate a contiguous block. |
172 | | static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, |
173 | | MVT &LocVT, |
174 | | CCValAssign::LocInfo &LocInfo, |
175 | | ISD::ArgFlagsTy &ArgFlags, |
176 | 6.00k | CCState &State) { |
177 | 6.00k | SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs(); |
178 | 6.00k | |
179 | 6.00k | // AAPCS HFAs must have 1-4 elements, all of the same type |
180 | 6.00k | if (PendingMembers.size() > 0) |
181 | 6.00k | assert(PendingMembers[0].getLocVT() == LocVT); |
182 | 6.00k | |
183 | 6.00k | // Add the argument to the list to be allocated once we know the size of the |
184 | 6.00k | // aggregate. Store the type's required alignmnent as extra info for later: in |
185 | 6.00k | // the [N x i64] case all trace has been removed by the time we actually get |
186 | 6.00k | // to do allocation. |
187 | 6.00k | PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo, |
188 | 6.00k | ArgFlags.getOrigAlign())); |
189 | 6.00k | |
190 | 6.00k | if (!ArgFlags.isInConsecutiveRegsLast()) |
191 | 478 | return true; |
192 | 5.52k | |
193 | 5.52k | // Try to allocate a contiguous block of registers, each of the correct |
194 | 5.52k | // size to hold one member. |
195 | 5.52k | auto &DL = State.getMachineFunction().getDataLayout(); |
196 | 5.52k | unsigned StackAlign = DL.getStackAlignment(); |
197 | 5.52k | unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign); |
198 | 5.52k | |
199 | 5.52k | ArrayRef<MCPhysReg> RegList; |
200 | 5.52k | switch (LocVT.SimpleTy) { |
201 | 5.52k | case MVT::i32: { |
202 | 189 | RegList = RRegList; |
203 | 189 | unsigned RegIdx = State.getFirstUnallocated(RegList); |
204 | 189 | |
205 | 189 | // First consume all registers that would give an unaligned object. Whether |
206 | 189 | // we go on stack or in regs, no-one will be using them in future. |
207 | 189 | unsigned RegAlign = alignTo(Align, 4) / 4; |
208 | 192 | while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()3 ) |
209 | 3 | State.AllocateReg(RegList[RegIdx++]); |
210 | 189 | |
211 | 189 | break; |
212 | 5.52k | } |
213 | 5.52k | case MVT::f16: |
214 | 1.88k | case MVT::f32: |
215 | 1.88k | RegList = SRegList; |
216 | 1.88k | break; |
217 | 2.36k | case MVT::v4f16: |
218 | 2.36k | case MVT::f64: |
219 | 2.36k | RegList = DRegList; |
220 | 2.36k | break; |
221 | 2.36k | case MVT::v8f16: |
222 | 1.08k | case MVT::v2f64: |
223 | 1.08k | RegList = QRegList; |
224 | 1.08k | break; |
225 | 1.08k | default: |
226 | 0 | llvm_unreachable("Unexpected member type for block aggregate"); |
227 | 1.08k | break0 ; |
228 | 5.52k | } |
229 | 5.52k | |
230 | 5.52k | unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); |
231 | 5.52k | if (RegResult) { |
232 | 5.36k | for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin(); |
233 | 11.0k | It != PendingMembers.end(); ++It5.64k ) { |
234 | 5.64k | It->convertToReg(RegResult); |
235 | 5.64k | State.addLoc(*It); |
236 | 5.64k | ++RegResult; |
237 | 5.64k | } |
238 | 5.36k | PendingMembers.clear(); |
239 | 5.36k | return true; |
240 | 5.36k | } |
241 | 164 | |
242 | 164 | // Register allocation failed, we'll be needing the stack |
243 | 164 | unsigned Size = LocVT.getSizeInBits() / 8; |
244 | 164 | if (LocVT == MVT::i32 && State.getNextStackOffset() == 091 ) { |
245 | 78 | // If nothing else has used the stack until this point, a non-HFA aggregate |
246 | 78 | // can be split between regs and stack. |
247 | 78 | unsigned RegIdx = State.getFirstUnallocated(RegList); |
248 | 225 | for (auto &It : PendingMembers) { |
249 | 225 | if (RegIdx >= RegList.size()) |
250 | 117 | It.convertToMem(State.AllocateStack(Size, Size)); |
251 | 108 | else |
252 | 108 | It.convertToReg(State.AllocateReg(RegList[RegIdx++])); |
253 | 225 | |
254 | 225 | State.addLoc(It); |
255 | 225 | } |
256 | 78 | PendingMembers.clear(); |
257 | 78 | return true; |
258 | 86 | } else if (LocVT != MVT::i32) |
259 | 73 | RegList = SRegList; |
260 | 164 | |
261 | 164 | // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) |
262 | 164 | for (auto Reg : RegList)86 |
263 | 1.22k | State.AllocateReg(Reg); |
264 | 86 | |
265 | 86 | // After the first item has been allocated, the rest are packed as tightly as |
266 | 86 | // possible. (E.g. an incoming i64 would have starting Align of 8, but we'll |
267 | 86 | // be allocating a bunch of i32 slots). |
268 | 86 | unsigned RestAlign = std::min(Align, Size); |
269 | 86 | |
270 | 136 | for (auto &It : PendingMembers) { |
271 | 136 | It.convertToMem(State.AllocateStack(Size, Align)); |
272 | 136 | State.addLoc(It); |
273 | 136 | Align = RestAlign; |
274 | 136 | } |
275 | 86 | |
276 | 86 | // All pending members have now been allocated |
277 | 86 | PendingMembers.clear(); |
278 | 86 | |
279 | 86 | // This will be allocated by the last member of the aggregate |
280 | 86 | return true; |
281 | 164 | } |
282 | | |
283 | | // Include the table generated calling convention implementations. |
284 | | #include "ARMGenCallingConv.inc" |