Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMCallingConv.cpp
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//=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the ARM Calling Convention that
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// aren't done by tablegen, and includes the table generated implementations.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMCallingConv.h"
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#include "ARMSubtarget.h"
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#include "ARMRegisterInfo.h"
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using namespace llvm;
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// APCS f64 is in register pairs, possibly split to stack
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static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                          CCValAssign::LocInfo &LocInfo,
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1.12k
                          CCState &State, bool CanFail) {
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1.12k
  static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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  // Try to get the first register.
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  if (unsigned Reg = State.AllocateReg(RegList))
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    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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  else {
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    // For the 2nd half of a v2f64, do not fail.
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    if (CanFail)
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      return false;
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    // Put the whole thing on the stack.
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    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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                                           State.AllocateStack(8, 4),
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                                           LocVT, LocInfo));
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    return true;
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  }
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  // Try to get the second register.
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  if (unsigned Reg = State.AllocateReg(RegList))
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    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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  else
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    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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                                           State.AllocateStack(4, 4),
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                                           LocVT, LocInfo));
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  return true;
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}
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static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                                   CCValAssign::LocInfo &LocInfo,
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                                   ISD::ArgFlagsTy &ArgFlags,
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1.03k
                                   CCState &State) {
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  if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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    return false;
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539
  if (LocVT == MVT::v2f64 &&
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!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)84
)
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0
    return false;
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  return true;  // we handled it
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}
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// AAPCS f64 is in aligned register pairs
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static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                           CCValAssign::LocInfo &LocInfo,
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2.57k
                           CCState &State, bool CanFail) {
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  static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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  static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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  static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
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  static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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  unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
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  if (Reg == 0) {
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    // If we had R3 unallocated only, now we still must to waste it.
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    Reg = State.AllocateReg(GPRArgRegs);
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    assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
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    // For the 2nd half of a v2f64, do not just fail.
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    if (CanFail)
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      return false;
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    // Put the whole thing on the stack.
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    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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                                           State.AllocateStack(8, 8),
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                                           LocVT, LocInfo));
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    return true;
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  }
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  unsigned i;
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  for (i = 0; i < 2; 
++i838
)
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    if (HiRegList[i] == Reg)
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      break;
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  unsigned T = State.AllocateReg(LoRegList[i]);
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  (void)T;
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  assert(T == LoRegList[i] && "Could not allocate register");
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  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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                                         LocVT, LocInfo));
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  return true;
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}
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static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                                    CCValAssign::LocInfo &LocInfo,
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                                    ISD::ArgFlagsTy &ArgFlags,
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                                    CCState &State) {
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  if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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    return false;
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  if (LocVT == MVT::v2f64 &&
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!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)280
)
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    return false;
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  return true;  // we handled it
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}
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static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                         CCValAssign::LocInfo &LocInfo, CCState &State) {
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  static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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  static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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  unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
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  if (Reg == 0)
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    return false; // we didn't handle it
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  unsigned i;
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  for (i = 0; i < 2; 
++i1.86k
)
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    if (HiRegList[i] == Reg)
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      break;
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  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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                                         LocVT, LocInfo));
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  return true;
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}
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static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                                      CCValAssign::LocInfo &LocInfo,
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                                      ISD::ArgFlagsTy &ArgFlags,
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                                      CCState &State) {
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  if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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    return false;
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  if (LocVT == MVT::v2f64 && 
!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)1.82k
)
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    return false;
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  return true;  // we handled it
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}
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static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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                                       CCValAssign::LocInfo &LocInfo,
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                                       ISD::ArgFlagsTy &ArgFlags,
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                                       CCState &State) {
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  return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
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                                   State);
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}
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static const MCPhysReg RRegList[] = { ARM::R0,  ARM::R1,  ARM::R2,  ARM::R3 };
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static const MCPhysReg SRegList[] = { ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
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                                      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
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                                      ARM::S8,  ARM::S9,  ARM::S10, ARM::S11,
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                                      ARM::S12, ARM::S13, ARM::S14,  ARM::S15 };
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static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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                                      ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
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// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
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// has InConsecutiveRegs set, and that the last member also has
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// InConsecutiveRegsLast set. We must process all members of the HA before
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// we can allocate it, as we need to know the total number of registers that
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// will be needed in order to (attempt to) allocate a contiguous block.
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static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT,
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                                          MVT &LocVT,
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                                          CCValAssign::LocInfo &LocInfo,
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                                          ISD::ArgFlagsTy &ArgFlags,
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6.00k
                                          CCState &State) {
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6.00k
  SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
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6.00k
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  // AAPCS HFAs must have 1-4 elements, all of the same type
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  if (PendingMembers.size() > 0)
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    assert(PendingMembers[0].getLocVT() == LocVT);
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  // Add the argument to the list to be allocated once we know the size of the
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  // aggregate. Store the type's required alignmnent as extra info for later: in
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  // the [N x i64] case all trace has been removed by the time we actually get
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  // to do allocation.
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  PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
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                                                   ArgFlags.getOrigAlign()));
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  if (!ArgFlags.isInConsecutiveRegsLast())
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    return true;
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5.52k
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  // Try to allocate a contiguous block of registers, each of the correct
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  // size to hold one member.
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  auto &DL = State.getMachineFunction().getDataLayout();
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  unsigned StackAlign = DL.getStackAlignment();
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  unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign);
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  ArrayRef<MCPhysReg> RegList;
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  switch (LocVT.SimpleTy) {
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  case MVT::i32: {
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    RegList = RRegList;
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    unsigned RegIdx = State.getFirstUnallocated(RegList);
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    // First consume all registers that would give an unaligned object. Whether
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    // we go on stack or in regs, no-one will be using them in future.
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    unsigned RegAlign = alignTo(Align, 4) / 4;
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    while (RegIdx % RegAlign != 0 && 
RegIdx < RegList.size()3
)
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3
      State.AllocateReg(RegList[RegIdx++]);
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    break;
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  }
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5.52k
  case MVT::f16:
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1.88k
  case MVT::f32:
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1.88k
    RegList = SRegList;
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    break;
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2.36k
  case MVT::v4f16:
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2.36k
  case MVT::f64:
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    RegList = DRegList;
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    break;
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  case MVT::v8f16:
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1.08k
  case MVT::v2f64:
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    RegList = QRegList;
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    break;
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  default:
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    llvm_unreachable("Unexpected member type for block aggregate");
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break0
;
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  }
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  unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
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  if (RegResult) {
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    for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
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11.0k
         It != PendingMembers.end(); 
++It5.64k
) {
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5.64k
      It->convertToReg(RegResult);
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      State.addLoc(*It);
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      ++RegResult;
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    }
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    PendingMembers.clear();
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    return true;
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  }
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  // Register allocation failed, we'll be needing the stack
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  unsigned Size = LocVT.getSizeInBits() / 8;
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  if (LocVT == MVT::i32 && 
State.getNextStackOffset() == 091
) {
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    // If nothing else has used the stack until this point, a non-HFA aggregate
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    // can be split between regs and stack.
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    unsigned RegIdx = State.getFirstUnallocated(RegList);
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    for (auto &It : PendingMembers) {
249
225
      if (RegIdx >= RegList.size())
250
117
        It.convertToMem(State.AllocateStack(Size, Size));
251
108
      else
252
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        It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
253
225
254
225
      State.addLoc(It);
255
225
    }
256
78
    PendingMembers.clear();
257
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    return true;
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86
  } else if (LocVT != MVT::i32)
259
73
    RegList = SRegList;
260
164
261
164
  // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core)
262
164
  
for (auto Reg : RegList)86
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1.22k
    State.AllocateReg(Reg);
264
86
265
86
  // After the first item has been allocated, the rest are packed as tightly as
266
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  // possible. (E.g. an incoming i64 would have starting Align of 8, but we'll
267
86
  // be allocating a bunch of i32 slots).
268
86
  unsigned RestAlign = std::min(Align, Size);
269
86
270
136
  for (auto &It : PendingMembers) {
271
136
    It.convertToMem(State.AllocateStack(Size, Align));
272
136
    State.addLoc(It);
273
136
    Align = RestAlign;
274
136
  }
275
86
276
86
  // All pending members have now been allocated
277
86
  PendingMembers.clear();
278
86
279
86
  // This will be allocated by the last member of the aggregate
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86
  return true;
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164
}
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// Include the table generated calling convention implementations.
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#include "ARMGenCallingConv.inc"