/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
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1 | | //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains small standalone helper functions and enum definitions for |
10 | | // the ARM target useful for the compiler back-end and the MC libraries. |
11 | | // As such, it deliberately does not include references to LLVM core |
12 | | // code gen types, passes, etc.. |
13 | | // |
14 | | //===----------------------------------------------------------------------===// |
15 | | |
16 | | #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H |
17 | | #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H |
18 | | |
19 | | #include "ARMMCTargetDesc.h" |
20 | | #include "llvm/Support/ErrorHandling.h" |
21 | | #include "Utils/ARMBaseInfo.h" |
22 | | |
23 | | namespace llvm { |
24 | | |
25 | | namespace ARM_PROC { |
26 | | enum IMod { |
27 | | IE = 2, |
28 | | ID = 3 |
29 | | }; |
30 | | |
31 | | enum IFlags { |
32 | | F = 1, |
33 | | I = 2, |
34 | | A = 4 |
35 | | }; |
36 | | |
37 | 70 | inline static const char *IFlagsToString(unsigned val) { |
38 | 70 | switch (val) { |
39 | 70 | default: 0 llvm_unreachable0 ("Unknown iflags operand"); |
40 | 70 | case F: return "f"33 ; |
41 | 70 | case I: return "i"21 ; |
42 | 70 | case A: return "a"16 ; |
43 | 70 | } |
44 | 70 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) ARMInstPrinter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Line | Count | Source | 37 | 70 | inline static const char *IFlagsToString(unsigned val) { | 38 | 70 | switch (val) { | 39 | 70 | default: 0 llvm_unreachable0 ("Unknown iflags operand"); | 40 | 70 | case F: return "f"33 ; | 41 | 70 | case I: return "i"21 ; | 42 | 70 | case A: return "a"16 ; | 43 | 70 | } | 44 | 70 | } |
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_PROC::IFlagsToString(unsigned int) |
45 | | |
46 | 51 | inline static const char *IModToString(unsigned val) { |
47 | 51 | switch (val) { |
48 | 51 | default: 0 llvm_unreachable0 ("Unknown imod operand"); |
49 | 51 | case IE: return "ie"35 ; |
50 | 51 | case ID: return "id"16 ; |
51 | 51 | } |
52 | 51 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_PROC::IModToString(unsigned int) ARMInstPrinter.cpp:llvm::ARM_PROC::IModToString(unsigned int) Line | Count | Source | 46 | 51 | inline static const char *IModToString(unsigned val) { | 47 | 51 | switch (val) { | 48 | 51 | default: 0 llvm_unreachable0 ("Unknown imod operand"); | 49 | 51 | case IE: return "ie"35 ; | 50 | 51 | case ID: return "id"16 ; | 51 | 51 | } | 52 | 51 | } |
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_PROC::IModToString(unsigned int) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_PROC::IModToString(unsigned int) |
53 | | } |
54 | | |
55 | | namespace ARM_MB { |
56 | | // The Memory Barrier Option constants map directly to the 4-bit encoding of |
57 | | // the option field for memory barrier operations. |
58 | | enum MemBOpt { |
59 | | RESERVED_0 = 0, |
60 | | OSHLD = 1, |
61 | | OSHST = 2, |
62 | | OSH = 3, |
63 | | RESERVED_4 = 4, |
64 | | NSHLD = 5, |
65 | | NSHST = 6, |
66 | | NSH = 7, |
67 | | RESERVED_8 = 8, |
68 | | ISHLD = 9, |
69 | | ISHST = 10, |
70 | | ISH = 11, |
71 | | RESERVED_12 = 12, |
72 | | LD = 13, |
73 | | ST = 14, |
74 | | SY = 15 |
75 | | }; |
76 | | |
77 | 612 | inline static const char *MemBOptToString(unsigned val, bool HasV8) { |
78 | 612 | switch (val) { |
79 | 612 | default: 0 llvm_unreachable0 ("Unknown memory operation"); |
80 | 612 | case SY: return "sy"92 ; |
81 | 612 | case ST: return "st"21 ; |
82 | 612 | case LD: return HasV8 19 ? "ld"7 : "#0xd"12 ; |
83 | 612 | case RESERVED_12: return "#0xc"14 ; |
84 | 612 | case ISH: return "ish"243 ; |
85 | 612 | case ISHST: return "ishst"33 ; |
86 | 612 | case ISHLD: return HasV8 20 ? "ishld"7 : "#0x9"13 ; |
87 | 612 | case RESERVED_8: return "#0x8"14 ; |
88 | 612 | case NSH: return "nsh"34 ; |
89 | 612 | case NSHST: return "nshst"29 ; |
90 | 612 | case NSHLD: return HasV8 18 ? "nshld"6 : "#0x5"12 ; |
91 | 612 | case RESERVED_4: return "#0x4"6 ; |
92 | 612 | case OSH: return "osh"23 ; |
93 | 612 | case OSHST: return "oshst"22 ; |
94 | 612 | case OSHLD: return HasV8 18 ? "oshld"6 : "#0x1"12 ; |
95 | 612 | case RESERVED_0: return "#0x0"6 ; |
96 | 612 | } |
97 | 612 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) ARMInstPrinter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Line | Count | Source | 77 | 612 | inline static const char *MemBOptToString(unsigned val, bool HasV8) { | 78 | 612 | switch (val) { | 79 | 612 | default: 0 llvm_unreachable0 ("Unknown memory operation"); | 80 | 612 | case SY: return "sy"92 ; | 81 | 612 | case ST: return "st"21 ; | 82 | 612 | case LD: return HasV8 19 ? "ld"7 : "#0xd"12 ; | 83 | 612 | case RESERVED_12: return "#0xc"14 ; | 84 | 612 | case ISH: return "ish"243 ; | 85 | 612 | case ISHST: return "ishst"33 ; | 86 | 612 | case ISHLD: return HasV8 20 ? "ishld"7 : "#0x9"13 ; | 87 | 612 | case RESERVED_8: return "#0x8"14 ; | 88 | 612 | case NSH: return "nsh"34 ; | 89 | 612 | case NSHST: return "nshst"29 ; | 90 | 612 | case NSHLD: return HasV8 18 ? "nshld"6 : "#0x5"12 ; | 91 | 612 | case RESERVED_4: return "#0x4"6 ; | 92 | 612 | case OSH: return "osh"23 ; | 93 | 612 | case OSHST: return "oshst"22 ; | 94 | 612 | case OSHLD: return HasV8 18 ? "oshld"6 : "#0x1"12 ; | 95 | 612 | case RESERVED_0: return "#0x0"6 ; | 96 | 612 | } | 97 | 612 | } |
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_MB::MemBOptToString(unsigned int, bool) |
98 | | } // namespace ARM_MB |
99 | | |
100 | | namespace ARM_TSB { |
101 | | enum TraceSyncBOpt { |
102 | | CSYNC = 0 |
103 | | }; |
104 | | |
105 | 0 | inline static const char *TraceSyncBOptToString(unsigned val) { |
106 | 0 | switch (val) { |
107 | 0 | default: |
108 | 0 | llvm_unreachable("Unknown trace synchronization barrier operation"); |
109 | 0 | case CSYNC: return "csync"; |
110 | 0 | } |
111 | 0 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMInstPrinter.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_TSB::TraceSyncBOptToString(unsigned int) |
112 | | } // namespace ARM_TSB |
113 | | |
114 | | namespace ARM_ISB { |
115 | | enum InstSyncBOpt { |
116 | | RESERVED_0 = 0, |
117 | | RESERVED_1 = 1, |
118 | | RESERVED_2 = 2, |
119 | | RESERVED_3 = 3, |
120 | | RESERVED_4 = 4, |
121 | | RESERVED_5 = 5, |
122 | | RESERVED_6 = 6, |
123 | | RESERVED_7 = 7, |
124 | | RESERVED_8 = 8, |
125 | | RESERVED_9 = 9, |
126 | | RESERVED_10 = 10, |
127 | | RESERVED_11 = 11, |
128 | | RESERVED_12 = 12, |
129 | | RESERVED_13 = 13, |
130 | | RESERVED_14 = 14, |
131 | | SY = 15 |
132 | | }; |
133 | | |
134 | 36 | inline static const char *InstSyncBOptToString(unsigned val) { |
135 | 36 | switch (val) { |
136 | 36 | default: |
137 | 0 | llvm_unreachable("Unknown memory operation"); |
138 | 36 | case RESERVED_0: return "#0x0"0 ; |
139 | 36 | case RESERVED_1: return "#0x1"4 ; |
140 | 36 | case RESERVED_2: return "#0x2"0 ; |
141 | 36 | case RESERVED_3: return "#0x3"0 ; |
142 | 36 | case RESERVED_4: return "#0x4"0 ; |
143 | 36 | case RESERVED_5: return "#0x5"0 ; |
144 | 36 | case RESERVED_6: return "#0x6"0 ; |
145 | 36 | case RESERVED_7: return "#0x7"0 ; |
146 | 36 | case RESERVED_8: return "#0x8"0 ; |
147 | 36 | case RESERVED_9: return "#0x9"0 ; |
148 | 36 | case RESERVED_10: return "#0xa"2 ; |
149 | 36 | case RESERVED_11: return "#0xb"0 ; |
150 | 36 | case RESERVED_12: return "#0xc"0 ; |
151 | 36 | case RESERVED_13: return "#0xd"0 ; |
152 | 36 | case RESERVED_14: return "#0xe"0 ; |
153 | 36 | case SY: return "sy"30 ; |
154 | 36 | } |
155 | 36 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) ARMInstPrinter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Line | Count | Source | 134 | 36 | inline static const char *InstSyncBOptToString(unsigned val) { | 135 | 36 | switch (val) { | 136 | 36 | default: | 137 | 0 | llvm_unreachable("Unknown memory operation"); | 138 | 36 | case RESERVED_0: return "#0x0"0 ; | 139 | 36 | case RESERVED_1: return "#0x1"4 ; | 140 | 36 | case RESERVED_2: return "#0x2"0 ; | 141 | 36 | case RESERVED_3: return "#0x3"0 ; | 142 | 36 | case RESERVED_4: return "#0x4"0 ; | 143 | 36 | case RESERVED_5: return "#0x5"0 ; | 144 | 36 | case RESERVED_6: return "#0x6"0 ; | 145 | 36 | case RESERVED_7: return "#0x7"0 ; | 146 | 36 | case RESERVED_8: return "#0x8"0 ; | 147 | 36 | case RESERVED_9: return "#0x9"0 ; | 148 | 36 | case RESERVED_10: return "#0xa"2 ; | 149 | 36 | case RESERVED_11: return "#0xb"0 ; | 150 | 36 | case RESERVED_12: return "#0xc"0 ; | 151 | 36 | case RESERVED_13: return "#0xd"0 ; | 152 | 36 | case RESERVED_14: return "#0xe"0 ; | 153 | 36 | case SY: return "sy"30 ; | 154 | 36 | } | 155 | 36 | } |
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARM_ISB::InstSyncBOptToString(unsigned int) |
156 | | } // namespace ARM_ISB |
157 | | |
158 | | /// isARMLowRegister - Returns true if the register is a low register (r0-r7). |
159 | | /// |
160 | 446k | static inline bool isARMLowRegister(unsigned Reg) { |
161 | 446k | using namespace ARM; |
162 | 446k | switch (Reg) { |
163 | 446k | case R0: 396k case R1: 396k case R2: 396k case R3: |
164 | 396k | case R4: case R5: case R6: case R7: |
165 | 396k | return true; |
166 | 396k | default: |
167 | 50.1k | return false; |
168 | 446k | } |
169 | 446k | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isARMLowRegister(unsigned int) ARMBaseInstrInfo.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 12.6k | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 12.6k | using namespace ARM; | 162 | 12.6k | switch (Reg) { | 163 | 12.6k | case R0: 11.9k case R1: 11.9k case R2: 11.9k case R3: | 164 | 11.9k | case R4: case R5: case R6: case R7: | 165 | 11.9k | return true; | 166 | 11.9k | default: | 167 | 736 | return false; | 168 | 12.6k | } | 169 | 12.6k | } |
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMCallingConv.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMCallLowering.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isARMLowRegister(unsigned int) ARMConstantIslandPass.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 375 | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 375 | using namespace ARM; | 162 | 375 | switch (Reg) { | 163 | 375 | case R0: 366 case R1: 366 case R2: 366 case R3: | 164 | 366 | case R4: case R5: case R6: case R7: | 165 | 366 | return true; | 166 | 366 | default: | 167 | 9 | return false; | 168 | 375 | } | 169 | 375 | } |
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMFastISel.cpp:llvm::isARMLowRegister(unsigned int) ARMFrameLowering.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 5.22k | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 5.22k | using namespace ARM; | 162 | 5.22k | switch (Reg) { | 163 | 5.22k | case R0: 1.63k case R1: 1.63k case R2: 1.63k case R3: | 164 | 1.63k | case R4: case R5: case R6: case R7: | 165 | 1.63k | return true; | 166 | 3.59k | default: | 167 | 3.59k | return false; | 168 | 5.22k | } | 169 | 5.22k | } |
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMISelLowering.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isARMLowRegister(unsigned int) ARMLoadStoreOptimizer.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 18 | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 18 | using namespace ARM; | 162 | 18 | switch (Reg) { | 163 | 18 | case R0: case R1: case R2: case R3: | 164 | 18 | case R4: case R5: case R6: case R7: | 165 | 18 | return true; | 166 | 18 | default: | 167 | 0 | return false; | 168 | 18 | } | 169 | 18 | } |
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMSubtarget.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isARMLowRegister(unsigned int) Thumb1FrameLowering.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 2.45k | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 2.45k | using namespace ARM; | 162 | 2.45k | switch (Reg) { | 163 | 2.45k | case R0: 1.26k case R1: 1.26k case R2: 1.26k case R3: | 164 | 1.26k | case R4: case R5: case R6: case R7: | 165 | 1.26k | return true; | 166 | 1.26k | default: | 167 | 1.19k | return false; | 168 | 2.45k | } | 169 | 2.45k | } |
ThumbRegisterInfo.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 598 | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 598 | using namespace ARM; | 162 | 598 | switch (Reg) { | 163 | 598 | case R0: 556 case R1: 556 case R2: 556 case R3: | 164 | 556 | case R4: case R5: case R6: case R7: | 165 | 556 | return true; | 166 | 556 | default: | 167 | 42 | return false; | 168 | 598 | } | 169 | 598 | } |
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isARMLowRegister(unsigned int) Thumb2SizeReduction.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 417k | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 417k | using namespace ARM; | 162 | 417k | switch (Reg) { | 163 | 417k | case R0: 374k case R1: 374k case R2: 374k case R3: | 164 | 374k | case R4: case R5: case R6: case R7: | 165 | 374k | return true; | 166 | 374k | default: | 167 | 42.9k | return false; | 168 | 417k | } | 169 | 417k | } |
ARMAsmParser.cpp:llvm::isARMLowRegister(unsigned int) Line | Count | Source | 160 | 7.35k | static inline bool isARMLowRegister(unsigned Reg) { | 161 | 7.35k | using namespace ARM; | 162 | 7.35k | switch (Reg) { | 163 | 7.35k | case R0: 5.71k case R1: 5.71k case R2: 5.71k case R3: | 164 | 5.71k | case R4: case R5: case R6: case R7: | 165 | 5.71k | return true; | 166 | 5.71k | default: | 167 | 1.64k | return false; | 168 | 7.35k | } | 169 | 7.35k | } |
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMInstPrinter.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::isARMLowRegister(unsigned int) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::isARMLowRegister(unsigned int) |
170 | | |
171 | | /// ARMII - This namespace holds all of the target specific flags that |
172 | | /// instruction info tracks. |
173 | | /// |
174 | | namespace ARMII { |
175 | | |
176 | | /// ARM Index Modes |
177 | | enum IndexMode { |
178 | | IndexModeNone = 0, |
179 | | IndexModePre = 1, |
180 | | IndexModePost = 2, |
181 | | IndexModeUpd = 3 |
182 | | }; |
183 | | |
184 | | /// ARM Addressing Modes |
185 | | enum AddrMode { |
186 | | AddrModeNone = 0, |
187 | | AddrMode1 = 1, |
188 | | AddrMode2 = 2, |
189 | | AddrMode3 = 3, |
190 | | AddrMode4 = 4, |
191 | | AddrMode5 = 5, |
192 | | AddrMode6 = 6, |
193 | | AddrModeT1_1 = 7, |
194 | | AddrModeT1_2 = 8, |
195 | | AddrModeT1_4 = 9, |
196 | | AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data |
197 | | AddrModeT2_i12 = 11, |
198 | | AddrModeT2_i8 = 12, |
199 | | AddrModeT2_so = 13, |
200 | | AddrModeT2_pc = 14, // +/- i12 for pc relative data |
201 | | AddrModeT2_i8s4 = 15, // i8 * 4 |
202 | | AddrMode_i12 = 16, |
203 | | AddrMode5FP16 = 17, // i8 * 2 |
204 | | AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst |
205 | | AddrModeT2_i7s4 = 19, // i7 * 4 |
206 | | AddrModeT2_i7s2 = 20, // i7 * 2 |
207 | | AddrModeT2_i7 = 21, // i7 * 1 |
208 | | }; |
209 | | |
210 | 0 | inline static const char *AddrModeToString(AddrMode addrmode) { |
211 | 0 | switch (addrmode) { |
212 | 0 | case AddrModeNone: return "AddrModeNone"; |
213 | 0 | case AddrMode1: return "AddrMode1"; |
214 | 0 | case AddrMode2: return "AddrMode2"; |
215 | 0 | case AddrMode3: return "AddrMode3"; |
216 | 0 | case AddrMode4: return "AddrMode4"; |
217 | 0 | case AddrMode5: return "AddrMode5"; |
218 | 0 | case AddrMode5FP16: return "AddrMode5FP16"; |
219 | 0 | case AddrMode6: return "AddrMode6"; |
220 | 0 | case AddrModeT1_1: return "AddrModeT1_1"; |
221 | 0 | case AddrModeT1_2: return "AddrModeT1_2"; |
222 | 0 | case AddrModeT1_4: return "AddrModeT1_4"; |
223 | 0 | case AddrModeT1_s: return "AddrModeT1_s"; |
224 | 0 | case AddrModeT2_i12: return "AddrModeT2_i12"; |
225 | 0 | case AddrModeT2_i8: return "AddrModeT2_i8"; |
226 | 0 | case AddrModeT2_so: return "AddrModeT2_so"; |
227 | 0 | case AddrModeT2_pc: return "AddrModeT2_pc"; |
228 | 0 | case AddrModeT2_i8s4: return "AddrModeT2_i8s4"; |
229 | 0 | case AddrMode_i12: return "AddrMode_i12"; |
230 | 0 | case AddrModeT2_ldrex:return "AddrModeT2_ldrex"; |
231 | 0 | case AddrModeT2_i7s4: return "AddrModeT2_i7s4"; |
232 | 0 | case AddrModeT2_i7s2: return "AddrModeT2_i7s2"; |
233 | 0 | case AddrModeT2_i7: return "AddrModeT2_i7"; |
234 | 0 | } |
235 | 0 | } Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMInstPrinter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMII::AddrModeToString(llvm::ARMII::AddrMode) |
236 | | |
237 | | /// Target Operand Flag enum. |
238 | | enum TOF { |
239 | | //===------------------------------------------------------------------===// |
240 | | // ARM Specific MachineOperand flags. |
241 | | |
242 | | MO_NO_FLAG = 0, |
243 | | |
244 | | /// MO_LO16 - On a symbol operand, this represents a relocation containing |
245 | | /// lower 16 bit of the address. Used only via movw instruction. |
246 | | MO_LO16 = 0x1, |
247 | | |
248 | | /// MO_HI16 - On a symbol operand, this represents a relocation containing |
249 | | /// higher 16 bit of the address. Used only via movt instruction. |
250 | | MO_HI16 = 0x2, |
251 | | |
252 | | /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects |
253 | | /// just that part of the flag set. |
254 | | MO_OPTION_MASK = 0x3, |
255 | | |
256 | | /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the |
257 | | /// reference is actually to the ".refptrp.FOO" symbol. This is used for |
258 | | /// stub symbols on windows. |
259 | | MO_COFFSTUB = 0x4, |
260 | | |
261 | | /// MO_GOT - On a symbol operand, this represents a GOT relative relocation. |
262 | | MO_GOT = 0x8, |
263 | | |
264 | | /// MO_SBREL - On a symbol operand, this represents a static base relative |
265 | | /// relocation. Used in movw and movt instructions. |
266 | | MO_SBREL = 0x10, |
267 | | |
268 | | /// MO_DLLIMPORT - On a symbol operand, this represents that the reference |
269 | | /// to the symbol is for an import stub. This is used for DLL import |
270 | | /// storage class indication on Windows. |
271 | | MO_DLLIMPORT = 0x20, |
272 | | |
273 | | /// MO_SECREL - On a symbol operand this indicates that the immediate is |
274 | | /// the offset from beginning of section. |
275 | | /// |
276 | | /// This is the TLS offset for the COFF/Windows TLS mechanism. |
277 | | MO_SECREL = 0x40, |
278 | | |
279 | | /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it |
280 | | /// represents a symbol which, if indirect, will get special Darwin mangling |
281 | | /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be |
282 | | /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for |
283 | | /// example). |
284 | | MO_NONLAZY = 0x80, |
285 | | |
286 | | // It's undefined behaviour if an enum overflows the range between its |
287 | | // smallest and largest values, but since these are |ed together, it can |
288 | | // happen. Put a sentinel in (values of this enum are stored as "unsigned |
289 | | // char"). |
290 | | MO_UNUSED_MAXIMUM = 0xff |
291 | | }; |
292 | | |
293 | | enum { |
294 | | //===------------------------------------------------------------------===// |
295 | | // Instruction Flags. |
296 | | |
297 | | //===------------------------------------------------------------------===// |
298 | | // This four-bit field describes the addressing mode used. |
299 | | AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h |
300 | | |
301 | | // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load |
302 | | // and store ops only. Generic "updating" flag is used for ld/st multiple. |
303 | | // The index mode enums are declared in ARMBaseInfo.h |
304 | | IndexModeShift = 5, |
305 | | IndexModeMask = 3 << IndexModeShift, |
306 | | |
307 | | //===------------------------------------------------------------------===// |
308 | | // Instruction encoding formats. |
309 | | // |
310 | | FormShift = 7, |
311 | | FormMask = 0x3f << FormShift, |
312 | | |
313 | | // Pseudo instructions |
314 | | Pseudo = 0 << FormShift, |
315 | | |
316 | | // Multiply instructions |
317 | | MulFrm = 1 << FormShift, |
318 | | |
319 | | // Branch instructions |
320 | | BrFrm = 2 << FormShift, |
321 | | BrMiscFrm = 3 << FormShift, |
322 | | |
323 | | // Data Processing instructions |
324 | | DPFrm = 4 << FormShift, |
325 | | DPSoRegFrm = 5 << FormShift, |
326 | | |
327 | | // Load and Store |
328 | | LdFrm = 6 << FormShift, |
329 | | StFrm = 7 << FormShift, |
330 | | LdMiscFrm = 8 << FormShift, |
331 | | StMiscFrm = 9 << FormShift, |
332 | | LdStMulFrm = 10 << FormShift, |
333 | | |
334 | | LdStExFrm = 11 << FormShift, |
335 | | |
336 | | // Miscellaneous arithmetic instructions |
337 | | ArithMiscFrm = 12 << FormShift, |
338 | | SatFrm = 13 << FormShift, |
339 | | |
340 | | // Extend instructions |
341 | | ExtFrm = 14 << FormShift, |
342 | | |
343 | | // VFP formats |
344 | | VFPUnaryFrm = 15 << FormShift, |
345 | | VFPBinaryFrm = 16 << FormShift, |
346 | | VFPConv1Frm = 17 << FormShift, |
347 | | VFPConv2Frm = 18 << FormShift, |
348 | | VFPConv3Frm = 19 << FormShift, |
349 | | VFPConv4Frm = 20 << FormShift, |
350 | | VFPConv5Frm = 21 << FormShift, |
351 | | VFPLdStFrm = 22 << FormShift, |
352 | | VFPLdStMulFrm = 23 << FormShift, |
353 | | VFPMiscFrm = 24 << FormShift, |
354 | | |
355 | | // Thumb format |
356 | | ThumbFrm = 25 << FormShift, |
357 | | |
358 | | // Miscelleaneous format |
359 | | MiscFrm = 26 << FormShift, |
360 | | |
361 | | // NEON formats |
362 | | NGetLnFrm = 27 << FormShift, |
363 | | NSetLnFrm = 28 << FormShift, |
364 | | NDupFrm = 29 << FormShift, |
365 | | NLdStFrm = 30 << FormShift, |
366 | | N1RegModImmFrm= 31 << FormShift, |
367 | | N2RegFrm = 32 << FormShift, |
368 | | NVCVTFrm = 33 << FormShift, |
369 | | NVDupLnFrm = 34 << FormShift, |
370 | | N2RegVShLFrm = 35 << FormShift, |
371 | | N2RegVShRFrm = 36 << FormShift, |
372 | | N3RegFrm = 37 << FormShift, |
373 | | N3RegVShFrm = 38 << FormShift, |
374 | | NVExtFrm = 39 << FormShift, |
375 | | NVMulSLFrm = 40 << FormShift, |
376 | | NVTBLFrm = 41 << FormShift, |
377 | | N3RegCplxFrm = 43 << FormShift, |
378 | | |
379 | | //===------------------------------------------------------------------===// |
380 | | // Misc flags. |
381 | | |
382 | | // UnaryDP - Indicates this is a unary data processing instruction, i.e. |
383 | | // it doesn't have a Rn operand. |
384 | | UnaryDP = 1 << 13, |
385 | | |
386 | | // Xform16Bit - Indicates this Thumb2 instruction may be transformed into |
387 | | // a 16-bit Thumb instruction if certain conditions are met. |
388 | | Xform16Bit = 1 << 14, |
389 | | |
390 | | // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb |
391 | | // instruction. Used by the parser to determine whether to require the 'S' |
392 | | // suffix on the mnemonic (when not in an IT block) or preclude it (when |
393 | | // in an IT block). |
394 | | ThumbArithFlagSetting = 1 << 19, |
395 | | |
396 | | //===------------------------------------------------------------------===// |
397 | | // Code domain. |
398 | | DomainShift = 15, |
399 | | DomainMask = 15 << DomainShift, |
400 | | DomainGeneral = 0 << DomainShift, |
401 | | DomainVFP = 1 << DomainShift, |
402 | | DomainNEON = 2 << DomainShift, |
403 | | DomainNEONA8 = 4 << DomainShift, |
404 | | DomainMVE = 8 << DomainShift, |
405 | | |
406 | | //===------------------------------------------------------------------===// |
407 | | // Field shifts - such shifts are used to set field while generating |
408 | | // machine instructions. |
409 | | // |
410 | | // FIXME: This list will need adjusting/fixing as the MC code emitter |
411 | | // takes shape and the ARMCodeEmitter.cpp bits go away. |
412 | | ShiftTypeShift = 4, |
413 | | |
414 | | M_BitShift = 5, |
415 | | ShiftImmShift = 5, |
416 | | ShiftShift = 7, |
417 | | N_BitShift = 7, |
418 | | ImmHiShift = 8, |
419 | | SoRotImmShift = 8, |
420 | | RegRsShift = 8, |
421 | | ExtRotImmShift = 10, |
422 | | RegRdLoShift = 12, |
423 | | RegRdShift = 12, |
424 | | RegRdHiShift = 16, |
425 | | RegRnShift = 16, |
426 | | S_BitShift = 20, |
427 | | W_BitShift = 21, |
428 | | AM3_I_BitShift = 22, |
429 | | D_BitShift = 22, |
430 | | U_BitShift = 23, |
431 | | P_BitShift = 24, |
432 | | I_BitShift = 25, |
433 | | CondShift = 28 |
434 | | }; |
435 | | |
436 | | } // end namespace ARMII |
437 | | |
438 | | } // end namespace llvm; |
439 | | |
440 | | #endif |