Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/RDFRegisters.cpp
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Count
Source (jump to first uncovered line)
1
//===- RDFRegisters.cpp ---------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
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9
#include "RDFRegisters.h"
10
#include "llvm/ADT/BitVector.h"
11
#include "llvm/CodeGen/MachineFunction.h"
12
#include "llvm/CodeGen/MachineInstr.h"
13
#include "llvm/CodeGen/MachineOperand.h"
14
#include "llvm/CodeGen/TargetRegisterInfo.h"
15
#include "llvm/MC/LaneBitmask.h"
16
#include "llvm/MC/MCRegisterInfo.h"
17
#include "llvm/Support/ErrorHandling.h"
18
#include "llvm/Support/raw_ostream.h"
19
#include <cassert>
20
#include <cstdint>
21
#include <set>
22
#include <utility>
23
24
using namespace llvm;
25
using namespace rdf;
26
27
PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
28
      const MachineFunction &mf)
29
6.69k
    : TRI(tri) {
30
6.69k
  RegInfos.resize(TRI.getNumRegs());
31
6.69k
32
6.69k
  BitVector BadRC(TRI.getNumRegs());
33
167k
  for (const TargetRegisterClass *RC : TRI.regclasses()) {
34
1.73M
    for (MCPhysReg R : *RC) {
35
1.73M
      RegInfo &RI = RegInfos[R];
36
1.73M
      if (RI.RegClass != nullptr && 
!BadRC[R]381k
) {
37
381k
        if (RC->LaneMask != RI.RegClass->LaneMask) {
38
53.5k
          BadRC.set(R);
39
53.5k
          RI.RegClass = nullptr;
40
53.5k
        }
41
381k
      } else
42
1.35M
        RI.RegClass = RC;
43
1.73M
    }
44
167k
  }
45
6.69k
46
6.69k
  UnitInfos.resize(TRI.getNumRegUnits());
47
6.69k
48
857k
  for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; 
++U850k
) {
49
850k
    if (UnitInfos[U].Reg != 0)
50
0
      continue;
51
850k
    MCRegUnitRootIterator R(U, &TRI);
52
850k
    assert(R.isValid());
53
850k
    RegisterId F = *R;
54
850k
    ++R;
55
850k
    if (R.isValid()) {
56
33.4k
      UnitInfos[U].Mask = LaneBitmask::getAll();
57
33.4k
      UnitInfos[U].Reg = F;
58
817k
    } else {
59
1.63M
      for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); 
++I817k
) {
60
817k
        std::pair<uint32_t,LaneBitmask> P = *I;
61
817k
        UnitInfo &UI = UnitInfos[P.first];
62
817k
        UI.Reg = F;
63
817k
        if (P.second.any()) {
64
0
          UI.Mask = P.second;
65
817k
        } else {
66
817k
          if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
67
803k
            UI.Mask = RC->LaneMask;
68
13.3k
          else
69
13.3k
            UI.Mask = LaneBitmask::getAll();
70
817k
        }
71
817k
      }
72
817k
    }
73
850k
  }
74
6.69k
75
6.69k
  for (const uint32_t *RM : TRI.getRegMasks())
76
6.69k
    RegMasks.insert(RM);
77
6.69k
  for (const MachineBasicBlock &B : mf)
78
11.0k
    for (const MachineInstr &In : B)
79
59.0k
      for (const MachineOperand &Op : In.operands())
80
188k
        if (Op.isRegMask())
81
1.42k
          RegMasks.insert(Op.getRegMask());
82
6.69k
83
6.69k
  MaskInfos.resize(RegMasks.size()+1);
84
13.3k
  for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; 
++M6.69k
) {
85
6.69k
    BitVector PU(TRI.getNumRegUnits());
86
6.69k
    const uint32_t *MB = RegMasks.get(M);
87
1.31M
    for (unsigned i = 1, e = TRI.getNumRegs(); i != e; 
++i1.31M
) {
88
1.31M
      if (!(MB[i/32] & (1u << (i%32))))
89
1.19M
        continue;
90
281k
      
for (MCRegUnitIterator U(i, &TRI); 120k
U.isValid();
++U160k
)
91
160k
        PU.set(*U);
92
120k
    }
93
6.69k
    MaskInfos[M].Units = PU.flip();
94
6.69k
  }
95
6.69k
}
96
97
71.7k
RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
98
71.7k
  return RR;
99
71.7k
}
100
101
85.6k
std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
102
85.6k
  // Do not include RR in the alias set.
103
85.6k
  std::set<RegisterId> AS;
104
85.6k
  assert(isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg));
105
85.6k
  if (isRegMaskId(Reg)) {
106
1.89k
    // XXX SLOW
107
1.89k
    const uint32_t *MB = getRegMaskBits(Reg);
108
372k
    for (unsigned i = 1, e = TRI.getNumRegs(); i != e; 
++i371k
) {
109
371k
      if (MB[i/32] & (1u << (i%32)))
110
34.0k
        continue;
111
336k
      AS.insert(i);
112
336k
    }
113
1.89k
    for (const uint32_t *RM : RegMasks) {
114
1.89k
      RegisterId MI = getRegMaskId(RM);
115
1.89k
      if (MI != Reg && 
aliasMM(RegisterRef(Reg), RegisterRef(MI))0
)
116
0
        AS.insert(MI);
117
1.89k
    }
118
1.89k
    return AS;
119
1.89k
  }
120
83.7k
121
199k
  
for (MCRegAliasIterator AI(Reg, &TRI, false); 83.7k
AI.isValid();
++AI115k
)
122
115k
    AS.insert(*AI);
123
83.7k
  for (const uint32_t *RM : RegMasks) {
124
83.7k
    RegisterId MI = getRegMaskId(RM);
125
83.7k
    if (aliasRM(RegisterRef(Reg), RegisterRef(MI)))
126
81.2k
      AS.insert(MI);
127
83.7k
  }
128
83.7k
  return AS;
129
83.7k
}
130
131
348k
bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
132
348k
  assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg));
133
348k
  assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg));
134
348k
135
348k
  MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
136
348k
  MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
137
348k
  // Reg units are returned in the numerical order.
138
724k
  while (UMA.isValid() && 
UMB.isValid()614k
) {
139
471k
    // Skip units that are masked off in RA.
140
471k
    std::pair<RegisterId,LaneBitmask> PA = *UMA;
141
471k
    if (PA.second.any() && 
(PA.second & RA.Mask).none()265k
) {
142
100k
      ++UMA;
143
100k
      continue;
144
100k
    }
145
370k
    // Skip units that are masked off in RB.
146
370k
    std::pair<RegisterId,LaneBitmask> PB = *UMB;
147
370k
    if (PB.second.any() && 
(PB.second & RB.Mask).none()42.2k
) {
148
0
      ++UMB;
149
0
      continue;
150
0
    }
151
370k
152
370k
    if (PA.first == PB.first)
153
94.6k
      return true;
154
275k
    if (PA.first < PB.first)
155
118k
      ++UMA;
156
157k
    else if (PB.first < PA.first)
157
157k
      ++UMB;
158
275k
  }
159
348k
  
return false253k
;
160
348k
}
161
162
100k
bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const {
163
100k
  assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg));
164
100k
  const uint32_t *MB = getRegMaskBits(RM.Reg);
165
100k
  bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32));
166
100k
  // If the lane mask information is "full", e.g. when the given lane mask
167
100k
  // is a superset of the lane mask from the register class, check the regmask
168
100k
  // bit directly.
169
100k
  if (RR.Mask == LaneBitmask::getAll())
170
99.7k
    return !Preserved;
171
739
  const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
172
739
  if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask)
173
393
    return !Preserved;
174
346
175
346
  // Otherwise, check all subregisters whose lane mask overlaps the given
176
346
  // mask. For each such register, if it is preserved by the regmask, then
177
346
  // clear the corresponding bits in the given mask. If at the end, all
178
346
  // bits have been cleared, the register does not alias the regmask (i.e.
179
346
  // is it preserved by it).
180
346
  LaneBitmask M = RR.Mask;
181
1.27k
  for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); 
++SI932
) {
182
932
    LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex());
183
932
    if ((SM & RR.Mask).none())
184
466
      continue;
185
466
    unsigned SR = SI.getSubReg();
186
466
    if (!(MB[SR/32] & (1u << (SR%32))))
187
466
      continue;
188
0
    // The subregister SR is preserved.
189
0
    M &= ~SM;
190
0
    if (M.none())
191
0
      return false;
192
0
  }
193
346
194
346
  return true;
195
346
}
196
197
1.46k
bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
198
1.46k
  assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg));
199
1.46k
  unsigned NumRegs = TRI.getNumRegs();
200
1.46k
  const uint32_t *BM = getRegMaskBits(RM.Reg);
201
1.46k
  const uint32_t *BN = getRegMaskBits(RN.Reg);
202
1.46k
203
1.46k
  for (unsigned w = 0, nw = NumRegs/32; w != nw; 
++w0
) {
204
1.46k
    // Intersect the negations of both words. Disregard reg=0,
205
1.46k
    // i.e. 0th bit in the 0th word.
206
1.46k
    uint32_t C = ~BM[w] & ~BN[w];
207
1.46k
    if (w == 0)
208
1.46k
      C &= ~1;
209
1.46k
    if (C)
210
1.46k
      return true;
211
1.46k
  }
212
1.46k
213
1.46k
  // Check the remaining registers in the last word.
214
1.46k
  unsigned TailRegs = NumRegs % 32;
215
0
  if (TailRegs == 0)
216
0
    return false;
217
0
  unsigned TW = NumRegs / 32;
218
0
  uint32_t TailMask = (1u << TailRegs) - 1;
219
0
  if (~BM[TW] & ~BN[TW] & TailMask)
220
0
    return true;
221
0
222
0
  return false;
223
0
}
224
225
32.2k
RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
226
32.2k
  if (RR.Reg == R)
227
15.4k
    return RR;
228
16.8k
  if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg))
229
848
    return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
230
15.9k
  if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) {
231
15.9k
    const RegInfo &RI = RegInfos[R];
232
15.9k
    LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
233
15.9k
                                  : 
LaneBitmask::getAll()0
;
234
15.9k
    LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);
235
15.9k
    return RegisterRef(R, M & RCM);
236
15.9k
  }
237
0
  llvm_unreachable("Invalid arguments: unrelated registers?");
238
0
}
239
240
182k
bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
241
182k
  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
242
12.7k
    return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
243
170k
244
328k
  
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); 170k
U.isValid();
++U158k
) {
245
185k
    std::pair<uint32_t,LaneBitmask> P = *U;
246
185k
    if (P.second.none() || 
(P.second & RR.Mask).any()38.5k
)
247
185k
      if (Units.test(P.first))
248
27.1k
        return true;
249
185k
  }
250
170k
  
return false142k
;
251
170k
}
252
253
1.28M
bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
254
1.28M
  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
255
64.0k
    BitVector T(PRI.getMaskUnits(RR.Reg));
256
64.0k
    return T.reset(Units).none();
257
64.0k
  }
258
1.21M
259
1.56M
  
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); 1.21M
U.isValid();
++U351k
) {
260
1.33M
    std::pair<uint32_t,LaneBitmask> P = *U;
261
1.33M
    if (P.second.none() || 
(P.second & RR.Mask).any()398k
)
262
1.25M
      if (!Units.test(P.first))
263
983k
        return false;
264
1.33M
  }
265
1.21M
  
return true235k
;
266
1.21M
}
267
268
1.32M
RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
269
1.32M
  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
270
29.1k
    Units |= PRI.getMaskUnits(RR.Reg);
271
29.1k
    return *this;
272
29.1k
  }
273
1.29M
274
2.78M
  
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); 1.29M
U.isValid();
++U1.48M
) {
275
1.48M
    std::pair<uint32_t,LaneBitmask> P = *U;
276
1.48M
    if (P.second.none() || 
(P.second & RR.Mask).any()354k
)
277
1.45M
      Units.set(P.first);
278
1.48M
  }
279
1.29M
  return *this;
280
1.29M
}
281
282
403
RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
283
403
  Units |= RG.Units;
284
403
  return *this;
285
403
}
286
287
14.3k
RegisterAggr &RegisterAggr::intersect(RegisterRef RR) {
288
14.3k
  return intersect(RegisterAggr(PRI).insert(RR));
289
14.3k
}
290
291
30.6k
RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) {
292
30.6k
  Units &= RG.Units;
293
30.6k
  return *this;
294
30.6k
}
295
296
0
RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
297
0
  return clear(RegisterAggr(PRI).insert(RR));
298
0
}
299
300
76.1k
RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) {
301
76.1k
  Units.reset(RG.Units);
302
76.1k
  return *this;
303
76.1k
}
304
305
16.2k
RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const {
306
16.2k
  RegisterAggr T(PRI);
307
16.2k
  T.insert(RR).intersect(*this);
308
16.2k
  if (T.empty())
309
0
    return RegisterRef();
310
16.2k
  RegisterRef NR = T.makeRegRef();
311
16.2k
  assert(NR);
312
16.2k
  return NR;
313
16.2k
}
314
315
76.1k
RegisterRef RegisterAggr::clearIn(RegisterRef RR) const {
316
76.1k
  return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
317
76.1k
}
318
319
106k
RegisterRef RegisterAggr::makeRegRef() const {
320
106k
  int U = Units.find_first();
321
106k
  if (U < 0)
322
25.2k
    return RegisterRef();
323
81.5k
324
93.0k
  
auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) 81.5k
{
325
189k
    for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); 
++R96.6k
)
326
302k
      
for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); 96.6k
S.isValid();
++S205k
)
327
205k
        Regs.set(*S);
328
93.0k
  };
329
81.5k
330
81.5k
  // Find the set of all registers that are aliased to all the units
331
81.5k
  // in this aggregate.
332
81.5k
333
81.5k
  // Get all the registers aliased to the first unit in the bit vector.
334
81.5k
  BitVector Regs(PRI.getTRI().getNumRegs());
335
81.5k
  AliasedRegs(U, Regs);
336
81.5k
  U = Units.find_next(U);
337
81.5k
338
81.5k
  // For each other unit, intersect it with the set of all registers
339
81.5k
  // aliased that unit.
340
93.0k
  while (U >= 0) {
341
11.5k
    BitVector AR(PRI.getTRI().getNumRegs());
342
11.5k
    AliasedRegs(U, AR);
343
11.5k
    Regs &= AR;
344
11.5k
    U = Units.find_next(U);
345
11.5k
  }
346
81.5k
347
81.5k
  // If there is at least one register remaining, pick the first one,
348
81.5k
  // and consolidate the masks of all of its units contained in this
349
81.5k
  // aggregate.
350
81.5k
351
81.5k
  int F = Regs.find_first();
352
81.5k
  if (F <= 0)
353
0
    return RegisterRef();
354
81.5k
355
81.5k
  LaneBitmask M;
356
237k
  for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); 
++I155k
) {
357
155k
    std::pair<uint32_t,LaneBitmask> P = *I;
358
155k
    if (Units.test(P.first))
359
93.0k
      M |= P.second.none() ? 
LaneBitmask::getAll()14.8k
:
P.second78.2k
;
360
155k
  }
361
81.5k
  return RegisterRef(F, M);
362
81.5k
}
363
364
0
void RegisterAggr::print(raw_ostream &OS) const {
365
0
  OS << '{';
366
0
  for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
367
0
    OS << ' ' << printRegUnit(U, &PRI.getTRI());
368
0
  OS << " }";
369
0
}
370
371
RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
372
      bool End)
373
18.0k
    : Owner(&RG) {
374
68.3k
  for (int U = RG.Units.find_first(); U >= 0; 
U = RG.Units.find_next(U)50.3k
) {
375
50.3k
    RegisterRef R = RG.PRI.getRefForUnit(U);
376
50.3k
    Masks[R.Reg] |= R.Mask;
377
50.3k
  }
378
18.0k
  Pos = End ? 
Masks.end()9.02k
:
Masks.begin()9.02k
;
379
18.0k
  Index = End ? 
Masks.size()9.02k
:
09.02k
;
380
18.0k
}