/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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1 | | //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file is part of the Mips Disassembler. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "MCTargetDesc/MipsMCTargetDesc.h" |
15 | | #include "Mips.h" |
16 | | #include "llvm/ADT/ArrayRef.h" |
17 | | #include "llvm/MC/MCContext.h" |
18 | | #include "llvm/MC/MCDisassembler/MCDisassembler.h" |
19 | | #include "llvm/MC/MCFixedLenDisassembler.h" |
20 | | #include "llvm/MC/MCInst.h" |
21 | | #include "llvm/MC/MCRegisterInfo.h" |
22 | | #include "llvm/MC/MCSubtargetInfo.h" |
23 | | #include "llvm/Support/Compiler.h" |
24 | | #include "llvm/Support/Debug.h" |
25 | | #include "llvm/Support/ErrorHandling.h" |
26 | | #include "llvm/Support/MathExtras.h" |
27 | | #include "llvm/Support/TargetRegistry.h" |
28 | | #include "llvm/Support/raw_ostream.h" |
29 | | #include <cassert> |
30 | | #include <cstdint> |
31 | | |
32 | | using namespace llvm; |
33 | | |
34 | | #define DEBUG_TYPE "mips-disassembler" |
35 | | |
36 | | using DecodeStatus = MCDisassembler::DecodeStatus; |
37 | | |
38 | | namespace { |
39 | | |
40 | | class MipsDisassembler : public MCDisassembler { |
41 | | bool IsMicroMips; |
42 | | bool IsBigEndian; |
43 | | |
44 | | public: |
45 | | MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) |
46 | | : MCDisassembler(STI, Ctx), |
47 | | IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), |
48 | 235 | IsBigEndian(IsBigEndian) {} |
49 | | |
50 | 62.1k | bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } |
51 | 1.61k | bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } |
52 | 62.8k | bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } |
53 | | |
54 | 190k | bool hasMips32r6() const { |
55 | 190k | return STI.getFeatureBits()[Mips::FeatureMips32r6]; |
56 | 190k | } |
57 | | |
58 | 61.0k | bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } |
59 | | |
60 | 63.5k | bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } |
61 | | |
62 | 62.7k | bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } |
63 | | |
64 | 62.1k | bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } |
65 | | |
66 | 62.8k | bool hasCOP3() const { |
67 | 62.8k | // Only present in MIPS-I and MIPS-II |
68 | 62.8k | return !hasMips32() && !hasMips3()1.61k ; |
69 | 62.8k | } |
70 | | |
71 | | DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, |
72 | | ArrayRef<uint8_t> Bytes, uint64_t Address, |
73 | | raw_ostream &VStream, |
74 | | raw_ostream &CStream) const override; |
75 | | }; |
76 | | |
77 | | } // end anonymous namespace |
78 | | |
79 | | // Forward declare these because the autogenerated code will reference them. |
80 | | // Definitions are further down. |
81 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, |
82 | | unsigned RegNo, |
83 | | uint64_t Address, |
84 | | const void *Decoder); |
85 | | |
86 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, |
87 | | unsigned RegNo, |
88 | | uint64_t Address, |
89 | | const void *Decoder); |
90 | | |
91 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, |
92 | | unsigned RegNo, |
93 | | uint64_t Address, |
94 | | const void *Decoder); |
95 | | |
96 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, |
97 | | unsigned RegNo, |
98 | | uint64_t Address, |
99 | | const void *Decoder); |
100 | | |
101 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, |
102 | | unsigned RegNo, |
103 | | uint64_t Address, |
104 | | const void *Decoder); |
105 | | |
106 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, |
107 | | unsigned RegNo, |
108 | | uint64_t Address, |
109 | | const void *Decoder); |
110 | | |
111 | | static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, |
112 | | unsigned Insn, |
113 | | uint64_t Address, |
114 | | const void *Decoder); |
115 | | |
116 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, |
117 | | unsigned RegNo, |
118 | | uint64_t Address, |
119 | | const void *Decoder); |
120 | | |
121 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, |
122 | | unsigned RegNo, |
123 | | uint64_t Address, |
124 | | const void *Decoder); |
125 | | |
126 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, |
127 | | unsigned RegNo, |
128 | | uint64_t Address, |
129 | | const void *Decoder); |
130 | | |
131 | | static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, |
132 | | unsigned RegNo, |
133 | | uint64_t Address, |
134 | | const void *Decoder); |
135 | | |
136 | | static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, |
137 | | unsigned RegNo, |
138 | | uint64_t Address, |
139 | | const void *Decoder); |
140 | | |
141 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, |
142 | | uint64_t Address, |
143 | | const void *Decoder); |
144 | | |
145 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, |
146 | | unsigned Insn, |
147 | | uint64_t Address, |
148 | | const void *Decoder); |
149 | | |
150 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, |
151 | | unsigned RegNo, |
152 | | uint64_t Address, |
153 | | const void *Decoder); |
154 | | |
155 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, |
156 | | unsigned RegNo, |
157 | | uint64_t Address, |
158 | | const void *Decoder); |
159 | | |
160 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, |
161 | | unsigned RegNo, |
162 | | uint64_t Address, |
163 | | const void *Decoder); |
164 | | |
165 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, |
166 | | unsigned RegNo, |
167 | | uint64_t Address, |
168 | | const void *Decoder); |
169 | | |
170 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, |
171 | | unsigned RegNo, |
172 | | uint64_t Address, |
173 | | const void *Decoder); |
174 | | |
175 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, |
176 | | unsigned RegNo, |
177 | | uint64_t Address, |
178 | | const void *Decoder); |
179 | | |
180 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, |
181 | | unsigned RegNo, |
182 | | uint64_t Address, |
183 | | const void *Decoder); |
184 | | |
185 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, |
186 | | unsigned RegNo, |
187 | | uint64_t Address, |
188 | | const void *Decoder); |
189 | | |
190 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, |
191 | | unsigned RegNo, |
192 | | uint64_t Address, |
193 | | const void *Decoder); |
194 | | |
195 | | static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, |
196 | | unsigned RegNo, |
197 | | uint64_t Address, |
198 | | const void *Decoder); |
199 | | |
200 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, |
201 | | unsigned RegNo, |
202 | | uint64_t Address, |
203 | | const void *Decoder); |
204 | | |
205 | | static DecodeStatus DecodeBranchTarget(MCInst &Inst, |
206 | | unsigned Offset, |
207 | | uint64_t Address, |
208 | | const void *Decoder); |
209 | | |
210 | | static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, |
211 | | unsigned Offset, |
212 | | uint64_t Address, |
213 | | const void *Decoder); |
214 | | |
215 | | static DecodeStatus DecodeJumpTarget(MCInst &Inst, |
216 | | unsigned Insn, |
217 | | uint64_t Address, |
218 | | const void *Decoder); |
219 | | |
220 | | static DecodeStatus DecodeBranchTarget21(MCInst &Inst, |
221 | | unsigned Offset, |
222 | | uint64_t Address, |
223 | | const void *Decoder); |
224 | | |
225 | | static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, |
226 | | unsigned Offset, |
227 | | uint64_t Address, |
228 | | const void *Decoder); |
229 | | |
230 | | static DecodeStatus DecodeBranchTarget26(MCInst &Inst, |
231 | | unsigned Offset, |
232 | | uint64_t Address, |
233 | | const void *Decoder); |
234 | | |
235 | | // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is |
236 | | // shifted left by 1 bit. |
237 | | static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, |
238 | | unsigned Offset, |
239 | | uint64_t Address, |
240 | | const void *Decoder); |
241 | | |
242 | | // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is |
243 | | // shifted left by 1 bit. |
244 | | static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, |
245 | | unsigned Offset, |
246 | | uint64_t Address, |
247 | | const void *Decoder); |
248 | | |
249 | | // DecodeBranchTargetMM - Decode microMIPS branch offset, which is |
250 | | // shifted left by 1 bit. |
251 | | static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, |
252 | | unsigned Offset, |
253 | | uint64_t Address, |
254 | | const void *Decoder); |
255 | | |
256 | | // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is |
257 | | // shifted left by 1 bit. |
258 | | static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, |
259 | | unsigned Offset, |
260 | | uint64_t Address, |
261 | | const void *Decoder); |
262 | | |
263 | | // DecodeJumpTargetMM - Decode microMIPS jump target, which is |
264 | | // shifted left by 1 bit. |
265 | | static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, |
266 | | unsigned Insn, |
267 | | uint64_t Address, |
268 | | const void *Decoder); |
269 | | |
270 | | static DecodeStatus DecodeMem(MCInst &Inst, |
271 | | unsigned Insn, |
272 | | uint64_t Address, |
273 | | const void *Decoder); |
274 | | |
275 | | static DecodeStatus DecodeMemEVA(MCInst &Inst, |
276 | | unsigned Insn, |
277 | | uint64_t Address, |
278 | | const void *Decoder); |
279 | | |
280 | | static DecodeStatus DecodeLoadByte15(MCInst &Inst, |
281 | | unsigned Insn, |
282 | | uint64_t Address, |
283 | | const void *Decoder); |
284 | | |
285 | | static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, |
286 | | const void *Decoder); |
287 | | |
288 | | static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, |
289 | | unsigned Insn, |
290 | | uint64_t Address, |
291 | | const void *Decoder); |
292 | | |
293 | | static DecodeStatus DecodeCacheOpMM(MCInst &Inst, |
294 | | unsigned Insn, |
295 | | uint64_t Address, |
296 | | const void *Decoder); |
297 | | |
298 | | static DecodeStatus DecodePrefeOpMM(MCInst &Inst, |
299 | | unsigned Insn, |
300 | | uint64_t Address, |
301 | | const void *Decoder); |
302 | | |
303 | | static DecodeStatus DecodeSyncI(MCInst &Inst, |
304 | | unsigned Insn, |
305 | | uint64_t Address, |
306 | | const void *Decoder); |
307 | | |
308 | | static DecodeStatus DecodeSynciR6(MCInst &Inst, |
309 | | unsigned Insn, |
310 | | uint64_t Address, |
311 | | const void *Decoder); |
312 | | |
313 | | static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, |
314 | | uint64_t Address, const void *Decoder); |
315 | | |
316 | | static DecodeStatus DecodeMemMMImm4(MCInst &Inst, |
317 | | unsigned Insn, |
318 | | uint64_t Address, |
319 | | const void *Decoder); |
320 | | |
321 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, |
322 | | unsigned Insn, |
323 | | uint64_t Address, |
324 | | const void *Decoder); |
325 | | |
326 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, |
327 | | unsigned Insn, |
328 | | uint64_t Address, |
329 | | const void *Decoder); |
330 | | |
331 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, |
332 | | unsigned Insn, |
333 | | uint64_t Address, |
334 | | const void *Decoder); |
335 | | |
336 | | static DecodeStatus DecodeMemMMImm9(MCInst &Inst, |
337 | | unsigned Insn, |
338 | | uint64_t Address, |
339 | | const void *Decoder); |
340 | | |
341 | | static DecodeStatus DecodeMemMMImm12(MCInst &Inst, |
342 | | unsigned Insn, |
343 | | uint64_t Address, |
344 | | const void *Decoder); |
345 | | |
346 | | static DecodeStatus DecodeMemMMImm16(MCInst &Inst, |
347 | | unsigned Insn, |
348 | | uint64_t Address, |
349 | | const void *Decoder); |
350 | | |
351 | | static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, |
352 | | uint64_t Address, |
353 | | const void *Decoder); |
354 | | |
355 | | static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, |
356 | | uint64_t Address, |
357 | | const void *Decoder); |
358 | | |
359 | | static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, |
360 | | const void *Decoder); |
361 | | |
362 | | static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, |
363 | | const void *Decoder); |
364 | | |
365 | | static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, |
366 | | uint64_t Address, const void *Decoder); |
367 | | |
368 | | static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, |
369 | | uint64_t Address, |
370 | | const void *Decoder); |
371 | | |
372 | | static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, |
373 | | unsigned Insn, |
374 | | uint64_t Address, |
375 | | const void *Decoder); |
376 | | |
377 | | static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, |
378 | | unsigned Value, |
379 | | uint64_t Address, |
380 | | const void *Decoder); |
381 | | |
382 | | static DecodeStatus DecodeLi16Imm(MCInst &Inst, |
383 | | unsigned Value, |
384 | | uint64_t Address, |
385 | | const void *Decoder); |
386 | | |
387 | | static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, |
388 | | unsigned Value, |
389 | | uint64_t Address, |
390 | | const void *Decoder); |
391 | | |
392 | | template <unsigned Bits, int Offset, int Scale> |
393 | | static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, |
394 | | uint64_t Address, |
395 | | const void *Decoder); |
396 | | |
397 | | template <unsigned Bits, int Offset> |
398 | | static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, |
399 | | uint64_t Address, |
400 | 28 | const void *Decoder) { |
401 | 28 | return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, |
402 | 28 | Decoder); |
403 | 28 | } MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffset<5u, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 400 | 13 | const void *Decoder) { | 401 | 13 | return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, | 402 | 13 | Decoder); | 403 | 13 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffset<2u, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 400 | 15 | const void *Decoder) { | 401 | 15 | return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, | 402 | 15 | Decoder); | 403 | 15 | } |
|
404 | | |
405 | | template <unsigned Bits, int Offset = 0, int ScaleBy = 1> |
406 | | static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, |
407 | | uint64_t Address, |
408 | | const void *Decoder); |
409 | | |
410 | | static DecodeStatus DecodeInsSize(MCInst &Inst, |
411 | | unsigned Insn, |
412 | | uint64_t Address, |
413 | | const void *Decoder); |
414 | | |
415 | | static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, |
416 | | uint64_t Address, const void *Decoder); |
417 | | |
418 | | static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, |
419 | | uint64_t Address, const void *Decoder); |
420 | | |
421 | | static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, |
422 | | uint64_t Address, const void *Decoder); |
423 | | |
424 | | static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, |
425 | | uint64_t Address, const void *Decoder); |
426 | | |
427 | | static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, |
428 | | uint64_t Address, const void *Decoder); |
429 | | |
430 | | /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't |
431 | | /// handle. |
432 | | template <typename InsnType> |
433 | | static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, |
434 | | const void *Decoder); |
435 | | |
436 | | template <typename InsnType> |
437 | | static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
438 | | const void *Decoder); |
439 | | |
440 | | template <typename InsnType> |
441 | | static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, |
442 | | const void *Decoder); |
443 | | |
444 | | template <typename InsnType> |
445 | | static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
446 | | const void *Decoder); |
447 | | |
448 | | template <typename InsnType> |
449 | | static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, |
450 | | const void *Decoder); |
451 | | |
452 | | template <typename InsnType> |
453 | | static DecodeStatus |
454 | | DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
455 | | const void *Decoder); |
456 | | |
457 | | template <typename InsnType> |
458 | | static DecodeStatus |
459 | | DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
460 | | const void *Decoder); |
461 | | |
462 | | template <typename InsnType> |
463 | | static DecodeStatus |
464 | | DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
465 | | const void *Decoder); |
466 | | |
467 | | template <typename InsnType> |
468 | | static DecodeStatus |
469 | | DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
470 | | const void *Decoder); |
471 | | |
472 | | template <typename InsnType> |
473 | | static DecodeStatus |
474 | | DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
475 | | const void *Decoder); |
476 | | |
477 | | template <typename InsnType> |
478 | | static DecodeStatus |
479 | | DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
480 | | const void *Decoder); |
481 | | |
482 | | template <typename InsnType> |
483 | | static DecodeStatus |
484 | | DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
485 | | const void *Decoder); |
486 | | |
487 | | template <typename InsnType> |
488 | | static DecodeStatus |
489 | | DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
490 | | const void *Decoder); |
491 | | |
492 | | template <typename InsnType> |
493 | | static DecodeStatus |
494 | | DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
495 | | const void *Decoder); |
496 | | |
497 | | template <typename InsnType> |
498 | | static DecodeStatus |
499 | | DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, |
500 | | const void *Decoder); |
501 | | |
502 | | template <typename InsnType> |
503 | | static DecodeStatus |
504 | | DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
505 | | const void *Decoder); |
506 | | |
507 | | template <typename InsnType> |
508 | | static DecodeStatus |
509 | | DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
510 | | const void *Decoder); |
511 | | |
512 | | template <typename InsnType> |
513 | | static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, |
514 | | const void *Decoder); |
515 | | |
516 | | template <typename InsnType> |
517 | | static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, |
518 | | const void *Decoder); |
519 | | |
520 | | static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, |
521 | | uint64_t Address, |
522 | | const void *Decoder); |
523 | | |
524 | | static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, |
525 | | uint64_t Address, |
526 | | const void *Decoder); |
527 | | |
528 | | static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, |
529 | | uint64_t Address, |
530 | | const void *Decoder); |
531 | | |
532 | | namespace llvm { |
533 | | |
534 | | Target &getTheMipselTarget(); |
535 | | Target &getTheMipsTarget(); |
536 | | Target &getTheMips64Target(); |
537 | | Target &getTheMips64elTarget(); |
538 | | |
539 | | } // end namespace llvm |
540 | | |
541 | | static MCDisassembler *createMipsDisassembler( |
542 | | const Target &T, |
543 | | const MCSubtargetInfo &STI, |
544 | 170 | MCContext &Ctx) { |
545 | 170 | return new MipsDisassembler(STI, Ctx, true); |
546 | 170 | } |
547 | | |
548 | | static MCDisassembler *createMipselDisassembler( |
549 | | const Target &T, |
550 | | const MCSubtargetInfo &STI, |
551 | 65 | MCContext &Ctx) { |
552 | 65 | return new MipsDisassembler(STI, Ctx, false); |
553 | 65 | } |
554 | | |
555 | 7.19k | extern "C" void LLVMInitializeMipsDisassembler() { |
556 | 7.19k | // Register the disassembler. |
557 | 7.19k | TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), |
558 | 7.19k | createMipsDisassembler); |
559 | 7.19k | TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), |
560 | 7.19k | createMipselDisassembler); |
561 | 7.19k | TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), |
562 | 7.19k | createMipsDisassembler); |
563 | 7.19k | TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), |
564 | 7.19k | createMipselDisassembler); |
565 | 7.19k | } |
566 | | |
567 | | #include "MipsGenDisassemblerTables.inc" |
568 | | |
569 | 128k | static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { |
570 | 128k | const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); |
571 | 128k | const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); |
572 | 128k | return *(RegInfo->getRegClass(RC).begin() + RegNo); |
573 | 128k | } |
574 | | |
575 | | template <typename InsnType> |
576 | | static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, |
577 | 4 | const void *Decoder) { |
578 | 4 | using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); |
579 | 4 | |
580 | 4 | // The size of the n field depends on the element size |
581 | 4 | // The register class also depends on this. |
582 | 4 | InsnType tmp = fieldFromInstruction(insn, 17, 5); |
583 | 4 | unsigned NSize = 0; |
584 | 4 | DecodeFN RegDecoder = nullptr; |
585 | 4 | if ((tmp & 0x18) == 0x00) { // INSVE_B |
586 | 1 | NSize = 4; |
587 | 1 | RegDecoder = DecodeMSA128BRegisterClass; |
588 | 3 | } else if ((tmp & 0x1c) == 0x10) { // INSVE_H |
589 | 1 | NSize = 3; |
590 | 1 | RegDecoder = DecodeMSA128HRegisterClass; |
591 | 2 | } else if ((tmp & 0x1e) == 0x18) { // INSVE_W |
592 | 1 | NSize = 2; |
593 | 1 | RegDecoder = DecodeMSA128WRegisterClass; |
594 | 1 | } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D |
595 | 1 | NSize = 1; |
596 | 1 | RegDecoder = DecodeMSA128DRegisterClass; |
597 | 1 | } else |
598 | 1 | llvm_unreachable0 ("Invalid encoding"); |
599 | 4 | |
600 | 4 | assert(NSize != 0 && RegDecoder != nullptr); |
601 | 4 | |
602 | 4 | // $wd |
603 | 4 | tmp = fieldFromInstruction(insn, 6, 5); |
604 | 4 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) |
605 | 0 | return MCDisassembler::Fail; |
606 | 4 | // $wd_in |
607 | 4 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) |
608 | 0 | return MCDisassembler::Fail; |
609 | 4 | // $n |
610 | 4 | tmp = fieldFromInstruction(insn, 16, NSize); |
611 | 4 | MI.addOperand(MCOperand::createImm(tmp)); |
612 | 4 | // $ws |
613 | 4 | tmp = fieldFromInstruction(insn, 11, 5); |
614 | 4 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) |
615 | 0 | return MCDisassembler::Fail; |
616 | 4 | // $n2 |
617 | 4 | MI.addOperand(MCOperand::createImm(0)); |
618 | 4 | |
619 | 4 | return MCDisassembler::Success; |
620 | 4 | } |
621 | | |
622 | | template <typename InsnType> |
623 | | static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, |
624 | | const void *Decoder) { |
625 | | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
626 | | InsnType Imm = fieldFromInstruction(insn, 0, 16); |
627 | | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, |
628 | | Rs))); |
629 | | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, |
630 | | Rs))); |
631 | | MI.addOperand(MCOperand::createImm(Imm)); |
632 | | |
633 | | return MCDisassembler::Success; |
634 | | } |
635 | | |
636 | | template <typename InsnType> |
637 | | static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, |
638 | 5 | const void *Decoder) { |
639 | 5 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
640 | 5 | InsnType Imm = fieldFromInstruction(insn, 0, 16); |
641 | 5 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, |
642 | 5 | Rs))); |
643 | 5 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, |
644 | 5 | Rs))); |
645 | 5 | MI.addOperand(MCOperand::createImm(Imm)); |
646 | 5 | |
647 | 5 | return MCDisassembler::Success; |
648 | 5 | } |
649 | | |
650 | | template <typename InsnType> |
651 | | static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, |
652 | | uint64_t Address, |
653 | 31 | const void *Decoder) { |
654 | 31 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
655 | 31 | // (otherwise we would have matched the ADDI instruction from the earlier |
656 | 31 | // ISA's instead). |
657 | 31 | // |
658 | 31 | // We have: |
659 | 31 | // 0b001000 sssss ttttt iiiiiiiiiiiiiiii |
660 | 31 | // BOVC if rs >= rt |
661 | 31 | // BEQZALC if rs == 0 && rt != 0 |
662 | 31 | // BEQC if rs < rt && rs != 0 |
663 | 31 | |
664 | 31 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
665 | 31 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
666 | 31 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
667 | 31 | bool HasRs = false; |
668 | 31 | |
669 | 31 | if (Rs >= Rt) { |
670 | 20 | MI.setOpcode(Mips::BOVC); |
671 | 20 | HasRs = true; |
672 | 20 | } else if (11 Rs != 011 && Rs < Rt7 ) { |
673 | 7 | MI.setOpcode(Mips::BEQC); |
674 | 7 | HasRs = true; |
675 | 7 | } else |
676 | 4 | MI.setOpcode(Mips::BEQZALC); |
677 | 31 | |
678 | 31 | if (HasRs) |
679 | 27 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
680 | 27 | Rs))); |
681 | 31 | |
682 | 31 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
683 | 31 | Rt))); |
684 | 31 | MI.addOperand(MCOperand::createImm(Imm)); |
685 | 31 | |
686 | 31 | return MCDisassembler::Success; |
687 | 31 | } |
688 | | |
689 | | template <typename InsnType> |
690 | | static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, |
691 | | uint64_t Address, |
692 | 3 | const void *Decoder) { |
693 | 3 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
694 | 3 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
695 | 3 | int64_t Imm = 0; |
696 | 3 | |
697 | 3 | if (Rs >= Rt) { |
698 | 1 | MI.setOpcode(Mips::BOVC_MMR6); |
699 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
700 | 1 | Rt))); |
701 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
702 | 1 | Rs))); |
703 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
704 | 2 | } else if (Rs != 0 && Rs < Rt1 ) { |
705 | 1 | MI.setOpcode(Mips::BEQC_MMR6); |
706 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
707 | 1 | Rs))); |
708 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
709 | 1 | Rt))); |
710 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
711 | 1 | } else { |
712 | 1 | MI.setOpcode(Mips::BEQZALC_MMR6); |
713 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
714 | 1 | Rt))); |
715 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
716 | 1 | } |
717 | 3 | |
718 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
719 | 3 | |
720 | 3 | return MCDisassembler::Success; |
721 | 3 | } |
722 | | |
723 | | template <typename InsnType> |
724 | | static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, |
725 | | uint64_t Address, |
726 | 37 | const void *Decoder) { |
727 | 37 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
728 | 37 | // (otherwise we would have matched the ADDI instruction from the earlier |
729 | 37 | // ISA's instead). |
730 | 37 | // |
731 | 37 | // We have: |
732 | 37 | // 0b011000 sssss ttttt iiiiiiiiiiiiiiii |
733 | 37 | // BNVC if rs >= rt |
734 | 37 | // BNEZALC if rs == 0 && rt != 0 |
735 | 37 | // BNEC if rs < rt && rs != 0 |
736 | 37 | |
737 | 37 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
738 | 37 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
739 | 37 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
740 | 37 | bool HasRs = false; |
741 | 37 | |
742 | 37 | if (Rs >= Rt) { |
743 | 20 | MI.setOpcode(Mips::BNVC); |
744 | 20 | HasRs = true; |
745 | 20 | } else if (17 Rs != 017 && Rs < Rt13 ) { |
746 | 13 | MI.setOpcode(Mips::BNEC); |
747 | 13 | HasRs = true; |
748 | 13 | } else |
749 | 4 | MI.setOpcode(Mips::BNEZALC); |
750 | 37 | |
751 | 37 | if (HasRs) |
752 | 33 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
753 | 33 | Rs))); |
754 | 37 | |
755 | 37 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
756 | 37 | Rt))); |
757 | 37 | MI.addOperand(MCOperand::createImm(Imm)); |
758 | 37 | |
759 | 37 | return MCDisassembler::Success; |
760 | 37 | } |
761 | | |
762 | | template <typename InsnType> |
763 | | static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, |
764 | | uint64_t Address, |
765 | 3 | const void *Decoder) { |
766 | 3 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
767 | 3 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
768 | 3 | int64_t Imm = 0; |
769 | 3 | |
770 | 3 | if (Rs >= Rt) { |
771 | 1 | MI.setOpcode(Mips::BNVC_MMR6); |
772 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
773 | 1 | Rt))); |
774 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
775 | 1 | Rs))); |
776 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
777 | 2 | } else if (Rs != 0 && Rs < Rt1 ) { |
778 | 1 | MI.setOpcode(Mips::BNEC_MMR6); |
779 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
780 | 1 | Rs))); |
781 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
782 | 1 | Rt))); |
783 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
784 | 1 | } else { |
785 | 1 | MI.setOpcode(Mips::BNEZALC_MMR6); |
786 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
787 | 1 | Rt))); |
788 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
789 | 1 | } |
790 | 3 | |
791 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
792 | 3 | |
793 | 3 | return MCDisassembler::Success; |
794 | 3 | } |
795 | | |
796 | | template <typename InsnType> |
797 | | static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, |
798 | | uint64_t Address, |
799 | 3 | const void *Decoder) { |
800 | 3 | // We have: |
801 | 3 | // 0b110101 ttttt sssss iiiiiiiiiiiiiiii |
802 | 3 | // Invalid if rt == 0 |
803 | 3 | // BGTZC_MMR6 if rs == 0 && rt != 0 |
804 | 3 | // BLTZC_MMR6 if rs == rt && rt != 0 |
805 | 3 | // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 |
806 | 3 | |
807 | 3 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
808 | 3 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
809 | 3 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
810 | 3 | bool HasRs = false; |
811 | 3 | |
812 | 3 | if (Rt == 0) |
813 | 0 | return MCDisassembler::Fail; |
814 | 3 | else if (Rs == 0) |
815 | 1 | MI.setOpcode(Mips::BGTZC_MMR6); |
816 | 2 | else if (Rs == Rt) |
817 | 1 | MI.setOpcode(Mips::BLTZC_MMR6); |
818 | 1 | else { |
819 | 1 | MI.setOpcode(Mips::BLTC_MMR6); |
820 | 1 | HasRs = true; |
821 | 1 | } |
822 | 3 | |
823 | 3 | if (HasRs) |
824 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
825 | 1 | Rs))); |
826 | 3 | |
827 | 3 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
828 | 3 | Rt))); |
829 | 3 | |
830 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
831 | 3 | |
832 | 3 | return MCDisassembler::Success; |
833 | 3 | } |
834 | | |
835 | | template <typename InsnType> |
836 | | static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, |
837 | | uint64_t Address, |
838 | 5 | const void *Decoder) { |
839 | 5 | // We have: |
840 | 5 | // 0b111101 ttttt sssss iiiiiiiiiiiiiiii |
841 | 5 | // Invalid if rt == 0 |
842 | 5 | // BLEZC_MMR6 if rs == 0 && rt != 0 |
843 | 5 | // BGEZC_MMR6 if rs == rt && rt != 0 |
844 | 5 | // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 |
845 | 5 | |
846 | 5 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
847 | 5 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
848 | 5 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
849 | 5 | bool HasRs = false; |
850 | 5 | |
851 | 5 | if (Rt == 0) |
852 | 2 | return MCDisassembler::Fail; |
853 | 3 | else if (Rs == 0) |
854 | 1 | MI.setOpcode(Mips::BLEZC_MMR6); |
855 | 2 | else if (Rs == Rt) |
856 | 1 | MI.setOpcode(Mips::BGEZC_MMR6); |
857 | 1 | else { |
858 | 1 | HasRs = true; |
859 | 1 | MI.setOpcode(Mips::BGEC_MMR6); |
860 | 1 | } |
861 | 5 | |
862 | 5 | if (3 HasRs3 ) |
863 | 1 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
864 | 1 | Rs))); |
865 | 3 | |
866 | 3 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
867 | 3 | Rt))); |
868 | 3 | |
869 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
870 | 3 | |
871 | 3 | return MCDisassembler::Success; |
872 | 5 | } |
873 | | |
874 | | template <typename InsnType> |
875 | | static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, |
876 | | uint64_t Address, |
877 | 24 | const void *Decoder) { |
878 | 24 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
879 | 24 | // (otherwise we would have matched the BLEZL instruction from the earlier |
880 | 24 | // ISA's instead). |
881 | 24 | // |
882 | 24 | // We have: |
883 | 24 | // 0b010110 sssss ttttt iiiiiiiiiiiiiiii |
884 | 24 | // Invalid if rs == 0 |
885 | 24 | // BLEZC if rs == 0 && rt != 0 |
886 | 24 | // BGEZC if rs == rt && rt != 0 |
887 | 24 | // BGEC if rs != rt && rs != 0 && rt != 0 |
888 | 24 | |
889 | 24 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
890 | 24 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
891 | 24 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
892 | 24 | bool HasRs = false; |
893 | 24 | |
894 | 24 | if (Rt == 0) |
895 | 0 | return MCDisassembler::Fail; |
896 | 24 | else if (Rs == 0) |
897 | 8 | MI.setOpcode(Mips::BLEZC); |
898 | 16 | else if (Rs == Rt) |
899 | 8 | MI.setOpcode(Mips::BGEZC); |
900 | 8 | else { |
901 | 8 | HasRs = true; |
902 | 8 | MI.setOpcode(Mips::BGEC); |
903 | 8 | } |
904 | 24 | |
905 | 24 | if (HasRs) |
906 | 8 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
907 | 8 | Rs))); |
908 | 24 | |
909 | 24 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
910 | 24 | Rt))); |
911 | 24 | |
912 | 24 | MI.addOperand(MCOperand::createImm(Imm)); |
913 | 24 | |
914 | 24 | return MCDisassembler::Success; |
915 | 24 | } |
916 | | |
917 | | template <typename InsnType> |
918 | | static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, |
919 | | uint64_t Address, |
920 | 24 | const void *Decoder) { |
921 | 24 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
922 | 24 | // (otherwise we would have matched the BGTZL instruction from the earlier |
923 | 24 | // ISA's instead). |
924 | 24 | // |
925 | 24 | // We have: |
926 | 24 | // 0b010111 sssss ttttt iiiiiiiiiiiiiiii |
927 | 24 | // Invalid if rs == 0 |
928 | 24 | // BGTZC if rs == 0 && rt != 0 |
929 | 24 | // BLTZC if rs == rt && rt != 0 |
930 | 24 | // BLTC if rs != rt && rs != 0 && rt != 0 |
931 | 24 | |
932 | 24 | bool HasRs = false; |
933 | 24 | |
934 | 24 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
935 | 24 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
936 | 24 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
937 | 24 | |
938 | 24 | if (Rt == 0) |
939 | 0 | return MCDisassembler::Fail; |
940 | 24 | else if (Rs == 0) |
941 | 8 | MI.setOpcode(Mips::BGTZC); |
942 | 16 | else if (Rs == Rt) |
943 | 8 | MI.setOpcode(Mips::BLTZC); |
944 | 8 | else { |
945 | 8 | MI.setOpcode(Mips::BLTC); |
946 | 8 | HasRs = true; |
947 | 8 | } |
948 | 24 | |
949 | 24 | if (HasRs) |
950 | 8 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
951 | 8 | Rs))); |
952 | 24 | |
953 | 24 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
954 | 24 | Rt))); |
955 | 24 | |
956 | 24 | MI.addOperand(MCOperand::createImm(Imm)); |
957 | 24 | |
958 | 24 | return MCDisassembler::Success; |
959 | 24 | } |
960 | | |
961 | | template <typename InsnType> |
962 | | static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, |
963 | | uint64_t Address, |
964 | 24 | const void *Decoder) { |
965 | 24 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
966 | 24 | // (otherwise we would have matched the BGTZ instruction from the earlier |
967 | 24 | // ISA's instead). |
968 | 24 | // |
969 | 24 | // We have: |
970 | 24 | // 0b000111 sssss ttttt iiiiiiiiiiiiiiii |
971 | 24 | // BGTZ if rt == 0 |
972 | 24 | // BGTZALC if rs == 0 && rt != 0 |
973 | 24 | // BLTZALC if rs != 0 && rs == rt |
974 | 24 | // BLTUC if rs != 0 && rs != rt |
975 | 24 | |
976 | 24 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
977 | 24 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
978 | 24 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
979 | 24 | bool HasRs = false; |
980 | 24 | bool HasRt = false; |
981 | 24 | |
982 | 24 | if (Rt == 0) { |
983 | 0 | MI.setOpcode(Mips::BGTZ); |
984 | 0 | HasRs = true; |
985 | 24 | } else if (Rs == 0) { |
986 | 8 | MI.setOpcode(Mips::BGTZALC); |
987 | 8 | HasRt = true; |
988 | 16 | } else if (Rs == Rt) { |
989 | 8 | MI.setOpcode(Mips::BLTZALC); |
990 | 8 | HasRs = true; |
991 | 8 | } else { |
992 | 8 | MI.setOpcode(Mips::BLTUC); |
993 | 8 | HasRs = true; |
994 | 8 | HasRt = true; |
995 | 8 | } |
996 | 24 | |
997 | 24 | if (HasRs) |
998 | 16 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
999 | 16 | Rs))); |
1000 | 24 | |
1001 | 24 | if (HasRt) |
1002 | 16 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
1003 | 16 | Rt))); |
1004 | 24 | |
1005 | 24 | MI.addOperand(MCOperand::createImm(Imm)); |
1006 | 24 | |
1007 | 24 | return MCDisassembler::Success; |
1008 | 24 | } |
1009 | | |
1010 | | template <typename InsnType> |
1011 | | static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, |
1012 | | uint64_t Address, |
1013 | 24 | const void *Decoder) { |
1014 | 24 | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
1015 | 24 | // (otherwise we would have matched the BLEZL instruction from the earlier |
1016 | 24 | // ISA's instead). |
1017 | 24 | // |
1018 | 24 | // We have: |
1019 | 24 | // 0b000110 sssss ttttt iiiiiiiiiiiiiiii |
1020 | 24 | // Invalid if rs == 0 |
1021 | 24 | // BLEZALC if rs == 0 && rt != 0 |
1022 | 24 | // BGEZALC if rs == rt && rt != 0 |
1023 | 24 | // BGEUC if rs != rt && rs != 0 && rt != 0 |
1024 | 24 | |
1025 | 24 | InsnType Rs = fieldFromInstruction(insn, 21, 5); |
1026 | 24 | InsnType Rt = fieldFromInstruction(insn, 16, 5); |
1027 | 24 | int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
1028 | 24 | bool HasRs = false; |
1029 | 24 | |
1030 | 24 | if (Rt == 0) |
1031 | 0 | return MCDisassembler::Fail; |
1032 | 24 | else if (Rs == 0) |
1033 | 8 | MI.setOpcode(Mips::BLEZALC); |
1034 | 16 | else if (Rs == Rt) |
1035 | 8 | MI.setOpcode(Mips::BGEZALC); |
1036 | 8 | else { |
1037 | 8 | HasRs = true; |
1038 | 8 | MI.setOpcode(Mips::BGEUC); |
1039 | 8 | } |
1040 | 24 | |
1041 | 24 | if (HasRs) |
1042 | 8 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
1043 | 8 | Rs))); |
1044 | 24 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, |
1045 | 24 | Rt))); |
1046 | 24 | |
1047 | 24 | MI.addOperand(MCOperand::createImm(Imm)); |
1048 | 24 | |
1049 | 24 | return MCDisassembler::Success; |
1050 | 24 | } |
1051 | | |
1052 | | // Override the generated disassembler to produce DEXT all the time. This is |
1053 | | // for feature / behaviour parity with binutils. |
1054 | | template <typename InsnType> |
1055 | | static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, |
1056 | 19 | const void *Decoder) { |
1057 | 19 | unsigned Msbd = fieldFromInstruction(Insn, 11, 5); |
1058 | 19 | unsigned Lsb = fieldFromInstruction(Insn, 6, 5); |
1059 | 19 | unsigned Size = 0; |
1060 | 19 | unsigned Pos = 0; |
1061 | 19 | |
1062 | 19 | switch (MI.getOpcode()) { |
1063 | 19 | case Mips::DEXT: |
1064 | 13 | Pos = Lsb; |
1065 | 13 | Size = Msbd + 1; |
1066 | 13 | break; |
1067 | 19 | case Mips::DEXTM: |
1068 | 3 | Pos = Lsb; |
1069 | 3 | Size = Msbd + 1 + 32; |
1070 | 3 | break; |
1071 | 19 | case Mips::DEXTU: |
1072 | 3 | Pos = Lsb + 32; |
1073 | 3 | Size = Msbd + 1; |
1074 | 3 | break; |
1075 | 19 | default: |
1076 | 0 | llvm_unreachable("Unknown DEXT instruction!"); |
1077 | 19 | } |
1078 | 19 | |
1079 | 19 | MI.setOpcode(Mips::DEXT); |
1080 | 19 | |
1081 | 19 | InsnType Rs = fieldFromInstruction(Insn, 21, 5); |
1082 | 19 | InsnType Rt = fieldFromInstruction(Insn, 16, 5); |
1083 | 19 | |
1084 | 19 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); |
1085 | 19 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); |
1086 | 19 | MI.addOperand(MCOperand::createImm(Pos)); |
1087 | 19 | MI.addOperand(MCOperand::createImm(Size)); |
1088 | 19 | |
1089 | 19 | return MCDisassembler::Success; |
1090 | 19 | } |
1091 | | |
1092 | | // Override the generated disassembler to produce DINS all the time. This is |
1093 | | // for feature / behaviour parity with binutils. |
1094 | | template <typename InsnType> |
1095 | | static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, |
1096 | 15 | const void *Decoder) { |
1097 | 15 | unsigned Msbd = fieldFromInstruction(Insn, 11, 5); |
1098 | 15 | unsigned Lsb = fieldFromInstruction(Insn, 6, 5); |
1099 | 15 | unsigned Size = 0; |
1100 | 15 | unsigned Pos = 0; |
1101 | 15 | |
1102 | 15 | switch (MI.getOpcode()) { |
1103 | 15 | case Mips::DINS: |
1104 | 9 | Pos = Lsb; |
1105 | 9 | Size = Msbd + 1 - Pos; |
1106 | 9 | break; |
1107 | 15 | case Mips::DINSM: |
1108 | 3 | Pos = Lsb; |
1109 | 3 | Size = Msbd + 33 - Pos; |
1110 | 3 | break; |
1111 | 15 | case Mips::DINSU: |
1112 | 3 | Pos = Lsb + 32; |
1113 | 3 | // mbsd = pos + size - 33 |
1114 | 3 | // mbsd - pos + 33 = size |
1115 | 3 | Size = Msbd + 33 - Pos; |
1116 | 3 | break; |
1117 | 15 | default: |
1118 | 0 | llvm_unreachable("Unknown DINS instruction!"); |
1119 | 15 | } |
1120 | 15 | |
1121 | 15 | InsnType Rs = fieldFromInstruction(Insn, 21, 5); |
1122 | 15 | InsnType Rt = fieldFromInstruction(Insn, 16, 5); |
1123 | 15 | |
1124 | 15 | MI.setOpcode(Mips::DINS); |
1125 | 15 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); |
1126 | 15 | MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); |
1127 | 15 | MI.addOperand(MCOperand::createImm(Pos)); |
1128 | 15 | MI.addOperand(MCOperand::createImm(Size)); |
1129 | 15 | |
1130 | 15 | return MCDisassembler::Success; |
1131 | 15 | } |
1132 | | /// Read two bytes from the ArrayRef and return 16 bit halfword sorted |
1133 | | /// according to the given endianness. |
1134 | | static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, |
1135 | | uint64_t &Size, uint32_t &Insn, |
1136 | 1.32k | bool IsBigEndian) { |
1137 | 1.32k | // We want to read exactly 2 Bytes of data. |
1138 | 1.32k | if (Bytes.size() < 2) { |
1139 | 1 | Size = 0; |
1140 | 1 | return MCDisassembler::Fail; |
1141 | 1 | } |
1142 | 1.32k | |
1143 | 1.32k | if (IsBigEndian) { |
1144 | 955 | Insn = (Bytes[0] << 8) | Bytes[1]; |
1145 | 955 | } else { |
1146 | 371 | Insn = (Bytes[1] << 8) | Bytes[0]; |
1147 | 371 | } |
1148 | 1.32k | |
1149 | 1.32k | return MCDisassembler::Success; |
1150 | 1.32k | } |
1151 | | |
1152 | | /// Read four bytes from the ArrayRef and return 32 bit word sorted |
1153 | | /// according to the given endianness. |
1154 | | static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, |
1155 | | uint64_t &Size, uint32_t &Insn, |
1156 | 63.9k | bool IsBigEndian, bool IsMicroMips) { |
1157 | 63.9k | // We want to read exactly 4 Bytes of data. |
1158 | 63.9k | if (Bytes.size() < 4) { |
1159 | 3 | Size = 0; |
1160 | 3 | return MCDisassembler::Fail; |
1161 | 3 | } |
1162 | 63.9k | |
1163 | 63.9k | // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) |
1164 | 63.9k | // always precede the low 16 bits in the instruction stream (that is, they |
1165 | 63.9k | // are placed at lower addresses in the instruction stream). |
1166 | 63.9k | // |
1167 | 63.9k | // microMIPS byte ordering: |
1168 | 63.9k | // Big-endian: 0 | 1 | 2 | 3 |
1169 | 63.9k | // Little-endian: 1 | 0 | 3 | 2 |
1170 | 63.9k | |
1171 | 63.9k | if (IsBigEndian) { |
1172 | 10.2k | // Encoded as a big-endian 32-bit word in the stream. |
1173 | 10.2k | Insn = |
1174 | 10.2k | (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); |
1175 | 53.6k | } else { |
1176 | 53.6k | if (IsMicroMips) { |
1177 | 286 | Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | |
1178 | 286 | (Bytes[1] << 24); |
1179 | 53.3k | } else { |
1180 | 53.3k | Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | |
1181 | 53.3k | (Bytes[3] << 24); |
1182 | 53.3k | } |
1183 | 53.6k | } |
1184 | 63.9k | |
1185 | 63.9k | return MCDisassembler::Success; |
1186 | 63.9k | } |
1187 | | |
1188 | | DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, |
1189 | | ArrayRef<uint8_t> Bytes, |
1190 | | uint64_t Address, |
1191 | | raw_ostream &VStream, |
1192 | 64.1k | raw_ostream &CStream) const { |
1193 | 64.1k | uint32_t Insn; |
1194 | 64.1k | DecodeStatus Result; |
1195 | 64.1k | Size = 0; |
1196 | 64.1k | |
1197 | 64.1k | if (IsMicroMips) { |
1198 | 1.32k | Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); |
1199 | 1.32k | if (Result == MCDisassembler::Fail) |
1200 | 1 | return MCDisassembler::Fail; |
1201 | 1.32k | |
1202 | 1.32k | if (hasMips32r6()) { |
1203 | 660 | DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); |
1204 | 660 | // Calling the auto-generated decoder function for microMIPS32R6 |
1205 | 660 | // 16-bit instructions. |
1206 | 660 | Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, |
1207 | 660 | Address, this, STI); |
1208 | 660 | if (Result != MCDisassembler::Fail) { |
1209 | 49 | Size = 2; |
1210 | 49 | return Result; |
1211 | 49 | } |
1212 | 1.27k | } |
1213 | 1.27k | |
1214 | 1.27k | DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); |
1215 | 1.27k | // Calling the auto-generated decoder function for microMIPS 16-bit |
1216 | 1.27k | // instructions. |
1217 | 1.27k | Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, |
1218 | 1.27k | this, STI); |
1219 | 1.27k | if (Result != MCDisassembler::Fail) { |
1220 | 188 | Size = 2; |
1221 | 188 | return Result; |
1222 | 188 | } |
1223 | 1.08k | |
1224 | 1.08k | Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); |
1225 | 1.08k | if (Result == MCDisassembler::Fail) |
1226 | 1 | return MCDisassembler::Fail; |
1227 | 1.08k | |
1228 | 1.08k | if (hasMips32r6()) { |
1229 | 590 | DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); |
1230 | 590 | // Calling the auto-generated decoder function. |
1231 | 590 | Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, |
1232 | 590 | this, STI); |
1233 | 590 | if (Result != MCDisassembler::Fail) { |
1234 | 255 | Size = 4; |
1235 | 255 | return Result; |
1236 | 255 | } |
1237 | 833 | } |
1238 | 833 | |
1239 | 833 | DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); |
1240 | 833 | // Calling the auto-generated decoder function. |
1241 | 833 | Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, |
1242 | 833 | this, STI); |
1243 | 833 | if (Result != MCDisassembler::Fail) { |
1244 | 803 | Size = 4; |
1245 | 803 | return Result; |
1246 | 803 | } |
1247 | 30 | |
1248 | 30 | if (isFP64()) { |
1249 | 26 | DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); |
1250 | 26 | Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, |
1251 | 26 | Address, this, STI); |
1252 | 26 | if (Result != MCDisassembler::Fail) { |
1253 | 26 | Size = 4; |
1254 | 26 | return Result; |
1255 | 26 | } |
1256 | 4 | } |
1257 | 4 | |
1258 | 4 | // This is an invalid instruction. Claim that the Size is 2 bytes. Since |
1259 | 4 | // microMIPS instructions have a minimum alignment of 2, the next 2 bytes |
1260 | 4 | // could form a valid instruction. The two bytes we rejected as an |
1261 | 4 | // instruction could have actually beeen an inline constant pool that is |
1262 | 4 | // unconditionally branched over. |
1263 | 4 | Size = 2; |
1264 | 4 | return MCDisassembler::Fail; |
1265 | 4 | } |
1266 | 62.8k | |
1267 | 62.8k | // Attempt to read the instruction so that we can attempt to decode it. If |
1268 | 62.8k | // the buffer is not 4 bytes long, let the higher level logic figure out |
1269 | 62.8k | // what to do with a size of zero and MCDisassembler::Fail. |
1270 | 62.8k | Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); |
1271 | 62.8k | if (Result == MCDisassembler::Fail) |
1272 | 2 | return MCDisassembler::Fail; |
1273 | 62.8k | |
1274 | 62.8k | // The only instruction size for standard encoded MIPS. |
1275 | 62.8k | Size = 4; |
1276 | 62.8k | |
1277 | 62.8k | if (hasCOP3()) { |
1278 | 642 | DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); |
1279 | 642 | Result = |
1280 | 642 | decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); |
1281 | 642 | if (Result != MCDisassembler::Fail) |
1282 | 14 | return Result; |
1283 | 62.8k | } |
1284 | 62.8k | |
1285 | 62.8k | if (hasMips32r6() && isGP64()1.02k ) { |
1286 | 526 | DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); |
1287 | 526 | Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, |
1288 | 526 | Address, this, STI); |
1289 | 526 | if (Result != MCDisassembler::Fail) |
1290 | 125 | return Result; |
1291 | 62.6k | } |
1292 | 62.6k | |
1293 | 62.6k | if (hasMips32r6() && isPTR64()898 ) { |
1294 | 0 | DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); |
1295 | 0 | Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, |
1296 | 0 | Address, this, STI); |
1297 | 0 | if (Result != MCDisassembler::Fail) |
1298 | 0 | return Result; |
1299 | 62.6k | } |
1300 | 62.6k | |
1301 | 62.6k | if (hasMips32r6()) { |
1302 | 898 | DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); |
1303 | 898 | Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, |
1304 | 898 | Address, this, STI); |
1305 | 898 | if (Result != MCDisassembler::Fail) |
1306 | 587 | return Result; |
1307 | 62.1k | } |
1308 | 62.1k | |
1309 | 62.1k | if (hasMips2() && isPTR64()61.8k ) { |
1310 | 0 | DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); |
1311 | 0 | Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, |
1312 | 0 | Address, this, STI); |
1313 | 0 | if (Result != MCDisassembler::Fail) |
1314 | 0 | return Result; |
1315 | 62.1k | } |
1316 | 62.1k | |
1317 | 62.1k | if (hasCnMips()) { |
1318 | 0 | DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); |
1319 | 0 | Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, |
1320 | 0 | Address, this, STI); |
1321 | 0 | if (Result != MCDisassembler::Fail) |
1322 | 0 | return Result; |
1323 | 62.1k | } |
1324 | 62.1k | |
1325 | 62.1k | if (isGP64()) { |
1326 | 5.55k | DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); |
1327 | 5.55k | Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, |
1328 | 5.55k | Address, this, STI); |
1329 | 5.55k | if (Result != MCDisassembler::Fail) |
1330 | 1.10k | return Result; |
1331 | 61.0k | } |
1332 | 61.0k | |
1333 | 61.0k | if (isFP64()) { |
1334 | 6.26k | DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); |
1335 | 6.26k | Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, |
1336 | 6.26k | Address, this, STI); |
1337 | 6.26k | if (Result != MCDisassembler::Fail) |
1338 | 1.26k | return Result; |
1339 | 59.7k | } |
1340 | 59.7k | |
1341 | 59.7k | DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); |
1342 | 59.7k | // Calling the auto-generated decoder function. |
1343 | 59.7k | Result = |
1344 | 59.7k | decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); |
1345 | 59.7k | if (Result != MCDisassembler::Fail) |
1346 | 59.2k | return Result; |
1347 | 539 | |
1348 | 539 | return MCDisassembler::Fail; |
1349 | 539 | } |
1350 | | |
1351 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, |
1352 | | unsigned RegNo, |
1353 | | uint64_t Address, |
1354 | 0 | const void *Decoder) { |
1355 | 0 | return MCDisassembler::Fail; |
1356 | 0 | } |
1357 | | |
1358 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, |
1359 | | unsigned RegNo, |
1360 | | uint64_t Address, |
1361 | 2.27k | const void *Decoder) { |
1362 | 2.27k | if (RegNo > 31) |
1363 | 0 | return MCDisassembler::Fail; |
1364 | 2.27k | |
1365 | 2.27k | unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); |
1366 | 2.27k | Inst.addOperand(MCOperand::createReg(Reg)); |
1367 | 2.27k | return MCDisassembler::Success; |
1368 | 2.27k | } |
1369 | | |
1370 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, |
1371 | | unsigned RegNo, |
1372 | | uint64_t Address, |
1373 | 212 | const void *Decoder) { |
1374 | 212 | if (RegNo > 7) |
1375 | 0 | return MCDisassembler::Fail; |
1376 | 212 | unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); |
1377 | 212 | Inst.addOperand(MCOperand::createReg(Reg)); |
1378 | 212 | return MCDisassembler::Success; |
1379 | 212 | } |
1380 | | |
1381 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, |
1382 | | unsigned RegNo, |
1383 | | uint64_t Address, |
1384 | 12 | const void *Decoder) { |
1385 | 12 | if (RegNo > 7) |
1386 | 0 | return MCDisassembler::Fail; |
1387 | 12 | unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); |
1388 | 12 | Inst.addOperand(MCOperand::createReg(Reg)); |
1389 | 12 | return MCDisassembler::Success; |
1390 | 12 | } |
1391 | | |
1392 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, |
1393 | | unsigned RegNo, |
1394 | | uint64_t Address, |
1395 | 12 | const void *Decoder) { |
1396 | 12 | if (RegNo > 7) |
1397 | 0 | return MCDisassembler::Fail; |
1398 | 12 | unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); |
1399 | 12 | Inst.addOperand(MCOperand::createReg(Reg)); |
1400 | 12 | return MCDisassembler::Success; |
1401 | 12 | } |
1402 | | |
1403 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, |
1404 | | unsigned RegNo, |
1405 | | uint64_t Address, |
1406 | 110k | const void *Decoder) { |
1407 | 110k | if (RegNo > 31) |
1408 | 0 | return MCDisassembler::Fail; |
1409 | 110k | unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); |
1410 | 110k | Inst.addOperand(MCOperand::createReg(Reg)); |
1411 | 110k | return MCDisassembler::Success; |
1412 | 110k | } |
1413 | | |
1414 | | static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, |
1415 | | unsigned RegNo, |
1416 | | uint64_t Address, |
1417 | 406 | const void *Decoder) { |
1418 | 406 | if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) |
1419 | 206 | return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); |
1420 | 200 | |
1421 | 200 | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
1422 | 200 | } |
1423 | | |
1424 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, |
1425 | | unsigned RegNo, |
1426 | | uint64_t Address, |
1427 | 621 | const void *Decoder) { |
1428 | 621 | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
1429 | 621 | } |
1430 | | |
1431 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, |
1432 | | unsigned RegNo, |
1433 | | uint64_t Address, |
1434 | 2.69k | const void *Decoder) { |
1435 | 2.69k | if (RegNo > 31) |
1436 | 0 | return MCDisassembler::Fail; |
1437 | 2.69k | |
1438 | 2.69k | unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); |
1439 | 2.69k | Inst.addOperand(MCOperand::createReg(Reg)); |
1440 | 2.69k | return MCDisassembler::Success; |
1441 | 2.69k | } |
1442 | | |
1443 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, |
1444 | | unsigned RegNo, |
1445 | | uint64_t Address, |
1446 | 4.17k | const void *Decoder) { |
1447 | 4.17k | if (RegNo > 31) |
1448 | 0 | return MCDisassembler::Fail; |
1449 | 4.17k | |
1450 | 4.17k | unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); |
1451 | 4.17k | Inst.addOperand(MCOperand::createReg(Reg)); |
1452 | 4.17k | return MCDisassembler::Success; |
1453 | 4.17k | } |
1454 | | |
1455 | | static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, |
1456 | | unsigned RegNo, |
1457 | | uint64_t Address, |
1458 | 98 | const void *Decoder) { |
1459 | 98 | if (RegNo > 31) |
1460 | 0 | return MCDisassembler::Fail; |
1461 | 98 | unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); |
1462 | 98 | Inst.addOperand(MCOperand::createReg(Reg)); |
1463 | 98 | return MCDisassembler::Success; |
1464 | 98 | } |
1465 | | |
1466 | | static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, |
1467 | | unsigned RegNo, |
1468 | | uint64_t Address, |
1469 | 1.48k | const void *Decoder) { |
1470 | 1.48k | if (RegNo > 7) |
1471 | 0 | return MCDisassembler::Fail; |
1472 | 1.48k | unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); |
1473 | 1.48k | Inst.addOperand(MCOperand::createReg(Reg)); |
1474 | 1.48k | return MCDisassembler::Success; |
1475 | 1.48k | } |
1476 | | |
1477 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, |
1478 | | uint64_t Address, |
1479 | 165 | const void *Decoder) { |
1480 | 165 | if (RegNo > 31) |
1481 | 0 | return MCDisassembler::Fail; |
1482 | 165 | |
1483 | 165 | unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); |
1484 | 165 | Inst.addOperand(MCOperand::createReg(Reg)); |
1485 | 165 | return MCDisassembler::Success; |
1486 | 165 | } |
1487 | | |
1488 | | static DecodeStatus DecodeMem(MCInst &Inst, |
1489 | | unsigned Insn, |
1490 | | uint64_t Address, |
1491 | 976 | const void *Decoder) { |
1492 | 976 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1493 | 976 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1494 | 976 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1495 | 976 | |
1496 | 976 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1497 | 976 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1498 | 976 | |
1499 | 976 | if (Inst.getOpcode() == Mips::SC || |
1500 | 976 | Inst.getOpcode() == Mips::SCD919 ) |
1501 | 71 | Inst.addOperand(MCOperand::createReg(Reg)); |
1502 | 976 | |
1503 | 976 | Inst.addOperand(MCOperand::createReg(Reg)); |
1504 | 976 | Inst.addOperand(MCOperand::createReg(Base)); |
1505 | 976 | Inst.addOperand(MCOperand::createImm(Offset)); |
1506 | 976 | |
1507 | 976 | return MCDisassembler::Success; |
1508 | 976 | } |
1509 | | |
1510 | | static DecodeStatus DecodeMemEVA(MCInst &Inst, |
1511 | | unsigned Insn, |
1512 | | uint64_t Address, |
1513 | 288 | const void *Decoder) { |
1514 | 288 | int Offset = SignExtend32<9>(Insn >> 7); |
1515 | 288 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1516 | 288 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1517 | 288 | |
1518 | 288 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1519 | 288 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1520 | 288 | |
1521 | 288 | if (Inst.getOpcode() == Mips::SCE) |
1522 | 24 | Inst.addOperand(MCOperand::createReg(Reg)); |
1523 | 288 | |
1524 | 288 | Inst.addOperand(MCOperand::createReg(Reg)); |
1525 | 288 | Inst.addOperand(MCOperand::createReg(Base)); |
1526 | 288 | Inst.addOperand(MCOperand::createImm(Offset)); |
1527 | 288 | |
1528 | 288 | return MCDisassembler::Success; |
1529 | 288 | } |
1530 | | |
1531 | | static DecodeStatus DecodeLoadByte15(MCInst &Inst, |
1532 | | unsigned Insn, |
1533 | | uint64_t Address, |
1534 | 2 | const void *Decoder) { |
1535 | 2 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1536 | 2 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1537 | 2 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1538 | 2 | |
1539 | 2 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1540 | 2 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1541 | 2 | |
1542 | 2 | Inst.addOperand(MCOperand::createReg(Reg)); |
1543 | 2 | Inst.addOperand(MCOperand::createReg(Base)); |
1544 | 2 | Inst.addOperand(MCOperand::createImm(Offset)); |
1545 | 2 | |
1546 | 2 | return MCDisassembler::Success; |
1547 | 2 | } |
1548 | | |
1549 | | static DecodeStatus DecodeCacheOp(MCInst &Inst, |
1550 | | unsigned Insn, |
1551 | | uint64_t Address, |
1552 | 66 | const void *Decoder) { |
1553 | 66 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1554 | 66 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); |
1555 | 66 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1556 | 66 | |
1557 | 66 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1558 | 66 | |
1559 | 66 | Inst.addOperand(MCOperand::createReg(Base)); |
1560 | 66 | Inst.addOperand(MCOperand::createImm(Offset)); |
1561 | 66 | Inst.addOperand(MCOperand::createImm(Hint)); |
1562 | 66 | |
1563 | 66 | return MCDisassembler::Success; |
1564 | 66 | } |
1565 | | |
1566 | | static DecodeStatus DecodeCacheOpMM(MCInst &Inst, |
1567 | | unsigned Insn, |
1568 | | uint64_t Address, |
1569 | 6 | const void *Decoder) { |
1570 | 6 | int Offset = SignExtend32<12>(Insn & 0xfff); |
1571 | 6 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1572 | 6 | unsigned Hint = fieldFromInstruction(Insn, 21, 5); |
1573 | 6 | |
1574 | 6 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1575 | 6 | |
1576 | 6 | Inst.addOperand(MCOperand::createReg(Base)); |
1577 | 6 | Inst.addOperand(MCOperand::createImm(Offset)); |
1578 | 6 | Inst.addOperand(MCOperand::createImm(Hint)); |
1579 | 6 | |
1580 | 6 | return MCDisassembler::Success; |
1581 | 6 | } |
1582 | | |
1583 | | static DecodeStatus DecodePrefeOpMM(MCInst &Inst, |
1584 | | unsigned Insn, |
1585 | | uint64_t Address, |
1586 | 6 | const void *Decoder) { |
1587 | 6 | int Offset = SignExtend32<9>(Insn & 0x1ff); |
1588 | 6 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1589 | 6 | unsigned Hint = fieldFromInstruction(Insn, 21, 5); |
1590 | 6 | |
1591 | 6 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1592 | 6 | |
1593 | 6 | Inst.addOperand(MCOperand::createReg(Base)); |
1594 | 6 | Inst.addOperand(MCOperand::createImm(Offset)); |
1595 | 6 | Inst.addOperand(MCOperand::createImm(Hint)); |
1596 | 6 | |
1597 | 6 | return MCDisassembler::Success; |
1598 | 6 | } |
1599 | | |
1600 | | static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, |
1601 | | unsigned Insn, |
1602 | | uint64_t Address, |
1603 | 56 | const void *Decoder) { |
1604 | 56 | int Offset = SignExtend32<9>(Insn >> 7); |
1605 | 56 | unsigned Hint = fieldFromInstruction(Insn, 16, 5); |
1606 | 56 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1607 | 56 | |
1608 | 56 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1609 | 56 | |
1610 | 56 | Inst.addOperand(MCOperand::createReg(Base)); |
1611 | 56 | Inst.addOperand(MCOperand::createImm(Offset)); |
1612 | 56 | Inst.addOperand(MCOperand::createImm(Hint)); |
1613 | 56 | |
1614 | 56 | return MCDisassembler::Success; |
1615 | 56 | } |
1616 | | |
1617 | | static DecodeStatus DecodeSyncI(MCInst &Inst, |
1618 | | unsigned Insn, |
1619 | | uint64_t Address, |
1620 | 14 | const void *Decoder) { |
1621 | 14 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1622 | 14 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1623 | 14 | |
1624 | 14 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1625 | 14 | |
1626 | 14 | Inst.addOperand(MCOperand::createReg(Base)); |
1627 | 14 | Inst.addOperand(MCOperand::createImm(Offset)); |
1628 | 14 | |
1629 | 14 | return MCDisassembler::Success; |
1630 | 14 | } |
1631 | | |
1632 | | static DecodeStatus DecodeSynciR6(MCInst &Inst, |
1633 | | unsigned Insn, |
1634 | | uint64_t Address, |
1635 | 1 | const void *Decoder) { |
1636 | 1 | int Immediate = SignExtend32<16>(Insn & 0xffff); |
1637 | 1 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1638 | 1 | |
1639 | 1 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1640 | 1 | |
1641 | 1 | Inst.addOperand(MCOperand::createReg(Base)); |
1642 | 1 | Inst.addOperand(MCOperand::createImm(Immediate)); |
1643 | 1 | |
1644 | 1 | return MCDisassembler::Success; |
1645 | 1 | } |
1646 | | |
1647 | | static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, |
1648 | 23 | uint64_t Address, const void *Decoder) { |
1649 | 23 | int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); |
1650 | 23 | unsigned Reg = fieldFromInstruction(Insn, 6, 5); |
1651 | 23 | unsigned Base = fieldFromInstruction(Insn, 11, 5); |
1652 | 23 | |
1653 | 23 | Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); |
1654 | 23 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1655 | 23 | |
1656 | 23 | Inst.addOperand(MCOperand::createReg(Reg)); |
1657 | 23 | Inst.addOperand(MCOperand::createReg(Base)); |
1658 | 23 | |
1659 | 23 | // The immediate field of an LD/ST instruction is scaled which means it must |
1660 | 23 | // be multiplied (when decoding) by the size (in bytes) of the instructions' |
1661 | 23 | // data format. |
1662 | 23 | // .b - 1 byte |
1663 | 23 | // .h - 2 bytes |
1664 | 23 | // .w - 4 bytes |
1665 | 23 | // .d - 8 bytes |
1666 | 23 | switch(Inst.getOpcode()) |
1667 | 23 | { |
1668 | 23 | default: |
1669 | 0 | assert(false && "Unexpected instruction"); |
1670 | 0 | return MCDisassembler::Fail; |
1671 | 23 | break0 ; |
1672 | 23 | case Mips::LD_B: |
1673 | 3 | case Mips::ST_B: |
1674 | 3 | Inst.addOperand(MCOperand::createImm(Offset)); |
1675 | 3 | break; |
1676 | 5 | case Mips::LD_H: |
1677 | 5 | case Mips::ST_H: |
1678 | 5 | Inst.addOperand(MCOperand::createImm(Offset * 2)); |
1679 | 5 | break; |
1680 | 6 | case Mips::LD_W: |
1681 | 6 | case Mips::ST_W: |
1682 | 6 | Inst.addOperand(MCOperand::createImm(Offset * 4)); |
1683 | 6 | break; |
1684 | 9 | case Mips::LD_D: |
1685 | 9 | case Mips::ST_D: |
1686 | 9 | Inst.addOperand(MCOperand::createImm(Offset * 8)); |
1687 | 9 | break; |
1688 | 23 | } |
1689 | 23 | |
1690 | 23 | return MCDisassembler::Success; |
1691 | 23 | } |
1692 | | |
1693 | | static DecodeStatus DecodeMemMMImm4(MCInst &Inst, |
1694 | | unsigned Insn, |
1695 | | uint64_t Address, |
1696 | 28 | const void *Decoder) { |
1697 | 28 | unsigned Offset = Insn & 0xf; |
1698 | 28 | unsigned Reg = fieldFromInstruction(Insn, 7, 3); |
1699 | 28 | unsigned Base = fieldFromInstruction(Insn, 4, 3); |
1700 | 28 | |
1701 | 28 | switch (Inst.getOpcode()) { |
1702 | 28 | case Mips::LBU16_MM: |
1703 | 16 | case Mips::LHU16_MM: |
1704 | 16 | case Mips::LW16_MM: |
1705 | 16 | if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) |
1706 | 16 | == MCDisassembler::Fail) |
1707 | 0 | return MCDisassembler::Fail; |
1708 | 16 | break; |
1709 | 16 | case Mips::SB16_MM: |
1710 | 12 | case Mips::SB16_MMR6: |
1711 | 12 | case Mips::SH16_MM: |
1712 | 12 | case Mips::SH16_MMR6: |
1713 | 12 | case Mips::SW16_MM: |
1714 | 12 | case Mips::SW16_MMR6: |
1715 | 12 | if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) |
1716 | 12 | == MCDisassembler::Fail) |
1717 | 0 | return MCDisassembler::Fail; |
1718 | 12 | break; |
1719 | 28 | } |
1720 | 28 | |
1721 | 28 | if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) |
1722 | 28 | == MCDisassembler::Fail) |
1723 | 0 | return MCDisassembler::Fail; |
1724 | 28 | |
1725 | 28 | switch (Inst.getOpcode()) { |
1726 | 28 | case Mips::LBU16_MM: |
1727 | 8 | if (Offset == 0xf) |
1728 | 4 | Inst.addOperand(MCOperand::createImm(-1)); |
1729 | 4 | else |
1730 | 4 | Inst.addOperand(MCOperand::createImm(Offset)); |
1731 | 8 | break; |
1732 | 28 | case Mips::SB16_MM: |
1733 | 3 | case Mips::SB16_MMR6: |
1734 | 3 | Inst.addOperand(MCOperand::createImm(Offset)); |
1735 | 3 | break; |
1736 | 7 | case Mips::LHU16_MM: |
1737 | 7 | case Mips::SH16_MM: |
1738 | 7 | case Mips::SH16_MMR6: |
1739 | 7 | Inst.addOperand(MCOperand::createImm(Offset << 1)); |
1740 | 7 | break; |
1741 | 10 | case Mips::LW16_MM: |
1742 | 10 | case Mips::SW16_MM: |
1743 | 10 | case Mips::SW16_MMR6: |
1744 | 10 | Inst.addOperand(MCOperand::createImm(Offset << 2)); |
1745 | 10 | break; |
1746 | 28 | } |
1747 | 28 | |
1748 | 28 | return MCDisassembler::Success; |
1749 | 28 | } |
1750 | | |
1751 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, |
1752 | | unsigned Insn, |
1753 | | uint64_t Address, |
1754 | 7 | const void *Decoder) { |
1755 | 7 | unsigned Offset = Insn & 0x1F; |
1756 | 7 | unsigned Reg = fieldFromInstruction(Insn, 5, 5); |
1757 | 7 | |
1758 | 7 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1759 | 7 | |
1760 | 7 | Inst.addOperand(MCOperand::createReg(Reg)); |
1761 | 7 | Inst.addOperand(MCOperand::createReg(Mips::SP)); |
1762 | 7 | Inst.addOperand(MCOperand::createImm(Offset << 2)); |
1763 | 7 | |
1764 | 7 | return MCDisassembler::Success; |
1765 | 7 | } |
1766 | | |
1767 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, |
1768 | | unsigned Insn, |
1769 | | uint64_t Address, |
1770 | 4 | const void *Decoder) { |
1771 | 4 | unsigned Offset = Insn & 0x7F; |
1772 | 4 | unsigned Reg = fieldFromInstruction(Insn, 7, 3); |
1773 | 4 | |
1774 | 4 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1775 | 4 | |
1776 | 4 | Inst.addOperand(MCOperand::createReg(Reg)); |
1777 | 4 | Inst.addOperand(MCOperand::createReg(Mips::GP)); |
1778 | 4 | Inst.addOperand(MCOperand::createImm(Offset << 2)); |
1779 | 4 | |
1780 | 4 | return MCDisassembler::Success; |
1781 | 4 | } |
1782 | | |
1783 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, |
1784 | | unsigned Insn, |
1785 | | uint64_t Address, |
1786 | 6 | const void *Decoder) { |
1787 | 6 | int Offset; |
1788 | 6 | switch (Inst.getOpcode()) { |
1789 | 6 | case Mips::LWM16_MMR6: |
1790 | 2 | case Mips::SWM16_MMR6: |
1791 | 2 | Offset = fieldFromInstruction(Insn, 4, 4); |
1792 | 2 | break; |
1793 | 4 | default: |
1794 | 4 | Offset = SignExtend32<4>(Insn & 0xf); |
1795 | 4 | break; |
1796 | 6 | } |
1797 | 6 | |
1798 | 6 | if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) |
1799 | 6 | == MCDisassembler::Fail) |
1800 | 0 | return MCDisassembler::Fail; |
1801 | 6 | |
1802 | 6 | Inst.addOperand(MCOperand::createReg(Mips::SP)); |
1803 | 6 | Inst.addOperand(MCOperand::createImm(Offset << 2)); |
1804 | 6 | |
1805 | 6 | return MCDisassembler::Success; |
1806 | 6 | } |
1807 | | |
1808 | | static DecodeStatus DecodeMemMMImm9(MCInst &Inst, |
1809 | | unsigned Insn, |
1810 | | uint64_t Address, |
1811 | 38 | const void *Decoder) { |
1812 | 38 | int Offset = SignExtend32<9>(Insn & 0x1ff); |
1813 | 38 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1814 | 38 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1815 | 38 | |
1816 | 38 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1817 | 38 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1818 | 38 | |
1819 | 38 | if (Inst.getOpcode() == Mips::SCE_MM) |
1820 | 3 | Inst.addOperand(MCOperand::createReg(Reg)); |
1821 | 38 | |
1822 | 38 | Inst.addOperand(MCOperand::createReg(Reg)); |
1823 | 38 | Inst.addOperand(MCOperand::createReg(Base)); |
1824 | 38 | Inst.addOperand(MCOperand::createImm(Offset)); |
1825 | 38 | |
1826 | 38 | return MCDisassembler::Success; |
1827 | 38 | } |
1828 | | |
1829 | | static DecodeStatus DecodeMemMMImm12(MCInst &Inst, |
1830 | | unsigned Insn, |
1831 | | uint64_t Address, |
1832 | 36 | const void *Decoder) { |
1833 | 36 | int Offset = SignExtend32<12>(Insn & 0x0fff); |
1834 | 36 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1835 | 36 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1836 | 36 | |
1837 | 36 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1838 | 36 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1839 | 36 | |
1840 | 36 | switch (Inst.getOpcode()) { |
1841 | 36 | case Mips::SWM32_MM: |
1842 | 10 | case Mips::LWM32_MM: |
1843 | 10 | if (DecodeRegListOperand(Inst, Insn, Address, Decoder) |
1844 | 10 | == MCDisassembler::Fail) |
1845 | 1 | return MCDisassembler::Fail; |
1846 | 9 | Inst.addOperand(MCOperand::createReg(Base)); |
1847 | 9 | Inst.addOperand(MCOperand::createImm(Offset)); |
1848 | 9 | break; |
1849 | 9 | case Mips::SC_MM: |
1850 | 5 | Inst.addOperand(MCOperand::createReg(Reg)); |
1851 | 5 | LLVM_FALLTHROUGH; |
1852 | 26 | default: |
1853 | 26 | Inst.addOperand(MCOperand::createReg(Reg)); |
1854 | 26 | if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM24 || |
1855 | 26 | Inst.getOpcode() == Mips::LWP_MMR622 || Inst.getOpcode() == Mips::SWP_MMR621 ) |
1856 | 6 | Inst.addOperand(MCOperand::createReg(Reg+1)); |
1857 | 26 | |
1858 | 26 | Inst.addOperand(MCOperand::createReg(Base)); |
1859 | 26 | Inst.addOperand(MCOperand::createImm(Offset)); |
1860 | 36 | } |
1861 | 36 | |
1862 | 36 | return MCDisassembler::Success35 ; |
1863 | 36 | } |
1864 | | |
1865 | | static DecodeStatus DecodeMemMMImm16(MCInst &Inst, |
1866 | | unsigned Insn, |
1867 | | uint64_t Address, |
1868 | 56 | const void *Decoder) { |
1869 | 56 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1870 | 56 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1871 | 56 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1872 | 56 | |
1873 | 56 | Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); |
1874 | 56 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1875 | 56 | |
1876 | 56 | Inst.addOperand(MCOperand::createReg(Reg)); |
1877 | 56 | Inst.addOperand(MCOperand::createReg(Base)); |
1878 | 56 | Inst.addOperand(MCOperand::createImm(Offset)); |
1879 | 56 | |
1880 | 56 | return MCDisassembler::Success; |
1881 | 56 | } |
1882 | | |
1883 | | static DecodeStatus DecodeFMem(MCInst &Inst, |
1884 | | unsigned Insn, |
1885 | | uint64_t Address, |
1886 | 188 | const void *Decoder) { |
1887 | 188 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1888 | 188 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1889 | 188 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1890 | 188 | |
1891 | 188 | Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); |
1892 | 188 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1893 | 188 | |
1894 | 188 | Inst.addOperand(MCOperand::createReg(Reg)); |
1895 | 188 | Inst.addOperand(MCOperand::createReg(Base)); |
1896 | 188 | Inst.addOperand(MCOperand::createImm(Offset)); |
1897 | 188 | |
1898 | 188 | return MCDisassembler::Success; |
1899 | 188 | } |
1900 | | |
1901 | | static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, |
1902 | 30 | uint64_t Address, const void *Decoder) { |
1903 | 30 | // This function is the same as DecodeFMem but with the Reg and Base fields |
1904 | 30 | // swapped according to microMIPS spec. |
1905 | 30 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1906 | 30 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1907 | 30 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1908 | 30 | |
1909 | 30 | Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); |
1910 | 30 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1911 | 30 | |
1912 | 30 | Inst.addOperand(MCOperand::createReg(Reg)); |
1913 | 30 | Inst.addOperand(MCOperand::createReg(Base)); |
1914 | 30 | Inst.addOperand(MCOperand::createImm(Offset)); |
1915 | 30 | |
1916 | 30 | return MCDisassembler::Success; |
1917 | 30 | } |
1918 | | |
1919 | | static DecodeStatus DecodeFMem2(MCInst &Inst, |
1920 | | unsigned Insn, |
1921 | | uint64_t Address, |
1922 | 121 | const void *Decoder) { |
1923 | 121 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1924 | 121 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1925 | 121 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1926 | 121 | |
1927 | 121 | Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); |
1928 | 121 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1929 | 121 | |
1930 | 121 | Inst.addOperand(MCOperand::createReg(Reg)); |
1931 | 121 | Inst.addOperand(MCOperand::createReg(Base)); |
1932 | 121 | Inst.addOperand(MCOperand::createImm(Offset)); |
1933 | 121 | |
1934 | 121 | return MCDisassembler::Success; |
1935 | 121 | } |
1936 | | |
1937 | | static DecodeStatus DecodeFMem3(MCInst &Inst, |
1938 | | unsigned Insn, |
1939 | | uint64_t Address, |
1940 | 14 | const void *Decoder) { |
1941 | 14 | int Offset = SignExtend32<16>(Insn & 0xffff); |
1942 | 14 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1943 | 14 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1944 | 14 | |
1945 | 14 | Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); |
1946 | 14 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1947 | 14 | |
1948 | 14 | Inst.addOperand(MCOperand::createReg(Reg)); |
1949 | 14 | Inst.addOperand(MCOperand::createReg(Base)); |
1950 | 14 | Inst.addOperand(MCOperand::createImm(Offset)); |
1951 | 14 | |
1952 | 14 | return MCDisassembler::Success; |
1953 | 14 | } |
1954 | | |
1955 | | static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, |
1956 | | unsigned Insn, |
1957 | | uint64_t Address, |
1958 | 16 | const void *Decoder) { |
1959 | 16 | int Offset = SignExtend32<11>(Insn & 0x07ff); |
1960 | 16 | unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
1961 | 16 | unsigned Base = fieldFromInstruction(Insn, 11, 5); |
1962 | 16 | |
1963 | 16 | Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); |
1964 | 16 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1965 | 16 | |
1966 | 16 | Inst.addOperand(MCOperand::createReg(Reg)); |
1967 | 16 | Inst.addOperand(MCOperand::createReg(Base)); |
1968 | 16 | Inst.addOperand(MCOperand::createImm(Offset)); |
1969 | 16 | |
1970 | 16 | return MCDisassembler::Success; |
1971 | 16 | } |
1972 | | |
1973 | | static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, |
1974 | 4 | uint64_t Address, const void *Decoder) { |
1975 | 4 | int Offset = SignExtend32<11>(Insn & 0x07ff); |
1976 | 4 | unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
1977 | 4 | unsigned Base = fieldFromInstruction(Insn, 16, 5); |
1978 | 4 | |
1979 | 4 | Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); |
1980 | 4 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1981 | 4 | |
1982 | 4 | Inst.addOperand(MCOperand::createReg(Reg)); |
1983 | 4 | Inst.addOperand(MCOperand::createReg(Base)); |
1984 | 4 | Inst.addOperand(MCOperand::createImm(Offset)); |
1985 | 4 | |
1986 | 4 | return MCDisassembler::Success; |
1987 | 4 | } |
1988 | | |
1989 | | static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, |
1990 | | unsigned Insn, |
1991 | | uint64_t Address, |
1992 | 12 | const void *Decoder) { |
1993 | 12 | int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); |
1994 | 12 | unsigned Rt = fieldFromInstruction(Insn, 16, 5); |
1995 | 12 | unsigned Base = fieldFromInstruction(Insn, 21, 5); |
1996 | 12 | |
1997 | 12 | Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); |
1998 | 12 | Base = getReg(Decoder, Mips::GPR32RegClassID, Base); |
1999 | 12 | |
2000 | 12 | if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R68 ){ |
2001 | 6 | Inst.addOperand(MCOperand::createReg(Rt)); |
2002 | 6 | } |
2003 | 12 | |
2004 | 12 | Inst.addOperand(MCOperand::createReg(Rt)); |
2005 | 12 | Inst.addOperand(MCOperand::createReg(Base)); |
2006 | 12 | Inst.addOperand(MCOperand::createImm(Offset)); |
2007 | 12 | |
2008 | 12 | return MCDisassembler::Success; |
2009 | 12 | } |
2010 | | |
2011 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, |
2012 | | unsigned RegNo, |
2013 | | uint64_t Address, |
2014 | 17 | const void *Decoder) { |
2015 | 17 | // Currently only hardware register 29 is supported. |
2016 | 17 | if (RegNo != 29) |
2017 | 0 | return MCDisassembler::Fail; |
2018 | 17 | Inst.addOperand(MCOperand::createReg(Mips::HWR29)); |
2019 | 17 | return MCDisassembler::Success; |
2020 | 17 | } |
2021 | | |
2022 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, |
2023 | | unsigned RegNo, |
2024 | | uint64_t Address, |
2025 | 1.26k | const void *Decoder) { |
2026 | 1.26k | if (RegNo > 30 || RegNo %21.25k ) |
2027 | 70 | return MCDisassembler::Fail; |
2028 | 1.19k | |
2029 | 1.19k | unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); |
2030 | 1.19k | Inst.addOperand(MCOperand::createReg(Reg)); |
2031 | 1.19k | return MCDisassembler::Success; |
2032 | 1.19k | } |
2033 | | |
2034 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, |
2035 | | unsigned RegNo, |
2036 | | uint64_t Address, |
2037 | 250 | const void *Decoder) { |
2038 | 250 | if (RegNo >= 4) |
2039 | 0 | return MCDisassembler::Fail; |
2040 | 250 | |
2041 | 250 | unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); |
2042 | 250 | Inst.addOperand(MCOperand::createReg(Reg)); |
2043 | 250 | return MCDisassembler::Success; |
2044 | 250 | } |
2045 | | |
2046 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, |
2047 | | unsigned RegNo, |
2048 | | uint64_t Address, |
2049 | 4 | const void *Decoder) { |
2050 | 4 | if (RegNo >= 4) |
2051 | 0 | return MCDisassembler::Fail; |
2052 | 4 | |
2053 | 4 | unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); |
2054 | 4 | Inst.addOperand(MCOperand::createReg(Reg)); |
2055 | 4 | return MCDisassembler::Success; |
2056 | 4 | } |
2057 | | |
2058 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, |
2059 | | unsigned RegNo, |
2060 | | uint64_t Address, |
2061 | 4 | const void *Decoder) { |
2062 | 4 | if (RegNo >= 4) |
2063 | 0 | return MCDisassembler::Fail; |
2064 | 4 | |
2065 | 4 | unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); |
2066 | 4 | Inst.addOperand(MCOperand::createReg(Reg)); |
2067 | 4 | return MCDisassembler::Success; |
2068 | 4 | } |
2069 | | |
2070 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, |
2071 | | unsigned RegNo, |
2072 | | uint64_t Address, |
2073 | 296 | const void *Decoder) { |
2074 | 296 | if (RegNo > 31) |
2075 | 0 | return MCDisassembler::Fail; |
2076 | 296 | |
2077 | 296 | unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); |
2078 | 296 | Inst.addOperand(MCOperand::createReg(Reg)); |
2079 | 296 | return MCDisassembler::Success; |
2080 | 296 | } |
2081 | | |
2082 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, |
2083 | | unsigned RegNo, |
2084 | | uint64_t Address, |
2085 | 295 | const void *Decoder) { |
2086 | 295 | if (RegNo > 31) |
2087 | 0 | return MCDisassembler::Fail; |
2088 | 295 | |
2089 | 295 | unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); |
2090 | 295 | Inst.addOperand(MCOperand::createReg(Reg)); |
2091 | 295 | return MCDisassembler::Success; |
2092 | 295 | } |
2093 | | |
2094 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, |
2095 | | unsigned RegNo, |
2096 | | uint64_t Address, |
2097 | 427 | const void *Decoder) { |
2098 | 427 | if (RegNo > 31) |
2099 | 0 | return MCDisassembler::Fail; |
2100 | 427 | |
2101 | 427 | unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); |
2102 | 427 | Inst.addOperand(MCOperand::createReg(Reg)); |
2103 | 427 | return MCDisassembler::Success; |
2104 | 427 | } |
2105 | | |
2106 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, |
2107 | | unsigned RegNo, |
2108 | | uint64_t Address, |
2109 | 377 | const void *Decoder) { |
2110 | 377 | if (RegNo > 31) |
2111 | 0 | return MCDisassembler::Fail; |
2112 | 377 | |
2113 | 377 | unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); |
2114 | 377 | Inst.addOperand(MCOperand::createReg(Reg)); |
2115 | 377 | return MCDisassembler::Success; |
2116 | 377 | } |
2117 | | |
2118 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, |
2119 | | unsigned RegNo, |
2120 | | uint64_t Address, |
2121 | 32 | const void *Decoder) { |
2122 | 32 | if (RegNo > 7) |
2123 | 0 | return MCDisassembler::Fail; |
2124 | 32 | |
2125 | 32 | unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); |
2126 | 32 | Inst.addOperand(MCOperand::createReg(Reg)); |
2127 | 32 | return MCDisassembler::Success; |
2128 | 32 | } |
2129 | | |
2130 | | static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, |
2131 | | unsigned RegNo, |
2132 | | uint64_t Address, |
2133 | 113 | const void *Decoder) { |
2134 | 113 | if (RegNo > 31) |
2135 | 0 | return MCDisassembler::Fail; |
2136 | 113 | |
2137 | 113 | unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); |
2138 | 113 | Inst.addOperand(MCOperand::createReg(Reg)); |
2139 | 113 | return MCDisassembler::Success; |
2140 | 113 | } |
2141 | | |
2142 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, |
2143 | | unsigned RegNo, |
2144 | | uint64_t Address, |
2145 | 60 | const void *Decoder) { |
2146 | 60 | if (RegNo > 31) |
2147 | 0 | return MCDisassembler::Fail; |
2148 | 60 | |
2149 | 60 | unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); |
2150 | 60 | Inst.addOperand(MCOperand::createReg(Reg)); |
2151 | 60 | return MCDisassembler::Success; |
2152 | 60 | } |
2153 | | |
2154 | | static DecodeStatus DecodeBranchTarget(MCInst &Inst, |
2155 | | unsigned Offset, |
2156 | | uint64_t Address, |
2157 | 824 | const void *Decoder) { |
2158 | 824 | int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; |
2159 | 824 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2160 | 824 | return MCDisassembler::Success; |
2161 | 824 | } |
2162 | | |
2163 | | static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, |
2164 | | unsigned Offset, |
2165 | | uint64_t Address, |
2166 | 1 | const void *Decoder) { |
2167 | 1 | int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); |
2168 | 1 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2169 | 1 | return MCDisassembler::Success; |
2170 | 1 | } |
2171 | | |
2172 | | static DecodeStatus DecodeJumpTarget(MCInst &Inst, |
2173 | | unsigned Insn, |
2174 | | uint64_t Address, |
2175 | 231 | const void *Decoder) { |
2176 | 231 | unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; |
2177 | 231 | Inst.addOperand(MCOperand::createImm(JumpOffset)); |
2178 | 231 | return MCDisassembler::Success; |
2179 | 231 | } |
2180 | | |
2181 | | static DecodeStatus DecodeBranchTarget21(MCInst &Inst, |
2182 | | unsigned Offset, |
2183 | | uint64_t Address, |
2184 | 28 | const void *Decoder) { |
2185 | 28 | int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; |
2186 | 28 | |
2187 | 28 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2188 | 28 | return MCDisassembler::Success; |
2189 | 28 | } |
2190 | | |
2191 | | static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, |
2192 | | unsigned Offset, |
2193 | | uint64_t Address, |
2194 | 2 | const void *Decoder) { |
2195 | 2 | int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; |
2196 | 2 | |
2197 | 2 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2198 | 2 | return MCDisassembler::Success; |
2199 | 2 | } |
2200 | | |
2201 | | static DecodeStatus DecodeBranchTarget26(MCInst &Inst, |
2202 | | unsigned Offset, |
2203 | | uint64_t Address, |
2204 | 17 | const void *Decoder) { |
2205 | 17 | int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; |
2206 | 17 | |
2207 | 17 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2208 | 17 | return MCDisassembler::Success; |
2209 | 17 | } |
2210 | | |
2211 | | static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, |
2212 | | unsigned Offset, |
2213 | | uint64_t Address, |
2214 | 9 | const void *Decoder) { |
2215 | 9 | int32_t BranchOffset = SignExtend32<8>(Offset << 1); |
2216 | 9 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2217 | 9 | return MCDisassembler::Success; |
2218 | 9 | } |
2219 | | |
2220 | | static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, |
2221 | | unsigned Offset, |
2222 | | uint64_t Address, |
2223 | 6 | const void *Decoder) { |
2224 | 6 | int32_t BranchOffset = SignExtend32<11>(Offset << 1); |
2225 | 6 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2226 | 6 | return MCDisassembler::Success; |
2227 | 6 | } |
2228 | | |
2229 | | static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, |
2230 | | unsigned Offset, |
2231 | | uint64_t Address, |
2232 | 40 | const void *Decoder) { |
2233 | 40 | int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; |
2234 | 40 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2235 | 40 | return MCDisassembler::Success; |
2236 | 40 | } |
2237 | | |
2238 | | static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, |
2239 | | unsigned Offset, |
2240 | | uint64_t Address, |
2241 | 3 | const void *Decoder) { |
2242 | 3 | int32_t BranchOffset = SignExtend32<27>(Offset << 1); |
2243 | 3 | |
2244 | 3 | Inst.addOperand(MCOperand::createImm(BranchOffset)); |
2245 | 3 | return MCDisassembler::Success; |
2246 | 3 | } |
2247 | | |
2248 | | static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, |
2249 | | unsigned Insn, |
2250 | | uint64_t Address, |
2251 | 17 | const void *Decoder) { |
2252 | 17 | unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; |
2253 | 17 | Inst.addOperand(MCOperand::createImm(JumpOffset)); |
2254 | 17 | return MCDisassembler::Success; |
2255 | 17 | } |
2256 | | |
2257 | | static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, |
2258 | | unsigned Value, |
2259 | | uint64_t Address, |
2260 | 6 | const void *Decoder) { |
2261 | 6 | if (Value == 0) |
2262 | 0 | Inst.addOperand(MCOperand::createImm(1)); |
2263 | 6 | else if (Value == 0x7) |
2264 | 3 | Inst.addOperand(MCOperand::createImm(-1)); |
2265 | 3 | else |
2266 | 3 | Inst.addOperand(MCOperand::createImm(Value << 2)); |
2267 | 6 | return MCDisassembler::Success; |
2268 | 6 | } |
2269 | | |
2270 | | static DecodeStatus DecodeLi16Imm(MCInst &Inst, |
2271 | | unsigned Value, |
2272 | | uint64_t Address, |
2273 | 31 | const void *Decoder) { |
2274 | 31 | if (Value == 0x7F) |
2275 | 3 | Inst.addOperand(MCOperand::createImm(-1)); |
2276 | 28 | else |
2277 | 28 | Inst.addOperand(MCOperand::createImm(Value)); |
2278 | 31 | return MCDisassembler::Success; |
2279 | 31 | } |
2280 | | |
2281 | | static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, |
2282 | | unsigned Value, |
2283 | | uint64_t Address, |
2284 | 13 | const void *Decoder) { |
2285 | 13 | Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 84 : Value9 )); |
2286 | 13 | return MCDisassembler::Success; |
2287 | 13 | } |
2288 | | |
2289 | | template <unsigned Bits, int Offset, int Scale> |
2290 | | static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, |
2291 | | uint64_t Address, |
2292 | 34 | const void *Decoder) { |
2293 | 34 | Value &= ((1 << Bits) - 1); |
2294 | 34 | Value *= Scale; |
2295 | 34 | Inst.addOperand(MCOperand::createImm(Value + Offset)); |
2296 | 34 | return MCDisassembler::Success; |
2297 | 34 | } MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffsetAndScale<5u, 0, 4>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2292 | 3 | const void *Decoder) { | 2293 | 3 | Value &= ((1 << Bits) - 1); | 2294 | 3 | Value *= Scale; | 2295 | 3 | Inst.addOperand(MCOperand::createImm(Value + Offset)); | 2296 | 3 | return MCDisassembler::Success; | 2297 | 3 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffsetAndScale<6u, 0, 4>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2292 | 3 | const void *Decoder) { | 2293 | 3 | Value &= ((1 << Bits) - 1); | 2294 | 3 | Value *= Scale; | 2295 | 3 | Inst.addOperand(MCOperand::createImm(Value + Offset)); | 2296 | 3 | return MCDisassembler::Success; | 2297 | 3 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffsetAndScale<5u, 1, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2292 | 13 | const void *Decoder) { | 2293 | 13 | Value &= ((1 << Bits) - 1); | 2294 | 13 | Value *= Scale; | 2295 | 13 | Inst.addOperand(MCOperand::createImm(Value + Offset)); | 2296 | 13 | return MCDisassembler::Success; | 2297 | 13 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeUImmWithOffsetAndScale<2u, 1, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2292 | 15 | const void *Decoder) { | 2293 | 15 | Value &= ((1 << Bits) - 1); | 2294 | 15 | Value *= Scale; | 2295 | 15 | Inst.addOperand(MCOperand::createImm(Value + Offset)); | 2296 | 15 | return MCDisassembler::Success; | 2297 | 15 | } |
|
2298 | | |
2299 | | template <unsigned Bits, int Offset, int ScaleBy> |
2300 | | static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, |
2301 | | uint64_t Address, |
2302 | 920 | const void *Decoder) { |
2303 | 920 | int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; |
2304 | 920 | Inst.addOperand(MCOperand::createImm(Imm + Offset)); |
2305 | 920 | return MCDisassembler::Success; |
2306 | 920 | } MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeSImmWithOffsetAndScale<10u, 0, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2302 | 3 | const void *Decoder) { | 2303 | 3 | int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; | 2304 | 3 | Inst.addOperand(MCOperand::createImm(Imm + Offset)); | 2305 | 3 | return MCDisassembler::Success; | 2306 | 3 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeSImmWithOffsetAndScale<4u, 0, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2302 | 3 | const void *Decoder) { | 2303 | 3 | int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; | 2304 | 3 | Inst.addOperand(MCOperand::createImm(Imm + Offset)); | 2305 | 3 | return MCDisassembler::Success; | 2306 | 3 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeSImmWithOffsetAndScale<6u, 0, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2302 | 5 | const void *Decoder) { | 2303 | 5 | int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; | 2304 | 5 | Inst.addOperand(MCOperand::createImm(Imm + Offset)); | 2305 | 5 | return MCDisassembler::Success; | 2306 | 5 | } |
MipsDisassembler.cpp:llvm::MCDisassembler::DecodeStatus DecodeSImmWithOffsetAndScale<16u, 0, 1>(llvm::MCInst&, unsigned int, unsigned long long, void const*) Line | Count | Source | 2302 | 909 | const void *Decoder) { | 2303 | 909 | int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; | 2304 | 909 | Inst.addOperand(MCOperand::createImm(Imm + Offset)); | 2305 | 909 | return MCDisassembler::Success; | 2306 | 909 | } |
|
2307 | | |
2308 | | static DecodeStatus DecodeInsSize(MCInst &Inst, |
2309 | | unsigned Insn, |
2310 | | uint64_t Address, |
2311 | 25 | const void *Decoder) { |
2312 | 25 | // First we need to grab the pos(lsb) from MCInst. |
2313 | 25 | // This function only handles the 32 bit variants of ins, as dins |
2314 | 25 | // variants are handled differently. |
2315 | 25 | int Pos = Inst.getOperand(2).getImm(); |
2316 | 25 | int Size = (int) Insn - Pos + 1; |
2317 | 25 | Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); |
2318 | 25 | return MCDisassembler::Success; |
2319 | 25 | } |
2320 | | |
2321 | | static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, |
2322 | 25 | uint64_t Address, const void *Decoder) { |
2323 | 25 | Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); |
2324 | 25 | return MCDisassembler::Success; |
2325 | 25 | } |
2326 | | |
2327 | | static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, |
2328 | 4 | uint64_t Address, const void *Decoder) { |
2329 | 4 | Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); |
2330 | 4 | return MCDisassembler::Success; |
2331 | 4 | } |
2332 | | |
2333 | | static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, |
2334 | 15 | uint64_t Address, const void *Decoder) { |
2335 | 15 | int32_t DecodedValue; |
2336 | 15 | switch (Insn) { |
2337 | 15 | case 0: DecodedValue = 256; break3 ; |
2338 | 15 | case 1: DecodedValue = 257; break3 ; |
2339 | 15 | case 510: DecodedValue = -258; break3 ; |
2340 | 15 | case 511: DecodedValue = -257; break3 ; |
2341 | 15 | default: DecodedValue = SignExtend32<9>(Insn); break3 ; |
2342 | 15 | } |
2343 | 15 | Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); |
2344 | 15 | return MCDisassembler::Success; |
2345 | 15 | } |
2346 | | |
2347 | | static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, |
2348 | 3 | uint64_t Address, const void *Decoder) { |
2349 | 3 | // Insn must be >= 0, since it is unsigned that condition is always true. |
2350 | 3 | assert(Insn < 16); |
2351 | 3 | int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, |
2352 | 3 | 255, 32768, 65535}; |
2353 | 3 | Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); |
2354 | 3 | return MCDisassembler::Success; |
2355 | 3 | } |
2356 | | |
2357 | | static DecodeStatus DecodeRegListOperand(MCInst &Inst, |
2358 | | unsigned Insn, |
2359 | | uint64_t Address, |
2360 | 10 | const void *Decoder) { |
2361 | 10 | unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, |
2362 | 10 | Mips::S6, Mips::S7, Mips::FP}; |
2363 | 10 | unsigned RegNum; |
2364 | 10 | |
2365 | 10 | unsigned RegLst = fieldFromInstruction(Insn, 21, 5); |
2366 | 10 | |
2367 | 10 | // Empty register lists are not allowed. |
2368 | 10 | if (RegLst == 0) |
2369 | 0 | return MCDisassembler::Fail; |
2370 | 10 | |
2371 | 10 | RegNum = RegLst & 0xf; |
2372 | 10 | |
2373 | 10 | // RegLst values 10-15, and 26-31 are reserved. |
2374 | 10 | if (RegNum > 9) |
2375 | 1 | return MCDisassembler::Fail; |
2376 | 9 | |
2377 | 48 | for (unsigned i = 0; 9 i < RegNum; i++39 ) |
2378 | 39 | Inst.addOperand(MCOperand::createReg(Regs[i])); |
2379 | 9 | |
2380 | 9 | if (RegLst & 0x10) |
2381 | 0 | Inst.addOperand(MCOperand::createReg(Mips::RA)); |
2382 | 9 | |
2383 | 9 | return MCDisassembler::Success; |
2384 | 9 | } |
2385 | | |
2386 | | static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, |
2387 | | uint64_t Address, |
2388 | 6 | const void *Decoder) { |
2389 | 6 | unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; |
2390 | 6 | unsigned RegLst; |
2391 | 6 | switch(Inst.getOpcode()) { |
2392 | 6 | default: |
2393 | 4 | RegLst = fieldFromInstruction(Insn, 4, 2); |
2394 | 4 | break; |
2395 | 6 | case Mips::LWM16_MMR6: |
2396 | 2 | case Mips::SWM16_MMR6: |
2397 | 2 | RegLst = fieldFromInstruction(Insn, 8, 2); |
2398 | 2 | break; |
2399 | 6 | } |
2400 | 6 | unsigned RegNum = RegLst & 0x3; |
2401 | 6 | |
2402 | 18 | for (unsigned i = 0; i <= RegNum; i++12 ) |
2403 | 12 | Inst.addOperand(MCOperand::createReg(Regs[i])); |
2404 | 6 | |
2405 | 6 | Inst.addOperand(MCOperand::createReg(Mips::RA)); |
2406 | 6 | |
2407 | 6 | return MCDisassembler::Success; |
2408 | 6 | } |
2409 | | |
2410 | | static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, |
2411 | 6 | uint64_t Address, const void *Decoder) { |
2412 | 6 | switch (RegPair) { |
2413 | 6 | default: |
2414 | 0 | return MCDisassembler::Fail; |
2415 | 6 | case 0: |
2416 | 3 | Inst.addOperand(MCOperand::createReg(Mips::A1)); |
2417 | 3 | Inst.addOperand(MCOperand::createReg(Mips::A2)); |
2418 | 3 | break; |
2419 | 6 | case 1: |
2420 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A1)); |
2421 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A3)); |
2422 | 0 | break; |
2423 | 6 | case 2: |
2424 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A2)); |
2425 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A3)); |
2426 | 0 | break; |
2427 | 6 | case 3: |
2428 | 3 | Inst.addOperand(MCOperand::createReg(Mips::A0)); |
2429 | 3 | Inst.addOperand(MCOperand::createReg(Mips::S5)); |
2430 | 3 | break; |
2431 | 6 | case 4: |
2432 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A0)); |
2433 | 0 | Inst.addOperand(MCOperand::createReg(Mips::S6)); |
2434 | 0 | break; |
2435 | 6 | case 5: |
2436 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A0)); |
2437 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A1)); |
2438 | 0 | break; |
2439 | 6 | case 6: |
2440 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A0)); |
2441 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A2)); |
2442 | 0 | break; |
2443 | 6 | case 7: |
2444 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A0)); |
2445 | 0 | Inst.addOperand(MCOperand::createReg(Mips::A3)); |
2446 | 0 | break; |
2447 | 6 | } |
2448 | 6 | |
2449 | 6 | return MCDisassembler::Success; |
2450 | 6 | } |
2451 | | |
2452 | | static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, |
2453 | 12 | uint64_t Address, const void *Decoder) { |
2454 | 12 | Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); |
2455 | 12 | return MCDisassembler::Success; |
2456 | 12 | } |
2457 | | |
2458 | | template <typename InsnType> |
2459 | | static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, |
2460 | | uint64_t Address, |
2461 | 3 | const void *Decoder) { |
2462 | 3 | // We have: |
2463 | 3 | // 0b000111 ttttt sssss iiiiiiiiiiiiiiii |
2464 | 3 | // Invalid if rt == 0 |
2465 | 3 | // BGTZALC_MMR6 if rs == 0 && rt != 0 |
2466 | 3 | // BLTZALC_MMR6 if rs != 0 && rs == rt |
2467 | 3 | // BLTUC_MMR6 if rs != 0 && rs != rt |
2468 | 3 | |
2469 | 3 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
2470 | 3 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
2471 | 3 | InsnType Imm = 0; |
2472 | 3 | bool HasRs = false; |
2473 | 3 | bool HasRt = false; |
2474 | 3 | |
2475 | 3 | if (Rt == 0) |
2476 | 0 | return MCDisassembler::Fail; |
2477 | 3 | else if (Rs == 0) { |
2478 | 1 | MI.setOpcode(Mips::BGTZALC_MMR6); |
2479 | 1 | HasRt = true; |
2480 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
2481 | 1 | } |
2482 | 2 | else if (Rs == Rt) { |
2483 | 1 | MI.setOpcode(Mips::BLTZALC_MMR6); |
2484 | 1 | HasRs = true; |
2485 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
2486 | 1 | } |
2487 | 1 | else { |
2488 | 1 | MI.setOpcode(Mips::BLTUC_MMR6); |
2489 | 1 | HasRs = true; |
2490 | 1 | HasRt = true; |
2491 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
2492 | 1 | } |
2493 | 3 | |
2494 | 3 | if (HasRs) |
2495 | 2 | MI.addOperand( |
2496 | 2 | MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); |
2497 | 3 | |
2498 | 3 | if (HasRt) |
2499 | 2 | MI.addOperand( |
2500 | 2 | MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); |
2501 | 3 | |
2502 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
2503 | 3 | |
2504 | 3 | return MCDisassembler::Success; |
2505 | 3 | } |
2506 | | |
2507 | | template <typename InsnType> |
2508 | | static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, |
2509 | | uint64_t Address, |
2510 | 3 | const void *Decoder) { |
2511 | 3 | // We have: |
2512 | 3 | // 0b000110 ttttt sssss iiiiiiiiiiiiiiii |
2513 | 3 | // Invalid if rt == 0 |
2514 | 3 | // BLEZALC_MMR6 if rs == 0 && rt != 0 |
2515 | 3 | // BGEZALC_MMR6 if rs == rt && rt != 0 |
2516 | 3 | // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 |
2517 | 3 | |
2518 | 3 | InsnType Rt = fieldFromInstruction(insn, 21, 5); |
2519 | 3 | InsnType Rs = fieldFromInstruction(insn, 16, 5); |
2520 | 3 | InsnType Imm = 0; |
2521 | 3 | bool HasRs = false; |
2522 | 3 | |
2523 | 3 | if (Rt == 0) |
2524 | 0 | return MCDisassembler::Fail; |
2525 | 3 | else if (Rs == 0) { |
2526 | 1 | MI.setOpcode(Mips::BLEZALC_MMR6); |
2527 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
2528 | 1 | } |
2529 | 2 | else if (Rs == Rt) { |
2530 | 1 | MI.setOpcode(Mips::BGEZALC_MMR6); |
2531 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; |
2532 | 1 | } |
2533 | 1 | else { |
2534 | 1 | HasRs = true; |
2535 | 1 | MI.setOpcode(Mips::BGEUC_MMR6); |
2536 | 1 | Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; |
2537 | 1 | } |
2538 | 3 | |
2539 | 3 | if (HasRs) |
2540 | 1 | MI.addOperand( |
2541 | 1 | MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); |
2542 | 3 | MI.addOperand( |
2543 | 3 | MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); |
2544 | 3 | |
2545 | 3 | MI.addOperand(MCOperand::createImm(Imm)); |
2546 | 3 | |
2547 | 3 | return MCDisassembler::Success; |
2548 | 3 | } |