Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#include "NVPTX.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace NVPTXISD {
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enum NodeType : unsigned {
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  // Start the numbering from where ISD NodeType finishes.
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  FIRST_NUMBER = ISD::BUILTIN_OP_END,
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  Wrapper,
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  CALL,
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  RET_FLAG,
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  LOAD_PARAM,
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  DeclareParam,
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  DeclareScalarParam,
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  DeclareRetParam,
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  DeclareRet,
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  DeclareScalarRet,
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  PrintCall,
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  PrintConvergentCall,
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  PrintCallUni,
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  PrintConvergentCallUni,
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  CallArgBegin,
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  CallArg,
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  LastCallArg,
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  CallArgEnd,
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  CallVoid,
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  CallVal,
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  CallSymbol,
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  Prototype,
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  MoveParam,
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  PseudoUseParam,
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  RETURN,
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  CallSeqBegin,
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  CallSeqEnd,
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  CallPrototype,
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  ProxyReg,
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  FUN_SHFL_CLAMP,
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  FUN_SHFR_CLAMP,
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  MUL_WIDE_SIGNED,
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  MUL_WIDE_UNSIGNED,
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  IMAD,
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  SETP_F16X2,
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  Dummy,
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  LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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  LoadV4,
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  LDGV2, // LDG.v2
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  LDGV4, // LDG.v4
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  LDUV2, // LDU.v2
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  LDUV4, // LDU.v4
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  StoreV2,
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  StoreV4,
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  LoadParam,
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  LoadParamV2,
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  LoadParamV4,
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  StoreParam,
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  StoreParamV2,
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  StoreParamV4,
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  StoreParamS32, // to sext and store a <32bit value, not used currently
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  StoreParamU32, // to zext and store a <32bit value, not used currently
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  StoreRetval,
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  StoreRetvalV2,
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  StoreRetvalV4,
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  // Texture intrinsics
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  Tex1DFloatS32,
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  Tex1DFloatFloat,
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  Tex1DFloatFloatLevel,
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  Tex1DFloatFloatGrad,
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  Tex1DS32S32,
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  Tex1DS32Float,
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  Tex1DS32FloatLevel,
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  Tex1DS32FloatGrad,
91
  Tex1DU32S32,
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  Tex1DU32Float,
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  Tex1DU32FloatLevel,
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  Tex1DU32FloatGrad,
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  Tex1DArrayFloatS32,
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  Tex1DArrayFloatFloat,
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  Tex1DArrayFloatFloatLevel,
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  Tex1DArrayFloatFloatGrad,
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  Tex1DArrayS32S32,
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  Tex1DArrayS32Float,
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  Tex1DArrayS32FloatLevel,
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  Tex1DArrayS32FloatGrad,
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  Tex1DArrayU32S32,
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  Tex1DArrayU32Float,
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  Tex1DArrayU32FloatLevel,
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  Tex1DArrayU32FloatGrad,
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  Tex2DFloatS32,
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  Tex2DFloatFloat,
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  Tex2DFloatFloatLevel,
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  Tex2DFloatFloatGrad,
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  Tex2DS32S32,
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  Tex2DS32Float,
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  Tex2DS32FloatLevel,
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  Tex2DS32FloatGrad,
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  Tex2DU32S32,
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  Tex2DU32Float,
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  Tex2DU32FloatLevel,
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  Tex2DU32FloatGrad,
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  Tex2DArrayFloatS32,
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  Tex2DArrayFloatFloat,
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  Tex2DArrayFloatFloatLevel,
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  Tex2DArrayFloatFloatGrad,
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  Tex2DArrayS32S32,
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  Tex2DArrayS32Float,
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  Tex2DArrayS32FloatLevel,
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  Tex2DArrayS32FloatGrad,
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  Tex2DArrayU32S32,
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  Tex2DArrayU32Float,
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  Tex2DArrayU32FloatLevel,
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  Tex2DArrayU32FloatGrad,
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  Tex3DFloatS32,
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  Tex3DFloatFloat,
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  Tex3DFloatFloatLevel,
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  Tex3DFloatFloatGrad,
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  Tex3DS32S32,
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  Tex3DS32Float,
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  Tex3DS32FloatLevel,
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  Tex3DS32FloatGrad,
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  Tex3DU32S32,
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  Tex3DU32Float,
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  Tex3DU32FloatLevel,
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  Tex3DU32FloatGrad,
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  TexCubeFloatFloat,
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  TexCubeFloatFloatLevel,
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  TexCubeS32Float,
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  TexCubeS32FloatLevel,
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  TexCubeU32Float,
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  TexCubeU32FloatLevel,
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  TexCubeArrayFloatFloat,
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  TexCubeArrayFloatFloatLevel,
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  TexCubeArrayS32Float,
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  TexCubeArrayS32FloatLevel,
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  TexCubeArrayU32Float,
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  TexCubeArrayU32FloatLevel,
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  Tld4R2DFloatFloat,
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  Tld4G2DFloatFloat,
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  Tld4B2DFloatFloat,
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  Tld4A2DFloatFloat,
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  Tld4R2DS64Float,
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  Tld4G2DS64Float,
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  Tld4B2DS64Float,
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  Tld4A2DS64Float,
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  Tld4R2DU64Float,
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  Tld4G2DU64Float,
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  Tld4B2DU64Float,
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  Tld4A2DU64Float,
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  TexUnified1DFloatS32,
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  TexUnified1DFloatFloat,
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  TexUnified1DFloatFloatLevel,
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  TexUnified1DFloatFloatGrad,
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  TexUnified1DS32S32,
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  TexUnified1DS32Float,
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  TexUnified1DS32FloatLevel,
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  TexUnified1DS32FloatGrad,
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  TexUnified1DU32S32,
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  TexUnified1DU32Float,
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  TexUnified1DU32FloatLevel,
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  TexUnified1DU32FloatGrad,
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  TexUnified1DArrayFloatS32,
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  TexUnified1DArrayFloatFloat,
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  TexUnified1DArrayFloatFloatLevel,
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  TexUnified1DArrayFloatFloatGrad,
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  TexUnified1DArrayS32S32,
184
  TexUnified1DArrayS32Float,
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  TexUnified1DArrayS32FloatLevel,
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  TexUnified1DArrayS32FloatGrad,
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  TexUnified1DArrayU32S32,
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  TexUnified1DArrayU32Float,
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  TexUnified1DArrayU32FloatLevel,
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  TexUnified1DArrayU32FloatGrad,
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  TexUnified2DFloatS32,
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  TexUnified2DFloatFloat,
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  TexUnified2DFloatFloatLevel,
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  TexUnified2DFloatFloatGrad,
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  TexUnified2DS32S32,
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  TexUnified2DS32Float,
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  TexUnified2DS32FloatLevel,
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  TexUnified2DS32FloatGrad,
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  TexUnified2DU32S32,
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  TexUnified2DU32Float,
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  TexUnified2DU32FloatLevel,
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  TexUnified2DU32FloatGrad,
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  TexUnified2DArrayFloatS32,
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  TexUnified2DArrayFloatFloat,
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  TexUnified2DArrayFloatFloatLevel,
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  TexUnified2DArrayFloatFloatGrad,
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  TexUnified2DArrayS32S32,
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  TexUnified2DArrayS32Float,
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  TexUnified2DArrayS32FloatLevel,
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  TexUnified2DArrayS32FloatGrad,
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  TexUnified2DArrayU32S32,
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  TexUnified2DArrayU32Float,
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  TexUnified2DArrayU32FloatLevel,
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  TexUnified2DArrayU32FloatGrad,
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  TexUnified3DFloatS32,
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  TexUnified3DFloatFloat,
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  TexUnified3DFloatFloatLevel,
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  TexUnified3DFloatFloatGrad,
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  TexUnified3DS32S32,
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  TexUnified3DS32Float,
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  TexUnified3DS32FloatLevel,
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  TexUnified3DS32FloatGrad,
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  TexUnified3DU32S32,
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  TexUnified3DU32Float,
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  TexUnified3DU32FloatLevel,
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  TexUnified3DU32FloatGrad,
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  TexUnifiedCubeFloatFloat,
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  TexUnifiedCubeFloatFloatLevel,
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  TexUnifiedCubeS32Float,
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  TexUnifiedCubeS32FloatLevel,
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  TexUnifiedCubeU32Float,
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  TexUnifiedCubeU32FloatLevel,
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  TexUnifiedCubeArrayFloatFloat,
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  TexUnifiedCubeArrayFloatFloatLevel,
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  TexUnifiedCubeArrayS32Float,
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  TexUnifiedCubeArrayS32FloatLevel,
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  TexUnifiedCubeArrayU32Float,
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  TexUnifiedCubeArrayU32FloatLevel,
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  Tld4UnifiedR2DFloatFloat,
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  Tld4UnifiedG2DFloatFloat,
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  Tld4UnifiedB2DFloatFloat,
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  Tld4UnifiedA2DFloatFloat,
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  Tld4UnifiedR2DS64Float,
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  Tld4UnifiedG2DS64Float,
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  Tld4UnifiedB2DS64Float,
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  Tld4UnifiedA2DS64Float,
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  Tld4UnifiedR2DU64Float,
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  Tld4UnifiedG2DU64Float,
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  Tld4UnifiedB2DU64Float,
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  Tld4UnifiedA2DU64Float,
251
252
  // Surface intrinsics
253
  Suld1DI8Clamp,
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  Suld1DI16Clamp,
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  Suld1DI32Clamp,
256
  Suld1DI64Clamp,
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  Suld1DV2I8Clamp,
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  Suld1DV2I16Clamp,
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  Suld1DV2I32Clamp,
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  Suld1DV2I64Clamp,
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  Suld1DV4I8Clamp,
262
  Suld1DV4I16Clamp,
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  Suld1DV4I32Clamp,
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  Suld1DArrayI8Clamp,
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  Suld1DArrayI16Clamp,
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  Suld1DArrayI32Clamp,
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  Suld1DArrayI64Clamp,
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  Suld1DArrayV2I8Clamp,
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  Suld1DArrayV2I16Clamp,
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  Suld1DArrayV2I32Clamp,
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  Suld1DArrayV2I64Clamp,
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  Suld1DArrayV4I8Clamp,
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  Suld1DArrayV4I16Clamp,
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  Suld1DArrayV4I32Clamp,
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277
  Suld2DI8Clamp,
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  Suld2DI16Clamp,
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  Suld2DI32Clamp,
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  Suld2DI64Clamp,
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  Suld2DV2I8Clamp,
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  Suld2DV2I16Clamp,
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  Suld2DV2I32Clamp,
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  Suld2DV2I64Clamp,
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  Suld2DV4I8Clamp,
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  Suld2DV4I16Clamp,
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  Suld2DV4I32Clamp,
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  Suld2DArrayI8Clamp,
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  Suld2DArrayI16Clamp,
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  Suld2DArrayI32Clamp,
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  Suld2DArrayI64Clamp,
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  Suld2DArrayV2I8Clamp,
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  Suld2DArrayV2I16Clamp,
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  Suld2DArrayV2I32Clamp,
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  Suld2DArrayV2I64Clamp,
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  Suld2DArrayV4I8Clamp,
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  Suld2DArrayV4I16Clamp,
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  Suld2DArrayV4I32Clamp,
300
301
  Suld3DI8Clamp,
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  Suld3DI16Clamp,
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  Suld3DI32Clamp,
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  Suld3DI64Clamp,
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  Suld3DV2I8Clamp,
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  Suld3DV2I16Clamp,
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  Suld3DV2I32Clamp,
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  Suld3DV2I64Clamp,
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  Suld3DV4I8Clamp,
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  Suld3DV4I16Clamp,
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  Suld3DV4I32Clamp,
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313
  Suld1DI8Trap,
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  Suld1DI16Trap,
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  Suld1DI32Trap,
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  Suld1DI64Trap,
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  Suld1DV2I8Trap,
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  Suld1DV2I16Trap,
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  Suld1DV2I32Trap,
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  Suld1DV2I64Trap,
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  Suld1DV4I8Trap,
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  Suld1DV4I16Trap,
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  Suld1DV4I32Trap,
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325
  Suld1DArrayI8Trap,
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  Suld1DArrayI16Trap,
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  Suld1DArrayI32Trap,
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  Suld1DArrayI64Trap,
329
  Suld1DArrayV2I8Trap,
330
  Suld1DArrayV2I16Trap,
331
  Suld1DArrayV2I32Trap,
332
  Suld1DArrayV2I64Trap,
333
  Suld1DArrayV4I8Trap,
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  Suld1DArrayV4I16Trap,
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  Suld1DArrayV4I32Trap,
336
337
  Suld2DI8Trap,
338
  Suld2DI16Trap,
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  Suld2DI32Trap,
340
  Suld2DI64Trap,
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  Suld2DV2I8Trap,
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  Suld2DV2I16Trap,
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  Suld2DV2I32Trap,
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  Suld2DV2I64Trap,
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  Suld2DV4I8Trap,
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  Suld2DV4I16Trap,
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  Suld2DV4I32Trap,
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349
  Suld2DArrayI8Trap,
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  Suld2DArrayI16Trap,
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  Suld2DArrayI32Trap,
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  Suld2DArrayI64Trap,
353
  Suld2DArrayV2I8Trap,
354
  Suld2DArrayV2I16Trap,
355
  Suld2DArrayV2I32Trap,
356
  Suld2DArrayV2I64Trap,
357
  Suld2DArrayV4I8Trap,
358
  Suld2DArrayV4I16Trap,
359
  Suld2DArrayV4I32Trap,
360
361
  Suld3DI8Trap,
362
  Suld3DI16Trap,
363
  Suld3DI32Trap,
364
  Suld3DI64Trap,
365
  Suld3DV2I8Trap,
366
  Suld3DV2I16Trap,
367
  Suld3DV2I32Trap,
368
  Suld3DV2I64Trap,
369
  Suld3DV4I8Trap,
370
  Suld3DV4I16Trap,
371
  Suld3DV4I32Trap,
372
373
  Suld1DI8Zero,
374
  Suld1DI16Zero,
375
  Suld1DI32Zero,
376
  Suld1DI64Zero,
377
  Suld1DV2I8Zero,
378
  Suld1DV2I16Zero,
379
  Suld1DV2I32Zero,
380
  Suld1DV2I64Zero,
381
  Suld1DV4I8Zero,
382
  Suld1DV4I16Zero,
383
  Suld1DV4I32Zero,
384
385
  Suld1DArrayI8Zero,
386
  Suld1DArrayI16Zero,
387
  Suld1DArrayI32Zero,
388
  Suld1DArrayI64Zero,
389
  Suld1DArrayV2I8Zero,
390
  Suld1DArrayV2I16Zero,
391
  Suld1DArrayV2I32Zero,
392
  Suld1DArrayV2I64Zero,
393
  Suld1DArrayV4I8Zero,
394
  Suld1DArrayV4I16Zero,
395
  Suld1DArrayV4I32Zero,
396
397
  Suld2DI8Zero,
398
  Suld2DI16Zero,
399
  Suld2DI32Zero,
400
  Suld2DI64Zero,
401
  Suld2DV2I8Zero,
402
  Suld2DV2I16Zero,
403
  Suld2DV2I32Zero,
404
  Suld2DV2I64Zero,
405
  Suld2DV4I8Zero,
406
  Suld2DV4I16Zero,
407
  Suld2DV4I32Zero,
408
409
  Suld2DArrayI8Zero,
410
  Suld2DArrayI16Zero,
411
  Suld2DArrayI32Zero,
412
  Suld2DArrayI64Zero,
413
  Suld2DArrayV2I8Zero,
414
  Suld2DArrayV2I16Zero,
415
  Suld2DArrayV2I32Zero,
416
  Suld2DArrayV2I64Zero,
417
  Suld2DArrayV4I8Zero,
418
  Suld2DArrayV4I16Zero,
419
  Suld2DArrayV4I32Zero,
420
421
  Suld3DI8Zero,
422
  Suld3DI16Zero,
423
  Suld3DI32Zero,
424
  Suld3DI64Zero,
425
  Suld3DV2I8Zero,
426
  Suld3DV2I16Zero,
427
  Suld3DV2I32Zero,
428
  Suld3DV2I64Zero,
429
  Suld3DV4I8Zero,
430
  Suld3DV4I16Zero,
431
  Suld3DV4I32Zero
432
};
433
}
434
435
class NVPTXSubtarget;
436
437
//===--------------------------------------------------------------------===//
438
// TargetLowering Implementation
439
//===--------------------------------------------------------------------===//
440
class NVPTXTargetLowering : public TargetLowering {
441
public:
442
  explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
443
                               const NVPTXSubtarget &STI);
444
  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
445
446
  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
447
448
  const char *getTargetNodeName(unsigned Opcode) const override;
449
450
  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
451
                          MachineFunction &MF,
452
                          unsigned Intrinsic) const override;
453
454
  /// isLegalAddressingMode - Return true if the addressing mode represented
455
  /// by AM is legal for this target, for a load/store of the specified type
456
  /// Used to guide target specific optimizations, like loop strength
457
  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
458
  /// address mode (CodeGenPrepare.cpp)
459
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
460
                             unsigned AS,
461
                             Instruction *I = nullptr) const override;
462
463
100
  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
464
100
    // Truncating 64-bit to 32-bit is free in SASS.
465
100
    if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
466
0
      return false;
467
100
    return SrcTy->getPrimitiveSizeInBits() == 64 &&
468
100
           
DstTy->getPrimitiveSizeInBits() == 3252
;
469
100
  }
470
471
  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
472
958
                         EVT VT) const override {
473
958
    if (VT.isVector())
474
2
      return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
475
956
    return MVT::i1;
476
956
  }
477
478
  ConstraintType getConstraintType(StringRef Constraint) const override;
479
  std::pair<unsigned, const TargetRegisterClass *>
480
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
481
                               StringRef Constraint, MVT VT) const override;
482
483
  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
484
                               bool isVarArg,
485
                               const SmallVectorImpl<ISD::InputArg> &Ins,
486
                               const SDLoc &dl, SelectionDAG &DAG,
487
                               SmallVectorImpl<SDValue> &InVals) const override;
488
489
  SDValue LowerCall(CallLoweringInfo &CLI,
490
                    SmallVectorImpl<SDValue> &InVals) const override;
491
492
  std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
493
                           const SmallVectorImpl<ISD::OutputArg> &,
494
                           unsigned retAlignment,
495
                           ImmutableCallSite CS) const;
496
497
  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
498
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
499
                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
500
                      SelectionDAG &DAG) const override;
501
502
  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
503
                                    std::vector<SDValue> &Ops,
504
                                    SelectionDAG &DAG) const override;
505
506
  const NVPTXTargetMachine *nvTM;
507
508
  // PTX always uses 32-bit shift amounts
509
612
  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
510
612
    return MVT::i32;
511
612
  }
512
513
  TargetLoweringBase::LegalizeTypeAction
514
  getPreferredVectorAction(MVT VT) const override;
515
516
  // Get the degree of precision we want from 32-bit floating point division
517
  // operations.
518
  //
519
  //  0 - Use ptx div.approx
520
  //  1 - Use ptx.div.full (approximate, but less so than div.approx)
521
  //  2 - Use IEEE-compliant div instructions, if available.
522
  int getDivF32Level() const;
523
524
  // Get whether we should use a precise or approximate 32-bit floating point
525
  // sqrt instruction.
526
  bool usePrecSqrtF32() const;
527
528
  // Get whether we should use instructions that flush floating-point denormals
529
  // to sign-preserving zero.
530
  bool useF32FTZ(const MachineFunction &MF) const;
531
532
  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
533
                          int &ExtraSteps, bool &UseOneConst,
534
                          bool Reciprocal) const override;
535
536
16
  unsigned combineRepeatedFPDivisors() const override { return 2; }
537
538
  bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
539
  bool allowUnsafeFPMath(MachineFunction &MF) const;
540
541
515
  bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
542
543
74
  bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
544
545
  // The default is to transform llvm.ctlz(x, false) (where false indicates that
546
  // x == 0 is not undefined behavior) into a branch that checks whether x is 0
547
  // and avoids calling ctlz in that case.  We have a dedicated ctlz
548
  // instruction, so we say that ctlz is cheap to speculate.
549
7
  bool isCheapToSpeculateCtlz() const override { return true; }
550
551
private:
552
  const NVPTXSubtarget &STI; // cache the subtarget here
553
  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
554
555
  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
556
  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
557
  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
558
559
  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
560
  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
561
  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
562
563
  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
564
  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
565
566
  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
567
  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
568
  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
569
570
  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
571
  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
572
573
  SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
574
575
  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
576
                          SelectionDAG &DAG) const override;
577
  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
578
579
  unsigned getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty,
580
                                unsigned Idx, const DataLayout &DL) const;
581
};
582
} // namespace llvm
583
584
#endif