/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
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1 | | //===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | |
9 | | #include "PPCMachineScheduler.h" |
10 | | #include "MCTargetDesc/PPCMCTargetDesc.h" |
11 | | |
12 | | using namespace llvm; |
13 | | |
14 | | static cl::opt<bool> |
15 | | DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", |
16 | | cl::desc("Disable scheduling addi instruction before" |
17 | | "load for ppc"), cl::Hidden); |
18 | | |
19 | | bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand, |
20 | | SchedCandidate &TryCand, |
21 | 40.0k | SchedBoundary &Zone) const { |
22 | 40.0k | if (DisableAddiLoadHeuristic) |
23 | 10 | return false; |
24 | 39.9k | |
25 | 47.0k | auto isADDIInstr = [&] (const MachineInstr &Inst) 39.9k { |
26 | 47.0k | return Inst.getOpcode() == PPC::ADDI || Inst.getOpcode() == PPC::ADDI846.9k ; |
27 | 47.0k | }; |
28 | 39.9k | |
29 | 39.9k | SchedCandidate &FirstCand = Zone.isTop() ? TryCand13.1k : Cand26.8k ; |
30 | 39.9k | SchedCandidate &SecondCand = Zone.isTop() ? Cand13.1k : TryCand26.8k ; |
31 | 39.9k | if (isADDIInstr(*FirstCand.SU->getInstr()) && |
32 | 39.9k | SecondCand.SU->getInstr()->mayLoad()341 ) { |
33 | 37 | TryCand.Reason = Stall; |
34 | 37 | return true; |
35 | 37 | } |
36 | 39.9k | if (FirstCand.SU->getInstr()->mayLoad() && |
37 | 39.9k | isADDIInstr(*SecondCand.SU->getInstr())7.01k ) { |
38 | 22 | TryCand.Reason = NoCand; |
39 | 22 | return true; |
40 | 22 | } |
41 | 39.9k | |
42 | 39.9k | return false; |
43 | 39.9k | } |
44 | | |
45 | | void PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand, |
46 | | SchedCandidate &TryCand, |
47 | 70.3k | SchedBoundary *Zone) const { |
48 | 70.3k | GenericScheduler::tryCandidate(Cand, TryCand, Zone); |
49 | 70.3k | |
50 | 70.3k | if (!Cand.isValid() || !Zone55.2k ) |
51 | 27.0k | return; |
52 | 43.3k | |
53 | 43.3k | // Add powerpc specific heuristic only when TryCand isn't selected or |
54 | 43.3k | // selected as node order. |
55 | 43.3k | if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand31.6k ) |
56 | 3.32k | return; |
57 | 40.0k | |
58 | 40.0k | // There are some benefits to schedule the ADDI before the load to hide the |
59 | 40.0k | // latency, as RA may create a true dependency between the load and addi. |
60 | 40.0k | if (biasAddiLoadCandidate(Cand, TryCand, *Zone)) |
61 | 59 | return; |
62 | 40.0k | } |
63 | | |
64 | 2.69k | void PPCPostRASchedStrategy::enterMBB(MachineBasicBlock *MBB) { |
65 | 2.69k | // Custom PPC PostRA specific behavior here. |
66 | 2.69k | PostGenericScheduler::enterMBB(MBB); |
67 | 2.69k | } |
68 | | |
69 | 2.69k | void PPCPostRASchedStrategy::leaveMBB() { |
70 | 2.69k | // Custom PPC PostRA specific behavior here. |
71 | 2.69k | PostGenericScheduler::leaveMBB(); |
72 | 2.69k | } |
73 | | |
74 | 2.63k | void PPCPostRASchedStrategy::initialize(ScheduleDAGMI *Dag) { |
75 | 2.63k | // Custom PPC PostRA specific initialization here. |
76 | 2.63k | PostGenericScheduler::initialize(Dag); |
77 | 2.63k | } |
78 | | |
79 | 19.7k | SUnit *PPCPostRASchedStrategy::pickNode(bool &IsTopNode) { |
80 | 19.7k | // Custom PPC PostRA specific scheduling here. |
81 | 19.7k | return PostGenericScheduler::pickNode(IsTopNode); |
82 | 19.7k | } |
83 | | |