/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
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1 | | //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | /// |
9 | | /// This file provides RISCV-specific target descriptions. |
10 | | /// |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "RISCVMCTargetDesc.h" |
14 | | #include "RISCVELFStreamer.h" |
15 | | #include "RISCVInstPrinter.h" |
16 | | #include "RISCVMCAsmInfo.h" |
17 | | #include "RISCVTargetStreamer.h" |
18 | | #include "TargetInfo/RISCVTargetInfo.h" |
19 | | #include "llvm/ADT/STLExtras.h" |
20 | | #include "llvm/MC/MCAsmInfo.h" |
21 | | #include "llvm/MC/MCInstrInfo.h" |
22 | | #include "llvm/MC/MCRegisterInfo.h" |
23 | | #include "llvm/MC/MCStreamer.h" |
24 | | #include "llvm/MC/MCSubtargetInfo.h" |
25 | | #include "llvm/Support/ErrorHandling.h" |
26 | | #include "llvm/Support/TargetRegistry.h" |
27 | | |
28 | | #define GET_INSTRINFO_MC_DESC |
29 | | #include "RISCVGenInstrInfo.inc" |
30 | | |
31 | | #define GET_REGINFO_MC_DESC |
32 | | #include "RISCVGenRegisterInfo.inc" |
33 | | |
34 | | #define GET_SUBTARGETINFO_MC_DESC |
35 | | #include "RISCVGenSubtargetInfo.inc" |
36 | | |
37 | | using namespace llvm; |
38 | | |
39 | 963 | static MCInstrInfo *createRISCVMCInstrInfo() { |
40 | 963 | MCInstrInfo *X = new MCInstrInfo(); |
41 | 963 | InitRISCVMCInstrInfo(X); |
42 | 963 | return X; |
43 | 963 | } |
44 | | |
45 | 966 | static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { |
46 | 966 | MCRegisterInfo *X = new MCRegisterInfo(); |
47 | 966 | InitRISCVMCRegisterInfo(X, RISCV::X1); |
48 | 966 | return X; |
49 | 966 | } |
50 | | |
51 | | static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, |
52 | 962 | const Triple &TT) { |
53 | 962 | MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); |
54 | 962 | |
55 | 962 | unsigned SP = MRI.getDwarfRegNum(RISCV::X2, true); |
56 | 962 | MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); |
57 | 962 | MAI->addInitialFrameState(Inst); |
58 | 962 | |
59 | 962 | return MAI; |
60 | 962 | } |
61 | | |
62 | | static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, |
63 | 954 | StringRef CPU, StringRef FS) { |
64 | 954 | std::string CPUName = CPU; |
65 | 954 | if (CPUName.empty()) |
66 | 954 | CPUName = TT.isArch64Bit() ? "generic-rv64"410 : "generic-rv32"544 ; |
67 | 954 | return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS); |
68 | 954 | } |
69 | | |
70 | | static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, |
71 | | unsigned SyntaxVariant, |
72 | | const MCAsmInfo &MAI, |
73 | | const MCInstrInfo &MII, |
74 | 667 | const MCRegisterInfo &MRI) { |
75 | 667 | return new RISCVInstPrinter(MAI, MII, MRI); |
76 | 667 | } |
77 | | |
78 | | static MCTargetStreamer * |
79 | 245 | createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { |
80 | 245 | const Triple &TT = STI.getTargetTriple(); |
81 | 245 | if (TT.isOSBinFormatELF()) |
82 | 245 | return new RISCVTargetELFStreamer(S, STI); |
83 | 0 | return nullptr; |
84 | 0 | } |
85 | | |
86 | | static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, |
87 | | formatted_raw_ostream &OS, |
88 | | MCInstPrinter *InstPrint, |
89 | 500 | bool isVerboseAsm) { |
90 | 500 | return new RISCVTargetAsmStreamer(S, OS); |
91 | 500 | } |
92 | | |
93 | 96.4k | extern "C" void LLVMInitializeRISCVTargetMC() { |
94 | 192k | for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { |
95 | 192k | TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); |
96 | 192k | TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); |
97 | 192k | TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); |
98 | 192k | TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); |
99 | 192k | TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); |
100 | 192k | TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); |
101 | 192k | TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); |
102 | 192k | TargetRegistry::RegisterObjectTargetStreamer( |
103 | 192k | *T, createRISCVObjectTargetStreamer); |
104 | 192k | |
105 | 192k | // Register the asm target streamer. |
106 | 192k | TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); |
107 | 192k | } |
108 | 96.4k | } |