/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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1 | | //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | |
9 | | #include "MCTargetDesc/SparcMCExpr.h" |
10 | | #include "MCTargetDesc/SparcMCTargetDesc.h" |
11 | | #include "TargetInfo/SparcTargetInfo.h" |
12 | | #include "llvm/ADT/STLExtras.h" |
13 | | #include "llvm/ADT/SmallVector.h" |
14 | | #include "llvm/ADT/StringRef.h" |
15 | | #include "llvm/ADT/Triple.h" |
16 | | #include "llvm/MC/MCContext.h" |
17 | | #include "llvm/MC/MCExpr.h" |
18 | | #include "llvm/MC/MCInst.h" |
19 | | #include "llvm/MC/MCObjectFileInfo.h" |
20 | | #include "llvm/MC/MCParser/MCAsmLexer.h" |
21 | | #include "llvm/MC/MCParser/MCAsmParser.h" |
22 | | #include "llvm/MC/MCParser/MCParsedAsmOperand.h" |
23 | | #include "llvm/MC/MCParser/MCTargetAsmParser.h" |
24 | | #include "llvm/MC/MCRegisterInfo.h" |
25 | | #include "llvm/MC/MCStreamer.h" |
26 | | #include "llvm/MC/MCSubtargetInfo.h" |
27 | | #include "llvm/MC/MCSymbol.h" |
28 | | #include "llvm/Support/Casting.h" |
29 | | #include "llvm/Support/ErrorHandling.h" |
30 | | #include "llvm/Support/SMLoc.h" |
31 | | #include "llvm/Support/TargetRegistry.h" |
32 | | #include "llvm/Support/raw_ostream.h" |
33 | | #include <algorithm> |
34 | | #include <cassert> |
35 | | #include <cstdint> |
36 | | #include <memory> |
37 | | |
38 | | using namespace llvm; |
39 | | |
40 | | // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target |
41 | | // namespace. But SPARC backend uses "SP" as its namespace. |
42 | | namespace llvm { |
43 | | namespace Sparc { |
44 | | |
45 | | using namespace SP; |
46 | | |
47 | | } // end namespace Sparc |
48 | | } // end namespace llvm |
49 | | |
50 | | namespace { |
51 | | |
52 | | class SparcOperand; |
53 | | |
54 | | class SparcAsmParser : public MCTargetAsmParser { |
55 | | MCAsmParser &Parser; |
56 | | |
57 | | /// @name Auto-generated Match Functions |
58 | | /// { |
59 | | |
60 | | #define GET_ASSEMBLER_HEADER |
61 | | #include "SparcGenAsmMatcher.inc" |
62 | | |
63 | | /// } |
64 | | |
65 | | // public interface of the MCTargetAsmParser. |
66 | | bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
67 | | OperandVector &Operands, MCStreamer &Out, |
68 | | uint64_t &ErrorInfo, |
69 | | bool MatchingInlineAsm) override; |
70 | | bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; |
71 | | bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, |
72 | | SMLoc NameLoc, OperandVector &Operands) override; |
73 | | bool ParseDirective(AsmToken DirectiveID) override; |
74 | | |
75 | | unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, |
76 | | unsigned Kind) override; |
77 | | |
78 | | // Custom parse functions for Sparc specific operands. |
79 | | OperandMatchResultTy parseMEMOperand(OperandVector &Operands); |
80 | | |
81 | | OperandMatchResultTy parseMembarTag(OperandVector &Operands); |
82 | | |
83 | | OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name); |
84 | | |
85 | | OperandMatchResultTy |
86 | | parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand, |
87 | | bool isCall = false); |
88 | | |
89 | | OperandMatchResultTy parseBranchModifiers(OperandVector &Operands); |
90 | | |
91 | | // Helper function for dealing with %lo / %hi in PIC mode. |
92 | | const SparcMCExpr *adjustPICRelocation(SparcMCExpr::VariantKind VK, |
93 | | const MCExpr *subExpr); |
94 | | |
95 | | // returns true if Tok is matched to a register and returns register in RegNo. |
96 | | bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, |
97 | | unsigned &RegKind); |
98 | | |
99 | | bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); |
100 | | |
101 | 270 | bool is64Bit() const { |
102 | 270 | return getSTI().getTargetTriple().getArch() == Triple::sparcv9; |
103 | 270 | } |
104 | | |
105 | | bool expandSET(MCInst &Inst, SMLoc IDLoc, |
106 | | SmallVectorImpl<MCInst> &Instructions); |
107 | | |
108 | | public: |
109 | | SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, |
110 | | const MCInstrInfo &MII, |
111 | | const MCTargetOptions &Options) |
112 | 109 | : MCTargetAsmParser(Options, sti, MII), Parser(parser) { |
113 | 109 | Parser.addAliasForDirective(".half", ".2byte"); |
114 | 109 | Parser.addAliasForDirective(".uahalf", ".2byte"); |
115 | 109 | Parser.addAliasForDirective(".word", ".4byte"); |
116 | 109 | Parser.addAliasForDirective(".uaword", ".4byte"); |
117 | 109 | Parser.addAliasForDirective(".nword", is64Bit() ? ".8byte"46 : ".4byte"63 ); |
118 | 109 | if (is64Bit()) |
119 | 46 | Parser.addAliasForDirective(".xword", ".8byte"); |
120 | 109 | |
121 | 109 | // Initialize the set of available features. |
122 | 109 | setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); |
123 | 109 | } |
124 | | }; |
125 | | |
126 | | } // end anonymous namespace |
127 | | |
128 | | static const MCPhysReg IntRegs[32] = { |
129 | | Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3, |
130 | | Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7, |
131 | | Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3, |
132 | | Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7, |
133 | | Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3, |
134 | | Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7, |
135 | | Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3, |
136 | | Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 }; |
137 | | |
138 | | static const MCPhysReg FloatRegs[32] = { |
139 | | Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3, |
140 | | Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7, |
141 | | Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11, |
142 | | Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15, |
143 | | Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19, |
144 | | Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23, |
145 | | Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27, |
146 | | Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 }; |
147 | | |
148 | | static const MCPhysReg DoubleRegs[32] = { |
149 | | Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3, |
150 | | Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7, |
151 | | Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11, |
152 | | Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15, |
153 | | Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19, |
154 | | Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23, |
155 | | Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27, |
156 | | Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 }; |
157 | | |
158 | | static const MCPhysReg QuadFPRegs[32] = { |
159 | | Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3, |
160 | | Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7, |
161 | | Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11, |
162 | | Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 }; |
163 | | |
164 | | static const MCPhysReg ASRRegs[32] = { |
165 | | SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, |
166 | | SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, |
167 | | SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, |
168 | | SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, |
169 | | SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, |
170 | | SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, |
171 | | SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, |
172 | | SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; |
173 | | |
174 | | static const MCPhysReg IntPairRegs[] = { |
175 | | Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7, |
176 | | Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7, |
177 | | Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7, |
178 | | Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7}; |
179 | | |
180 | | static const MCPhysReg CoprocRegs[32] = { |
181 | | Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3, |
182 | | Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7, |
183 | | Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11, |
184 | | Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15, |
185 | | Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19, |
186 | | Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23, |
187 | | Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27, |
188 | | Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 }; |
189 | | |
190 | | static const MCPhysReg CoprocPairRegs[] = { |
191 | | Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7, |
192 | | Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15, |
193 | | Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23, |
194 | | Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31}; |
195 | | |
196 | | namespace { |
197 | | |
198 | | /// SparcOperand - Instances of this class represent a parsed Sparc machine |
199 | | /// instruction. |
200 | | class SparcOperand : public MCParsedAsmOperand { |
201 | | public: |
202 | | enum RegisterKind { |
203 | | rk_None, |
204 | | rk_IntReg, |
205 | | rk_IntPairReg, |
206 | | rk_FloatReg, |
207 | | rk_DoubleReg, |
208 | | rk_QuadReg, |
209 | | rk_CoprocReg, |
210 | | rk_CoprocPairReg, |
211 | | rk_Special, |
212 | | }; |
213 | | |
214 | | private: |
215 | | enum KindTy { |
216 | | k_Token, |
217 | | k_Register, |
218 | | k_Immediate, |
219 | | k_MemoryReg, |
220 | | k_MemoryImm |
221 | | } Kind; |
222 | | |
223 | | SMLoc StartLoc, EndLoc; |
224 | | |
225 | | struct Token { |
226 | | const char *Data; |
227 | | unsigned Length; |
228 | | }; |
229 | | |
230 | | struct RegOp { |
231 | | unsigned RegNum; |
232 | | RegisterKind Kind; |
233 | | }; |
234 | | |
235 | | struct ImmOp { |
236 | | const MCExpr *Val; |
237 | | }; |
238 | | |
239 | | struct MemOp { |
240 | | unsigned Base; |
241 | | unsigned OffsetReg; |
242 | | const MCExpr *Off; |
243 | | }; |
244 | | |
245 | | union { |
246 | | struct Token Tok; |
247 | | struct RegOp Reg; |
248 | | struct ImmOp Imm; |
249 | | struct MemOp Mem; |
250 | | }; |
251 | | |
252 | | public: |
253 | 6.71k | SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} |
254 | | |
255 | 11.4k | bool isToken() const override { return Kind == k_Token; } |
256 | 5.70k | bool isReg() const override { return Kind == k_Register; } |
257 | 2.14k | bool isImm() const override { return Kind == k_Immediate; } |
258 | 0 | bool isMem() const override { return isMEMrr() || isMEMri(); } |
259 | 319 | bool isMEMrr() const { return Kind == k_MemoryReg; } |
260 | 368 | bool isMEMri() const { return Kind == k_MemoryImm; } |
261 | 5 | bool isMembarTag() const { return Kind == k_Immediate; } |
262 | | |
263 | 4.69k | bool isIntReg() const { |
264 | 4.69k | return (Kind == k_Register && Reg.Kind == rk_IntReg1.03k ); |
265 | 4.69k | } |
266 | | |
267 | 66 | bool isFloatReg() const { |
268 | 66 | return (Kind == k_Register && Reg.Kind == rk_FloatReg); |
269 | 66 | } |
270 | | |
271 | 4.81k | bool isFloatOrDoubleReg() const { |
272 | 4.81k | return (Kind == k_Register && (1.15k Reg.Kind == rk_FloatReg1.15k |
273 | 1.15k | || Reg.Kind == rk_DoubleReg1.03k )); |
274 | 4.81k | } |
275 | | |
276 | 4.67k | bool isCoprocReg() const { |
277 | 4.67k | return (Kind == k_Register && Reg.Kind == rk_CoprocReg1.01k ); |
278 | 4.67k | } |
279 | | |
280 | 6.01k | StringRef getToken() const { |
281 | 6.01k | assert(Kind == k_Token && "Invalid access!"); |
282 | 6.01k | return StringRef(Tok.Data, Tok.Length); |
283 | 6.01k | } |
284 | | |
285 | 6.09k | unsigned getReg() const override { |
286 | 6.09k | assert((Kind == k_Register) && "Invalid access!"); |
287 | 6.09k | return Reg.RegNum; |
288 | 6.09k | } |
289 | | |
290 | 1.06k | const MCExpr *getImm() const { |
291 | 1.06k | assert((Kind == k_Immediate) && "Invalid access!"); |
292 | 1.06k | return Imm.Val; |
293 | 1.06k | } |
294 | | |
295 | 246 | unsigned getMemBase() const { |
296 | 246 | assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!"); |
297 | 246 | return Mem.Base; |
298 | 246 | } |
299 | | |
300 | 186 | unsigned getMemOffsetReg() const { |
301 | 186 | assert((Kind == k_MemoryReg) && "Invalid access!"); |
302 | 186 | return Mem.OffsetReg; |
303 | 186 | } |
304 | | |
305 | 60 | const MCExpr *getMemOff() const { |
306 | 60 | assert((Kind == k_MemoryImm) && "Invalid access!"); |
307 | 60 | return Mem.Off; |
308 | 60 | } |
309 | | |
310 | | /// getStartLoc - Get the location of the first token of this operand. |
311 | 0 | SMLoc getStartLoc() const override { |
312 | 0 | return StartLoc; |
313 | 0 | } |
314 | | /// getEndLoc - Get the location of the last token of this operand. |
315 | 0 | SMLoc getEndLoc() const override { |
316 | 0 | return EndLoc; |
317 | 0 | } |
318 | | |
319 | | void print(raw_ostream &OS) const override { |
320 | | switch (Kind) { |
321 | | case k_Token: OS << "Token: " << getToken() << "\n"; break; |
322 | | case k_Register: OS << "Reg: #" << getReg() << "\n"; break; |
323 | | case k_Immediate: OS << "Imm: " << getImm() << "\n"; break; |
324 | | case k_MemoryReg: OS << "Mem: " << getMemBase() << "+" |
325 | | << getMemOffsetReg() << "\n"; break; |
326 | | case k_MemoryImm: assert(getMemOff() != nullptr); |
327 | | OS << "Mem: " << getMemBase() |
328 | | << "+" << *getMemOff() |
329 | | << "\n"; break; |
330 | | } |
331 | | } |
332 | | |
333 | 2.08k | void addRegOperands(MCInst &Inst, unsigned N) const { |
334 | 2.08k | assert(N == 1 && "Invalid number of operands!"); |
335 | 2.08k | Inst.addOperand(MCOperand::createReg(getReg())); |
336 | 2.08k | } |
337 | | |
338 | 995 | void addImmOperands(MCInst &Inst, unsigned N) const { |
339 | 995 | assert(N == 1 && "Invalid number of operands!"); |
340 | 995 | const MCExpr *Expr = getImm(); |
341 | 995 | addExpr(Inst, Expr); |
342 | 995 | } |
343 | | |
344 | 1.05k | void addExpr(MCInst &Inst, const MCExpr *Expr) const{ |
345 | 1.05k | // Add as immediate when possible. Null MCExpr = 0. |
346 | 1.05k | if (!Expr) |
347 | 0 | Inst.addOperand(MCOperand::createImm(0)); |
348 | 1.05k | else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) |
349 | 402 | Inst.addOperand(MCOperand::createImm(CE->getValue())); |
350 | 657 | else |
351 | 657 | Inst.addOperand(MCOperand::createExpr(Expr)); |
352 | 1.05k | } |
353 | | |
354 | 186 | void addMEMrrOperands(MCInst &Inst, unsigned N) const { |
355 | 186 | assert(N == 2 && "Invalid number of operands!"); |
356 | 186 | |
357 | 186 | Inst.addOperand(MCOperand::createReg(getMemBase())); |
358 | 186 | |
359 | 186 | assert(getMemOffsetReg() != 0 && "Invalid offset"); |
360 | 186 | Inst.addOperand(MCOperand::createReg(getMemOffsetReg())); |
361 | 186 | } |
362 | | |
363 | 60 | void addMEMriOperands(MCInst &Inst, unsigned N) const { |
364 | 60 | assert(N == 2 && "Invalid number of operands!"); |
365 | 60 | |
366 | 60 | Inst.addOperand(MCOperand::createReg(getMemBase())); |
367 | 60 | |
368 | 60 | const MCExpr *Expr = getMemOff(); |
369 | 60 | addExpr(Inst, Expr); |
370 | 60 | } |
371 | | |
372 | 4 | void addMembarTagOperands(MCInst &Inst, unsigned N) const { |
373 | 4 | assert(N == 1 && "Invalid number of operands!"); |
374 | 4 | const MCExpr *Expr = getImm(); |
375 | 4 | addExpr(Inst, Expr); |
376 | 4 | } |
377 | | |
378 | 3.28k | static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) { |
379 | 3.28k | auto Op = make_unique<SparcOperand>(k_Token); |
380 | 3.28k | Op->Tok.Data = Str.data(); |
381 | 3.28k | Op->Tok.Length = Str.size(); |
382 | 3.28k | Op->StartLoc = S; |
383 | 3.28k | Op->EndLoc = S; |
384 | 3.28k | return Op; |
385 | 3.28k | } |
386 | | |
387 | | static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, |
388 | 2.26k | SMLoc S, SMLoc E) { |
389 | 2.26k | auto Op = make_unique<SparcOperand>(k_Register); |
390 | 2.26k | Op->Reg.RegNum = RegNum; |
391 | 2.26k | Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; |
392 | 2.26k | Op->StartLoc = S; |
393 | 2.26k | Op->EndLoc = E; |
394 | 2.26k | return Op; |
395 | 2.26k | } |
396 | | |
397 | | static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S, |
398 | 1.08k | SMLoc E) { |
399 | 1.08k | auto Op = make_unique<SparcOperand>(k_Immediate); |
400 | 1.08k | Op->Imm.Val = Val; |
401 | 1.08k | Op->StartLoc = S; |
402 | 1.08k | Op->EndLoc = E; |
403 | 1.08k | return Op; |
404 | 1.08k | } |
405 | | |
406 | 21 | static bool MorphToIntPairReg(SparcOperand &Op) { |
407 | 21 | unsigned Reg = Op.getReg(); |
408 | 21 | assert(Op.Reg.Kind == rk_IntReg); |
409 | 21 | unsigned regIdx = 32; |
410 | 21 | if (Reg >= Sparc::G0 && Reg <= Sparc::G7) |
411 | 2 | regIdx = Reg - Sparc::G0; |
412 | 19 | else if (Reg >= Sparc::O0 && Reg <= Sparc::O717 ) |
413 | 17 | regIdx = Reg - Sparc::O0 + 8; |
414 | 2 | else if (Reg >= Sparc::L0 && Reg <= Sparc::L71 ) |
415 | 1 | regIdx = Reg - Sparc::L0 + 16; |
416 | 1 | else if (Reg >= Sparc::I0 && Reg <= Sparc::I7) |
417 | 1 | regIdx = Reg - Sparc::I0 + 24; |
418 | 21 | if (regIdx % 2 || regIdx > 31) |
419 | 0 | return false; |
420 | 21 | Op.Reg.RegNum = IntPairRegs[regIdx / 2]; |
421 | 21 | Op.Reg.Kind = rk_IntPairReg; |
422 | 21 | return true; |
423 | 21 | } |
424 | | |
425 | 66 | static bool MorphToDoubleReg(SparcOperand &Op) { |
426 | 66 | unsigned Reg = Op.getReg(); |
427 | 66 | assert(Op.Reg.Kind == rk_FloatReg); |
428 | 66 | unsigned regIdx = Reg - Sparc::F0; |
429 | 66 | if (regIdx % 2 || regIdx > 31) |
430 | 0 | return false; |
431 | 66 | Op.Reg.RegNum = DoubleRegs[regIdx / 2]; |
432 | 66 | Op.Reg.Kind = rk_DoubleReg; |
433 | 66 | return true; |
434 | 66 | } |
435 | | |
436 | 58 | static bool MorphToQuadReg(SparcOperand &Op) { |
437 | 58 | unsigned Reg = Op.getReg(); |
438 | 58 | unsigned regIdx = 0; |
439 | 58 | switch (Op.Reg.Kind) { |
440 | 58 | default: 0 llvm_unreachable0 ("Unexpected register kind!"); |
441 | 58 | case rk_FloatReg: |
442 | 44 | regIdx = Reg - Sparc::F0; |
443 | 44 | if (regIdx % 4 || regIdx > 31) |
444 | 0 | return false; |
445 | 44 | Reg = QuadFPRegs[regIdx / 4]; |
446 | 44 | break; |
447 | 44 | case rk_DoubleReg: |
448 | 14 | regIdx = Reg - Sparc::D0; |
449 | 14 | if (regIdx % 2 || regIdx > 31) |
450 | 0 | return false; |
451 | 14 | Reg = QuadFPRegs[regIdx / 2]; |
452 | 14 | break; |
453 | 58 | } |
454 | 58 | Op.Reg.RegNum = Reg; |
455 | 58 | Op.Reg.Kind = rk_QuadReg; |
456 | 58 | return true; |
457 | 58 | } |
458 | | |
459 | 10 | static bool MorphToCoprocPairReg(SparcOperand &Op) { |
460 | 10 | unsigned Reg = Op.getReg(); |
461 | 10 | assert(Op.Reg.Kind == rk_CoprocReg); |
462 | 10 | unsigned regIdx = 32; |
463 | 10 | if (Reg >= Sparc::C0 && Reg <= Sparc::C31) |
464 | 10 | regIdx = Reg - Sparc::C0; |
465 | 10 | if (regIdx % 2 || regIdx > 31) |
466 | 0 | return false; |
467 | 10 | Op.Reg.RegNum = CoprocPairRegs[regIdx / 2]; |
468 | 10 | Op.Reg.Kind = rk_CoprocPairReg; |
469 | 10 | return true; |
470 | 10 | } |
471 | | |
472 | | static std::unique_ptr<SparcOperand> |
473 | 114 | MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) { |
474 | 114 | unsigned offsetReg = Op->getReg(); |
475 | 114 | Op->Kind = k_MemoryReg; |
476 | 114 | Op->Mem.Base = Base; |
477 | 114 | Op->Mem.OffsetReg = offsetReg; |
478 | 114 | Op->Mem.Off = nullptr; |
479 | 114 | return Op; |
480 | 114 | } |
481 | | |
482 | | static std::unique_ptr<SparcOperand> |
483 | 85 | CreateMEMr(unsigned Base, SMLoc S, SMLoc E) { |
484 | 85 | auto Op = make_unique<SparcOperand>(k_MemoryReg); |
485 | 85 | Op->Mem.Base = Base; |
486 | 85 | Op->Mem.OffsetReg = Sparc::G0; // always 0 |
487 | 85 | Op->Mem.Off = nullptr; |
488 | 85 | Op->StartLoc = S; |
489 | 85 | Op->EndLoc = E; |
490 | 85 | return Op; |
491 | 85 | } |
492 | | |
493 | | static std::unique_ptr<SparcOperand> |
494 | 63 | MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) { |
495 | 63 | const MCExpr *Imm = Op->getImm(); |
496 | 63 | Op->Kind = k_MemoryImm; |
497 | 63 | Op->Mem.Base = Base; |
498 | 63 | Op->Mem.OffsetReg = 0; |
499 | 63 | Op->Mem.Off = Imm; |
500 | 63 | return Op; |
501 | 63 | } |
502 | | }; |
503 | | |
504 | | } // end anonymous namespace |
505 | | |
506 | | bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, |
507 | 60 | SmallVectorImpl<MCInst> &Instructions) { |
508 | 60 | MCOperand MCRegOp = Inst.getOperand(0); |
509 | 60 | MCOperand MCValOp = Inst.getOperand(1); |
510 | 60 | assert(MCRegOp.isReg()); |
511 | 60 | assert(MCValOp.isImm() || MCValOp.isExpr()); |
512 | 60 | |
513 | 60 | // the imm operand can be either an expression or an immediate. |
514 | 60 | bool IsImm = Inst.getOperand(1).isImm(); |
515 | 60 | int64_t RawImmValue = IsImm ? MCValOp.getImm()56 : 04 ; |
516 | 60 | |
517 | 60 | // Allow either a signed or unsigned 32-bit immediate. |
518 | 60 | if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL58 ) { |
519 | 4 | return Error(IDLoc, |
520 | 4 | "set: argument must be between -2147483648 and 4294967295"); |
521 | 4 | } |
522 | 56 | |
523 | 56 | // If the value was expressed as a large unsigned number, that's ok. |
524 | 56 | // We want to see if it "looks like" a small signed number. |
525 | 56 | int32_t ImmValue = RawImmValue; |
526 | 56 | // For 'set' you can't use 'or' with a negative operand on V9 because |
527 | 56 | // that would splat the sign bit across the upper half of the destination |
528 | 56 | // register, whereas 'set' is defined to zero the high 32 bits. |
529 | 56 | bool IsEffectivelyImm13 = |
530 | 56 | IsImm && (52 (is64Bit() 52 ? 026 : -409626 ) <= ImmValue && ImmValue < 409638 ); |
531 | 56 | const MCExpr *ValExpr; |
532 | 56 | if (IsImm) |
533 | 52 | ValExpr = MCConstantExpr::create(ImmValue, getContext()); |
534 | 4 | else |
535 | 4 | ValExpr = MCValOp.getExpr(); |
536 | 56 | |
537 | 56 | MCOperand PrevReg = MCOperand::createReg(Sparc::G0); |
538 | 56 | |
539 | 56 | // If not just a signed imm13 value, then either we use a 'sethi' with a |
540 | 56 | // following 'or', or a 'sethi' by itself if there are no more 1 bits. |
541 | 56 | // In either case, start with the 'sethi'. |
542 | 56 | if (!IsEffectivelyImm13) { |
543 | 42 | MCInst TmpInst; |
544 | 42 | const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr); |
545 | 42 | TmpInst.setLoc(IDLoc); |
546 | 42 | TmpInst.setOpcode(SP::SETHIi); |
547 | 42 | TmpInst.addOperand(MCRegOp); |
548 | 42 | TmpInst.addOperand(MCOperand::createExpr(Expr)); |
549 | 42 | Instructions.push_back(TmpInst); |
550 | 42 | PrevReg = MCRegOp; |
551 | 42 | } |
552 | 56 | |
553 | 56 | // The low bits require touching in 3 cases: |
554 | 56 | // * A non-immediate value will always require both instructions. |
555 | 56 | // * An effectively imm13 value needs only an 'or' instruction. |
556 | 56 | // * Otherwise, an immediate that is not effectively imm13 requires the |
557 | 56 | // 'or' only if bits remain after clearing the 22 bits that 'sethi' set. |
558 | 56 | // If the low bits are known zeros, there's nothing to do. |
559 | 56 | // In the second case, and only in that case, must we NOT clear |
560 | 56 | // bits of the immediate value via the %lo() assembler function. |
561 | 56 | // Note also, the 'or' instruction doesn't mind a large value in the case |
562 | 56 | // where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean. |
563 | 56 | if (!IsImm || IsEffectivelyImm1352 || (ImmValue & 0x3ff)38 ) { |
564 | 34 | MCInst TmpInst; |
565 | 34 | const MCExpr *Expr; |
566 | 34 | if (IsEffectivelyImm13) |
567 | 14 | Expr = ValExpr; |
568 | 20 | else |
569 | 20 | Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr); |
570 | 34 | TmpInst.setLoc(IDLoc); |
571 | 34 | TmpInst.setOpcode(SP::ORri); |
572 | 34 | TmpInst.addOperand(MCRegOp); |
573 | 34 | TmpInst.addOperand(PrevReg); |
574 | 34 | TmpInst.addOperand(MCOperand::createExpr(Expr)); |
575 | 34 | Instructions.push_back(TmpInst); |
576 | 34 | } |
577 | 56 | return false; |
578 | 56 | } |
579 | | |
580 | | bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
581 | | OperandVector &Operands, |
582 | | MCStreamer &Out, |
583 | | uint64_t &ErrorInfo, |
584 | 1.85k | bool MatchingInlineAsm) { |
585 | 1.85k | MCInst Inst; |
586 | 1.85k | SmallVector<MCInst, 8> Instructions; |
587 | 1.85k | unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, |
588 | 1.85k | MatchingInlineAsm); |
589 | 1.85k | switch (MatchResult) { |
590 | 1.85k | case Match_Success: { |
591 | 1.79k | switch (Inst.getOpcode()) { |
592 | 1.79k | default: |
593 | 1.73k | Inst.setLoc(IDLoc); |
594 | 1.73k | Instructions.push_back(Inst); |
595 | 1.73k | break; |
596 | 1.79k | case SP::SET: |
597 | 60 | if (expandSET(Inst, IDLoc, Instructions)) |
598 | 4 | return true; |
599 | 56 | break; |
600 | 1.78k | } |
601 | 1.78k | |
602 | 1.80k | for (const MCInst &I : Instructions)1.78k { |
603 | 1.80k | Out.EmitInstruction(I, getSTI()); |
604 | 1.80k | } |
605 | 1.78k | return false; |
606 | 1.78k | } |
607 | 1.78k | |
608 | 1.78k | case Match_MissingFeature: |
609 | 61 | return Error(IDLoc, |
610 | 61 | "instruction requires a CPU feature not currently enabled"); |
611 | 1.78k | |
612 | 1.78k | case Match_InvalidOperand: { |
613 | 0 | SMLoc ErrorLoc = IDLoc; |
614 | 0 | if (ErrorInfo != ~0ULL) { |
615 | 0 | if (ErrorInfo >= Operands.size()) |
616 | 0 | return Error(IDLoc, "too few operands for instruction"); |
617 | 0 | |
618 | 0 | ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc(); |
619 | 0 | if (ErrorLoc == SMLoc()) |
620 | 0 | ErrorLoc = IDLoc; |
621 | 0 | } |
622 | 0 |
|
623 | 0 | return Error(ErrorLoc, "invalid operand for instruction"); |
624 | 0 | } |
625 | 8 | case Match_MnemonicFail: |
626 | 8 | return Error(IDLoc, "invalid instruction mnemonic"); |
627 | 0 | } |
628 | 0 | llvm_unreachable("Implement any new match types added!"); |
629 | 0 | } |
630 | | |
631 | | bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, |
632 | 308 | SMLoc &EndLoc) { |
633 | 308 | const AsmToken &Tok = Parser.getTok(); |
634 | 308 | StartLoc = Tok.getLoc(); |
635 | 308 | EndLoc = Tok.getEndLoc(); |
636 | 308 | RegNo = 0; |
637 | 308 | if (getLexer().getKind() != AsmToken::Percent) |
638 | 44 | return false; |
639 | 264 | Parser.Lex(); |
640 | 264 | unsigned regKind = SparcOperand::rk_None; |
641 | 264 | if (matchRegisterName(Tok, RegNo, regKind)) { |
642 | 264 | Parser.Lex(); |
643 | 264 | return false; |
644 | 264 | } |
645 | 0 | |
646 | 0 | return Error(StartLoc, "invalid register name"); |
647 | 0 | } |
648 | | |
649 | | static void applyMnemonicAliases(StringRef &Mnemonic, |
650 | | const FeatureBitset &Features, |
651 | | unsigned VariantID); |
652 | | |
653 | | bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info, |
654 | | StringRef Name, SMLoc NameLoc, |
655 | 1.86k | OperandVector &Operands) { |
656 | 1.86k | |
657 | 1.86k | // First operand in MCInst is instruction mnemonic. |
658 | 1.86k | Operands.push_back(SparcOperand::CreateToken(Name, NameLoc)); |
659 | 1.86k | |
660 | 1.86k | // apply mnemonic aliases, if any, so that we can parse operands correctly. |
661 | 1.86k | applyMnemonicAliases(Name, getAvailableFeatures(), 0); |
662 | 1.86k | |
663 | 1.86k | if (getLexer().isNot(AsmToken::EndOfStatement)) { |
664 | 1.82k | // Read the first operand. |
665 | 1.82k | if (getLexer().is(AsmToken::Comma)) { |
666 | 329 | if (parseBranchModifiers(Operands) != MatchOperand_Success) { |
667 | 0 | SMLoc Loc = getLexer().getLoc(); |
668 | 0 | return Error(Loc, "unexpected token"); |
669 | 0 | } |
670 | 1.82k | } |
671 | 1.82k | if (parseOperand(Operands, Name) != MatchOperand_Success) { |
672 | 3 | SMLoc Loc = getLexer().getLoc(); |
673 | 3 | return Error(Loc, "unexpected token"); |
674 | 3 | } |
675 | 1.82k | |
676 | 3.81k | while (1.82k getLexer().is(AsmToken::Comma) || getLexer().is(AsmToken::Plus)1.91k ) { |
677 | 1.99k | if (getLexer().is(AsmToken::Plus)) { |
678 | 96 | // Plus tokens are significant in software_traps (p83, sparcv8.pdf). We must capture them. |
679 | 96 | Operands.push_back(SparcOperand::CreateToken("+", Parser.getTok().getLoc())); |
680 | 96 | } |
681 | 1.99k | Parser.Lex(); // Eat the comma or plus. |
682 | 1.99k | // Parse and remember the operand. |
683 | 1.99k | if (parseOperand(Operands, Name) != MatchOperand_Success) { |
684 | 0 | SMLoc Loc = getLexer().getLoc(); |
685 | 0 | return Error(Loc, "unexpected token"); |
686 | 0 | } |
687 | 1.99k | } |
688 | 1.82k | } |
689 | 1.86k | if (1.85k getLexer().isNot(AsmToken::EndOfStatement)1.85k ) { |
690 | 0 | SMLoc Loc = getLexer().getLoc(); |
691 | 0 | return Error(Loc, "unexpected token"); |
692 | 0 | } |
693 | 1.85k | Parser.Lex(); // Consume the EndOfStatement. |
694 | 1.85k | return false; |
695 | 1.85k | } |
696 | | |
697 | | bool SparcAsmParser:: |
698 | | ParseDirective(AsmToken DirectiveID) |
699 | 107 | { |
700 | 107 | StringRef IDVal = DirectiveID.getString(); |
701 | 107 | |
702 | 107 | if (IDVal == ".register") { |
703 | 0 | // For now, ignore .register directive. |
704 | 0 | Parser.eatToEndOfStatement(); |
705 | 0 | return false; |
706 | 0 | } |
707 | 107 | if (IDVal == ".proc") { |
708 | 2 | // For compatibility, ignore this directive. |
709 | 2 | // (It's supposed to be an "optimization" in the Sun assembler) |
710 | 2 | Parser.eatToEndOfStatement(); |
711 | 2 | return false; |
712 | 2 | } |
713 | 105 | |
714 | 105 | // Let the MC layer to handle other directives. |
715 | 105 | return true; |
716 | 105 | } |
717 | | |
718 | | OperandMatchResultTy |
719 | 306 | SparcAsmParser::parseMEMOperand(OperandVector &Operands) { |
720 | 306 | SMLoc S, E; |
721 | 306 | unsigned BaseReg = 0; |
722 | 306 | |
723 | 306 | if (ParseRegister(BaseReg, S, E)) { |
724 | 0 | return MatchOperand_NoMatch; |
725 | 0 | } |
726 | 306 | |
727 | 306 | switch (getLexer().getKind()) { |
728 | 306 | default: return MatchOperand_NoMatch44 ; |
729 | 306 | |
730 | 306 | case AsmToken::Comma: |
731 | 85 | case AsmToken::RBrac: |
732 | 85 | case AsmToken::EndOfStatement: |
733 | 85 | Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E)); |
734 | 85 | return MatchOperand_Success; |
735 | 85 | |
736 | 174 | case AsmToken:: Plus: |
737 | 174 | Parser.Lex(); // Eat the '+' |
738 | 174 | break; |
739 | 85 | case AsmToken::Minus: |
740 | 3 | break; |
741 | 177 | } |
742 | 177 | |
743 | 177 | std::unique_ptr<SparcOperand> Offset; |
744 | 177 | OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset); |
745 | 177 | if (ResTy != MatchOperand_Success || !Offset) |
746 | 0 | return MatchOperand_NoMatch; |
747 | 177 | |
748 | 177 | Operands.push_back( |
749 | 177 | Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))63 |
750 | 177 | : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset))114 ); |
751 | 177 | |
752 | 177 | return MatchOperand_Success; |
753 | 177 | } |
754 | | |
755 | 6 | OperandMatchResultTy SparcAsmParser::parseMembarTag(OperandVector &Operands) { |
756 | 6 | SMLoc S = Parser.getTok().getLoc(); |
757 | 6 | const MCExpr *EVal; |
758 | 6 | int64_t ImmVal = 0; |
759 | 6 | |
760 | 6 | std::unique_ptr<SparcOperand> Mask; |
761 | 6 | if (parseSparcAsmOperand(Mask) == MatchOperand_Success) { |
762 | 2 | if (!Mask->isImm() || !Mask->getImm()->evaluateAsAbsolute(ImmVal) || |
763 | 2 | ImmVal < 0 || ImmVal > 1271 ) { |
764 | 1 | Error(S, "invalid membar mask number"); |
765 | 1 | return MatchOperand_ParseFail; |
766 | 1 | } |
767 | 5 | } |
768 | 5 | |
769 | 15 | while (5 getLexer().getKind() == AsmToken::Hash) { |
770 | 11 | SMLoc TagStart = getLexer().getLoc(); |
771 | 11 | Parser.Lex(); // Eat the '#'. |
772 | 11 | unsigned MaskVal = StringSwitch<unsigned>(Parser.getTok().getString()) |
773 | 11 | .Case("LoadLoad", 0x1) |
774 | 11 | .Case("StoreLoad", 0x2) |
775 | 11 | .Case("LoadStore", 0x4) |
776 | 11 | .Case("StoreStore", 0x8) |
777 | 11 | .Case("Lookaside", 0x10) |
778 | 11 | .Case("MemIssue", 0x20) |
779 | 11 | .Case("Sync", 0x40) |
780 | 11 | .Default(0); |
781 | 11 | |
782 | 11 | Parser.Lex(); // Eat the identifier token. |
783 | 11 | |
784 | 11 | if (!MaskVal) { |
785 | 1 | Error(TagStart, "unknown membar tag"); |
786 | 1 | return MatchOperand_ParseFail; |
787 | 1 | } |
788 | 10 | |
789 | 10 | ImmVal |= MaskVal; |
790 | 10 | |
791 | 10 | if (getLexer().getKind() == AsmToken::Pipe) |
792 | 7 | Parser.Lex(); // Eat the '|'. |
793 | 10 | } |
794 | 5 | |
795 | 5 | EVal = MCConstantExpr::create(ImmVal, getContext()); |
796 | 4 | SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); |
797 | 4 | Operands.push_back(SparcOperand::CreateImm(EVal, S, E)); |
798 | 4 | return MatchOperand_Success; |
799 | 5 | } |
800 | | |
801 | | OperandMatchResultTy |
802 | 3.81k | SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { |
803 | 3.81k | |
804 | 3.81k | OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); |
805 | 3.81k | |
806 | 3.81k | // If there wasn't a custom match, try the generic matcher below. Otherwise, |
807 | 3.81k | // there was a match, but an error occurred, in which case, just return that |
808 | 3.81k | // the operand parsing failed. |
809 | 3.81k | if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail3.77k ) |
810 | 43 | return ResTy; |
811 | 3.77k | |
812 | 3.77k | if (getLexer().is(AsmToken::LBrac)) { |
813 | 237 | // Memory operand |
814 | 237 | Operands.push_back(SparcOperand::CreateToken("[", |
815 | 237 | Parser.getTok().getLoc())); |
816 | 237 | Parser.Lex(); // Eat the [ |
817 | 237 | |
818 | 237 | if (Mnemonic == "cas" || Mnemonic == "casx"236 || Mnemonic == "casa"235 ) { |
819 | 12 | SMLoc S = Parser.getTok().getLoc(); |
820 | 12 | if (getLexer().getKind() != AsmToken::Percent) |
821 | 0 | return MatchOperand_NoMatch; |
822 | 12 | Parser.Lex(); // eat % |
823 | 12 | |
824 | 12 | unsigned RegNo, RegKind; |
825 | 12 | if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) |
826 | 0 | return MatchOperand_NoMatch; |
827 | 12 | |
828 | 12 | Parser.Lex(); // Eat the identifier token. |
829 | 12 | SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1); |
830 | 12 | Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); |
831 | 12 | ResTy = MatchOperand_Success; |
832 | 225 | } else { |
833 | 225 | ResTy = parseMEMOperand(Operands); |
834 | 225 | } |
835 | 237 | |
836 | 237 | if (ResTy != MatchOperand_Success) |
837 | 0 | return ResTy; |
838 | 237 | |
839 | 237 | if (!getLexer().is(AsmToken::RBrac)) |
840 | 0 | return MatchOperand_ParseFail; |
841 | 237 | |
842 | 237 | Operands.push_back(SparcOperand::CreateToken("]", |
843 | 237 | Parser.getTok().getLoc())); |
844 | 237 | Parser.Lex(); // Eat the ] |
845 | 237 | |
846 | 237 | // Parse an optional address-space identifier after the address. |
847 | 237 | if (getLexer().is(AsmToken::Integer)) { |
848 | 58 | std::unique_ptr<SparcOperand> Op; |
849 | 58 | ResTy = parseSparcAsmOperand(Op, false); |
850 | 58 | if (ResTy != MatchOperand_Success || !Op) |
851 | 0 | return MatchOperand_ParseFail; |
852 | 58 | Operands.push_back(std::move(Op)); |
853 | 58 | } |
854 | 237 | return MatchOperand_Success; |
855 | 3.53k | } |
856 | 3.53k | |
857 | 3.53k | std::unique_ptr<SparcOperand> Op; |
858 | 3.53k | |
859 | 3.53k | ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call")); |
860 | 3.53k | if (ResTy != MatchOperand_Success || !Op3.53k ) |
861 | 1 | return MatchOperand_ParseFail; |
862 | 3.53k | |
863 | 3.53k | // Push the parsed operand into the list of operands |
864 | 3.53k | Operands.push_back(std::move(Op)); |
865 | 3.53k | |
866 | 3.53k | return MatchOperand_Success; |
867 | 3.53k | } |
868 | | |
869 | | OperandMatchResultTy |
870 | | SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op, |
871 | 3.78k | bool isCall) { |
872 | 3.78k | SMLoc S = Parser.getTok().getLoc(); |
873 | 3.78k | SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); |
874 | 3.78k | const MCExpr *EVal; |
875 | 3.78k | |
876 | 3.78k | Op = nullptr; |
877 | 3.78k | switch (getLexer().getKind()) { |
878 | 3.78k | default: break5 ; |
879 | 3.78k | |
880 | 3.78k | case AsmToken::Percent: |
881 | 2.83k | Parser.Lex(); // Eat the '%'. |
882 | 2.83k | unsigned RegNo; |
883 | 2.83k | unsigned RegKind; |
884 | 2.83k | if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { |
885 | 2.69k | StringRef name = Parser.getTok().getString(); |
886 | 2.69k | Parser.Lex(); // Eat the identifier token. |
887 | 2.69k | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); |
888 | 2.69k | switch (RegNo) { |
889 | 2.69k | default: |
890 | 2.25k | Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); |
891 | 2.25k | break; |
892 | 2.69k | case Sparc::PSR: |
893 | 27 | Op = SparcOperand::CreateToken("%psr", S); |
894 | 27 | break; |
895 | 2.69k | case Sparc::FSR: |
896 | 16 | Op = SparcOperand::CreateToken("%fsr", S); |
897 | 16 | break; |
898 | 2.69k | case Sparc::FQ: |
899 | 5 | Op = SparcOperand::CreateToken("%fq", S); |
900 | 5 | break; |
901 | 2.69k | case Sparc::CPSR: |
902 | 6 | Op = SparcOperand::CreateToken("%csr", S); |
903 | 6 | break; |
904 | 2.69k | case Sparc::CPQ: |
905 | 3 | Op = SparcOperand::CreateToken("%cq", S); |
906 | 3 | break; |
907 | 2.69k | case Sparc::WIM: |
908 | 24 | Op = SparcOperand::CreateToken("%wim", S); |
909 | 24 | break; |
910 | 2.69k | case Sparc::TBR: |
911 | 24 | Op = SparcOperand::CreateToken("%tbr", S); |
912 | 24 | break; |
913 | 2.69k | case Sparc::ICC: |
914 | 336 | if (name == "xcc") |
915 | 175 | Op = SparcOperand::CreateToken("%xcc", S); |
916 | 161 | else |
917 | 161 | Op = SparcOperand::CreateToken("%icc", S); |
918 | 336 | break; |
919 | 2.69k | } |
920 | 2.69k | break; |
921 | 2.69k | } |
922 | 144 | if (matchSparcAsmModifiers(EVal, E)) { |
923 | 144 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); |
924 | 144 | Op = SparcOperand::CreateImm(EVal, S, E); |
925 | 144 | } |
926 | 144 | break; |
927 | 144 | |
928 | 428 | case AsmToken::Minus: |
929 | 428 | case AsmToken::Integer: |
930 | 428 | case AsmToken::LParen: |
931 | 428 | case AsmToken::Dot: |
932 | 428 | if (!getParser().parseExpression(EVal, E)) |
933 | 428 | Op = SparcOperand::CreateImm(EVal, S, E); |
934 | 428 | break; |
935 | 428 | |
936 | 511 | case AsmToken::Identifier: { |
937 | 511 | StringRef Identifier; |
938 | 511 | if (!getParser().parseIdentifier(Identifier)) { |
939 | 511 | E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); |
940 | 511 | MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); |
941 | 511 | |
942 | 511 | const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, |
943 | 511 | getContext()); |
944 | 511 | SparcMCExpr::VariantKind Kind = SparcMCExpr::VK_Sparc_13; |
945 | 511 | |
946 | 511 | if (getContext().getObjectFileInfo()->isPositionIndependent()) { |
947 | 6 | if (isCall) |
948 | 3 | Kind = SparcMCExpr::VK_Sparc_WPLT30; |
949 | 3 | else |
950 | 3 | Kind = SparcMCExpr::VK_Sparc_GOT13; |
951 | 6 | } |
952 | 511 | |
953 | 511 | Res = SparcMCExpr::create(Kind, Res, getContext()); |
954 | 511 | |
955 | 511 | Op = SparcOperand::CreateImm(Res, S, E); |
956 | 511 | } |
957 | 511 | break; |
958 | 3.78k | } |
959 | 3.78k | } |
960 | 3.78k | return (Op) ? MatchOperand_Success3.77k : MatchOperand_ParseFail5 ; |
961 | 3.78k | } |
962 | | |
963 | | OperandMatchResultTy |
964 | 329 | SparcAsmParser::parseBranchModifiers(OperandVector &Operands) { |
965 | 329 | // parse (,a|,pn|,pt)+ |
966 | 329 | |
967 | 739 | while (getLexer().is(AsmToken::Comma)) { |
968 | 410 | Parser.Lex(); // Eat the comma |
969 | 410 | |
970 | 410 | if (!getLexer().is(AsmToken::Identifier)) |
971 | 0 | return MatchOperand_ParseFail; |
972 | 410 | StringRef modName = Parser.getTok().getString(); |
973 | 410 | if (modName == "a" || modName == "pn"169 || modName == "pt"81 ) { |
974 | 410 | Operands.push_back(SparcOperand::CreateToken(modName, |
975 | 410 | Parser.getTok().getLoc())); |
976 | 410 | Parser.Lex(); // eat the identifier. |
977 | 410 | } |
978 | 410 | } |
979 | 329 | return MatchOperand_Success; |
980 | 329 | } |
981 | | |
982 | | bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo, |
983 | 3.11k | unsigned &RegKind) { |
984 | 3.11k | int64_t intVal = 0; |
985 | 3.11k | RegNo = 0; |
986 | 3.11k | RegKind = SparcOperand::rk_None; |
987 | 3.11k | if (Tok.is(AsmToken::Identifier)) { |
988 | 3.11k | StringRef name = Tok.getString(); |
989 | 3.11k | |
990 | 3.11k | // %fp |
991 | 3.11k | if (name.equals("fp")) { |
992 | 2 | RegNo = Sparc::I6; |
993 | 2 | RegKind = SparcOperand::rk_IntReg; |
994 | 2 | return true; |
995 | 2 | } |
996 | 3.11k | // %sp |
997 | 3.11k | if (name.equals("sp")) { |
998 | 8 | RegNo = Sparc::O6; |
999 | 8 | RegKind = SparcOperand::rk_IntReg; |
1000 | 8 | return true; |
1001 | 8 | } |
1002 | 3.10k | |
1003 | 3.10k | if (name.equals("y")) { |
1004 | 24 | RegNo = Sparc::Y; |
1005 | 24 | RegKind = SparcOperand::rk_Special; |
1006 | 24 | return true; |
1007 | 24 | } |
1008 | 3.07k | |
1009 | 3.07k | if (name.substr(0, 3).equals_lower("asr") |
1010 | 3.07k | && !name.substr(3).getAsInteger(10, intVal)26 |
1011 | 3.07k | && intVal > 026 && intVal < 3226 ) { |
1012 | 26 | RegNo = ASRRegs[intVal]; |
1013 | 26 | RegKind = SparcOperand::rk_Special; |
1014 | 26 | return true; |
1015 | 26 | } |
1016 | 3.05k | |
1017 | 3.05k | // %fprs is an alias of %asr6. |
1018 | 3.05k | if (name.equals("fprs")) { |
1019 | 4 | RegNo = ASRRegs[6]; |
1020 | 4 | RegKind = SparcOperand::rk_Special; |
1021 | 4 | return true; |
1022 | 4 | } |
1023 | 3.04k | |
1024 | 3.04k | if (name.equals("icc")) { |
1025 | 161 | RegNo = Sparc::ICC; |
1026 | 161 | RegKind = SparcOperand::rk_Special; |
1027 | 161 | return true; |
1028 | 161 | } |
1029 | 2.88k | |
1030 | 2.88k | if (name.equals("psr")) { |
1031 | 27 | RegNo = Sparc::PSR; |
1032 | 27 | RegKind = SparcOperand::rk_Special; |
1033 | 27 | return true; |
1034 | 27 | } |
1035 | 2.86k | |
1036 | 2.86k | if (name.equals("fsr")) { |
1037 | 16 | RegNo = Sparc::FSR; |
1038 | 16 | RegKind = SparcOperand::rk_Special; |
1039 | 16 | return true; |
1040 | 16 | } |
1041 | 2.84k | |
1042 | 2.84k | if (name.equals("fq")) { |
1043 | 5 | RegNo = Sparc::FQ; |
1044 | 5 | RegKind = SparcOperand::rk_Special; |
1045 | 5 | return true; |
1046 | 5 | } |
1047 | 2.83k | |
1048 | 2.83k | if (name.equals("csr")) { |
1049 | 6 | RegNo = Sparc::CPSR; |
1050 | 6 | RegKind = SparcOperand::rk_Special; |
1051 | 6 | return true; |
1052 | 6 | } |
1053 | 2.83k | |
1054 | 2.83k | if (name.equals("cq")) { |
1055 | 3 | RegNo = Sparc::CPQ; |
1056 | 3 | RegKind = SparcOperand::rk_Special; |
1057 | 3 | return true; |
1058 | 3 | } |
1059 | 2.83k | |
1060 | 2.83k | if (name.equals("wim")) { |
1061 | 24 | RegNo = Sparc::WIM; |
1062 | 24 | RegKind = SparcOperand::rk_Special; |
1063 | 24 | return true; |
1064 | 24 | } |
1065 | 2.80k | |
1066 | 2.80k | if (name.equals("tbr")) { |
1067 | 24 | RegNo = Sparc::TBR; |
1068 | 24 | RegKind = SparcOperand::rk_Special; |
1069 | 24 | return true; |
1070 | 24 | } |
1071 | 2.78k | |
1072 | 2.78k | if (name.equals("xcc")) { |
1073 | 175 | // FIXME:: check 64bit. |
1074 | 175 | RegNo = Sparc::ICC; |
1075 | 175 | RegKind = SparcOperand::rk_Special; |
1076 | 175 | return true; |
1077 | 175 | } |
1078 | 2.60k | |
1079 | 2.60k | // %fcc0 - %fcc3 |
1080 | 2.60k | if (name.substr(0, 3).equals_lower("fcc") |
1081 | 2.60k | && !name.substr(3).getAsInteger(10, intVal)130 |
1082 | 2.60k | && intVal < 4130 ) { |
1083 | 130 | // FIXME: check 64bit and handle %fcc1 - %fcc3 |
1084 | 130 | RegNo = Sparc::FCC0 + intVal; |
1085 | 130 | RegKind = SparcOperand::rk_Special; |
1086 | 130 | return true; |
1087 | 130 | } |
1088 | 2.47k | |
1089 | 2.47k | // %g0 - %g7 |
1090 | 2.47k | if (name.substr(0, 1).equals_lower("g") |
1091 | 2.47k | && !name.substr(1).getAsInteger(10, intVal)813 |
1092 | 2.47k | && intVal < 8813 ) { |
1093 | 813 | RegNo = IntRegs[intVal]; |
1094 | 813 | RegKind = SparcOperand::rk_IntReg; |
1095 | 813 | return true; |
1096 | 813 | } |
1097 | 1.66k | // %o0 - %o7 |
1098 | 1.66k | if (name.substr(0, 1).equals_lower("o") |
1099 | 1.66k | && !name.substr(1).getAsInteger(10, intVal)283 |
1100 | 1.66k | && intVal < 8277 ) { |
1101 | 277 | RegNo = IntRegs[8 + intVal]; |
1102 | 277 | RegKind = SparcOperand::rk_IntReg; |
1103 | 277 | return true; |
1104 | 277 | } |
1105 | 1.38k | if (name.substr(0, 1).equals_lower("l") |
1106 | 1.38k | && !name.substr(1).getAsInteger(10, intVal)136 |
1107 | 1.38k | && intVal < 8120 ) { |
1108 | 118 | RegNo = IntRegs[16 + intVal]; |
1109 | 118 | RegKind = SparcOperand::rk_IntReg; |
1110 | 118 | return true; |
1111 | 118 | } |
1112 | 1.26k | if (name.substr(0, 1).equals_lower("i") |
1113 | 1.26k | && !name.substr(1).getAsInteger(10, intVal)712 |
1114 | 1.26k | && intVal < 8712 ) { |
1115 | 712 | RegNo = IntRegs[24 + intVal]; |
1116 | 712 | RegKind = SparcOperand::rk_IntReg; |
1117 | 712 | return true; |
1118 | 712 | } |
1119 | 557 | // %f0 - %f31 |
1120 | 557 | if (name.substr(0, 1).equals_lower("f") |
1121 | 557 | && !name.substr(1, 2).getAsInteger(10, intVal)299 && intVal < 32299 ) { |
1122 | 275 | RegNo = FloatRegs[intVal]; |
1123 | 275 | RegKind = SparcOperand::rk_FloatReg; |
1124 | 275 | return true; |
1125 | 275 | } |
1126 | 282 | // %f32 - %f62 |
1127 | 282 | if (name.substr(0, 1).equals_lower("f") |
1128 | 282 | && !name.substr(1, 2).getAsInteger(10, intVal)24 |
1129 | 282 | && intVal >= 3224 && intVal <= 6224 && (intVal % 2 == 0)24 ) { |
1130 | 24 | // FIXME: Check V9 |
1131 | 24 | RegNo = DoubleRegs[intVal/2]; |
1132 | 24 | RegKind = SparcOperand::rk_DoubleReg; |
1133 | 24 | return true; |
1134 | 24 | } |
1135 | 258 | |
1136 | 258 | // %r0 - %r31 |
1137 | 258 | if (name.substr(0, 1).equals_lower("r") |
1138 | 258 | && !name.substr(1, 2).getAsInteger(10, intVal)4 && intVal < 314 ) { |
1139 | 4 | RegNo = IntRegs[intVal]; |
1140 | 4 | RegKind = SparcOperand::rk_IntReg; |
1141 | 4 | return true; |
1142 | 4 | } |
1143 | 254 | |
1144 | 254 | // %c0 - %c31 |
1145 | 254 | if (name.substr(0, 1).equals_lower("c") |
1146 | 254 | && !name.substr(1).getAsInteger(10, intVal)44 |
1147 | 254 | && intVal < 3220 ) { |
1148 | 20 | RegNo = CoprocRegs[intVal]; |
1149 | 20 | RegKind = SparcOperand::rk_CoprocReg; |
1150 | 20 | return true; |
1151 | 20 | } |
1152 | 234 | |
1153 | 234 | if (name.equals("tpc")) { |
1154 | 6 | RegNo = Sparc::TPC; |
1155 | 6 | RegKind = SparcOperand::rk_Special; |
1156 | 6 | return true; |
1157 | 6 | } |
1158 | 228 | if (name.equals("tnpc")) { |
1159 | 6 | RegNo = Sparc::TNPC; |
1160 | 6 | RegKind = SparcOperand::rk_Special; |
1161 | 6 | return true; |
1162 | 6 | } |
1163 | 222 | if (name.equals("tstate")) { |
1164 | 6 | RegNo = Sparc::TSTATE; |
1165 | 6 | RegKind = SparcOperand::rk_Special; |
1166 | 6 | return true; |
1167 | 6 | } |
1168 | 216 | if (name.equals("tt")) { |
1169 | 6 | RegNo = Sparc::TT; |
1170 | 6 | RegKind = SparcOperand::rk_Special; |
1171 | 6 | return true; |
1172 | 6 | } |
1173 | 210 | if (name.equals("tick")) { |
1174 | 6 | RegNo = Sparc::TICK; |
1175 | 6 | RegKind = SparcOperand::rk_Special; |
1176 | 6 | return true; |
1177 | 6 | } |
1178 | 204 | if (name.equals("tba")) { |
1179 | 6 | RegNo = Sparc::TBA; |
1180 | 6 | RegKind = SparcOperand::rk_Special; |
1181 | 6 | return true; |
1182 | 6 | } |
1183 | 198 | if (name.equals("pstate")) { |
1184 | 6 | RegNo = Sparc::PSTATE; |
1185 | 6 | RegKind = SparcOperand::rk_Special; |
1186 | 6 | return true; |
1187 | 6 | } |
1188 | 192 | if (name.equals("tl")) { |
1189 | 6 | RegNo = Sparc::TL; |
1190 | 6 | RegKind = SparcOperand::rk_Special; |
1191 | 6 | return true; |
1192 | 6 | } |
1193 | 186 | if (name.equals("pil")) { |
1194 | 6 | RegNo = Sparc::PIL; |
1195 | 6 | RegKind = SparcOperand::rk_Special; |
1196 | 6 | return true; |
1197 | 6 | } |
1198 | 180 | if (name.equals("cwp")) { |
1199 | 6 | RegNo = Sparc::CWP; |
1200 | 6 | RegKind = SparcOperand::rk_Special; |
1201 | 6 | return true; |
1202 | 6 | } |
1203 | 174 | if (name.equals("cansave")) { |
1204 | 6 | RegNo = Sparc::CANSAVE; |
1205 | 6 | RegKind = SparcOperand::rk_Special; |
1206 | 6 | return true; |
1207 | 6 | } |
1208 | 168 | if (name.equals("canrestore")) { |
1209 | 6 | RegNo = Sparc::CANRESTORE; |
1210 | 6 | RegKind = SparcOperand::rk_Special; |
1211 | 6 | return true; |
1212 | 6 | } |
1213 | 162 | if (name.equals("cleanwin")) { |
1214 | 6 | RegNo = Sparc::CLEANWIN; |
1215 | 6 | RegKind = SparcOperand::rk_Special; |
1216 | 6 | return true; |
1217 | 6 | } |
1218 | 156 | if (name.equals("otherwin")) { |
1219 | 6 | RegNo = Sparc::OTHERWIN; |
1220 | 6 | RegKind = SparcOperand::rk_Special; |
1221 | 6 | return true; |
1222 | 6 | } |
1223 | 150 | if (name.equals("wstate")) { |
1224 | 6 | RegNo = Sparc::WSTATE; |
1225 | 6 | RegKind = SparcOperand::rk_Special; |
1226 | 6 | return true; |
1227 | 6 | } |
1228 | 144 | } |
1229 | 144 | return false; |
1230 | 144 | } |
1231 | | |
1232 | | // Determine if an expression contains a reference to the symbol |
1233 | | // "_GLOBAL_OFFSET_TABLE_". |
1234 | 20 | static bool hasGOTReference(const MCExpr *Expr) { |
1235 | 20 | switch (Expr->getKind()) { |
1236 | 20 | case MCExpr::Target: |
1237 | 4 | if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr)) |
1238 | 4 | return hasGOTReference(SE->getSubExpr()); |
1239 | 0 | break; |
1240 | 0 |
|
1241 | 0 | case MCExpr::Constant: |
1242 | 0 | break; |
1243 | 0 |
|
1244 | 4 | case MCExpr::Binary: { |
1245 | 4 | const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr); |
1246 | 4 | return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS())0 ; |
1247 | 0 | } |
1248 | 0 |
|
1249 | 12 | case MCExpr::SymbolRef: { |
1250 | 12 | const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr); |
1251 | 12 | return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_"); |
1252 | 0 | } |
1253 | 0 |
|
1254 | 0 | case MCExpr::Unary: |
1255 | 0 | return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr()); |
1256 | 0 | } |
1257 | 0 | return false; |
1258 | 0 | } |
1259 | | |
1260 | | const SparcMCExpr * |
1261 | | SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK, |
1262 | 206 | const MCExpr *subExpr) { |
1263 | 206 | // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently. |
1264 | 206 | // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is |
1265 | 206 | // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted |
1266 | 206 | // as %got10 or %got22 relocation. |
1267 | 206 | |
1268 | 206 | if (getContext().getObjectFileInfo()->isPositionIndependent()) { |
1269 | 12 | switch(VK) { |
1270 | 12 | default: break0 ; |
1271 | 12 | case SparcMCExpr::VK_Sparc_LO: |
1272 | 6 | VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC103 |
1273 | 6 | : SparcMCExpr::VK_Sparc_GOT103 ); |
1274 | 6 | break; |
1275 | 12 | case SparcMCExpr::VK_Sparc_HI: |
1276 | 6 | VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC223 |
1277 | 6 | : SparcMCExpr::VK_Sparc_GOT223 ); |
1278 | 6 | break; |
1279 | 206 | } |
1280 | 206 | } |
1281 | 206 | |
1282 | 206 | return SparcMCExpr::create(VK, subExpr, getContext()); |
1283 | 206 | } |
1284 | | |
1285 | | bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal, |
1286 | 144 | SMLoc &EndLoc) { |
1287 | 144 | AsmToken Tok = Parser.getTok(); |
1288 | 144 | if (!Tok.is(AsmToken::Identifier)) |
1289 | 0 | return false; |
1290 | 144 | |
1291 | 144 | StringRef name = Tok.getString(); |
1292 | 144 | |
1293 | 144 | SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name); |
1294 | 144 | |
1295 | 144 | if (VK == SparcMCExpr::VK_Sparc_None) |
1296 | 0 | return false; |
1297 | 144 | |
1298 | 144 | Parser.Lex(); // Eat the identifier. |
1299 | 144 | if (Parser.getTok().getKind() != AsmToken::LParen) |
1300 | 0 | return false; |
1301 | 144 | |
1302 | 144 | Parser.Lex(); // Eat the LParen token. |
1303 | 144 | const MCExpr *subExpr; |
1304 | 144 | if (Parser.parseParenExpression(subExpr, EndLoc)) |
1305 | 0 | return false; |
1306 | 144 | |
1307 | 144 | EVal = adjustPICRelocation(VK, subExpr); |
1308 | 144 | return true; |
1309 | 144 | } |
1310 | | |
1311 | 91.7k | extern "C" void LLVMInitializeSparcAsmParser() { |
1312 | 91.7k | RegisterMCAsmParser<SparcAsmParser> A(getTheSparcTarget()); |
1313 | 91.7k | RegisterMCAsmParser<SparcAsmParser> B(getTheSparcV9Target()); |
1314 | 91.7k | RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget()); |
1315 | 91.7k | } |
1316 | | |
1317 | | #define GET_REGISTER_MATCHER |
1318 | | #define GET_MATCHER_IMPLEMENTATION |
1319 | | #include "SparcGenAsmMatcher.inc" |
1320 | | |
1321 | | unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp, |
1322 | 4.81k | unsigned Kind) { |
1323 | 4.81k | SparcOperand &Op = (SparcOperand &)GOp; |
1324 | 4.81k | if (Op.isFloatOrDoubleReg()) { |
1325 | 149 | switch (Kind) { |
1326 | 149 | default: break25 ; |
1327 | 149 | case MCK_DFPRegs: |
1328 | 66 | if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op)) |
1329 | 66 | return MCTargetAsmParser::Match_Success; |
1330 | 0 | break; |
1331 | 58 | case MCK_QFPRegs: |
1332 | 58 | if (SparcOperand::MorphToQuadReg(Op)) |
1333 | 58 | return MCTargetAsmParser::Match_Success; |
1334 | 0 | break; |
1335 | 149 | } |
1336 | 149 | } |
1337 | 4.69k | if (Op.isIntReg() && Kind == MCK_IntPair690 ) { |
1338 | 21 | if (SparcOperand::MorphToIntPairReg(Op)) |
1339 | 21 | return MCTargetAsmParser::Match_Success; |
1340 | 4.67k | } |
1341 | 4.67k | if (Op.isCoprocReg() && Kind == MCK_CoprocPair60 ) { |
1342 | 10 | if (SparcOperand::MorphToCoprocPairReg(Op)) |
1343 | 10 | return MCTargetAsmParser::Match_Success; |
1344 | 4.66k | } |
1345 | 4.66k | return Match_InvalidOperand; |
1346 | 4.66k | } |