/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZISelLowering.h
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1 | | //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file defines the interfaces that SystemZ uses to lower LLVM code into a |
10 | | // selection DAG. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H |
15 | | #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H |
16 | | |
17 | | #include "SystemZ.h" |
18 | | #include "SystemZInstrInfo.h" |
19 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
20 | | #include "llvm/CodeGen/SelectionDAG.h" |
21 | | #include "llvm/CodeGen/TargetLowering.h" |
22 | | |
23 | | namespace llvm { |
24 | | namespace SystemZISD { |
25 | | enum NodeType : unsigned { |
26 | | FIRST_NUMBER = ISD::BUILTIN_OP_END, |
27 | | |
28 | | // Return with a flag operand. Operand 0 is the chain operand. |
29 | | RET_FLAG, |
30 | | |
31 | | // Calls a function. Operand 0 is the chain operand and operand 1 |
32 | | // is the target address. The arguments start at operand 2. |
33 | | // There is an optional glue operand at the end. |
34 | | CALL, |
35 | | SIBCALL, |
36 | | |
37 | | // TLS calls. Like regular calls, except operand 1 is the TLS symbol. |
38 | | // (The call target is implicitly __tls_get_offset.) |
39 | | TLS_GDCALL, |
40 | | TLS_LDCALL, |
41 | | |
42 | | // Wraps a TargetGlobalAddress that should be loaded using PC-relative |
43 | | // accesses (LARL). Operand 0 is the address. |
44 | | PCREL_WRAPPER, |
45 | | |
46 | | // Used in cases where an offset is applied to a TargetGlobalAddress. |
47 | | // Operand 0 is the full TargetGlobalAddress and operand 1 is a |
48 | | // PCREL_WRAPPER for an anchor point. This is used so that we can |
49 | | // cheaply refer to either the full address or the anchor point |
50 | | // as a register base. |
51 | | PCREL_OFFSET, |
52 | | |
53 | | // Integer absolute. |
54 | | IABS, |
55 | | |
56 | | // Integer comparisons. There are three operands: the two values |
57 | | // to compare, and an integer of type SystemZICMP. |
58 | | ICMP, |
59 | | |
60 | | // Floating-point comparisons. The two operands are the values to compare. |
61 | | FCMP, |
62 | | |
63 | | // Test under mask. The first operand is ANDed with the second operand |
64 | | // and the condition codes are set on the result. The third operand is |
65 | | // a boolean that is true if the condition codes need to distinguish |
66 | | // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the |
67 | | // register forms do but the memory forms don't). |
68 | | TM, |
69 | | |
70 | | // Branches if a condition is true. Operand 0 is the chain operand; |
71 | | // operand 1 is the 4-bit condition-code mask, with bit N in |
72 | | // big-endian order meaning "branch if CC=N"; operand 2 is the |
73 | | // target block and operand 3 is the flag operand. |
74 | | BR_CCMASK, |
75 | | |
76 | | // Selects between operand 0 and operand 1. Operand 2 is the |
77 | | // mask of condition-code values for which operand 0 should be |
78 | | // chosen over operand 1; it has the same form as BR_CCMASK. |
79 | | // Operand 3 is the flag operand. |
80 | | SELECT_CCMASK, |
81 | | |
82 | | // Evaluates to the gap between the stack pointer and the |
83 | | // base of the dynamically-allocatable area. |
84 | | ADJDYNALLOC, |
85 | | |
86 | | // Count number of bits set in operand 0 per byte. |
87 | | POPCNT, |
88 | | |
89 | | // Wrappers around the ISD opcodes of the same name. The output is GR128. |
90 | | // Input operands may be GR64 or GR32, depending on the instruction. |
91 | | SMUL_LOHI, |
92 | | UMUL_LOHI, |
93 | | SDIVREM, |
94 | | UDIVREM, |
95 | | |
96 | | // Add/subtract with overflow/carry. These have the same operands as |
97 | | // the corresponding standard operations, except with the carry flag |
98 | | // replaced by a condition code value. |
99 | | SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, |
100 | | |
101 | | // Set the condition code from a boolean value in operand 0. |
102 | | // Operand 1 is a mask of all condition-code values that may result of this |
103 | | // operation, operand 2 is a mask of condition-code values that may result |
104 | | // if the boolean is true. |
105 | | // Note that this operation is always optimized away, we will never |
106 | | // generate any code for it. |
107 | | GET_CCMASK, |
108 | | |
109 | | // Use a series of MVCs to copy bytes from one memory location to another. |
110 | | // The operands are: |
111 | | // - the target address |
112 | | // - the source address |
113 | | // - the constant length |
114 | | // |
115 | | // This isn't a memory opcode because we'd need to attach two |
116 | | // MachineMemOperands rather than one. |
117 | | MVC, |
118 | | |
119 | | // Like MVC, but implemented as a loop that handles X*256 bytes |
120 | | // followed by straight-line code to handle the rest (if any). |
121 | | // The value of X is passed as an additional operand. |
122 | | MVC_LOOP, |
123 | | |
124 | | // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). |
125 | | NC, |
126 | | NC_LOOP, |
127 | | OC, |
128 | | OC_LOOP, |
129 | | XC, |
130 | | XC_LOOP, |
131 | | |
132 | | // Use CLC to compare two blocks of memory, with the same comments |
133 | | // as for MVC and MVC_LOOP. |
134 | | CLC, |
135 | | CLC_LOOP, |
136 | | |
137 | | // Use an MVST-based sequence to implement stpcpy(). |
138 | | STPCPY, |
139 | | |
140 | | // Use a CLST-based sequence to implement strcmp(). The two input operands |
141 | | // are the addresses of the strings to compare. |
142 | | STRCMP, |
143 | | |
144 | | // Use an SRST-based sequence to search a block of memory. The first |
145 | | // operand is the end address, the second is the start, and the third |
146 | | // is the character to search for. CC is set to 1 on success and 2 |
147 | | // on failure. |
148 | | SEARCH_STRING, |
149 | | |
150 | | // Store the CC value in bits 29 and 28 of an integer. |
151 | | IPM, |
152 | | |
153 | | // Compiler barrier only; generate a no-op. |
154 | | MEMBARRIER, |
155 | | |
156 | | // Transaction begin. The first operand is the chain, the second |
157 | | // the TDB pointer, and the third the immediate control field. |
158 | | // Returns CC value and chain. |
159 | | TBEGIN, |
160 | | TBEGIN_NOFLOAT, |
161 | | |
162 | | // Transaction end. Just the chain operand. Returns CC value and chain. |
163 | | TEND, |
164 | | |
165 | | // Create a vector constant by filling byte N of the result with bit |
166 | | // 15-N of the single operand. |
167 | | BYTE_MASK, |
168 | | |
169 | | // Create a vector constant by replicating an element-sized RISBG-style mask. |
170 | | // The first operand specifies the starting set bit and the second operand |
171 | | // specifies the ending set bit. Both operands count from the MSB of the |
172 | | // element. |
173 | | ROTATE_MASK, |
174 | | |
175 | | // Replicate a GPR scalar value into all elements of a vector. |
176 | | REPLICATE, |
177 | | |
178 | | // Create a vector from two i64 GPRs. |
179 | | JOIN_DWORDS, |
180 | | |
181 | | // Replicate one element of a vector into all elements. The first operand |
182 | | // is the vector and the second is the index of the element to replicate. |
183 | | SPLAT, |
184 | | |
185 | | // Interleave elements from the high half of operand 0 and the high half |
186 | | // of operand 1. |
187 | | MERGE_HIGH, |
188 | | |
189 | | // Likewise for the low halves. |
190 | | MERGE_LOW, |
191 | | |
192 | | // Concatenate the vectors in the first two operands, shift them left |
193 | | // by the third operand, and take the first half of the result. |
194 | | SHL_DOUBLE, |
195 | | |
196 | | // Take one element of the first v2i64 operand and the one element of |
197 | | // the second v2i64 operand and concatenate them to form a v2i64 result. |
198 | | // The third operand is a 4-bit value of the form 0A0B, where A and B |
199 | | // are the element selectors for the first operand and second operands |
200 | | // respectively. |
201 | | PERMUTE_DWORDS, |
202 | | |
203 | | // Perform a general vector permute on vector operands 0 and 1. |
204 | | // Each byte of operand 2 controls the corresponding byte of the result, |
205 | | // in the same way as a byte-level VECTOR_SHUFFLE mask. |
206 | | PERMUTE, |
207 | | |
208 | | // Pack vector operands 0 and 1 into a single vector with half-sized elements. |
209 | | PACK, |
210 | | |
211 | | // Likewise, but saturate the result and set CC. PACKS_CC does signed |
212 | | // saturation and PACKLS_CC does unsigned saturation. |
213 | | PACKS_CC, |
214 | | PACKLS_CC, |
215 | | |
216 | | // Unpack the first half of vector operand 0 into double-sized elements. |
217 | | // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. |
218 | | UNPACK_HIGH, |
219 | | UNPACKL_HIGH, |
220 | | |
221 | | // Likewise for the second half. |
222 | | UNPACK_LOW, |
223 | | UNPACKL_LOW, |
224 | | |
225 | | // Shift each element of vector operand 0 by the number of bits specified |
226 | | // by scalar operand 1. |
227 | | VSHL_BY_SCALAR, |
228 | | VSRL_BY_SCALAR, |
229 | | VSRA_BY_SCALAR, |
230 | | |
231 | | // For each element of the output type, sum across all sub-elements of |
232 | | // operand 0 belonging to the corresponding element, and add in the |
233 | | // rightmost sub-element of the corresponding element of operand 1. |
234 | | VSUM, |
235 | | |
236 | | // Compare integer vector operands 0 and 1 to produce the usual 0/-1 |
237 | | // vector result. VICMPE is for equality, VICMPH for "signed greater than" |
238 | | // and VICMPHL for "unsigned greater than". |
239 | | VICMPE, |
240 | | VICMPH, |
241 | | VICMPHL, |
242 | | |
243 | | // Likewise, but also set the condition codes on the result. |
244 | | VICMPES, |
245 | | VICMPHS, |
246 | | VICMPHLS, |
247 | | |
248 | | // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1 |
249 | | // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and |
250 | | // greater than" and VFCMPHE for "ordered and greater than or equal to". |
251 | | VFCMPE, |
252 | | VFCMPH, |
253 | | VFCMPHE, |
254 | | |
255 | | // Likewise, but also set the condition codes on the result. |
256 | | VFCMPES, |
257 | | VFCMPHS, |
258 | | VFCMPHES, |
259 | | |
260 | | // Test floating-point data class for vectors. |
261 | | VFTCI, |
262 | | |
263 | | // Extend the even f32 elements of vector operand 0 to produce a vector |
264 | | // of f64 elements. |
265 | | VEXTEND, |
266 | | |
267 | | // Round the f64 elements of vector operand 0 to f32s and store them in the |
268 | | // even elements of the result. |
269 | | VROUND, |
270 | | |
271 | | // AND the two vector operands together and set CC based on the result. |
272 | | VTM, |
273 | | |
274 | | // String operations that set CC as a side-effect. |
275 | | VFAE_CC, |
276 | | VFAEZ_CC, |
277 | | VFEE_CC, |
278 | | VFEEZ_CC, |
279 | | VFENE_CC, |
280 | | VFENEZ_CC, |
281 | | VISTR_CC, |
282 | | VSTRC_CC, |
283 | | VSTRCZ_CC, |
284 | | VSTRS_CC, |
285 | | VSTRSZ_CC, |
286 | | |
287 | | // Test Data Class. |
288 | | // |
289 | | // Operand 0: the value to test |
290 | | // Operand 1: the bit mask |
291 | | TDC, |
292 | | |
293 | | // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or |
294 | | // ATOMIC_LOAD_<op>. |
295 | | // |
296 | | // Operand 0: the address of the containing 32-bit-aligned field |
297 | | // Operand 1: the second operand of <op>, in the high bits of an i32 |
298 | | // for everything except ATOMIC_SWAPW |
299 | | // Operand 2: how many bits to rotate the i32 left to bring the first |
300 | | // operand into the high bits |
301 | | // Operand 3: the negative of operand 2, for rotating the other way |
302 | | // Operand 4: the width of the field in bits (8 or 16) |
303 | | ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, |
304 | | ATOMIC_LOADW_ADD, |
305 | | ATOMIC_LOADW_SUB, |
306 | | ATOMIC_LOADW_AND, |
307 | | ATOMIC_LOADW_OR, |
308 | | ATOMIC_LOADW_XOR, |
309 | | ATOMIC_LOADW_NAND, |
310 | | ATOMIC_LOADW_MIN, |
311 | | ATOMIC_LOADW_MAX, |
312 | | ATOMIC_LOADW_UMIN, |
313 | | ATOMIC_LOADW_UMAX, |
314 | | |
315 | | // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. |
316 | | // |
317 | | // Operand 0: the address of the containing 32-bit-aligned field |
318 | | // Operand 1: the compare value, in the low bits of an i32 |
319 | | // Operand 2: the swap value, in the low bits of an i32 |
320 | | // Operand 3: how many bits to rotate the i32 left to bring the first |
321 | | // operand into the high bits |
322 | | // Operand 4: the negative of operand 2, for rotating the other way |
323 | | // Operand 5: the width of the field in bits (8 or 16) |
324 | | ATOMIC_CMP_SWAPW, |
325 | | |
326 | | // Atomic compare-and-swap returning CC value. |
327 | | // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) |
328 | | ATOMIC_CMP_SWAP, |
329 | | |
330 | | // 128-bit atomic load. |
331 | | // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) |
332 | | ATOMIC_LOAD_128, |
333 | | |
334 | | // 128-bit atomic store. |
335 | | // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) |
336 | | ATOMIC_STORE_128, |
337 | | |
338 | | // 128-bit atomic compare-and-swap. |
339 | | // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) |
340 | | ATOMIC_CMP_SWAP_128, |
341 | | |
342 | | // Byte swapping load/store. Same operands as regular load/store. |
343 | | LRV, STRV, |
344 | | |
345 | | // Element swapping load/store. Same operands as regular load/store. |
346 | | VLER, VSTER, |
347 | | |
348 | | // Prefetch from the second operand using the 4-bit control code in |
349 | | // the first operand. The code is 1 for a load prefetch and 2 for |
350 | | // a store prefetch. |
351 | | PREFETCH |
352 | | }; |
353 | | |
354 | | // Return true if OPCODE is some kind of PC-relative address. |
355 | 8.69k | inline bool isPCREL(unsigned Opcode) { |
356 | 8.69k | return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET6.11k ; |
357 | 8.69k | } |
358 | | } // end namespace SystemZISD |
359 | | |
360 | | namespace SystemZICMP { |
361 | | // Describes whether an integer comparison needs to be signed or unsigned, |
362 | | // or whether either type is OK. |
363 | | enum { |
364 | | Any, |
365 | | UnsignedOnly, |
366 | | SignedOnly |
367 | | }; |
368 | | } // end namespace SystemZICMP |
369 | | |
370 | | class SystemZSubtarget; |
371 | | class SystemZTargetMachine; |
372 | | |
373 | | class SystemZTargetLowering : public TargetLowering { |
374 | | public: |
375 | | explicit SystemZTargetLowering(const TargetMachine &TM, |
376 | | const SystemZSubtarget &STI); |
377 | | |
378 | | // Override TargetLowering. |
379 | 5.14k | MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { |
380 | 5.14k | return MVT::i32; |
381 | 5.14k | } |
382 | 5.46k | MVT getVectorIdxTy(const DataLayout &DL) const override { |
383 | 5.46k | // Only the lower 12 bits of an element index are used, so we don't |
384 | 5.46k | // want to clobber the upper 32 bits of a GPR unnecessarily. |
385 | 5.46k | return MVT::i32; |
386 | 5.46k | } |
387 | | TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) |
388 | 119k | const override { |
389 | 119k | // Widen subvectors to the full width rather than promoting integer |
390 | 119k | // elements. This is better because: |
391 | 119k | // |
392 | 119k | // (a) it means that we can handle the ABI for passing and returning |
393 | 119k | // sub-128 vectors without having to handle them as legal types. |
394 | 119k | // |
395 | 119k | // (b) we don't have instructions to extend on load and truncate on store, |
396 | 119k | // so promoting the integers is less efficient. |
397 | 119k | // |
398 | 119k | // (c) there are no multiplication instructions for the widest integer |
399 | 119k | // type (v2i64). |
400 | 119k | if (VT.getScalarSizeInBits() % 8 == 0) |
401 | 101k | return TypeWidenVector; |
402 | 17.5k | return TargetLoweringBase::getPreferredVectorAction(VT); |
403 | 17.5k | } |
404 | 16 | bool isCheapToSpeculateCtlz() const override { return true; } |
405 | | EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, |
406 | | EVT) const override; |
407 | | bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; |
408 | | bool isFPImmLegal(const APFloat &Imm, EVT VT, |
409 | | bool ForCodeSize) const override; |
410 | | bool isLegalICmpImmediate(int64_t Imm) const override; |
411 | | bool isLegalAddImmediate(int64_t Imm) const override; |
412 | | bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, |
413 | | unsigned AS, |
414 | | Instruction *I = nullptr) const override; |
415 | | bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, |
416 | | unsigned Align, |
417 | | MachineMemOperand::Flags Flags, |
418 | | bool *Fast) const override; |
419 | | bool isTruncateFree(Type *, Type *) const override; |
420 | | bool isTruncateFree(EVT, EVT) const override; |
421 | | const char *getTargetNodeName(unsigned Opcode) const override; |
422 | | std::pair<unsigned, const TargetRegisterClass *> |
423 | | getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
424 | | StringRef Constraint, MVT VT) const override; |
425 | | TargetLowering::ConstraintType |
426 | | getConstraintType(StringRef Constraint) const override; |
427 | | TargetLowering::ConstraintWeight |
428 | | getSingleConstraintMatchWeight(AsmOperandInfo &info, |
429 | | const char *constraint) const override; |
430 | | void LowerAsmOperandForConstraint(SDValue Op, |
431 | | std::string &Constraint, |
432 | | std::vector<SDValue> &Ops, |
433 | | SelectionDAG &DAG) const override; |
434 | | |
435 | 24 | unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { |
436 | 24 | if (ConstraintCode.size() == 1) { |
437 | 24 | switch(ConstraintCode[0]) { |
438 | 24 | default: |
439 | 1 | break; |
440 | 24 | case 'o': |
441 | 1 | return InlineAsm::Constraint_o; |
442 | 24 | case 'Q': |
443 | 5 | return InlineAsm::Constraint_Q; |
444 | 24 | case 'R': |
445 | 7 | return InlineAsm::Constraint_R; |
446 | 24 | case 'S': |
447 | 4 | return InlineAsm::Constraint_S; |
448 | 24 | case 'T': |
449 | 6 | return InlineAsm::Constraint_T; |
450 | 1 | } |
451 | 1 | } |
452 | 1 | return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); |
453 | 1 | } |
454 | | |
455 | | /// If a physical register, this returns the register that receives the |
456 | | /// exception address on entry to an EH pad. |
457 | | unsigned |
458 | 8 | getExceptionPointerRegister(const Constant *PersonalityFn) const override { |
459 | 8 | return SystemZ::R6D; |
460 | 8 | } |
461 | | |
462 | | /// If a physical register, this returns the register that receives the |
463 | | /// exception typeid on entry to a landing pad. |
464 | | unsigned |
465 | 4 | getExceptionSelectorRegister(const Constant *PersonalityFn) const override { |
466 | 4 | return SystemZ::R7D; |
467 | 4 | } |
468 | | |
469 | | /// Override to support customized stack guard loading. |
470 | 3 | bool useLoadStackGuardNode() const override { |
471 | 3 | return true; |
472 | 3 | } |
473 | 1 | void insertSSPDeclarations(Module &M) const override { |
474 | 1 | } |
475 | | |
476 | | MachineBasicBlock * |
477 | | EmitInstrWithCustomInserter(MachineInstr &MI, |
478 | | MachineBasicBlock *BB) const override; |
479 | | SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |
480 | | void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, |
481 | | SelectionDAG &DAG) const override; |
482 | | void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, |
483 | | SelectionDAG &DAG) const override; |
484 | | const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; |
485 | | bool allowTruncateForTailCall(Type *, Type *) const override; |
486 | | bool mayBeEmittedAsTailCall(const CallInst *CI) const override; |
487 | | SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, |
488 | | bool isVarArg, |
489 | | const SmallVectorImpl<ISD::InputArg> &Ins, |
490 | | const SDLoc &DL, SelectionDAG &DAG, |
491 | | SmallVectorImpl<SDValue> &InVals) const override; |
492 | | SDValue LowerCall(CallLoweringInfo &CLI, |
493 | | SmallVectorImpl<SDValue> &InVals) const override; |
494 | | |
495 | | bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, |
496 | | bool isVarArg, |
497 | | const SmallVectorImpl<ISD::OutputArg> &Outs, |
498 | | LLVMContext &Context) const override; |
499 | | SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, |
500 | | const SmallVectorImpl<ISD::OutputArg> &Outs, |
501 | | const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, |
502 | | SelectionDAG &DAG) const override; |
503 | | SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; |
504 | | |
505 | | /// Determine which of the bits specified in Mask are known to be either |
506 | | /// zero or one and return them in the KnownZero/KnownOne bitsets. |
507 | | void computeKnownBitsForTargetNode(const SDValue Op, |
508 | | KnownBits &Known, |
509 | | const APInt &DemandedElts, |
510 | | const SelectionDAG &DAG, |
511 | | unsigned Depth = 0) const override; |
512 | | |
513 | | /// Determine the number of bits in the operation that are sign bits. |
514 | | unsigned ComputeNumSignBitsForTargetNode(SDValue Op, |
515 | | const APInt &DemandedElts, |
516 | | const SelectionDAG &DAG, |
517 | | unsigned Depth) const override; |
518 | | |
519 | 51 | ISD::NodeType getExtendForAtomicOps() const override { |
520 | 51 | return ISD::ANY_EXTEND; |
521 | 51 | } |
522 | | |
523 | 145k | bool supportSwiftError() const override { |
524 | 145k | return true; |
525 | 145k | } |
526 | | |
527 | | private: |
528 | | const SystemZSubtarget &Subtarget; |
529 | | |
530 | | // Implement LowerOperation for individual opcodes. |
531 | | SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, |
532 | | const SDLoc &DL, EVT VT, |
533 | | SDValue CmpOp0, SDValue CmpOp1) const; |
534 | | SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, |
535 | | EVT VT, ISD::CondCode CC, |
536 | | SDValue CmpOp0, SDValue CmpOp1) const; |
537 | | SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; |
538 | | SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; |
539 | | SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; |
540 | | SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, |
541 | | SelectionDAG &DAG) const; |
542 | | SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, |
543 | | SelectionDAG &DAG, unsigned Opcode, |
544 | | SDValue GOTOffset) const; |
545 | | SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; |
546 | | SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, |
547 | | SelectionDAG &DAG) const; |
548 | | SDValue lowerBlockAddress(BlockAddressSDNode *Node, |
549 | | SelectionDAG &DAG) const; |
550 | | SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; |
551 | | SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; |
552 | | SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; |
553 | | SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; |
554 | | SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; |
555 | | SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; |
556 | | SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; |
557 | | SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; |
558 | | SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; |
559 | | SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; |
560 | | SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; |
561 | | SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; |
562 | | SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const; |
563 | | SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const; |
564 | | SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; |
565 | | SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; |
566 | | SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; |
567 | | SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; |
568 | | SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; |
569 | | SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; |
570 | | SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, |
571 | | unsigned Opcode) const; |
572 | | SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; |
573 | | SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; |
574 | | SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; |
575 | | SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; |
576 | | SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; |
577 | | SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; |
578 | | SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; |
579 | | bool isVectorElementLoad(SDValue Op) const; |
580 | | SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, |
581 | | SmallVectorImpl<SDValue> &Elems) const; |
582 | | SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; |
583 | | SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; |
584 | | SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; |
585 | | SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; |
586 | | SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; |
587 | | SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, |
588 | | unsigned UnpackHigh) const; |
589 | | SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; |
590 | | |
591 | | bool canTreatAsByteVector(EVT VT) const; |
592 | | SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, |
593 | | unsigned Index, DAGCombinerInfo &DCI, |
594 | | bool Force) const; |
595 | | SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, |
596 | | DAGCombinerInfo &DCI) const; |
597 | | SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; |
598 | | SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; |
599 | | SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const; |
600 | | SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; |
601 | | bool canLoadStoreByteSwapped(EVT VT) const; |
602 | | SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const; |
603 | | SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; |
604 | | SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const; |
605 | | SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; |
606 | | SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; |
607 | | SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; |
608 | | SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; |
609 | | SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; |
610 | | SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; |
611 | | SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; |
612 | | SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; |
613 | | SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const; |
614 | | |
615 | | SDValue unwrapAddress(SDValue N) const override; |
616 | | |
617 | | // If the last instruction before MBBI in MBB was some form of COMPARE, |
618 | | // try to replace it with a COMPARE AND BRANCH just before MBBI. |
619 | | // CCMask and Target are the BRC-like operands for the branch. |
620 | | // Return true if the change was made. |
621 | | bool convertPrevCompareToBranch(MachineBasicBlock *MBB, |
622 | | MachineBasicBlock::iterator MBBI, |
623 | | unsigned CCMask, |
624 | | MachineBasicBlock *Target) const; |
625 | | |
626 | | // Implement EmitInstrWithCustomInserter for individual operation types. |
627 | | MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; |
628 | | MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, |
629 | | unsigned StoreOpcode, unsigned STOCOpcode, |
630 | | bool Invert) const; |
631 | | MachineBasicBlock *emitPair128(MachineInstr &MI, |
632 | | MachineBasicBlock *MBB) const; |
633 | | MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, |
634 | | bool ClearEven) const; |
635 | | MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, |
636 | | MachineBasicBlock *BB, |
637 | | unsigned BinOpcode, unsigned BitSize, |
638 | | bool Invert = false) const; |
639 | | MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, |
640 | | MachineBasicBlock *MBB, |
641 | | unsigned CompareOpcode, |
642 | | unsigned KeepOldMask, |
643 | | unsigned BitSize) const; |
644 | | MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, |
645 | | MachineBasicBlock *BB) const; |
646 | | MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, |
647 | | unsigned Opcode) const; |
648 | | MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, |
649 | | unsigned Opcode) const; |
650 | | MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, |
651 | | MachineBasicBlock *MBB, |
652 | | unsigned Opcode, bool NoFloat) const; |
653 | | MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, |
654 | | MachineBasicBlock *MBB, |
655 | | unsigned Opcode) const; |
656 | | |
657 | | MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override; |
658 | | const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; |
659 | | }; |
660 | | |
661 | | struct SystemZVectorConstantInfo { |
662 | | private: |
663 | | APInt IntBits; // The 128 bits as an integer. |
664 | | APInt SplatBits; // Smallest splat value. |
665 | | APInt SplatUndef; // Bits correspoding to undef operands of the BVN. |
666 | | unsigned SplatBitSize = 0; |
667 | | bool isFP128 = false; |
668 | | |
669 | | public: |
670 | | unsigned Opcode = 0; |
671 | | SmallVector<unsigned, 2> OpVals; |
672 | | MVT VecVT; |
673 | | SystemZVectorConstantInfo(APFloat FPImm); |
674 | | SystemZVectorConstantInfo(BuildVectorSDNode *BVN); |
675 | | bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); |
676 | | }; |
677 | | |
678 | | } // end namespace llvm |
679 | | |
680 | | #endif |