Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/SystemZ/SystemZISelLowering.h
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//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SystemZ uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace SystemZISD {
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enum NodeType : unsigned {
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  FIRST_NUMBER = ISD::BUILTIN_OP_END,
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  // Return with a flag operand.  Operand 0 is the chain operand.
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  RET_FLAG,
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31
  // Calls a function.  Operand 0 is the chain operand and operand 1
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  // is the target address.  The arguments start at operand 2.
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  // There is an optional glue operand at the end.
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  CALL,
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  SIBCALL,
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  // TLS calls.  Like regular calls, except operand 1 is the TLS symbol.
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  // (The call target is implicitly __tls_get_offset.)
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  TLS_GDCALL,
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  TLS_LDCALL,
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  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
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  // accesses (LARL).  Operand 0 is the address.
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  PCREL_WRAPPER,
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  // Used in cases where an offset is applied to a TargetGlobalAddress.
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  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
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  // PCREL_WRAPPER for an anchor point.  This is used so that we can
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  // cheaply refer to either the full address or the anchor point
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  // as a register base.
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  PCREL_OFFSET,
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  // Integer absolute.
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  IABS,
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  // Integer comparisons.  There are three operands: the two values
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  // to compare, and an integer of type SystemZICMP.
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  ICMP,
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  // Floating-point comparisons.  The two operands are the values to compare.
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  FCMP,
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63
  // Test under mask.  The first operand is ANDed with the second operand
64
  // and the condition codes are set on the result.  The third operand is
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  // a boolean that is true if the condition codes need to distinguish
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  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
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  // register forms do but the memory forms don't).
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  TM,
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70
  // Branches if a condition is true.  Operand 0 is the chain operand;
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  // operand 1 is the 4-bit condition-code mask, with bit N in
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  // big-endian order meaning "branch if CC=N"; operand 2 is the
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  // target block and operand 3 is the flag operand.
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  BR_CCMASK,
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76
  // Selects between operand 0 and operand 1.  Operand 2 is the
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  // mask of condition-code values for which operand 0 should be
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  // chosen over operand 1; it has the same form as BR_CCMASK.
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  // Operand 3 is the flag operand.
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  SELECT_CCMASK,
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  // Evaluates to the gap between the stack pointer and the
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  // base of the dynamically-allocatable area.
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  ADJDYNALLOC,
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  // Count number of bits set in operand 0 per byte.
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  POPCNT,
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  // Wrappers around the ISD opcodes of the same name.  The output is GR128.
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  // Input operands may be GR64 or GR32, depending on the instruction.
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  SMUL_LOHI,
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  UMUL_LOHI,
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  SDIVREM,
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  UDIVREM,
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96
  // Add/subtract with overflow/carry.  These have the same operands as
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  // the corresponding standard operations, except with the carry flag
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  // replaced by a condition code value.
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  SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY,
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101
  // Set the condition code from a boolean value in operand 0.
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  // Operand 1 is a mask of all condition-code values that may result of this
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  // operation, operand 2 is a mask of condition-code values that may result
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  // if the boolean is true.
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  // Note that this operation is always optimized away, we will never
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  // generate any code for it.
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  GET_CCMASK,
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109
  // Use a series of MVCs to copy bytes from one memory location to another.
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  // The operands are:
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  // - the target address
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  // - the source address
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  // - the constant length
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  //
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  // This isn't a memory opcode because we'd need to attach two
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  // MachineMemOperands rather than one.
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  MVC,
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  // Like MVC, but implemented as a loop that handles X*256 bytes
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  // followed by straight-line code to handle the rest (if any).
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  // The value of X is passed as an additional operand.
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  MVC_LOOP,
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  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
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  NC,
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  NC_LOOP,
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  OC,
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  OC_LOOP,
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  XC,
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  XC_LOOP,
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  // Use CLC to compare two blocks of memory, with the same comments
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  // as for MVC and MVC_LOOP.
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  CLC,
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  CLC_LOOP,
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  // Use an MVST-based sequence to implement stpcpy().
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  STPCPY,
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  // Use a CLST-based sequence to implement strcmp().  The two input operands
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  // are the addresses of the strings to compare.
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  STRCMP,
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  // Use an SRST-based sequence to search a block of memory.  The first
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  // operand is the end address, the second is the start, and the third
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  // is the character to search for.  CC is set to 1 on success and 2
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  // on failure.
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  SEARCH_STRING,
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  // Store the CC value in bits 29 and 28 of an integer.
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  IPM,
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  // Compiler barrier only; generate a no-op.
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  MEMBARRIER,
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  // Transaction begin.  The first operand is the chain, the second
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  // the TDB pointer, and the third the immediate control field.
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  // Returns CC value and chain.
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  TBEGIN,
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  TBEGIN_NOFLOAT,
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  // Transaction end.  Just the chain operand.  Returns CC value and chain.
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  TEND,
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  // Create a vector constant by filling byte N of the result with bit
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  // 15-N of the single operand.
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  BYTE_MASK,
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169
  // Create a vector constant by replicating an element-sized RISBG-style mask.
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  // The first operand specifies the starting set bit and the second operand
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  // specifies the ending set bit.  Both operands count from the MSB of the
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  // element.
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  ROTATE_MASK,
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175
  // Replicate a GPR scalar value into all elements of a vector.
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  REPLICATE,
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  // Create a vector from two i64 GPRs.
179
  JOIN_DWORDS,
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  // Replicate one element of a vector into all elements.  The first operand
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  // is the vector and the second is the index of the element to replicate.
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  SPLAT,
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  // Interleave elements from the high half of operand 0 and the high half
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  // of operand 1.
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  MERGE_HIGH,
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  // Likewise for the low halves.
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  MERGE_LOW,
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  // Concatenate the vectors in the first two operands, shift them left
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  // by the third operand, and take the first half of the result.
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  SHL_DOUBLE,
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196
  // Take one element of the first v2i64 operand and the one element of
197
  // the second v2i64 operand and concatenate them to form a v2i64 result.
198
  // The third operand is a 4-bit value of the form 0A0B, where A and B
199
  // are the element selectors for the first operand and second operands
200
  // respectively.
201
  PERMUTE_DWORDS,
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  // Perform a general vector permute on vector operands 0 and 1.
204
  // Each byte of operand 2 controls the corresponding byte of the result,
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  // in the same way as a byte-level VECTOR_SHUFFLE mask.
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  PERMUTE,
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  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
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  PACK,
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211
  // Likewise, but saturate the result and set CC.  PACKS_CC does signed
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  // saturation and PACKLS_CC does unsigned saturation.
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  PACKS_CC,
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  PACKLS_CC,
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  // Unpack the first half of vector operand 0 into double-sized elements.
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  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
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  UNPACK_HIGH,
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  UNPACKL_HIGH,
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  // Likewise for the second half.
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  UNPACK_LOW,
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  UNPACKL_LOW,
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  // Shift each element of vector operand 0 by the number of bits specified
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  // by scalar operand 1.
227
  VSHL_BY_SCALAR,
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  VSRL_BY_SCALAR,
229
  VSRA_BY_SCALAR,
230
231
  // For each element of the output type, sum across all sub-elements of
232
  // operand 0 belonging to the corresponding element, and add in the
233
  // rightmost sub-element of the corresponding element of operand 1.
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  VSUM,
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  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
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  // vector result.  VICMPE is for equality, VICMPH for "signed greater than"
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  // and VICMPHL for "unsigned greater than".
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  VICMPE,
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  VICMPH,
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  VICMPHL,
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  // Likewise, but also set the condition codes on the result.
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  VICMPES,
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  VICMPHS,
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  VICMPHLS,
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  // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
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  // vector result.  VFCMPE is for "ordered and equal", VFCMPH for "ordered and
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  // greater than" and VFCMPHE for "ordered and greater than or equal to".
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  VFCMPE,
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  VFCMPH,
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  VFCMPHE,
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  // Likewise, but also set the condition codes on the result.
256
  VFCMPES,
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  VFCMPHS,
258
  VFCMPHES,
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260
  // Test floating-point data class for vectors.
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  VFTCI,
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  // Extend the even f32 elements of vector operand 0 to produce a vector
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  // of f64 elements.
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  VEXTEND,
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  // Round the f64 elements of vector operand 0 to f32s and store them in the
268
  // even elements of the result.
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  VROUND,
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  // AND the two vector operands together and set CC based on the result.
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  VTM,
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  // String operations that set CC as a side-effect.
275
  VFAE_CC,
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  VFAEZ_CC,
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  VFEE_CC,
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  VFEEZ_CC,
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  VFENE_CC,
280
  VFENEZ_CC,
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  VISTR_CC,
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  VSTRC_CC,
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  VSTRCZ_CC,
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  VSTRS_CC,
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  VSTRSZ_CC,
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  // Test Data Class.
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  //
289
  // Operand 0: the value to test
290
  // Operand 1: the bit mask
291
  TDC,
292
293
  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
294
  // ATOMIC_LOAD_<op>.
295
  //
296
  // Operand 0: the address of the containing 32-bit-aligned field
297
  // Operand 1: the second operand of <op>, in the high bits of an i32
298
  //            for everything except ATOMIC_SWAPW
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  // Operand 2: how many bits to rotate the i32 left to bring the first
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  //            operand into the high bits
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  // Operand 3: the negative of operand 2, for rotating the other way
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  // Operand 4: the width of the field in bits (8 or 16)
303
  ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
304
  ATOMIC_LOADW_ADD,
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  ATOMIC_LOADW_SUB,
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  ATOMIC_LOADW_AND,
307
  ATOMIC_LOADW_OR,
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  ATOMIC_LOADW_XOR,
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  ATOMIC_LOADW_NAND,
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  ATOMIC_LOADW_MIN,
311
  ATOMIC_LOADW_MAX,
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  ATOMIC_LOADW_UMIN,
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  ATOMIC_LOADW_UMAX,
314
315
  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
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  //
317
  // Operand 0: the address of the containing 32-bit-aligned field
318
  // Operand 1: the compare value, in the low bits of an i32
319
  // Operand 2: the swap value, in the low bits of an i32
320
  // Operand 3: how many bits to rotate the i32 left to bring the first
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  //            operand into the high bits
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  // Operand 4: the negative of operand 2, for rotating the other way
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  // Operand 5: the width of the field in bits (8 or 16)
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  ATOMIC_CMP_SWAPW,
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326
  // Atomic compare-and-swap returning CC value.
327
  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
328
  ATOMIC_CMP_SWAP,
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330
  // 128-bit atomic load.
331
  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
332
  ATOMIC_LOAD_128,
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  // 128-bit atomic store.
335
  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
336
  ATOMIC_STORE_128,
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338
  // 128-bit atomic compare-and-swap.
339
  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
340
  ATOMIC_CMP_SWAP_128,
341
342
  // Byte swapping load/store.  Same operands as regular load/store.
343
  LRV, STRV,
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345
  // Element swapping load/store.  Same operands as regular load/store.
346
  VLER, VSTER,
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348
  // Prefetch from the second operand using the 4-bit control code in
349
  // the first operand.  The code is 1 for a load prefetch and 2 for
350
  // a store prefetch.
351
  PREFETCH
352
};
353
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// Return true if OPCODE is some kind of PC-relative address.
355
8.69k
inline bool isPCREL(unsigned Opcode) {
356
8.69k
  return Opcode == PCREL_WRAPPER || 
Opcode == PCREL_OFFSET6.11k
;
357
8.69k
}
358
} // end namespace SystemZISD
359
360
namespace SystemZICMP {
361
// Describes whether an integer comparison needs to be signed or unsigned,
362
// or whether either type is OK.
363
enum {
364
  Any,
365
  UnsignedOnly,
366
  SignedOnly
367
};
368
} // end namespace SystemZICMP
369
370
class SystemZSubtarget;
371
class SystemZTargetMachine;
372
373
class SystemZTargetLowering : public TargetLowering {
374
public:
375
  explicit SystemZTargetLowering(const TargetMachine &TM,
376
                                 const SystemZSubtarget &STI);
377
378
  // Override TargetLowering.
379
5.14k
  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
380
5.14k
    return MVT::i32;
381
5.14k
  }
382
5.46k
  MVT getVectorIdxTy(const DataLayout &DL) const override {
383
5.46k
    // Only the lower 12 bits of an element index are used, so we don't
384
5.46k
    // want to clobber the upper 32 bits of a GPR unnecessarily.
385
5.46k
    return MVT::i32;
386
5.46k
  }
387
  TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
388
119k
    const override {
389
119k
    // Widen subvectors to the full width rather than promoting integer
390
119k
    // elements.  This is better because:
391
119k
    //
392
119k
    // (a) it means that we can handle the ABI for passing and returning
393
119k
    //     sub-128 vectors without having to handle them as legal types.
394
119k
    //
395
119k
    // (b) we don't have instructions to extend on load and truncate on store,
396
119k
    //     so promoting the integers is less efficient.
397
119k
    //
398
119k
    // (c) there are no multiplication instructions for the widest integer
399
119k
    //     type (v2i64).
400
119k
    if (VT.getScalarSizeInBits() % 8 == 0)
401
101k
      return TypeWidenVector;
402
17.5k
    return TargetLoweringBase::getPreferredVectorAction(VT);
403
17.5k
  }
404
16
  bool isCheapToSpeculateCtlz() const override { return true; }
405
  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
406
                         EVT) const override;
407
  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
408
  bool isFPImmLegal(const APFloat &Imm, EVT VT,
409
                    bool ForCodeSize) const override;
410
  bool isLegalICmpImmediate(int64_t Imm) const override;
411
  bool isLegalAddImmediate(int64_t Imm) const override;
412
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
413
                             unsigned AS,
414
                             Instruction *I = nullptr) const override;
415
  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
416
                                      unsigned Align,
417
                                      MachineMemOperand::Flags Flags,
418
                                      bool *Fast) const override;
419
  bool isTruncateFree(Type *, Type *) const override;
420
  bool isTruncateFree(EVT, EVT) const override;
421
  const char *getTargetNodeName(unsigned Opcode) const override;
422
  std::pair<unsigned, const TargetRegisterClass *>
423
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
424
                               StringRef Constraint, MVT VT) const override;
425
  TargetLowering::ConstraintType
426
  getConstraintType(StringRef Constraint) const override;
427
  TargetLowering::ConstraintWeight
428
    getSingleConstraintMatchWeight(AsmOperandInfo &info,
429
                                   const char *constraint) const override;
430
  void LowerAsmOperandForConstraint(SDValue Op,
431
                                    std::string &Constraint,
432
                                    std::vector<SDValue> &Ops,
433
                                    SelectionDAG &DAG) const override;
434
435
24
  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
436
24
    if (ConstraintCode.size() == 1) {
437
24
      switch(ConstraintCode[0]) {
438
24
      default:
439
1
        break;
440
24
      case 'o':
441
1
        return InlineAsm::Constraint_o;
442
24
      case 'Q':
443
5
        return InlineAsm::Constraint_Q;
444
24
      case 'R':
445
7
        return InlineAsm::Constraint_R;
446
24
      case 'S':
447
4
        return InlineAsm::Constraint_S;
448
24
      case 'T':
449
6
        return InlineAsm::Constraint_T;
450
1
      }
451
1
    }
452
1
    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
453
1
  }
454
455
  /// If a physical register, this returns the register that receives the
456
  /// exception address on entry to an EH pad.
457
  unsigned
458
8
  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
459
8
    return SystemZ::R6D;
460
8
  }
461
462
  /// If a physical register, this returns the register that receives the
463
  /// exception typeid on entry to a landing pad.
464
  unsigned
465
4
  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
466
4
    return SystemZ::R7D;
467
4
  }
468
469
  /// Override to support customized stack guard loading.
470
3
  bool useLoadStackGuardNode() const override {
471
3
    return true;
472
3
  }
473
1
  void insertSSPDeclarations(Module &M) const override {
474
1
  }
475
476
  MachineBasicBlock *
477
  EmitInstrWithCustomInserter(MachineInstr &MI,
478
                              MachineBasicBlock *BB) const override;
479
  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
480
  void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
481
                             SelectionDAG &DAG) const override;
482
  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
483
                          SelectionDAG &DAG) const override;
484
  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
485
  bool allowTruncateForTailCall(Type *, Type *) const override;
486
  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
487
  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
488
                               bool isVarArg,
489
                               const SmallVectorImpl<ISD::InputArg> &Ins,
490
                               const SDLoc &DL, SelectionDAG &DAG,
491
                               SmallVectorImpl<SDValue> &InVals) const override;
492
  SDValue LowerCall(CallLoweringInfo &CLI,
493
                    SmallVectorImpl<SDValue> &InVals) const override;
494
495
  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
496
                      bool isVarArg,
497
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
498
                      LLVMContext &Context) const override;
499
  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
500
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
501
                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
502
                      SelectionDAG &DAG) const override;
503
  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
504
505
  /// Determine which of the bits specified in Mask are known to be either
506
  /// zero or one and return them in the KnownZero/KnownOne bitsets.
507
  void computeKnownBitsForTargetNode(const SDValue Op,
508
                                     KnownBits &Known,
509
                                     const APInt &DemandedElts,
510
                                     const SelectionDAG &DAG,
511
                                     unsigned Depth = 0) const override;
512
513
  /// Determine the number of bits in the operation that are sign bits.
514
  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
515
                                           const APInt &DemandedElts,
516
                                           const SelectionDAG &DAG,
517
                                           unsigned Depth) const override;
518
519
51
  ISD::NodeType getExtendForAtomicOps() const override {
520
51
    return ISD::ANY_EXTEND;
521
51
  }
522
523
145k
  bool supportSwiftError() const override {
524
145k
    return true;
525
145k
  }
526
527
private:
528
  const SystemZSubtarget &Subtarget;
529
530
  // Implement LowerOperation for individual opcodes.
531
  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
532
                       const SDLoc &DL, EVT VT,
533
                       SDValue CmpOp0, SDValue CmpOp1) const;
534
  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
535
                           EVT VT, ISD::CondCode CC,
536
                           SDValue CmpOp0, SDValue CmpOp1) const;
537
  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
538
  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
539
  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
540
  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
541
                             SelectionDAG &DAG) const;
542
  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
543
                            SelectionDAG &DAG, unsigned Opcode,
544
                            SDValue GOTOffset) const;
545
  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
546
  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
547
                                SelectionDAG &DAG) const;
548
  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
549
                            SelectionDAG &DAG) const;
550
  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
551
  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
552
  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
553
  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
554
  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
555
  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
556
  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
557
  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
558
  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
559
  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
560
  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
561
  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
562
  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
563
  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
564
  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
565
  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
566
  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
567
  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
568
  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
569
  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
570
  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
571
                              unsigned Opcode) const;
572
  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
573
  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
574
  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
575
  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
576
  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
577
  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
578
  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
579
  bool isVectorElementLoad(SDValue Op) const;
580
  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
581
                      SmallVectorImpl<SDValue> &Elems) const;
582
  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
583
  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
584
  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
585
  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
586
  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
587
  SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
588
                                 unsigned UnpackHigh) const;
589
  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
590
591
  bool canTreatAsByteVector(EVT VT) const;
592
  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
593
                         unsigned Index, DAGCombinerInfo &DCI,
594
                         bool Force) const;
595
  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
596
                                 DAGCombinerInfo &DCI) const;
597
  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
598
  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
599
  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
600
  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
601
  bool canLoadStoreByteSwapped(EVT VT) const;
602
  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
603
  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
604
  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
605
  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
606
  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
607
  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
608
  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
609
  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
610
  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
611
  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
612
  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
613
  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
614
615
  SDValue unwrapAddress(SDValue N) const override;
616
617
  // If the last instruction before MBBI in MBB was some form of COMPARE,
618
  // try to replace it with a COMPARE AND BRANCH just before MBBI.
619
  // CCMask and Target are the BRC-like operands for the branch.
620
  // Return true if the change was made.
621
  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
622
                                  MachineBasicBlock::iterator MBBI,
623
                                  unsigned CCMask,
624
                                  MachineBasicBlock *Target) const;
625
626
  // Implement EmitInstrWithCustomInserter for individual operation types.
627
  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
628
  MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
629
                                   unsigned StoreOpcode, unsigned STOCOpcode,
630
                                   bool Invert) const;
631
  MachineBasicBlock *emitPair128(MachineInstr &MI,
632
                                 MachineBasicBlock *MBB) const;
633
  MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
634
                                bool ClearEven) const;
635
  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
636
                                          MachineBasicBlock *BB,
637
                                          unsigned BinOpcode, unsigned BitSize,
638
                                          bool Invert = false) const;
639
  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
640
                                          MachineBasicBlock *MBB,
641
                                          unsigned CompareOpcode,
642
                                          unsigned KeepOldMask,
643
                                          unsigned BitSize) const;
644
  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
645
                                        MachineBasicBlock *BB) const;
646
  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
647
                                       unsigned Opcode) const;
648
  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
649
                                       unsigned Opcode) const;
650
  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
651
                                          MachineBasicBlock *MBB,
652
                                          unsigned Opcode, bool NoFloat) const;
653
  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
654
                                         MachineBasicBlock *MBB,
655
                                         unsigned Opcode) const;
656
657
  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
658
  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
659
};
660
661
struct SystemZVectorConstantInfo {
662
private:
663
  APInt IntBits;             // The 128 bits as an integer.
664
  APInt SplatBits;           // Smallest splat value.
665
  APInt SplatUndef;          // Bits correspoding to undef operands of the BVN.
666
  unsigned SplatBitSize = 0;
667
  bool isFP128 = false;
668
669
public:
670
  unsigned Opcode = 0;
671
  SmallVector<unsigned, 2> OpVals;
672
  MVT VecVT;
673
  SystemZVectorConstantInfo(APFloat FPImm);
674
  SystemZVectorConstantInfo(BuildVectorSDNode *BVN);
675
  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
676
};
677
678
} // end namespace llvm
679
680
#endif