Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
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//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the WebAssembly implementation of the
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/// TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyInstrInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-instr-info"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "WebAssemblyGenInstrInfo.inc"
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// defines WebAssembly::getNamedOperandIdx
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#define GET_INSTRINFO_NAMED_OPS
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#include "WebAssemblyGenInstrInfo.inc"
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WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
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    : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
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                              WebAssembly::ADJCALLSTACKUP,
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                              WebAssembly::CATCHRET),
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      RI(STI.getTargetTriple()) {}
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bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
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    const MachineInstr &MI, AliasAnalysis *AA) const {
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  switch (MI.getOpcode()) {
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  case WebAssembly::CONST_I32:
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  case WebAssembly::CONST_I64:
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  case WebAssembly::CONST_F32:
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  case WebAssembly::CONST_F64:
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    // isReallyTriviallyReMaterializableGeneric misses these because of the
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    // ARGUMENTS implicit def, so we manualy override it here.
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    return true;
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  default:
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    return false;
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  }
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}
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void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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                                       MachineBasicBlock::iterator I,
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                                       const DebugLoc &DL, unsigned DestReg,
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                                       unsigned SrcReg, bool KillSrc) const {
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  // This method is called by post-RA expansion, which expects only pregs to
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  // exist. However we need to handle both here.
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  auto &MRI = MBB.getParent()->getRegInfo();
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  const TargetRegisterClass *RC =
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      TargetRegisterInfo::isVirtualRegister(DestReg)
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          ? 
MRI.getRegClass(DestReg)108
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          : 
MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg)18
;
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  unsigned CopyOpcode;
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  if (RC == &WebAssembly::I32RegClass)
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    CopyOpcode = WebAssembly::COPY_I32;
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  else if (RC == &WebAssembly::I64RegClass)
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    CopyOpcode = WebAssembly::COPY_I64;
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  else if (RC == &WebAssembly::F32RegClass)
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    CopyOpcode = WebAssembly::COPY_F32;
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  else if (RC == &WebAssembly::F64RegClass)
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    CopyOpcode = WebAssembly::COPY_F64;
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  else if (RC == &WebAssembly::V128RegClass)
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    CopyOpcode = WebAssembly::COPY_V128;
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  else if (RC == &WebAssembly::EXNREFRegClass)
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    CopyOpcode = WebAssembly::COPY_EXNREF;
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  else
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llvm_unreachable0
("Unexpected register class");
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  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
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      .addReg(SrcReg, KillSrc ? 
RegState::Kill0
: 0);
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}
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MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
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    MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
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  // If the operands are stackified, we can't reorder them.
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  WebAssemblyFunctionInfo &MFI =
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      *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
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  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
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      MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
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    return nullptr;
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  // Otherwise use the default implementation.
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  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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// Branch analysis.
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bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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                                         MachineBasicBlock *&TBB,
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                                         MachineBasicBlock *&FBB,
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                                         SmallVectorImpl<MachineOperand> &Cond,
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                                         bool /*AllowModify*/) const {
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  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
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  // WebAssembly has control flow that doesn't have explicit branches or direct
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  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
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  // is created after CFGStackify.
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  if (MFI.isCFGStackified())
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    return true;
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  bool HaveCond = false;
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  for (MachineInstr &MI : MBB.terminators()) {
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    switch (MI.getOpcode()) {
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    default:
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      // Unhandled instruction; bail out.
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      return true;
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    case WebAssembly::BR_IF:
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      if (HaveCond)
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        return true;
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      Cond.push_back(MachineOperand::CreateImm(true));
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      Cond.push_back(MI.getOperand(1));
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      TBB = MI.getOperand(0).getMBB();
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      HaveCond = true;
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      break;
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    case WebAssembly::BR_UNLESS:
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      if (HaveCond)
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        return true;
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      Cond.push_back(MachineOperand::CreateImm(false));
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      Cond.push_back(MI.getOperand(1));
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      TBB = MI.getOperand(0).getMBB();
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      HaveCond = true;
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      break;
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    case WebAssembly::BR:
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      if (!HaveCond)
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        TBB = MI.getOperand(0).getMBB();
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      else
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        FBB = MI.getOperand(0).getMBB();
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      break;
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    case WebAssembly::BR_ON_EXN:
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      if (HaveCond)
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        return true;
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      Cond.push_back(MachineOperand::CreateImm(true));
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      Cond.push_back(MI.getOperand(2));
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      TBB = MI.getOperand(0).getMBB();
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      HaveCond = true;
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      break;
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    }
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    if (MI.isBarrier())
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      break;
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  }
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return false14.6k
;
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}
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unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
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                                            int *BytesRemoved) const {
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  assert(!BytesRemoved && "code size not handled");
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  MachineBasicBlock::instr_iterator I = MBB.instr_end();
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  unsigned Count = 0;
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  while (I != MBB.instr_begin()) {
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    --I;
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    if (I->isDebugInstr())
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      continue;
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    if (!I->isTerminator())
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      break;
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    // Remove the branch.
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    I->eraseFromParent();
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    I = MBB.instr_end();
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    ++Count;
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  }
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  return Count;
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}
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unsigned WebAssemblyInstrInfo::insertBranch(
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    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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    ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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  assert(!BytesAdded && "code size not handled");
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  if (Cond.empty()) {
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    if (!TBB)
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      return 0;
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    BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
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    return 1;
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  }
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  assert(Cond.size() == 2 && "Expected a flag and a successor block");
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  MachineFunction &MF = *MBB.getParent();
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  auto &MRI = MF.getRegInfo();
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  bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
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                                          &WebAssembly::EXNREFRegClass;
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  if (Cond[0].getImm()) {
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    if (IsBrOnExn) {
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      const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception");
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      BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
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          .addMBB(TBB)
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          .addExternalSymbol(CPPExnSymbol)
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          .add(Cond[1]);
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    } else
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      BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
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  } else {
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    assert(!IsBrOnExn && "br_on_exn does not have a reversed condition");
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    BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
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  }
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  if (!FBB)
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    return 1;
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  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
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  return 2;
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}
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bool WebAssemblyInstrInfo::reverseBranchCondition(
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    SmallVectorImpl<MachineOperand> &Cond) const {
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  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
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  // br_on_exn's condition cannot be reversed
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  MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
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  auto &MRI = MF.getRegInfo();
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  if (Cond[1].isReg() &&
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      MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
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    return true;
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  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
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  return false;
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}