/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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1 | | //===-- X86DisassemblerDecoder.cpp - Disassembler decoder -----------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file is part of the X86 Disassembler. |
11 | | // It contains the implementation of the instruction decoder. |
12 | | // Documentation for the disassembler can be found in X86Disassembler.h. |
13 | | // |
14 | | //===----------------------------------------------------------------------===// |
15 | | |
16 | | #include <cstdarg> /* for va_*() */ |
17 | | #include <cstdio> /* for vsnprintf() */ |
18 | | #include <cstdlib> /* for exit() */ |
19 | | #include <cstring> /* for memset() */ |
20 | | |
21 | | #include "X86DisassemblerDecoder.h" |
22 | | |
23 | | using namespace llvm::X86Disassembler; |
24 | | |
25 | | /// Specifies whether a ModR/M byte is needed and (if so) which |
26 | | /// instruction each possible value of the ModR/M byte corresponds to. Once |
27 | | /// this information is known, we have narrowed down to a single instruction. |
28 | | struct ModRMDecision { |
29 | | uint8_t modrm_type; |
30 | | uint16_t instructionIDs; |
31 | | }; |
32 | | |
33 | | /// Specifies which set of ModR/M->instruction tables to look at |
34 | | /// given a particular opcode. |
35 | | struct OpcodeDecision { |
36 | | ModRMDecision modRMDecisions[256]; |
37 | | }; |
38 | | |
39 | | /// Specifies which opcode->instruction tables to look at given |
40 | | /// a particular context (set of attributes). Since there are many possible |
41 | | /// contexts, the decoder first uses CONTEXTS_SYM to determine which context |
42 | | /// applies given a specific set of attributes. Hence there are only IC_max |
43 | | /// entries in this table, rather than 2^(ATTR_max). |
44 | | struct ContextDecision { |
45 | | OpcodeDecision opcodeDecisions[IC_max]; |
46 | | }; |
47 | | |
48 | | #include "X86GenDisassemblerTables.inc" |
49 | | |
50 | | #ifndef NDEBUG |
51 | | #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0) |
52 | | #else |
53 | 0 | #define debug(s) do { } while (0) |
54 | | #endif |
55 | | |
56 | | /* |
57 | | * contextForAttrs - Client for the instruction context table. Takes a set of |
58 | | * attributes and returns the appropriate decode context. |
59 | | * |
60 | | * @param attrMask - Attributes, from the enumeration attributeBits. |
61 | | * @return - The InstructionContext to use when looking up an |
62 | | * an instruction with these attributes. |
63 | | */ |
64 | 515k | static InstructionContext contextForAttrs(uint16_t attrMask) { |
65 | 515k | return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]); |
66 | 515k | } |
67 | | |
68 | | /* |
69 | | * modRMRequired - Reads the appropriate instruction table to determine whether |
70 | | * the ModR/M byte is required to decode a particular instruction. |
71 | | * |
72 | | * @param type - The opcode type (i.e., how many bytes it has). |
73 | | * @param insnContext - The context for the instruction, as returned by |
74 | | * contextForAttrs. |
75 | | * @param opcode - The last byte of the instruction's opcode, not counting |
76 | | * ModR/M extensions and escapes. |
77 | | * @return - true if the ModR/M byte is required, false otherwise. |
78 | | */ |
79 | | static int modRMRequired(OpcodeType type, |
80 | | InstructionContext insnContext, |
81 | 515k | uint16_t opcode) { |
82 | 515k | const struct ContextDecision* decision = nullptr; |
83 | 515k | |
84 | 515k | switch (type) { |
85 | 515k | case ONEBYTE: |
86 | 477k | decision = &ONEBYTE_SYM; |
87 | 477k | break; |
88 | 515k | case TWOBYTE: |
89 | 37.3k | decision = &TWOBYTE_SYM; |
90 | 37.3k | break; |
91 | 515k | case THREEBYTE_38: |
92 | 347 | decision = &THREEBYTE38_SYM; |
93 | 347 | break; |
94 | 515k | case THREEBYTE_3A: |
95 | 155 | decision = &THREEBYTE3A_SYM; |
96 | 155 | break; |
97 | 515k | case XOP8_MAP: |
98 | 16 | decision = &XOP8_MAP_SYM; |
99 | 16 | break; |
100 | 515k | case XOP9_MAP: |
101 | 12 | decision = &XOP9_MAP_SYM; |
102 | 12 | break; |
103 | 515k | case XOPA_MAP: |
104 | 11 | decision = &XOPA_MAP_SYM; |
105 | 11 | break; |
106 | 515k | } |
107 | 515k | |
108 | 515k | return decision->opcodeDecisions[insnContext].modRMDecisions[opcode]. |
109 | 515k | modrm_type != MODRM_ONEENTRY; |
110 | 515k | } |
111 | | |
112 | | /* |
113 | | * decode - Reads the appropriate instruction table to obtain the unique ID of |
114 | | * an instruction. |
115 | | * |
116 | | * @param type - See modRMRequired(). |
117 | | * @param insnContext - See modRMRequired(). |
118 | | * @param opcode - See modRMRequired(). |
119 | | * @param modRM - The ModR/M byte if required, or any value if not. |
120 | | * @return - The UID of the instruction, or 0 on failure. |
121 | | */ |
122 | | static InstrUID decode(OpcodeType type, |
123 | | InstructionContext insnContext, |
124 | | uint8_t opcode, |
125 | 515k | uint8_t modRM) { |
126 | 515k | const struct ModRMDecision* dec = nullptr; |
127 | 515k | |
128 | 515k | switch (type) { |
129 | 515k | case ONEBYTE: |
130 | 477k | dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
131 | 477k | break; |
132 | 515k | case TWOBYTE: |
133 | 37.3k | dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
134 | 37.3k | break; |
135 | 515k | case THREEBYTE_38: |
136 | 347 | dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
137 | 347 | break; |
138 | 515k | case THREEBYTE_3A: |
139 | 155 | dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
140 | 155 | break; |
141 | 515k | case XOP8_MAP: |
142 | 16 | dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
143 | 16 | break; |
144 | 515k | case XOP9_MAP: |
145 | 12 | dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
146 | 12 | break; |
147 | 515k | case XOPA_MAP: |
148 | 11 | dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; |
149 | 11 | break; |
150 | 515k | } |
151 | 515k | |
152 | 515k | switch (dec->modrm_type) { |
153 | 515k | default: |
154 | 0 | debug("Corrupt table! Unknown modrm_type"); |
155 | 0 | return 0; |
156 | 515k | case MODRM_ONEENTRY: |
157 | 197k | return modRMTable[dec->instructionIDs]; |
158 | 515k | case MODRM_SPLITRM: |
159 | 238k | if (modFromModRM(modRM) == 0x3) |
160 | 115k | return modRMTable[dec->instructionIDs+1]; |
161 | 123k | return modRMTable[dec->instructionIDs]; |
162 | 123k | case MODRM_SPLITREG: |
163 | 57.9k | if (modFromModRM(modRM) == 0x3) |
164 | 42.9k | return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8]; |
165 | 14.9k | return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; |
166 | 21.0k | case MODRM_SPLITMISC: |
167 | 21.0k | if (modFromModRM(modRM) == 0x3) |
168 | 732 | return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8]; |
169 | 20.2k | return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; |
170 | 20.2k | case MODRM_FULL: |
171 | 0 | return modRMTable[dec->instructionIDs+modRM]; |
172 | 0 | } |
173 | 0 | } |
174 | | |
175 | | /* |
176 | | * specifierForUID - Given a UID, returns the name and operand specification for |
177 | | * that instruction. |
178 | | * |
179 | | * @param uid - The unique ID for the instruction. This should be returned by |
180 | | * decode(); specifierForUID will not check bounds. |
181 | | * @return - A pointer to the specification for that instruction. |
182 | | */ |
183 | 515k | static const struct InstructionSpecifier *specifierForUID(InstrUID uid) { |
184 | 515k | return &INSTRUCTIONS_SYM[uid]; |
185 | 515k | } |
186 | | |
187 | | /* |
188 | | * consumeByte - Uses the reader function provided by the user to consume one |
189 | | * byte from the instruction's memory and advance the cursor. |
190 | | * |
191 | | * @param insn - The instruction with the reader function to use. The cursor |
192 | | * for this instruction is advanced. |
193 | | * @param byte - A pointer to a pre-allocated memory buffer to be populated |
194 | | * with the data read. |
195 | | * @return - 0 if the read was successful; nonzero otherwise. |
196 | | */ |
197 | 1.54M | static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { |
198 | 1.54M | int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); |
199 | 1.54M | |
200 | 1.54M | if (!ret) |
201 | 1.54M | ++(insn->readerCursor); |
202 | 1.54M | |
203 | 1.54M | return ret; |
204 | 1.54M | } |
205 | | |
206 | | /* |
207 | | * lookAtByte - Like consumeByte, but does not advance the cursor. |
208 | | * |
209 | | * @param insn - See consumeByte(). |
210 | | * @param byte - See consumeByte(). |
211 | | * @return - See consumeByte(). |
212 | | */ |
213 | 252k | static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { |
214 | 252k | return insn->reader(insn->readerArg, byte, insn->readerCursor); |
215 | 252k | } |
216 | | |
217 | 278k | static void unconsumeByte(struct InternalInstruction* insn) { |
218 | 278k | insn->readerCursor--; |
219 | 278k | } |
220 | | |
221 | | #define CONSUME_FUNC(name, type) \ |
222 | 220k | static int name(struct InternalInstruction* insn, type* ptr) { \ |
223 | 220k | type combined = 0; \ |
224 | 220k | unsigned offset; \ |
225 | 882k | for (offset = 0; offset < sizeof(type); ++offset662k ) { \ |
226 | 662k | uint8_t byte; \ |
227 | 662k | int ret = insn->reader(insn->readerArg, \ |
228 | 662k | &byte, \ |
229 | 662k | insn->readerCursor + offset); \ |
230 | 662k | if (ret) \ |
231 | 662k | return ret3 ; \ |
232 | 662k | combined = combined | ((uint64_t)byte << (offset * 8)); \ |
233 | 662k | } \ |
234 | 220k | *ptr = combined; \ |
235 | 220k | insn->readerCursor += sizeof(type); \ |
236 | 220k | return 0; \ |
237 | 220k | } X86DisassemblerDecoder.cpp:consumeInt8(llvm::X86Disassembler::InternalInstruction*, signed char*) Line | Count | Source | 222 | 74.3k | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 74.3k | type combined = 0; \ | 224 | 74.3k | unsigned offset; \ | 225 | 148k | for (offset = 0; offset < sizeof(type); ++offset74.3k ) { \ | 226 | 74.3k | uint8_t byte; \ | 227 | 74.3k | int ret = insn->reader(insn->readerArg, \ | 228 | 74.3k | &byte, \ | 229 | 74.3k | insn->readerCursor + offset); \ | 230 | 74.3k | if (ret) \ | 231 | 74.3k | return ret0 ; \ | 232 | 74.3k | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 74.3k | } \ | 234 | 74.3k | *ptr = combined; \ | 235 | 74.3k | insn->readerCursor += sizeof(type); \ | 236 | 74.3k | return 0; \ | 237 | 74.3k | } |
X86DisassemblerDecoder.cpp:consumeInt16(llvm::X86Disassembler::InternalInstruction*, short*) Line | Count | Source | 222 | 14 | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 14 | type combined = 0; \ | 224 | 14 | unsigned offset; \ | 225 | 42 | for (offset = 0; offset < sizeof(type); ++offset28 ) { \ | 226 | 28 | uint8_t byte; \ | 227 | 28 | int ret = insn->reader(insn->readerArg, \ | 228 | 28 | &byte, \ | 229 | 28 | insn->readerCursor + offset); \ | 230 | 28 | if (ret) \ | 231 | 28 | return ret0 ; \ | 232 | 28 | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 28 | } \ | 234 | 14 | *ptr = combined; \ | 235 | 14 | insn->readerCursor += sizeof(type); \ | 236 | 14 | return 0; \ | 237 | 14 | } |
X86DisassemblerDecoder.cpp:consumeInt32(llvm::X86Disassembler::InternalInstruction*, int*) Line | Count | Source | 222 | 58.3k | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 58.3k | type combined = 0; \ | 224 | 58.3k | unsigned offset; \ | 225 | 291k | for (offset = 0; offset < sizeof(type); ++offset233k ) { \ | 226 | 233k | uint8_t byte; \ | 227 | 233k | int ret = insn->reader(insn->readerArg, \ | 228 | 233k | &byte, \ | 229 | 233k | insn->readerCursor + offset); \ | 230 | 233k | if (ret) \ | 231 | 233k | return ret1 ; \ | 232 | 233k | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 233k | } \ | 234 | 58.3k | *ptr = combined; \ | 235 | 58.3k | insn->readerCursor += sizeof(type); \ | 236 | 58.3k | return 0; \ | 237 | 58.3k | } |
X86DisassemblerDecoder.cpp:consumeUInt16(llvm::X86Disassembler::InternalInstruction*, unsigned short*) Line | Count | Source | 222 | 183 | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 183 | type combined = 0; \ | 224 | 183 | unsigned offset; \ | 225 | 549 | for (offset = 0; offset < sizeof(type); ++offset366 ) { \ | 226 | 366 | uint8_t byte; \ | 227 | 366 | int ret = insn->reader(insn->readerArg, \ | 228 | 366 | &byte, \ | 229 | 366 | insn->readerCursor + offset); \ | 230 | 366 | if (ret) \ | 231 | 366 | return ret0 ; \ | 232 | 366 | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 366 | } \ | 234 | 183 | *ptr = combined; \ | 235 | 183 | insn->readerCursor += sizeof(type); \ | 236 | 183 | return 0; \ | 237 | 183 | } |
X86DisassemblerDecoder.cpp:consumeUInt32(llvm::X86Disassembler::InternalInstruction*, unsigned int*) Line | Count | Source | 222 | 86.1k | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 86.1k | type combined = 0; \ | 224 | 86.1k | unsigned offset; \ | 225 | 430k | for (offset = 0; offset < sizeof(type); ++offset344k ) { \ | 226 | 344k | uint8_t byte; \ | 227 | 344k | int ret = insn->reader(insn->readerArg, \ | 228 | 344k | &byte, \ | 229 | 344k | insn->readerCursor + offset); \ | 230 | 344k | if (ret) \ | 231 | 344k | return ret2 ; \ | 232 | 344k | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 344k | } \ | 234 | 86.1k | *ptr = combined; \ | 235 | 86.1k | insn->readerCursor += sizeof(type); \ | 236 | 86.1k | return 0; \ | 237 | 86.1k | } |
X86DisassemblerDecoder.cpp:consumeUInt64(llvm::X86Disassembler::InternalInstruction*, unsigned long long*) Line | Count | Source | 222 | 1.19k | static int name(struct InternalInstruction* insn, type* ptr) { \ | 223 | 1.19k | type combined = 0; \ | 224 | 1.19k | unsigned offset; \ | 225 | 10.7k | for (offset = 0; offset < sizeof(type); ++offset9.54k ) { \ | 226 | 9.54k | uint8_t byte; \ | 227 | 9.54k | int ret = insn->reader(insn->readerArg, \ | 228 | 9.54k | &byte, \ | 229 | 9.54k | insn->readerCursor + offset); \ | 230 | 9.54k | if (ret) \ | 231 | 9.54k | return ret0 ; \ | 232 | 9.54k | combined = combined | ((uint64_t)byte << (offset * 8)); \ | 233 | 9.54k | } \ | 234 | 1.19k | *ptr = combined; \ | 235 | 1.19k | insn->readerCursor += sizeof(type); \ | 236 | 1.19k | return 0; \ | 237 | 1.19k | } |
|
238 | | |
239 | | /* |
240 | | * consume* - Use the reader function provided by the user to consume data |
241 | | * values of various sizes from the instruction's memory and advance the |
242 | | * cursor appropriately. These readers perform endian conversion. |
243 | | * |
244 | | * @param insn - See consumeByte(). |
245 | | * @param ptr - A pointer to a pre-allocated memory of appropriate size to |
246 | | * be populated with the data read. |
247 | | * @return - See consumeByte(). |
248 | | */ |
249 | | CONSUME_FUNC(consumeInt8, int8_t) |
250 | | CONSUME_FUNC(consumeInt16, int16_t) |
251 | | CONSUME_FUNC(consumeInt32, int32_t) |
252 | | CONSUME_FUNC(consumeUInt16, uint16_t) |
253 | | CONSUME_FUNC(consumeUInt32, uint32_t) |
254 | | CONSUME_FUNC(consumeUInt64, uint64_t) |
255 | | |
256 | | /* |
257 | | * dbgprintf - Uses the logging function provided by the user to log a single |
258 | | * message, typically without a carriage-return. |
259 | | * |
260 | | * @param insn - The instruction containing the logging function. |
261 | | * @param format - See printf(). |
262 | | * @param ... - See printf(). |
263 | | */ |
264 | | static void dbgprintf(struct InternalInstruction* insn, |
265 | | const char* format, |
266 | 5.24M | ...) { |
267 | 5.24M | char buffer[256]; |
268 | 5.24M | va_list ap; |
269 | 5.24M | |
270 | 5.24M | if (!insn->dlog) |
271 | 5.24M | return; |
272 | 0 | |
273 | 0 | va_start(ap, format); |
274 | 0 | (void)vsnprintf(buffer, sizeof(buffer), format, ap); |
275 | 0 | va_end(ap); |
276 | 0 |
|
277 | 0 | insn->dlog(insn->dlogArg, buffer); |
278 | 0 | } |
279 | | |
280 | 527k | static bool isREX(struct InternalInstruction *insn, uint8_t prefix) { |
281 | 527k | if (insn->mode == MODE_64BIT) |
282 | 509k | return prefix >= 0x40 && prefix <= 0x4f457k ; |
283 | 18.8k | return false; |
284 | 18.8k | } |
285 | | |
286 | | /* |
287 | | * setPrefixPresent - Marks that a particular prefix is present as mandatory |
288 | | * |
289 | | * @param insn - The instruction to be marked as having the prefix. |
290 | | * @param prefix - The prefix that is present. |
291 | | */ |
292 | 16.9k | static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) { |
293 | 16.9k | uint8_t nextByte; |
294 | 16.9k | switch (prefix) { |
295 | 16.9k | case 0xf2: |
296 | 1.44k | case 0xf3: |
297 | 1.44k | if (lookAtByte(insn, &nextByte)) |
298 | 1 | break; |
299 | 1.44k | // TODO: |
300 | 1.44k | // 1. There could be several 0x66 |
301 | 1.44k | // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then |
302 | 1.44k | // it's not mandatory prefix |
303 | 1.44k | // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need |
304 | 1.44k | // 0x0f exactly after it to be mandatory prefix |
305 | 1.44k | if (isREX(insn, nextByte) || nextByte == 0x0f1.35k || nextByte == 0x66216 ) |
306 | 1.23k | // The last of 0xf2 /0xf3 is mandatory prefix |
307 | 1.23k | insn->mandatoryPrefix = prefix; |
308 | 1.44k | insn->repeatPrefix = prefix; |
309 | 1.44k | break; |
310 | 13.4k | case 0x66: |
311 | 13.4k | if (lookAtByte(insn, &nextByte)) |
312 | 3 | break; |
313 | 13.4k | // 0x66 can't overwrite existing mandatory prefix and should be ignored |
314 | 13.4k | if (!insn->mandatoryPrefix && (13.4k nextByte == 0x0f13.4k || isREX(insn, nextByte)11.1k )) |
315 | 3.55k | insn->mandatoryPrefix = prefix; |
316 | 13.4k | break; |
317 | 16.9k | } |
318 | 16.9k | } |
319 | | |
320 | | /* |
321 | | * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the |
322 | | * instruction as having them. Also sets the instruction's default operand, |
323 | | * address, and other relevant data sizes to report operands correctly. |
324 | | * |
325 | | * @param insn - The instruction whose prefixes are to be read. |
326 | | * @return - 0 if the instruction could be read until the end of the prefix |
327 | | * bytes, and no prefixes conflicted; nonzero otherwise. |
328 | | */ |
329 | 514k | static int readPrefixes(struct InternalInstruction* insn) { |
330 | 514k | bool isPrefix = true; |
331 | 514k | uint8_t byte = 0; |
332 | 514k | uint8_t nextByte; |
333 | 514k | |
334 | 514k | dbgprintf(insn, "readPrefixes()"); |
335 | 514k | |
336 | 1.04M | while (isPrefix) { |
337 | 531k | /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */ |
338 | 531k | if (consumeByte(insn, &byte)) |
339 | 4 | break; |
340 | 531k | |
341 | 531k | /* |
342 | 531k | * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then |
343 | 531k | * break and let it be disassembled as a normal "instruction". |
344 | 531k | */ |
345 | 531k | if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0514k ) // LOCK |
346 | 289 | break; |
347 | 531k | |
348 | 531k | if ((byte == 0xf2 || byte == 0xf3530k ) && !lookAtByte(insn, &nextByte)1.45k ) { |
349 | 1.44k | /* |
350 | 1.44k | * If the byte is 0xf2 or 0xf3, and any of the following conditions are |
351 | 1.44k | * met: |
352 | 1.44k | * - it is followed by a LOCK (0xf0) prefix |
353 | 1.44k | * - it is followed by an xchg instruction |
354 | 1.44k | * then it should be disassembled as a xacquire/xrelease not repne/rep. |
355 | 1.44k | */ |
356 | 1.44k | if (((nextByte == 0xf0) || |
357 | 1.44k | (1.44k (nextByte & 0xfe) == 0x861.44k || (nextByte & 0xf8) == 0x901.44k ))) { |
358 | 123 | insn->xAcquireRelease = true; |
359 | 123 | if (!(byte == 0xf3 && nextByte == 0x90121 )) // PAUSE instruction support |
360 | 5 | break; |
361 | 1.44k | } |
362 | 1.44k | /* |
363 | 1.44k | * Also if the byte is 0xf3, and the following condition is met: |
364 | 1.44k | * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or |
365 | 1.44k | * "mov mem, imm" (opcode 0xc6/0xc7) instructions. |
366 | 1.44k | * then it should be disassembled as an xrelease not rep. |
367 | 1.44k | */ |
368 | 1.44k | if (byte == 0xf3 && (894 nextByte == 0x88894 || nextByte == 0x89893 || |
369 | 894 | nextByte == 0xc6892 || nextByte == 0xc7891 )) { |
370 | 4 | insn->xAcquireRelease = true; |
371 | 4 | if (nextByte != 0x90) // PAUSE instruction support |
372 | 4 | break; |
373 | 1.44k | } |
374 | 1.44k | if (isREX(insn, nextByte)) { |
375 | 81 | uint8_t nnextByte; |
376 | 81 | // Go to REX prefix after the current one |
377 | 81 | if (consumeByte(insn, &nnextByte)) |
378 | 0 | return -1; |
379 | 81 | // We should be able to read next byte after REX prefix |
380 | 81 | if (lookAtByte(insn, &nnextByte)) |
381 | 0 | return -1; |
382 | 81 | unconsumeByte(insn); |
383 | 81 | } |
384 | 1.44k | } |
385 | 531k | |
386 | 531k | switch (byte) { |
387 | 531k | case 0xf0: /* LOCK */ |
388 | 1.44k | case 0xf2: /* REPNE/REPNZ */ |
389 | 1.44k | case 0xf3: /* REP or REPE/REPZ */ |
390 | 1.44k | setPrefixPresent(insn, byte); |
391 | 1.44k | break; |
392 | 1.93k | case 0x2e: /* CS segment override -OR- Branch not taken */ |
393 | 1.93k | case 0x36: /* SS segment override -OR- Branch taken */ |
394 | 1.93k | case 0x3e: /* DS segment override */ |
395 | 1.93k | case 0x26: /* ES segment override */ |
396 | 1.93k | case 0x64: /* FS segment override */ |
397 | 1.93k | case 0x65: /* GS segment override */ |
398 | 1.93k | switch (byte) { |
399 | 1.93k | case 0x2e: |
400 | 1.79k | insn->segmentOverride = SEG_OVERRIDE_CS; |
401 | 1.79k | break; |
402 | 1.93k | case 0x36: |
403 | 0 | insn->segmentOverride = SEG_OVERRIDE_SS; |
404 | 0 | break; |
405 | 1.93k | case 0x3e: |
406 | 1 | insn->segmentOverride = SEG_OVERRIDE_DS; |
407 | 1 | break; |
408 | 1.93k | case 0x26: |
409 | 9 | insn->segmentOverride = SEG_OVERRIDE_ES; |
410 | 9 | break; |
411 | 1.93k | case 0x64: |
412 | 76 | insn->segmentOverride = SEG_OVERRIDE_FS; |
413 | 76 | break; |
414 | 1.93k | case 0x65: |
415 | 57 | insn->segmentOverride = SEG_OVERRIDE_GS; |
416 | 57 | break; |
417 | 1.93k | default: |
418 | 0 | debug("Unhandled override"); |
419 | 0 | return -1; |
420 | 1.93k | } |
421 | 1.93k | setPrefixPresent(insn, byte); |
422 | 1.93k | break; |
423 | 13.4k | case 0x66: /* Operand-size override */ |
424 | 13.4k | insn->hasOpSize = true; |
425 | 13.4k | setPrefixPresent(insn, byte); |
426 | 13.4k | break; |
427 | 1.93k | case 0x67: /* Address-size override */ |
428 | 87 | insn->hasAdSize = true; |
429 | 87 | setPrefixPresent(insn, byte); |
430 | 87 | break; |
431 | 514k | default: /* Not a prefix byte */ |
432 | 514k | isPrefix = false; |
433 | 514k | break; |
434 | 531k | } |
435 | 531k | |
436 | 531k | if (isPrefix) |
437 | 16.9k | dbgprintf(insn, "Found prefix 0x%hhx", byte); |
438 | 531k | } |
439 | 514k | |
440 | 514k | insn->vectorExtensionType = TYPE_NO_VEX_XOP; |
441 | 514k | |
442 | 514k | if (byte == 0x62) { |
443 | 335 | uint8_t byte1, byte2; |
444 | 335 | |
445 | 335 | if (consumeByte(insn, &byte1)) { |
446 | 0 | dbgprintf(insn, "Couldn't read second byte of EVEX prefix"); |
447 | 0 | return -1; |
448 | 0 | } |
449 | 335 | |
450 | 335 | if (lookAtByte(insn, &byte2)) { |
451 | 0 | dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); |
452 | 0 | return -1; |
453 | 0 | } |
454 | 335 | |
455 | 335 | if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc02 ) && |
456 | 335 | ((~byte1 & 0xc) == 0xc)333 && ((byte2 & 0x4) == 0x4)332 ) { |
457 | 331 | insn->vectorExtensionType = TYPE_EVEX; |
458 | 331 | } else { |
459 | 4 | unconsumeByte(insn); /* unconsume byte1 */ |
460 | 4 | unconsumeByte(insn); /* unconsume byte */ |
461 | 4 | } |
462 | 335 | |
463 | 335 | if (insn->vectorExtensionType == TYPE_EVEX) { |
464 | 331 | insn->vectorExtensionPrefix[0] = byte; |
465 | 331 | insn->vectorExtensionPrefix[1] = byte1; |
466 | 331 | if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) { |
467 | 0 | dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); |
468 | 0 | return -1; |
469 | 0 | } |
470 | 331 | if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) { |
471 | 0 | dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix"); |
472 | 0 | return -1; |
473 | 0 | } |
474 | 331 | |
475 | 331 | /* We simulate the REX prefix for simplicity's sake */ |
476 | 331 | if (insn->mode == MODE_64BIT) { |
477 | 331 | insn->rexPrefix = 0x40 |
478 | 331 | | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) |
479 | 331 | | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) |
480 | 331 | | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) |
481 | 331 | | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); |
482 | 331 | } |
483 | 331 | |
484 | 331 | dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx", |
485 | 331 | insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], |
486 | 331 | insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]); |
487 | 331 | } |
488 | 514k | } else if (byte == 0xc4) { |
489 | 227 | uint8_t byte1; |
490 | 227 | |
491 | 227 | if (lookAtByte(insn, &byte1)) { |
492 | 0 | dbgprintf(insn, "Couldn't read second byte of VEX"); |
493 | 0 | return -1; |
494 | 0 | } |
495 | 227 | |
496 | 227 | if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc067 ) |
497 | 225 | insn->vectorExtensionType = TYPE_VEX_3B; |
498 | 2 | else |
499 | 2 | unconsumeByte(insn); |
500 | 227 | |
501 | 227 | if (insn->vectorExtensionType == TYPE_VEX_3B) { |
502 | 225 | insn->vectorExtensionPrefix[0] = byte; |
503 | 225 | consumeByte(insn, &insn->vectorExtensionPrefix[1]); |
504 | 225 | consumeByte(insn, &insn->vectorExtensionPrefix[2]); |
505 | 225 | |
506 | 225 | /* We simulate the REX prefix for simplicity's sake */ |
507 | 225 | |
508 | 225 | if (insn->mode == MODE_64BIT) |
509 | 160 | insn->rexPrefix = 0x40 |
510 | 160 | | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) |
511 | 160 | | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) |
512 | 160 | | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) |
513 | 160 | | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); |
514 | 225 | |
515 | 225 | dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", |
516 | 225 | insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], |
517 | 225 | insn->vectorExtensionPrefix[2]); |
518 | 225 | } |
519 | 514k | } else if (byte == 0xc5) { |
520 | 292 | uint8_t byte1; |
521 | 292 | |
522 | 292 | if (lookAtByte(insn, &byte1)) { |
523 | 0 | dbgprintf(insn, "Couldn't read second byte of VEX"); |
524 | 0 | return -1; |
525 | 0 | } |
526 | 292 | |
527 | 292 | if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc034 ) |
528 | 292 | insn->vectorExtensionType = TYPE_VEX_2B; |
529 | 0 | else |
530 | 0 | unconsumeByte(insn); |
531 | 292 | |
532 | 292 | if (insn->vectorExtensionType == TYPE_VEX_2B) { |
533 | 292 | insn->vectorExtensionPrefix[0] = byte; |
534 | 292 | consumeByte(insn, &insn->vectorExtensionPrefix[1]); |
535 | 292 | |
536 | 292 | if (insn->mode == MODE_64BIT) |
537 | 258 | insn->rexPrefix = 0x40 |
538 | 258 | | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); |
539 | 292 | |
540 | 292 | switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { |
541 | 292 | default: |
542 | 182 | break; |
543 | 292 | case VEX_PREFIX_66: |
544 | 110 | insn->hasOpSize = true; |
545 | 110 | break; |
546 | 292 | } |
547 | 292 | |
548 | 292 | dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", |
549 | 292 | insn->vectorExtensionPrefix[0], |
550 | 292 | insn->vectorExtensionPrefix[1]); |
551 | 292 | } |
552 | 514k | } else if (byte == 0x8f) { |
553 | 41 | uint8_t byte1; |
554 | 41 | |
555 | 41 | if (lookAtByte(insn, &byte1)) { |
556 | 0 | dbgprintf(insn, "Couldn't read second byte of XOP"); |
557 | 0 | return -1; |
558 | 0 | } |
559 | 41 | |
560 | 41 | if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */ |
561 | 41 | insn->vectorExtensionType = TYPE_XOP; |
562 | 0 | else |
563 | 0 | unconsumeByte(insn); |
564 | 41 | |
565 | 41 | if (insn->vectorExtensionType == TYPE_XOP) { |
566 | 41 | insn->vectorExtensionPrefix[0] = byte; |
567 | 41 | consumeByte(insn, &insn->vectorExtensionPrefix[1]); |
568 | 41 | consumeByte(insn, &insn->vectorExtensionPrefix[2]); |
569 | 41 | |
570 | 41 | /* We simulate the REX prefix for simplicity's sake */ |
571 | 41 | |
572 | 41 | if (insn->mode == MODE_64BIT) |
573 | 35 | insn->rexPrefix = 0x40 |
574 | 35 | | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) |
575 | 35 | | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) |
576 | 35 | | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) |
577 | 35 | | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); |
578 | 41 | |
579 | 41 | switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { |
580 | 41 | default: |
581 | 41 | break; |
582 | 41 | case VEX_PREFIX_66: |
583 | 0 | insn->hasOpSize = true; |
584 | 0 | break; |
585 | 41 | } |
586 | 41 | |
587 | 41 | dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx", |
588 | 41 | insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], |
589 | 41 | insn->vectorExtensionPrefix[2]); |
590 | 41 | } |
591 | 513k | } else if (isREX(insn, byte)) { |
592 | 235k | if (lookAtByte(insn, &nextByte)) |
593 | 0 | return -1; |
594 | 235k | insn->rexPrefix = byte; |
595 | 235k | dbgprintf(insn, "Found REX prefix 0x%hhx", byte); |
596 | 235k | } else |
597 | 278k | unconsumeByte(insn); |
598 | 514k | |
599 | 514k | if (insn->mode == MODE_16BIT) { |
600 | 363 | insn->registerSize = (insn->hasOpSize ? 4103 : 2260 ); |
601 | 363 | insn->addressSize = (insn->hasAdSize ? 436 : 2327 ); |
602 | 363 | insn->displacementSize = (insn->hasAdSize ? 436 : 2327 ); |
603 | 363 | insn->immediateSize = (insn->hasOpSize ? 4103 : 2260 ); |
604 | 514k | } else if (insn->mode == MODE_32BIT) { |
605 | 18.3k | insn->registerSize = (insn->hasOpSize ? 2128 : 418.1k ); |
606 | 18.3k | insn->addressSize = (insn->hasAdSize ? 216 : 418.2k ); |
607 | 18.3k | insn->displacementSize = (insn->hasAdSize ? 216 : 418.2k ); |
608 | 18.3k | insn->immediateSize = (insn->hasOpSize ? 2128 : 418.1k ); |
609 | 496k | } else if (insn->mode == MODE_64BIT) { |
610 | 496k | if (insn->rexPrefix && wFromREX235k (insn->rexPrefix)) { |
611 | 190k | insn->registerSize = 8; |
612 | 190k | insn->addressSize = (insn->hasAdSize ? 47 : 8190k ); |
613 | 190k | insn->displacementSize = 4; |
614 | 190k | insn->immediateSize = 4; |
615 | 305k | } else { |
616 | 305k | insn->registerSize = (insn->hasOpSize ? 27.39k : 4297k ); |
617 | 305k | insn->addressSize = (insn->hasAdSize ? 428 : 8305k ); |
618 | 305k | insn->displacementSize = (insn->hasOpSize ? 27.39k : 4297k ); |
619 | 305k | insn->immediateSize = (insn->hasOpSize ? 27.39k : 4297k ); |
620 | 305k | } |
621 | 496k | } |
622 | 514k | |
623 | 514k | return 0; |
624 | 514k | } |
625 | | |
626 | | /* |
627 | | * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of |
628 | | * extended or escape opcodes). |
629 | | * |
630 | | * @param insn - The instruction whose opcode is to be read. |
631 | | * @return - 0 if the opcode could be read successfully; nonzero otherwise. |
632 | | */ |
633 | 514k | static int readOpcode(struct InternalInstruction* insn) { |
634 | 514k | /* Determine the length of the primary opcode */ |
635 | 514k | |
636 | 514k | uint8_t current; |
637 | 514k | |
638 | 514k | dbgprintf(insn, "readOpcode()"); |
639 | 514k | |
640 | 514k | insn->opcodeType = ONEBYTE; |
641 | 514k | |
642 | 514k | if (insn->vectorExtensionType == TYPE_EVEX) { |
643 | 331 | switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { |
644 | 331 | default: |
645 | 2 | dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)", |
646 | 2 | mmFromEVEX2of4(insn->vectorExtensionPrefix[1])); |
647 | 2 | return -1; |
648 | 331 | case VEX_LOB_0F: |
649 | 126 | insn->opcodeType = TWOBYTE; |
650 | 126 | return consumeByte(insn, &insn->opcode); |
651 | 331 | case VEX_LOB_0F38: |
652 | 167 | insn->opcodeType = THREEBYTE_38; |
653 | 167 | return consumeByte(insn, &insn->opcode); |
654 | 331 | case VEX_LOB_0F3A: |
655 | 36 | insn->opcodeType = THREEBYTE_3A; |
656 | 36 | return consumeByte(insn, &insn->opcode); |
657 | 514k | } |
658 | 514k | } else if (insn->vectorExtensionType == TYPE_VEX_3B) { |
659 | 225 | switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { |
660 | 225 | default: |
661 | 0 | dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", |
662 | 0 | mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); |
663 | 0 | return -1; |
664 | 225 | case VEX_LOB_0F: |
665 | 21 | insn->opcodeType = TWOBYTE; |
666 | 21 | return consumeByte(insn, &insn->opcode); |
667 | 225 | case VEX_LOB_0F38: |
668 | 123 | insn->opcodeType = THREEBYTE_38; |
669 | 123 | return consumeByte(insn, &insn->opcode); |
670 | 225 | case VEX_LOB_0F3A: |
671 | 81 | insn->opcodeType = THREEBYTE_3A; |
672 | 81 | return consumeByte(insn, &insn->opcode); |
673 | 514k | } |
674 | 514k | } else if (insn->vectorExtensionType == TYPE_VEX_2B) { |
675 | 292 | insn->opcodeType = TWOBYTE; |
676 | 292 | return consumeByte(insn, &insn->opcode); |
677 | 514k | } else if (insn->vectorExtensionType == TYPE_XOP) { |
678 | 41 | switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { |
679 | 41 | default: |
680 | 2 | dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", |
681 | 2 | mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); |
682 | 2 | return -1; |
683 | 41 | case XOP_MAP_SELECT_8: |
684 | 16 | insn->opcodeType = XOP8_MAP; |
685 | 16 | return consumeByte(insn, &insn->opcode); |
686 | 41 | case XOP_MAP_SELECT_9: |
687 | 12 | insn->opcodeType = XOP9_MAP; |
688 | 12 | return consumeByte(insn, &insn->opcode); |
689 | 41 | case XOP_MAP_SELECT_A: |
690 | 11 | insn->opcodeType = XOPA_MAP; |
691 | 11 | return consumeByte(insn, &insn->opcode); |
692 | 513k | } |
693 | 513k | } |
694 | 513k | |
695 | 513k | if (consumeByte(insn, ¤t)) |
696 | 0 | return -1; |
697 | 513k | |
698 | 513k | if (current == 0x0f) { |
699 | 36.8k | dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); |
700 | 36.8k | |
701 | 36.8k | if (consumeByte(insn, ¤t)) |
702 | 0 | return -1; |
703 | 36.8k | |
704 | 36.8k | if (current == 0x38) { |
705 | 49 | dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); |
706 | 49 | |
707 | 49 | if (consumeByte(insn, ¤t)) |
708 | 0 | return -1; |
709 | 49 | |
710 | 49 | insn->opcodeType = THREEBYTE_38; |
711 | 36.7k | } else if (current == 0x3a) { |
712 | 36 | dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); |
713 | 36 | |
714 | 36 | if (consumeByte(insn, ¤t)) |
715 | 0 | return -1; |
716 | 36 | |
717 | 36 | insn->opcodeType = THREEBYTE_3A; |
718 | 36.7k | } else { |
719 | 36.7k | dbgprintf(insn, "Didn't find a three-byte escape prefix"); |
720 | 36.7k | |
721 | 36.7k | insn->opcodeType = TWOBYTE; |
722 | 36.7k | } |
723 | 477k | } else if (insn->mandatoryPrefix) |
724 | 777 | // The opcode with mandatory prefix must start with opcode escape. |
725 | 777 | // If not it's legacy repeat prefix |
726 | 777 | insn->mandatoryPrefix = 0; |
727 | 513k | |
728 | 513k | /* |
729 | 513k | * At this point we have consumed the full opcode. |
730 | 513k | * Anything we consume from here on must be unconsumed. |
731 | 513k | */ |
732 | 513k | |
733 | 513k | insn->opcode = current; |
734 | 513k | |
735 | 513k | return 0; |
736 | 513k | } |
737 | | |
738 | | static int readModRM(struct InternalInstruction* insn); |
739 | | |
740 | | /* |
741 | | * getIDWithAttrMask - Determines the ID of an instruction, consuming |
742 | | * the ModR/M byte as appropriate for extended and escape opcodes, |
743 | | * and using a supplied attribute mask. |
744 | | * |
745 | | * @param instructionID - A pointer whose target is filled in with the ID of the |
746 | | * instruction. |
747 | | * @param insn - The instruction whose ID is to be determined. |
748 | | * @param attrMask - The attribute mask to search. |
749 | | * @return - 0 if the ModR/M could be read when needed or was not |
750 | | * needed; nonzero otherwise. |
751 | | */ |
752 | | static int getIDWithAttrMask(uint16_t* instructionID, |
753 | | struct InternalInstruction* insn, |
754 | 515k | uint16_t attrMask) { |
755 | 515k | bool hasModRMExtension; |
756 | 515k | |
757 | 515k | InstructionContext instructionClass = contextForAttrs(attrMask); |
758 | 515k | |
759 | 515k | hasModRMExtension = modRMRequired(insn->opcodeType, |
760 | 515k | instructionClass, |
761 | 515k | insn->opcode); |
762 | 515k | |
763 | 515k | if (hasModRMExtension) { |
764 | 317k | if (readModRM(insn)) |
765 | 12 | return -1; |
766 | 317k | |
767 | 317k | *instructionID = decode(insn->opcodeType, |
768 | 317k | instructionClass, |
769 | 317k | insn->opcode, |
770 | 317k | insn->modRM); |
771 | 317k | } else { |
772 | 197k | *instructionID = decode(insn->opcodeType, |
773 | 197k | instructionClass, |
774 | 197k | insn->opcode, |
775 | 197k | 0); |
776 | 197k | } |
777 | 515k | |
778 | 515k | return 0515k ; |
779 | 515k | } |
780 | | |
781 | | /* |
782 | | * is16BitEquivalent - Determines whether two instruction names refer to |
783 | | * equivalent instructions but one is 16-bit whereas the other is not. |
784 | | * |
785 | | * @param orig - The instruction that is not 16-bit |
786 | | * @param equiv - The instruction that is 16-bit |
787 | | */ |
788 | 373 | static bool is16BitEquivalent(const char *orig, const char *equiv) { |
789 | 373 | off_t i; |
790 | 373 | |
791 | 2.83k | for (i = 0;; i++2.45k ) { |
792 | 2.83k | if (orig[i] == '\0' && equiv[i] == '\0'345 ) |
793 | 345 | return true; |
794 | 2.48k | if (orig[i] == '\0' || equiv[i] == '\0') |
795 | 0 | return false; |
796 | 2.48k | if (orig[i] != equiv[i]) { |
797 | 475 | if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W'21 ) |
798 | 21 | continue; |
799 | 454 | if ((orig[i] == '6' || orig[i] == '3'452 ) && equiv[i] == '1'215 ) |
800 | 213 | continue; |
801 | 241 | if ((orig[i] == '4' || orig[i] == '2'222 ) && equiv[i] == '6'232 ) |
802 | 213 | continue; |
803 | 28 | return false; |
804 | 28 | } |
805 | 2.48k | } |
806 | 373 | } |
807 | | |
808 | | /* |
809 | | * is64Bit - Determines whether this instruction is a 64-bit instruction. |
810 | | * |
811 | | * @param name - The instruction that is not 16-bit |
812 | | */ |
813 | 9 | static bool is64Bit(const char *name) { |
814 | 9 | off_t i; |
815 | 9 | |
816 | 52 | for (i = 0;; ++i43 ) { |
817 | 52 | if (name[i] == '\0') |
818 | 4 | return false; |
819 | 48 | if (name[i] == '6' && name[i+1] == '4'5 ) |
820 | 5 | return true; |
821 | 48 | } |
822 | 9 | } |
823 | | |
824 | | /* |
825 | | * getID - Determines the ID of an instruction, consuming the ModR/M byte as |
826 | | * appropriate for extended and escape opcodes. Determines the attributes and |
827 | | * context for the instruction before doing so. |
828 | | * |
829 | | * @param insn - The instruction whose ID is to be determined. |
830 | | * @return - 0 if the ModR/M could be read when needed or was not needed; |
831 | | * nonzero otherwise. |
832 | | */ |
833 | 514k | static int getID(struct InternalInstruction* insn, const void *miiArg) { |
834 | 514k | uint16_t attrMask; |
835 | 514k | uint16_t instructionID; |
836 | 514k | |
837 | 514k | dbgprintf(insn, "getID()"); |
838 | 514k | |
839 | 514k | attrMask = ATTR_NONE; |
840 | 514k | |
841 | 514k | if (insn->mode == MODE_64BIT) |
842 | 496k | attrMask |= ATTR_64BIT; |
843 | 514k | |
844 | 514k | if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { |
845 | 885 | attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX329 : ATTR_VEX556 ; |
846 | 885 | |
847 | 885 | if (insn->vectorExtensionType == TYPE_EVEX) { |
848 | 329 | switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { |
849 | 329 | case VEX_PREFIX_66: |
850 | 240 | attrMask |= ATTR_OPSIZE; |
851 | 240 | break; |
852 | 329 | case VEX_PREFIX_F3: |
853 | 42 | attrMask |= ATTR_XS; |
854 | 42 | break; |
855 | 329 | case VEX_PREFIX_F2: |
856 | 12 | attrMask |= ATTR_XD; |
857 | 12 | break; |
858 | 329 | } |
859 | 329 | |
860 | 329 | if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) |
861 | 329 | attrMask |= ATTR_EVEXKZ10 ; |
862 | 329 | if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) |
863 | 329 | attrMask |= ATTR_EVEXB82 ; |
864 | 329 | if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) |
865 | 329 | attrMask |= ATTR_EVEXK126 ; |
866 | 329 | if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) |
867 | 329 | attrMask |= ATTR_EVEXL92 ; |
868 | 329 | if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) |
869 | 329 | attrMask |= ATTR_EVEXL2146 ; |
870 | 556 | } else if (insn->vectorExtensionType == TYPE_VEX_3B) { |
871 | 225 | switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { |
872 | 225 | case VEX_PREFIX_66: |
873 | 146 | attrMask |= ATTR_OPSIZE; |
874 | 146 | break; |
875 | 225 | case VEX_PREFIX_F3: |
876 | 12 | attrMask |= ATTR_XS; |
877 | 12 | break; |
878 | 225 | case VEX_PREFIX_F2: |
879 | 35 | attrMask |= ATTR_XD; |
880 | 35 | break; |
881 | 225 | } |
882 | 225 | |
883 | 225 | if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) |
884 | 225 | attrMask |= ATTR_VEXL64 ; |
885 | 331 | } else if (insn->vectorExtensionType == TYPE_VEX_2B) { |
886 | 292 | switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { |
887 | 292 | case VEX_PREFIX_66: |
888 | 110 | attrMask |= ATTR_OPSIZE; |
889 | 110 | break; |
890 | 292 | case VEX_PREFIX_F3: |
891 | 27 | attrMask |= ATTR_XS; |
892 | 27 | break; |
893 | 292 | case VEX_PREFIX_F2: |
894 | 81 | attrMask |= ATTR_XD; |
895 | 81 | break; |
896 | 292 | } |
897 | 292 | |
898 | 292 | if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) |
899 | 292 | attrMask |= ATTR_VEXL99 ; |
900 | 292 | } else if (39 insn->vectorExtensionType == TYPE_XOP39 ) { |
901 | 39 | switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { |
902 | 39 | case VEX_PREFIX_66: |
903 | 0 | attrMask |= ATTR_OPSIZE; |
904 | 0 | break; |
905 | 39 | case VEX_PREFIX_F3: |
906 | 0 | attrMask |= ATTR_XS; |
907 | 0 | break; |
908 | 39 | case VEX_PREFIX_F2: |
909 | 0 | attrMask |= ATTR_XD; |
910 | 0 | break; |
911 | 39 | } |
912 | 39 | |
913 | 39 | if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) |
914 | 39 | attrMask |= ATTR_VEXL5 ; |
915 | 39 | } else { |
916 | 0 | return -1; |
917 | 0 | } |
918 | 513k | } else if (!insn->mandatoryPrefix) { |
919 | 509k | // If we don't have mandatory prefix we should use legacy prefixes here |
920 | 509k | if (insn->hasOpSize && (insn->mode != MODE_16BIT)4.92k ) |
921 | 4.86k | attrMask |= ATTR_OPSIZE; |
922 | 509k | if (insn->hasAdSize) |
923 | 81 | attrMask |= ATTR_ADSIZE; |
924 | 509k | if (insn->opcodeType == ONEBYTE) { |
925 | 477k | if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90)172 ) |
926 | 118 | // Special support for PAUSE |
927 | 118 | attrMask |= ATTR_XS; |
928 | 477k | } else { |
929 | 32.8k | if (insn->repeatPrefix == 0xf2) |
930 | 0 | attrMask |= ATTR_XD; |
931 | 32.8k | else if (insn->repeatPrefix == 0xf3) |
932 | 0 | attrMask |= ATTR_XS; |
933 | 32.8k | } |
934 | 509k | } else { |
935 | 4.00k | switch (insn->mandatoryPrefix) { |
936 | 4.00k | case 0xf2: |
937 | 504 | attrMask |= ATTR_XD; |
938 | 504 | break; |
939 | 4.00k | case 0xf3: |
940 | 716 | attrMask |= ATTR_XS; |
941 | 716 | break; |
942 | 4.00k | case 0x66: |
943 | 2.78k | if (insn->mode != MODE_16BIT) |
944 | 2.74k | attrMask |= ATTR_OPSIZE; |
945 | 2.78k | break; |
946 | 4.00k | case 0x67: |
947 | 0 | attrMask |= ATTR_ADSIZE; |
948 | 0 | break; |
949 | 514k | } |
950 | 514k | } |
951 | 514k | |
952 | 514k | if (insn->rexPrefix & 0x08) { |
953 | 190k | attrMask |= ATTR_REXW; |
954 | 190k | attrMask &= ~ATTR_ADSIZE; |
955 | 190k | } |
956 | 514k | |
957 | 514k | /* |
958 | 514k | * JCXZ/JECXZ need special handling for 16-bit mode because the meaning |
959 | 514k | * of the AdSize prefix is inverted w.r.t. 32-bit mode. |
960 | 514k | */ |
961 | 514k | if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE363 && |
962 | 514k | insn->opcode == 0xE3265 ) |
963 | 2 | attrMask ^= ATTR_ADSIZE; |
964 | 514k | |
965 | 514k | /* |
966 | 514k | * In 64-bit mode all f64 superscripted opcodes ignore opcode size prefix |
967 | 514k | * CALL/JMP/JCC instructions need to ignore 0x66 and consume 4 bytes |
968 | 514k | */ |
969 | 514k | |
970 | 514k | if ((insn->mode == MODE_64BIT) && insn->hasOpSize496k ) { |
971 | 7.60k | switch (insn->opcode) { |
972 | 7.60k | case 0xE8: |
973 | 5 | case 0xE9: |
974 | 5 | // Take care of psubsb and other mmx instructions. |
975 | 5 | if (insn->opcodeType == ONEBYTE) { |
976 | 4 | attrMask ^= ATTR_OPSIZE; |
977 | 4 | insn->immediateSize = 4; |
978 | 4 | insn->displacementSize = 4; |
979 | 4 | } |
980 | 5 | break; |
981 | 1.66k | case 0x82: |
982 | 1.66k | case 0x83: |
983 | 1.66k | case 0x84: |
984 | 1.66k | case 0x85: |
985 | 1.66k | case 0x86: |
986 | 1.66k | case 0x87: |
987 | 1.66k | case 0x88: |
988 | 1.66k | case 0x89: |
989 | 1.66k | case 0x8A: |
990 | 1.66k | case 0x8B: |
991 | 1.66k | case 0x8C: |
992 | 1.66k | case 0x8D: |
993 | 1.66k | case 0x8E: |
994 | 1.66k | case 0x8F: |
995 | 1.66k | // Take care of lea and three byte ops. |
996 | 1.66k | if (insn->opcodeType == TWOBYTE) { |
997 | 14 | attrMask ^= ATTR_OPSIZE; |
998 | 14 | insn->immediateSize = 4; |
999 | 14 | insn->displacementSize = 4; |
1000 | 14 | } |
1001 | 1.66k | break; |
1002 | 514k | } |
1003 | 514k | } |
1004 | 514k | |
1005 | 514k | if (getIDWithAttrMask(&instructionID, insn, attrMask)) |
1006 | 12 | return -1; |
1007 | 514k | |
1008 | 514k | /* The following clauses compensate for limitations of the tables. */ |
1009 | 514k | |
1010 | 514k | if (insn->mode != MODE_64BIT && |
1011 | 514k | insn->vectorExtensionType != TYPE_NO_VEX_XOP18.6k ) { |
1012 | 105 | /* |
1013 | 105 | * The tables can't distinquish between cases where the W-bit is used to |
1014 | 105 | * select register size and cases where its a required part of the opcode. |
1015 | 105 | */ |
1016 | 105 | if ((insn->vectorExtensionType == TYPE_EVEX && |
1017 | 105 | wFromEVEX3of40 (insn->vectorExtensionPrefix[2])) || |
1018 | 105 | (insn->vectorExtensionType == TYPE_VEX_3B && |
1019 | 105 | wFromVEX3of365 (insn->vectorExtensionPrefix[2])) || |
1020 | 105 | (96 insn->vectorExtensionType == TYPE_XOP96 && |
1021 | 96 | wFromXOP3of36 (insn->vectorExtensionPrefix[2]))) { |
1022 | 9 | |
1023 | 9 | uint16_t instructionIDWithREXW; |
1024 | 9 | if (getIDWithAttrMask(&instructionIDWithREXW, |
1025 | 9 | insn, attrMask | ATTR_REXW)) { |
1026 | 0 | insn->instructionID = instructionID; |
1027 | 0 | insn->spec = specifierForUID(instructionID); |
1028 | 0 | return 0; |
1029 | 0 | } |
1030 | 9 | |
1031 | 9 | auto SpecName = GetInstrName(instructionIDWithREXW, miiArg); |
1032 | 9 | // If not a 64-bit instruction. Switch the opcode. |
1033 | 9 | if (!is64Bit(SpecName.data())) { |
1034 | 4 | insn->instructionID = instructionIDWithREXW; |
1035 | 4 | insn->spec = specifierForUID(instructionIDWithREXW); |
1036 | 4 | return 0; |
1037 | 4 | } |
1038 | 514k | } |
1039 | 105 | } |
1040 | 514k | |
1041 | 514k | /* |
1042 | 514k | * Absolute moves need special handling. |
1043 | 514k | * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are |
1044 | 514k | * inverted w.r.t. |
1045 | 514k | * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in |
1046 | 514k | * any position. |
1047 | 514k | */ |
1048 | 514k | if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)477k ) { |
1049 | 142 | /* Make sure we observed the prefixes in any position. */ |
1050 | 142 | if (insn->hasAdSize) |
1051 | 32 | attrMask |= ATTR_ADSIZE; |
1052 | 142 | if (insn->hasOpSize) |
1053 | 35 | attrMask |= ATTR_OPSIZE; |
1054 | 142 | |
1055 | 142 | /* In 16-bit, invert the attributes. */ |
1056 | 142 | if (insn->mode == MODE_16BIT) |
1057 | 19 | attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE; |
1058 | 142 | |
1059 | 142 | if (getIDWithAttrMask(&instructionID, insn, attrMask)) |
1060 | 0 | return -1; |
1061 | 142 | |
1062 | 142 | insn->instructionID = instructionID; |
1063 | 142 | insn->spec = specifierForUID(instructionID); |
1064 | 142 | return 0; |
1065 | 142 | } |
1066 | 514k | |
1067 | 514k | if ((insn->mode == MODE_16BIT || insn->hasOpSize514k ) && |
1068 | 514k | !(attrMask & ATTR_OPSIZE)8.05k ) { |
1069 | 373 | /* |
1070 | 373 | * The instruction tables make no distinction between instructions that |
1071 | 373 | * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a |
1072 | 373 | * particular spot (i.e., many MMX operations). In general we're |
1073 | 373 | * conservative, but in the specific case where OpSize is present but not |
1074 | 373 | * in the right place we check if there's a 16-bit operation. |
1075 | 373 | */ |
1076 | 373 | |
1077 | 373 | const struct InstructionSpecifier *spec; |
1078 | 373 | uint16_t instructionIDWithOpsize; |
1079 | 373 | llvm::StringRef specName, specWithOpSizeName; |
1080 | 373 | |
1081 | 373 | spec = specifierForUID(instructionID); |
1082 | 373 | |
1083 | 373 | if (getIDWithAttrMask(&instructionIDWithOpsize, |
1084 | 373 | insn, |
1085 | 373 | attrMask | ATTR_OPSIZE)) { |
1086 | 0 | /* |
1087 | 0 | * ModRM required with OpSize but not present; give up and return version |
1088 | 0 | * without OpSize set |
1089 | 0 | */ |
1090 | 0 |
|
1091 | 0 | insn->instructionID = instructionID; |
1092 | 0 | insn->spec = spec; |
1093 | 0 | return 0; |
1094 | 0 | } |
1095 | 373 | |
1096 | 373 | specName = GetInstrName(instructionID, miiArg); |
1097 | 373 | specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg); |
1098 | 373 | |
1099 | 373 | if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) && |
1100 | 373 | (insn->mode == MODE_16BIT) ^ insn->hasOpSize345 ) { |
1101 | 251 | insn->instructionID = instructionIDWithOpsize; |
1102 | 251 | insn->spec = specifierForUID(instructionIDWithOpsize); |
1103 | 251 | } else { |
1104 | 122 | insn->instructionID = instructionID; |
1105 | 122 | insn->spec = spec; |
1106 | 122 | } |
1107 | 373 | return 0; |
1108 | 373 | } |
1109 | 514k | |
1110 | 514k | if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90476k && |
1111 | 514k | insn->rexPrefix & 0x0114.1k ) { |
1112 | 4 | /* |
1113 | 4 | * NOOP shouldn't decode as NOOP if REX.b is set. Instead |
1114 | 4 | * it should decode as XCHG %r8, %eax. |
1115 | 4 | */ |
1116 | 4 | |
1117 | 4 | const struct InstructionSpecifier *spec; |
1118 | 4 | uint16_t instructionIDWithNewOpcode; |
1119 | 4 | const struct InstructionSpecifier *specWithNewOpcode; |
1120 | 4 | |
1121 | 4 | spec = specifierForUID(instructionID); |
1122 | 4 | |
1123 | 4 | /* Borrow opcode from one of the other XCHGar opcodes */ |
1124 | 4 | insn->opcode = 0x91; |
1125 | 4 | |
1126 | 4 | if (getIDWithAttrMask(&instructionIDWithNewOpcode, |
1127 | 4 | insn, |
1128 | 4 | attrMask)) { |
1129 | 0 | insn->opcode = 0x90; |
1130 | 0 |
|
1131 | 0 | insn->instructionID = instructionID; |
1132 | 0 | insn->spec = spec; |
1133 | 0 | return 0; |
1134 | 0 | } |
1135 | 4 | |
1136 | 4 | specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); |
1137 | 4 | |
1138 | 4 | /* Change back */ |
1139 | 4 | insn->opcode = 0x90; |
1140 | 4 | |
1141 | 4 | insn->instructionID = instructionIDWithNewOpcode; |
1142 | 4 | insn->spec = specWithNewOpcode; |
1143 | 4 | |
1144 | 4 | return 0; |
1145 | 4 | } |
1146 | 514k | |
1147 | 514k | insn->instructionID = instructionID; |
1148 | 514k | insn->spec = specifierForUID(insn->instructionID); |
1149 | 514k | |
1150 | 514k | return 0; |
1151 | 514k | } |
1152 | | |
1153 | | /* |
1154 | | * readSIB - Consumes the SIB byte to determine addressing information for an |
1155 | | * instruction. |
1156 | | * |
1157 | | * @param insn - The instruction whose SIB byte is to be read. |
1158 | | * @return - 0 if the SIB byte was successfully read; nonzero otherwise. |
1159 | | */ |
1160 | 45.8k | static int readSIB(struct InternalInstruction* insn) { |
1161 | 45.8k | SIBBase sibBaseBase = SIB_BASE_NONE; |
1162 | 45.8k | uint8_t index, base; |
1163 | 45.8k | |
1164 | 45.8k | dbgprintf(insn, "readSIB()"); |
1165 | 45.8k | |
1166 | 45.8k | if (insn->consumedSIB) |
1167 | 0 | return 0; |
1168 | 45.8k | |
1169 | 45.8k | insn->consumedSIB = true; |
1170 | 45.8k | |
1171 | 45.8k | switch (insn->addressSize) { |
1172 | 45.8k | case 2: |
1173 | 0 | dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); |
1174 | 0 | return -1; |
1175 | 45.8k | case 4: |
1176 | 140 | insn->sibIndexBase = SIB_INDEX_EAX; |
1177 | 140 | sibBaseBase = SIB_BASE_EAX; |
1178 | 140 | break; |
1179 | 45.8k | case 8: |
1180 | 45.7k | insn->sibIndexBase = SIB_INDEX_RAX; |
1181 | 45.7k | sibBaseBase = SIB_BASE_RAX; |
1182 | 45.7k | break; |
1183 | 45.8k | } |
1184 | 45.8k | |
1185 | 45.8k | if (consumeByte(insn, &insn->sib)) |
1186 | 1 | return -1; |
1187 | 45.8k | |
1188 | 45.8k | index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); |
1189 | 45.8k | |
1190 | 45.8k | if (index == 0x4) { |
1191 | 32.8k | insn->sibIndex = SIB_INDEX_NONE; |
1192 | 32.8k | } else { |
1193 | 13.0k | insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index); |
1194 | 13.0k | } |
1195 | 45.8k | |
1196 | 45.8k | insn->sibScale = 1 << scaleFromSIB(insn->sib); |
1197 | 45.8k | |
1198 | 45.8k | base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); |
1199 | 45.8k | |
1200 | 45.8k | switch (base) { |
1201 | 45.8k | case 0x5: |
1202 | 1.03k | case 0xd: |
1203 | 1.03k | switch (modFromModRM(insn->modRM)) { |
1204 | 1.03k | case 0x0: |
1205 | 550 | insn->eaDisplacement = EA_DISP_32; |
1206 | 550 | insn->sibBase = SIB_BASE_NONE; |
1207 | 550 | break; |
1208 | 1.03k | case 0x1: |
1209 | 323 | insn->eaDisplacement = EA_DISP_8; |
1210 | 323 | insn->sibBase = (SIBBase)(sibBaseBase + base); |
1211 | 323 | break; |
1212 | 1.03k | case 0x2: |
1213 | 160 | insn->eaDisplacement = EA_DISP_32; |
1214 | 160 | insn->sibBase = (SIBBase)(sibBaseBase + base); |
1215 | 160 | break; |
1216 | 1.03k | case 0x3: |
1217 | 0 | debug("Cannot have Mod = 0b11 and a SIB byte"); |
1218 | 0 | return -1; |
1219 | 1.03k | } |
1220 | 1.03k | break; |
1221 | 44.8k | default: |
1222 | 44.8k | insn->sibBase = (SIBBase)(sibBaseBase + base); |
1223 | 44.8k | break; |
1224 | 45.8k | } |
1225 | 45.8k | |
1226 | 45.8k | return 0; |
1227 | 45.8k | } |
1228 | | |
1229 | | /* |
1230 | | * readDisplacement - Consumes the displacement of an instruction. |
1231 | | * |
1232 | | * @param insn - The instruction whose displacement is to be read. |
1233 | | * @return - 0 if the displacement byte was successfully read; nonzero |
1234 | | * otherwise. |
1235 | | */ |
1236 | 140k | static int readDisplacement(struct InternalInstruction* insn) { |
1237 | 140k | int8_t d8; |
1238 | 140k | int16_t d16; |
1239 | 140k | int32_t d32; |
1240 | 140k | |
1241 | 140k | dbgprintf(insn, "readDisplacement()"); |
1242 | 140k | |
1243 | 140k | if (insn->consumedDisplacement) |
1244 | 0 | return 0; |
1245 | 140k | |
1246 | 140k | insn->consumedDisplacement = true; |
1247 | 140k | insn->displacementOffset = insn->readerCursor - insn->startLocation; |
1248 | 140k | |
1249 | 140k | switch (insn->eaDisplacement) { |
1250 | 140k | case EA_DISP_NONE: |
1251 | 8.21k | insn->consumedDisplacement = false; |
1252 | 8.21k | break; |
1253 | 140k | case EA_DISP_8: |
1254 | 74.3k | if (consumeInt8(insn, &d8)) |
1255 | 0 | return -1; |
1256 | 74.3k | insn->displacement = d8; |
1257 | 74.3k | break; |
1258 | 74.3k | case EA_DISP_16: |
1259 | 14 | if (consumeInt16(insn, &d16)) |
1260 | 0 | return -1; |
1261 | 14 | insn->displacement = d16; |
1262 | 14 | break; |
1263 | 58.3k | case EA_DISP_32: |
1264 | 58.3k | if (consumeInt32(insn, &d32)) |
1265 | 1 | return -1; |
1266 | 58.3k | insn->displacement = d32; |
1267 | 58.3k | break; |
1268 | 140k | } |
1269 | 140k | |
1270 | 140k | insn->consumedDisplacement = true; |
1271 | 140k | return 0; |
1272 | 140k | } |
1273 | | |
1274 | | /* |
1275 | | * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and |
1276 | | * displacement) for an instruction and interprets it. |
1277 | | * |
1278 | | * @param insn - The instruction whose addressing information is to be read. |
1279 | | * @return - 0 if the information was successfully read; nonzero otherwise. |
1280 | | */ |
1281 | 866k | static int readModRM(struct InternalInstruction* insn) { |
1282 | 866k | uint8_t mod, rm, reg; |
1283 | 866k | |
1284 | 866k | dbgprintf(insn, "readModRM()"); |
1285 | 866k | |
1286 | 866k | if (insn->consumedModRM) |
1287 | 549k | return 0; |
1288 | 317k | |
1289 | 317k | if (consumeByte(insn, &insn->modRM)) |
1290 | 10 | return -1; |
1291 | 317k | insn->consumedModRM = true; |
1292 | 317k | |
1293 | 317k | mod = modFromModRM(insn->modRM); |
1294 | 317k | rm = rmFromModRM(insn->modRM); |
1295 | 317k | reg = regFromModRM(insn->modRM); |
1296 | 317k | |
1297 | 317k | /* |
1298 | 317k | * This goes by insn->registerSize to pick the correct register, which messes |
1299 | 317k | * up if we're using (say) XMM or 8-bit register operands. That gets fixed in |
1300 | 317k | * fixupReg(). |
1301 | 317k | */ |
1302 | 317k | switch (insn->registerSize) { |
1303 | 317k | case 2: |
1304 | 7.30k | insn->regBase = MODRM_REG_AX; |
1305 | 7.30k | insn->eaRegBase = EA_REG_AX; |
1306 | 7.30k | break; |
1307 | 317k | case 4: |
1308 | 121k | insn->regBase = MODRM_REG_EAX; |
1309 | 121k | insn->eaRegBase = EA_REG_EAX; |
1310 | 121k | break; |
1311 | 317k | case 8: |
1312 | 188k | insn->regBase = MODRM_REG_RAX; |
1313 | 188k | insn->eaRegBase = EA_REG_RAX; |
1314 | 188k | break; |
1315 | 317k | } |
1316 | 317k | |
1317 | 317k | reg |= rFromREX(insn->rexPrefix) << 3; |
1318 | 317k | rm |= bFromREX(insn->rexPrefix) << 3; |
1319 | 317k | if (insn->vectorExtensionType == TYPE_EVEX) { |
1320 | 327 | reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; |
1321 | 327 | rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; |
1322 | 327 | } |
1323 | 317k | |
1324 | 317k | insn->reg = (Reg)(insn->regBase + reg); |
1325 | 317k | |
1326 | 317k | switch (insn->addressSize) { |
1327 | 317k | case 2: |
1328 | 119 | insn->eaBaseBase = EA_BASE_BX_SI; |
1329 | 119 | |
1330 | 119 | switch (mod) { |
1331 | 119 | case 0x0: |
1332 | 17 | if (rm == 0x6) { |
1333 | 14 | insn->eaBase = EA_BASE_NONE; |
1334 | 14 | insn->eaDisplacement = EA_DISP_16; |
1335 | 14 | if (readDisplacement(insn)) |
1336 | 0 | return -1; |
1337 | 3 | } else { |
1338 | 3 | insn->eaBase = (EABase)(insn->eaBaseBase + rm); |
1339 | 3 | insn->eaDisplacement = EA_DISP_NONE; |
1340 | 3 | } |
1341 | 17 | break; |
1342 | 17 | case 0x1: |
1343 | 2 | insn->eaBase = (EABase)(insn->eaBaseBase + rm); |
1344 | 2 | insn->eaDisplacement = EA_DISP_8; |
1345 | 2 | insn->displacementSize = 1; |
1346 | 2 | if (readDisplacement(insn)) |
1347 | 0 | return -1; |
1348 | 2 | break; |
1349 | 2 | case 0x2: |
1350 | 0 | insn->eaBase = (EABase)(insn->eaBaseBase + rm); |
1351 | 0 | insn->eaDisplacement = EA_DISP_16; |
1352 | 0 | if (readDisplacement(insn)) |
1353 | 0 | return -1; |
1354 | 0 | break; |
1355 | 100 | case 0x3: |
1356 | 100 | insn->eaBase = (EABase)(insn->eaRegBase + rm); |
1357 | 100 | if (readDisplacement(insn)) |
1358 | 0 | return -1; |
1359 | 100 | break; |
1360 | 119 | } |
1361 | 119 | break; |
1362 | 317k | case 4: |
1363 | 317k | case 8: |
1364 | 317k | insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX990 : EA_BASE_RAX316k ); |
1365 | 317k | |
1366 | 317k | switch (mod) { |
1367 | 317k | case 0x0: |
1368 | 55.9k | insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ |
1369 | 55.9k | // In determining whether RIP-relative mode is used (rm=5), |
1370 | 55.9k | // or whether a SIB byte is present (rm=4), |
1371 | 55.9k | // the extension bits (REX.b and EVEX.x) are ignored. |
1372 | 55.9k | switch (rm & 7) { |
1373 | 55.9k | case 0x4: // SIB byte is present |
1374 | 8.66k | insn->eaBase = (insn->addressSize == 4 ? |
1375 | 8.62k | EA_BASE_sib39 : EA_BASE_sib64); |
1376 | 8.66k | if (readSIB(insn) || readDisplacement(insn)8.66k ) |
1377 | 1 | return -1; |
1378 | 8.66k | break; |
1379 | 29.3k | case 0x5: // RIP-relative |
1380 | 29.3k | insn->eaBase = EA_BASE_NONE; |
1381 | 29.3k | insn->eaDisplacement = EA_DISP_32; |
1382 | 29.3k | if (readDisplacement(insn)) |
1383 | 0 | return -1; |
1384 | 29.3k | break; |
1385 | 29.3k | default: |
1386 | 17.8k | insn->eaBase = (EABase)(insn->eaBaseBase + rm); |
1387 | 17.8k | break; |
1388 | 55.9k | } |
1389 | 55.9k | break; |
1390 | 74.3k | case 0x1: |
1391 | 74.3k | insn->displacementSize = 1; |
1392 | 74.3k | /* FALLTHROUGH */ |
1393 | 102k | case 0x2: |
1394 | 102k | insn->eaDisplacement = (mod == 0x1 ? EA_DISP_874.3k : EA_DISP_3228.3k ); |
1395 | 102k | switch (rm & 7) { |
1396 | 102k | case 0x4: // SIB byte is present |
1397 | 37.2k | insn->eaBase = EA_BASE_sib; |
1398 | 37.2k | if (readSIB(insn) || readDisplacement(insn)) |
1399 | 0 | return -1; |
1400 | 37.2k | break; |
1401 | 65.4k | default: |
1402 | 65.4k | insn->eaBase = (EABase)(insn->eaBaseBase + rm); |
1403 | 65.4k | if (readDisplacement(insn)) |
1404 | 1 | return -1; |
1405 | 65.4k | break; |
1406 | 102k | } |
1407 | 102k | break; |
1408 | 158k | case 0x3: |
1409 | 158k | insn->eaDisplacement = EA_DISP_NONE; |
1410 | 158k | insn->eaBase = (EABase)(insn->eaRegBase + rm); |
1411 | 158k | break; |
1412 | 317k | } |
1413 | 317k | break; |
1414 | 317k | } /* switch (insn->addressSize) */ |
1415 | 317k | |
1416 | 317k | return 0; |
1417 | 317k | } |
1418 | | |
1419 | | #define GENERIC_FIXUP_FUNC(name, base, prefix) \ |
1420 | | static uint16_t name(struct InternalInstruction *insn, \ |
1421 | | OperandType type, \ |
1422 | | uint8_t index, \ |
1423 | 391k | uint8_t *valid) { \ |
1424 | 391k | *valid = 1; \ |
1425 | 391k | switch (type) { \ |
1426 | 391k | default: \ |
1427 | 0 | debug("Unhandled register type"); \ |
1428 | 0 | *valid = 0; \ |
1429 | 0 | return 0; \ |
1430 | 391k | case TYPE_Rv: \ |
1431 | 102k | return base + index; \ |
1432 | 391k | case TYPE_R8: \ |
1433 | 28.7k | if (insn->rexPrefix && \ |
1434 | 28.7k | index >= 48.19k && index <= 76.70k ) { \ |
1435 | 1.15k | return prefix##_SPL + (index - 4); \ |
1436 | 27.5k | } else { \ |
1437 | 27.5k | return prefix##_AL + index; \ |
1438 | 27.5k | } \ |
1439 | 28.7k | case TYPE_R16: \ |
1440 | 438 | return prefix##_AX + index; \ |
1441 | 28.7k | case TYPE_R32: \ |
1442 | 941 | return prefix##_EAX + index; \ |
1443 | 248k | case TYPE_R64: \ |
1444 | 248k | return prefix##_RAX + index; \ |
1445 | 28.7k | case TYPE_ZMM: \ |
1446 | 327 | return prefix##_ZMM0 + index; \ |
1447 | 28.7k | case TYPE_YMM: \ |
1448 | 319 | return prefix##_YMM0 + index; \ |
1449 | 28.7k | case TYPE_XMM: \ |
1450 | 9.28k | return prefix##_XMM0 + index; \ |
1451 | 28.7k | case TYPE_VK: \ |
1452 | 99 | if (index > 7) \ |
1453 | 99 | *valid = 00 ; \ |
1454 | 99 | return prefix##_K0 + index; \ |
1455 | 28.7k | case TYPE_MM64: \ |
1456 | 19 | return prefix##_MM0 + (index & 0x7); \ |
1457 | 28.7k | case TYPE_SEGMENTREG: \ |
1458 | 10 | if ((index & 7) > 5) \ |
1459 | 10 | *valid = 02 ; \ |
1460 | 10 | return prefix##_ES + (index & 7); \ |
1461 | 28.7k | case TYPE_DEBUGREG: \ |
1462 | 10 | return prefix##_DR0 + index; \ |
1463 | 28.7k | case TYPE_CONTROLREG: \ |
1464 | 8 | return prefix##_CR0 + index; \ |
1465 | 28.7k | case TYPE_BNDR: \ |
1466 | 10 | if (index > 3) \ |
1467 | 10 | *valid = 00 ; \ |
1468 | 10 | return prefix##_BND0 + index; \ |
1469 | 28.7k | case TYPE_MVSIBX: \ |
1470 | 0 | return prefix##_XMM0 + index; \ |
1471 | 28.7k | case TYPE_MVSIBY: \ |
1472 | 0 | return prefix##_YMM0 + index; \ |
1473 | 28.7k | case TYPE_MVSIBZ: \ |
1474 | 0 | return prefix##_ZMM0 + index; \ |
1475 | 391k | } \ |
1476 | 391k | } X86DisassemblerDecoder.cpp:fixupRegValue(llvm::X86Disassembler::InternalInstruction*, llvm::X86Disassembler::OperandType, unsigned char, unsigned char*) Line | Count | Source | 1423 | 234k | uint8_t *valid) { \ | 1424 | 234k | *valid = 1; \ | 1425 | 234k | switch (type) { \ | 1426 | 234k | default: \ | 1427 | 0 | debug("Unhandled register type"); \ | 1428 | 0 | *valid = 0; \ | 1429 | 0 | return 0; \ | 1430 | 234k | case TYPE_Rv: \ | 1431 | 57.7k | return base + index; \ | 1432 | 234k | case TYPE_R8: \ | 1433 | 14.9k | if (insn->rexPrefix && \ | 1434 | 14.9k | index >= 44.40k && index <= 73.19k ) { \ | 1435 | 602 | return prefix##_SPL + (index - 4); \ | 1436 | 14.3k | } else { \ | 1437 | 14.3k | return prefix##_AL + index; \ | 1438 | 14.3k | } \ | 1439 | 14.9k | case TYPE_R16: \ | 1440 | 2 | return prefix##_AX + index; \ | 1441 | 14.9k | case TYPE_R32: \ | 1442 | 179 | return prefix##_EAX + index; \ | 1443 | 153k | case TYPE_R64: \ | 1444 | 153k | return prefix##_RAX + index; \ | 1445 | 14.9k | case TYPE_ZMM: \ | 1446 | 228 | return prefix##_ZMM0 + index; \ | 1447 | 14.9k | case TYPE_YMM: \ | 1448 | 235 | return prefix##_YMM0 + index; \ | 1449 | 14.9k | case TYPE_XMM: \ | 1450 | 7.19k | return prefix##_XMM0 + index; \ | 1451 | 14.9k | case TYPE_VK: \ | 1452 | 78 | if (index > 7) \ | 1453 | 78 | *valid = 00 ; \ | 1454 | 78 | return prefix##_K0 + index; \ | 1455 | 14.9k | case TYPE_MM64: \ | 1456 | 12 | return prefix##_MM0 + (index & 0x7); \ | 1457 | 14.9k | case TYPE_SEGMENTREG: \ | 1458 | 10 | if ((index & 7) > 5) \ | 1459 | 10 | *valid = 02 ; \ | 1460 | 10 | return prefix##_ES + (index & 7); \ | 1461 | 14.9k | case TYPE_DEBUGREG: \ | 1462 | 10 | return prefix##_DR0 + index; \ | 1463 | 14.9k | case TYPE_CONTROLREG: \ | 1464 | 8 | return prefix##_CR0 + index; \ | 1465 | 14.9k | case TYPE_BNDR: \ | 1466 | 9 | if (index > 3) \ | 1467 | 9 | *valid = 00 ; \ | 1468 | 9 | return prefix##_BND0 + index; \ | 1469 | 14.9k | case TYPE_MVSIBX: \ | 1470 | 0 | return prefix##_XMM0 + index; \ | 1471 | 14.9k | case TYPE_MVSIBY: \ | 1472 | 0 | return prefix##_YMM0 + index; \ | 1473 | 14.9k | case TYPE_MVSIBZ: \ | 1474 | 0 | return prefix##_ZMM0 + index; \ | 1475 | 234k | } \ | 1476 | 234k | } |
X86DisassemblerDecoder.cpp:fixupRMValue(llvm::X86Disassembler::InternalInstruction*, llvm::X86Disassembler::OperandType, unsigned char, unsigned char*) Line | Count | Source | 1423 | 156k | uint8_t *valid) { \ | 1424 | 156k | *valid = 1; \ | 1425 | 156k | switch (type) { \ | 1426 | 156k | default: \ | 1427 | 0 | debug("Unhandled register type"); \ | 1428 | 0 | *valid = 0; \ | 1429 | 0 | return 0; \ | 1430 | 156k | case TYPE_Rv: \ | 1431 | 45.1k | return base + index; \ | 1432 | 156k | case TYPE_R8: \ | 1433 | 13.8k | if (insn->rexPrefix && \ | 1434 | 13.8k | index >= 43.79k && index <= 73.51k ) { \ | 1435 | 551 | return prefix##_SPL + (index - 4); \ | 1436 | 13.2k | } else { \ | 1437 | 13.2k | return prefix##_AL + index; \ | 1438 | 13.2k | } \ | 1439 | 13.8k | case TYPE_R16: \ | 1440 | 436 | return prefix##_AX + index; \ | 1441 | 13.8k | case TYPE_R32: \ | 1442 | 762 | return prefix##_EAX + index; \ | 1443 | 94.1k | case TYPE_R64: \ | 1444 | 94.1k | return prefix##_RAX + index; \ | 1445 | 13.8k | case TYPE_ZMM: \ | 1446 | 99 | return prefix##_ZMM0 + index; \ | 1447 | 13.8k | case TYPE_YMM: \ | 1448 | 84 | return prefix##_YMM0 + index; \ | 1449 | 13.8k | case TYPE_XMM: \ | 1450 | 2.09k | return prefix##_XMM0 + index; \ | 1451 | 13.8k | case TYPE_VK: \ | 1452 | 21 | if (index > 7) \ | 1453 | 21 | *valid = 00 ; \ | 1454 | 21 | return prefix##_K0 + index; \ | 1455 | 13.8k | case TYPE_MM64: \ | 1456 | 7 | return prefix##_MM0 + (index & 0x7); \ | 1457 | 13.8k | case TYPE_SEGMENTREG: \ | 1458 | 0 | if ((index & 7) > 5) \ | 1459 | 0 | *valid = 0; \ | 1460 | 0 | return prefix##_ES + (index & 7); \ | 1461 | 13.8k | case TYPE_DEBUGREG: \ | 1462 | 0 | return prefix##_DR0 + index; \ | 1463 | 13.8k | case TYPE_CONTROLREG: \ | 1464 | 0 | return prefix##_CR0 + index; \ | 1465 | 13.8k | case TYPE_BNDR: \ | 1466 | 1 | if (index > 3) \ | 1467 | 1 | *valid = 00 ; \ | 1468 | 1 | return prefix##_BND0 + index; \ | 1469 | 13.8k | case TYPE_MVSIBX: \ | 1470 | 0 | return prefix##_XMM0 + index; \ | 1471 | 13.8k | case TYPE_MVSIBY: \ | 1472 | 0 | return prefix##_YMM0 + index; \ | 1473 | 13.8k | case TYPE_MVSIBZ: \ | 1474 | 0 | return prefix##_ZMM0 + index; \ | 1475 | 156k | } \ | 1476 | 156k | } |
|
1477 | | |
1478 | | /* |
1479 | | * fixup*Value - Consults an operand type to determine the meaning of the |
1480 | | * reg or R/M field. If the operand is an XMM operand, for example, an |
1481 | | * operand would be XMM0 instead of AX, which readModRM() would otherwise |
1482 | | * misinterpret it as. |
1483 | | * |
1484 | | * @param insn - The instruction containing the operand. |
1485 | | * @param type - The operand type. |
1486 | | * @param index - The existing value of the field as reported by readModRM(). |
1487 | | * @param valid - The address of a uint8_t. The target is set to 1 if the |
1488 | | * field is valid for the register class; 0 if not. |
1489 | | * @return - The proper value. |
1490 | | */ |
1491 | | GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) |
1492 | | GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) |
1493 | | |
1494 | | /* |
1495 | | * fixupReg - Consults an operand specifier to determine which of the |
1496 | | * fixup*Value functions to use in correcting readModRM()'ss interpretation. |
1497 | | * |
1498 | | * @param insn - See fixup*Value(). |
1499 | | * @param op - The operand specifier. |
1500 | | * @return - 0 if fixup was successful; -1 if the register returned was |
1501 | | * invalid for its class. |
1502 | | */ |
1503 | | static int fixupReg(struct InternalInstruction *insn, |
1504 | 549k | const struct OperandSpecifier *op) { |
1505 | 549k | uint8_t valid; |
1506 | 549k | |
1507 | 549k | dbgprintf(insn, "fixupReg()"); |
1508 | 549k | |
1509 | 549k | switch ((OperandEncoding)op->encoding) { |
1510 | 549k | default: |
1511 | 0 | debug("Expected a REG or R/M encoding in fixupReg"); |
1512 | 0 | return -1; |
1513 | 549k | case ENCODING_VVVV: |
1514 | 502 | insn->vvvv = (Reg)fixupRegValue(insn, |
1515 | 502 | (OperandType)op->type, |
1516 | 502 | insn->vvvv, |
1517 | 502 | &valid); |
1518 | 502 | if (!valid) |
1519 | 0 | return -1; |
1520 | 502 | break; |
1521 | 234k | case ENCODING_REG: |
1522 | 234k | insn->reg = (Reg)fixupRegValue(insn, |
1523 | 234k | (OperandType)op->type, |
1524 | 234k | insn->reg - insn->regBase, |
1525 | 234k | &valid); |
1526 | 234k | if (!valid) |
1527 | 2 | return -1; |
1528 | 234k | break; |
1529 | 2.20M | CASE_ENCODING_RM314k : |
1530 | 2.20M | if (insn->eaBase >= insn->eaRegBase314k ) { |
1531 | 156k | insn->eaBase = (EABase)fixupRMValue(insn, |
1532 | 156k | (OperandType)op->type, |
1533 | 156k | insn->eaBase - insn->eaRegBase, |
1534 | 156k | &valid); |
1535 | 156k | if (!valid) |
1536 | 0 | return -1; |
1537 | 314k | } |
1538 | 314k | break; |
1539 | 549k | } |
1540 | 549k | |
1541 | 549k | return 0; |
1542 | 549k | } |
1543 | | |
1544 | | /* |
1545 | | * readOpcodeRegister - Reads an operand from the opcode field of an |
1546 | | * instruction and interprets it appropriately given the operand width. |
1547 | | * Handles AddRegFrm instructions. |
1548 | | * |
1549 | | * @param insn - the instruction whose opcode field is to be read. |
1550 | | * @param size - The width (in bytes) of the register being specified. |
1551 | | * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means |
1552 | | * RAX. |
1553 | | * @return - 0 on success; nonzero otherwise. |
1554 | | */ |
1555 | 48.7k | static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) { |
1556 | 48.7k | dbgprintf(insn, "readOpcodeRegister()"); |
1557 | 48.7k | |
1558 | 48.7k | if (size == 0) |
1559 | 18.3k | size = insn->registerSize; |
1560 | 48.7k | |
1561 | 48.7k | switch (size) { |
1562 | 48.7k | case 1: |
1563 | 1.92k | insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) |
1564 | 1.92k | | (insn->opcode & 7))); |
1565 | 1.92k | if (insn->rexPrefix && |
1566 | 1.92k | insn->opcodeRegister >= MODRM_REG_AL + 0x4250 && |
1567 | 1.92k | insn->opcodeRegister < MODRM_REG_AL + 0x8250 ) { |
1568 | 60 | insn->opcodeRegister = (Reg)(MODRM_REG_SPL |
1569 | 60 | + (insn->opcodeRegister - MODRM_REG_AL - 4)); |
1570 | 60 | } |
1571 | 1.92k | |
1572 | 1.92k | break; |
1573 | 48.7k | case 2: |
1574 | 79 | insn->opcodeRegister = (Reg)(MODRM_REG_AX |
1575 | 79 | + ((bFromREX(insn->rexPrefix) << 3) |
1576 | 79 | | (insn->opcode & 7))); |
1577 | 79 | break; |
1578 | 48.7k | case 4: |
1579 | 18.2k | insn->opcodeRegister = (Reg)(MODRM_REG_EAX |
1580 | 18.2k | + ((bFromREX(insn->rexPrefix) << 3) |
1581 | 18.2k | | (insn->opcode & 7))); |
1582 | 18.2k | break; |
1583 | 48.7k | case 8: |
1584 | 28.5k | insn->opcodeRegister = (Reg)(MODRM_REG_RAX |
1585 | 28.5k | + ((bFromREX(insn->rexPrefix) << 3) |
1586 | 28.5k | | (insn->opcode & 7))); |
1587 | 28.5k | break; |
1588 | 48.7k | } |
1589 | 48.7k | |
1590 | 48.7k | return 0; |
1591 | 48.7k | } |
1592 | | |
1593 | | /* |
1594 | | * readImmediate - Consumes an immediate operand from an instruction, given the |
1595 | | * desired operand size. |
1596 | | * |
1597 | | * @param insn - The instruction whose operand is to be read. |
1598 | | * @param size - The width (in bytes) of the operand. |
1599 | | * @return - 0 if the immediate was successfully consumed; nonzero |
1600 | | * otherwise. |
1601 | | */ |
1602 | 181k | static int readImmediate(struct InternalInstruction* insn, uint8_t size) { |
1603 | 181k | uint8_t imm8; |
1604 | 181k | uint16_t imm16; |
1605 | 181k | uint32_t imm32; |
1606 | 181k | uint64_t imm64; |
1607 | 181k | |
1608 | 181k | dbgprintf(insn, "readImmediate()"); |
1609 | 181k | |
1610 | 181k | if (insn->numImmediatesConsumed == 2) { |
1611 | 0 | debug("Already consumed two immediates"); |
1612 | 0 | return -1; |
1613 | 0 | } |
1614 | 181k | |
1615 | 181k | if (size == 0) |
1616 | 0 | size = insn->immediateSize; |
1617 | 181k | else |
1618 | 181k | insn->immediateSize = size; |
1619 | 181k | insn->immediateOffset = insn->readerCursor - insn->startLocation; |
1620 | 181k | |
1621 | 181k | switch (size) { |
1622 | 181k | case 1: |
1623 | 93.5k | if (consumeByte(insn, &imm8)) |
1624 | 0 | return -1; |
1625 | 93.5k | insn->immediates[insn->numImmediatesConsumed] = imm8; |
1626 | 93.5k | break; |
1627 | 93.5k | case 2: |
1628 | 183 | if (consumeUInt16(insn, &imm16)) |
1629 | 0 | return -1; |
1630 | 183 | insn->immediates[insn->numImmediatesConsumed] = imm16; |
1631 | 183 | break; |
1632 | 86.1k | case 4: |
1633 | 86.1k | if (consumeUInt32(insn, &imm32)) |
1634 | 2 | return -1; |
1635 | 86.1k | insn->immediates[insn->numImmediatesConsumed] = imm32; |
1636 | 86.1k | break; |
1637 | 86.1k | case 8: |
1638 | 1.19k | if (consumeUInt64(insn, &imm64)) |
1639 | 0 | return -1; |
1640 | 1.19k | insn->immediates[insn->numImmediatesConsumed] = imm64; |
1641 | 1.19k | break; |
1642 | 181k | } |
1643 | 181k | |
1644 | 181k | insn->numImmediatesConsumed++; |
1645 | 181k | |
1646 | 181k | return 0; |
1647 | 181k | } |
1648 | | |
1649 | | /* |
1650 | | * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. |
1651 | | * |
1652 | | * @param insn - The instruction whose operand is to be read. |
1653 | | * @return - 0 if the vvvv was successfully consumed; nonzero |
1654 | | * otherwise. |
1655 | | */ |
1656 | 513k | static int readVVVV(struct InternalInstruction* insn) { |
1657 | 513k | dbgprintf(insn, "readVVVV()"); |
1658 | 513k | |
1659 | 513k | int vvvv; |
1660 | 513k | if (insn->vectorExtensionType == TYPE_EVEX) |
1661 | 327 | vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | |
1662 | 327 | vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); |
1663 | 512k | else if (insn->vectorExtensionType == TYPE_VEX_3B) |
1664 | 219 | vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); |
1665 | 512k | else if (512k insn->vectorExtensionType == TYPE_VEX_2B512k ) |
1666 | 292 | vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); |
1667 | 512k | else if (512k insn->vectorExtensionType == TYPE_XOP512k ) |
1668 | 39 | vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); |
1669 | 512k | else |
1670 | 512k | return -1512k ; |
1671 | 877 | |
1672 | 877 | if (insn->mode != MODE_64BIT) |
1673 | 102 | vvvv &= 0x7; |
1674 | 877 | |
1675 | 877 | insn->vvvv = static_cast<Reg>(vvvv); |
1676 | 877 | return 0; |
1677 | 877 | } |
1678 | | |
1679 | | /* |
1680 | | * readMaskRegister - Reads an mask register from the opcode field of an |
1681 | | * instruction. |
1682 | | * |
1683 | | * @param insn - The instruction whose opcode field is to be read. |
1684 | | * @return - 0 on success; nonzero otherwise. |
1685 | | */ |
1686 | 124 | static int readMaskRegister(struct InternalInstruction* insn) { |
1687 | 124 | dbgprintf(insn, "readMaskRegister()"); |
1688 | 124 | |
1689 | 124 | if (insn->vectorExtensionType != TYPE_EVEX) |
1690 | 0 | return -1; |
1691 | 124 | |
1692 | 124 | insn->writemask = |
1693 | 124 | static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])); |
1694 | 124 | return 0; |
1695 | 124 | } |
1696 | | |
1697 | | /* |
1698 | | * readOperands - Consults the specifier for an instruction and consumes all |
1699 | | * operands for that instruction, interpreting them as it goes. |
1700 | | * |
1701 | | * @param insn - The instruction whose operands are to be read and interpreted. |
1702 | | * @return - 0 if all operands could be read; nonzero otherwise. |
1703 | | */ |
1704 | 513k | static int readOperands(struct InternalInstruction* insn) { |
1705 | 513k | int hasVVVV, needVVVV; |
1706 | 513k | int sawRegImm = 0; |
1707 | 513k | |
1708 | 513k | dbgprintf(insn, "readOperands()"); |
1709 | 513k | |
1710 | 513k | /* If non-zero vvvv specified, need to make sure one of the operands |
1711 | 513k | uses it. */ |
1712 | 513k | hasVVVV = !readVVVV(insn); |
1713 | 513k | needVVVV = hasVVVV && (insn->vvvv != 0)877 ; |
1714 | 513k | |
1715 | 3.07M | for (const auto &Op : x86OperandSets[insn->spec->operands]) { |
1716 | 3.07M | switch (Op.encoding) { |
1717 | 3.07M | case ENCODING_NONE: |
1718 | 2.23M | case ENCODING_SI: |
1719 | 2.23M | case ENCODING_DI: |
1720 | 2.23M | break; |
1721 | 2.23M | CASE_ENCODING_VSIB113 : |
1722 | 791 | // VSIB can use the V2 bit so check only the other bits. |
1723 | 791 | if (needVVVV113 ) |
1724 | 102 | needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); |
1725 | 791 | if (readModRM(insn)113 ) |
1726 | 0 | return -1; |
1727 | 113 | |
1728 | 113 | // Reject if SIB wasn't used. |
1729 | 113 | if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib6417 ) |
1730 | 1 | return -1; |
1731 | 112 | |
1732 | 112 | // If sibIndex was set to SIB_INDEX_NONE, index offset is 4. |
1733 | 112 | if (insn->sibIndex == SIB_INDEX_NONE) |
1734 | 0 | insn->sibIndex = (SIBIndex)4; |
1735 | 112 | |
1736 | 112 | // If EVEX.v2 is set this is one of the 16-31 registers. |
1737 | 112 | if (insn->vectorExtensionType == TYPE_EVEX && |
1738 | 112 | v2FromEVEX4of4102 (insn->vectorExtensionPrefix[3])) |
1739 | 112 | insn->sibIndex = (SIBIndex)(insn->sibIndex + 16)96 ; |
1740 | 112 | |
1741 | 112 | // Adjust the index register to the correct size. |
1742 | 112 | switch ((OperandType)Op.type) { |
1743 | 112 | default: |
1744 | 0 | debug("Unhandled VSIB index type"); |
1745 | 0 | return -1; |
1746 | 112 | case TYPE_MVSIBX: |
1747 | 67 | insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 + |
1748 | 67 | (insn->sibIndex - insn->sibIndexBase)); |
1749 | 67 | break; |
1750 | 112 | case TYPE_MVSIBY: |
1751 | 42 | insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 + |
1752 | 42 | (insn->sibIndex - insn->sibIndexBase)); |
1753 | 42 | break; |
1754 | 112 | case TYPE_MVSIBZ: |
1755 | 3 | insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 + |
1756 | 3 | (insn->sibIndex - insn->sibIndexBase)); |
1757 | 3 | break; |
1758 | 112 | } |
1759 | 112 | |
1760 | 112 | // Apply the AVX512 compressed displacement scaling factor. |
1761 | 112 | if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) |
1762 | 96 | insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); |
1763 | 112 | break; |
1764 | 549k | case ENCODING_REG: |
1765 | 3.84M | CASE_ENCODING_RM549k : |
1766 | 3.84M | if (readModRM(insn)549k ) |
1767 | 0 | return -1; |
1768 | 549k | if (fixupReg(insn, &Op)) |
1769 | 2 | return -1; |
1770 | 549k | // Apply the AVX512 compressed displacement scaling factor. |
1771 | 549k | if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8314k ) |
1772 | 74.2k | insn->displacement *= 1 << (Op.encoding - ENCODING_RM); |
1773 | 549k | break; |
1774 | 549k | case ENCODING_IB: |
1775 | 93.5k | if (sawRegImm) { |
1776 | 8 | /* Saw a register immediate so don't read again and instead split the |
1777 | 8 | previous immediate. FIXME: This is a hack. */ |
1778 | 8 | insn->immediates[insn->numImmediatesConsumed] = |
1779 | 8 | insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; |
1780 | 8 | ++insn->numImmediatesConsumed; |
1781 | 8 | break; |
1782 | 8 | } |
1783 | 93.5k | if (readImmediate(insn, 1)) |
1784 | 0 | return -1; |
1785 | 93.5k | if (Op.type == TYPE_XMM || Op.type == TYPE_YMM93.4k ) |
1786 | 35 | sawRegImm = 1; |
1787 | 93.5k | break; |
1788 | 93.5k | case ENCODING_IW: |
1789 | 41 | if (readImmediate(insn, 2)) |
1790 | 0 | return -1; |
1791 | 41 | break; |
1792 | 41.3k | case ENCODING_ID: |
1793 | 41.3k | if (readImmediate(insn, 4)) |
1794 | 0 | return -1; |
1795 | 41.3k | break; |
1796 | 41.3k | case ENCODING_IO: |
1797 | 1.15k | if (readImmediate(insn, 8)) |
1798 | 0 | return -1; |
1799 | 1.15k | break; |
1800 | 44.9k | case ENCODING_Iv: |
1801 | 44.9k | if (readImmediate(insn, insn->immediateSize)) |
1802 | 2 | return -1; |
1803 | 44.9k | break; |
1804 | 44.9k | case ENCODING_Ia: |
1805 | 142 | if (readImmediate(insn, insn->addressSize)) |
1806 | 0 | return -1; |
1807 | 142 | break; |
1808 | 142 | case ENCODING_IRC: |
1809 | 42 | insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) | |
1810 | 42 | lFromEVEX4of4(insn->vectorExtensionPrefix[3]); |
1811 | 42 | break; |
1812 | 1.92k | case ENCODING_RB: |
1813 | 1.92k | if (readOpcodeRegister(insn, 1)) |
1814 | 0 | return -1; |
1815 | 1.92k | break; |
1816 | 1.92k | case ENCODING_RW: |
1817 | 0 | if (readOpcodeRegister(insn, 2)) |
1818 | 0 | return -1; |
1819 | 0 | break; |
1820 | 0 | case ENCODING_RD: |
1821 | 0 | if (readOpcodeRegister(insn, 4)) |
1822 | 0 | return -1; |
1823 | 0 | break; |
1824 | 28.5k | case ENCODING_RO: |
1825 | 28.5k | if (readOpcodeRegister(insn, 8)) |
1826 | 0 | return -1; |
1827 | 28.5k | break; |
1828 | 28.5k | case ENCODING_Rv: |
1829 | 18.3k | if (readOpcodeRegister(insn, 0)) |
1830 | 0 | return -1; |
1831 | 18.3k | break; |
1832 | 18.3k | case ENCODING_FP: |
1833 | 659 | break; |
1834 | 18.3k | case ENCODING_VVVV: |
1835 | 502 | needVVVV = 0; /* Mark that we have found a VVVV operand. */ |
1836 | 502 | if (!hasVVVV) |
1837 | 0 | return -1; |
1838 | 502 | if (fixupReg(insn, &Op)) |
1839 | 0 | return -1; |
1840 | 502 | break; |
1841 | 502 | case ENCODING_WRITEMASK: |
1842 | 124 | if (readMaskRegister(insn)) |
1843 | 0 | return -1; |
1844 | 124 | break; |
1845 | 63.0k | case ENCODING_DUP: |
1846 | 63.0k | break; |
1847 | 124 | default: |
1848 | 0 | dbgprintf(insn, "Encountered an operand with an unknown encoding."); |
1849 | 0 | return -1; |
1850 | 3.07M | } |
1851 | 3.07M | } |
1852 | 513k | |
1853 | 513k | /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ |
1854 | 513k | if (513k needVVVV513k ) return -11 ; |
1855 | 513k | |
1856 | 513k | return 0; |
1857 | 513k | } |
1858 | | |
1859 | | /* |
1860 | | * decodeInstruction - Reads and interprets a full instruction provided by the |
1861 | | * user. |
1862 | | * |
1863 | | * @param insn - A pointer to the instruction to be populated. Must be |
1864 | | * pre-allocated. |
1865 | | * @param reader - The function to be used to read the instruction's bytes. |
1866 | | * @param readerArg - A generic argument to be passed to the reader to store |
1867 | | * any internal state. |
1868 | | * @param logger - If non-NULL, the function to be used to write log messages |
1869 | | * and warnings. |
1870 | | * @param loggerArg - A generic argument to be passed to the logger to store |
1871 | | * any internal state. |
1872 | | * @param startLoc - The address (in the reader's address space) of the first |
1873 | | * byte in the instruction. |
1874 | | * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to |
1875 | | * decode the instruction in. |
1876 | | * @return - 0 if the instruction's memory could be read; nonzero if |
1877 | | * not. |
1878 | | */ |
1879 | | int llvm::X86Disassembler::decodeInstruction( |
1880 | | struct InternalInstruction *insn, byteReader_t reader, |
1881 | | const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, |
1882 | 514k | uint64_t startLoc, DisassemblerMode mode) { |
1883 | 514k | memset(insn, 0, sizeof(struct InternalInstruction)); |
1884 | 514k | |
1885 | 514k | insn->reader = reader; |
1886 | 514k | insn->readerArg = readerArg; |
1887 | 514k | insn->dlog = logger; |
1888 | 514k | insn->dlogArg = loggerArg; |
1889 | 514k | insn->startLocation = startLoc; |
1890 | 514k | insn->readerCursor = startLoc; |
1891 | 514k | insn->mode = mode; |
1892 | 514k | insn->numImmediatesConsumed = 0; |
1893 | 514k | |
1894 | 514k | if (readPrefixes(insn) || |
1895 | 514k | readOpcode(insn) || |
1896 | 514k | getID(insn, miiArg)514k || |
1897 | 514k | insn->instructionID == 0514k || |
1898 | 514k | readOperands(insn)513k ) |
1899 | 1.57k | return -1; |
1900 | 513k | |
1901 | 513k | insn->operands = x86OperandSets[insn->spec->operands]; |
1902 | 513k | |
1903 | 513k | insn->length = insn->readerCursor - insn->startLocation; |
1904 | 513k | |
1905 | 513k | dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu", |
1906 | 513k | startLoc, insn->readerCursor, insn->length); |
1907 | 513k | |
1908 | 513k | if (insn->length > 15) |
1909 | 0 | dbgprintf(insn, "Instruction exceeds 15-byte limit"); |
1910 | 513k | |
1911 | 513k | return 0; |
1912 | 513k | } |