Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/clang/lib/Basic/Targets/AArch64.cpp
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Source (jump to first uncovered line)
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//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
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//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
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13
#include "AArch64.h"
14
#include "clang/Basic/TargetBuiltins.h"
15
#include "clang/Basic/TargetInfo.h"
16
#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringExtras.h"
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19
using namespace clang;
20
using namespace clang::targets;
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22
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
23
#define BUILTIN(ID, TYPE, ATTRS)                                               \
24
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
25
#include "clang/Basic/BuiltinsNEON.def"
26
27
#define BUILTIN(ID, TYPE, ATTRS)                                               \
28
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
29
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
30
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
31
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
32
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
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#include "clang/Basic/BuiltinsAArch64.def"
34
};
35
36
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
37
                                     const TargetOptions &Opts)
38
7.76k
    : TargetInfo(Triple), ABI("aapcs") {
39
7.76k
  if (getTriple().isOSOpenBSD()) {
40
5
    Int64Type = SignedLongLong;
41
5
    IntMaxType = SignedLongLong;
42
7.75k
  } else {
43
7.75k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()342
)
44
336
      WCharType = UnsignedInt;
45
7.75k
46
7.75k
    Int64Type = SignedLong;
47
7.75k
    IntMaxType = SignedLong;
48
7.75k
  }
49
7.76k
50
7.76k
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
51
7.76k
  HasLegalHalfType = true;
52
7.76k
  HasFloat16 = true;
53
7.76k
54
7.76k
  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
55
7.76k
  MaxVectorAlign = 128;
56
7.76k
  MaxAtomicInlineWidth = 128;
57
7.76k
  MaxAtomicPromoteWidth = 128;
58
7.76k
59
7.76k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
60
7.76k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
61
7.76k
62
7.76k
  // Make __builtin_ms_va_list available.
63
7.76k
  HasBuiltinMSVaList = true;
64
7.76k
65
7.76k
  // {} in inline assembly are neon specifiers, not assembly variant
66
7.76k
  // specifiers.
67
7.76k
  NoAsmVariants = true;
68
7.76k
69
7.76k
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
70
7.76k
  // contributes to the alignment of the containing aggregate in the same way
71
7.76k
  // a plain (non bit-field) member of that type would, without exception for
72
7.76k
  // zero-sized or anonymous bit-fields."
73
7.76k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
74
7.76k
  UseZeroLengthBitfieldAlignment = true;
75
7.76k
76
7.76k
  // AArch64 targets default to using the ARM C++ ABI.
77
7.76k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
78
7.76k
79
7.76k
  if (Triple.getOS() == llvm::Triple::Linux)
80
178
    this->MCountName = "\01_mcount";
81
7.58k
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
82
111
    this->MCountName =
83
111
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
:
"mcount"110
;
84
7.76k
}
85
86
3.38k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
87
88
7.43k
bool AArch64TargetInfo::setABI(const std::string &Name) {
89
7.43k
  if (Name != "aapcs" && 
Name != "darwinpcs"7.30k
)
90
0
    return false;
91
7.43k
92
7.43k
  ABI = Name;
93
7.43k
  return true;
94
7.43k
}
95
96
7.45k
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
97
7.45k
  return Name == "generic" ||
98
7.45k
         
llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID7.32k
;
99
7.45k
}
100
101
7.45k
bool AArch64TargetInfo::setCPU(const std::string &Name) {
102
7.45k
  return isValidCPUName(Name);
103
7.45k
}
104
105
void AArch64TargetInfo::fillValidCPUList(
106
1
    SmallVectorImpl<StringRef> &Values) const {
107
1
  llvm::AArch64::fillValidCPUArchList(Values);
108
1
}
109
110
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
111
66
                                                MacroBuilder &Builder) const {
112
66
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
113
66
}
114
115
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
116
63
                                                MacroBuilder &Builder) const {
117
63
  // Also include the ARMv8.1 defines
118
63
  getTargetDefinesARMV81A(Opts, Builder);
119
63
}
120
121
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
122
23
                                                MacroBuilder &Builder) const {
123
23
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
124
23
  // Also include the Armv8.2 defines
125
23
  getTargetDefinesARMV82A(Opts, Builder);
126
23
}
127
128
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
129
15
                                                MacroBuilder &Builder) const {
130
15
  // Also include the Armv8.3 defines
131
15
  // FIXME: Armv8.4 makes some extensions mandatory. Handle them here.
132
15
  getTargetDefinesARMV83A(Opts, Builder);
133
15
}
134
135
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
136
2
                                                MacroBuilder &Builder) const {
137
2
  // Also include the Armv8.4 defines
138
2
  // FIXME: Armv8.5 makes some extensions mandatory. Handle them here.
139
2
  getTargetDefinesARMV84A(Opts, Builder);
140
2
}
141
142
143
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
144
3.59k
                                         MacroBuilder &Builder) const {
145
3.59k
  // Target identification.
146
3.59k
  Builder.defineMacro("__aarch64__");
147
3.59k
  // For bare-metal.
148
3.59k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
149
3.59k
      
getTriple().isOSBinFormatELF()110
)
150
109
    Builder.defineMacro("__ELF__");
151
3.59k
152
3.59k
  // Target properties.
153
3.59k
  if (!getTriple().isOSWindows()) {
154
3.55k
    Builder.defineMacro("_LP64");
155
3.55k
    Builder.defineMacro("__LP64__");
156
3.55k
  }
157
3.59k
158
3.59k
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
159
3.59k
  Builder.defineMacro("__ARM_ACLE", "200");
160
3.59k
  Builder.defineMacro("__ARM_ARCH", "8");
161
3.59k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
162
3.59k
163
3.59k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
164
3.59k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
165
3.59k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
166
3.59k
167
3.59k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
168
3.59k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
169
3.59k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
170
3.59k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
171
3.59k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
172
3.59k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
173
3.59k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
174
3.59k
175
3.59k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
176
3.59k
177
3.59k
  // 0xe implies support for half, single and double precision operations.
178
3.59k
  Builder.defineMacro("__ARM_FP", "0xE");
179
3.59k
180
3.59k
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
181
3.59k
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
182
3.59k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
183
3.59k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
184
3.59k
185
3.59k
  if (Opts.UnsafeFPMath)
186
7
    Builder.defineMacro("__ARM_FP_FAST", "1");
187
3.59k
188
3.59k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
189
3.59k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
43.58k
));
190
3.59k
191
3.59k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"3.59k
);
192
3.59k
193
3.59k
  if (FPU & NeonMode) {
194
3.33k
    Builder.defineMacro("__ARM_NEON", "1");
195
3.33k
    // 64-bit NEON supports half, single and double precision operations.
196
3.33k
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
197
3.33k
  }
198
3.59k
199
3.59k
  if (FPU & SveMode)
200
10
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
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3.59k
202
3.59k
  if (HasCRC)
203
6
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
204
3.59k
205
3.59k
  if (HasCrypto)
206
3.13k
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
207
3.59k
208
3.59k
  if (HasUnaligned)
209
3.59k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
210
3.59k
211
3.59k
  if ((FPU & NeonMode) && 
HasFullFP163.33k
)
212
41
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
213
3.59k
  if (HasFullFP16)
214
46
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
215
3.59k
216
3.59k
  if (HasDotProd)
217
2
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
218
3.59k
219
3.59k
  if (HasMTE)
220
4
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
221
3.59k
222
3.59k
  if ((FPU & NeonMode) && 
HasFP16FML3.33k
)
223
7
    Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
224
3.59k
225
3.59k
  switch (ArchKind) {
226
3.59k
  default:
227
3.52k
    break;
228
3.59k
  case llvm::AArch64::ArchKind::ARMV8_1A:
229
3
    getTargetDefinesARMV81A(Opts, Builder);
230
3
    break;
231
3.59k
  case llvm::AArch64::ArchKind::ARMV8_2A:
232
40
    getTargetDefinesARMV82A(Opts, Builder);
233
40
    break;
234
3.59k
  case llvm::AArch64::ArchKind::ARMV8_3A:
235
8
    getTargetDefinesARMV83A(Opts, Builder);
236
8
    break;
237
3.59k
  case llvm::AArch64::ArchKind::ARMV8_4A:
238
13
    getTargetDefinesARMV84A(Opts, Builder);
239
13
    break;
240
3.59k
  case llvm::AArch64::ArchKind::ARMV8_5A:
241
2
    getTargetDefinesARMV85A(Opts, Builder);
242
2
    break;
243
3.59k
  }
244
3.59k
245
3.59k
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
246
3.59k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
247
3.59k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
248
3.59k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
249
3.59k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
250
3.59k
}
251
252
3.59k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
253
3.59k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
254
3.59k
                                             Builtin::FirstTSBuiltin);
255
3.59k
}
256
257
109k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
258
109k
  return Feature == "aarch64" || 
Feature == "arm64"109k
||
Feature == "arm"109k
||
259
109k
         
(109k
Feature == "neon"109k
&&
(FPU & NeonMode)2.27k
) ||
260
109k
         
(107k
Feature == "sve"107k
&&
(FPU & SveMode)104
);
261
109k
}
262
263
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
264
7.76k
                                             DiagnosticsEngine &Diags) {
265
7.76k
  FPU = FPUMode;
266
7.76k
  HasCRC = false;
267
7.76k
  HasCrypto = false;
268
7.76k
  HasUnaligned = true;
269
7.76k
  HasFullFP16 = false;
270
7.76k
  HasDotProd = false;
271
7.76k
  HasFP16FML = false;
272
7.76k
  HasMTE = false;
273
7.76k
  ArchKind = llvm::AArch64::ArchKind::ARMV8A;
274
7.76k
275
51.4k
  for (const auto &Feature : Features) {
276
51.4k
    if (Feature == "+neon")
277
7.50k
      FPU |= NeonMode;
278
51.4k
    if (Feature == "+sve")
279
10
      FPU |= SveMode;
280
51.4k
    if (Feature == "+crc")
281
6
      HasCRC = true;
282
51.4k
    if (Feature == "+crypto")
283
7.30k
      HasCrypto = true;
284
51.4k
    if (Feature == "+strict-align")
285
0
      HasUnaligned = false;
286
51.4k
    if (Feature == "+v8.1a")
287
3
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
288
51.4k
    if (Feature == "+v8.2a")
289
40
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
290
51.4k
    if (Feature == "+v8.3a")
291
8
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
292
51.4k
    if (Feature == "+v8.4a")
293
13
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
294
51.4k
    if (Feature == "+v8.5a")
295
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
296
51.4k
    if (Feature == "+fullfp16")
297
46
      HasFullFP16 = true;
298
51.4k
    if (Feature == "+dotprod")
299
2
      HasDotProd = true;
300
51.4k
    if (Feature == "+fp16fml")
301
10
      HasFP16FML = true;
302
51.4k
    if (Feature == "+mte")
303
4
      HasMTE = true;
304
51.4k
  }
305
7.76k
306
7.76k
  setDataLayout();
307
7.76k
308
7.76k
  return true;
309
7.76k
}
310
311
TargetInfo::CallingConvCheckResult
312
339
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
313
339
  switch (CC) {
314
339
  case CC_C:
315
339
  case CC_Swift:
316
339
  case CC_PreserveMost:
317
339
  case CC_PreserveAll:
318
339
  case CC_OpenCLKernel:
319
339
  case CC_AArch64VectorCall:
320
339
  case CC_Win64:
321
339
    return CCCR_OK;
322
339
  default:
323
0
    return CCCR_Warning;
324
339
  }
325
339
}
326
327
184
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
328
329
316
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
330
316
  return TargetInfo::AArch64ABIBuiltinVaList;
331
316
}
332
333
const char *const AArch64TargetInfo::GCCRegNames[] = {
334
    // 32-bit Integer registers
335
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
336
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
337
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
338
339
    // 64-bit Integer registers
340
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
341
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
342
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
343
344
    // 32-bit floating point regsisters
345
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
346
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
347
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
348
349
    // 64-bit floating point regsisters
350
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
351
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
352
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
353
354
    // Vector registers
355
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
356
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
357
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
358
};
359
360
2.52k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
361
2.52k
  return llvm::makeArrayRef(GCCRegNames);
362
2.52k
}
363
364
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
365
    {{"w31"}, "wsp"},
366
    {{"x31"}, "sp"},
367
    // GCC rN registers are aliases of xN registers.
368
    {{"r0"}, "x0"},
369
    {{"r1"}, "x1"},
370
    {{"r2"}, "x2"},
371
    {{"r3"}, "x3"},
372
    {{"r4"}, "x4"},
373
    {{"r5"}, "x5"},
374
    {{"r6"}, "x6"},
375
    {{"r7"}, "x7"},
376
    {{"r8"}, "x8"},
377
    {{"r9"}, "x9"},
378
    {{"r10"}, "x10"},
379
    {{"r11"}, "x11"},
380
    {{"r12"}, "x12"},
381
    {{"r13"}, "x13"},
382
    {{"r14"}, "x14"},
383
    {{"r15"}, "x15"},
384
    {{"r16"}, "x16"},
385
    {{"r17"}, "x17"},
386
    {{"r18"}, "x18"},
387
    {{"r19"}, "x19"},
388
    {{"r20"}, "x20"},
389
    {{"r21"}, "x21"},
390
    {{"r22"}, "x22"},
391
    {{"r23"}, "x23"},
392
    {{"r24"}, "x24"},
393
    {{"r25"}, "x25"},
394
    {{"r26"}, "x26"},
395
    {{"r27"}, "x27"},
396
    {{"r28"}, "x28"},
397
    {{"r29", "x29"}, "fp"},
398
    {{"r30", "x30"}, "lr"},
399
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
400
    // don't want to substitute one of these for a different-sized one.
401
};
402
403
2.19k
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
404
2.19k
  return llvm::makeArrayRef(GCCRegAliases);
405
2.19k
}
406
407
bool AArch64TargetInfo::validateAsmConstraint(
408
26
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
409
26
  switch (*Name) {
410
26
  default:
411
0
    return false;
412
26
  case 'w': // Floating point and SIMD registers (V0-V31)
413
10
    Info.setAllowsRegister();
414
10
    return true;
415
26
  case 'I': // Constant that can be used with an ADD instruction
416
6
  case 'J': // Constant that can be used with a SUB instruction
417
6
  case 'K': // Constant that can be used with a 32-bit logical instruction
418
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
419
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
420
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
421
6
  case 'Y': // Floating point constant zero
422
6
  case 'Z': // Integer constant zero
423
6
    return true;
424
6
  case 'Q': // A memory reference with base register and no offset
425
4
    Info.setAllowsMemory();
426
4
    return true;
427
6
  case 'S': // A symbolic address
428
2
    Info.setAllowsRegister();
429
2
    return true;
430
6
  case 'U':
431
0
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
432
0
    // Utf: A memory address suitable for ldp/stp in TF mode.
433
0
    // Usa: An absolute symbolic address.
434
0
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
435
0
    llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
436
6
  case 'z': // Zero register, wzr or xzr
437
4
    Info.setAllowsRegister();
438
4
    return true;
439
6
  case 'x': // Floating point and SIMD registers (V0-V15)
440
0
    Info.setAllowsRegister();
441
0
    return true;
442
0
  }
443
0
  return false;
444
0
}
445
446
bool AArch64TargetInfo::validateConstraintModifier(
447
    StringRef Constraint, char Modifier, unsigned Size,
448
55
    std::string &SuggestedModifier) const {
449
55
  // Strip off constraint modifiers.
450
82
  while (Constraint[0] == '=' || 
Constraint[0] == '+'63
||
Constraint[0] == '&'56
)
451
27
    Constraint = Constraint.substr(1);
452
55
453
55
  switch (Constraint[0]) {
454
55
  default:
455
22
    return true;
456
55
  case 'z':
457
33
  case 'r': {
458
33
    switch (Modifier) {
459
33
    case 'x':
460
7
    case 'w':
461
7
      // For now assume that the person knows what they're
462
7
      // doing with the modifier.
463
7
      return true;
464
26
    default:
465
26
      // By default an 'r' constraint will be in the 'x'
466
26
      // registers.
467
26
      if (Size == 64)
468
15
        return true;
469
11
470
11
      SuggestedModifier = "w";
471
11
      return false;
472
33
    }
473
33
  }
474
55
  }
475
55
}
476
477
663
const char *AArch64TargetInfo::getClobbers() const { return ""; }
478
479
2
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
480
2
  if (RegNo == 0)
481
1
    return 0;
482
1
  if (RegNo == 1)
483
1
    return 1;
484
0
  return -1;
485
0
}
486
487
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
488
                                         const TargetOptions &Opts)
489
7.73k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
489
7.64k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
489
96
    : AArch64TargetInfo(Triple, Opts) {}
490
491
7.69k
void AArch64leTargetInfo::setDataLayout() {
492
7.69k
  if (getTriple().isOSBinFormatMachO())
493
7.41k
    resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
494
280
  else
495
280
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
496
7.69k
}
497
498
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
499
3.56k
                                           MacroBuilder &Builder) const {
500
3.56k
  Builder.defineMacro("__AARCH64EL__");
501
3.56k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
502
3.56k
}
503
504
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
505
                                         const TargetOptions &Opts)
506
25
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
506
8
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
506
17
    : AArch64TargetInfo(Triple, Opts) {}
507
508
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
509
25
                                           MacroBuilder &Builder) const {
510
25
  Builder.defineMacro("__AARCH64EB__");
511
25
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
512
25
  Builder.defineMacro("__ARM_BIG_ENDIAN");
513
25
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
514
25
}
515
516
25
void AArch64beTargetInfo::setDataLayout() {
517
25
  assert(!getTriple().isOSBinFormatMachO());
518
25
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
519
25
}
520
521
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
522
                                               const TargetOptions &Opts)
523
40
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
524
40
525
40
  // This is an LLP64 platform.
526
40
  // int:4, long:4, long long:8, long double:8.
527
40
  IntWidth = IntAlign = 32;
528
40
  LongWidth = LongAlign = 32;
529
40
  DoubleAlign = LongLongAlign = 64;
530
40
  LongDoubleWidth = LongDoubleAlign = 64;
531
40
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
532
40
  IntMaxType = SignedLongLong;
533
40
  Int64Type = SignedLongLong;
534
40
  SizeType = UnsignedLongLong;
535
40
  PtrDiffType = SignedLongLong;
536
40
  IntPtrType = SignedLongLong;
537
40
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
523
40
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
524
40
525
40
  // This is an LLP64 platform.
526
40
  // int:4, long:4, long long:8, long double:8.
527
40
  IntWidth = IntAlign = 32;
528
40
  LongWidth = LongAlign = 32;
529
40
  DoubleAlign = LongLongAlign = 64;
530
40
  LongDoubleWidth = LongDoubleAlign = 64;
531
40
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
532
40
  IntMaxType = SignedLongLong;
533
40
  Int64Type = SignedLongLong;
534
40
  SizeType = UnsignedLongLong;
535
40
  PtrDiffType = SignedLongLong;
536
40
  IntPtrType = SignedLongLong;
537
40
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
538
539
40
void WindowsARM64TargetInfo::setDataLayout() {
540
40
  resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128");
541
40
}
542
543
TargetInfo::BuiltinVaListKind
544
39
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
545
39
  return TargetInfo::CharPtrBuiltinVaList;
546
39
}
547
548
TargetInfo::CallingConvCheckResult
549
52
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
550
52
  switch (CC) {
551
52
  case CC_X86StdCall:
552
7
  case CC_X86ThisCall:
553
7
  case CC_X86FastCall:
554
7
  case CC_X86VectorCall:
555
7
    return CCCR_Ignore;
556
45
  case CC_C:
557
45
  case CC_OpenCLKernel:
558
45
  case CC_PreserveMost:
559
45
  case CC_PreserveAll:
560
45
  case CC_Swift:
561
45
  case CC_Win64:
562
45
    return CCCR_OK;
563
45
  default:
564
0
    return CCCR_Warning;
565
52
  }
566
52
}
567
568
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
569
                                                   const TargetOptions &Opts)
570
37
    : WindowsARM64TargetInfo(Triple, Opts) {
571
37
  TheCXXABI.set(TargetCXXABI::Microsoft);
572
37
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
570
37
    : WindowsARM64TargetInfo(Triple, Opts) {
571
37
  TheCXXABI.set(TargetCXXABI::Microsoft);
572
37
}
573
574
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
575
37
                                                MacroBuilder &Builder) const {
576
37
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
577
37
  Builder.defineMacro("_M_ARM64", "1");
578
37
}
579
580
TargetInfo::CallingConvKind
581
71
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
582
71
  return CCK_MicrosoftWin64;
583
71
}
584
585
162
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
586
162
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
587
162
588
162
  // MSVC does size based alignment for arm64 based on alignment section in
589
162
  // below document, replicate that to keep alignment consistent with object
590
162
  // files compiled by MSVC.
591
162
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
592
162
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
593
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
594
152
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
595
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
596
95
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
597
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
598
45
  }
599
162
  return Align;
600
162
}
601
602
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
603
                                           const TargetOptions &Opts)
604
3
    : WindowsARM64TargetInfo(Triple, Opts) {
605
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
606
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
604
3
    : WindowsARM64TargetInfo(Triple, Opts) {
605
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
606
3
}
607
608
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
609
                                                 const TargetOptions &Opts)
610
7.41k
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
611
7.41k
  Int64Type = SignedLongLong;
612
7.41k
  UseSignedCharForObjCBool = false;
613
7.41k
614
7.41k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
615
7.41k
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
616
7.41k
617
7.41k
  TheCXXABI.set(TargetCXXABI::iOS64);
618
7.41k
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
610
7.41k
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
611
7.41k
  Int64Type = SignedLongLong;
612
7.41k
  UseSignedCharForObjCBool = false;
613
7.41k
614
7.41k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
615
7.41k
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
616
7.41k
617
7.41k
  TheCXXABI.set(TargetCXXABI::iOS64);
618
7.41k
}
619
620
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
621
                                           const llvm::Triple &Triple,
622
3.24k
                                           MacroBuilder &Builder) const {
623
3.24k
  Builder.defineMacro("__AARCH64_SIMD__");
624
3.24k
  Builder.defineMacro("__ARM64_ARCH_8__");
625
3.24k
  Builder.defineMacro("__ARM_NEON__");
626
3.24k
  Builder.defineMacro("__LITTLE_ENDIAN__");
627
3.24k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
628
3.24k
  Builder.defineMacro("__arm64", "1");
629
3.24k
  Builder.defineMacro("__arm64__", "1");
630
3.24k
631
3.24k
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
632
3.24k
}
633
634
TargetInfo::BuiltinVaListKind
635
3.42k
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
636
3.42k
  return TargetInfo::CharPtrBuiltinVaList;
637
3.42k
}
638
639
// 64-bit RenderScript is aarch64
640
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
641
                                                   const TargetOptions &Opts)
642
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
643
                                       Triple.getOSName(),
644
                                       Triple.getEnvironmentName()),
645
1
                          Opts) {
646
1
  IsRenderScriptTarget = true;
647
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
645
1
                          Opts) {
646
1
  IsRenderScriptTarget = true;
647
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
648
649
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
650
1
                                                MacroBuilder &Builder) const {
651
1
  Builder.defineMacro("__RENDERSCRIPT__");
652
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
653
1
}