Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/clang/lib/Basic/Targets/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements ARM TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARM.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
21
using namespace clang;
22
using namespace clang::targets;
23
24
3.61k
void ARMTargetInfo::setABIAAPCS() {
25
3.61k
  IsAAPCS = true;
26
3.61k
27
3.61k
  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
28
3.61k
  const llvm::Triple &T = getTriple();
29
3.61k
30
3.61k
  bool IsNetBSD = T.isOSNetBSD();
31
3.61k
  bool IsOpenBSD = T.isOSOpenBSD();
32
3.61k
  if (!T.isOSWindows() && 
!IsNetBSD3.52k
&&
!IsOpenBSD3.51k
)
33
3.50k
    WCharType = UnsignedInt;
34
3.61k
35
3.61k
  UseBitFieldTypeAlignment = true;
36
3.61k
37
3.61k
  ZeroLengthBitfieldBoundary = 0;
38
3.61k
39
3.61k
  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
40
3.61k
  // so set preferred for small types to 32.
41
3.61k
  if (T.isOSBinFormatMachO()) {
42
2.47k
    resetDataLayout(BigEndian
43
2.47k
                        ? 
"E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"0
44
2.47k
                        : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
45
2.47k
  } else 
if (1.14k
T.isOSWindows()1.14k
) {
46
95
    assert(!BigEndian && "Windows on ARM does not support big endian");
47
95
    resetDataLayout("e"
48
95
                    "-m:w"
49
95
                    "-p:32:32"
50
95
                    "-Fi8"
51
95
                    "-i64:64"
52
95
                    "-v128:64:128"
53
95
                    "-a:0:32"
54
95
                    "-n32"
55
95
                    "-S64");
56
1.04k
  } else if (T.isOSNaCl()) {
57
2
    assert(!BigEndian && "NaCl on ARM does not support big endian");
58
2
    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
59
1.04k
  } else {
60
1.04k
    resetDataLayout(BigEndian
61
1.04k
                        ? 
"E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"21
62
1.04k
                        : 
"e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"1.02k
);
63
1.04k
  }
64
3.61k
65
3.61k
  // FIXME: Enumerated types are variable width in straight AAPCS.
66
3.61k
}
67
68
3.42k
void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
69
3.42k
  const llvm::Triple &T = getTriple();
70
3.42k
71
3.42k
  IsAAPCS = false;
72
3.42k
73
3.42k
  if (IsAAPCS16)
74
1.36k
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
75
2.05k
  else
76
2.05k
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
77
3.42k
78
3.42k
  WCharType = SignedInt;
79
3.42k
80
3.42k
  // Do not respect the alignment of bit-field types when laying out
81
3.42k
  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
82
3.42k
  UseBitFieldTypeAlignment = false;
83
3.42k
84
3.42k
  /// gcc forces the alignment to 4 bytes, regardless of the type of the
85
3.42k
  /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
86
3.42k
  /// gcc.
87
3.42k
  ZeroLengthBitfieldBoundary = 32;
88
3.42k
89
3.42k
  if (T.isOSBinFormatMachO() && 
IsAAPCS163.37k
) {
90
1.36k
    assert(!BigEndian && "AAPCS16 does not support big-endian");
91
1.36k
    resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128");
92
2.05k
  } else if (T.isOSBinFormatMachO())
93
2.01k
    resetDataLayout(
94
2.01k
        BigEndian
95
2.01k
            ? 
"E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
96
2.01k
            : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
97
45
  else
98
45
    resetDataLayout(
99
45
        BigEndian
100
45
            ? 
"E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
101
45
            : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
102
3.42k
103
3.42k
  // FIXME: Override "preferred align" for double and long long.
104
3.42k
}
105
106
3.76k
void ARMTargetInfo::setArchInfo() {
107
3.76k
  StringRef ArchName = getTriple().getArchName();
108
3.76k
109
3.76k
  ArchISA = llvm::ARM::parseArchISA(ArchName);
110
3.76k
  CPU = llvm::ARM::getDefaultCPU(ArchName);
111
3.76k
  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName);
112
3.76k
  if (AK != llvm::ARM::ArchKind::INVALID)
113
3.64k
    ArchKind = AK;
114
3.76k
  setArchInfo(ArchKind);
115
3.76k
}
116
117
6.01k
void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
118
6.01k
  StringRef SubArch;
119
6.01k
120
6.01k
  // cache TargetParser info
121
6.01k
  ArchKind = Kind;
122
6.01k
  SubArch = llvm::ARM::getSubArch(ArchKind);
123
6.01k
  ArchProfile = llvm::ARM::parseArchProfile(SubArch);
124
6.01k
  ArchVersion = llvm::ARM::parseArchVersion(SubArch);
125
6.01k
126
6.01k
  // cache CPU related strings
127
6.01k
  CPUAttr = getCPUAttr();
128
6.01k
  CPUProfile = getCPUProfile();
129
6.01k
}
130
131
7.04k
void ARMTargetInfo::setAtomic() {
132
7.04k
  // when triple does not specify a sub arch,
133
7.04k
  // then we are not using inline atomics
134
7.04k
  bool ShouldUseInlineAtomic =
135
7.04k
      (ArchISA == llvm::ARM::ISAKind::ARM && 
ArchVersion >= 6880
) ||
136
7.04k
      
(6.38k
ArchISA == llvm::ARM::ISAKind::THUMB6.38k
&&
ArchVersion >= 76.16k
);
137
7.04k
  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
138
7.04k
  if (ArchProfile == llvm::ARM::ProfileKind::M) {
139
1.70k
    MaxAtomicPromoteWidth = 32;
140
1.70k
    if (ShouldUseInlineAtomic)
141
1.32k
      MaxAtomicInlineWidth = 32;
142
5.34k
  } else {
143
5.34k
    MaxAtomicPromoteWidth = 64;
144
5.34k
    if (ShouldUseInlineAtomic)
145
5.09k
      MaxAtomicInlineWidth = 64;
146
5.34k
  }
147
7.04k
}
148
149
4.98k
bool ARMTargetInfo::hasMVE() const {
150
4.98k
  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && 
MVE != 010
;
151
4.98k
}
152
153
3
bool ARMTargetInfo::hasMVEFloat() const {
154
3
  return hasMVE() && (MVE & MVE_FP);
155
3
}
156
157
10.9k
bool ARMTargetInfo::isThumb() const {
158
10.9k
  return ArchISA == llvm::ARM::ISAKind::THUMB;
159
10.9k
}
160
161
409
bool ARMTargetInfo::supportsThumb() const {
162
409
  return CPUAttr.count('T') || 
ArchVersion >= 6244
;
163
409
}
164
165
6.90k
bool ARMTargetInfo::supportsThumb2() const {
166
6.90k
  return CPUAttr.equals("6T2") ||
167
6.90k
         
(6.90k
ArchVersion >= 76.90k
&&
!CPUAttr.equals("8M_BASE")6.28k
);
168
6.90k
}
169
170
6.01k
StringRef ARMTargetInfo::getCPUAttr() const {
171
6.01k
  // For most sub-arches, the build attribute CPU name is enough.
172
6.01k
  // For Cortex variants, it's slightly different.
173
6.01k
  switch (ArchKind) {
174
6.01k
  default:
175
999
    return llvm::ARM::getCPUAttr(ArchKind);
176
6.01k
  case llvm::ARM::ArchKind::ARMV6M:
177
379
    return "6M";
178
6.01k
  case llvm::ARM::ArchKind::ARMV7S:
179
938
    return "7S";
180
6.01k
  case llvm::ARM::ArchKind::ARMV7A:
181
2.10k
    return "7A";
182
6.01k
  case llvm::ARM::ArchKind::ARMV7R:
183
57
    return "7R";
184
6.01k
  case llvm::ARM::ArchKind::ARMV7M:
185
439
    return "7M";
186
6.01k
  case llvm::ARM::ArchKind::ARMV7EM:
187
836
    return "7EM";
188
6.01k
  case llvm::ARM::ArchKind::ARMV7VE:
189
7
    return "7VE";
190
6.01k
  case llvm::ARM::ArchKind::ARMV8A:
191
162
    return "8A";
192
6.01k
  case llvm::ARM::ArchKind::ARMV8_1A:
193
3
    return "8_1A";
194
6.01k
  case llvm::ARM::ArchKind::ARMV8_2A:
195
29
    return "8_2A";
196
6.01k
  case llvm::ARM::ArchKind::ARMV8_3A:
197
1
    return "8_3A";
198
6.01k
  case llvm::ARM::ArchKind::ARMV8_4A:
199
16
    return "8_4A";
200
6.01k
  case llvm::ARM::ArchKind::ARMV8_5A:
201
1
    return "8_5A";
202
6.01k
  case llvm::ARM::ArchKind::ARMV8MBaseline:
203
10
    return "8M_BASE";
204
6.01k
  case llvm::ARM::ArchKind::ARMV8MMainline:
205
16
    return "8M_MAIN";
206
6.01k
  case llvm::ARM::ArchKind::ARMV8R:
207
10
    return "8R";
208
6.01k
  case llvm::ARM::ArchKind::ARMV8_1MMainline:
209
7
    return "8_1M_MAIN";
210
6.01k
  }
211
6.01k
}
212
213
6.01k
StringRef ARMTargetInfo::getCPUProfile() const {
214
6.01k
  switch (ArchProfile) {
215
6.01k
  case llvm::ARM::ProfileKind::A:
216
3.02k
    return "A";
217
6.01k
  case llvm::ARM::ProfileKind::R:
218
67
    return "R";
219
6.01k
  case llvm::ARM::ProfileKind::M:
220
1.68k
    return "M";
221
6.01k
  default:
222
1.24k
    return "";
223
6.01k
  }
224
6.01k
}
225
226
ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
227
                             const TargetOptions &Opts)
228
    : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
229
3.76k
      HW_FP(0) {
230
3.76k
  bool IsOpenBSD = Triple.isOSOpenBSD();
231
3.76k
  bool IsNetBSD = Triple.isOSNetBSD();
232
3.76k
233
3.76k
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
234
3.76k
  // environment where size_t is `unsigned long` rather than `unsigned int`
235
3.76k
236
3.76k
  PtrDiffType = IntPtrType =
237
3.76k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
||
IsOpenBSD766
||
238
3.76k
       
IsNetBSD761
)
239
3.76k
          ? 
SignedLong3.00k
240
3.76k
          : 
SignedInt754
;
241
3.76k
242
3.76k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
||
IsOpenBSD766
||
243
3.76k
              
IsNetBSD761
)
244
3.76k
                 ? 
UnsignedLong3.00k
245
3.76k
                 : 
UnsignedInt754
;
246
3.76k
247
3.76k
  // ptrdiff_t is inconsistent on Darwin
248
3.76k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
) &&
249
3.76k
      
!Triple.isWatchABI()2.99k
)
250
2.30k
    PtrDiffType = SignedInt;
251
3.76k
252
3.76k
  // Cache arch related info.
253
3.76k
  setArchInfo();
254
3.76k
255
3.76k
  // {} in inline assembly are neon specifiers, not assembly variant
256
3.76k
  // specifiers.
257
3.76k
  NoAsmVariants = true;
258
3.76k
259
3.76k
  // FIXME: This duplicates code from the driver that sets the -target-abi
260
3.76k
  // option - this code is used if -target-abi isn't passed and should
261
3.76k
  // be unified in some way.
262
3.76k
  if (Triple.isOSBinFormatMachO()) {
263
2.99k
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
264
2.99k
    // the frontend matches that.
265
2.99k
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
266
2.99k
        
Triple.getOS() == llvm::Triple::UnknownOS2.55k
||
267
2.99k
        
ArchProfile == llvm::ARM::ProfileKind::M1.75k
) {
268
1.23k
      setABI("aapcs");
269
1.75k
    } else if (Triple.isWatchABI()) {
270
693
      setABI("aapcs16");
271
1.06k
    } else {
272
1.06k
      setABI("apcs-gnu");
273
1.06k
    }
274
2.99k
  } else 
if (766
Triple.isOSWindows()766
) {
275
93
    // FIXME: this is invalid for WindowsCE
276
93
    setABI("aapcs");
277
673
  } else {
278
673
    // Select the default based on the platform.
279
673
    switch (Triple.getEnvironment()) {
280
673
    case llvm::Triple::Android:
281
215
    case llvm::Triple::GNUEABI:
282
215
    case llvm::Triple::GNUEABIHF:
283
215
    case llvm::Triple::MuslEABI:
284
215
    case llvm::Triple::MuslEABIHF:
285
215
      setABI("aapcs-linux");
286
215
      break;
287
243
    case llvm::Triple::EABIHF:
288
243
    case llvm::Triple::EABI:
289
243
      setABI("aapcs");
290
243
      break;
291
243
    case llvm::Triple::GNU:
292
29
      setABI("apcs-gnu");
293
29
      break;
294
243
    default:
295
186
      if (IsNetBSD)
296
0
        setABI("apcs-gnu");
297
186
      else if (IsOpenBSD)
298
2
        setABI("aapcs-linux");
299
184
      else
300
184
        setABI("aapcs");
301
186
      break;
302
3.76k
    }
303
3.76k
  }
304
3.76k
305
3.76k
  // ARM targets default to using the ARM C++ ABI.
306
3.76k
  TheCXXABI.set(TargetCXXABI::GenericARM);
307
3.76k
308
3.76k
  // ARM has atomics up to 8 bytes
309
3.76k
  setAtomic();
310
3.76k
311
3.76k
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
312
3.76k
  if (IsAAPCS && 
(Triple.getEnvironment() != llvm::Triple::Android)1.97k
)
313
1.96k
    MaxVectorAlign = 64;
314
3.76k
315
3.76k
  // Do force alignment of members that follow zero length bitfields.  If
316
3.76k
  // the alignment of the zero-length bitfield is greater than the member
317
3.76k
  // that follows it, `bar', `bar' will be aligned as the  type of the
318
3.76k
  // zero length bitfield.
319
3.76k
  UseZeroLengthBitfieldAlignment = true;
320
3.76k
321
3.76k
  if (Triple.getOS() == llvm::Triple::Linux ||
322
3.76k
      
Triple.getOS() == llvm::Triple::UnknownOS3.50k
)
323
1.44k
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
324
1.44k
                           ? 
"\01__gnu_mcount_nc"9
325
1.44k
                           : 
"\01mcount"1.43k
;
326
3.76k
327
3.76k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
328
3.76k
}
clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
229
3.76k
      HW_FP(0) {
230
3.76k
  bool IsOpenBSD = Triple.isOSOpenBSD();
231
3.76k
  bool IsNetBSD = Triple.isOSNetBSD();
232
3.76k
233
3.76k
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
234
3.76k
  // environment where size_t is `unsigned long` rather than `unsigned int`
235
3.76k
236
3.76k
  PtrDiffType = IntPtrType =
237
3.76k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
||
IsOpenBSD766
||
238
3.76k
       
IsNetBSD761
)
239
3.76k
          ? 
SignedLong3.00k
240
3.76k
          : 
SignedInt754
;
241
3.76k
242
3.76k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
||
IsOpenBSD766
||
243
3.76k
              
IsNetBSD761
)
244
3.76k
                 ? 
UnsignedLong3.00k
245
3.76k
                 : 
UnsignedInt754
;
246
3.76k
247
3.76k
  // ptrdiff_t is inconsistent on Darwin
248
3.76k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.56k
) &&
249
3.76k
      
!Triple.isWatchABI()2.99k
)
250
2.30k
    PtrDiffType = SignedInt;
251
3.76k
252
3.76k
  // Cache arch related info.
253
3.76k
  setArchInfo();
254
3.76k
255
3.76k
  // {} in inline assembly are neon specifiers, not assembly variant
256
3.76k
  // specifiers.
257
3.76k
  NoAsmVariants = true;
258
3.76k
259
3.76k
  // FIXME: This duplicates code from the driver that sets the -target-abi
260
3.76k
  // option - this code is used if -target-abi isn't passed and should
261
3.76k
  // be unified in some way.
262
3.76k
  if (Triple.isOSBinFormatMachO()) {
263
2.99k
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
264
2.99k
    // the frontend matches that.
265
2.99k
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
266
2.99k
        
Triple.getOS() == llvm::Triple::UnknownOS2.55k
||
267
2.99k
        
ArchProfile == llvm::ARM::ProfileKind::M1.75k
) {
268
1.23k
      setABI("aapcs");
269
1.75k
    } else if (Triple.isWatchABI()) {
270
693
      setABI("aapcs16");
271
1.06k
    } else {
272
1.06k
      setABI("apcs-gnu");
273
1.06k
    }
274
2.99k
  } else 
if (766
Triple.isOSWindows()766
) {
275
93
    // FIXME: this is invalid for WindowsCE
276
93
    setABI("aapcs");
277
673
  } else {
278
673
    // Select the default based on the platform.
279
673
    switch (Triple.getEnvironment()) {
280
673
    case llvm::Triple::Android:
281
215
    case llvm::Triple::GNUEABI:
282
215
    case llvm::Triple::GNUEABIHF:
283
215
    case llvm::Triple::MuslEABI:
284
215
    case llvm::Triple::MuslEABIHF:
285
215
      setABI("aapcs-linux");
286
215
      break;
287
243
    case llvm::Triple::EABIHF:
288
243
    case llvm::Triple::EABI:
289
243
      setABI("aapcs");
290
243
      break;
291
243
    case llvm::Triple::GNU:
292
29
      setABI("apcs-gnu");
293
29
      break;
294
243
    default:
295
186
      if (IsNetBSD)
296
0
        setABI("apcs-gnu");
297
186
      else if (IsOpenBSD)
298
2
        setABI("aapcs-linux");
299
184
      else
300
184
        setABI("aapcs");
301
186
      break;
302
3.76k
    }
303
3.76k
  }
304
3.76k
305
3.76k
  // ARM targets default to using the ARM C++ ABI.
306
3.76k
  TheCXXABI.set(TargetCXXABI::GenericARM);
307
3.76k
308
3.76k
  // ARM has atomics up to 8 bytes
309
3.76k
  setAtomic();
310
3.76k
311
3.76k
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
312
3.76k
  if (IsAAPCS && 
(Triple.getEnvironment() != llvm::Triple::Android)1.97k
)
313
1.96k
    MaxVectorAlign = 64;
314
3.76k
315
3.76k
  // Do force alignment of members that follow zero length bitfields.  If
316
3.76k
  // the alignment of the zero-length bitfield is greater than the member
317
3.76k
  // that follows it, `bar', `bar' will be aligned as the  type of the
318
3.76k
  // zero length bitfield.
319
3.76k
  UseZeroLengthBitfieldAlignment = true;
320
3.76k
321
3.76k
  if (Triple.getOS() == llvm::Triple::Linux ||
322
3.76k
      
Triple.getOS() == llvm::Triple::UnknownOS3.50k
)
323
1.44k
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
324
1.44k
                           ? 
"\01__gnu_mcount_nc"9
325
1.44k
                           : 
"\01mcount"1.43k
;
326
3.76k
327
3.76k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
328
3.76k
}
Unexecuted instantiation: clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
329
330
2.48k
StringRef ARMTargetInfo::getABI() const { return ABI; }
331
332
7.03k
bool ARMTargetInfo::setABI(const std::string &Name) {
333
7.03k
  ABI = Name;
334
7.03k
335
7.03k
  // The defaults (above) are for AAPCS, check if we need to change them.
336
7.03k
  //
337
7.03k
  // FIXME: We need support for -meabi... we could just mangle it into the
338
7.03k
  // name.
339
7.03k
  if (Name == "apcs-gnu" || 
Name == "aapcs16"4.98k
) {
340
3.42k
    setABIAPCS(Name == "aapcs16");
341
3.42k
    return true;
342
3.42k
  }
343
3.61k
  if (Name == "aapcs" || 
Name == "aapcs-vfp"307
||
Name == "aapcs-linux"306
) {
344
3.61k
    setABIAAPCS();
345
3.61k
    return true;
346
3.61k
  }
347
0
  return false;
348
0
}
349
350
// FIXME: This should be based on Arch attributes, not CPU names.
351
bool ARMTargetInfo::initFeatureMap(
352
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
353
3.79k
    const std::vector<std::string> &FeaturesVec) const {
354
3.79k
355
3.79k
  std::string ArchFeature;
356
3.79k
  std::vector<StringRef> TargetFeatures;
357
3.79k
  llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName());
358
3.79k
359
3.79k
  // Map the base architecture to an appropriate target feature, so we don't
360
3.79k
  // rely on the target triple.
361
3.79k
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU);
362
3.79k
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
363
1.54k
    CPUArch = Arch;
364
3.79k
  if (CPUArch != llvm::ARM::ArchKind::INVALID) {
365
3.67k
    ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str();
366
3.67k
    TargetFeatures.push_back(ArchFeature);
367
3.67k
  }
368
3.79k
369
3.79k
  // get default FPU features
370
3.79k
  unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
371
3.79k
  llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
372
3.79k
373
3.79k
  // get default Extension features
374
3.79k
  unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
375
3.79k
  llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
376
3.79k
377
3.79k
  for (auto Feature : TargetFeatures)
378
128k
    if (Feature[0] == '+')
379
48.0k
      Features[Feature.drop_front(1)] = true;
380
3.79k
381
3.79k
  // Enable or disable thumb-mode explicitly per function to enable mixed
382
3.79k
  // ARM and Thumb code generation.
383
3.79k
  if (isThumb())
384
3.18k
    Features["thumb-mode"] = true;
385
611
  else
386
611
    Features["thumb-mode"] = false;
387
3.79k
388
3.79k
  // Convert user-provided arm and thumb GNU target attributes to
389
3.79k
  // [-|+]thumb-mode target features respectively.
390
3.79k
  std::vector<std::string> UpdatedFeaturesVec;
391
31.7k
  for (const auto &Feature : FeaturesVec) {
392
31.7k
    // Skip soft-float-abi; it's something we only use to initialize a bit of
393
31.7k
    // class state, and is otherwise unrecognized.
394
31.7k
    if (Feature == "+soft-float-abi")
395
2.08k
      continue;
396
29.7k
397
29.7k
    StringRef FixedFeature;
398
29.7k
    if (Feature == "+arm")
399
8
      FixedFeature = "-thumb-mode";
400
29.7k
    else if (Feature == "+thumb")
401
8
      FixedFeature = "+thumb-mode";
402
29.6k
    else
403
29.6k
      FixedFeature = Feature;
404
29.7k
    UpdatedFeaturesVec.push_back(FixedFeature.str());
405
29.7k
  }
406
3.79k
407
3.79k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
408
3.79k
}
409
410
411
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
412
3.75k
                                         DiagnosticsEngine &Diags) {
413
3.75k
  FPU = 0;
414
3.75k
  MVE = 0;
415
3.75k
  CRC = 0;
416
3.75k
  Crypto = 0;
417
3.75k
  DSP = 0;
418
3.75k
  Unaligned = 1;
419
3.75k
  SoftFloat = false;
420
3.75k
  // Note that SoftFloatABI is initialized in our constructor.
421
3.75k
  HWDiv = 0;
422
3.75k
  DotProd = 0;
423
3.75k
  HasFloat16 = true;
424
3.75k
425
3.75k
  // This does not diagnose illegal cases like having both
426
3.75k
  // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
427
75.1k
  for (const auto &Feature : Features) {
428
75.1k
    if (Feature == "+soft-float") {
429
923
      SoftFloat = true;
430
74.2k
    } else if (Feature == "+vfp2sp" || 
Feature == "+vfp2d16sp"72.1k
||
431
74.2k
               
Feature == "+vfp2"69.8k
||
Feature == "+vfp2d16"67.8k
) {
432
8.48k
      FPU |= VFP2FPU;
433
8.48k
      HW_FP |= HW_FP_SP;
434
8.48k
      if (Feature == "+vfp2" || 
Feature == "+vfp2d16"6.43k
)
435
4.13k
          HW_FP |= HW_FP_DP;
436
65.7k
    } else if (Feature == "+vfp3sp" || 
Feature == "+vfp3d16sp"63.7k
||
437
65.7k
               
Feature == "+vfp3"61.4k
||
Feature == "+vfp3d16"59.3k
) {
438
8.42k
      FPU |= VFP3FPU;
439
8.42k
      HW_FP |= HW_FP_SP;
440
8.42k
      if (Feature == "+vfp3" || 
Feature == "+vfp3d16"6.38k
)
441
4.10k
          HW_FP |= HW_FP_DP;
442
57.3k
    } else if (Feature == "+vfp4sp" || 
Feature == "+vfp4d16sp"56.0k
||
443
57.3k
               
Feature == "+vfp4"54.5k
||
Feature == "+vfp4d16"53.2k
) {
444
5.37k
      FPU |= VFP4FPU;
445
5.37k
      HW_FP |= HW_FP_SP | HW_FP_HP;
446
5.37k
      if (Feature == "+vfp4" || 
Feature == "+vfp4d16"4.09k
)
447
2.57k
          HW_FP |= HW_FP_DP;
448
51.9k
    } else if (Feature == "+fp-armv8sp" || 
Feature == "+fp-armv8d16sp"51.8k
||
449
51.9k
               
Feature == "+fp-armv8"51.7k
||
Feature == "+fp-armv8d16"51.6k
) {
450
410
      FPU |= FPARMV8;
451
410
      HW_FP |= HW_FP_SP | HW_FP_HP;
452
410
      if (Feature == "+fp-armv8" || 
Feature == "+fp-armv8d16"314
)
453
200
          HW_FP |= HW_FP_DP;
454
51.5k
    } else if (Feature == "+neon") {
455
2.05k
      FPU |= NeonFPU;
456
2.05k
      HW_FP |= HW_FP_SP;
457
49.4k
    } else if (Feature == "+hwdiv") {
458
2.02k
      HWDiv |= HWDivThumb;
459
47.4k
    } else if (Feature == "+hwdiv-arm") {
460
1.35k
      HWDiv |= HWDivARM;
461
46.1k
    } else if (Feature == "+crc") {
462
138
      CRC = 1;
463
45.9k
    } else if (Feature == "+crypto") {
464
67
      Crypto = 1;
465
45.8k
    } else if (Feature == "+dsp") {
466
2.80k
      DSP = 1;
467
43.0k
    } else if (Feature == "+fp64") {
468
2.07k
      HW_FP |= HW_FP_DP;
469
41.0k
    } else if (Feature == "+8msecext") {
470
5
      if (CPUProfile != "M" || ArchVersion != 8) {
471
1
        Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
472
1
        return false;
473
1
      }
474
41.0k
    } else if (Feature == "+strict-align") {
475
1.61k
      Unaligned = 0;
476
39.3k
    } else if (Feature == "+fp16") {
477
1.53k
      HW_FP |= HW_FP_HP;
478
37.8k
    } else if (Feature == "+fullfp16") {
479
31
      HasLegalHalfType = true;
480
37.8k
    } else if (Feature == "+dotprod") {
481
21
      DotProd = true;
482
37.8k
    } else if (Feature == "+mve") {
483
2
      DSP = 1;
484
2
      MVE |= MVE_INT;
485
37.8k
    } else if (Feature == "+mve.fp") {
486
1
      DSP = 1;
487
1
      HasLegalHalfType = true;
488
1
      FPU |= FPARMV8;
489
1
      MVE |= MVE_INT | MVE_FP;
490
1
      HW_FP |= HW_FP_SP | HW_FP_HP;
491
1
    }
492
75.1k
  }
493
3.75k
494
3.75k
  switch (ArchVersion) {
495
3.75k
  case 6:
496
235
    if (ArchProfile == llvm::ARM::ProfileKind::M)
497
191
      LDREX = 0;
498
44
    else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
499
6
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
500
38
    else
501
38
      LDREX = LDREX_W;
502
235
    break;
503
3.75k
  case 7:
504
3.16k
    if (ArchProfile == llvm::ARM::ProfileKind::M)
505
641
      LDREX = LDREX_W | LDREX_H | LDREX_B;
506
2.52k
    else
507
2.52k
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
508
3.16k
    break;
509
3.75k
  case 8:
510
183
    LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
511
3.75k
  }
512
3.75k
513
3.75k
  if (!(FPU & NeonFPU) && 
FPMath == FP_Neon1.70k
) {
514
2
    Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
515
2
    return false;
516
2
  }
517
3.75k
518
3.75k
  if (FPMath == FP_Neon)
519
1
    Features.push_back("+neonfp");
520
3.75k
  else if (FPMath == FP_VFP)
521
5
    Features.push_back("-neonfp");
522
3.75k
523
3.75k
  return true;
524
3.75k
}
525
526
1.23k
bool ARMTargetInfo::hasFeature(StringRef Feature) const {
527
1.23k
  return llvm::StringSwitch<bool>(Feature)
528
1.23k
      .Case("arm", true)
529
1.23k
      .Case("aarch32", true)
530
1.23k
      .Case("softfloat", SoftFloat)
531
1.23k
      .Case("thumb", isThumb())
532
1.23k
      .Case("neon", (FPU & NeonFPU) && 
!SoftFloat963
)
533
1.23k
      .Case("vfp", FPU && 
!SoftFloat972
)
534
1.23k
      .Case("hwdiv", HWDiv & HWDivThumb)
535
1.23k
      .Case("hwdiv-arm", HWDiv & HWDivARM)
536
1.23k
      .Case("mve", hasMVE())
537
1.23k
      .Default(false);
538
1.23k
}
539
540
0
bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
541
0
  return Name == "generic" ||
542
0
         llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
543
0
}
544
545
2
void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
546
2
  llvm::ARM::fillValidCPUArchList(Values);
547
2
}
548
549
3.28k
bool ARMTargetInfo::setCPU(const std::string &Name) {
550
3.28k
  if (Name != "generic")
551
2.25k
    setArchInfo(llvm::ARM::parseCPUArch(Name));
552
3.28k
553
3.28k
  if (ArchKind == llvm::ARM::ArchKind::INVALID)
554
2
    return false;
555
3.28k
  setAtomic();
556
3.28k
  CPU = Name;
557
3.28k
  return true;
558
3.28k
}
559
560
8
bool ARMTargetInfo::setFPMath(StringRef Name) {
561
8
  if (Name == "neon") {
562
3
    FPMath = FP_Neon;
563
3
    return true;
564
5
  } else if (Name == "vfp" || 
Name == "vfp2"3
||
Name == "vfp3"2
||
565
5
             
Name == "vfp4"1
) {
566
5
    FPMath = FP_VFP;
567
5
    return true;
568
5
  }
569
0
  return false;
570
0
}
571
572
void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
573
24
                                            MacroBuilder &Builder) const {
574
24
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
575
24
}
576
577
void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
578
21
                                            MacroBuilder &Builder) const {
579
21
  // Also include the ARMv8.1-A defines
580
21
  getTargetDefinesARMV81A(Opts, Builder);
581
21
}
582
583
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
584
3.74k
                                     MacroBuilder &Builder) const {
585
3.74k
  // Target identification.
586
3.74k
  Builder.defineMacro("__arm");
587
3.74k
  Builder.defineMacro("__arm__");
588
3.74k
  // For bare-metal none-eabi.
589
3.74k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
590
3.74k
      
(1.17k
getTriple().getEnvironment() == llvm::Triple::EABI1.17k
||
591
1.17k
       
getTriple().getEnvironment() == llvm::Triple::EABIHF976
))
592
211
    Builder.defineMacro("__ELF__");
593
3.74k
594
3.74k
  // Target properties.
595
3.74k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
596
3.74k
597
3.74k
  // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
598
3.74k
  // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
599
3.74k
  if (getTriple().isWatchABI())
600
693
    Builder.defineMacro("__ARM_ARCH_7K__", "2");
601
3.74k
602
3.74k
  if (!CPUAttr.empty())
603
3.74k
    Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
604
3.74k
605
3.74k
  // ACLE 6.4.1 ARM/Thumb instruction set architecture
606
3.74k
  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
607
3.74k
  Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
608
3.74k
609
3.74k
  if (ArchVersion >= 8) {
610
183
    // ACLE 6.5.7 Crypto Extension
611
183
    if (Crypto)
612
65
      Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
613
183
    // ACLE 6.5.8 CRC32 Extension
614
183
    if (CRC)
615
138
      Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
616
183
    // ACLE 6.5.10 Numeric Maximum and Minimum
617
183
    Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
618
183
    // ACLE 6.5.9 Directed Rounding
619
183
    Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
620
183
  }
621
3.74k
622
3.74k
  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
623
3.74k
  // is not defined for the M-profile.
624
3.74k
  // NOTE that the default profile is assumed to be 'A'
625
3.74k
  if (CPUProfile.empty() || 
ArchProfile != llvm::ARM::ProfileKind::M3.06k
)
626
2.89k
    Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
627
3.74k
628
3.74k
  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
629
3.74k
  // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the
630
3.74k
  // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
631
3.74k
  // v7 and v8 architectures excluding v8-M Baseline.
632
3.74k
  if (supportsThumb2())
633
3.33k
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
634
409
  else if (supportsThumb())
635
403
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
636
3.74k
637
3.74k
  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
638
3.74k
  // instruction set such as ARM or Thumb.
639
3.74k
  Builder.defineMacro("__ARM_32BIT_STATE", "1");
640
3.74k
641
3.74k
  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
642
3.74k
643
3.74k
  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
644
3.74k
  if (!CPUProfile.empty())
645
3.06k
    Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
646
3.74k
647
3.74k
  // ACLE 6.4.3 Unaligned access supported in hardware
648
3.74k
  if (Unaligned)
649
2.13k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
650
3.74k
651
3.74k
  // ACLE 6.4.4 LDREX/STREX
652
3.74k
  if (LDREX)
653
3.38k
    Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
654
3.74k
655
3.74k
  // ACLE 6.4.5 CLZ
656
3.74k
  if (ArchVersion == 5 || 
(3.73k
ArchVersion == 63.73k
&&
CPUProfile != "M"234
) ||
657
3.74k
      
ArchVersion > 63.69k
)
658
3.40k
    Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
659
3.74k
660
3.74k
  // ACLE 6.5.1 Hardware Floating Point
661
3.74k
  if (HW_FP)
662
2.33k
    Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
663
3.74k
664
3.74k
  // ACLE predefines.
665
3.74k
  Builder.defineMacro("__ARM_ACLE", "200");
666
3.74k
667
3.74k
  // FP16 support (we currently only support IEEE format).
668
3.74k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
669
3.74k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
670
3.74k
671
3.74k
  // ACLE 6.5.3 Fused multiply-accumulate (FMA)
672
3.74k
  if (ArchVersion >= 7 && 
(FPU & VFP4FPU)3.34k
)
673
1.50k
    Builder.defineMacro("__ARM_FEATURE_FMA", "1");
674
3.74k
675
3.74k
  // Subtarget options.
676
3.74k
677
3.74k
  // FIXME: It's more complicated than this and we don't really support
678
3.74k
  // interworking.
679
3.74k
  // Windows on ARM does not "support" interworking
680
3.74k
  if (5 <= ArchVersion && 
ArchVersion <= 83.59k
&&
!getTriple().isOSWindows()3.59k
)
681
3.50k
    Builder.defineMacro("__THUMB_INTERWORK__");
682
3.74k
683
3.74k
  if (ABI == "aapcs" || 
ABI == "aapcs-linux"1.97k
||
ABI == "aapcs-vfp"1.76k
) {
684
1.98k
    // Embedded targets on Darwin follow AAPCS, but not EABI.
685
1.98k
    // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
686
1.98k
    if (!getTriple().isOSBinFormatMachO() && 
!getTriple().isOSWindows()740
)
687
647
      Builder.defineMacro("__ARM_EABI__");
688
1.98k
    Builder.defineMacro("__ARM_PCS", "1");
689
1.98k
  }
690
3.74k
691
3.74k
  if ((!SoftFloat && 
!SoftFloatABI2.82k
) ||
ABI == "aapcs-vfp"2.08k
||
ABI == "aapcs16"2.08k
)
692
1.65k
    Builder.defineMacro("__ARM_PCS_VFP", "1");
693
3.74k
694
3.74k
  if (SoftFloat)
695
923
    Builder.defineMacro("__SOFTFP__");
696
3.74k
697
3.74k
  // ACLE position independent code macros.
698
3.74k
  if (Opts.ROPI)
699
2
    Builder.defineMacro("__ARM_ROPI", "1");
700
3.74k
  if (Opts.RWPI)
701
2
    Builder.defineMacro("__ARM_RWPI", "1");
702
3.74k
703
3.74k
  if (ArchKind == llvm::ARM::ArchKind::XSCALE)
704
0
    Builder.defineMacro("__XSCALE__");
705
3.74k
706
3.74k
  if (isThumb()) {
707
3.15k
    Builder.defineMacro("__THUMBEL__");
708
3.15k
    Builder.defineMacro("__thumb__");
709
3.15k
    if (supportsThumb2())
710
2.94k
      Builder.defineMacro("__thumb2__");
711
3.15k
  }
712
3.74k
713
3.74k
  // ACLE 6.4.9 32-bit SIMD instructions
714
3.74k
  if ((CPUProfile != "M" && 
ArchVersion >= 62.89k
) ||
(1.02k
CPUProfile == "M"1.02k
&&
DSP858
))
715
3.14k
    Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
716
3.74k
717
3.74k
  // ACLE 6.4.10 Hardware Integer Divide
718
3.74k
  if (((HWDiv & HWDivThumb) && 
isThumb()2.02k
) ||
719
3.74k
      
(1.87k
(HWDiv & HWDivARM)1.87k
&&
!isThumb()143
)) {
720
2.01k
    Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
721
2.01k
    Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
722
2.01k
  }
723
3.74k
724
3.74k
  // Note, this is always on in gcc, even though it doesn't make sense.
725
3.74k
  Builder.defineMacro("__APCS_32__");
726
3.74k
727
3.74k
  if (FPUModeIsVFP((FPUMode)FPU)) {
728
2.33k
    Builder.defineMacro("__VFP_FP__");
729
2.33k
    if (FPU & VFP2FPU)
730
2.30k
      Builder.defineMacro("__ARM_VFPV2__");
731
2.33k
    if (FPU & VFP3FPU)
732
2.28k
      Builder.defineMacro("__ARM_VFPV3__");
733
2.33k
    if (FPU & VFP4FPU)
734
1.51k
      Builder.defineMacro("__ARM_VFPV4__");
735
2.33k
    if (FPU & FPARMV8)
736
114
      Builder.defineMacro("__ARM_FPV5__");
737
2.33k
  }
738
3.74k
739
3.74k
  // This only gets set when Neon instructions are actually available, unlike
740
3.74k
  // the VFP define, hence the soft float and arch check. This is subtly
741
3.74k
  // different from gcc, we follow the intent which was that it should be set
742
3.74k
  // when Neon instructions are actually available.
743
3.74k
  if ((FPU & NeonFPU) && 
!SoftFloat2.05k
&&
ArchVersion >= 72.05k
) {
744
2.04k
    Builder.defineMacro("__ARM_NEON", "1");
745
2.04k
    Builder.defineMacro("__ARM_NEON__");
746
2.04k
    // current AArch32 NEON implementations do not support double-precision
747
2.04k
    // floating-point even when it is present in VFP.
748
2.04k
    Builder.defineMacro("__ARM_NEON_FP",
749
2.04k
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
750
2.04k
  }
751
3.74k
752
3.74k
  if (hasMVE()) {
753
3
    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? 
"3"1
:
"1"2
);
754
3
  }
755
3.74k
756
3.74k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
757
3.74k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
43.74k
));
758
3.74k
759
3.74k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"3.74k
);
760
3.74k
761
3.74k
  // CMSE
762
3.74k
  if (ArchVersion == 8 && 
ArchProfile == llvm::ARM::ProfileKind::M183
)
763
26
    Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? 
"3"4
:
"1"22
);
764
3.74k
765
3.74k
  if (ArchVersion >= 6 && 
CPUAttr != "6M"3.57k
&&
CPUAttr != "8M_BASE"3.38k
) {
766
3.37k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
767
3.37k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
768
3.37k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
769
3.37k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
770
3.37k
  }
771
3.74k
772
3.74k
  // ACLE 6.4.7 DSP instructions
773
3.74k
  if (DSP) {
774
2.80k
    Builder.defineMacro("__ARM_FEATURE_DSP", "1");
775
2.80k
  }
776
3.74k
777
3.74k
  // ACLE 6.4.8 Saturation instructions
778
3.74k
  bool SAT = false;
779
3.74k
  if ((ArchVersion == 6 && 
CPUProfile != "M"234
) ||
ArchVersion > 63.70k
) {
780
3.38k
    Builder.defineMacro("__ARM_FEATURE_SAT", "1");
781
3.38k
    SAT = true;
782
3.38k
  }
783
3.74k
784
3.74k
  // ACLE 6.4.6 Q (saturation) flag
785
3.74k
  if (DSP || 
SAT944
)
786
3.38k
    Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
787
3.74k
788
3.74k
  if (Opts.UnsafeFPMath)
789
2
    Builder.defineMacro("__ARM_FP_FAST", "1");
790
3.74k
791
3.74k
  // Armv8.2-A FP16 vector intrinsic
792
3.74k
  if ((FPU & NeonFPU) && 
HasLegalHalfType2.05k
)
793
21
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
794
3.74k
795
3.74k
  // Armv8.2-A FP16 scalar intrinsics
796
3.74k
  if (HasLegalHalfType)
797
31
    Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
798
3.74k
799
3.74k
  // Armv8.2-A dot product intrinsics
800
3.74k
  if (DotProd)
801
21
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
802
3.74k
803
3.74k
  switch (ArchKind) {
804
3.74k
  default:
805
3.72k
    break;
806
3.74k
  case llvm::ARM::ArchKind::ARMV8_1A:
807
3
    getTargetDefinesARMV81A(Opts, Builder);
808
3
    break;
809
3.74k
  case llvm::ARM::ArchKind::ARMV8_2A:
810
21
    getTargetDefinesARMV82A(Opts, Builder);
811
21
    break;
812
3.74k
  }
813
3.74k
}
814
815
const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
816
#define BUILTIN(ID, TYPE, ATTRS)                                               \
817
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
818
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
819
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
820
#include "clang/Basic/BuiltinsNEON.def"
821
822
#define BUILTIN(ID, TYPE, ATTRS)                                               \
823
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
824
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
825
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
826
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
827
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
828
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
829
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
830
#include "clang/Basic/BuiltinsARM.def"
831
};
832
833
3.74k
ArrayRef<Builtin::Info> ARMTargetInfo::getTargetBuiltins() const {
834
3.74k
  return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin -
835
3.74k
                                             Builtin::FirstTSBuiltin);
836
3.74k
}
837
838
620
bool ARMTargetInfo::isCLZForZeroUndef() const { return false; }
839
2.60k
TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const {
840
2.60k
  return IsAAPCS
841
2.60k
             ? 
AAPCSABIBuiltinVaList1.23k
842
2.60k
             : 
(getTriple().isWatchABI() 1.36k
?
TargetInfo::CharPtrBuiltinVaList520
843
1.36k
                                         : 
TargetInfo::VoidPtrBuiltinVaList847
);
844
2.60k
}
845
846
const char *const ARMTargetInfo::GCCRegNames[] = {
847
    // Integer registers
848
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
849
    "r12", "sp", "lr", "pc",
850
851
    // Float registers
852
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
853
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
854
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
855
856
    // Double registers
857
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
858
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
859
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
860
861
    // Quad registers
862
    "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11",
863
    "q12", "q13", "q14", "q15"};
864
865
2.81k
ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
866
2.81k
  return llvm::makeArrayRef(GCCRegNames);
867
2.81k
}
868
869
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
870
    {{"a1"}, "r0"},  {{"a2"}, "r1"},        {{"a3"}, "r2"},  {{"a4"}, "r3"},
871
    {{"v1"}, "r4"},  {{"v2"}, "r5"},        {{"v3"}, "r6"},  {{"v4"}, "r7"},
872
    {{"v5"}, "r8"},  {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"},
873
    {{"ip"}, "r12"}, {{"r13"}, "sp"},       {{"r14"}, "lr"}, {{"r15"}, "pc"},
874
    // The S, D and Q registers overlap, but aren't really aliases; we
875
    // don't want to substitute one of these for a different-sized one.
876
};
877
878
2.75k
ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
879
2.75k
  return llvm::makeArrayRef(GCCRegAliases);
880
2.75k
}
881
882
bool ARMTargetInfo::validateAsmConstraint(
883
34
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
884
34
  switch (*Name) {
885
34
  default:
886
1
    break;
887
34
  case 'l': // r0-r7
888
21
  case 'h': // r8-r15
889
21
  case 't': // VFP Floating point register single precision
890
21
  case 'w': // VFP Floating point register double precision
891
21
    Info.setAllowsRegister();
892
21
    return true;
893
21
  case 'I':
894
0
  case 'J':
895
0
  case 'K':
896
0
  case 'L':
897
0
  case 'M':
898
0
    // FIXME
899
0
    return true;
900
4
  case 'Q': // A memory address that is a single base register.
901
4
    Info.setAllowsMemory();
902
4
    return true;
903
6
  case 'T':
904
6
    switch (Name[1]) {
905
6
    default:
906
0
      break;
907
6
    case 'e': // Even general-purpose register
908
6
    case 'o': // Odd general-purpose register
909
6
      Info.setAllowsRegister();
910
6
      Name++;
911
6
      return true;
912
0
    }
913
0
    break;
914
2
  case 'U': // a memory reference...
915
2
    switch (Name[1]) {
916
2
    case 'q': // ...ARMV4 ldrsb
917
2
    case 'v': // ...VFP load/store (reg+constant offset)
918
2
    case 'y': // ...iWMMXt load/store
919
2
    case 't': // address valid for load/store opaque types wider
920
2
              // than 128-bits
921
2
    case 'n': // valid address for Neon doubleword vector load/store
922
2
    case 'm': // valid address for Neon element and structure load/store
923
2
    case 's': // valid address for non-offset loads/stores of quad-word
924
2
              // values in four ARM registers
925
2
      Info.setAllowsMemory();
926
2
      Name++;
927
2
      return true;
928
0
    }
929
0
    break;
930
1
  }
931
1
  return false;
932
1
}
933
934
309
std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
935
309
  std::string R;
936
309
  switch (*Constraint) {
937
309
  case 'U': // Two-character constraint; add "^" hint for later parsing.
938
4
  case 'T':
939
4
    R = std::string("^") + std::string(Constraint, 2);
940
4
    Constraint++;
941
4
    break;
942
5
  case 'p': // 'p' should be translated to 'r' by default.
943
5
    R = std::string("r");
944
5
    break;
945
300
  default:
946
300
    return std::string(1, *Constraint);
947
9
  }
948
9
  return R;
949
9
}
950
951
bool ARMTargetInfo::validateConstraintModifier(
952
    StringRef Constraint, char Modifier, unsigned Size,
953
206
    std::string &SuggestedModifier) const {
954
206
  bool isOutput = (Constraint[0] == '=');
955
206
  bool isInOut = (Constraint[0] == '+');
956
206
957
206
  // Strip off constraint modifiers.
958
316
  while (Constraint[0] == '=' || 
Constraint[0] == '+'213
||
Constraint[0] == '&'208
)
959
110
    Constraint = Constraint.substr(1);
960
206
961
206
  switch (Constraint[0]) {
962
206
  default:
963
58
    break;
964
206
  case 'r': {
965
148
    switch (Modifier) {
966
148
    default:
967
140
      return (isInOut || 
isOutput138
||
Size <= 6456
);
968
148
    case 'q':
969
8
      // A register of size 32 cannot fit a vector type.
970
8
      return false;
971
58
    }
972
58
  }
973
58
  }
974
58
975
58
  return true;
976
58
}
977
993
const char *ARMTargetInfo::getClobbers() const {
978
993
  // FIXME: Is this really right?
979
993
  return "";
980
993
}
981
982
TargetInfo::CallingConvCheckResult
983
539
ARMTargetInfo::checkCallingConvention(CallingConv CC) const {
984
539
  switch (CC) {
985
539
  case CC_AAPCS:
986
539
  case CC_AAPCS_VFP:
987
539
  case CC_Swift:
988
539
  case CC_OpenCLKernel:
989
539
    return CCCR_OK;
990
539
  default:
991
0
    return CCCR_Warning;
992
539
  }
993
539
}
994
995
16
int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
996
16
  if (RegNo == 0)
997
8
    return 0;
998
8
  if (RegNo == 1)
999
8
    return 1;
1000
0
  return -1;
1001
0
}
1002
1003
0
bool ARMTargetInfo::hasSjLjLowering() const { return true; }
1004
1005
ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple,
1006
                                 const TargetOptions &Opts)
1007
3.74k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1007
3.36k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1007
375
    : ARMTargetInfo(Triple, Opts) {}
1008
1009
void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1010
3.72k
                                       MacroBuilder &Builder) const {
1011
3.72k
  Builder.defineMacro("__ARMEL__");
1012
3.72k
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1013
3.72k
}
1014
1015
ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple,
1016
                                 const TargetOptions &Opts)
1017
19
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1017
7
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1017
12
    : ARMTargetInfo(Triple, Opts) {}
1018
1019
void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts,
1020
19
                                       MacroBuilder &Builder) const {
1021
19
  Builder.defineMacro("__ARMEB__");
1022
19
  Builder.defineMacro("__ARM_BIG_ENDIAN");
1023
19
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1024
19
}
1025
1026
WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
1027
                                           const TargetOptions &Opts)
1028
92
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1029
92
}
clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1028
92
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1029
92
}
Unexecuted instantiation: clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1030
1031
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
1032
80
                                                  MacroBuilder &Builder) const {
1033
80
  // FIXME: this is invalid for WindowsCE
1034
80
  Builder.defineMacro("_M_ARM_NT", "1");
1035
80
  Builder.defineMacro("_M_ARMT", "_M_ARM");
1036
80
  Builder.defineMacro("_M_THUMB", "_M_ARM");
1037
80
1038
80
  assert((Triple.getArch() == llvm::Triple::arm ||
1039
80
          Triple.getArch() == llvm::Triple::thumb) &&
1040
80
         "invalid architecture for Windows ARM target info");
1041
80
  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 
48
:
672
;
1042
80
  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
1043
80
1044
80
  // TODO map the complete set of values
1045
80
  // 31: VFPv3 40: VFPv4
1046
80
  Builder.defineMacro("_M_ARM_FP", "31");
1047
80
}
1048
1049
TargetInfo::BuiltinVaListKind
1050
82
WindowsARMTargetInfo::getBuiltinVaListKind() const {
1051
82
  return TargetInfo::CharPtrBuiltinVaList;
1052
82
}
1053
1054
TargetInfo::CallingConvCheckResult
1055
32
WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1056
32
  switch (CC) {
1057
32
  case CC_X86StdCall:
1058
1
  case CC_X86ThisCall:
1059
1
  case CC_X86FastCall:
1060
1
  case CC_X86VectorCall:
1061
1
    return CCCR_Ignore;
1062
31
  case CC_C:
1063
31
  case CC_OpenCLKernel:
1064
31
  case CC_PreserveMost:
1065
31
  case CC_PreserveAll:
1066
31
  case CC_Swift:
1067
31
    return CCCR_OK;
1068
31
  default:
1069
0
    return CCCR_Warning;
1070
32
  }
1071
32
}
1072
1073
// Windows ARM + Itanium C++ ABI Target
1074
ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(
1075
    const llvm::Triple &Triple, const TargetOptions &Opts)
1076
9
    : WindowsARMTargetInfo(Triple, Opts) {
1077
9
  TheCXXABI.set(TargetCXXABI::GenericARM);
1078
9
}
Unexecuted instantiation: clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1076
9
    : WindowsARMTargetInfo(Triple, Opts) {
1077
9
  TheCXXABI.set(TargetCXXABI::GenericARM);
1078
9
}
1079
1080
void ItaniumWindowsARMleTargetInfo::getTargetDefines(
1081
9
    const LangOptions &Opts, MacroBuilder &Builder) const {
1082
9
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1083
9
1084
9
  if (Opts.MSVCCompat)
1085
1
    WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1086
9
}
1087
1088
// Windows ARM, MS (C++) ABI
1089
MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
1090
                                                   const TargetOptions &Opts)
1091
79
    : WindowsARMTargetInfo(Triple, Opts) {
1092
79
  TheCXXABI.set(TargetCXXABI::Microsoft);
1093
79
}
Unexecuted instantiation: clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1091
79
    : WindowsARMTargetInfo(Triple, Opts) {
1092
79
  TheCXXABI.set(TargetCXXABI::Microsoft);
1093
79
}
1094
1095
void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1096
79
                                                MacroBuilder &Builder) const {
1097
79
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1098
79
  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1099
79
}
1100
1101
MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple,
1102
                                       const TargetOptions &Opts)
1103
4
    : WindowsARMTargetInfo(Triple, Opts) {
1104
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1105
4
}
Unexecuted instantiation: clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1103
4
    : WindowsARMTargetInfo(Triple, Opts) {
1104
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1105
4
}
1106
1107
void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1108
4
                                          MacroBuilder &Builder) const {
1109
4
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1110
4
  Builder.defineMacro("_ARM_");
1111
4
}
1112
1113
CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
1114
                                         const TargetOptions &Opts)
1115
1
    : ARMleTargetInfo(Triple, Opts) {
1116
1
  this->WCharType = TargetInfo::UnsignedShort;
1117
1
  TLSSupported = false;
1118
1
  DoubleAlign = LongLongAlign = 64;
1119
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1120
1
}
Unexecuted instantiation: clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1115
1
    : ARMleTargetInfo(Triple, Opts) {
1116
1
  this->WCharType = TargetInfo::UnsignedShort;
1117
1
  TLSSupported = false;
1118
1
  DoubleAlign = LongLongAlign = 64;
1119
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1120
1
}
1121
1122
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1123
1
                                           MacroBuilder &Builder) const {
1124
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1125
1
  Builder.defineMacro("_ARM_");
1126
1
  Builder.defineMacro("__CYGWIN__");
1127
1
  Builder.defineMacro("__CYGWIN32__");
1128
1
  DefineStd(Builder, "unix", Opts);
1129
1
  if (Opts.CPlusPlus)
1130
0
    Builder.defineMacro("_GNU_SOURCE");
1131
1
}
1132
1133
DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
1134
                                         const TargetOptions &Opts)
1135
2.99k
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1136
2.99k
  HasAlignMac68kSupport = true;
1137
2.99k
  // iOS always has 64-bit atomic instructions.
1138
2.99k
  // FIXME: This should be based off of the target features in
1139
2.99k
  // ARMleTargetInfo.
1140
2.99k
  MaxAtomicInlineWidth = 64;
1141
2.99k
1142
2.99k
  if (Triple.isWatchABI()) {
1143
693
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1144
693
    TheCXXABI.set(TargetCXXABI::WatchOS);
1145
693
1146
693
    // BOOL should be a real boolean on the new ABI
1147
693
    UseSignedCharForObjCBool = false;
1148
693
  } else
1149
2.30k
    TheCXXABI.set(TargetCXXABI::iOS);
1150
2.99k
}
Unexecuted instantiation: clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1135
2.99k
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1136
2.99k
  HasAlignMac68kSupport = true;
1137
2.99k
  // iOS always has 64-bit atomic instructions.
1138
2.99k
  // FIXME: This should be based off of the target features in
1139
2.99k
  // ARMleTargetInfo.
1140
2.99k
  MaxAtomicInlineWidth = 64;
1141
2.99k
1142
2.99k
  if (Triple.isWatchABI()) {
1143
693
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1144
693
    TheCXXABI.set(TargetCXXABI::WatchOS);
1145
693
1146
693
    // BOOL should be a real boolean on the new ABI
1147
693
    UseSignedCharForObjCBool = false;
1148
693
  } else
1149
2.30k
    TheCXXABI.set(TargetCXXABI::iOS);
1150
2.99k
}
1151
1152
void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts,
1153
                                       const llvm::Triple &Triple,
1154
2.98k
                                       MacroBuilder &Builder) const {
1155
2.98k
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1156
2.98k
}
1157
1158
RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple,
1159
                                                   const TargetOptions &Opts)
1160
    : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
1161
                                   Triple.getOSName(),
1162
                                   Triple.getEnvironmentName()),
1163
1
                      Opts) {
1164
1
  IsRenderScriptTarget = true;
1165
1
  LongWidth = LongAlign = 64;
1166
1
}
clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1163
1
                      Opts) {
1164
1
  IsRenderScriptTarget = true;
1165
1
  LongWidth = LongAlign = 64;
1166
1
}
Unexecuted instantiation: clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1167
1168
void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts,
1169
1
                                                MacroBuilder &Builder) const {
1170
1
  Builder.defineMacro("__RENDERSCRIPT__");
1171
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1172
1
}