Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/clang/lib/Basic/Targets/PPC.h
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//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
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13
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14
#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16
#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
19
#include "llvm/ADT/Triple.h"
20
#include "llvm/ADT/StringSwitch.h"
21
#include "llvm/Support/Compiler.h"
22
23
namespace clang {
24
namespace targets {
25
26
// PPC abstract base class
27
class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29
  /// Flags for architecture specific defines.
30
  typedef enum {
31
    ArchDefineNone = 0,
32
    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33
    ArchDefinePpcgr = 1 << 1,
34
    ArchDefinePpcsq = 1 << 2,
35
    ArchDefine440 = 1 << 3,
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    ArchDefine603 = 1 << 4,
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    ArchDefine604 = 1 << 5,
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    ArchDefinePwr4 = 1 << 6,
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    ArchDefinePwr5 = 1 << 7,
40
    ArchDefinePwr5x = 1 << 8,
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    ArchDefinePwr6 = 1 << 9,
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    ArchDefinePwr6x = 1 << 10,
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    ArchDefinePwr7 = 1 << 11,
44
    ArchDefinePwr8 = 1 << 12,
45
    ArchDefinePwr9 = 1 << 13,
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    ArchDefineA2 = 1 << 14,
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    ArchDefineA2q = 1 << 15
48
  } ArchDefineTypes;
49
50
51
  ArchDefineTypes ArchDefs = ArchDefineNone;
52
  static const Builtin::Info BuiltinInfo[];
53
  static const char *const GCCRegNames[];
54
  static const TargetInfo::GCCRegAlias GCCRegAliases[];
55
  std::string CPU;
56
  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
57
58
  // Target cpu features.
59
  bool HasAltivec = false;
60
  bool HasVSX = false;
61
  bool HasP8Vector = false;
62
  bool HasP8Crypto = false;
63
  bool HasDirectMove = false;
64
  bool HasQPX = false;
65
  bool HasHTM = false;
66
  bool HasBPERMD = false;
67
  bool HasExtDiv = false;
68
  bool HasP9Vector = false;
69
70
protected:
71
  std::string ABI;
72
73
public:
74
  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
75
2.52k
      : TargetInfo(Triple) {
76
2.52k
    SuitableAlign = 128;
77
2.52k
    SimdDefaultAlign = 128;
78
2.52k
    LongDoubleWidth = LongDoubleAlign = 128;
79
2.52k
    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
80
2.52k
  }
81
82
  // Set the language option for altivec based on our value.
83
  void adjust(LangOptions &Opts) override;
84
85
  // Note: GCC recognizes the following additional cpus:
86
  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
87
  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
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  //  titan, rs64.
89
  bool isValidCPUName(StringRef Name) const override;
90
  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
91
92
116
  bool setCPU(const std::string &Name) override {
93
116
    bool CPUKnown = isValidCPUName(Name);
94
116
    if (CPUKnown) {
95
115
      CPU = Name;
96
115
97
115
      // CPU identification.
98
115
      ArchDefs =
99
115
          (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
100
115
              .Case("440", ArchDefineName)
101
115
              .Case("450", ArchDefineName | ArchDefine440)
102
115
              .Case("601", ArchDefineName)
103
115
              .Case("602", ArchDefineName | ArchDefinePpcgr)
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115
              .Case("603", ArchDefineName | ArchDefinePpcgr)
105
115
              .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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115
              .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
107
115
              .Case("604", ArchDefineName | ArchDefinePpcgr)
108
115
              .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
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115
              .Case("620", ArchDefineName | ArchDefinePpcgr)
110
115
              .Case("630", ArchDefineName | ArchDefinePpcgr)
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115
              .Case("7400", ArchDefineName | ArchDefinePpcgr)
112
115
              .Case("7450", ArchDefineName | ArchDefinePpcgr)
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              .Case("750", ArchDefineName | ArchDefinePpcgr)
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115
              .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
115
115
                               ArchDefinePpcsq)
116
115
              .Case("a2", ArchDefineA2)
117
115
              .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
118
115
              .Cases("power3", "pwr3", ArchDefinePpcgr)
119
115
              .Cases("power4", "pwr4",
120
115
                    ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
121
115
              .Cases("power5", "pwr5",
122
115
                    ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
123
115
                        ArchDefinePpcsq)
124
115
              .Cases("power5x", "pwr5x",
125
115
                    ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
126
115
                        ArchDefinePpcgr | ArchDefinePpcsq)
127
115
              .Cases("power6", "pwr6",
128
115
                    ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
129
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                        ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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115
              .Cases("power6x", "pwr6x",
131
115
                    ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
132
115
                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
133
115
                        ArchDefinePpcsq)
134
115
              .Cases("power7", "pwr7",
135
115
                     ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
136
115
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
137
115
                         ArchDefinePpcsq)
138
115
              // powerpc64le automatically defaults to at least power8.
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115
              .Cases("power8", "pwr8", "ppc64le",
140
115
                     ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
141
115
                         ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
142
115
                         ArchDefinePpcgr | ArchDefinePpcsq)
143
115
              .Cases("power9", "pwr9",
144
115
                     ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
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115
                         ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
146
115
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
147
115
              .Default(ArchDefineNone);
148
115
    }
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    return CPUKnown;
150
116
  }
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4.94k
  StringRef getABI() const override { return ABI; }
153
154
  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
155
156
0
  bool isCLZForZeroUndef() const override { return false; }
157
158
  void getTargetDefines(const LangOptions &Opts,
159
                        MacroBuilder &Builder) const override;
160
161
  bool
162
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
163
                 StringRef CPU,
164
                 const std::vector<std::string> &FeaturesVec) const override;
165
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  bool handleTargetFeatures(std::vector<std::string> &Features,
167
                            DiagnosticsEngine &Diags) override;
168
169
  bool hasFeature(StringRef Feature) const override;
170
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  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
172
                         bool Enabled) const override;
173
174
  ArrayRef<const char *> getGCCRegNames() const override;
175
176
  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
177
178
  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
179
180
  bool validateAsmConstraint(const char *&Name,
181
217
                             TargetInfo::ConstraintInfo &Info) const override {
182
217
    switch (*Name) {
183
217
    default:
184
0
      return false;
185
217
    case 'O': // Zero
186
0
      break;
187
217
    case 'f': // Floating point register
188
19
      // Don't use floating point registers on soft float ABI.
189
19
      if (FloatABI == SoftFloat)
190
1
        return false;
191
18
      LLVM_FALLTHROUGH;
192
77
    case 'b': // Base register
193
77
      Info.setAllowsRegister();
194
77
      break;
195
18
    // FIXME: The following are added to allow parsing.
196
18
    // I just took a guess at what the actions should be.
197
18
    // Also, is more specific checking needed?  I.e. specific registers?
198
23
    case 'd': // Floating point register (containing 64-bit value)
199
23
    case 'v': // Altivec vector register
200
23
      // Don't use floating point and altivec vector registers
201
23
      // on soft float ABI
202
23
      if (FloatABI == SoftFloat)
203
2
        return false;
204
21
      Info.setAllowsRegister();
205
21
      break;
206
116
    case 'w':
207
116
      switch (Name[1]) {
208
116
      case 'd': // VSX vector register to hold vector double data
209
116
      case 'f': // VSX vector register to hold vector float data
210
116
      case 's': // VSX vector register to hold scalar double data
211
116
      case 'w': // VSX vector register to hold scalar double data
212
116
      case 'a': // Any VSX register
213
116
      case 'c': // An individual CR bit
214
116
      case 'i': // FP or VSX register to hold 64-bit integers data
215
116
        break;
216
116
      default:
217
0
        return false;
218
116
      }
219
116
      Info.setAllowsRegister();
220
116
      Name++; // Skip over 'w'.
221
116
      break;
222
116
    case 'h': // `MQ', `CTR', or `LINK' register
223
0
    case 'q': // `MQ' register
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0
    case 'c': // `CTR' register
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0
    case 'l': // `LINK' register
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0
    case 'x': // `CR' register (condition register) number 0
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0
    case 'y': // `CR' register (condition register)
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0
    case 'z': // `XER[CA]' carry bit (part of the XER register)
229
0
      Info.setAllowsRegister();
230
0
      break;
231
0
    case 'I': // Signed 16-bit constant
232
0
    case 'J': // Unsigned 16-bit constant shifted left 16 bits
233
0
              //  (use `L' instead for SImode constants)
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0
    case 'K': // Unsigned 16-bit constant
235
0
    case 'L': // Signed 16-bit constant shifted left 16 bits
236
0
    case 'M': // Constant larger than 31
237
0
    case 'N': // Exact power of 2
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0
    case 'P': // Constant whose negation is a signed 16-bit constant
239
0
    case 'G': // Floating point constant that can be loaded into a
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0
              // register with one instruction per word
241
0
    case 'H': // Integer/Floating point constant that can be loaded
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0
              // into a register using three instructions
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0
      break;
244
0
    case 'm': // Memory operand. Note that on PowerPC targets, m can
245
0
              // include addresses that update the base register. It
246
0
              // is therefore only safe to use `m' in an asm statement
247
0
              // if that asm statement accesses the operand exactly once.
248
0
              // The asm statement must also use `%U<opno>' as a
249
0
              // placeholder for the "update" flag in the corresponding
250
0
              // load or store instruction. For example:
251
0
              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
252
0
              // is correct but:
253
0
              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
254
0
              // is not. Use es rather than m if you don't want the base
255
0
              // register to be updated.
256
0
    case 'e':
257
0
      if (Name[1] != 's')
258
0
        return false;
259
0
      // es: A "stable" memory operand; that is, one which does not
260
0
      // include any automodification of the base register. Unlike
261
0
      // `m', this constraint can be used in asm statements that
262
0
      // might access the operand several times, or that might not
263
0
      // access it at all.
264
0
      Info.setAllowsMemory();
265
0
      Name++; // Skip over 'e'.
266
0
      break;
267
0
    case 'Q': // Memory operand that is an offset from a register (it is
268
0
              // usually better to use `m' or `es' in asm statements)
269
0
    case 'Z': // Memory operand that is an indexed or indirect from a
270
0
              // register (it is usually better to use `m' or `es' in
271
0
              // asm statements)
272
0
      Info.setAllowsMemory();
273
0
      Info.setAllowsRegister();
274
0
      break;
275
0
    case 'R': // AIX TOC entry
276
0
    case 'a': // Address operand that is an indexed or indirect from a
277
0
              // register (`p' is preferable for asm statements)
278
0
    case 'S': // Constant suitable as a 64-bit mask operand
279
0
    case 'T': // Constant suitable as a 32-bit mask operand
280
0
    case 'U': // System V Release 4 small data area reference
281
0
    case 't': // AND masks that can be performed by two rldic{l, r}
282
0
              // instructions
283
0
    case 'W': // Vector constant that does not require memory
284
0
    case 'j': // Vector constant that is all zeros.
285
0
      break;
286
214
      // End FIXME.
287
214
    }
288
214
    return true;
289
214
  }
290
291
336
  std::string convertConstraint(const char *&Constraint) const override {
292
336
    std::string R;
293
336
    switch (*Constraint) {
294
336
    case 'e':
295
39
    case 'w':
296
39
      // Two-character constraint; add "^" hint for later parsing.
297
39
      R = std::string("^") + std::string(Constraint, 2);
298
39
      Constraint++;
299
39
      break;
300
297
    default:
301
297
      return TargetInfo::convertConstraint(Constraint);
302
39
    }
303
39
    return R;
304
39
  }
305
306
125
  const char *getClobbers() const override { return ""; }
307
4
  int getEHDataRegisterNumber(unsigned RegNo) const override {
308
4
    if (RegNo == 0)
309
2
      return 3;
310
2
    if (RegNo == 1)
311
2
      return 4;
312
0
    return -1;
313
0
  }
314
315
4
  bool hasSjLjLowering() const override { return true; }
316
317
48
  const char *getLongDoubleMangling() const override {
318
48
    if (LongDoubleWidth == 64)
319
6
      return "e";
320
42
    return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
321
42
               ? 
"g"36
322
42
               : 
"u9__ieee128"6
;
323
42
  }
324
44
  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
325
};
326
327
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
328
public:
329
  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
330
73
      : PPCTargetInfo(Triple, Opts) {
331
73
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
332
73
333
73
    switch (getTriple().getOS()) {
334
73
    case llvm::Triple::Linux:
335
27
    case llvm::Triple::FreeBSD:
336
27
    case llvm::Triple::NetBSD:
337
27
      SizeType = UnsignedInt;
338
27
      PtrDiffType = SignedInt;
339
27
      IntPtrType = SignedInt;
340
27
      break;
341
27
    case llvm::Triple::AIX:
342
18
      SizeType = UnsignedLong;
343
18
      PtrDiffType = SignedLong;
344
18
      IntPtrType = SignedLong;
345
18
      SuitableAlign = 64;
346
18
      break;
347
28
    default:
348
28
      break;
349
73
    }
350
73
351
73
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()71
||
Triple.isOSOpenBSD()69
||
352
73
        
Triple.getOS() == llvm::Triple::AIX66
||
Triple.isMusl()48
) {
353
25
      LongDoubleWidth = LongDoubleAlign = 64;
354
25
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
355
25
    }
356
73
357
73
    // PPC32 supports atomics up to 4 bytes.
358
73
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
359
73
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
330
55
      : PPCTargetInfo(Triple, Opts) {
331
55
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
332
55
333
55
    switch (getTriple().getOS()) {
334
55
    case llvm::Triple::Linux:
335
27
    case llvm::Triple::FreeBSD:
336
27
    case llvm::Triple::NetBSD:
337
27
      SizeType = UnsignedInt;
338
27
      PtrDiffType = SignedInt;
339
27
      IntPtrType = SignedInt;
340
27
      break;
341
27
    case llvm::Triple::AIX:
342
18
      SizeType = UnsignedLong;
343
18
      PtrDiffType = SignedLong;
344
18
      IntPtrType = SignedLong;
345
18
      SuitableAlign = 64;
346
18
      break;
347
27
    default:
348
10
      break;
349
55
    }
350
55
351
55
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()53
||
Triple.isOSOpenBSD()51
||
352
55
        
Triple.getOS() == llvm::Triple::AIX48
||
Triple.isMusl()30
) {
353
25
      LongDoubleWidth = LongDoubleAlign = 64;
354
25
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
355
25
    }
356
55
357
55
    // PPC32 supports atomics up to 4 bytes.
358
55
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
359
55
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
330
18
      : PPCTargetInfo(Triple, Opts) {
331
18
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
332
18
333
18
    switch (getTriple().getOS()) {
334
18
    case llvm::Triple::Linux:
335
0
    case llvm::Triple::FreeBSD:
336
0
    case llvm::Triple::NetBSD:
337
0
      SizeType = UnsignedInt;
338
0
      PtrDiffType = SignedInt;
339
0
      IntPtrType = SignedInt;
340
0
      break;
341
0
    case llvm::Triple::AIX:
342
0
      SizeType = UnsignedLong;
343
0
      PtrDiffType = SignedLong;
344
0
      IntPtrType = SignedLong;
345
0
      SuitableAlign = 64;
346
0
      break;
347
18
    default:
348
18
      break;
349
18
    }
350
18
351
18
    if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
352
18
        Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
353
0
      LongDoubleWidth = LongDoubleAlign = 64;
354
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
355
0
    }
356
18
357
18
    // PPC32 supports atomics up to 4 bytes.
358
18
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
359
18
  }
360
361
39
  BuiltinVaListKind getBuiltinVaListKind() const override {
362
39
    // This is the ELF definition, and is overridden by the Darwin sub-target
363
39
    return TargetInfo::PowerABIBuiltinVaList;
364
39
  }
365
};
366
367
// Note: ABI differences may eventually require us to have a separate
368
// TargetInfo for little endian.
369
class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
370
public:
371
  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
372
2.45k
      : PPCTargetInfo(Triple, Opts) {
373
2.45k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
374
2.45k
    IntMaxType = SignedLong;
375
2.45k
    Int64Type = SignedLong;
376
2.45k
377
2.45k
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
378
2.30k
      resetDataLayout("e-m:e-i64:64-n32:64");
379
2.30k
      ABI = "elfv2";
380
2.30k
    } else {
381
150
      resetDataLayout("E-m:e-i64:64-n32:64");
382
150
      ABI = Triple.getEnvironment() == llvm::Triple::ELFv2 ? 
"elfv2"0
: "elfv1";
383
150
    }
384
2.45k
385
2.45k
    if (Triple.getOS() == llvm::Triple::AIX)
386
3
      SuitableAlign = 64;
387
2.45k
388
2.45k
    if (Triple.isOSFreeBSD() || 
Triple.getOS() == llvm::Triple::AIX2.45k
||
389
2.45k
        
Triple.isMusl()2.45k
) {
390
8
      LongDoubleWidth = LongDoubleAlign = 64;
391
8
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
392
8
    }
393
2.45k
394
2.45k
    // PPC64 supports atomics up to 8 bytes.
395
2.45k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
396
2.45k
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
372
200
      : PPCTargetInfo(Triple, Opts) {
373
200
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
374
200
    IntMaxType = SignedLong;
375
200
    Int64Type = SignedLong;
376
200
377
200
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
378
106
      resetDataLayout("e-m:e-i64:64-n32:64");
379
106
      ABI = "elfv2";
380
106
    } else {
381
94
      resetDataLayout("E-m:e-i64:64-n32:64");
382
94
      ABI = Triple.getEnvironment() == llvm::Triple::ELFv2 ? 
"elfv2"0
: "elfv1";
383
94
    }
384
200
385
200
    if (Triple.getOS() == llvm::Triple::AIX)
386
3
      SuitableAlign = 64;
387
200
388
200
    if (Triple.isOSFreeBSD() || 
Triple.getOS() == llvm::Triple::AIX198
||
389
200
        
Triple.isMusl()195
) {
390
8
      LongDoubleWidth = LongDoubleAlign = 64;
391
8
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
392
8
    }
393
200
394
200
    // PPC64 supports atomics up to 8 bytes.
395
200
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
396
200
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
372
2.25k
      : PPCTargetInfo(Triple, Opts) {
373
2.25k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
374
2.25k
    IntMaxType = SignedLong;
375
2.25k
    Int64Type = SignedLong;
376
2.25k
377
2.25k
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
378
2.20k
      resetDataLayout("e-m:e-i64:64-n32:64");
379
2.20k
      ABI = "elfv2";
380
2.20k
    } else {
381
56
      resetDataLayout("E-m:e-i64:64-n32:64");
382
56
      ABI = Triple.getEnvironment() == llvm::Triple::ELFv2 ? 
"elfv2"0
: "elfv1";
383
56
    }
384
2.25k
385
2.25k
    if (Triple.getOS() == llvm::Triple::AIX)
386
0
      SuitableAlign = 64;
387
2.25k
388
2.25k
    if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||
389
2.25k
        Triple.isMusl()) {
390
0
      LongDoubleWidth = LongDoubleAlign = 64;
391
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
392
0
    }
393
2.25k
394
2.25k
    // PPC64 supports atomics up to 8 bytes.
395
2.25k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
396
2.25k
  }
397
398
2.35k
  BuiltinVaListKind getBuiltinVaListKind() const override {
399
2.35k
    return TargetInfo::CharPtrBuiltinVaList;
400
2.35k
  }
401
402
  // PPC64 Linux-specific ABI options.
403
65
  bool setABI(const std::string &Name) override {
404
65
    if (Name == "elfv1" || 
Name == "elfv1-qpx"38
||
Name == "elfv2"33
) {
405
65
      ABI = Name;
406
65
      return true;
407
65
    }
408
0
    return false;
409
0
  }
410
411
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
412
    switch (CC) {
413
    case CC_Swift:
414
      return CCCR_OK;
415
    default:
416
      return CCCR_Warning;
417
    }
418
  }
419
};
420
421
class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
422
    : public DarwinTargetInfo<PPC32TargetInfo> {
423
public:
424
  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
425
7
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
426
7
    HasAlignMac68kSupport = true;
427
7
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
428
7
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
429
7
    LongLongAlign = 32;
430
7
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
431
7
  }
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
425
7
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
426
7
    HasAlignMac68kSupport = true;
427
7
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
428
7
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
429
7
    LongLongAlign = 32;
430
7
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
431
7
  }
Unexecuted instantiation: clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
432
433
6
  BuiltinVaListKind getBuiltinVaListKind() const override {
434
6
    return TargetInfo::CharPtrBuiltinVaList;
435
6
  }
436
};
437
438
class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
439
    : public DarwinTargetInfo<PPC64TargetInfo> {
440
public:
441
  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
442
2
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
443
2
    HasAlignMac68kSupport = true;
444
2
    resetDataLayout("E-m:o-i64:64-n32:64");
445
2
  }
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
442
2
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
443
2
    HasAlignMac68kSupport = true;
444
2
    resetDataLayout("E-m:o-i64:64-n32:64");
445
2
  }
Unexecuted instantiation: clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
446
};
447
448
class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
449
  public AIXTargetInfo<PPC32TargetInfo> {
450
public:
451
  using AIXTargetInfo::AIXTargetInfo;
452
2
  BuiltinVaListKind getBuiltinVaListKind() const override {
453
2
    return TargetInfo::CharPtrBuiltinVaList;
454
2
  }
455
};
456
457
class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
458
  public AIXTargetInfo<PPC64TargetInfo> {
459
public:
460
  using AIXTargetInfo::AIXTargetInfo;
461
};
462
463
} // namespace targets
464
} // namespace clang
465
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H