Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/clang/lib/Basic/Targets/X86.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
};
66
67
const TargetInfo::AddlRegName AddlRegNames[] = {
68
    {{"al", "ah", "eax", "rax"}, 0},
69
    {{"bl", "bh", "ebx", "rbx"}, 3},
70
    {{"cl", "ch", "ecx", "rcx"}, 2},
71
    {{"dl", "dh", "edx", "rdx"}, 1},
72
    {{"esi", "rsi"}, 4},
73
    {{"edi", "rdi"}, 5},
74
    {{"esp", "rsp"}, 7},
75
    {{"ebp", "rbp"}, 6},
76
    {{"r8d", "r8w", "r8b"}, 38},
77
    {{"r9d", "r9w", "r9b"}, 39},
78
    {{"r10d", "r10w", "r10b"}, 40},
79
    {{"r11d", "r11w", "r11b"}, 41},
80
    {{"r12d", "r12w", "r12b"}, 42},
81
    {{"r13d", "r13w", "r13b"}, 43},
82
    {{"r14d", "r14w", "r14b"}, 44},
83
    {{"r15d", "r15w", "r15b"}, 45},
84
};
85
86
} // namespace targets
87
} // namespace clang
88
89
using namespace clang;
90
using namespace clang::targets;
91
92
5
bool X86TargetInfo::setFPMath(StringRef Name) {
93
5
  if (Name == "387") {
94
2
    FPMath = FP_387;
95
2
    return true;
96
2
  }
97
3
  if (Name == "sse") {
98
2
    FPMath = FP_SSE;
99
2
    return true;
100
2
  }
101
1
  return false;
102
1
}
103
104
bool X86TargetInfo::initFeatureMap(
105
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106
82.6k
    const std::vector<std::string> &FeaturesVec) const {
107
82.6k
  // FIXME: This *really* should not be here.
108
82.6k
  // X86_64 always has SSE2.
109
82.6k
  if (getTriple().getArch() == llvm::Triple::x86_64)
110
76.2k
    setFeatureEnabledImpl(Features, "sse2", true);
111
82.6k
112
82.6k
  const CPUKind Kind = getCPUKind(CPU);
113
82.6k
114
82.6k
  // Enable X87 for all X86 processors but Lakemont.
115
82.6k
  if (Kind != CK_Lakemont)
116
82.6k
    setFeatureEnabledImpl(Features, "x87", true);
117
82.6k
118
82.6k
  // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
119
82.6k
  // compatibility.
120
82.6k
  if (Kind >= CK_i586 || 
Kind == CK_Generic67.5k
)
121
82.5k
    setFeatureEnabledImpl(Features, "cx8", true);
122
82.6k
123
82.6k
  switch (Kind) {
124
82.6k
  case CK_Generic:
125
67.7k
  case CK_i386:
126
67.7k
  case CK_i486:
127
67.7k
  case CK_i586:
128
67.7k
  case CK_Pentium:
129
67.7k
  case CK_PentiumPro:
130
67.7k
  case CK_i686:
131
67.7k
  case CK_Lakemont:
132
67.7k
    break;
133
67.7k
134
67.7k
  case CK_PentiumMMX:
135
4
  case CK_Pentium2:
136
4
  case CK_K6:
137
4
  case CK_WinChipC6:
138
4
    setFeatureEnabledImpl(Features, "mmx", true);
139
4
    break;
140
4
141
4
  case CK_Cooperlake:
142
2
    // CPX inherits all CLX features plus AVX512BF16
143
2
    setFeatureEnabledImpl(Features, "avx512bf16", true);
144
2
    LLVM_FALLTHROUGH;
145
4
  case CK_Cascadelake:
146
4
    // CLX inherits all SKX features plus AVX512VNNI
147
4
    setFeatureEnabledImpl(Features, "avx512vnni", true);
148
4
    LLVM_FALLTHROUGH;
149
926
  case CK_SkylakeServer:
150
926
    setFeatureEnabledImpl(Features, "avx512f", true);
151
926
    setFeatureEnabledImpl(Features, "avx512cd", true);
152
926
    setFeatureEnabledImpl(Features, "avx512dq", true);
153
926
    setFeatureEnabledImpl(Features, "avx512bw", true);
154
926
    setFeatureEnabledImpl(Features, "avx512vl", true);
155
926
    setFeatureEnabledImpl(Features, "clwb", true);
156
926
    setFeatureEnabledImpl(Features, "pku", true);
157
926
    // SkylakeServer cores inherits all SKL features, except SGX
158
926
    goto SkylakeCommon;
159
4
160
4
  case CK_IcelakeServer:
161
3
    setFeatureEnabledImpl(Features, "pconfig", true);
162
3
    setFeatureEnabledImpl(Features, "wbnoinvd", true);
163
3
    LLVM_FALLTHROUGH;
164
6
  case CK_IcelakeClient:
165
6
    setFeatureEnabledImpl(Features, "vaes", true);
166
6
    setFeatureEnabledImpl(Features, "gfni", true);
167
6
    setFeatureEnabledImpl(Features, "vpclmulqdq", true);
168
6
    setFeatureEnabledImpl(Features, "avx512bitalg", true);
169
6
    setFeatureEnabledImpl(Features, "avx512vbmi2", true);
170
6
    setFeatureEnabledImpl(Features, "avx512vnni", true);
171
6
    setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
172
6
    setFeatureEnabledImpl(Features, "rdpid", true);
173
6
    setFeatureEnabledImpl(Features, "clwb", true);
174
6
    LLVM_FALLTHROUGH;
175
9
  case CK_Cannonlake:
176
9
    setFeatureEnabledImpl(Features, "avx512f", true);
177
9
    setFeatureEnabledImpl(Features, "avx512cd", true);
178
9
    setFeatureEnabledImpl(Features, "avx512dq", true);
179
9
    setFeatureEnabledImpl(Features, "avx512bw", true);
180
9
    setFeatureEnabledImpl(Features, "avx512vl", true);
181
9
    setFeatureEnabledImpl(Features, "avx512ifma", true);
182
9
    setFeatureEnabledImpl(Features, "avx512vbmi", true);
183
9
    setFeatureEnabledImpl(Features, "pku", true);
184
9
    setFeatureEnabledImpl(Features, "sha", true);
185
9
    LLVM_FALLTHROUGH;
186
13
  case CK_SkylakeClient:
187
13
    setFeatureEnabledImpl(Features, "sgx", true);
188
13
    // SkylakeServer cores inherits all SKL features, except SGX
189
939
SkylakeCommon:
190
939
    setFeatureEnabledImpl(Features, "xsavec", true);
191
939
    setFeatureEnabledImpl(Features, "xsaves", true);
192
939
    setFeatureEnabledImpl(Features, "mpx", true);
193
939
    setFeatureEnabledImpl(Features, "clflushopt", true);
194
939
    setFeatureEnabledImpl(Features, "aes", true);
195
939
    LLVM_FALLTHROUGH;
196
943
  case CK_Broadwell:
197
943
    setFeatureEnabledImpl(Features, "rdseed", true);
198
943
    setFeatureEnabledImpl(Features, "adx", true);
199
943
    setFeatureEnabledImpl(Features, "prfchw", true);
200
943
    LLVM_FALLTHROUGH;
201
1.83k
  case CK_Haswell:
202
1.83k
    setFeatureEnabledImpl(Features, "avx2", true);
203
1.83k
    setFeatureEnabledImpl(Features, "lzcnt", true);
204
1.83k
    setFeatureEnabledImpl(Features, "bmi", true);
205
1.83k
    setFeatureEnabledImpl(Features, "bmi2", true);
206
1.83k
    setFeatureEnabledImpl(Features, "fma", true);
207
1.83k
    setFeatureEnabledImpl(Features, "invpcid", true);
208
1.83k
    setFeatureEnabledImpl(Features, "movbe", true);
209
1.83k
    LLVM_FALLTHROUGH;
210
1.92k
  case CK_IvyBridge:
211
1.92k
    setFeatureEnabledImpl(Features, "rdrnd", true);
212
1.92k
    setFeatureEnabledImpl(Features, "f16c", true);
213
1.92k
    setFeatureEnabledImpl(Features, "fsgsbase", true);
214
1.92k
    LLVM_FALLTHROUGH;
215
1.96k
  case CK_SandyBridge:
216
1.96k
    setFeatureEnabledImpl(Features, "avx", true);
217
1.96k
    setFeatureEnabledImpl(Features, "xsave", true);
218
1.96k
    setFeatureEnabledImpl(Features, "xsaveopt", true);
219
1.96k
    LLVM_FALLTHROUGH;
220
1.96k
  case CK_Westmere:
221
1.96k
    setFeatureEnabledImpl(Features, "pclmul", true);
222
1.96k
    LLVM_FALLTHROUGH;
223
1.99k
  case CK_Nehalem:
224
1.99k
    setFeatureEnabledImpl(Features, "sse4.2", true);
225
1.99k
    LLVM_FALLTHROUGH;
226
10.4k
  case CK_Penryn:
227
10.4k
    setFeatureEnabledImpl(Features, "sse4.1", true);
228
10.4k
    LLVM_FALLTHROUGH;
229
12.1k
  case CK_Core2:
230
12.1k
    setFeatureEnabledImpl(Features, "ssse3", true);
231
12.1k
    setFeatureEnabledImpl(Features, "sahf", true);
232
12.1k
    LLVM_FALLTHROUGH;
233
12.1k
  case CK_Nocona:
234
12.1k
    setFeatureEnabledImpl(Features, "cx16", true);
235
12.1k
    LLVM_FALLTHROUGH;
236
12.5k
  case CK_Yonah:
237
12.5k
  case CK_Prescott:
238
12.5k
    setFeatureEnabledImpl(Features, "sse3", true);
239
12.5k
    LLVM_FALLTHROUGH;
240
14.7k
  case CK_PentiumM:
241
14.7k
  case CK_Pentium4:
242
14.7k
  case CK_x86_64:
243
14.7k
    setFeatureEnabledImpl(Features, "sse2", true);
244
14.7k
    LLVM_FALLTHROUGH;
245
14.7k
  case CK_Pentium3:
246
14.7k
  case CK_C3_2:
247
14.7k
    setFeatureEnabledImpl(Features, "sse", true);
248
14.7k
    setFeatureEnabledImpl(Features, "fxsr", true);
249
14.7k
    break;
250
14.7k
251
14.7k
  case CK_Tremont:
252
2
    setFeatureEnabledImpl(Features, "cldemote", true);
253
2
    setFeatureEnabledImpl(Features, "movdiri", true);
254
2
    setFeatureEnabledImpl(Features, "movdir64b", true);
255
2
    setFeatureEnabledImpl(Features, "gfni", true);
256
2
    setFeatureEnabledImpl(Features, "waitpkg", true);
257
2
    LLVM_FALLTHROUGH;
258
4
  case CK_GoldmontPlus:
259
4
    setFeatureEnabledImpl(Features, "ptwrite", true);
260
4
    setFeatureEnabledImpl(Features, "rdpid", true);
261
4
    setFeatureEnabledImpl(Features, "sgx", true);
262
4
    LLVM_FALLTHROUGH;
263
6
  case CK_Goldmont:
264
6
    setFeatureEnabledImpl(Features, "sha", true);
265
6
    setFeatureEnabledImpl(Features, "rdseed", true);
266
6
    setFeatureEnabledImpl(Features, "xsave", true);
267
6
    setFeatureEnabledImpl(Features, "xsaveopt", true);
268
6
    setFeatureEnabledImpl(Features, "xsavec", true);
269
6
    setFeatureEnabledImpl(Features, "xsaves", true);
270
6
    setFeatureEnabledImpl(Features, "clflushopt", true);
271
6
    setFeatureEnabledImpl(Features, "mpx", true);
272
6
    setFeatureEnabledImpl(Features, "fsgsbase", true);
273
6
    setFeatureEnabledImpl(Features, "aes", true);
274
6
    LLVM_FALLTHROUGH;
275
9
  case CK_Silvermont:
276
9
    setFeatureEnabledImpl(Features, "rdrnd", true);
277
9
    setFeatureEnabledImpl(Features, "pclmul", true);
278
9
    setFeatureEnabledImpl(Features, "sse4.2", true);
279
9
    setFeatureEnabledImpl(Features, "prfchw", true);
280
9
    LLVM_FALLTHROUGH;
281
59
  case CK_Bonnell:
282
59
    setFeatureEnabledImpl(Features, "movbe", true);
283
59
    setFeatureEnabledImpl(Features, "ssse3", true);
284
59
    setFeatureEnabledImpl(Features, "fxsr", true);
285
59
    setFeatureEnabledImpl(Features, "cx16", true);
286
59
    setFeatureEnabledImpl(Features, "sahf", true);
287
59
    break;
288
9
289
9
  case CK_KNM:
290
3
    // TODO: Add avx5124fmaps/avx5124vnniw.
291
3
    setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
292
3
    LLVM_FALLTHROUGH;
293
9
  case CK_KNL:
294
9
    setFeatureEnabledImpl(Features, "avx512f", true);
295
9
    setFeatureEnabledImpl(Features, "avx512cd", true);
296
9
    setFeatureEnabledImpl(Features, "avx512er", true);
297
9
    setFeatureEnabledImpl(Features, "avx512pf", true);
298
9
    setFeatureEnabledImpl(Features, "prfchw", true);
299
9
    setFeatureEnabledImpl(Features, "prefetchwt1", true);
300
9
    setFeatureEnabledImpl(Features, "fxsr", true);
301
9
    setFeatureEnabledImpl(Features, "rdseed", true);
302
9
    setFeatureEnabledImpl(Features, "adx", true);
303
9
    setFeatureEnabledImpl(Features, "lzcnt", true);
304
9
    setFeatureEnabledImpl(Features, "bmi", true);
305
9
    setFeatureEnabledImpl(Features, "bmi2", true);
306
9
    setFeatureEnabledImpl(Features, "fma", true);
307
9
    setFeatureEnabledImpl(Features, "rdrnd", true);
308
9
    setFeatureEnabledImpl(Features, "f16c", true);
309
9
    setFeatureEnabledImpl(Features, "fsgsbase", true);
310
9
    setFeatureEnabledImpl(Features, "aes", true);
311
9
    setFeatureEnabledImpl(Features, "pclmul", true);
312
9
    setFeatureEnabledImpl(Features, "cx16", true);
313
9
    setFeatureEnabledImpl(Features, "xsaveopt", true);
314
9
    setFeatureEnabledImpl(Features, "xsave", true);
315
9
    setFeatureEnabledImpl(Features, "movbe", true);
316
9
    setFeatureEnabledImpl(Features, "sahf", true);
317
9
    break;
318
3
319
4
  case CK_K6_2:
320
4
  case CK_K6_3:
321
4
  case CK_WinChip2:
322
4
  case CK_C3:
323
4
    setFeatureEnabledImpl(Features, "3dnow", true);
324
4
    break;
325
4
326
4
  case CK_AMDFAM10:
327
4
    setFeatureEnabledImpl(Features, "sse4a", true);
328
4
    setFeatureEnabledImpl(Features, "lzcnt", true);
329
4
    setFeatureEnabledImpl(Features, "popcnt", true);
330
4
    setFeatureEnabledImpl(Features, "sahf", true);
331
4
    LLVM_FALLTHROUGH;
332
13
  case CK_K8SSE3:
333
13
    setFeatureEnabledImpl(Features, "sse3", true);
334
13
    LLVM_FALLTHROUGH;
335
25
  case CK_K8:
336
25
    setFeatureEnabledImpl(Features, "sse2", true);
337
25
    LLVM_FALLTHROUGH;
338
28
  case CK_AthlonXP:
339
28
    setFeatureEnabledImpl(Features, "sse", true);
340
28
    setFeatureEnabledImpl(Features, "fxsr", true);
341
28
    LLVM_FALLTHROUGH;
342
31
  case CK_Athlon:
343
31
  case CK_Geode:
344
31
    setFeatureEnabledImpl(Features, "3dnowa", true);
345
31
    break;
346
31
347
31
  case CK_BTVER2:
348
12
    setFeatureEnabledImpl(Features, "avx", true);
349
12
    setFeatureEnabledImpl(Features, "aes", true);
350
12
    setFeatureEnabledImpl(Features, "pclmul", true);
351
12
    setFeatureEnabledImpl(Features, "bmi", true);
352
12
    setFeatureEnabledImpl(Features, "f16c", true);
353
12
    setFeatureEnabledImpl(Features, "xsaveopt", true);
354
12
    setFeatureEnabledImpl(Features, "movbe", true);
355
12
    LLVM_FALLTHROUGH;
356
15
  case CK_BTVER1:
357
15
    setFeatureEnabledImpl(Features, "ssse3", true);
358
15
    setFeatureEnabledImpl(Features, "sse4a", true);
359
15
    setFeatureEnabledImpl(Features, "lzcnt", true);
360
15
    setFeatureEnabledImpl(Features, "popcnt", true);
361
15
    setFeatureEnabledImpl(Features, "prfchw", true);
362
15
    setFeatureEnabledImpl(Features, "cx16", true);
363
15
    setFeatureEnabledImpl(Features, "fxsr", true);
364
15
    setFeatureEnabledImpl(Features, "sahf", true);
365
15
    break;
366
12
367
12
  case CK_ZNVER2:
368
3
    setFeatureEnabledImpl(Features, "clwb", true);
369
3
    setFeatureEnabledImpl(Features, "rdpid", true);
370
3
    setFeatureEnabledImpl(Features, "wbnoinvd", true);
371
3
    LLVM_FALLTHROUGH;
372
6
  case CK_ZNVER1:
373
6
    setFeatureEnabledImpl(Features, "adx", true);
374
6
    setFeatureEnabledImpl(Features, "aes", true);
375
6
    setFeatureEnabledImpl(Features, "avx2", true);
376
6
    setFeatureEnabledImpl(Features, "bmi", true);
377
6
    setFeatureEnabledImpl(Features, "bmi2", true);
378
6
    setFeatureEnabledImpl(Features, "clflushopt", true);
379
6
    setFeatureEnabledImpl(Features, "clzero", true);
380
6
    setFeatureEnabledImpl(Features, "cx16", true);
381
6
    setFeatureEnabledImpl(Features, "f16c", true);
382
6
    setFeatureEnabledImpl(Features, "fma", true);
383
6
    setFeatureEnabledImpl(Features, "fsgsbase", true);
384
6
    setFeatureEnabledImpl(Features, "fxsr", true);
385
6
    setFeatureEnabledImpl(Features, "lzcnt", true);
386
6
    setFeatureEnabledImpl(Features, "mwaitx", true);
387
6
    setFeatureEnabledImpl(Features, "movbe", true);
388
6
    setFeatureEnabledImpl(Features, "pclmul", true);
389
6
    setFeatureEnabledImpl(Features, "popcnt", true);
390
6
    setFeatureEnabledImpl(Features, "prfchw", true);
391
6
    setFeatureEnabledImpl(Features, "rdrnd", true);
392
6
    setFeatureEnabledImpl(Features, "rdseed", true);
393
6
    setFeatureEnabledImpl(Features, "sahf", true);
394
6
    setFeatureEnabledImpl(Features, "sha", true);
395
6
    setFeatureEnabledImpl(Features, "sse4a", true);
396
6
    setFeatureEnabledImpl(Features, "xsave", true);
397
6
    setFeatureEnabledImpl(Features, "xsavec", true);
398
6
    setFeatureEnabledImpl(Features, "xsaveopt", true);
399
6
    setFeatureEnabledImpl(Features, "xsaves", true);
400
6
    break;
401
3
402
3
  case CK_BDVER4:
403
3
    setFeatureEnabledImpl(Features, "avx2", true);
404
3
    setFeatureEnabledImpl(Features, "bmi2", true);
405
3
    setFeatureEnabledImpl(Features, "mwaitx", true);
406
3
    LLVM_FALLTHROUGH;
407
6
  case CK_BDVER3:
408
6
    setFeatureEnabledImpl(Features, "fsgsbase", true);
409
6
    setFeatureEnabledImpl(Features, "xsaveopt", true);
410
6
    LLVM_FALLTHROUGH;
411
10
  case CK_BDVER2:
412
10
    setFeatureEnabledImpl(Features, "bmi", true);
413
10
    setFeatureEnabledImpl(Features, "fma", true);
414
10
    setFeatureEnabledImpl(Features, "f16c", true);
415
10
    setFeatureEnabledImpl(Features, "tbm", true);
416
10
    LLVM_FALLTHROUGH;
417
14
  case CK_BDVER1:
418
14
    // xop implies avx, sse4a and fma4.
419
14
    setFeatureEnabledImpl(Features, "xop", true);
420
14
    setFeatureEnabledImpl(Features, "lwp", true);
421
14
    setFeatureEnabledImpl(Features, "lzcnt", true);
422
14
    setFeatureEnabledImpl(Features, "aes", true);
423
14
    setFeatureEnabledImpl(Features, "pclmul", true);
424
14
    setFeatureEnabledImpl(Features, "prfchw", true);
425
14
    setFeatureEnabledImpl(Features, "cx16", true);
426
14
    setFeatureEnabledImpl(Features, "fxsr", true);
427
14
    setFeatureEnabledImpl(Features, "xsave", true);
428
14
    setFeatureEnabledImpl(Features, "sahf", true);
429
14
    break;
430
82.6k
  }
431
82.6k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
432
0
    return false;
433
82.6k
434
82.6k
  // Can't do this earlier because we need to be able to explicitly enable
435
82.6k
  // or disable these features and the things that they depend upon.
436
82.6k
437
82.6k
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
438
82.6k
  auto I = Features.find("sse4.2");
439
82.6k
  if (I != Features.end() && 
I->getValue()42.7k
&&
440
82.6k
      
llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()42.6k
)
441
42.6k
    Features["popcnt"] = true;
442
82.6k
443
82.6k
  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
444
82.6k
  I = Features.find("3dnow");
445
82.6k
  if (I != Features.end() && 
I->getValue()296
&&
446
82.6k
      
llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()289
)
447
288
    Features["prfchw"] = true;
448
82.6k
449
82.6k
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
450
82.6k
  // then enable MMX.
451
82.6k
  I = Features.find("sse");
452
82.6k
  if (I != Features.end() && 
I->getValue()78.8k
&&
453
82.6k
      
llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()78.8k
)
454
78.8k
    Features["mmx"] = true;
455
82.6k
456
82.6k
  return true;
457
82.6k
}
458
459
void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
460
370k
                                X86SSEEnum Level, bool Enabled) {
461
370k
  if (Enabled) {
462
370k
    switch (Level) {
463
370k
    case AVX512F:
464
85.3k
      Features["avx512f"] = true;
465
85.3k
      Features["fma"] = true;
466
85.3k
      Features["f16c"] = true;
467
85.3k
      LLVM_FALLTHROUGH;
468
99.1k
    case AVX2:
469
99.1k
      Features["avx2"] = true;
470
99.1k
      LLVM_FALLTHROUGH;
471
140k
    case AVX:
472
140k
      Features["avx"] = true;
473
140k
      Features["xsave"] = true;
474
140k
      LLVM_FALLTHROUGH;
475
153k
    case SSE42:
476
153k
      Features["sse4.2"] = true;
477
153k
      LLVM_FALLTHROUGH;
478
175k
    case SSE41:
479
175k
      Features["sse4.1"] = true;
480
175k
      LLVM_FALLTHROUGH;
481
200k
    case SSSE3:
482
200k
      Features["ssse3"] = true;
483
200k
      LLVM_FALLTHROUGH;
484
227k
    case SSE3:
485
227k
      Features["sse3"] = true;
486
227k
      LLVM_FALLTHROUGH;
487
341k
    case SSE2:
488
341k
      Features["sse2"] = true;
489
341k
      LLVM_FALLTHROUGH;
490
370k
    case SSE1:
491
370k
      Features["sse"] = true;
492
370k
      LLVM_FALLTHROUGH;
493
370k
    case NoSSE:
494
370k
      break;
495
370k
    }
496
370k
    return;
497
370k
  }
498
37
499
37
  switch (Level) {
500
37
  case NoSSE:
501
6
  case SSE1:
502
6
    Features["sse"] = false;
503
6
    LLVM_FALLTHROUGH;
504
19
  case SSE2:
505
19
    Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
506
19
    Features["sha"] = Features["gfni"] = false;
507
19
    LLVM_FALLTHROUGH;
508
20
  case SSE3:
509
20
    Features["sse3"] = false;
510
20
    setXOPLevel(Features, NoXOP, false);
511
20
    LLVM_FALLTHROUGH;
512
21
  case SSSE3:
513
21
    Features["ssse3"] = false;
514
21
    LLVM_FALLTHROUGH;
515
25
  case SSE41:
516
25
    Features["sse4.1"] = false;
517
25
    LLVM_FALLTHROUGH;
518
27
  case SSE42:
519
27
    Features["sse4.2"] = false;
520
27
    LLVM_FALLTHROUGH;
521
31
  case AVX:
522
31
    Features["fma"] = Features["avx"] = Features["f16c"] = false;
523
31
    Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false;
524
31
    Features["vpclmulqdq"] = false;
525
31
    setXOPLevel(Features, FMA4, false);
526
31
    LLVM_FALLTHROUGH;
527
32
  case AVX2:
528
32
    Features["avx2"] = false;
529
32
    LLVM_FALLTHROUGH;
530
37
  case AVX512F:
531
37
    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false;
532
37
    Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false;
533
37
    Features["avx512vl"] = Features["avx512vbmi"] = false;
534
37
    Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
535
37
    Features["avx512bitalg"] = Features["avx512vnni"] = false;
536
37
    Features["avx512vbmi2"] = Features["avx512bf16"] = false;
537
37
    Features["avx512vp2intersect"] = false;
538
37
    break;
539
37
  }
540
37
}
541
542
void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
543
14.2k
                                MMX3DNowEnum Level, bool Enabled) {
544
14.2k
  if (Enabled) {
545
14.2k
    switch (Level) {
546
14.2k
    case AMD3DNowAthlon:
547
331
      Features["3dnowa"] = true;
548
331
      LLVM_FALLTHROUGH;
549
539
    case AMD3DNow:
550
539
      Features["3dnow"] = true;
551
539
      LLVM_FALLTHROUGH;
552
14.2k
    case MMX:
553
14.2k
      Features["mmx"] = true;
554
14.2k
      LLVM_FALLTHROUGH;
555
14.2k
    case NoMMX3DNow:
556
14.2k
      break;
557
14.2k
    }
558
14.2k
    return;
559
14.2k
  }
560
7
561
7
  switch (Level) {
562
7
  case NoMMX3DNow:
563
6
  case MMX:
564
6
    Features["mmx"] = false;
565
6
    LLVM_FALLTHROUGH;
566
7
  case AMD3DNow:
567
7
    Features["3dnow"] = false;
568
7
    LLVM_FALLTHROUGH;
569
7
  case AMD3DNowAthlon:
570
7
    Features["3dnowa"] = false;
571
7
    break;
572
7
  }
573
7
}
574
575
void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
576
3.02k
                                bool Enabled) {
577
3.02k
  if (Enabled) {
578
2.97k
    switch (Level) {
579
2.97k
    case XOP:
580
2.05k
      Features["xop"] = true;
581
2.05k
      LLVM_FALLTHROUGH;
582
2.61k
    case FMA4:
583
2.61k
      Features["fma4"] = true;
584
2.61k
      setSSELevel(Features, AVX, true);
585
2.61k
      LLVM_FALLTHROUGH;
586
2.97k
    case SSE4A:
587
2.97k
      Features["sse4a"] = true;
588
2.97k
      setSSELevel(Features, SSE3, true);
589
2.97k
      LLVM_FALLTHROUGH;
590
2.97k
    case NoXOP:
591
2.97k
      break;
592
2.97k
    }
593
2.97k
    return;
594
2.97k
  }
595
54
596
54
  switch (Level) {
597
54
  case NoXOP:
598
21
  case SSE4A:
599
21
    Features["sse4a"] = false;
600
21
    LLVM_FALLTHROUGH;
601
53
  case FMA4:
602
53
    Features["fma4"] = false;
603
53
    LLVM_FALLTHROUGH;
604
54
  case XOP:
605
54
    Features["xop"] = false;
606
54
    break;
607
54
  }
608
54
}
609
610
void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
611
675k
                                          StringRef Name, bool Enabled) {
612
675k
  // This is a bit of a hack to deal with the sse4 target feature when used
613
675k
  // as part of the target attribute. We handle sse4 correctly everywhere
614
675k
  // else. See below for more information on how we handle the sse4 options.
615
675k
  if (Name != "sse4")
616
675k
    Features[Name] = Enabled;
617
675k
618
675k
  if (Name == "mmx") {
619
13.6k
    setMMXLevel(Features, MMX, Enabled);
620
661k
  } else if (Name == "sse") {
621
29.5k
    setSSELevel(Features, SSE1, Enabled);
622
631k
  } else if (Name == "sse2") {
623
110k
    setSSELevel(Features, SSE2, Enabled);
624
521k
  } else if (Name == "sse3") {
625
24.3k
    setSSELevel(Features, SSE3, Enabled);
626
497k
  } else if (Name == "ssse3") {
627
24.8k
    setSSELevel(Features, SSSE3, Enabled);
628
472k
  } else if (Name == "sse4.2") {
629
13.0k
    setSSELevel(Features, SSE42, Enabled);
630
459k
  } else if (Name == "sse4.1") {
631
22.2k
    setSSELevel(Features, SSE41, Enabled);
632
437k
  } else if (Name == "3dnow") {
633
209
    setMMXLevel(Features, AMD3DNow, Enabled);
634
436k
  } else if (Name == "3dnowa") {
635
331
    setMMXLevel(Features, AMD3DNowAthlon, Enabled);
636
436k
  } else if (Name == "aes") {
637
1.94k
    if (Enabled)
638
1.04k
      setSSELevel(Features, SSE2, Enabled);
639
895
    else
640
895
      Features["vaes"] = false;
641
434k
  } else if (Name == "vaes") {
642
179
    if (Enabled) {
643
118
      setSSELevel(Features, AVX, Enabled);
644
118
      Features["aes"] = true;
645
118
    }
646
434k
  } else if (Name == "pclmul") {
647
2.96k
    if (Enabled)
648
2.06k
      setSSELevel(Features, SSE2, Enabled);
649
893
    else
650
893
      Features["vpclmulqdq"] = false;
651
431k
  } else if (Name == "vpclmulqdq") {
652
74
    if (Enabled) {
653
13
      setSSELevel(Features, AVX, Enabled);
654
13
      Features["pclmul"] = true;
655
13
    }
656
431k
  } else if (Name == "gfni") {
657
188
     if (Enabled)
658
187
      setSSELevel(Features, SSE2, Enabled);
659
431k
  } else if (Name == "avx") {
660
17.7k
    setSSELevel(Features, AVX, Enabled);
661
413k
  } else if (Name == "avx2") {
662
13.7k
    setSSELevel(Features, AVX2, Enabled);
663
399k
  } else if (Name == "avx512f") {
664
32.3k
    setSSELevel(Features, AVX512F, Enabled);
665
367k
  } else if (Name.startswith("avx512")) {
666
53.0k
    if (Enabled)
667
53.0k
      setSSELevel(Features, AVX512F, Enabled);
668
53.0k
    // Enable BWI instruction if certain features are being enabled.
669
53.0k
    if ((Name == "avx512vbmi" || 
Name == "avx512vbmi2"52.6k
||
670
53.0k
         
Name == "avx512bitalg"51.3k
||
Name == "avx512bf16"51.0k
) &&
Enabled2.49k
)
671
2.49k
      Features["avx512bw"] = true;
672
53.0k
    // Also disable some features if BWI is being disabled.
673
53.0k
    if (Name == "avx512bw" && 
!Enabled16.7k
) {
674
5
      Features["avx512vbmi"] = false;
675
5
      Features["avx512vbmi2"] = false;
676
5
      Features["avx512bitalg"] = false;
677
5
      Features["avx512bf16"] = false;
678
5
    }
679
314k
  } else if (Name == "fma") {
680
10.4k
    if (Enabled)
681
10.4k
      setSSELevel(Features, AVX, Enabled);
682
1
    else
683
1
      setSSELevel(Features, AVX512F, Enabled);
684
303k
  } else if (Name == "fma4") {
685
560
    setXOPLevel(Features, FMA4, Enabled);
686
303k
  } else if (Name == "xop") {
687
2.06k
    setXOPLevel(Features, XOP, Enabled);
688
301k
  } else if (Name == "sse4a") {
689
353
    setXOPLevel(Features, SSE4A, Enabled);
690
300k
  } else if (Name == "f16c") {
691
10.2k
    if (Enabled)
692
10.2k
      setSSELevel(Features, AVX, Enabled);
693
1
    else
694
1
      setSSELevel(Features, AVX512F, Enabled);
695
290k
  } else if (Name == "sha") {
696
81
    if (Enabled)
697
79
      setSSELevel(Features, SSE2, Enabled);
698
290k
  } else if (Name == "sse4") {
699
4
    // We can get here via the __target__ attribute since that's not controlled
700
4
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
701
4
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
702
4
    // disabled.
703
4
    if (Enabled)
704
2
      setSSELevel(Features, SSE42, Enabled);
705
2
    else
706
2
      setSSELevel(Features, SSE41, Enabled);
707
290k
  } else if (Name == "xsave") {
708
13.0k
    if (!Enabled)
709
2
      Features["xsaveopt"] = false;
710
277k
  } else if (Name == "xsaveopt" || 
Name == "xsavec"274k
||
Name == "xsaves"272k
) {
711
6.42k
    if (Enabled)
712
6.42k
      Features["xsave"] = true;
713
6.42k
  }
714
675k
}
715
716
/// handleTargetFeatures - Perform initialization based on the user
717
/// configured set of features.
718
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
719
33.2k
                                         DiagnosticsEngine &Diags) {
720
238k
  for (const auto &Feature : Features) {
721
238k
    if (Feature[0] != '+')
722
5.35k
      continue;
723
233k
724
233k
    if (Feature == "+aes") {
725
85
      HasAES = true;
726
232k
    } else if (Feature == "+vaes") {
727
9
      HasVAES = true;
728
232k
    } else if (Feature == "+pclmul") {
729
109
      HasPCLMUL = true;
730
232k
    } else if (Feature == "+vpclmulqdq") {
731
9
      HasVPCLMULQDQ = true;
732
232k
    } else if (Feature == "+lzcnt") {
733
766
      HasLZCNT = true;
734
232k
    } else if (Feature == "+rdrnd") {
735
70
      HasRDRND = true;
736
232k
    } else if (Feature == "+fsgsbase") {
737
73
      HasFSGSBASE = true;
738
231k
    } else if (Feature == "+bmi") {
739
755
      HasBMI = true;
740
231k
    } else if (Feature == "+bmi2") {
741
737
      HasBMI2 = true;
742
230k
    } else if (Feature == "+popcnt") {
743
914
      HasPOPCNT = true;
744
229k
    } else if (Feature == "+rtm") {
745
1
      HasRTM = true;
746
229k
    } else if (Feature == "+prfchw") {
747
130
      HasPRFCHW = true;
748
229k
    } else if (Feature == "+rdseed") {
749
60
      HasRDSEED = true;
750
229k
    } else if (Feature == "+adx") {
751
54
      HasADX = true;
752
229k
    } else if (Feature == "+tbm") {
753
11
      HasTBM = true;
754
229k
    } else if (Feature == "+lwp") {
755
15
      HasLWP = true;
756
229k
    } else if (Feature == "+fma") {
757
811
      HasFMA = true;
758
228k
    } else if (Feature == "+f16c") {
759
827
      HasF16C = true;
760
227k
    } else if (Feature == "+gfni") {
761
12
      HasGFNI = true;
762
227k
    } else if (Feature == "+avx512cd") {
763
41
      HasAVX512CD = true;
764
227k
    } else if (Feature == "+avx512vpopcntdq") {
765
11
      HasAVX512VPOPCNTDQ = true;
766
227k
    } else if (Feature == "+avx512vnni") {
767
13
      HasAVX512VNNI = true;
768
227k
    } else if (Feature == "+avx512bf16") {
769
6
      HasAVX512BF16 = true;
770
227k
    } else if (Feature == "+avx512er") {
771
12
      HasAVX512ER = true;
772
227k
    } else if (Feature == "+avx512pf") {
773
11
      HasAVX512PF = true;
774
227k
    } else if (Feature == "+avx512dq") {
775
32
      HasAVX512DQ = true;
776
227k
    } else if (Feature == "+avx512bitalg") {
777
9
      HasAVX512BITALG = true;
778
227k
    } else if (Feature == "+avx512bw") {
779
48
      HasAVX512BW = true;
780
227k
    } else if (Feature == "+avx512vl") {
781
45
      HasAVX512VL = true;
782
227k
    } else if (Feature == "+avx512vbmi") {
783
12
      HasAVX512VBMI = true;
784
227k
    } else if (Feature == "+avx512vbmi2") {
785
9
      HasAVX512VBMI2 = true;
786
227k
    } else if (Feature == "+avx512ifma") {
787
12
      HasAVX512IFMA = true;
788
227k
    } else if (Feature == "+avx512vp2intersect") {
789
5
      HasAVX512VP2INTERSECT = true;
790
227k
    } else if (Feature == "+sha") {
791
23
      HasSHA = true;
792
227k
    } else if (Feature == "+mpx") {
793
39
      HasMPX = true;
794
227k
    } else if (Feature == "+shstk") {
795
6
      HasSHSTK = true;
796
227k
    } else if (Feature == "+movbe") {
797
805
      HasMOVBE = true;
798
226k
    } else if (Feature == "+sgx") {
799
19
      HasSGX = true;
800
226k
    } else if (Feature == "+cx8") {
801
33.1k
      HasCX8 = true;
802
193k
    } else if (Feature == "+cx16") {
803
10.5k
      HasCX16 = true;
804
182k
    } else if (Feature == "+fxsr") {
805
13.1k
      HasFXSR = true;
806
169k
    } else if (Feature == "+xsave") {
807
909
      HasXSAVE = true;
808
168k
    } else if (Feature == "+xsaveopt") {
809
774
      HasXSAVEOPT = true;
810
167k
    } else if (Feature == "+xsavec") {
811
53
      HasXSAVEC = true;
812
167k
    } else if (Feature == "+xsaves") {
813
53
      HasXSAVES = true;
814
167k
    } else if (Feature == "+mwaitx") {
815
12
      HasMWAITX = true;
816
167k
    } else if (Feature == "+pku") {
817
30
      HasPKU = true;
818
167k
    } else if (Feature == "+clflushopt") {
819
47
      HasCLFLUSHOPT = true;
820
167k
    } else if (Feature == "+clwb") {
821
30
      HasCLWB = true;
822
167k
    } else if (Feature == "+wbnoinvd") {
823
10
      HasWBNOINVD = true;
824
167k
    } else if (Feature == "+prefetchwt1") {
825
9
      HasPREFETCHWT1 = true;
826
167k
    } else if (Feature == "+clzero") {
827
10
      HasCLZERO = true;
828
167k
    } else if (Feature == "+cldemote") {
829
7
      HasCLDEMOTE = true;
830
167k
    } else if (Feature == "+rdpid") {
831
15
      HasRDPID = true;
832
167k
    } else if (Feature == "+retpoline-external-thunk") {
833
0
      HasRetpolineExternalThunk = true;
834
167k
    } else if (Feature == "+sahf") {
835
10.5k
      HasLAHFSAHF = true;
836
157k
    } else if (Feature == "+waitpkg") {
837
4
      HasWAITPKG = true;
838
157k
    } else if (Feature == "+movdiri") {
839
7
      HasMOVDIRI = true;
840
157k
    } else if (Feature == "+movdir64b") {
841
7
      HasMOVDIR64B = true;
842
157k
    } else if (Feature == "+pconfig") {
843
5
      HasPCONFIG = true;
844
157k
    } else if (Feature == "+ptwrite") {
845
6
      HasPTWRITE = true;
846
157k
    } else if (Feature == "+invpcid") {
847
719
      HasINVPCID = true;
848
156k
    } else if (Feature == "+enqcmd") {
849
3
      HasENQCMD = true;
850
3
    }
851
233k
852
233k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
853
233k
                           .Case("+avx512f", AVX512F)
854
233k
                           .Case("+avx2", AVX2)
855
233k
                           .Case("+avx", AVX)
856
233k
                           .Case("+sse4.2", SSE42)
857
233k
                           .Case("+sse4.1", SSE41)
858
233k
                           .Case("+ssse3", SSSE3)
859
233k
                           .Case("+sse3", SSE3)
860
233k
                           .Case("+sse2", SSE2)
861
233k
                           .Case("+sse", SSE1)
862
233k
                           .Default(NoSSE);
863
233k
    SSELevel = std::max(SSELevel, Level);
864
233k
865
233k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
866
233k
                                      .Case("+3dnowa", AMD3DNowAthlon)
867
233k
                                      .Case("+3dnow", AMD3DNow)
868
233k
                                      .Case("+mmx", MMX)
869
233k
                                      .Default(NoMMX3DNow);
870
233k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
871
233k
872
233k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
873
233k
                         .Case("+xop", XOP)
874
233k
                         .Case("+fma4", FMA4)
875
233k
                         .Case("+sse4a", SSE4A)
876
233k
                         .Default(NoXOP);
877
233k
    XOPLevel = std::max(XOPLevel, XLevel);
878
233k
  }
879
33.2k
880
33.2k
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
881
33.2k
  // matches the selected sse level.
882
33.2k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
883
33.2k
      (FPMath == FP_387 && 
SSELevel >= SSE12
)) {
884
2
    Diags.Report(diag::err_target_unsupported_fpmath)
885
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
886
2
    return false;
887
2
  }
888
33.2k
889
33.2k
  SimdDefaultAlign =
890
33.2k
      hasFeature("avx512f") ? 
512104
:
hasFeature("avx") 33.1k
?
256775
:
12832.3k
;
891
33.2k
  return true;
892
33.2k
}
893
894
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
895
/// definitions for this particular subtarget.
896
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
897
32.9k
                                     MacroBuilder &Builder) const {
898
32.9k
  // Inline assembly supports X86 flag outputs. 
899
32.9k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
900
32.9k
901
32.9k
  std::string CodeModel = getTargetOpts().CodeModel;
902
32.9k
  if (CodeModel == "default")
903
32.8k
    CodeModel = "small";
904
32.9k
  Builder.defineMacro("__code_model_" + CodeModel + "_");
905
32.9k
906
32.9k
  // Target identification.
907
32.9k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
908
27.0k
    Builder.defineMacro("__amd64__");
909
27.0k
    Builder.defineMacro("__amd64");
910
27.0k
    Builder.defineMacro("__x86_64");
911
27.0k
    Builder.defineMacro("__x86_64__");
912
27.0k
    if (getTriple().getArchName() == "x86_64h") {
913
676
      Builder.defineMacro("__x86_64h");
914
676
      Builder.defineMacro("__x86_64h__");
915
676
    }
916
27.0k
  } else {
917
5.93k
    DefineStd(Builder, "i386", Opts);
918
5.93k
  }
919
32.9k
920
32.9k
  Builder.defineMacro("__SEG_GS");
921
32.9k
  Builder.defineMacro("__SEG_FS");
922
32.9k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
923
32.9k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
924
32.9k
925
32.9k
  // Subtarget options.
926
32.9k
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
927
32.9k
  // truly should be based on -mtune options.
928
32.9k
  switch (CPU) {
929
32.9k
  case CK_Generic:
930
19.6k
    break;
931
32.9k
  case CK_i386:
932
14
    // The rest are coming from the i386 define above.
933
14
    Builder.defineMacro("__tune_i386__");
934
14
    break;
935
32.9k
  case CK_i486:
936
8
  case CK_WinChipC6:
937
8
  case CK_WinChip2:
938
8
  case CK_C3:
939
8
    defineCPUMacros(Builder, "i486");
940
8
    break;
941
8
  case CK_PentiumMMX:
942
1
    Builder.defineMacro("__pentium_mmx__");
943
1
    Builder.defineMacro("__tune_pentium_mmx__");
944
1
    LLVM_FALLTHROUGH;
945
172
  case CK_i586:
946
172
  case CK_Pentium:
947
172
    defineCPUMacros(Builder, "i586");
948
172
    defineCPUMacros(Builder, "pentium");
949
172
    break;
950
172
  case CK_Pentium3:
951
7
  case CK_PentiumM:
952
7
    Builder.defineMacro("__tune_pentium3__");
953
7
    LLVM_FALLTHROUGH;
954
9
  case CK_Pentium2:
955
9
  case CK_C3_2:
956
9
    Builder.defineMacro("__tune_pentium2__");
957
9
    LLVM_FALLTHROUGH;
958
25
  case CK_PentiumPro:
959
25
  case CK_i686:
960
25
    defineCPUMacros(Builder, "i686");
961
25
    defineCPUMacros(Builder, "pentiumpro");
962
25
    break;
963
1.93k
  case CK_Pentium4:
964
1.93k
    defineCPUMacros(Builder, "pentium4");
965
1.93k
    break;
966
365
  case CK_Yonah:
967
365
  case CK_Prescott:
968
365
  case CK_Nocona:
969
365
    defineCPUMacros(Builder, "nocona");
970
365
    break;
971
9.69k
  case CK_Core2:
972
9.69k
  case CK_Penryn:
973
9.69k
    defineCPUMacros(Builder, "core2");
974
9.69k
    break;
975
9.69k
  case CK_Bonnell:
976
50
    defineCPUMacros(Builder, "atom");
977
50
    break;
978
9.69k
  case CK_Silvermont:
979
3
    defineCPUMacros(Builder, "slm");
980
3
    break;
981
9.69k
  case CK_Goldmont:
982
2
    defineCPUMacros(Builder, "goldmont");
983
2
    break;
984
9.69k
  case CK_GoldmontPlus:
985
2
    defineCPUMacros(Builder, "goldmont_plus");
986
2
    break;
987
9.69k
  case CK_Tremont:
988
2
    defineCPUMacros(Builder, "tremont");
989
2
    break;
990
9.69k
  case CK_Nehalem:
991
735
  case CK_Westmere:
992
735
  case CK_SandyBridge:
993
735
  case CK_IvyBridge:
994
735
  case CK_Haswell:
995
735
  case CK_Broadwell:
996
735
  case CK_SkylakeClient:
997
735
  case CK_SkylakeServer:
998
735
  case CK_Cascadelake:
999
735
  case CK_Cooperlake:
1000
735
  case CK_Cannonlake:
1001
735
  case CK_IcelakeClient:
1002
735
  case CK_IcelakeServer:
1003
735
    // FIXME: Historically, we defined this legacy name, it would be nice to
1004
735
    // remove it at some point. We've never exposed fine-grained names for
1005
735
    // recent primary x86 CPUs, and we should keep it that way.
1006
735
    defineCPUMacros(Builder, "corei7");
1007
735
    break;
1008
735
  case CK_KNL:
1009
6
    defineCPUMacros(Builder, "knl");
1010
6
    break;
1011
735
  case CK_KNM:
1012
3
    break;
1013
735
  case CK_Lakemont:
1014
1
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
1015
1
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
1016
1
    Builder.defineMacro("__tune_lakemont__");
1017
1
    break;
1018
735
  case CK_K6_2:
1019
1
    Builder.defineMacro("__k6_2__");
1020
1
    Builder.defineMacro("__tune_k6_2__");
1021
1
    LLVM_FALLTHROUGH;
1022
2
  case CK_K6_3:
1023
2
    if (CPU != CK_K6_2) { // In case of fallthrough
1024
1
      // FIXME: GCC may be enabling these in cases where some other k6
1025
1
      // architecture is specified but -m3dnow is explicitly provided. The
1026
1
      // exact semantics need to be determined and emulated here.
1027
1
      Builder.defineMacro("__k6_3__");
1028
1
      Builder.defineMacro("__tune_k6_3__");
1029
1
    }
1030
2
    LLVM_FALLTHROUGH;
1031
3
  case CK_K6:
1032
3
    defineCPUMacros(Builder, "k6");
1033
3
    break;
1034
5
  case CK_Athlon:
1035
5
  case CK_AthlonXP:
1036
5
    defineCPUMacros(Builder, "athlon");
1037
5
    if (SSELevel != NoSSE) {
1038
3
      Builder.defineMacro("__athlon_sse__");
1039
3
      Builder.defineMacro("__tune_athlon_sse__");
1040
3
    }
1041
5
    break;
1042
219
  case CK_K8:
1043
219
  case CK_K8SSE3:
1044
219
  case CK_x86_64:
1045
219
    defineCPUMacros(Builder, "k8");
1046
219
    break;
1047
219
  case CK_AMDFAM10:
1048
4
    defineCPUMacros(Builder, "amdfam10");
1049
4
    break;
1050
219
  case CK_BTVER1:
1051
3
    defineCPUMacros(Builder, "btver1");
1052
3
    break;
1053
219
  case CK_BTVER2:
1054
10
    defineCPUMacros(Builder, "btver2");
1055
10
    break;
1056
219
  case CK_BDVER1:
1057
4
    defineCPUMacros(Builder, "bdver1");
1058
4
    break;
1059
219
  case CK_BDVER2:
1060
4
    defineCPUMacros(Builder, "bdver2");
1061
4
    break;
1062
219
  case CK_BDVER3:
1063
3
    defineCPUMacros(Builder, "bdver3");
1064
3
    break;
1065
219
  case CK_BDVER4:
1066
3
    defineCPUMacros(Builder, "bdver4");
1067
3
    break;
1068
219
  case CK_ZNVER1:
1069
3
    defineCPUMacros(Builder, "znver1");
1070
3
    break;
1071
219
  case CK_ZNVER2:
1072
3
    defineCPUMacros(Builder, "znver2");
1073
3
    break;
1074
219
  case CK_Geode:
1075
1
    defineCPUMacros(Builder, "geode");
1076
1
    break;
1077
32.9k
  }
1078
32.9k
1079
32.9k
  // Target properties.
1080
32.9k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
1081
32.9k
1082
32.9k
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1083
32.9k
  // functions in glibc header files that use FP Stack inline asm which the
1084
32.9k
  // backend can't deal with (PR879).
1085
32.9k
  Builder.defineMacro("__NO_MATH_INLINES");
1086
32.9k
1087
32.9k
  if (HasAES)
1088
83
    Builder.defineMacro("__AES__");
1089
32.9k
1090
32.9k
  if (HasVAES)
1091
9
    Builder.defineMacro("__VAES__");
1092
32.9k
1093
32.9k
  if (HasPCLMUL)
1094
107
    Builder.defineMacro("__PCLMUL__");
1095
32.9k
1096
32.9k
  if (HasVPCLMULQDQ)
1097
9
    Builder.defineMacro("__VPCLMULQDQ__");
1098
32.9k
1099
32.9k
  if (HasLZCNT)
1100
764
    Builder.defineMacro("__LZCNT__");
1101
32.9k
1102
32.9k
  if (HasRDRND)
1103
70
    Builder.defineMacro("__RDRND__");
1104
32.9k
1105
32.9k
  if (HasFSGSBASE)
1106
73
    Builder.defineMacro("__FSGSBASE__");
1107
32.9k
1108
32.9k
  if (HasBMI)
1109
753
    Builder.defineMacro("__BMI__");
1110
32.9k
1111
32.9k
  if (HasBMI2)
1112
737
    Builder.defineMacro("__BMI2__");
1113
32.9k
1114
32.9k
  if (HasPOPCNT)
1115
912
    Builder.defineMacro("__POPCNT__");
1116
32.9k
1117
32.9k
  if (HasRTM)
1118
1
    Builder.defineMacro("__RTM__");
1119
32.9k
1120
32.9k
  if (HasPRFCHW)
1121
128
    Builder.defineMacro("__PRFCHW__");
1122
32.9k
1123
32.9k
  if (HasRDSEED)
1124
60
    Builder.defineMacro("__RDSEED__");
1125
32.9k
1126
32.9k
  if (HasADX)
1127
54
    Builder.defineMacro("__ADX__");
1128
32.9k
1129
32.9k
  if (HasTBM)
1130
11
    Builder.defineMacro("__TBM__");
1131
32.9k
1132
32.9k
  if (HasLWP)
1133
15
    Builder.defineMacro("__LWP__");
1134
32.9k
1135
32.9k
  if (HasMWAITX)
1136
12
    Builder.defineMacro("__MWAITX__");
1137
32.9k
1138
32.9k
  if (HasMOVBE)
1139
803
    Builder.defineMacro("__MOVBE__");
1140
32.9k
1141
32.9k
  switch (XOPLevel) {
1142
32.9k
  case XOP:
1143
18
    Builder.defineMacro("__XOP__");
1144
18
    LLVM_FALLTHROUGH;
1145
19
  case FMA4:
1146
19
    Builder.defineMacro("__FMA4__");
1147
19
    LLVM_FALLTHROUGH;
1148
44
  case SSE4A:
1149
44
    Builder.defineMacro("__SSE4A__");
1150
44
    LLVM_FALLTHROUGH;
1151
32.9k
  case NoXOP:
1152
32.9k
    break;
1153
32.9k
  }
1154
32.9k
1155
32.9k
  if (HasFMA)
1156
811
    Builder.defineMacro("__FMA__");
1157
32.9k
1158
32.9k
  if (HasF16C)
1159
825
    Builder.defineMacro("__F16C__");
1160
32.9k
1161
32.9k
  if (HasGFNI)
1162
12
    Builder.defineMacro("__GFNI__");
1163
32.9k
1164
32.9k
  if (HasAVX512CD)
1165
41
    Builder.defineMacro("__AVX512CD__");
1166
32.9k
  if (HasAVX512VPOPCNTDQ)
1167
11
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
1168
32.9k
  if (HasAVX512VNNI)
1169
13
    Builder.defineMacro("__AVX512VNNI__");
1170
32.9k
  if (HasAVX512BF16)
1171
6
    Builder.defineMacro("__AVX512BF16__");
1172
32.9k
  if (HasAVX512ER)
1173
12
    Builder.defineMacro("__AVX512ER__");
1174
32.9k
  if (HasAVX512PF)
1175
11
    Builder.defineMacro("__AVX512PF__");
1176
32.9k
  if (HasAVX512DQ)
1177
32
    Builder.defineMacro("__AVX512DQ__");
1178
32.9k
  if (HasAVX512BITALG)
1179
9
    Builder.defineMacro("__AVX512BITALG__");
1180
32.9k
  if (HasAVX512BW)
1181
48
    Builder.defineMacro("__AVX512BW__");
1182
32.9k
  if (HasAVX512VL)
1183
45
    Builder.defineMacro("__AVX512VL__");
1184
32.9k
  if (HasAVX512VBMI)
1185
12
    Builder.defineMacro("__AVX512VBMI__");
1186
32.9k
  if (HasAVX512VBMI2)
1187
9
    Builder.defineMacro("__AVX512VBMI2__");
1188
32.9k
  if (HasAVX512IFMA)
1189
12
    Builder.defineMacro("__AVX512IFMA__");
1190
32.9k
  if (HasAVX512VP2INTERSECT)
1191
5
    Builder.defineMacro("__AVX512VP2INTERSECT__");
1192
32.9k
  if (HasSHA)
1193
23
    Builder.defineMacro("__SHA__");
1194
32.9k
1195
32.9k
  if (HasFXSR)
1196
13.0k
    Builder.defineMacro("__FXSR__");
1197
32.9k
  if (HasXSAVE)
1198
907
    Builder.defineMacro("__XSAVE__");
1199
32.9k
  if (HasXSAVEOPT)
1200
772
    Builder.defineMacro("__XSAVEOPT__");
1201
32.9k
  if (HasXSAVEC)
1202
53
    Builder.defineMacro("__XSAVEC__");
1203
32.9k
  if (HasXSAVES)
1204
53
    Builder.defineMacro("__XSAVES__");
1205
32.9k
  if (HasPKU)
1206
30
    Builder.defineMacro("__PKU__");
1207
32.9k
  if (HasCLFLUSHOPT)
1208
47
    Builder.defineMacro("__CLFLUSHOPT__");
1209
32.9k
  if (HasCLWB)
1210
30
    Builder.defineMacro("__CLWB__");
1211
32.9k
  if (HasWBNOINVD)
1212
10
    Builder.defineMacro("__WBNOINVD__");
1213
32.9k
  if (HasMPX)
1214
39
    Builder.defineMacro("__MPX__");
1215
32.9k
  if (HasSHSTK)
1216
6
    Builder.defineMacro("__SHSTK__");
1217
32.9k
  if (HasSGX)
1218
19
    Builder.defineMacro("__SGX__");
1219
32.9k
  if (HasPREFETCHWT1)
1220
9
    Builder.defineMacro("__PREFETCHWT1__");
1221
32.9k
  if (HasCLZERO)
1222
10
    Builder.defineMacro("__CLZERO__");
1223
32.9k
  if (HasRDPID)
1224
15
    Builder.defineMacro("__RDPID__");
1225
32.9k
  if (HasCLDEMOTE)
1226
7
    Builder.defineMacro("__CLDEMOTE__");
1227
32.9k
  if (HasWAITPKG)
1228
4
    Builder.defineMacro("__WAITPKG__");
1229
32.9k
  if (HasMOVDIRI)
1230
7
    Builder.defineMacro("__MOVDIRI__");
1231
32.9k
  if (HasMOVDIR64B)
1232
7
    Builder.defineMacro("__MOVDIR64B__");
1233
32.9k
  if (HasPCONFIG)
1234
5
    Builder.defineMacro("__PCONFIG__");
1235
32.9k
  if (HasPTWRITE)
1236
6
    Builder.defineMacro("__PTWRITE__");
1237
32.9k
  if (HasINVPCID)
1238
719
    Builder.defineMacro("__INVPCID__");
1239
32.9k
  if (HasENQCMD)
1240
3
    Builder.defineMacro("__ENQCMD__");
1241
32.9k
1242
32.9k
  // Each case falls through to the previous one here.
1243
32.9k
  switch (SSELevel) {
1244
32.9k
  case AVX512F:
1245
104
    Builder.defineMacro("__AVX512F__");
1246
104
    LLVM_FALLTHROUGH;
1247
806
  case AVX2:
1248
806
    Builder.defineMacro("__AVX2__");
1249
806
    LLVM_FALLTHROUGH;
1250
877
  case AVX:
1251
877
    Builder.defineMacro("__AVX__");
1252
877
    LLVM_FALLTHROUGH;
1253
904
  case SSE42:
1254
904
    Builder.defineMacro("__SSE4_2__");
1255
904
    LLVM_FALLTHROUGH;
1256
9.29k
  case SSE41:
1257
9.29k
    Builder.defineMacro("__SSE4_1__");
1258
9.29k
    LLVM_FALLTHROUGH;
1259
10.6k
  case SSSE3:
1260
10.6k
    Builder.defineMacro("__SSSE3__");
1261
10.6k
    LLVM_FALLTHROUGH;
1262
11.0k
  case SSE3:
1263
11.0k
    Builder.defineMacro("__SSE3__");
1264
11.0k
    LLVM_FALLTHROUGH;
1265
29.4k
  case SSE2:
1266
29.4k
    Builder.defineMacro("__SSE2__");
1267
29.4k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1268
29.4k
    LLVM_FALLTHROUGH;
1269
29.4k
  case SSE1:
1270
29.4k
    Builder.defineMacro("__SSE__");
1271
29.4k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1272
29.4k
    LLVM_FALLTHROUGH;
1273
32.9k
  case NoSSE:
1274
32.9k
    break;
1275
32.9k
  }
1276
32.9k
1277
32.9k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x862.26k
) {
1278
294
    switch (SSELevel) {
1279
294
    case AVX512F:
1280
37
    case AVX2:
1281
37
    case AVX:
1282
37
    case SSE42:
1283
37
    case SSE41:
1284
37
    case SSSE3:
1285
37
    case SSE3:
1286
37
    case SSE2:
1287
37
      Builder.defineMacro("_M_IX86_FP", Twine(2));
1288
37
      break;
1289
37
    case SSE1:
1290
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
1291
2
      break;
1292
255
    default:
1293
255
      Builder.defineMacro("_M_IX86_FP", Twine(0));
1294
255
      break;
1295
32.9k
    }
1296
32.9k
  }
1297
32.9k
1298
32.9k
  // Each case falls through to the previous one here.
1299
32.9k
  switch (MMX3DNowLevel) {
1300
32.9k
  case AMD3DNowAthlon:
1301
33
    Builder.defineMacro("__3dNOW_A__");
1302
33
    LLVM_FALLTHROUGH;
1303
39
  case AMD3DNow:
1304
39
    Builder.defineMacro("__3dNOW__");
1305
39
    LLVM_FALLTHROUGH;
1306
29.4k
  case MMX:
1307
29.4k
    Builder.defineMacro("__MMX__");
1308
29.4k
    LLVM_FALLTHROUGH;
1309
32.9k
  case NoMMX3DNow:
1310
32.9k
    break;
1311
32.9k
  }
1312
32.9k
1313
32.9k
  if (CPU >= CK_i486 || 
CPU == CK_Generic19.6k
) {
1314
32.9k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1315
32.9k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1316
32.9k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1317
32.9k
  }
1318
32.9k
  if (HasCX8)
1319
32.9k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1320
32.9k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6410.5k
)
1321
10.4k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1322
32.9k
1323
32.9k
  if (HasFloat128)
1324
1.72k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1325
32.9k
}
1326
1327
927k
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1328
927k
  return llvm::StringSwitch<bool>(Name)
1329
927k
      .Case("3dnow", true)
1330
927k
      .Case("3dnowa", true)
1331
927k
      .Case("adx", true)
1332
927k
      .Case("aes", true)
1333
927k
      .Case("avx", true)
1334
927k
      .Case("avx2", true)
1335
927k
      .Case("avx512f", true)
1336
927k
      .Case("avx512cd", true)
1337
927k
      .Case("avx512vpopcntdq", true)
1338
927k
      .Case("avx512vnni", true)
1339
927k
      .Case("avx512bf16", true)
1340
927k
      .Case("avx512er", true)
1341
927k
      .Case("avx512pf", true)
1342
927k
      .Case("avx512dq", true)
1343
927k
      .Case("avx512bitalg", true)
1344
927k
      .Case("avx512bw", true)
1345
927k
      .Case("avx512vl", true)
1346
927k
      .Case("avx512vbmi", true)
1347
927k
      .Case("avx512vbmi2", true)
1348
927k
      .Case("avx512ifma", true)
1349
927k
      .Case("avx512vp2intersect", true)
1350
927k
      .Case("bmi", true)
1351
927k
      .Case("bmi2", true)
1352
927k
      .Case("cldemote", true)
1353
927k
      .Case("clflushopt", true)
1354
927k
      .Case("clwb", true)
1355
927k
      .Case("clzero", true)
1356
927k
      .Case("cx16", true)
1357
927k
      .Case("enqcmd", true)
1358
927k
      .Case("f16c", true)
1359
927k
      .Case("fma", true)
1360
927k
      .Case("fma4", true)
1361
927k
      .Case("fsgsbase", true)
1362
927k
      .Case("fxsr", true)
1363
927k
      .Case("gfni", true)
1364
927k
      .Case("invpcid", true)
1365
927k
      .Case("lwp", true)
1366
927k
      .Case("lzcnt", true)
1367
927k
      .Case("mmx", true)
1368
927k
      .Case("movbe", true)
1369
927k
      .Case("movdiri", true)
1370
927k
      .Case("movdir64b", true)
1371
927k
      .Case("mpx", true)
1372
927k
      .Case("mwaitx", true)
1373
927k
      .Case("pclmul", true)
1374
927k
      .Case("pconfig", true)
1375
927k
      .Case("pku", true)
1376
927k
      .Case("popcnt", true)
1377
927k
      .Case("prefetchwt1", true)
1378
927k
      .Case("prfchw", true)
1379
927k
      .Case("ptwrite", true)
1380
927k
      .Case("rdpid", true)
1381
927k
      .Case("rdrnd", true)
1382
927k
      .Case("rdseed", true)
1383
927k
      .Case("rtm", true)
1384
927k
      .Case("sahf", true)
1385
927k
      .Case("sgx", true)
1386
927k
      .Case("sha", true)
1387
927k
      .Case("shstk", true)
1388
927k
      .Case("sse", true)
1389
927k
      .Case("sse2", true)
1390
927k
      .Case("sse3", true)
1391
927k
      .Case("ssse3", true)
1392
927k
      .Case("sse4", true)
1393
927k
      .Case("sse4.1", true)
1394
927k
      .Case("sse4.2", true)
1395
927k
      .Case("sse4a", true)
1396
927k
      .Case("tbm", true)
1397
927k
      .Case("vaes", true)
1398
927k
      .Case("vpclmulqdq", true)
1399
927k
      .Case("wbnoinvd", true)
1400
927k
      .Case("waitpkg", true)
1401
927k
      .Case("x87", true)
1402
927k
      .Case("xop", true)
1403
927k
      .Case("xsave", true)
1404
927k
      .Case("xsavec", true)
1405
927k
      .Case("xsaves", true)
1406
927k
      .Case("xsaveopt", true)
1407
927k
      .Default(false);
1408
927k
}
1409
1410
164k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
1411
164k
  return llvm::StringSwitch<bool>(Feature)
1412
164k
      .Case("adx", HasADX)
1413
164k
      .Case("aes", HasAES)
1414
164k
      .Case("avx", SSELevel >= AVX)
1415
164k
      .Case("avx2", SSELevel >= AVX2)
1416
164k
      .Case("avx512f", SSELevel >= AVX512F)
1417
164k
      .Case("avx512cd", HasAVX512CD)
1418
164k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1419
164k
      .Case("avx512vnni", HasAVX512VNNI)
1420
164k
      .Case("avx512bf16", HasAVX512BF16)
1421
164k
      .Case("avx512er", HasAVX512ER)
1422
164k
      .Case("avx512pf", HasAVX512PF)
1423
164k
      .Case("avx512dq", HasAVX512DQ)
1424
164k
      .Case("avx512bitalg", HasAVX512BITALG)
1425
164k
      .Case("avx512bw", HasAVX512BW)
1426
164k
      .Case("avx512vl", HasAVX512VL)
1427
164k
      .Case("avx512vbmi", HasAVX512VBMI)
1428
164k
      .Case("avx512vbmi2", HasAVX512VBMI2)
1429
164k
      .Case("avx512ifma", HasAVX512IFMA)
1430
164k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1431
164k
      .Case("bmi", HasBMI)
1432
164k
      .Case("bmi2", HasBMI2)
1433
164k
      .Case("cldemote", HasCLDEMOTE)
1434
164k
      .Case("clflushopt", HasCLFLUSHOPT)
1435
164k
      .Case("clwb", HasCLWB)
1436
164k
      .Case("clzero", HasCLZERO)
1437
164k
      .Case("cx8", HasCX8)
1438
164k
      .Case("cx16", HasCX16)
1439
164k
      .Case("enqcmd", HasENQCMD)
1440
164k
      .Case("f16c", HasF16C)
1441
164k
      .Case("fma", HasFMA)
1442
164k
      .Case("fma4", XOPLevel >= FMA4)
1443
164k
      .Case("fsgsbase", HasFSGSBASE)
1444
164k
      .Case("fxsr", HasFXSR)
1445
164k
      .Case("gfni", HasGFNI)
1446
164k
      .Case("invpcid", HasINVPCID)
1447
164k
      .Case("lwp", HasLWP)
1448
164k
      .Case("lzcnt", HasLZCNT)
1449
164k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1450
164k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1451
164k
      .Case("mmx", MMX3DNowLevel >= MMX)
1452
164k
      .Case("movbe", HasMOVBE)
1453
164k
      .Case("movdiri", HasMOVDIRI)
1454
164k
      .Case("movdir64b", HasMOVDIR64B)
1455
164k
      .Case("mpx", HasMPX)
1456
164k
      .Case("mwaitx", HasMWAITX)
1457
164k
      .Case("pclmul", HasPCLMUL)
1458
164k
      .Case("pconfig", HasPCONFIG)
1459
164k
      .Case("pku", HasPKU)
1460
164k
      .Case("popcnt", HasPOPCNT)
1461
164k
      .Case("prefetchwt1", HasPREFETCHWT1)
1462
164k
      .Case("prfchw", HasPRFCHW)
1463
164k
      .Case("ptwrite", HasPTWRITE)
1464
164k
      .Case("rdpid", HasRDPID)
1465
164k
      .Case("rdrnd", HasRDRND)
1466
164k
      .Case("rdseed", HasRDSEED)
1467
164k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1468
164k
      .Case("rtm", HasRTM)
1469
164k
      .Case("sahf", HasLAHFSAHF)
1470
164k
      .Case("sgx", HasSGX)
1471
164k
      .Case("sha", HasSHA)
1472
164k
      .Case("shstk", HasSHSTK)
1473
164k
      .Case("sse", SSELevel >= SSE1)
1474
164k
      .Case("sse2", SSELevel >= SSE2)
1475
164k
      .Case("sse3", SSELevel >= SSE3)
1476
164k
      .Case("ssse3", SSELevel >= SSSE3)
1477
164k
      .Case("sse4.1", SSELevel >= SSE41)
1478
164k
      .Case("sse4.2", SSELevel >= SSE42)
1479
164k
      .Case("sse4a", XOPLevel >= SSE4A)
1480
164k
      .Case("tbm", HasTBM)
1481
164k
      .Case("vaes", HasVAES)
1482
164k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1483
164k
      .Case("wbnoinvd", HasWBNOINVD)
1484
164k
      .Case("waitpkg", HasWAITPKG)
1485
164k
      .Case("x86", true)
1486
164k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1487
164k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1488
164k
      .Case("xop", XOPLevel >= XOP)
1489
164k
      .Case("xsave", HasXSAVE)
1490
164k
      .Case("xsavec", HasXSAVEC)
1491
164k
      .Case("xsaves", HasXSAVES)
1492
164k
      .Case("xsaveopt", HasXSAVEOPT)
1493
164k
      .Default(false);
1494
164k
}
1495
1496
// We can't use a generic validation scheme for the features accepted here
1497
// versus subtarget features accepted in the target attribute because the
1498
// bitfield structure that's initialized in the runtime only supports the
1499
// below currently rather than the full range of subtarget features. (See
1500
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1501
709
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1502
709
  return llvm::StringSwitch<bool>(FeatureStr)
1503
25.5k
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1504
709
#include "llvm/Support/X86TargetParser.def"
1505
709
      .Default(false);
1506
709
}
1507
1508
139
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1509
139
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1510
5.00k
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1511
139
#include "llvm/Support/X86TargetParser.def"
1512
139
      ;
1513
139
  // Note, this function should only be used after ensuring the value is
1514
139
  // correct, so it asserts if the value is out of range.
1515
139
}
1516
1517
301
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1518
301
  enum class FeatPriority {
1519
301
#define FEATURE(FEAT) FEAT,
1520
301
#include "clang/Basic/X86Target.def"
1521
301
  };
1522
301
  switch (Feat) {
1523
301
#define FEATURE(FEAT)                                                          \
1524
301
  case llvm::X86::FEAT:                                                        \
1525
301
    return static_cast<unsigned>(FeatPriority::FEAT);
1526
301
#include "clang/Basic/X86Target.def"
1527
301
  default:
1528
0
    llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1529
301
  }
1530
301
}
1531
1532
301
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1533
301
  // Valid CPUs have a 'key feature' that compares just better than its key
1534
301
  // feature.
1535
301
  CPUKind Kind = getCPUKind(Name);
1536
301
  if (Kind != CK_Generic) {
1537
162
    switch (Kind) {
1538
162
    default:
1539
0
      llvm_unreachable(
1540
162
          "CPU Type without a key feature used in 'target' attribute");
1541
162
#define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT)                              \
1542
162
  case CK_##ENUM:                                                              \
1543
162
    return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1544
162
#include 
"clang/Basic/X86Target.def"0
1545
162
    }
1546
162
  }
1547
301
1548
301
  // Now we know we have a feature, so get its priority and shift it a few so
1549
301
  // that we have sufficient room for the CPUs (above).
1550
301
  
return getFeaturePriority(getFeature(Name)) << 1139
;
1551
301
}
1552
1553
162
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1554
162
  return llvm::StringSwitch<bool>(Name)
1555
4.53k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1556
972
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1557
162
#include "clang/Basic/X86Target.def"
1558
162
      .Default(false);
1559
162
}
1560
1561
350
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1562
350
  return llvm::StringSwitch<StringRef>(Name)
1563
2.10k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1564
350
#include "clang/Basic/X86Target.def"
1565
350
      .Default(Name);
1566
350
}
1567
1568
250
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1569
250
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1570
7.00k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1571
250
#include "clang/Basic/X86Target.def"
1572
250
      .Default(0);
1573
250
}
1574
1575
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1576
100
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1577
100
  StringRef WholeList =
1578
100
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1579
2.80k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1580
100
#include "clang/Basic/X86Target.def"
1581
100
          .Default("");
1582
100
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1583
100
}
1584
1585
// We can't use a generic validation scheme for the cpus accepted here
1586
// versus subtarget cpus accepted in the target attribute because the
1587
// variables intitialized by the runtime only support the below currently
1588
// rather than the full range of cpus.
1589
150
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1590
150
  return llvm::StringSwitch<bool>(FeatureStr)
1591
300
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1592
150
#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS)             \
1593
600
  .Cases(STR, ALIAS, true)
1594
1.50k
#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1595
3.15k
#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1596
150
#include "llvm/Support/X86TargetParser.def"
1597
150
      .Default(false);
1598
150
}
1599
1600
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1601
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1602
87
                .Case("@cca", 4)
1603
87
                .Case("@ccae", 5)
1604
87
                .Case("@ccb", 4)
1605
87
                .Case("@ccbe", 5)
1606
87
                .Case("@ccc", 4)
1607
87
                .Case("@cce", 4)
1608
87
                .Case("@ccz", 4)
1609
87
                .Case("@ccg", 4)
1610
87
                .Case("@ccge", 5)
1611
87
                .Case("@ccl", 4)
1612
87
                .Case("@ccle", 5)
1613
87
                .Case("@ccna", 5)
1614
87
                .Case("@ccnae", 6)
1615
87
                .Case("@ccnb", 5)
1616
87
                .Case("@ccnbe", 6)
1617
87
                .Case("@ccnc", 5)
1618
87
                .Case("@ccne", 5)
1619
87
                .Case("@ccnz", 5)
1620
87
                .Case("@ccng", 5)
1621
87
                .Case("@ccnge", 6)
1622
87
                .Case("@ccnl", 5)
1623
87
                .Case("@ccnle", 6)
1624
87
                .Case("@ccno", 5)
1625
87
                .Case("@ccnp", 5)
1626
87
                .Case("@ccns", 5)
1627
87
                .Case("@cco", 4)
1628
87
                .Case("@ccp", 4)
1629
87
                .Case("@ccs", 4)
1630
87
                .Default(0);
1631
87
  return RV;
1632
87
}
1633
1634
bool X86TargetInfo::validateAsmConstraint(
1635
7.68k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1636
7.68k
  switch (*Name) {
1637
7.68k
  default:
1638
1
    return false;
1639
7.68k
  // Constant constraints.
1640
7.68k
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1641
17
            // instructions.
1642
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1643
17
            // x86_64 instructions.
1644
17
  case 's':
1645
17
    Info.setRequiresImmediate();
1646
17
    return true;
1647
30
  case 'I':
1648
30
    Info.setRequiresImmediate(0, 31);
1649
30
    return true;
1650
17
  case 'J':
1651
16
    Info.setRequiresImmediate(0, 63);
1652
16
    return true;
1653
17
  case 'K':
1654
16
    Info.setRequiresImmediate(-128, 127);
1655
16
    return true;
1656
32
  case 'L':
1657
32
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1658
32
    return true;
1659
17
  case 'M':
1660
16
    Info.setRequiresImmediate(0, 3);
1661
16
    return true;
1662
18
  case 'N':
1663
18
    Info.setRequiresImmediate(0, 255);
1664
18
    return true;
1665
17
  case 'O':
1666
8
    Info.setRequiresImmediate(0, 127);
1667
8
    return true;
1668
17
  // Register constraints.
1669
40
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1670
40
    // Shift the pointer to the second character of the constraint.
1671
40
    Name++;
1672
40
    switch (*Name) {
1673
40
    default:
1674
0
      return false;
1675
40
    case 'z':
1676
40
    case '0': // First SSE register.
1677
40
    case '2':
1678
40
    case 't': // Any SSE register, when SSE2 is enabled.
1679
40
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1680
40
    case 'm': // Any MMX register, when inter-unit moves enabled.
1681
40
    case 'k': // AVX512 arch mask registers: k1-k7.
1682
40
      Info.setAllowsRegister();
1683
40
      return true;
1684
0
    }
1685
3
  case 'f': // Any x87 floating point stack register.
1686
3
    // Constraint 'f' cannot be used for output operands.
1687
3
    if (Info.ConstraintStr[0] == '=')
1688
1
      return false;
1689
2
    Info.setAllowsRegister();
1690
2
    return true;
1691
7.41k
  case 'a': // eax.
1692
7.41k
  case 'b': // ebx.
1693
7.41k
  case 'c': // ecx.
1694
7.41k
  case 'd': // edx.
1695
7.41k
  case 'S': // esi.
1696
7.41k
  case 'D': // edi.
1697
7.41k
  case 'A': // edx:eax.
1698
7.41k
  case 't': // Top of floating point stack.
1699
7.41k
  case 'u': // Second from top of floating point stack.
1700
7.41k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1701
7.41k
  case 'y': // Any MMX register.
1702
7.41k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1703
7.41k
  case 'x': // Any SSE register.
1704
7.41k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1705
7.41k
            // for intermideate k reg operations).
1706
7.41k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1707
7.41k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1708
7.41k
  case 'l': // "Index" registers: any general register that can be used as an
1709
7.41k
            // index in a base+index memory access.
1710
7.41k
    Info.setAllowsRegister();
1711
7.41k
    return true;
1712
7.41k
  // Floating point constant constraints.
1713
7.41k
  case 'C': // SSE floating point constant.
1714
16
  case 'G': // x87 floating point constant.
1715
16
    return true;
1716
58
  case '@':
1717
58
    // CC condition changes.
1718
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1719
58
      Name += Len - 1;
1720
58
      Info.setAllowsRegister();
1721
58
      return true;
1722
58
    }
1723
0
    return false;
1724
7.68k
  }
1725
7.68k
}
1726
1727
bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1728
8.35k
                                       unsigned Size) const {
1729
8.35k
  // Strip off constraint modifiers.
1730
16.7k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'8.76k
||
Constraint[0] == '&'8.36k
)
1731
8.36k
    Constraint = Constraint.substr(1);
1732
8.35k
1733
8.35k
  return validateOperandSize(Constraint, Size);
1734
8.35k
}
1735
1736
bool X86TargetInfo::validateInputSize(StringRef Constraint,
1737
8.83k
                                      unsigned Size) const {
1738
8.83k
  return validateOperandSize(Constraint, Size);
1739
8.83k
}
1740
1741
bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1742
15.7k
                                        unsigned Size) const {
1743
15.7k
  switch (Constraint[0]) {
1744
15.7k
  default:
1745
15.6k
    break;
1746
15.7k
  case 'k':
1747
30
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1748
30
  case 'y':
1749
30
    return Size <= 64;
1750
30
  case 'f':
1751
17
  case 't':
1752
17
  case 'u':
1753
17
    return Size <= 128;
1754
20
  case 'Y':
1755
20
    // 'Y' is the first character for several 2-character constraints.
1756
20
    switch (Constraint[1]) {
1757
20
    default:
1758
0
      return false;
1759
20
    case 'm':
1760
5
      // 'Ym' is synonymous with 'y'.
1761
5
    case 'k':
1762
5
      return Size <= 64;
1763
5
    case 'z':
1764
2
    case '0':
1765
2
      // XMM0
1766
2
      if (SSELevel >= SSE1)
1767
2
        return Size <= 128U;
1768
0
      return false;
1769
13
    case 'i':
1770
13
    case 't':
1771
13
    case '2':
1772
13
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1773
13
      if (SSELevel < SSE2)
1774
0
        return false;
1775
13
      break;
1776
13
    }
1777
13
    LLVM_FALLTHROUGH;
1778
79
  case 'v':
1779
79
  case 'x':
1780
79
    if (SSELevel >= AVX512F)
1781
47
      // 512-bit zmm registers can be used if target supports AVX512F.
1782
47
      return Size <= 512U;
1783
32
    else if (SSELevel >= AVX)
1784
9
      // 256-bit ymm registers can be used if target supports AVX.
1785
9
      return Size <= 256U;
1786
23
    return Size <= 128U;
1787
15.6k
1788
15.6k
  }
1789
15.6k
1790
15.6k
  return true;
1791
15.6k
}
1792
1793
1.50k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1794
1.50k
  switch (*Constraint) {
1795
1.50k
  case '@':
1796
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1797
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1798
29
      Constraint += Len - 1;
1799
29
      return Converted;
1800
29
    }
1801
0
    return std::string(1, *Constraint);
1802
107
  case 'a':
1803
107
    return std::string("{ax}");
1804
35
  case 'b':
1805
35
    return std::string("{bx}");
1806
103
  case 'c':
1807
103
    return std::string("{cx}");
1808
64
  case 'd':
1809
64
    return std::string("{dx}");
1810
36
  case 'S':
1811
36
    return std::string("{si}");
1812
34
  case 'D':
1813
34
    return std::string("{di}");
1814
4
  case 'p': // address
1815
4
    return std::string("im");
1816
4
  case 't': // top of floating point stack.
1817
4
    return std::string("{st}");
1818
1
  case 'u':                        // second from top of floating point stack.
1819
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1820
20
  case 'Y':
1821
20
    switch (Constraint[1]) {
1822
20
    default:
1823
0
      // Break from inner switch and fall through (copy single char),
1824
0
      // continue parsing after copying the current constraint into
1825
0
      // the return string.
1826
0
      break;
1827
20
    case 'k':
1828
20
    case 'm':
1829
20
    case 'i':
1830
20
    case 't':
1831
20
    case 'z':
1832
20
    case '0':
1833
20
    case '2':
1834
20
      // "^" hints llvm that this is a 2 letter constraint.
1835
20
      // "Constraint++" is used to promote the string iterator
1836
20
      // to the next constraint.
1837
20
      return std::string("^") + std::string(Constraint++, 2);
1838
0
    }
1839
0
    LLVM_FALLTHROUGH;
1840
1.06k
  default:
1841
1.06k
    return std::string(1, *Constraint);
1842
1.50k
  }
1843
1.50k
}
1844
1845
14.2k
bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1846
14.2k
  // Perform any per-CPU checks necessary to determine if this CPU is
1847
14.2k
  // acceptable.
1848
14.2k
  switch (Kind) {
1849
14.2k
  case CK_Generic:
1850
5
    // No processor selected!
1851
5
    return false;
1852
14.2k
#define PROC(ENUM, STRING, IS64BIT)                                            \
1853
14.2k
  case CK_##ENUM:                                                              \
1854
14.2k
    return IS64BIT || 
getTriple().getArch() == llvm::Triple::x862.72k
;
1855
14.2k
#include 
"clang/Basic/X86Target.def"15
1856
14.2k
  }
1857
14.2k
  
llvm_unreachable0
("Unhandled CPU kind");
1858
14.2k
}
1859
1860
31
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1861
31
#define PROC(ENUM, STRING, IS64BIT)                                            \
1862
1.82k
  if (IS64BIT || 
getTriple().getArch() == llvm::Triple::x86744
) \
1863
1.82k
    
Values.emplace_back(STRING)1.10k
;
1864
31
  // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
1865
31
#define PROC_ALIAS(ENUM, ALIAS)                                                \
1866
558
  if (checkCPUKind(CK_##ENUM))                                                      \
1867
558
    
Values.emplace_back(ALIAS)408
;
1868
31
#include "clang/Basic/X86Target.def"
1869
31
}
1870
1871
96.6k
X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1872
96.6k
  return llvm::StringSwitch<CPUKind>(CPU)
1873
5.70M
#define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1874
1.73M
#define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1875
96.6k
#include "clang/Basic/X86Target.def"
1876
96.6k
      .Default(CK_Generic);
1877
96.6k
}
1878
1879
107k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1880
107k
  return llvm::makeArrayRef(GCCRegNames);
1881
107k
}
1882
1883
61.8k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1884
61.8k
  return llvm::makeArrayRef(AddlRegNames);
1885
61.8k
}
1886
1887
5.94k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1888
5.94k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1889
5.94k
                                                Builtin::FirstTSBuiltin + 1);
1890
5.94k
}
1891
1892
27.1k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1893
27.1k
  return llvm::makeArrayRef(BuiltinInfoX86,
1894
27.1k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1895
27.1k
}