Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp
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1
//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// These classes wrap the information about a call or function
10
// definition used to handle ABI compliancy.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "TargetInfo.h"
15
#include "ABIInfo.h"
16
#include "CGBlocks.h"
17
#include "CGCXXABI.h"
18
#include "CGValue.h"
19
#include "CodeGenFunction.h"
20
#include "clang/AST/RecordLayout.h"
21
#include "clang/Basic/CodeGenOptions.h"
22
#include "clang/CodeGen/CGFunctionInfo.h"
23
#include "clang/CodeGen/SwiftCallingConv.h"
24
#include "llvm/ADT/StringExtras.h"
25
#include "llvm/ADT/StringSwitch.h"
26
#include "llvm/ADT/Triple.h"
27
#include "llvm/ADT/Twine.h"
28
#include "llvm/IR/DataLayout.h"
29
#include "llvm/IR/Type.h"
30
#include "llvm/Support/raw_ostream.h"
31
#include <algorithm>    // std::sort
32
33
using namespace clang;
34
using namespace CodeGen;
35
36
// Helper for coercing an aggregate argument or return value into an integer
37
// array of the same size (including padding) and alignment.  This alternate
38
// coercion happens only for the RenderScript ABI and can be removed after
39
// runtimes that rely on it are no longer supported.
40
//
41
// RenderScript assumes that the size of the argument / return value in the IR
42
// is the same as the size of the corresponding qualified type. This helper
43
// coerces the aggregate type into an array of the same size (including
44
// padding).  This coercion is used in lieu of expansion of struct members or
45
// other canonical coercions that return a coerced-type of larger size.
46
//
47
// Ty          - The argument / return value type
48
// Context     - The associated ASTContext
49
// LLVMContext - The associated LLVMContext
50
static ABIArgInfo coerceToIntArray(QualType Ty,
51
                                   ASTContext &Context,
52
19
                                   llvm::LLVMContext &LLVMContext) {
53
19
  // Alignment and Size are measured in bits.
54
19
  const uint64_t Size = Context.getTypeSize(Ty);
55
19
  const uint64_t Alignment = Context.getTypeAlign(Ty);
56
19
  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
57
19
  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
58
19
  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
59
19
}
60
61
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
62
                               llvm::Value *Array,
63
                               llvm::Value *Value,
64
                               unsigned FirstIndex,
65
10
                               unsigned LastIndex) {
66
10
  // Alternatively, we could emit this as a loop in the source.
67
215
  for (unsigned I = FirstIndex; I <= LastIndex; 
++I205
) {
68
205
    llvm::Value *Cell =
69
205
        Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
70
205
    Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
71
205
  }
72
10
}
73
74
558k
static bool isAggregateTypeForABI(QualType T) {
75
558k
  return !CodeGenFunction::hasScalarEvaluationKind(T) ||
76
558k
         
T->isMemberFunctionPointerType()544k
;
77
558k
}
78
79
ABIArgInfo
80
ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
81
3.64k
                                 llvm::Type *Padding) const {
82
3.64k
  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
83
3.64k
                                 ByRef, Realign, Padding);
84
3.64k
}
85
86
ABIArgInfo
87
21
ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
88
21
  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
89
21
                                      /*ByRef*/ false, Realign);
90
21
}
91
92
Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
93
0
                             QualType Ty) const {
94
0
  return Address::invalid();
95
0
}
96
97
17.8k
ABIInfo::~ABIInfo() {}
98
99
/// Does the given lowering require more than the given number of
100
/// registers when expanded?
101
///
102
/// This is intended to be the basis of a reasonable basic implementation
103
/// of should{Pass,Return}IndirectlyForSwift.
104
///
105
/// For most targets, a limit of four total registers is reasonable; this
106
/// limits the amount of code required in order to move around the value
107
/// in case it wasn't produced immediately prior to the call by the caller
108
/// (or wasn't produced in exactly the right registers) or isn't used
109
/// immediately within the callee.  But some targets may need to further
110
/// limit the register count due to an inability to support that many
111
/// return registers.
112
static bool occupiesMoreThan(CodeGenTypes &cgt,
113
                             ArrayRef<llvm::Type*> scalarTypes,
114
1.04k
                             unsigned maxAllRegisters) {
115
1.04k
  unsigned intCount = 0, fpCount = 0;
116
4.17k
  for (llvm::Type *type : scalarTypes) {
117
4.17k
    if (type->isPointerTy()) {
118
0
      intCount++;
119
4.17k
    } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
120
2.28k
      auto ptrWidth = cgt.getTarget().getPointerWidth(0);
121
2.28k
      intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
122
2.28k
    } else {
123
1.88k
      assert(type->isVectorTy() || type->isFloatingPointTy());
124
1.88k
      fpCount++;
125
1.88k
    }
126
4.17k
  }
127
1.04k
128
1.04k
  return (intCount + fpCount > maxAllRegisters);
129
1.04k
}
130
131
bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
132
                                             llvm::Type *eltTy,
133
440
                                             unsigned numElts) const {
134
440
  // The default implementation of this assumes that the target guarantees
135
440
  // 128-bit SIMD support but nothing more.
136
440
  return (vectorSize.getQuantity() > 8 && 
vectorSize.getQuantity() <= 16432
);
137
440
}
138
139
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
140
16.9k
                                              CGCXXABI &CXXABI) {
141
16.9k
  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
142
16.9k
  if (!RD) {
143
3.50k
    if (!RT->getDecl()->canPassInRegisters())
144
8
      return CGCXXABI::RAA_Indirect;
145
3.49k
    return CGCXXABI::RAA_Default;
146
3.49k
  }
147
13.4k
  return CXXABI.getRecordArgABI(RD);
148
13.4k
}
149
150
static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
151
14.8k
                                              CGCXXABI &CXXABI) {
152
14.8k
  const RecordType *RT = T->getAs<RecordType>();
153
14.8k
  if (!RT)
154
5.03k
    return CGCXXABI::RAA_Default;
155
9.77k
  return getRecordArgABI(RT, CXXABI);
156
9.77k
}
157
158
static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
159
279k
                               const ABIInfo &Info) {
160
279k
  QualType Ty = FI.getReturnType();
161
279k
162
279k
  if (const auto *RT = Ty->getAs<RecordType>())
163
8.39k
    if (!isa<CXXRecordDecl>(RT->getDecl()) &&
164
8.39k
        
!RT->getDecl()->canPassInRegisters()1.13k
) {
165
12
      FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
166
12
      return true;
167
12
    }
168
279k
169
279k
  return CXXABI.classifyReturnType(FI);
170
279k
}
171
172
/// Pass transparent unions as if they were the type of the first element. Sema
173
/// should ensure that all elements of the union have the same "machine type".
174
570k
static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
175
570k
  if (const RecordType *UT = Ty->getAsUnionType()) {
176
147
    const RecordDecl *UD = UT->getDecl();
177
147
    if (UD->hasAttr<TransparentUnionAttr>()) {
178
23
      assert(!UD->field_empty() && "sema created an empty transparent union");
179
23
      return UD->field_begin()->getType();
180
23
    }
181
570k
  }
182
570k
  return Ty;
183
570k
}
184
185
320k
CGCXXABI &ABIInfo::getCXXABI() const {
186
320k
  return CGT.getCXXABI();
187
320k
}
188
189
350k
ASTContext &ABIInfo::getContext() const {
190
350k
  return CGT.getContext();
191
350k
}
192
193
24.0k
llvm::LLVMContext &ABIInfo::getVMContext() const {
194
24.0k
  return CGT.getLLVMContext();
195
24.0k
}
196
197
14.0k
const llvm::DataLayout &ABIInfo::getDataLayout() const {
198
14.0k
  return CGT.getDataLayout();
199
14.0k
}
200
201
15.6k
const TargetInfo &ABIInfo::getTarget() const {
202
15.6k
  return CGT.getTarget();
203
15.6k
}
204
205
0
const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
206
0
  return CGT.getCodeGenOpts();
207
0
}
208
209
1.09k
bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
210
211
0
bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
212
0
  return false;
213
0
}
214
215
bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
216
0
                                                uint64_t Members) const {
217
0
  return false;
218
0
}
219
220
0
LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
221
0
  raw_ostream &OS = llvm::errs();
222
0
  OS << "(ABIArgInfo Kind=";
223
0
  switch (TheKind) {
224
0
  case Direct:
225
0
    OS << "Direct Type=";
226
0
    if (llvm::Type *Ty = getCoerceToType())
227
0
      Ty->print(OS);
228
0
    else
229
0
      OS << "null";
230
0
    break;
231
0
  case Extend:
232
0
    OS << "Extend";
233
0
    break;
234
0
  case Ignore:
235
0
    OS << "Ignore";
236
0
    break;
237
0
  case InAlloca:
238
0
    OS << "InAlloca Offset=" << getInAllocaFieldIndex();
239
0
    break;
240
0
  case Indirect:
241
0
    OS << "Indirect Align=" << getIndirectAlign().getQuantity()
242
0
       << " ByVal=" << getIndirectByVal()
243
0
       << " Realign=" << getIndirectRealign();
244
0
    break;
245
0
  case Expand:
246
0
    OS << "Expand";
247
0
    break;
248
0
  case CoerceAndExpand:
249
0
    OS << "CoerceAndExpand Type=";
250
0
    getCoerceAndExpandType()->print(OS);
251
0
    break;
252
0
  }
253
0
  OS << ")\n";
254
0
}
255
256
// Dynamically round a pointer up to a multiple of the given alignment.
257
static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
258
                                                  llvm::Value *Ptr,
259
119
                                                  CharUnits Align) {
260
119
  llvm::Value *PtrAsInt = Ptr;
261
119
  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
262
119
  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
263
119
  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
264
119
        llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
265
119
  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
266
119
           llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
267
119
  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
268
119
                                        Ptr->getType(),
269
119
                                        Ptr->getName() + ".aligned");
270
119
  return PtrAsInt;
271
119
}
272
273
/// Emit va_arg for a platform using the common void* representation,
274
/// where arguments are simply emitted in an array of slots on the stack.
275
///
276
/// This version implements the core direct-value passing rules.
277
///
278
/// \param SlotSize - The size and alignment of a stack slot.
279
///   Each argument will be allocated to a multiple of this number of
280
///   slots, and all the slots will be aligned to this value.
281
/// \param AllowHigherAlign - The slot alignment is not a cap;
282
///   an argument type with an alignment greater than the slot size
283
///   will be emitted on a higher-alignment address, potentially
284
///   leaving one or more empty slots behind as padding.  If this
285
///   is false, the returned address might be less-aligned than
286
///   DirectAlign.
287
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
288
                                      Address VAListAddr,
289
                                      llvm::Type *DirectTy,
290
                                      CharUnits DirectSize,
291
                                      CharUnits DirectAlign,
292
                                      CharUnits SlotSize,
293
412
                                      bool AllowHigherAlign) {
294
412
  // Cast the element type to i8* if necessary.  Some platforms define
295
412
  // va_list as a struct containing an i8* instead of just an i8*.
296
412
  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
297
54
    VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
298
412
299
412
  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
300
412
301
412
  // If the CC aligns values higher than the slot size, do so if needed.
302
412
  Address Addr = Address::invalid();
303
412
  if (AllowHigherAlign && 
DirectAlign > SlotSize391
) {
304
82
    Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
305
82
                                                 DirectAlign);
306
330
  } else {
307
330
    Addr = Address(Ptr, SlotSize);
308
330
  }
309
412
310
412
  // Advance the pointer past the argument, then store that back.
311
412
  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
312
412
  Address NextPtr =
313
412
      CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
314
412
  CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
315
412
316
412
  // If the argument is smaller than a slot, and this is a big-endian
317
412
  // target, the argument will be right-adjusted in its slot.
318
412
  if (DirectSize < SlotSize && 
CGF.CGM.getDataLayout().isBigEndian()30
&&
319
412
      
!DirectTy->isStructTy()6
) {
320
0
    Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
321
0
  }
322
412
323
412
  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
324
412
  return Addr;
325
412
}
326
327
/// Emit va_arg for a platform using the common void* representation,
328
/// where arguments are simply emitted in an array of slots on the stack.
329
///
330
/// \param IsIndirect - Values of this type are passed indirectly.
331
/// \param ValueInfo - The size and alignment of this type, generally
332
///   computed with getContext().getTypeInfoInChars(ValueTy).
333
/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
334
///   Each argument will be allocated to a multiple of this number of
335
///   slots, and all the slots will be aligned to this value.
336
/// \param AllowHigherAlign - The slot alignment is not a cap;
337
///   an argument type with an alignment greater than the slot size
338
///   will be emitted on a higher-alignment address, potentially
339
///   leaving one or more empty slots behind as padding.
340
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
341
                                QualType ValueTy, bool IsIndirect,
342
                                std::pair<CharUnits, CharUnits> ValueInfo,
343
                                CharUnits SlotSizeAndAlign,
344
404
                                bool AllowHigherAlign) {
345
404
  // The size and alignment of the value that was passed directly.
346
404
  CharUnits DirectSize, DirectAlign;
347
404
  if (IsIndirect) {
348
30
    DirectSize = CGF.getPointerSize();
349
30
    DirectAlign = CGF.getPointerAlign();
350
374
  } else {
351
374
    DirectSize = ValueInfo.first;
352
374
    DirectAlign = ValueInfo.second;
353
374
  }
354
404
355
404
  // Cast the address we've calculated to the right type.
356
404
  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
357
404
  if (IsIndirect)
358
30
    DirectTy = DirectTy->getPointerTo(0);
359
404
360
404
  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
361
404
                                        DirectSize, DirectAlign,
362
404
                                        SlotSizeAndAlign,
363
404
                                        AllowHigherAlign);
364
404
365
404
  if (IsIndirect) {
366
30
    Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
367
30
  }
368
404
369
404
  return Addr;
370
404
371
404
}
372
373
static Address emitMergePHI(CodeGenFunction &CGF,
374
                            Address Addr1, llvm::BasicBlock *Block1,
375
                            Address Addr2, llvm::BasicBlock *Block2,
376
445
                            const llvm::Twine &Name = "") {
377
445
  assert(Addr1.getType() == Addr2.getType());
378
445
  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
379
445
  PHI->addIncoming(Addr1.getPointer(), Block1);
380
445
  PHI->addIncoming(Addr2.getPointer(), Block2);
381
445
  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
382
445
  return Address(PHI, Align);
383
445
}
384
385
17.6k
TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
386
387
// If someone can figure out a general rule for this, that would be great.
388
// It's probably just doomed to be platform-dependent, though.
389
5
unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
390
5
  // Verified for:
391
5
  //   x86-64     FreeBSD, Linux, Darwin
392
5
  //   x86-32     FreeBSD, Linux, Darwin
393
5
  //   PowerPC    Linux, Darwin
394
5
  //   ARM        Darwin (*not* EABI)
395
5
  //   AArch64    Linux
396
5
  return 32;
397
5
}
398
399
bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
400
9.00k
                                     const FunctionNoProtoType *fnType) const {
401
9.00k
  // The following conventions are known to require this to be false:
402
9.00k
  //   x86_stdcall
403
9.00k
  //   MIPS
404
9.00k
  // For everything else, we just prefer false unless we opt out.
405
9.00k
  return false;
406
9.00k
}
407
408
void
409
TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
410
2
                                             llvm::SmallString<24> &Opt) const {
411
2
  // This assumes the user is passing a library name like "rt" instead of a
412
2
  // filename like "librt.a/so", and that they don't care whether it's static or
413
2
  // dynamic.
414
2
  Opt = "-l";
415
2
  Opt += Lib;
416
2
}
417
418
39
unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
419
39
  // OpenCL kernels are called via an explicit runtime API with arguments
420
39
  // set with clSetKernelArg(), not as normal sub-functions.
421
39
  // Return SPIR_KERNEL by default as the kernel calling convention to
422
39
  // ensure the fingerprint is fixed such way that each OpenCL argument
423
39
  // gets one matching argument in the produced kernel function argument
424
39
  // list to enable feasible implementation of clSetKernelArg() with
425
39
  // aggregates etc. In case we would use the default C calling conv here,
426
39
  // clSetKernelArg() might break depending on the target-specific
427
39
  // conventions; different targets might split structs passed as values
428
39
  // to multiple function arguments etc.
429
39
  return llvm::CallingConv::SPIR_KERNEL;
430
39
}
431
432
llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
433
87.5k
    llvm::PointerType *T, QualType QT) const {
434
87.5k
  return llvm::ConstantPointerNull::get(T);
435
87.5k
}
436
437
LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
438
113k
                                                   const VarDecl *D) const {
439
113k
  assert(!CGM.getLangOpts().OpenCL &&
440
113k
         !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
441
113k
         "Address space agnostic languages only");
442
113k
  return D ? 
D->getType().getAddressSpace()110k
:
LangAS::Default2.23k
;
443
113k
}
444
445
llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
446
    CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
447
5.91k
    LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
448
5.91k
  // Since target may map different address spaces in AST to the same address
449
5.91k
  // space, an address space conversion may end up as a bitcast.
450
5.91k
  if (auto *C = dyn_cast<llvm::Constant>(Src))
451
49
    return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
452
5.87k
  // Try to preserve the source's name to make IR more readable.
453
5.87k
  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
454
5.87k
      Src, DestTy, Src->hasName() ? 
Src->getName() + ".ascast"3.23k
:
""2.63k
);
455
5.87k
}
456
457
llvm::Constant *
458
TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
459
                                        LangAS SrcAddr, LangAS DestAddr,
460
244
                                        llvm::Type *DestTy) const {
461
244
  // Since target may map different address spaces in AST to the same address
462
244
  // space, an address space conversion may end up as a bitcast.
463
244
  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
464
244
}
465
466
llvm::SyncScope::ID
467
TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
468
                                      SyncScope Scope,
469
                                      llvm::AtomicOrdering Ordering,
470
0
                                      llvm::LLVMContext &Ctx) const {
471
0
  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
472
0
}
473
474
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
475
476
/// isEmptyField - Return true iff a the field is "empty", that is it
477
/// is an unnamed bit-field or an (array of) empty record(s).
478
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
479
14.3k
                         bool AllowArrays) {
480
14.3k
  if (FD->isUnnamedBitfield())
481
87
    return true;
482
14.2k
483
14.2k
  QualType FT = FD->getType();
484
14.2k
485
14.2k
  // Constant arrays of empty records count as empty, strip them off.
486
14.2k
  // Constant arrays of zero length always count as empty.
487
14.2k
  if (AllowArrays)
488
16.5k
    
while (const ConstantArrayType *13.9k
AT = Context.getAsConstantArrayType(FT)) {
489
2.59k
      if (AT->getSize() == 0)
490
11
        return true;
491
2.58k
      FT = AT->getElementType();
492
2.58k
    }
493
14.2k
494
14.2k
  const RecordType *RT = FT->getAs<RecordType>();
495
14.2k
  if (!RT)
496
10.5k
    return false;
497
3.68k
498
3.68k
  // C++ record fields are never empty, at least in the Itanium ABI.
499
3.68k
  //
500
3.68k
  // FIXME: We should use a predicate for whether this behavior is true in the
501
3.68k
  // current ABI.
502
3.68k
  if (isa<CXXRecordDecl>(RT->getDecl()))
503
3.34k
    return false;
504
342
505
342
  return isEmptyRecord(Context, FT, AllowArrays);
506
342
}
507
508
/// isEmptyRecord - Return true iff a structure contains only empty
509
/// fields. Note that a structure with a flexible array member is not
510
/// considered empty.
511
33.3k
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
512
33.3k
  const RecordType *RT = T->getAs<RecordType>();
513
33.3k
  if (!RT)
514
9.82k
    return false;
515
23.4k
  const RecordDecl *RD = RT->getDecl();
516
23.4k
  if (RD->hasFlexibleArrayMember())
517
4
    return false;
518
23.4k
519
23.4k
  // If this is a C++ record, check the bases first.
520
23.4k
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
521
19.7k
    for (const auto &I : CXXRD->bases())
522
5.52k
      if (!isEmptyRecord(Context, I.getType(), true))
523
1.50k
        return false;
524
23.4k
525
23.4k
  
for (const auto *I : RD->fields())21.9k
526
12.9k
    if (!isEmptyField(Context, I, AllowArrays))
527
12.7k
      return false;
528
21.9k
  
return true9.25k
;
529
21.9k
}
530
531
/// isSingleElementStruct - Determine if a structure is a "single
532
/// element struct", i.e. it has exactly one non-empty field or
533
/// exactly one field which is itself a single element
534
/// struct. Structures with flexible array members are never
535
/// considered single element structs.
536
///
537
/// \return The field declaration for the single non-empty field, if
538
/// it exists.
539
68.4k
static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
540
68.4k
  const RecordType *RT = T->getAs<RecordType>();
541
68.4k
  if (!RT)
542
67.6k
    return nullptr;
543
870
544
870
  const RecordDecl *RD = RT->getDecl();
545
870
  if (RD->hasFlexibleArrayMember())
546
4
    return nullptr;
547
866
548
866
  const Type *Found = nullptr;
549
866
550
866
  // If this is a C++ record, check the bases first.
551
866
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
552
310
    for (const auto &I : CXXRD->bases()) {
553
39
      // Ignore empty records.
554
39
      if (isEmptyRecord(Context, I.getType(), true))
555
4
        continue;
556
35
557
35
      // If we already found an element then this isn't a single-element struct.
558
35
      if (Found)
559
11
        return nullptr;
560
24
561
24
      // If this is non-empty and not a single element struct, the composite
562
24
      // cannot be a single element struct.
563
24
      Found = isSingleElementStruct(I.getType(), Context);
564
24
      if (!Found)
565
1
        return nullptr;
566
24
    }
567
310
  }
568
866
569
866
  // Check for single element.
570
1.22k
  
for (const auto *FD : RD->fields())854
{
571
1.22k
    QualType FT = FD->getType();
572
1.22k
573
1.22k
    // Ignore empty fields.
574
1.22k
    if (isEmptyField(Context, FD, true))
575
15
      continue;
576
1.20k
577
1.20k
    // If we already found an element then this isn't a single-element
578
1.20k
    // struct.
579
1.20k
    if (Found)
580
380
      return nullptr;
581
827
582
827
    // Treat single element arrays as the element.
583
841
    
while (const ConstantArrayType *827
AT = Context.getAsConstantArrayType(FT)) {
584
178
      if (AT->getSize().getZExtValue() != 1)
585
164
        break;
586
14
      FT = AT->getElementType();
587
14
    }
588
827
589
827
    if (!isAggregateTypeForABI(FT)) {
590
636
      Found = FT.getTypePtr();
591
636
    } else {
592
191
      Found = isSingleElementStruct(FT, Context);
593
191
      if (!Found)
594
181
        return nullptr;
595
191
    }
596
827
  }
597
854
598
854
  // We don't consider a struct a single-element struct if it has
599
854
  // padding beyond the element type.
600
854
  
if (293
Found293
&&
Context.getTypeSize(Found) != Context.getTypeSize(T)278
)
601
3
    return nullptr;
602
290
603
290
  return Found;
604
290
}
605
606
namespace {
607
Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
608
148
                       const ABIArgInfo &AI) {
609
148
  // This default implementation defers to the llvm backend's va_arg
610
148
  // instruction. It can handle only passing arguments directly
611
148
  // (typically only handled in the backend for primitive types), or
612
148
  // aggregates passed indirectly by pointer (NOTE: if the "byval"
613
148
  // flag has ABI impact in the callee, this implementation cannot
614
148
  // work.)
615
148
616
148
  // Only a few cases are covered here at the moment -- those needed
617
148
  // by the default abi.
618
148
  llvm::Value *Val;
619
148
620
148
  if (AI.isIndirect()) {
621
1
    assert(!AI.getPaddingType() &&
622
1
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
623
1
    assert(
624
1
        !AI.getIndirectRealign() &&
625
1
        "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
626
1
627
1
    auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
628
1
    CharUnits TyAlignForABI = TyInfo.second;
629
1
630
1
    llvm::Type *BaseTy =
631
1
        llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
632
1
    llvm::Value *Addr =
633
1
        CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
634
1
    return Address(Addr, TyAlignForABI);
635
147
  } else {
636
147
    assert((AI.isDirect() || AI.isExtend()) &&
637
147
           "Unexpected ArgInfo Kind in generic VAArg emitter!");
638
147
639
147
    assert(!AI.getInReg() &&
640
147
           "Unexpected InReg seen in arginfo in generic VAArg emitter!");
641
147
    assert(!AI.getPaddingType() &&
642
147
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
643
147
    assert(!AI.getDirectOffset() &&
644
147
           "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
645
147
    assert(!AI.getCoerceToType() &&
646
147
           "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
647
147
648
147
    Address Temp = CGF.CreateMemTemp(Ty, "varet");
649
147
    Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
650
147
    CGF.Builder.CreateStore(Val, Temp);
651
147
    return Temp;
652
147
  }
653
148
}
654
655
/// DefaultABIInfo - The default implementation for ABI specific
656
/// details. This implementation provides information which results in
657
/// self-consistent and sensible LLVM IR generation, but does not
658
/// conform to any particular ABI.
659
class DefaultABIInfo : public ABIInfo {
660
public:
661
511
  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
662
663
  ABIArgInfo classifyReturnType(QualType RetTy) const;
664
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
665
666
810
  void computeInfo(CGFunctionInfo &FI) const override {
667
810
    if (!getCXXABI().classifyReturnType(FI))
668
809
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
669
810
    for (auto &I : FI.arguments())
670
1.35k
      I.info = classifyArgumentType(I.type);
671
810
  }
672
673
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
674
3
                    QualType Ty) const override {
675
3
    return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
676
3
  }
677
};
678
679
class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
680
public:
681
  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
682
9
    : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
683
};
684
685
2.45k
ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
686
2.45k
  Ty = useFirstFieldIfTransparentUnion(Ty);
687
2.45k
688
2.45k
  if (isAggregateTypeForABI(Ty)) {
689
103
    // Records with non-trivial destructors/copy-constructors should not be
690
103
    // passed by value.
691
103
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
692
2
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
693
101
694
101
    return getNaturalAlignIndirect(Ty);
695
101
  }
696
2.35k
697
2.35k
  // Treat an enum type as its underlying type.
698
2.35k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
699
7
    Ty = EnumTy->getDecl()->getIntegerType();
700
2.35k
701
2.35k
  return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)84
702
2.35k
                                        : 
ABIArgInfo::getDirect()2.27k
);
703
2.35k
}
704
705
1.78k
ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
706
1.78k
  if (RetTy->isVoidType())
707
1.00k
    return ABIArgInfo::getIgnore();
708
788
709
788
  if (isAggregateTypeForABI(RetTy))
710
44
    return getNaturalAlignIndirect(RetTy);
711
744
712
744
  // Treat an enum type as its underlying type.
713
744
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
714
0
    RetTy = EnumTy->getDecl()->getIntegerType();
715
744
716
744
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)68
717
744
                                           : 
ABIArgInfo::getDirect()676
);
718
744
}
719
720
//===----------------------------------------------------------------------===//
721
// WebAssembly ABI Implementation
722
//
723
// This is a very simple ABI that relies a lot on DefaultABIInfo.
724
//===----------------------------------------------------------------------===//
725
726
class WebAssemblyABIInfo final : public SwiftABIInfo {
727
  DefaultABIInfo defaultInfo;
728
729
public:
730
  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
731
29
      : SwiftABIInfo(CGT), defaultInfo(CGT) {}
732
733
private:
734
  ABIArgInfo classifyReturnType(QualType RetTy) const;
735
  ABIArgInfo classifyArgumentType(QualType Ty) const;
736
737
  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
738
  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
739
  // overload them.
740
279
  void computeInfo(CGFunctionInfo &FI) const override {
741
279
    if (!getCXXABI().classifyReturnType(FI))
742
271
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
743
279
    for (auto &Arg : FI.arguments())
744
253
      Arg.info = classifyArgumentType(Arg.type);
745
279
  }
746
747
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
748
                    QualType Ty) const override;
749
750
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
751
0
                                    bool asReturnValue) const override {
752
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
753
0
  }
754
755
0
  bool isSwiftErrorInRegister() const override {
756
0
    return false;
757
0
  }
758
};
759
760
class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
761
public:
762
  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
763
29
      : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
764
765
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
766
917
                           CodeGen::CodeGenModule &CGM) const override {
767
917
    TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
768
917
    if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
769
768
      if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
770
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
771
1
        llvm::AttrBuilder B;
772
1
        B.addAttribute("wasm-import-module", Attr->getImportModule());
773
1
        Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
774
1
      }
775
768
      if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
776
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
777
1
        llvm::AttrBuilder B;
778
1
        B.addAttribute("wasm-import-name", Attr->getImportName());
779
1
        Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
780
1
      }
781
768
    }
782
917
783
917
    if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
784
768
      llvm::Function *Fn = cast<llvm::Function>(GV);
785
768
      if (!FD->doesThisDeclarationHaveABody() && 
!FD->hasPrototype()64
)
786
1
        Fn->addFnAttr("no-prototype");
787
768
    }
788
917
  }
789
};
790
791
/// Classify argument of given type \p Ty.
792
253
ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
793
253
  Ty = useFirstFieldIfTransparentUnion(Ty);
794
253
795
253
  if (isAggregateTypeForABI(Ty)) {
796
36
    // Records with non-trivial destructors/copy-constructors should not be
797
36
    // passed by value.
798
36
    if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
799
8
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
800
28
    // Ignore empty structs/unions.
801
28
    if (isEmptyRecord(getContext(), Ty, true))
802
4
      return ABIArgInfo::getIgnore();
803
24
    // Lower single-element structs to just pass a regular value. TODO: We
804
24
    // could do reasonable-size multiple-element structs too, using getExpand(),
805
24
    // though watch out for things like bitfields.
806
24
    if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
807
8
      return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
808
233
  }
809
233
810
233
  // Otherwise just do the default thing.
811
233
  return defaultInfo.classifyArgumentType(Ty);
812
233
}
813
814
271
ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
815
271
  if (isAggregateTypeForABI(RetTy)) {
816
22
    // Records with non-trivial destructors/copy-constructors should not be
817
22
    // returned by value.
818
22
    if (!getRecordArgABI(RetTy, getCXXABI())) {
819
22
      // Ignore empty structs/unions.
820
22
      if (isEmptyRecord(getContext(), RetTy, true))
821
4
        return ABIArgInfo::getIgnore();
822
18
      // Lower single-element structs to just return a regular value. TODO: We
823
18
      // could do reasonable-size multiple-element structs too, using
824
18
      // ABIArgInfo::getDirect().
825
18
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
826
10
        return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
827
257
    }
828
22
  }
829
257
830
257
  // Otherwise just do the default thing.
831
257
  return defaultInfo.classifyReturnType(RetTy);
832
257
}
833
834
Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
835
3
                                      QualType Ty) const {
836
3
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*IsIndirect=*/ false,
837
3
                          getContext().getTypeInfoInChars(Ty),
838
3
                          CharUnits::fromQuantity(4),
839
3
                          /*AllowHigherAlign=*/ true);
840
3
}
841
842
//===----------------------------------------------------------------------===//
843
// le32/PNaCl bitcode ABI Implementation
844
//
845
// This is a simplified version of the x86_32 ABI.  Arguments and return values
846
// are always passed on the stack.
847
//===----------------------------------------------------------------------===//
848
849
class PNaClABIInfo : public ABIInfo {
850
 public:
851
16
  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
852
853
  ABIArgInfo classifyReturnType(QualType RetTy) const;
854
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
855
856
  void computeInfo(CGFunctionInfo &FI) const override;
857
  Address EmitVAArg(CodeGenFunction &CGF,
858
                    Address VAListAddr, QualType Ty) const override;
859
};
860
861
class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
862
 public:
863
  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
864
16
    : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
865
};
866
867
91
void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
868
91
  if (!getCXXABI().classifyReturnType(FI))
869
91
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
870
91
871
91
  for (auto &I : FI.arguments())
872
62
    I.info = classifyArgumentType(I.type);
873
91
}
874
875
Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
876
3
                                QualType Ty) const {
877
3
  // The PNaCL ABI is a bit odd, in that varargs don't use normal
878
3
  // function classification. Structs get passed directly for varargs
879
3
  // functions, through a rewriting transform in
880
3
  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
881
3
  // this target to actually support a va_arg instructions with an
882
3
  // aggregate type, unlike other targets.
883
3
  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
884
3
}
885
886
/// Classify argument of given type \p Ty.
887
62
ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
888
62
  if (isAggregateTypeForABI(Ty)) {
889
9
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
890
0
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
891
9
    return getNaturalAlignIndirect(Ty);
892
53
  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
893
1
    // Treat an enum type as its underlying type.
894
1
    Ty = EnumTy->getDecl()->getIntegerType();
895
52
  } else if (Ty->isFloatingType()) {
896
19
    // Floating-point types don't go inreg.
897
19
    return ABIArgInfo::getDirect();
898
19
  }
899
34
900
34
  return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)5
901
34
                                        : 
ABIArgInfo::getDirect()29
);
902
34
}
903
904
91
ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
905
91
  if (RetTy->isVoidType())
906
35
    return ABIArgInfo::getIgnore();
907
56
908
56
  // In the PNaCl ABI we always return records/structures on the stack.
909
56
  if (isAggregateTypeForABI(RetTy))
910
2
    return getNaturalAlignIndirect(RetTy);
911
54
912
54
  // Treat an enum type as its underlying type.
913
54
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
914
0
    RetTy = EnumTy->getDecl()->getIntegerType();
915
54
916
54
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)18
917
54
                                           : 
ABIArgInfo::getDirect()36
);
918
54
}
919
920
/// IsX86_MMXType - Return true if this is an MMX type.
921
61
bool IsX86_MMXType(llvm::Type *IRType) {
922
61
  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
923
61
  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
924
61
    
cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy()19
&&
925
61
    
IRType->getScalarSizeInBits() != 6417
;
926
61
}
927
928
static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
929
                                          StringRef Constraint,
930
1.06k
                                          llvm::Type* Ty) {
931
1.06k
  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
932
1.06k
                     .Cases("y", "&y", "^Ym", true)
933
1.06k
                     .Default(false);
934
1.06k
  if (IsMMXCons && 
Ty->isVectorTy()18
) {
935
14
    if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
936
0
      // Invalid MMX constraint
937
0
      return nullptr;
938
0
    }
939
14
940
14
    return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
941
14
  }
942
1.04k
943
1.04k
  // No operation needed
944
1.04k
  return Ty;
945
1.04k
}
946
947
/// Returns true if this type can be passed in SSE registers with the
948
/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
949
760
static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
950
760
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
951
463
    if (BT->isFloatingPoint() && 
BT->getKind() != BuiltinType::Half275
) {
952
275
      if (BT->getKind() == BuiltinType::LongDouble) {
953
6
        if (&Context.getTargetInfo().getLongDoubleFormat() ==
954
6
            &llvm::APFloat::x87DoubleExtended())
955
2
          return false;
956
273
      }
957
273
      return true;
958
273
    }
959
297
  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
960
264
    // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
961
264
    // registers specially.
962
264
    unsigned VecSize = Context.getTypeSize(VT);
963
264
    if (VecSize == 128 || 
VecSize == 2560
||
VecSize == 5120
)
964
264
      return true;
965
221
  }
966
221
  return false;
967
221
}
968
969
/// Returns true if this aggregate is small enough to be passed in SSE registers
970
/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
971
725
static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
972
725
  return NumMembers <= 4;
973
725
}
974
975
/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
976
30
static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
977
30
  auto AI = ABIArgInfo::getDirect(T);
978
30
  AI.setInReg(true);
979
30
  AI.setCanBeFlattened(false);
980
30
  return AI;
981
30
}
982
983
//===----------------------------------------------------------------------===//
984
// X86-32 ABI Implementation
985
//===----------------------------------------------------------------------===//
986
987
/// Similar to llvm::CCState, but for Clang.
988
struct CCState {
989
22.6k
  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
990
991
  unsigned CC;
992
  unsigned FreeRegs;
993
  unsigned FreeSSERegs;
994
};
995
996
enum {
997
  // Vectorcall only allows the first 6 parameters to be passed in registers.
998
  VectorcallMaxParamNumAsReg = 6
999
};
1000
1001
/// X86_32ABIInfo - The X86-32 ABI information.
1002
class X86_32ABIInfo : public SwiftABIInfo {
1003
  enum Class {
1004
    Integer,
1005
    Float
1006
  };
1007
1008
  static const unsigned MinABIStackAlignInBytes = 4;
1009
1010
  bool IsDarwinVectorABI;
1011
  bool IsRetSmallStructInRegABI;
1012
  bool IsWin32StructABI;
1013
  bool IsSoftFloatABI;
1014
  bool IsMCUABI;
1015
  unsigned DefaultNumRegisterParameters;
1016
1017
582
  static bool isRegisterSize(unsigned Size) {
1018
582
    return (Size == 8 || 
Size == 16551
||
Size == 32532
||
Size == 64250
);
1019
582
  }
1020
1021
391
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1022
391
    // FIXME: Assumes vectorcall is in use.
1023
391
    return isX86VectorTypeForVectorCall(getContext(), Ty);
1024
391
  }
1025
1026
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1027
319
                                         uint64_t NumMembers) const override {
1028
319
    // FIXME: Assumes vectorcall is in use.
1029
319
    return isX86VectorCallAggregateSmallEnough(NumMembers);
1030
319
  }
1031
1032
  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1033
1034
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1035
  /// such that the argument will be passed in memory.
1036
  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1037
1038
  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1039
1040
  /// Return the alignment to use for the given type on the stack.
1041
  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1042
1043
  Class classify(QualType Ty) const;
1044
  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1045
  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1046
1047
  /// Updates the number of available free registers, returns
1048
  /// true if any registers were allocated.
1049
  bool updateFreeRegs(QualType Ty, CCState &State) const;
1050
1051
  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1052
                                bool &NeedsPadding) const;
1053
  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1054
1055
  bool canExpandIndirectArgument(QualType Ty) const;
1056
1057
  /// Rewrite the function info so that all memory arguments use
1058
  /// inalloca.
1059
  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1060
1061
  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1062
                           CharUnits &StackOffset, ABIArgInfo &Info,
1063
                           QualType Type) const;
1064
  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1065
                             bool &UsedInAlloca) const;
1066
1067
public:
1068
1069
  void computeInfo(CGFunctionInfo &FI) const override;
1070
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1071
                    QualType Ty) const override;
1072
1073
  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1074
                bool RetSmallStructInRegABI, bool Win32StructABI,
1075
                unsigned NumRegisterParameters, bool SoftFloatABI)
1076
    : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1077
      IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1078
      IsWin32StructABI(Win32StructABI),
1079
      IsSoftFloatABI(SoftFloatABI),
1080
      IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1081
2.72k
      DefaultNumRegisterParameters(NumRegisterParameters) {}
1082
1083
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1084
0
                                    bool asReturnValue) const override {
1085
0
    // LLVM's x86-32 lowering currently only assigns up to three
1086
0
    // integer registers and three fp registers.  Oddly, it'll use up to
1087
0
    // four vector registers for vectors, but those can overlap with the
1088
0
    // scalar registers.
1089
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1090
0
  }
1091
1092
0
  bool isSwiftErrorInRegister() const override {
1093
0
    // x86-32 lowering does not support passing swifterror in a register.
1094
0
    return false;
1095
0
  }
1096
};
1097
1098
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1099
public:
1100
  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1101
                          bool RetSmallStructInRegABI, bool Win32StructABI,
1102
                          unsigned NumRegisterParameters, bool SoftFloatABI)
1103
      : TargetCodeGenInfo(new X86_32ABIInfo(
1104
            CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1105
2.72k
            NumRegisterParameters, SoftFloatABI)) {}
1106
1107
  static bool isStructReturnInRegABI(
1108
      const llvm::Triple &Triple, const CodeGenOptions &Opts);
1109
1110
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1111
                           CodeGen::CodeGenModule &CGM) const override;
1112
1113
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1114
0
    // Darwin uses different dwarf register numbers for EH.
1115
0
    if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1116
0
    return 4;
1117
0
  }
1118
1119
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1120
                               llvm::Value *Address) const override;
1121
1122
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1123
                                  StringRef Constraint,
1124
537
                                  llvm::Type* Ty) const override {
1125
537
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1126
537
  }
1127
1128
  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1129
                                std::string &Constraints,
1130
                                std::vector<llvm::Type *> &ResultRegTypes,
1131
                                std::vector<llvm::Type *> &ResultTruncRegTypes,
1132
                                std::vector<LValue> &ResultRegDests,
1133
                                std::string &AsmString,
1134
                                unsigned NumOutputs) const override;
1135
1136
  llvm::Constant *
1137
36
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1138
36
    unsigned Sig = (0xeb << 0) |  // jmp rel8
1139
36
                   (0x06 << 8) |  //           .+0x08
1140
36
                   ('v' << 16) |
1141
36
                   ('2' << 24);
1142
36
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1143
36
  }
1144
1145
7
  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1146
7
    return "movl\t%ebp, %ebp"
1147
7
           "\t\t// marker for objc_retainAutoreleaseReturnValue";
1148
7
  }
1149
};
1150
1151
}
1152
1153
/// Rewrite input constraint references after adding some output constraints.
1154
/// In the case where there is one output and one input and we add one output,
1155
/// we need to replace all operand references greater than or equal to 1:
1156
///     mov $0, $1
1157
///     mov eax, $1
1158
/// The result will be:
1159
///     mov $0, $2
1160
///     mov eax, $2
1161
static void rewriteInputConstraintReferences(unsigned FirstIn,
1162
                                             unsigned NumNewOuts,
1163
23
                                             std::string &AsmString) {
1164
23
  std::string Buf;
1165
23
  llvm::raw_string_ostream OS(Buf);
1166
23
  size_t Pos = 0;
1167
74
  while (Pos < AsmString.size()) {
1168
51
    size_t DollarStart = AsmString.find('$', Pos);
1169
51
    if (DollarStart == std::string::npos)
1170
15
      DollarStart = AsmString.size();
1171
51
    size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1172
51
    if (DollarEnd == std::string::npos)
1173
15
      DollarEnd = AsmString.size();
1174
51
    OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1175
51
    Pos = DollarEnd;
1176
51
    size_t NumDollars = DollarEnd - DollarStart;
1177
51
    if (NumDollars % 2 != 0 && 
Pos < AsmString.size()18
) {
1178
18
      // We have an operand reference.
1179
18
      size_t DigitStart = Pos;
1180
18
      size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1181
18
      if (DigitEnd == std::string::npos)
1182
6
        DigitEnd = AsmString.size();
1183
18
      StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1184
18
      unsigned OperandIndex;
1185
18
      if (!OperandStr.getAsInteger(10, OperandIndex)) {
1186
18
        if (OperandIndex >= FirstIn)
1187
14
          OperandIndex += NumNewOuts;
1188
18
        OS << OperandIndex;
1189
18
      } else {
1190
0
        OS << OperandStr;
1191
0
      }
1192
18
      Pos = DigitEnd;
1193
18
    }
1194
51
  }
1195
23
  AsmString = std::move(OS.str());
1196
23
}
1197
1198
/// Add output constraints for EAX:EDX because they are return registers.
1199
void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1200
    CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1201
    std::vector<llvm::Type *> &ResultRegTypes,
1202
    std::vector<llvm::Type *> &ResultTruncRegTypes,
1203
    std::vector<LValue> &ResultRegDests, std::string &AsmString,
1204
23
    unsigned NumOutputs) const {
1205
23
  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1206
23
1207
23
  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1208
23
  // larger.
1209
23
  if (!Constraints.empty())
1210
3
    Constraints += ',';
1211
23
  if (RetWidth <= 32) {
1212
20
    Constraints += "={eax}";
1213
20
    ResultRegTypes.push_back(CGF.Int32Ty);
1214
20
  } else {
1215
3
    // Use the 'A' constraint for EAX:EDX.
1216
3
    Constraints += "=A";
1217
3
    ResultRegTypes.push_back(CGF.Int64Ty);
1218
3
  }
1219
23
1220
23
  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1221
23
  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1222
23
  ResultTruncRegTypes.push_back(CoerceTy);
1223
23
1224
23
  // Coerce the integer by bitcasting the return slot pointer.
1225
23
  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1226
23
                                                  CoerceTy->getPointerTo()));
1227
23
  ResultRegDests.push_back(ReturnSlot);
1228
23
1229
23
  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1230
23
}
1231
1232
/// shouldReturnTypeInRegister - Determine if the given type should be
1233
/// returned in a register (for the Darwin and MCU ABI).
1234
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1235
601
                                               ASTContext &Context) const {
1236
601
  uint64_t Size = Context.getTypeSize(Ty);
1237
601
1238
601
  // For i386, type must be register sized.
1239
601
  // For the MCU ABI, it only needs to be <= 8-byte
1240
601
  if ((IsMCUABI && 
Size > 6419
) ||
(598
!IsMCUABI598
&&
!isRegisterSize(Size)582
))
1241
86
   return false;
1242
515
1243
515
  if (Ty->isVectorType()) {
1244
4
    // 64- and 128- bit vectors inside structures are not returned in
1245
4
    // registers.
1246
4
    if (Size == 64 || 
Size == 1281
)
1247
3
      return false;
1248
1
1249
1
    return true;
1250
1
  }
1251
511
1252
511
  // If this is a builtin, pointer, enum, complex type, member pointer, or
1253
511
  // member function pointer it is ok.
1254
511
  if (Ty->getAs<BuiltinType>() || 
Ty->hasPointerRepresentation()421
||
1255
511
      
Ty->isAnyComplexType()396
||
Ty->isEnumeralType()371
||
1256
511
      
Ty->isBlockPointerType()369
||
Ty->isMemberPointerType()369
)
1257
404
    return true;
1258
107
1259
107
  // Arrays are treated like records.
1260
107
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1261
6
    return shouldReturnTypeInRegister(AT->getElementType(), Context);
1262
101
1263
101
  // Otherwise, it must be a record type.
1264
101
  const RecordType *RT = Ty->getAs<RecordType>();
1265
101
  if (!RT) 
return false0
;
1266
101
1267
101
  // FIXME: Traverse bases here too.
1268
101
1269
101
  // Structure types are passed in register if all fields would be
1270
101
  // passed in a register.
1271
136
  
for (const auto *FD : RT->getDecl()->fields())101
{
1272
136
    // Empty fields are ignored.
1273
136
    if (isEmptyField(Context, FD, true))
1274
11
      continue;
1275
125
1276
125
    // Check fields recursively.
1277
125
    if (!shouldReturnTypeInRegister(FD->getType(), Context))
1278
4
      return false;
1279
125
  }
1280
101
  
return true97
;
1281
101
}
1282
1283
229
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1284
229
  // Treat complex types as the element type.
1285
229
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1286
2
    Ty = CTy->getElementType();
1287
229
1288
229
  // Check for a type which we know has a simple scalar argument-passing
1289
229
  // convention without any padding.  (We're specifically looking for 32
1290
229
  // and 64-bit integer and integer-equivalents, float, and double.)
1291
229
  if (!Ty->getAs<BuiltinType>() && 
!Ty->hasPointerRepresentation()35
&&
1292
229
      
!Ty->isEnumeralType()31
&&
!Ty->isBlockPointerType()28
)
1293
28
    return false;
1294
201
1295
201
  uint64_t Size = Context.getTypeSize(Ty);
1296
201
  return Size == 32 || 
Size == 6454
;
1297
201
}
1298
1299
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1300
265
                          uint64_t &Size) {
1301
265
  for (const auto *FD : RD->fields()) {
1302
229
    // Scalar arguments on the stack get 4 byte alignment on x86. If the
1303
229
    // argument is smaller than 32-bits, expanding the struct will create
1304
229
    // alignment padding.
1305
229
    if (!is32Or64BitBasicType(FD->getType(), Context))
1306
75
      return false;
1307
154
1308
154
    // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1309
154
    // how to expand them yet, and the predicate for telling if a bitfield still
1310
154
    // counts as "basic" is more complicated than what we were doing previously.
1311
154
    if (FD->isBitField())
1312
2
      return false;
1313
152
1314
152
    Size += Context.getTypeSize(FD->getType());
1315
152
  }
1316
265
  
return true188
;
1317
265
}
1318
1319
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1320
164
                                 uint64_t &Size) {
1321
164
  // Don't do this if there are any non-empty bases.
1322
164
  for (const CXXBaseSpecifier &Base : RD->bases()) {
1323
1
    if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1324
1
                              Size))
1325
0
      return false;
1326
1
  }
1327
164
  if (!addFieldSizes(Context, RD, Size))
1328
35
    return false;
1329
129
  return true;
1330
129
}
1331
1332
/// Test whether an argument type which is to be passed indirectly (on the
1333
/// stack) would have the equivalent layout if it was expanded into separate
1334
/// arguments. If so, we prefer to do the latter to avoid inhibiting
1335
/// optimizations.
1336
386
bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1337
386
  // We can only expand structure types.
1338
386
  const RecordType *RT = Ty->getAs<RecordType>();
1339
386
  if (!RT)
1340
66
    return false;
1341
320
  const RecordDecl *RD = RT->getDecl();
1342
320
  uint64_t Size = 0;
1343
320
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1344
219
    if (!IsWin32StructABI) {
1345
102
      // On non-Windows, we have to conservatively match our old bitcode
1346
102
      // prototypes in order to be ABI-compatible at the bitcode level.
1347
102
      if (!CXXRD->isCLike())
1348
56
        return false;
1349
117
    } else {
1350
117
      // Don't do this for dynamic classes.
1351
117
      if (CXXRD->isDynamicClass())
1352
0
        return false;
1353
163
    }
1354
163
    if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1355
35
      return false;
1356
101
  } else {
1357
101
    if (!addFieldSizes(getContext(), RD, Size))
1358
42
      return false;
1359
187
  }
1360
187
1361
187
  // We can do this if there was no alignment padding.
1362
187
  return Size == getContext().getTypeSize(Ty);
1363
187
}
1364
1365
155
ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1366
155
  // If the return value is indirect, then the hidden argument is consuming one
1367
155
  // integer register.
1368
155
  if (State.FreeRegs) {
1369
6
    --State.FreeRegs;
1370
6
    if (!IsMCUABI)
1371
3
      return getNaturalAlignIndirectInReg(RetTy);
1372
152
  }
1373
152
  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1374
152
}
1375
1376
ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1377
22.5k
                                             CCState &State) const {
1378
22.5k
  if (RetTy->isVoidType())
1379
12.9k
    return ABIArgInfo::getIgnore();
1380
9.56k
1381
9.56k
  const Type *Base = nullptr;
1382
9.56k
  uint64_t NumElts = 0;
1383
9.56k
  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1384
9.56k
       
State.CC == llvm::CallingConv::X86_RegCall9.55k
) &&
1385
9.56k
      
isHomogeneousAggregate(RetTy, Base, NumElts)23
) {
1386
14
    // The LLVM struct type for such an aggregate should lower properly.
1387
14
    return ABIArgInfo::getDirect();
1388
14
  }
1389
9.55k
1390
9.55k
  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1391
31
    // On Darwin, some vectors are returned in registers.
1392
31
    if (IsDarwinVectorABI) {
1393
15
      uint64_t Size = getContext().getTypeSize(RetTy);
1394
15
1395
15
      // 128-bit vectors are a special case; they are returned in
1396
15
      // registers and we need to make sure to pick a type the LLVM
1397
15
      // backend will like.
1398
15
      if (Size == 128)
1399
5
        return ABIArgInfo::getDirect(llvm::VectorType::get(
1400
5
                  llvm::Type::getInt64Ty(getVMContext()), 2));
1401
10
1402
10
      // Always return in register if it fits in a general purpose
1403
10
      // register, or if it is 64 bits and has a single element.
1404
10
      if ((Size == 8 || Size == 16 || Size == 32) ||
1405
10
          
(7
Size == 647
&&
VT->getNumElements() == 17
))
1406
7
        return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1407
7
                                                            Size));
1408
3
1409
3
      return getIndirectReturnResult(RetTy, State);
1410
3
    }
1411
16
1412
16
    return ABIArgInfo::getDirect();
1413
16
  }
1414
9.51k
1415
9.51k
  if (isAggregateTypeForABI(RetTy)) {
1416
567
    if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1417
242
      // Structures with flexible arrays are always indirect.
1418
242
      if (RT->getDecl()->hasFlexibleArrayMember())
1419
1
        return getIndirectReturnResult(RetTy, State);
1420
566
    }
1421
566
1422
566
    // If specified, structs and unions are always indirect.
1423
566
    if (!IsRetSmallStructInRegABI && 
!RetTy->isAnyComplexType()94
)
1424
62
      return getIndirectReturnResult(RetTy, State);
1425
504
1426
504
    // Ignore empty structs/unions.
1427
504
    if (isEmptyRecord(getContext(), RetTy, true))
1428
34
      return ABIArgInfo::getIgnore();
1429
470
1430
470
    // Small structures which are register sized are generally returned
1431
470
    // in a register.
1432
470
    if (shouldReturnTypeInRegister(RetTy, getContext())) {
1433
381
      uint64_t Size = getContext().getTypeSize(RetTy);
1434
381
1435
381
      // As a special-case, if the struct is a "single-element" struct, and
1436
381
      // the field is of type "float" or "double", return it in a
1437
381
      // floating-point register. (MSVC does not apply this special case.)
1438
381
      // We apply a similar transformation for pointer types to improve the
1439
381
      // quality of the generated IR.
1440
381
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1441
69
        if ((!IsWin32StructABI && 
SeltTy->isRealFloatingType()57
)
1442
69
            || 
SeltTy->hasPointerRepresentation()53
)
1443
39
          return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1444
342
1445
342
      // FIXME: We should be able to narrow this integer in cases with dead
1446
342
      // padding.
1447
342
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1448
342
    }
1449
89
1450
89
    return getIndirectReturnResult(RetTy, State);
1451
89
  }
1452
8.95k
1453
8.95k
  // Treat an enum type as its underlying type.
1454
8.95k
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1455
98
    RetTy = EnumTy->getDecl()->getIntegerType();
1456
8.95k
1457
8.95k
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)901
1458
8.95k
                                           : 
ABIArgInfo::getDirect()8.05k
);
1459
8.95k
}
1460
1461
62
static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1462
62
  return Ty->getAs<VectorType>() && 
Context.getTypeSize(Ty) == 12812
;
1463
62
}
1464
1465
54
static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1466
54
  const RecordType *RT = Ty->getAs<RecordType>();
1467
54
  if (!RT)
1468
32
    return 0;
1469
22
  const RecordDecl *RD = RT->getDecl();
1470
22
1471
22
  // If this is a C++ record, check the bases first.
1472
22
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1473
6
    for (const auto &I : CXXRD->bases())
1474
0
      if (!isRecordWithSSEVectorType(Context, I.getType()))
1475
0
        return false;
1476
22
1477
40
  
for (const auto *i : RD->fields())22
{
1478
40
    QualType FT = i->getType();
1479
40
1480
40
    if (isSSEVectorType(Context, FT))
1481
7
      return true;
1482
33
1483
33
    if (isRecordWithSSEVectorType(Context, FT))
1484
0
      return true;
1485
33
  }
1486
22
1487
22
  
return false15
;
1488
22
}
1489
1490
unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1491
416
                                                 unsigned Align) const {
1492
416
  // Otherwise, if the alignment is less than or equal to the minimum ABI
1493
416
  // alignment, just use the default; the backend will handle this.
1494
416
  if (Align <= MinABIStackAlignInBytes)
1495
361
    return 0; // Use default alignment.
1496
55
1497
55
  // On non-Darwin, the stack type alignment is always 4.
1498
55
  if (!IsDarwinVectorABI) {
1499
23
    // Set explicit alignment, since we may need to realign the top.
1500
23
    return MinABIStackAlignInBytes;
1501
23
  }
1502
32
1503
32
  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1504
32
  if (Align >= 16 && 
(22
isSSEVectorType(getContext(), Ty)22
||
1505
22
                      
isRecordWithSSEVectorType(getContext(), Ty)21
))
1506
8
    return 16;
1507
24
1508
24
  return MinABIStackAlignInBytes;
1509
24
}
1510
1511
ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1512
479
                                            CCState &State) const {
1513
479
  if (!ByVal) {
1514
116
    if (State.FreeRegs) {
1515
18
      --State.FreeRegs; // Non-byval indirects just use one pointer.
1516
18
      if (!IsMCUABI)
1517
18
        return getNaturalAlignIndirectInReg(Ty);
1518
98
    }
1519
98
    return getNaturalAlignIndirect(Ty, false);
1520
98
  }
1521
363
1522
363
  // Compute the byval alignment.
1523
363
  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1524
363
  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1525
363
  if (StackAlign == 0)
1526
312
    return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1527
51
1528
51
  // If the stack alignment is less than the type alignment, realign the
1529
51
  // argument.
1530
51
  bool Realign = TypeAlign > StackAlign;
1531
51
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1532
51
                                 /*ByVal=*/true, Realign);
1533
51
}
1534
1535
40.1k
X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1536
40.1k
  const Type *T = isSingleElementStruct(Ty, getContext());
1537
40.1k
  if (!T)
1538
40.0k
    T = Ty.getTypePtr();
1539
40.1k
1540
40.1k
  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1541
13.6k
    BuiltinType::Kind K = BT->getKind();
1542
13.6k
    if (K == BuiltinType::Float || 
K == BuiltinType::Double13.3k
)
1543
623
      return Float;
1544
39.5k
  }
1545
39.5k
  return Integer;
1546
39.5k
}
1547
1548
40.1k
bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1549
40.1k
  if (!IsSoftFloatABI) {
1550
40.1k
    Class C = classify(Ty);
1551
40.1k
    if (C == Float)
1552
623
      return false;
1553
39.5k
  }
1554
39.5k
1555
39.5k
  unsigned Size = getContext().getTypeSize(Ty);
1556
39.5k
  unsigned SizeInRegs = (Size + 31) / 32;
1557
39.5k
1558
39.5k
  if (SizeInRegs == 0)
1559
2
    return false;
1560
39.5k
1561
39.5k
  if (!IsMCUABI) {
1562
39.5k
    if (SizeInRegs > State.FreeRegs) {
1563
39.3k
      State.FreeRegs = 0;
1564
39.3k
      return false;
1565
39.3k
    }
1566
42
  } else {
1567
42
    // The MCU psABI allows passing parameters in-reg even if there are
1568
42
    // earlier parameters that are passed on the stack. Also,
1569
42
    // it does not allow passing >8-byte structs in-register,
1570
42
    // even if there are 3 free registers available.
1571
42
    if (SizeInRegs > State.FreeRegs || 
SizeInRegs > 234
)
1572
9
      return false;
1573
234
  }
1574
234
1575
234
  State.FreeRegs -= SizeInRegs;
1576
234
  return true;
1577
234
}
1578
1579
bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1580
                                             bool &InReg,
1581
462
                                             bool &NeedsPadding) const {
1582
462
  // On Windows, aggregates other than HFAs are never passed in registers, and
1583
462
  // they do not consume register slots. Homogenous floating-point aggregates
1584
462
  // (HFAs) have already been dealt with at this point.
1585
462
  if (IsWin32StructABI && 
isAggregateTypeForABI(Ty)163
)
1586
163
    return false;
1587
299
1588
299
  NeedsPadding = false;
1589
299
  InReg = !IsMCUABI;
1590
299
1591
299
  if (!updateFreeRegs(Ty, State))
1592
279
    return false;
1593
20
1594
20
  if (IsMCUABI)
1595
7
    return true;
1596
13
1597
13
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1598
13
      
State.CC == llvm::CallingConv::X86_VectorCall10
||
1599
13
      
State.CC == llvm::CallingConv::X86_RegCall10
) {
1600
4
    if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1601
3
      NeedsPadding = true;
1602
4
1603
4
    return false;
1604
4
  }
1605
9
1606
9
  return true;
1607
9
}
1608
1609
39.8k
bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1610
39.8k
  if (!updateFreeRegs(Ty, State))
1611
39.6k
    return false;
1612
214
1613
214
  if (IsMCUABI)
1614
26
    return false;
1615
188
1616
188
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1617
188
      
State.CC == llvm::CallingConv::X86_VectorCall134
||
1618
188
      
State.CC == llvm::CallingConv::X86_RegCall94
) {
1619
137
    if (getContext().getTypeSize(Ty) > 32)
1620
13
      return false;
1621
124
1622
124
    return (Ty->isIntegralOrEnumerationType() || 
Ty->isPointerType()27
||
1623
124
        
Ty->isReferenceType()7
);
1624
124
  }
1625
51
1626
51
  return true;
1627
51
}
1628
1629
ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1630
40.6k
                                               CCState &State) const {
1631
40.6k
  // FIXME: Set alignment on indirect arguments.
1632
40.6k
1633
40.6k
  Ty = useFirstFieldIfTransparentUnion(Ty);
1634
40.6k
1635
40.6k
  // Check with the C++ ABI first.
1636
40.6k
  const RecordType *RT = Ty->getAs<RecordType>();
1637
40.6k
  if (RT) {
1638
620
    CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1639
620
    if (RAA == CGCXXABI::RAA_Indirect) {
1640
98
      return getIndirectResult(Ty, false, State);
1641
522
    } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1642
78
      // The field index doesn't matter, we'll fix it up later.
1643
78
      return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1644
78
    }
1645
40.5k
  }
1646
40.5k
1647
40.5k
  // Regcall uses the concept of a homogenous vector aggregate, similar
1648
40.5k
  // to other targets.
1649
40.5k
  const Type *Base = nullptr;
1650
40.5k
  uint64_t NumElts = 0;
1651
40.5k
  if (State.CC == llvm::CallingConv::X86_RegCall &&
1652
40.5k
      
isHomogeneousAggregate(Ty, Base, NumElts)102
) {
1653
51
1654
51
    if (State.FreeSSERegs >= NumElts) {
1655
43
      State.FreeSSERegs -= NumElts;
1656
43
      if (Ty->isBuiltinType() || 
Ty->isVectorType()33
)
1657
20
        return ABIArgInfo::getDirect();
1658
23
      return ABIArgInfo::getExpand();
1659
23
    }
1660
8
    return getIndirectResult(Ty, /*ByVal=*/false, State);
1661
8
  }
1662
40.4k
1663
40.4k
  if (isAggregateTypeForABI(Ty)) {
1664
494
    // Structures with flexible arrays are always indirect.
1665
494
    // FIXME: This should not be byval!
1666
494
    if (RT && 
RT->getDecl()->hasFlexibleArrayMember()418
)
1667
1
      return getIndirectResult(Ty, true, State);
1668
493
1669
493
    // Ignore empty structs/unions on non-Windows.
1670
493
    if (!IsWin32StructABI && 
isEmptyRecord(getContext(), Ty, true)330
)
1671
31
      return ABIArgInfo::getIgnore();
1672
462
1673
462
    llvm::LLVMContext &LLVMContext = getVMContext();
1674
462
    llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1675
462
    bool NeedsPadding = false;
1676
462
    bool InReg;
1677
462
    if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1678
16
      unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1679
16
      SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1680
16
      llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1681
16
      if (InReg)
1682
9
        return ABIArgInfo::getDirectInReg(Result);
1683
7
      else
1684
7
        return ABIArgInfo::getDirect(Result);
1685
446
    }
1686
446
    llvm::IntegerType *PaddingType = NeedsPadding ? 
Int323
:
nullptr443
;
1687
446
1688
446
    // Expand small (<= 128-bit) record types when we know that the stack layout
1689
446
    // of those arguments will match the struct. This is important because the
1690
446
    // LLVM backend isn't smart enough to remove byval, which inhibits many
1691
446
    // optimizations.
1692
446
    // Don't do this for the MCU if there are still free integer registers
1693
446
    // (see X86_64 ABI for full explanation).
1694
446
    if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1695
446
        
(389
!IsMCUABI389
||
State.FreeRegs == 05
) &&
canExpandIndirectArgument(Ty)386
)
1696
84
      return ABIArgInfo::getExpandWithPadding(
1697
84
          State.CC == llvm::CallingConv::X86_FastCall ||
1698
84
              
State.CC == llvm::CallingConv::X86_VectorCall80
||
1699
84
              
State.CC == llvm::CallingConv::X86_RegCall79
,
1700
84
          PaddingType);
1701
362
1702
362
    return getIndirectResult(Ty, true, State);
1703
362
  }
1704
39.9k
1705
39.9k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1706
68
    // On Darwin, some vectors are passed in memory, we handle this by passing
1707
68
    // it as an i8/i16/i32/i64.
1708
68
    if (IsDarwinVectorABI) {
1709
24
      uint64_t Size = getContext().getTypeSize(Ty);
1710
24
      if ((Size == 8 || Size == 16 || Size == 32) ||
1711
24
          
(22
Size == 6422
&&
VT->getNumElements() == 110
))
1712
7
        return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1713
7
                                                            Size));
1714
61
    }
1715
61
1716
61
    if (IsX86_MMXType(CGT.ConvertType(Ty)))
1717
8
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1718
53
1719
53
    return ABIArgInfo::getDirect();
1720
53
  }
1721
39.8k
1722
39.8k
1723
39.8k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1724
312
    Ty = EnumTy->getDecl()->getIntegerType();
1725
39.8k
1726
39.8k
  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1727
39.8k
1728
39.8k
  if (Ty->isPromotableIntegerType()) {
1729
662
    if (InReg)
1730
25
      return ABIArgInfo::getExtendInReg(Ty);
1731
637
    return ABIArgInfo::getExtend(Ty);
1732
637
  }
1733
39.2k
1734
39.2k
  if (InReg)
1735
150
    return ABIArgInfo::getDirectInReg();
1736
39.0k
  return ABIArgInfo::getDirect();
1737
39.0k
}
1738
1739
void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1740
52
                                          bool &UsedInAlloca) const {
1741
52
  // Vectorcall x86 works subtly different than in x64, so the format is
1742
52
  // a bit different than the x64 version.  First, all vector types (not HVAs)
1743
52
  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1744
52
  // This differs from the x64 implementation, where the first 6 by INDEX get
1745
52
  // registers.
1746
52
  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1747
52
  // Integers are passed as ECX/EDX if one is available (in order).  HVAs will
1748
52
  // first take up the remaining YMM/XMM registers. If insufficient registers
1749
52
  // remain but an integer register (ECX/EDX) is available, it will be passed
1750
52
  // in that, else, on the stack.
1751
92
  for (auto &I : FI.arguments()) {
1752
92
    // First pass do all the vector types.
1753
92
    const Type *Base = nullptr;
1754
92
    uint64_t NumElts = 0;
1755
92
    const QualType& Ty = I.type;
1756
92
    if ((Ty->isVectorType() || 
Ty->isBuiltinType()79
) &&
1757
92
        
isHomogeneousAggregate(Ty, Base, NumElts)63
) {
1758
24
      if (State.FreeSSERegs >= NumElts) {
1759
24
        State.FreeSSERegs -= NumElts;
1760
24
        I.info = ABIArgInfo::getDirect();
1761
24
      } else {
1762
0
        I.info = classifyArgumentType(Ty, State);
1763
0
      }
1764
24
      UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1765
24
    }
1766
92
  }
1767
52
1768
92
  for (auto &I : FI.arguments()) {
1769
92
    // Second pass, do the rest!
1770
92
    const Type *Base = nullptr;
1771
92
    uint64_t NumElts = 0;
1772
92
    const QualType& Ty = I.type;
1773
92
    bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1774
92
1775
92
    if (IsHva && 
!Ty->isVectorType()46
&&
!Ty->isBuiltinType()33
) {
1776
22
      // Assign true HVAs (non vector/native FP types).
1777
22
      if (State.FreeSSERegs >= NumElts) {
1778
12
        State.FreeSSERegs -= NumElts;
1779
12
        I.info = getDirectX86Hva();
1780
12
      } else {
1781
10
        I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1782
10
      }
1783
70
    } else if (!IsHva) {
1784
46
      // Assign all Non-HVAs, so this will exclude Vector/FP args.
1785
46
      I.info = classifyArgumentType(Ty, State);
1786
46
      UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1787
46
    }
1788
92
  }
1789
52
}
1790
1791
22.6k
void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1792
22.6k
  CCState State(FI.getCallingConvention());
1793
22.6k
  if (IsMCUABI)
1794
33
    State.FreeRegs = 3;
1795
22.6k
  else if (State.CC == llvm::CallingConv::X86_FastCall)
1796
68
    State.FreeRegs = 2;
1797
22.5k
  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1798
52
    State.FreeRegs = 2;
1799
52
    State.FreeSSERegs = 6;
1800
22.4k
  } else if (FI.getHasRegParm())
1801
32
    State.FreeRegs = FI.getRegParm();
1802
22.4k
  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1803
50
    State.FreeRegs = 5;
1804
50
    State.FreeSSERegs = 8;
1805
50
  } else
1806
22.4k
    State.FreeRegs = DefaultNumRegisterParameters;
1807
22.6k
1808
22.6k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1809
22.5k
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1810
22.5k
  } else 
if (81
FI.getReturnInfo().isIndirect()81
) {
1811
81
    // The C++ ABI is not aware of register usage, so we have to check if the
1812
81
    // return value was sret and put it in a register ourselves if appropriate.
1813
81
    if (State.FreeRegs) {
1814
4
      --State.FreeRegs;  // The sret parameter consumes a register.
1815
4
      if (!IsMCUABI)
1816
4
        FI.getReturnInfo().setInReg(true);
1817
4
    }
1818
81
  }
1819
22.6k
1820
22.6k
  // The chain argument effectively gives us another free register.
1821
22.6k
  if (FI.isChainCall())
1822
4
    ++State.FreeRegs;
1823
22.6k
1824
22.6k
  bool UsedInAlloca = false;
1825
22.6k
  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1826
52
    computeVectorCallArgs(FI, State, UsedInAlloca);
1827
22.5k
  } else {
1828
22.5k
    // If not vectorcall, revert to normal behavior.
1829
40.6k
    for (auto &I : FI.arguments()) {
1830
40.6k
      I.info = classifyArgumentType(I.type, State);
1831
40.6k
      UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1832
40.6k
    }
1833
22.5k
  }
1834
22.6k
1835
22.6k
  // If we needed to use inalloca for any argument, do a second pass and rewrite
1836
22.6k
  // all the memory arguments to use inalloca.
1837
22.6k
  if (UsedInAlloca)
1838
66
    rewriteWithInAlloca(FI);
1839
22.6k
}
1840
1841
void
1842
X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1843
                                   CharUnits &StackOffset, ABIArgInfo &Info,
1844
153
                                   QualType Type) const {
1845
153
  // Arguments are always 4-byte-aligned.
1846
153
  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1847
153
1848
153
  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1849
153
  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1850
153
  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1851
153
  StackOffset += getContext().getTypeSizeInChars(Type);
1852
153
1853
153
  // Insert padding bytes to respect alignment.
1854
153
  CharUnits FieldEnd = StackOffset;
1855
153
  StackOffset = FieldEnd.alignTo(FieldAlign);
1856
153
  if (StackOffset != FieldEnd) {
1857
40
    CharUnits NumBytes = StackOffset - FieldEnd;
1858
40
    llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1859
40
    Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1860
40
    FrameFields.push_back(Ty);
1861
40
  }
1862
153
}
1863
1864
147
static bool isArgInAlloca(const ABIArgInfo &Info) {
1865
147
  // Leave ignored and inreg arguments alone.
1866
147
  switch (Info.getKind()) {
1867
147
  case ABIArgInfo::InAlloca:
1868
78
    return true;
1869
147
  case ABIArgInfo::Indirect:
1870
3
    assert(Info.getIndirectByVal());
1871
3
    return true;
1872
147
  case ABIArgInfo::Ignore:
1873
0
    return false;
1874
147
  case ABIArgInfo::Direct:
1875
65
  case ABIArgInfo::Extend:
1876
65
    if (Info.getInReg())
1877
2
      return false;
1878
63
    return true;
1879
63
  case ABIArgInfo::Expand:
1880
1
  case ABIArgInfo::CoerceAndExpand:
1881
1
    // These are aggregate types which are never passed in registers when
1882
1
    // inalloca is involved.
1883
1
    return true;
1884
0
  }
1885
0
  llvm_unreachable("invalid enum");
1886
0
}
1887
1888
66
void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1889
66
  assert(IsWin32StructABI && "inalloca only supported on win32");
1890
66
1891
66
  // Build a packed struct type for all of the arguments in memory.
1892
66
  SmallVector<llvm::Type *, 6> FrameFields;
1893
66
1894
66
  // The stack alignment is always 4.
1895
66
  CharUnits StackAlign = CharUnits::fromQuantity(4);
1896
66
1897
66
  CharUnits StackOffset;
1898
66
  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1899
66
1900
66
  // Put 'this' into the struct before 'sret', if necessary.
1901
66
  bool IsThisCall =
1902
66
      FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1903
66
  ABIArgInfo &Ret = FI.getReturnInfo();
1904
66
  if (Ret.isIndirect() && 
Ret.isSRetAfterThis()9
&&
!IsThisCall7
&&
1905
66
      
isArgInAlloca(I->info)6
) {
1906
5
    addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1907
5
    ++I;
1908
5
  }
1909
66
1910
66
  // Put the sret parameter into the inalloca struct if it's in memory.
1911
66
  if (Ret.isIndirect() && 
!Ret.getInReg()9
) {
1912
8
    CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1913
8
    addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1914
8
    // On Windows, the hidden sret parameter is always returned in eax.
1915
8
    Ret.setInAllocaSRet(IsWin32StructABI);
1916
8
  }
1917
66
1918
66
  // Skip the 'this' parameter in ecx.
1919
66
  if (IsThisCall)
1920
16
    ++I;
1921
66
1922
66
  // Put arguments passed in memory into the struct.
1923
207
  for (; I != E; 
++I141
) {
1924
141
    if (isArgInAlloca(I->info))
1925
140
      addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1926
141
  }
1927
66
1928
66
  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1929
66
                                        /*isPacked=*/true),
1930
66
                  StackAlign);
1931
66
}
1932
1933
Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1934
53
                                 Address VAListAddr, QualType Ty) const {
1935
53
1936
53
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1937
53
1938
53
  // x86-32 changes the alignment of certain arguments on the stack.
1939
53
  //
1940
53
  // Just messing with TypeInfo like this works because we never pass
1941
53
  // anything indirectly.
1942
53
  TypeInfo.second = CharUnits::fromQuantity(
1943
53
                getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1944
53
1945
53
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1946
53
                          TypeInfo, CharUnits::fromQuantity(4),
1947
53
                          /*AllowHigherAlign*/ true);
1948
53
}
1949
1950
bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1951
2.72k
    const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1952
2.72k
  assert(Triple.getArch() == llvm::Triple::x86);
1953
2.72k
1954
2.72k
  switch (Opts.getStructReturnConvention()) {
1955
2.72k
  case CodeGenOptions::SRCK_Default:
1956
2.71k
    break;
1957
2.72k
  case CodeGenOptions::SRCK_OnStack:  // -fpcc-struct-return
1958
3
    return false;
1959
2.72k
  case CodeGenOptions::SRCK_InRegs:  // -freg-struct-return
1960
3
    return true;
1961
2.71k
  }
1962
2.71k
1963
2.71k
  if (Triple.isOSDarwin() || 
Triple.isOSIAMCU()2.06k
)
1964
655
    return true;
1965
2.06k
1966
2.06k
  switch (Triple.getOS()) {
1967
2.06k
  case llvm::Triple::DragonFly:
1968
400
  case llvm::Triple::FreeBSD:
1969
400
  case llvm::Triple::OpenBSD:
1970
400
  case llvm::Triple::Win32:
1971
400
    return true;
1972
1.66k
  default:
1973
1.66k
    return false;
1974
2.06k
  }
1975
2.06k
}
1976
1977
void X86_32TargetCodeGenInfo::setTargetAttributes(
1978
73.9k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1979
73.9k
  if (GV->isDeclaration())
1980
45.1k
    return;
1981
28.7k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1982
24.1k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1983
2
      llvm::Function *Fn = cast<llvm::Function>(GV);
1984
2
      Fn->addFnAttr("stackrealign");
1985
2
    }
1986
24.1k
    if (FD->hasAttr<AnyX86InterruptAttr>()) {
1987
10
      llvm::Function *Fn = cast<llvm::Function>(GV);
1988
10
      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1989
10
    }
1990
24.1k
  }
1991
28.7k
}
1992
1993
bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1994
                                               CodeGen::CodeGenFunction &CGF,
1995
0
                                               llvm::Value *Address) const {
1996
0
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1997
0
1998
0
  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1999
0
2000
0
  // 0-7 are the eight integer registers;  the order is different
2001
0
  //   on Darwin (for EH), but the range is the same.
2002
0
  // 8 is %eip.
2003
0
  AssignToArrayRange(Builder, Address, Four8, 0, 8);
2004
0
2005
0
  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2006
0
    // 12-16 are st(0..4).  Not sure why we stop at 4.
2007
0
    // These have size 16, which is sizeof(long double) on
2008
0
    // platforms with 8-byte alignment for that type.
2009
0
    llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2010
0
    AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2011
0
2012
0
  } else {
2013
0
    // 9 is %eflags, which doesn't get a size on Darwin for some
2014
0
    // reason.
2015
0
    Builder.CreateAlignedStore(
2016
0
        Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2017
0
                               CharUnits::One());
2018
0
2019
0
    // 11-16 are st(0..5).  Not sure why we stop at 5.
2020
0
    // These have size 12, which is sizeof(long double) on
2021
0
    // platforms with 4-byte alignment for that type.
2022
0
    llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2023
0
    AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2024
0
  }
2025
0
2026
0
  return false;
2027
0
}
2028
2029
//===----------------------------------------------------------------------===//
2030
// X86-64 ABI Implementation
2031
//===----------------------------------------------------------------------===//
2032
2033
2034
namespace {
2035
/// The AVX ABI level for X86 targets.
2036
enum class X86AVXABILevel {
2037
  None,
2038
  AVX,
2039
  AVX512
2040
};
2041
2042
/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2043
3.12k
static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2044
3.12k
  switch (AVXLevel) {
2045
3.12k
  case X86AVXABILevel::AVX512:
2046
2.43k
    return 512;
2047
3.12k
  case X86AVXABILevel::AVX:
2048
592
    return 256;
2049
3.12k
  case X86AVXABILevel::None:
2050
99
    return 128;
2051
0
  }
2052
0
  llvm_unreachable("Unknown AVXLevel");
2053
0
}
2054
2055
/// X86_64ABIInfo - The X86_64 ABI information.
2056
class X86_64ABIInfo : public SwiftABIInfo {
2057
  enum Class {
2058
    Integer = 0,
2059
    SSE,
2060
    SSEUp,
2061
    X87,
2062
    X87Up,
2063
    ComplexX87,
2064
    NoClass,
2065
    Memory
2066
  };
2067
2068
  /// merge - Implement the X86_64 ABI merging algorithm.
2069
  ///
2070
  /// Merge an accumulating classification \arg Accum with a field
2071
  /// classification \arg Field.
2072
  ///
2073
  /// \param Accum - The accumulating classification. This should
2074
  /// always be either NoClass or the result of a previous merge
2075
  /// call. In addition, this should never be Memory (the caller
2076
  /// should just return Memory for the aggregate).
2077
  static Class merge(Class Accum, Class Field);
2078
2079
  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2080
  ///
2081
  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2082
  /// final MEMORY or SSE classes when necessary.
2083
  ///
2084
  /// \param AggregateSize - The size of the current aggregate in
2085
  /// the classification process.
2086
  ///
2087
  /// \param Lo - The classification for the parts of the type
2088
  /// residing in the low word of the containing object.
2089
  ///
2090
  /// \param Hi - The classification for the parts of the type
2091
  /// residing in the higher words of the containing object.
2092
  ///
2093
  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2094
2095
  /// classify - Determine the x86_64 register classes in which the
2096
  /// given type T should be passed.
2097
  ///
2098
  /// \param Lo - The classification for the parts of the type
2099
  /// residing in the low word of the containing object.
2100
  ///
2101
  /// \param Hi - The classification for the parts of the type
2102
  /// residing in the high word of the containing object.
2103
  ///
2104
  /// \param OffsetBase - The bit offset of this type in the
2105
  /// containing object.  Some parameters are classified different
2106
  /// depending on whether they straddle an eightbyte boundary.
2107
  ///
2108
  /// \param isNamedArg - Whether the argument in question is a "named"
2109
  /// argument, as used in AMD64-ABI 3.5.7.
2110
  ///
2111
  /// If a word is unused its result will be NoClass; if a type should
2112
  /// be passed in Memory then at least the classification of \arg Lo
2113
  /// will be Memory.
2114
  ///
2115
  /// The \arg Lo class will be NoClass iff the argument is ignored.
2116
  ///
2117
  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2118
  /// also be ComplexX87.
2119
  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2120
                bool isNamedArg) const;
2121
2122
  llvm::Type *GetByteVectorType(QualType Ty) const;
2123
  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2124
                                 unsigned IROffset, QualType SourceTy,
2125
                                 unsigned SourceOffset) const;
2126
  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2127
                                     unsigned IROffset, QualType SourceTy,
2128
                                     unsigned SourceOffset) const;
2129
2130
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2131
  /// such that the argument will be returned in memory.
2132
  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2133
2134
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2135
  /// such that the argument will be passed in memory.
2136
  ///
2137
  /// \param freeIntRegs - The number of free integer registers remaining
2138
  /// available.
2139
  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2140
2141
  ABIArgInfo classifyReturnType(QualType RetTy) const;
2142
2143
  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2144
                                  unsigned &neededInt, unsigned &neededSSE,
2145
                                  bool isNamedArg) const;
2146
2147
  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2148
                                       unsigned &NeededSSE) const;
2149
2150
  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2151
                                           unsigned &NeededSSE) const;
2152
2153
  bool IsIllegalVectorType(QualType Ty) const;
2154
2155
  /// The 0.98 ABI revision clarified a lot of ambiguities,
2156
  /// unfortunately in ways that were not always consistent with
2157
  /// certain previous compilers.  In particular, platforms which
2158
  /// required strict binary compatibility with older versions of GCC
2159
  /// may need to exempt themselves.
2160
17
  bool honorsRevision0_98() const {
2161
17
    return !getTarget().getTriple().isOSDarwin();
2162
17
  }
2163
2164
  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2165
  /// classify it as INTEGER (for compatibility with older clang compilers).
2166
143
  bool classifyIntegerMMXAsSSE() const {
2167
143
    // Clang <= 3.8 did not do this.
2168
143
    if (getContext().getLangOpts().getClangABICompat() <=
2169
143
        LangOptions::ClangABI::Ver3_8)
2170
2
      return false;
2171
141
2172
141
    const llvm::Triple &Triple = getTarget().getTriple();
2173
141
    if (Triple.isOSDarwin() || 
Triple.getOS() == llvm::Triple::PS462
)
2174
84
      return false;
2175
57
    if (Triple.isOSFreeBSD() && 
Triple.getOSMajorVersion() >= 100
)
2176
0
      return false;
2177
57
    return true;
2178
57
  }
2179
2180
  X86AVXABILevel AVXLevel;
2181
  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2182
  // 64-bit hardware.
2183
  bool Has64BitPointers;
2184
2185
public:
2186
  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2187
      SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2188
6.25k
      Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2189
6.25k
  }
2190
2191
84
  bool isPassedUsingAVXType(QualType type) const {
2192
84
    unsigned neededInt, neededSSE;
2193
84
    // The freeIntRegs argument doesn't matter here.
2194
84
    ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2195
84
                                           /*isNamedArg*/true);
2196
84
    if (info.isDirect()) {
2197
83
      llvm::Type *ty = info.getCoerceToType();
2198
83
      if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2199
2
        return (vectorTy->getBitWidth() > 128);
2200
82
    }
2201
82
    return false;
2202
82
  }
2203
2204
  void computeInfo(CGFunctionInfo &FI) const override;
2205
2206
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2207
                    QualType Ty) const override;
2208
  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2209
                      QualType Ty) const override;
2210
2211
0
  bool has64BitPointers() const {
2212
0
    return Has64BitPointers;
2213
0
  }
2214
2215
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2216
298
                                    bool asReturnValue) const override {
2217
298
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2218
298
  }
2219
0
  bool isSwiftErrorInRegister() const override {
2220
0
    return true;
2221
0
  }
2222
};
2223
2224
/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2225
class WinX86_64ABIInfo : public SwiftABIInfo {
2226
public:
2227
  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2228
      : SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2229
313
        IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2230
2231
  void computeInfo(CGFunctionInfo &FI) const override;
2232
2233
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2234
                    QualType Ty) const override;
2235
2236
369
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2237
369
    // FIXME: Assumes vectorcall is in use.
2238
369
    return isX86VectorTypeForVectorCall(getContext(), Ty);
2239
369
  }
2240
2241
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2242
406
                                         uint64_t NumMembers) const override {
2243
406
    // FIXME: Assumes vectorcall is in use.
2244
406
    return isX86VectorCallAggregateSmallEnough(NumMembers);
2245
406
  }
2246
2247
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2248
25
                                    bool asReturnValue) const override {
2249
25
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2250
25
  }
2251
2252
0
  bool isSwiftErrorInRegister() const override {
2253
0
    return true;
2254
0
  }
2255
2256
private:
2257
  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2258
                      bool IsVectorCall, bool IsRegCall) const;
2259
  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2260
                                      const ABIArgInfo &current) const;
2261
  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2262
                             bool IsVectorCall, bool IsRegCall) const;
2263
2264
  X86AVXABILevel AVXLevel;
2265
2266
  bool IsMingw64;
2267
};
2268
2269
class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2270
public:
2271
  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2272
6.23k
      : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2273
2274
84
  const X86_64ABIInfo &getABIInfo() const {
2275
84
    return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2276
84
  }
2277
2278
  /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2279
  /// the autoreleaseRV/retainRV optimization.
2280
218
  bool shouldSuppressTailCallsOfRetainAutoreleasedReturnValue() const override {
2281
218
    return true;
2282
218
  }
2283
2284
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2285
0
    return 7;
2286
0
  }
2287
2288
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2289
0
                               llvm::Value *Address) const override {
2290
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2291
0
2292
0
    // 0-15 are the 16 integer registers.
2293
0
    // 16 is %rip.
2294
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2295
0
    return false;
2296
0
  }
2297
2298
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2299
                                  StringRef Constraint,
2300
524
                                  llvm::Type* Ty) const override {
2301
524
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2302
524
  }
2303
2304
  bool isNoProtoCallVariadic(const CallArgList &args,
2305
484
                             const FunctionNoProtoType *fnType) const override {
2306
484
    // The default CC on x86-64 sets %al to the number of SSA
2307
484
    // registers used, and GCC sets this when calling an unprototyped
2308
484
    // function, so we override the default behavior.  However, don't do
2309
484
    // that when AVX types are involved: the ABI explicitly states it is
2310
484
    // undefined, and it doesn't work in practice because of how the ABI
2311
484
    // defines varargs anyway.
2312
484
    if (fnType->getCallConv() == CC_C) {
2313
484
      bool HasAVXType = false;
2314
484
      for (CallArgList::const_iterator
2315
566
             it = args.begin(), ie = args.end(); it != ie; 
++it82
) {
2316
84
        if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2317
2
          HasAVXType = true;
2318
2
          break;
2319
2
        }
2320
84
      }
2321
484
2322
484
      if (!HasAVXType)
2323
482
        return true;
2324
2
    }
2325
2
2326
2
    return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2327
2
  }
2328
2329
  llvm::Constant *
2330
82
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2331
82
    unsigned Sig = (0xeb << 0) | // jmp rel8
2332
82
                   (0x06 << 8) | //           .+0x08
2333
82
                   ('v' << 16) |
2334
82
                   ('2' << 24);
2335
82
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2336
82
  }
2337
2338
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2339
271k
                           CodeGen::CodeGenModule &CGM) const override {
2340
271k
    if (GV->isDeclaration())
2341
153k
      return;
2342
117k
    if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2343
105k
      if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2344
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
2345
1
        Fn->addFnAttr("stackrealign");
2346
1
      }
2347
105k
      if (FD->hasAttr<AnyX86InterruptAttr>()) {
2348
10
        llvm::Function *Fn = cast<llvm::Function>(GV);
2349
10
        Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2350
10
      }
2351
105k
    }
2352
117k
  }
2353
};
2354
2355
73
static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2356
73
  // If the argument does not end in .lib, automatically add the suffix.
2357
73
  // If the argument contains a space, enclose it in quotes.
2358
73
  // This matches the behavior of MSVC.
2359
73
  bool Quote = (Lib.find(" ") != StringRef::npos);
2360
73
  std::string ArgStr = Quote ? 
"\""4
:
""69
;
2361
73
  ArgStr += Lib;
2362
73
  if (!Lib.endswith_lower(".lib") && 
!Lib.endswith_lower(".a")61
)
2363
61
    ArgStr += ".lib";
2364
73
  ArgStr += Quote ? 
"\""4
:
""69
;
2365
73
  return ArgStr;
2366
73
}
2367
2368
class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2369
public:
2370
  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2371
        bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2372
        unsigned NumRegisterParameters)
2373
    : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2374
400
        Win32StructABI, NumRegisterParameters, false) {}
2375
2376
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2377
                           CodeGen::CodeGenModule &CGM) const override;
2378
2379
  void getDependentLibraryOption(llvm::StringRef Lib,
2380
31
                                 llvm::SmallString<24> &Opt) const override {
2381
31
    Opt = "/DEFAULTLIB:";
2382
31
    Opt += qualifyWindowsLibrary(Lib);
2383
31
  }
2384
2385
  void getDetectMismatchOption(llvm::StringRef Name,
2386
                               llvm::StringRef Value,
2387
2
                               llvm::SmallString<32> &Opt) const override {
2388
2
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2389
2
  }
2390
};
2391
2392
static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2393
16.0k
                                          CodeGen::CodeGenModule &CGM) {
2394
16.0k
  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2395
13.7k
2396
13.7k
    if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2397
1
      Fn->addFnAttr("stack-probe-size",
2398
1
                    llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2399
13.7k
    if (CGM.getCodeGenOpts().NoStackArgProbe)
2400
4
      Fn->addFnAttr("no-stack-arg-probe");
2401
13.7k
  }
2402
16.0k
}
2403
2404
void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2405
16.8k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2406
16.8k
  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2407
16.8k
  if (GV->isDeclaration())
2408
9.62k
    return;
2409
7.23k
  addStackProbeTargetAttributes(D, GV, CGM);
2410
7.23k
}
2411
2412
class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2413
public:
2414
  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2415
                             X86AVXABILevel AVXLevel)
2416
302
      : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT, AVXLevel)) {}
2417
2418
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2419
                           CodeGen::CodeGenModule &CGM) const override;
2420
2421
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2422
0
    return 7;
2423
0
  }
2424
2425
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2426
0
                               llvm::Value *Address) const override {
2427
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2428
0
2429
0
    // 0-15 are the 16 integer registers.
2430
0
    // 16 is %rip.
2431
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2432
0
    return false;
2433
0
  }
2434
2435
  void getDependentLibraryOption(llvm::StringRef Lib,
2436
31
                                 llvm::SmallString<24> &Opt) const override {
2437
31
    Opt = "/DEFAULTLIB:";
2438
31
    Opt += qualifyWindowsLibrary(Lib);
2439
31
  }
2440
2441
  void getDetectMismatchOption(llvm::StringRef Name,
2442
                               llvm::StringRef Value,
2443
2
                               llvm::SmallString<32> &Opt) const override {
2444
2
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2445
2
  }
2446
};
2447
2448
void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2449
17.5k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2450
17.5k
  TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2451
17.5k
  if (GV->isDeclaration())
2452
9.55k
    return;
2453
8.01k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2454
7.06k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2455
0
      llvm::Function *Fn = cast<llvm::Function>(GV);
2456
0
      Fn->addFnAttr("stackrealign");
2457
0
    }
2458
7.06k
    if (FD->hasAttr<AnyX86InterruptAttr>()) {
2459
5
      llvm::Function *Fn = cast<llvm::Function>(GV);
2460
5
      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2461
5
    }
2462
7.06k
  }
2463
8.01k
2464
8.01k
  addStackProbeTargetAttributes(D, GV, CGM);
2465
8.01k
}
2466
}
2467
2468
void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2469
6.12k
                              Class &Hi) const {
2470
6.12k
  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2471
6.12k
  //
2472
6.12k
  // (a) If one of the classes is Memory, the whole argument is passed in
2473
6.12k
  //     memory.
2474
6.12k
  //
2475
6.12k
  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2476
6.12k
  //     memory.
2477
6.12k
  //
2478
6.12k
  // (c) If the size of the aggregate exceeds two eightbytes and the first
2479
6.12k
  //     eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2480
6.12k
  //     argument is passed in memory. NOTE: This is necessary to keep the
2481
6.12k
  //     ABI working for processors that don't support the __m256 type.
2482
6.12k
  //
2483
6.12k
  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2484
6.12k
  //
2485
6.12k
  // Some of these are enforced by the merging logic.  Others can arise
2486
6.12k
  // only with unions; for example:
2487
6.12k
  //   union { _Complex double; unsigned; }
2488
6.12k
  //
2489
6.12k
  // Note that clauses (b) and (c) were added in 0.98.
2490
6.12k
  //
2491
6.12k
  if (Hi == Memory)
2492
0
    Lo = Memory;
2493
6.12k
  if (Hi == X87Up && 
Lo != X8720
&&
honorsRevision0_98()17
)
2494
15
    Lo = Memory;
2495
6.12k
  if (AggregateSize > 128 && 
(379
Lo != SSE379
||
Hi != SSEUp21
))
2496
358
    Lo = Memory;
2497
6.12k
  if (Hi == SSEUp && 
Lo != SSE30
)
2498
1
    Hi = SSE;
2499
6.12k
}
2500
2501
10.8k
X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2502
10.8k
  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2503
10.8k
  // classified recursively so that always two fields are
2504
10.8k
  // considered. The resulting class is calculated according to
2505
10.8k
  // the classes of the fields in the eightbyte:
2506
10.8k
  //
2507
10.8k
  // (a) If both classes are equal, this is the resulting class.
2508
10.8k
  //
2509
10.8k
  // (b) If one of the classes is NO_CLASS, the resulting class is
2510
10.8k
  // the other class.
2511
10.8k
  //
2512
10.8k
  // (c) If one of the classes is MEMORY, the result is the MEMORY
2513
10.8k
  // class.
2514
10.8k
  //
2515
10.8k
  // (d) If one of the classes is INTEGER, the result is the
2516
10.8k
  // INTEGER.
2517
10.8k
  //
2518
10.8k
  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2519
10.8k
  // MEMORY is used as class.
2520
10.8k
  //
2521
10.8k
  // (f) Otherwise class SSE is used.
2522
10.8k
2523
10.8k
  // Accum should never be memory (we should have returned) or
2524
10.8k
  // ComplexX87 (because this cannot be passed in a structure).
2525
10.8k
  assert((Accum != Memory && Accum != ComplexX87) &&
2526
10.8k
         "Invalid accumulated classification during merge.");
2527
10.8k
  if (Accum == Field || 
Field == NoClass5.38k
)
2528
6.53k
    return Accum;
2529
4.31k
  if (Field == Memory)
2530
13
    return Memory;
2531
4.30k
  if (Accum == NoClass)
2532
4.27k
    return Field;
2533
28
  if (Accum == Integer || 
Field == Integer18
)
2534
25
    return Integer;
2535
3
  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2536
3
      Accum == X87 || 
Accum == X87Up0
)
2537
3
    return Memory;
2538
0
  return SSE;
2539
0
}
2540
2541
void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2542
249k
                             Class &Lo, Class &Hi, bool isNamedArg) const {
2543
249k
  // FIXME: This code can be simplified by introducing a simple value class for
2544
249k
  // Class pairs with appropriate constructor methods for the various
2545
249k
  // situations.
2546
249k
2547
249k
  // FIXME: Some of the split computations are wrong; unaligned vectors
2548
249k
  // shouldn't be passed in registers for example, so there is no chance they
2549
249k
  // can straddle an eightbyte. Verify & simplify.
2550
249k
2551
249k
  Lo = Hi = NoClass;
2552
249k
2553
249k
  Class &Current = OffsetBase < 64 ? 
Lo248k
:
Hi1.15k
;
2554
249k
  Current = Memory;
2555
249k
2556
249k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2557
111k
    BuiltinType::Kind k = BT->getKind();
2558
111k
2559
111k
    if (k == BuiltinType::Void) {
2560
38.7k
      Current = NoClass;
2561
72.4k
    } else if (k == BuiltinType::Int128 || 
k == BuiltinType::UInt12872.0k
) {
2562
601
      Lo = Integer;
2563
601
      Hi = Integer;
2564
71.8k
    } else if (k >= BuiltinType::Bool && 
k <= BuiltinType::LongLong71.8k
) {
2565
67.9k
      Current = Integer;
2566
67.9k
    } else 
if (3.91k
k == BuiltinType::Float3.91k
||
k == BuiltinType::Double2.29k
) {
2567
3.18k
      Current = SSE;
2568
3.18k
    } else 
if (729
k == BuiltinType::LongDouble729
) {
2569
663
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2570
663
      if (LDF == &llvm::APFloat::IEEEquad()) {
2571
15
        Lo = SSE;
2572
15
        Hi = SSEUp;
2573
648
      } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2574
626
        Lo = X87;
2575
626
        Hi = X87Up;
2576
626
      } else 
if (22
LDF == &llvm::APFloat::IEEEdouble()22
) {
2577
22
        Current = SSE;
2578
22
      } else
2579
22
        
llvm_unreachable0
("unexpected long double representation!");
2580
663
    }
2581
111k
    // FIXME: _Decimal32 and _Decimal64 are SSE.
2582
111k
    // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2583
111k
    return;
2584
138k
  }
2585
138k
2586
138k
  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2587
3.12k
    // Classify the underlying integer type.
2588
3.12k
    classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2589
3.12k
    return;
2590
3.12k
  }
2591
135k
2592
135k
  if (Ty->hasPointerRepresentation()) {
2593
123k
    Current = Integer;
2594
123k
    return;
2595
123k
  }
2596
12.2k
2597
12.2k
  if (Ty->isMemberPointerType()) {
2598
108
    if (Ty->isMemberFunctionPointerType()) {
2599
61
      if (Has64BitPointers) {
2600
53
        // If Has64BitPointers, this is an {i64, i64}, so classify both
2601
53
        // Lo and Hi now.
2602
53
        Lo = Hi = Integer;
2603
53
      } else {
2604
8
        // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2605
8
        // straddles an eightbyte boundary, Hi should be classified as well.
2606
8
        uint64_t EB_FuncPtr = (OffsetBase) / 64;
2607
8
        uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2608
8
        if (EB_FuncPtr != EB_ThisAdj) {
2609
2
          Lo = Hi = Integer;
2610
6
        } else {
2611
6
          Current = Integer;
2612
6
        }
2613
8
      }
2614
61
    } else {
2615
47
      Current = Integer;
2616
47
    }
2617
108
    return;
2618
108
  }
2619
12.1k
2620
12.1k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2621
5.15k
    uint64_t Size = getContext().getTypeSize(VT);
2622
5.15k
    if (Size == 1 || Size == 8 || 
Size == 165.15k
||
Size == 325.15k
) {
2623
5
      // gcc passes the following as integer:
2624
5
      // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2625
5
      // 2 bytes - <2 x char>, <1 x short>
2626
5
      // 1 byte  - <1 x char>
2627
5
      Current = Integer;
2628
5
2629
5
      // If this type crosses an eightbyte boundary, it should be
2630
5
      // split.
2631
5
      uint64_t EB_Lo = (OffsetBase) / 64;
2632
5
      uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2633
5
      if (EB_Lo != EB_Hi)
2634
0
        Hi = Lo;
2635
5.14k
    } else if (Size == 64) {
2636
143
      QualType ElementType = VT->getElementType();
2637
143
2638
143
      // gcc passes <1 x double> in memory. :(
2639
143
      if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2640
0
        return;
2641
143
2642
143
      // gcc passes <1 x long long> as SSE but clang used to unconditionally
2643
143
      // pass them as integer.  For platforms where clang is the de facto
2644
143
      // platform compiler, we must continue to use integer.
2645
143
      if (!classifyIntegerMMXAsSSE() &&
2646
143
          
(86
ElementType->isSpecificBuiltinType(BuiltinType::LongLong)86
||
2647
86
           
ElementType->isSpecificBuiltinType(BuiltinType::ULongLong)9
||
2648
86
           
ElementType->isSpecificBuiltinType(BuiltinType::Long)9
||
2649
86
           
ElementType->isSpecificBuiltinType(BuiltinType::ULong)9
))
2650
77
        Current = Integer;
2651
66
      else
2652
66
        Current = SSE;
2653
143
2654
143
      // If this type crosses an eightbyte boundary, it should be
2655
143
      // split.
2656
143
      if (OffsetBase && 
OffsetBase != 640
)
2657
0
        Hi = Lo;
2658
5.00k
    } else if (Size == 128 ||
2659
5.00k
               
(3.00k
isNamedArg3.00k
&&
Size <= getNativeVectorSizeForAVXABI(AVXLevel)2.98k
)) {
2660
4.92k
      // Arguments of 256-bits are split into four eightbyte chunks. The
2661
4.92k
      // least significant one belongs to class SSE and all the others to class
2662
4.92k
      // SSEUP. The original Lo and Hi design considers that types can't be
2663
4.92k
      // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2664
4.92k
      // This design isn't correct for 256-bits, but since there're no cases
2665
4.92k
      // where the upper parts would need to be inspected, avoid adding
2666
4.92k
      // complexity and just consider Hi to match the 64-256 part.
2667
4.92k
      //
2668
4.92k
      // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2669
4.92k
      // registers if they are "named", i.e. not part of the "..." of a
2670
4.92k
      // variadic function.
2671
4.92k
      //
2672
4.92k
      // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2673
4.92k
      // split into eight eightbyte chunks, one SSE and seven SSEUP.
2674
4.92k
      Lo = SSE;
2675
4.92k
      Hi = SSEUp;
2676
4.92k
    }
2677
5.15k
    return;
2678
6.97k
  }
2679
6.97k
2680
6.97k
  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2681
402
    QualType ET = getContext().getCanonicalType(CT->getElementType());
2682
402
2683
402
    uint64_t Size = getContext().getTypeSize(Ty);
2684
402
    if (ET->isIntegralOrEnumerationType()) {
2685
32
      if (Size <= 64)
2686
30
        Current = Integer;
2687
2
      else if (Size <= 128)
2688
2
        Lo = Hi = Integer;
2689
370
    } else if (ET == getContext().FloatTy) {
2690
136
      Current = SSE;
2691
234
    } else if (ET == getContext().DoubleTy) {
2692
115
      Lo = Hi = SSE;
2693
119
    } else if (ET == getContext().LongDoubleTy) {
2694
119
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2695
119
      if (LDF == &llvm::APFloat::IEEEquad())
2696
8
        Current = Memory;
2697
111
      else if (LDF == &llvm::APFloat::x87DoubleExtended())
2698
103
        Current = ComplexX87;
2699
8
      else if (LDF == &llvm::APFloat::IEEEdouble())
2700
8
        Lo = Hi = SSE;
2701
8
      else
2702
8
        
llvm_unreachable0
("unexpected long double representation!");
2703
119
    }
2704
402
2705
402
    // If this complex type crosses an eightbyte boundary then it
2706
402
    // should be split.
2707
402
    uint64_t EB_Real = (OffsetBase) / 64;
2708
402
    uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2709
402
    if (Hi == NoClass && 
EB_Real != EB_Imag277
)
2710
114
      Hi = Lo;
2711
402
2712
402
    return;
2713
6.57k
  }
2714
6.57k
2715
6.57k
  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2716
77
    // Arrays are treated like structures.
2717
77
2718
77
    uint64_t Size = getContext().getTypeSize(Ty);
2719
77
2720
77
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2721
77
    // than eight eightbytes, ..., it has class MEMORY.
2722
77
    if (Size > 512)
2723
0
      return;
2724
77
2725
77
    // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2726
77
    // fields, it has class MEMORY.
2727
77
    //
2728
77
    // Only need to check alignment of array base.
2729
77
    if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2730
0
      return;
2731
77
2732
77
    // Otherwise implement simplified merge. We could be smarter about
2733
77
    // this, but it isn't worth it and would be harder to verify.
2734
77
    Current = NoClass;
2735
77
    uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2736
77
    uint64_t ArraySize = AT->getSize().getZExtValue();
2737
77
2738
77
    // The only case a 256-bit wide vector could be used is when the array
2739
77
    // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2740
77
    // to work for sizes wider than 128, early check and fallback to memory.
2741
77
    //
2742
77
    if (Size > 128 &&
2743
77
        
(15
Size != EltSize15
||
Size > getNativeVectorSizeForAVXABI(AVXLevel)4
))
2744
11
      return;
2745
66
2746
421
    
for (uint64_t i=0, Offset=OffsetBase; 66
i<ArraySize;
++i, Offset += EltSize355
) {
2747
355
      Class FieldLo, FieldHi;
2748
355
      classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2749
355
      Lo = merge(Lo, FieldLo);
2750
355
      Hi = merge(Hi, FieldHi);
2751
355
      if (Lo == Memory || Hi == Memory)
2752
0
        break;
2753
355
    }
2754
66
2755
66
    postMerge(Size, Lo, Hi);
2756
66
    assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2757
66
    return;
2758
66
  }
2759
6.49k
2760
6.49k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2761
6.48k
    uint64_t Size = getContext().getTypeSize(Ty);
2762
6.48k
2763
6.48k
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2764
6.48k
    // than eight eightbytes, ..., it has class MEMORY.
2765
6.48k
    if (Size > 512)
2766
209
      return;
2767
6.28k
2768
6.28k
    // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2769
6.28k
    // copy constructor or a non-trivial destructor, it is passed by invisible
2770
6.28k
    // reference.
2771
6.28k
    if (getRecordArgABI(RT, getCXXABI()))
2772
221
      return;
2773
6.05k
2774
6.05k
    const RecordDecl *RD = RT->getDecl();
2775
6.05k
2776
6.05k
    // Assume variable sized types are passed in memory.
2777
6.05k
    if (RD->hasFlexibleArrayMember())
2778
0
      return;
2779
6.05k
2780
6.05k
    const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2781
6.05k
2782
6.05k
    // Reset Lo class, this will be recomputed.
2783
6.05k
    Current = NoClass;
2784
6.05k
2785
6.05k
    // If this is a C++ record, classify the bases first.
2786
6.05k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2787
5.69k
      for (const auto &I : CXXRD->bases()) {
2788
651
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2789
651
               "Unexpected base class!");
2790
651
        const CXXRecordDecl *Base =
2791
651
          cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2792
651
2793
651
        // Classify this field.
2794
651
        //
2795
651
        // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2796
651
        // single eightbyte, each is classified separately. Each eightbyte gets
2797
651
        // initialized to class NO_CLASS.
2798
651
        Class FieldLo, FieldHi;
2799
651
        uint64_t Offset =
2800
651
          OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2801
651
        classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2802
651
        Lo = merge(Lo, FieldLo);
2803
651
        Hi = merge(Hi, FieldHi);
2804
651
        if (Lo == Memory || 
Hi == Memory645
) {
2805
6
          postMerge(Size, Lo, Hi);
2806
6
          return;
2807
6
        }
2808
651
      }
2809
5.69k
    }
2810
6.05k
2811
6.05k
    // Classify the fields one at a time, merging the results.
2812
6.05k
    unsigned idx = 0;
2813
6.05k
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2814
10.4k
           i != e; 
++i, ++idx4.42k
) {
2815
4.78k
      uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2816
4.78k
      bool BitField = i->isBitField();
2817
4.78k
2818
4.78k
      // Ignore padding bit-fields.
2819
4.78k
      if (BitField && 
i->isUnnamedBitfield()66
)
2820
12
        continue;
2821
4.77k
2822
4.77k
      // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2823
4.77k
      // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2824
4.77k
      //
2825
4.77k
      // The only case a 256-bit wide vector could be used is when the struct
2826
4.77k
      // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2827
4.77k
      // to work for sizes wider than 128, early check and fallback to memory.
2828
4.77k
      //
2829
4.77k
      if (Size > 128 && 
(373
Size != getContext().getTypeSize(i->getType())373
||
2830
373
                         
Size > getNativeVectorSizeForAVXABI(AVXLevel)71
)) {
2831
347
        Lo = Memory;
2832
347
        postMerge(Size, Lo, Hi);
2833
347
        return;
2834
347
      }
2835
4.42k
      // Note, skip this test for bit-fields, see below.
2836
4.42k
      if (!BitField && 
Offset % getContext().getTypeAlign(i->getType())4.36k
) {
2837
2
        Lo = Memory;
2838
2
        postMerge(Size, Lo, Hi);
2839
2
        return;
2840
2
      }
2841
4.42k
2842
4.42k
      // Classify this field.
2843
4.42k
      //
2844
4.42k
      // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2845
4.42k
      // exceeds a single eightbyte, each is classified
2846
4.42k
      // separately. Each eightbyte gets initialized to class
2847
4.42k
      // NO_CLASS.
2848
4.42k
      Class FieldLo, FieldHi;
2849
4.42k
2850
4.42k
      // Bit-fields require special handling, they do not force the
2851
4.42k
      // structure to be passed in memory even if unaligned, and
2852
4.42k
      // therefore they can straddle an eightbyte.
2853
4.42k
      if (BitField) {
2854
54
        assert(!i->isUnnamedBitfield());
2855
54
        uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2856
54
        uint64_t Size = i->getBitWidthValue(getContext());
2857
54
2858
54
        uint64_t EB_Lo = Offset / 64;
2859
54
        uint64_t EB_Hi = (Offset + Size - 1) / 64;
2860
54
2861
54
        if (EB_Lo) {
2862
0
          assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2863
0
          FieldLo = NoClass;
2864
0
          FieldHi = Integer;
2865
54
        } else {
2866
54
          FieldLo = Integer;
2867
54
          FieldHi = EB_Hi ? 
Integer0
: NoClass;
2868
54
        }
2869
54
      } else
2870
4.36k
        classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2871
4.42k
      Lo = merge(Lo, FieldLo);
2872
4.42k
      Hi = merge(Hi, FieldHi);
2873
4.42k
      if (Lo == Memory || 
Hi == Memory4.41k
)
2874
10
        break;
2875
4.42k
    }
2876
6.05k
2877
6.05k
    postMerge(Size, Lo, Hi);
2878
5.70k
  }
2879
6.49k
}
2880
2881
294
ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2882
294
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2883
294
  // place naturally.
2884
294
  if (!isAggregateTypeForABI(Ty)) {
2885
42
    // Treat an enum type as its underlying type.
2886
42
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2887
0
      Ty = EnumTy->getDecl()->getIntegerType();
2888
42
2889
42
    return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)0
2890
42
                                          : ABIArgInfo::getDirect());
2891
42
  }
2892
252
2893
252
  return getNaturalAlignIndirect(Ty);
2894
252
}
2895
2896
2.80k
bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2897
2.80k
  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2898
66
    uint64_t Size = getContext().getTypeSize(VecTy);
2899
66
    unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2900
66
    if (Size <= 64 || 
Size > LargestVector60
)
2901
54
      return true;
2902
2.74k
  }
2903
2.74k
2904
2.74k
  return false;
2905
2.74k
}
2906
2907
ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2908
3.44k
                                            unsigned freeIntRegs) const {
2909
3.44k
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2910
3.44k
  // place naturally.
2911
3.44k
  //
2912
3.44k
  // This assumption is optimistic, as there could be free registers available
2913
3.44k
  // when we need to pass this argument in memory, and LLVM could try to pass
2914
3.44k
  // the argument in the free register. This does not seem to happen currently,
2915
3.44k
  // but this code would be much safer if we could mark the argument with
2916
3.44k
  // 'onstack'. See PR12193.
2917
3.44k
  if (!isAggregateTypeForABI(Ty) && 
!IsIllegalVectorType(Ty)2.80k
) {
2918
2.74k
    // Treat an enum type as its underlying type.
2919
2.74k
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2920
72
      Ty = EnumTy->getDecl()->getIntegerType();
2921
2.74k
2922
2.74k
    return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)367
2923
2.74k
                                          : 
ABIArgInfo::getDirect()2.38k
);
2924
2.74k
  }
2925
701
2926
701
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2927
237
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2928
464
2929
464
  // Compute the byval alignment. We specify the alignment of the byval in all
2930
464
  // cases so that the mid-level optimizer knows the alignment of the byval.
2931
464
  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2932
464
2933
464
  // Attempt to avoid passing indirect results using byval when possible. This
2934
464
  // is important for good codegen.
2935
464
  //
2936
464
  // We do this by coercing the value into a scalar type which the backend can
2937
464
  // handle naturally (i.e., without using byval).
2938
464
  //
2939
464
  // For simplicity, we currently only do this when we have exhausted all of the
2940
464
  // free integer registers. Doing this when there are free integer registers
2941
464
  // would require more care, as we would have to ensure that the coerced value
2942
464
  // did not claim the unused register. That would require either reording the
2943
464
  // arguments to the function (so that any subsequent inreg values came first),
2944
464
  // or only doing this optimization when there were no following arguments that
2945
464
  // might be inreg.
2946
464
  //
2947
464
  // We currently expect it to be rare (particularly in well written code) for
2948
464
  // arguments to be passed on the stack when there are still free integer
2949
464
  // registers available (this would typically imply large structs being passed
2950
464
  // by value), so this seems like a fair tradeoff for now.
2951
464
  //
2952
464
  // We can revisit this if the backend grows support for 'onstack' parameter
2953
464
  // attributes. See PR12193.
2954
464
  if (freeIntRegs == 0) {
2955
40
    uint64_t Size = getContext().getTypeSize(Ty);
2956
40
2957
40
    // If this type fits in an eightbyte, coerce it into the matching integral
2958
40
    // type, which will end up on the stack (with alignment 8).
2959
40
    if (Align == 8 && 
Size <= 6430
)
2960
19
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2961
19
                                                          Size));
2962
445
  }
2963
445
2964
445
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2965
445
}
2966
2967
/// The ABI specifies that a value should be passed in a full vector XMM/YMM
2968
/// register. Pick an LLVM IR type that will be passed as a vector register.
2969
4.93k
llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2970
4.93k
  // Wrapper structs/arrays that only contain vectors are passed just like
2971
4.93k
  // vectors; strip them off if present.
2972
4.93k
  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2973
25
    Ty = QualType(InnerTy, 0);
2974
4.93k
2975
4.93k
  llvm::Type *IRType = CGT.ConvertType(Ty);
2976
4.93k
  if (isa<llvm::VectorType>(IRType) ||
2977
4.93k
      
IRType->getTypeID() == llvm::Type::FP128TyID15
)
2978
4.93k
    return IRType;
2979
0
2980
0
  // We couldn't find the preferred IR vector type for 'Ty'.
2981
0
  uint64_t Size = getContext().getTypeSize(Ty);
2982
0
  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2983
0
2984
0
  // Return a LLVM IR vector type based on the size of 'Ty'.
2985
0
  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2986
0
                               Size / 64);
2987
0
}
2988
2989
/// BitsContainNoUserData - Return true if the specified [start,end) bit range
2990
/// is known to either be off the end of the specified type or being in
2991
/// alignment padding.  The user type specified is known to be at most 128 bits
2992
/// in size, and have passed through X86_64ABIInfo::classify with a successful
2993
/// classification that put one of the two halves in the INTEGER class.
2994
///
2995
/// It is conservatively correct to return false.
2996
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2997
40.0k
                                  unsigned EndBit, ASTContext &Context) {
2998
40.0k
  // If the bytes being queried are off the end of the type, there is no user
2999
40.0k
  // data hiding here.  This handles analysis of builtins, vectors and other
3000
40.0k
  // types that don't contain interesting padding.
3001
40.0k
  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3002
40.0k
  if (TySize <= StartBit)
3003
31.9k
    return true;
3004
8.10k
3005
8.10k
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3006
44
    unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3007
44
    unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3008
44
3009
44
    // Check each element to see if the element overlaps with the queried range.
3010
197
    for (unsigned i = 0; i != NumElts; 
++i153
) {
3011
194
      // If the element is after the span we care about, then we're done..
3012
194
      unsigned EltOffset = i*EltSize;
3013
194
      if (EltOffset >= EndBit) 
break0
;
3014
194
3015
194
      unsigned EltStart = EltOffset < StartBit ? 
StartBit-EltOffset160
:
034
;
3016
194
      if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3017
194
                                 EndBit-EltOffset, Context))
3018
41
        return false;
3019
194
    }
3020
44
    // If it overlaps no elements, then it is safe to process as padding.
3021
44
    
return true3
;
3022
8.05k
  }
3023
8.05k
3024
8.05k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3025
653
    const RecordDecl *RD = RT->getDecl();
3026
653
    const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3027
653
3028
653
    // If this is a C++ record, check the bases first.
3029
653
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3030
472
      for (const auto &I : CXXRD->bases()) {
3031
27
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3032
27
               "Unexpected base class!");
3033
27
        const CXXRecordDecl *Base =
3034
27
          cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3035
27
3036
27
        // If the base is after the span we care about, ignore it.
3037
27
        unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3038
27
        if (BaseOffset >= EndBit) 
continue2
;
3039
25
3040
25
        unsigned BaseStart = BaseOffset < StartBit ? 
StartBit-BaseOffset21
:
04
;
3041
25
        if (!BitsContainNoUserData(I.getType(), BaseStart,
3042
25
                                   EndBit-BaseOffset, Context))
3043
7
          return false;
3044
25
      }
3045
472
    }
3046
653
3047
653
    // Verify that no field has data that overlaps the region of interest.  Yes
3048
653
    // this could be sped up a lot by being smarter about queried fields,
3049
653
    // however we're only looking at structs up to 16 bytes, so we don't care
3050
653
    // much.
3051
653
    unsigned idx = 0;
3052
646
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3053
1.56k
         i != e; 
++i, ++idx916
) {
3054
1.40k
      unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3055
1.40k
3056
1.40k
      // If we found a field after the region we care about, then we're done.
3057
1.40k
      if (FieldOffset >= EndBit) 
break13
;
3058
1.39k
3059
1.39k
      unsigned FieldStart = FieldOffset < StartBit ? 
StartBit-FieldOffset1.02k
:
0362
;
3060
1.39k
      if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3061
1.39k
                                 Context))
3062
475
        return false;
3063
1.39k
    }
3064
646
3065
646
    // If nothing in this record overlapped the area of interest, then we're
3066
646
    // clean.
3067
646
    
return true171
;
3068
7.40k
  }
3069
7.40k
3070
7.40k
  return false;
3071
7.40k
}
3072
3073
/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3074
/// float member at the specified offset.  For example, {int,{float}} has a
3075
/// float at offset 4.  It is conservatively correct for this routine to return
3076
/// false.
3077
static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3078
7.93k
                                  const llvm::DataLayout &TD) {
3079
7.93k
  // Base case if we find a float.
3080
7.93k
  if (IROffset == 0 && 
IRType->isFloatTy()7.58k
)
3081
384
    return true;
3082
7.54k
3083
7.54k
  // If this is a struct, recurse into the field at the specified offset.
3084
7.54k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3085
694
    const llvm::StructLayout *SL = TD.getStructLayout(STy);
3086
694
    unsigned Elt = SL->getElementContainingOffset(IROffset);
3087
694
    IROffset -= SL->getElementOffset(Elt);
3088
694
    return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3089
694
  }
3090
6.85k
3091
6.85k
  // If this is an array, recurse into the field at the specified offset.
3092
6.85k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3093
17
    llvm::Type *EltTy = ATy->getElementType();
3094
17
    unsigned EltSize = TD.getTypeAllocSize(EltTy);
3095
17
    IROffset -= IROffset/EltSize*EltSize;
3096
17
    return ContainsFloatAtOffset(EltTy, IROffset, TD);
3097
17
  }
3098
6.83k
3099
6.83k
  return false;
3100
6.83k
}
3101
3102
3103
/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3104
/// low 8 bytes of an XMM register, corresponding to the SSE class.
3105
llvm::Type *X86_64ABIInfo::
3106
GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3107
8.51k
                   QualType SourceTy, unsigned SourceOffset) const {
3108
8.51k
  // The only three choices we have are either double, <2 x float>, or float. We
3109
8.51k
  // pass as float if the last 4 bytes is just padding.  This happens for
3110
8.51k
  // structs that contain 3 floats.
3111
8.51k
  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3112
8.51k
                            SourceOffset*8+64, getContext()))
3113
1.49k
    return llvm::Type::getFloatTy(getVMContext());
3114
7.02k
3115
7.02k
  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3116
7.02k
  // offset+0 and offset+4.  Walk the LLVM IR type to find out if this is the
3117
7.02k
  // case.
3118
7.02k
  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3119
7.02k
      
ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())192
)
3120
192
    return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3121
6.83k
3122
6.83k
  return llvm::Type::getDoubleTy(getVMContext());
3123
6.83k
}
3124
3125
3126
/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3127
/// an 8-byte GPR.  This means that we either have a scalar or we are talking
3128
/// about the high or low part of an up-to-16-byte struct.  This routine picks
3129
/// the best LLVM IR type to represent this, which may be i64 or may be anything
3130
/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3131
/// etc).
3132
///
3133
/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3134
/// the source type.  IROffset is an offset in bytes into the LLVM IR type that
3135
/// the 8-byte value references.  PrefType may be null.
3136
///
3137
/// SourceTy is the source-level type for the entire argument.  SourceOffset is
3138
/// an offset into this that we're processing (which is always either 0 or 8).
3139
///
3140
llvm::Type *X86_64ABIInfo::
3141
GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3142
196k
                       QualType SourceTy, unsigned SourceOffset) const {
3143
196k
  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3144
196k
  // returning an 8-byte unit starting with it.  See if we can safely use it.
3145
196k
  if (IROffset == 0) {
3146
194k
    // Pointers and int64's always fill the 8-byte unit.
3147
194k
    if ((isa<llvm::PointerType>(IRType) && 
Has64BitPointers123k
) ||
3148
194k
        
IRType->isIntegerTy(64)71.6k
)
3149
154k
      return IRType;
3150
40.4k
3151
40.4k
    // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3152
40.4k
    // goodness in the source type is just tail padding.  This is allowed to
3153
40.4k
    // kick in for struct {double,int} on the int, but not on
3154
40.4k
    // struct{double,int,int} because we wouldn't return the second int.  We
3155
40.4k
    // have to do this analysis on the source type because we can't depend on
3156
40.4k
    // unions being lowered a specific way etc.
3157
40.4k
    if (IRType->isIntegerTy(8) || 
IRType->isIntegerTy(16)37.3k
||
3158
40.4k
        
IRType->isIntegerTy(32)36.5k
||
3159
40.4k
        
(10.5k
isa<llvm::PointerType>(IRType)10.5k
&&
!Has64BitPointers88
)) {
3160
29.9k
      unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 
3288
:
3161
29.9k
          
cast<llvm::IntegerType>(IRType)->getBitWidth()29.8k
;
3162
29.9k
3163
29.9k
      if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3164
29.9k
                                SourceOffset*8+64, getContext()))
3165
29.5k
        return IRType;
3166
12.3k
    }
3167
40.4k
  }
3168
12.3k
3169
12.3k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3170
4.10k
    // If this is a struct, recurse into the field at the specified offset.
3171
4.10k
    const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3172
4.10k
    if (IROffset < SL->getSizeInBytes()) {
3173
4.10k
      unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3174
4.10k
      IROffset -= SL->getElementOffset(FieldIdx);
3175
4.10k
3176
4.10k
      return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3177
4.10k
                                    SourceTy, SourceOffset);
3178
4.10k
    }
3179
8.22k
  }
3180
8.22k
3181
8.22k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3182
86
    llvm::Type *EltTy = ATy->getElementType();
3183
86
    unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3184
86
    unsigned EltOffset = IROffset/EltSize*EltSize;
3185
86
    return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3186
86
                                  SourceOffset);
3187
86
  }
3188
8.13k
3189
8.13k
  // Okay, we don't have any better idea of what to pass, so we pass this in an
3190
8.13k
  // integer register that isn't too big to fit the rest of the struct.
3191
8.13k
  unsigned TySizeInBytes =
3192
8.13k
    (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3193
8.13k
3194
8.13k
  assert(TySizeInBytes != SourceOffset && "Empty field?");
3195
8.13k
3196
8.13k
  // It is always safe to classify this as an integer type up to i64 that
3197
8.13k
  // isn't larger than the structure.
3198
8.13k
  return llvm::IntegerType::get(getVMContext(),
3199
8.13k
                                std::min(TySizeInBytes-SourceOffset, 8U)*8);
3200
8.13k
}
3201
3202
3203
/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3204
/// be used as elements of a two register pair to pass or return, return a
3205
/// first class aggregate to represent them.  For example, if the low part of
3206
/// a by-value argument should be passed as i32* and the high part as float,
3207
/// return {i32*, float}.
3208
static llvm::Type *
3209
GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3210
1.52k
                           const llvm::DataLayout &TD) {
3211
1.52k
  // In order to correctly satisfy the ABI, we need to the high part to start
3212
1.52k
  // at offset 8.  If the high and low parts we inferred are both 4-byte types
3213
1.52k
  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3214
1.52k
  // the second element at offset 8.  Check for this:
3215
1.52k
  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3216
1.52k
  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3217
1.52k
  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3218
1.52k
  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3219
1.52k
3220
1.52k
  // To handle this, we have to increase the size of the low part so that the
3221
1.52k
  // second element will start at an 8 byte offset.  We can't increase the size
3222
1.52k
  // of the second element because it might make us access off the end of the
3223
1.52k
  // struct.
3224
1.52k
  if (HiStart != 8) {
3225
5
    // There are usually two sorts of types the ABI generation code can produce
3226
5
    // for the low part of a pair that aren't 8 bytes in size: float or
3227
5
    // i8/i16/i32.  This can also include pointers when they are 32-bit (X32 and
3228
5
    // NaCl).
3229
5
    // Promote these to a larger type.
3230
5
    if (Lo->isFloatTy())
3231
0
      Lo = llvm::Type::getDoubleTy(Lo->getContext());
3232
5
    else {
3233
5
      assert((Lo->isIntegerTy() || Lo->isPointerTy())
3234
5
             && "Invalid/unknown lo type");
3235
5
      Lo = llvm::Type::getInt64Ty(Lo->getContext());
3236
5
    }
3237
5
  }
3238
1.52k
3239
1.52k
  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3240
1.52k
3241
1.52k
  // Verify that the second element is at an 8-byte offset.
3242
1.52k
  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3243
1.52k
         "Invalid x86-64 argument pair!");
3244
1.52k
  return Result;
3245
1.52k
}
3246
3247
ABIArgInfo X86_64ABIInfo::
3248
83.7k
classifyReturnType(QualType RetTy) const {
3249
83.7k
  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3250
83.7k
  // classification algorithm.
3251
83.7k
  X86_64ABIInfo::Class Lo, Hi;
3252
83.7k
  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3253
83.7k
3254
83.7k
  // Check some invariants.
3255
83.7k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3256
83.7k
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3257
83.7k
3258
83.7k
  llvm::Type *ResType = nullptr;
3259
83.7k
  switch (Lo) {
3260
83.7k
  case NoClass:
3261
39.0k
    if (Hi == NoClass)
3262
39.0k
      return ABIArgInfo::getIgnore();
3263
1
    // If the low part is just padding, it takes no register, leave ResType
3264
1
    // null.
3265
1
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3266
1
           "Unknown missing lo part");
3267
1
    break;
3268
1
3269
1
  case SSEUp:
3270
0
  case X87Up:
3271
0
    llvm_unreachable("Invalid classification for lo word.");
3272
0
3273
0
    // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3274
0
    // hidden argument.
3275
293
  case Memory:
3276
293
    return getIndirectReturnResult(RetTy);
3277
0
3278
0
    // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3279
0
    // available register of the sequence %rax, %rdx is used.
3280
41.2k
  case Integer:
3281
41.2k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3282
41.2k
3283
41.2k
    // If we have a sign or zero extended integer, make sure to return Extend
3284
41.2k
    // so that the parameter gets the right LLVM IR attributes.
3285
41.2k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)40.6k
) {
3286
21.8k
      // Treat an enum type as its underlying type.
3287
21.8k
      if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3288
343
        RetTy = EnumTy->getDecl()->getIntegerType();
3289
21.8k
3290
21.8k
      if (RetTy->isIntegralOrEnumerationType() &&
3291
21.8k
          
RetTy->isPromotableIntegerType()21.6k
)
3292
5.39k
        return ABIArgInfo::getExtend(RetTy);
3293
35.8k
    }
3294
35.8k
    break;
3295
35.8k
3296
35.8k
    // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3297
35.8k
    // available SSE register of the sequence %xmm0, %xmm1 is used.
3298
35.8k
  case SSE:
3299
2.94k
    ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3300
2.94k
    break;
3301
35.8k
3302
35.8k
    // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3303
35.8k
    // returned on the X87 stack in %st0 as 80-bit x87 number.
3304
35.8k
  case X87:
3305
203
    ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3306
203
    break;
3307
35.8k
3308
35.8k
    // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3309
35.8k
    // part of the value is returned in %st0 and the imaginary part in
3310
35.8k
    // %st1.
3311
35.8k
  case ComplexX87:
3312
53
    assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3313
53
    ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3314
53
                                    llvm::Type::getX86_FP80Ty(getVMContext()));
3315
53
    break;
3316
39.0k
  }
3317
39.0k
3318
39.0k
  llvm::Type *HighPart = nullptr;
3319
39.0k
  switch (Hi) {
3320
39.0k
    // Memory was handled previously and X87 should
3321
39.0k
    // never occur as a hi class.
3322
39.0k
  case Memory:
3323
0
  case X87:
3324
0
    llvm_unreachable("Invalid classification for hi word.");
3325
0
3326
36.3k
  case ComplexX87: // Previously handled.
3327
36.3k
  case NoClass:
3328
36.3k
    break;
3329
36.3k
3330
36.3k
  case Integer:
3331
557
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3332
557
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3333
0
      return ABIArgInfo::getDirect(HighPart, 8);
3334
557
    break;
3335
557
  case SSE:
3336
55
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3337
55
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3338
1
      return ABIArgInfo::getDirect(HighPart, 8);
3339
54
    break;
3340
54
3341
54
    // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3342
54
    // is passed in the next available eightbyte chunk if the last used
3343
54
    // vector register.
3344
54
    //
3345
54
    // SSEUP should always be preceded by SSE, just widen.
3346
1.82k
  case SSEUp:
3347
1.82k
    assert(Lo == SSE && "Unexpected SSEUp classification.");
3348
1.82k
    ResType = GetByteVectorType(RetTy);
3349
1.82k
    break;
3350
54
3351
54
    // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3352
54
    // returned together with the previous X87 value in %st0.
3353
203
  case X87Up:
3354
203
    // If X87Up is preceded by X87, we don't need to do
3355
203
    // anything. However, in some cases with unions it may not be
3356
203
    // preceded by X87. In such situations we follow gcc and pass the
3357
203
    // extra bits in an SSE reg.
3358
203
    if (Lo != X87) {
3359
0
      HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3360
0
      if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3361
0
        return ABIArgInfo::getDirect(HighPart, 8);
3362
203
    }
3363
203
    break;
3364
39.0k
  }
3365
39.0k
3366
39.0k
  // If a high part was specified, merge it together with the low part.  It is
3367
39.0k
  // known to pass in the high eightbyte of the result.  We do this by forming a
3368
39.0k
  // first class struct aggregate with the high and low part: {low, high}
3369
39.0k
  if (HighPart)
3370
611
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3371
39.0k
3372
39.0k
  return ABIArgInfo::getDirect(ResType);
3373
39.0k
}
3374
3375
ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3376
  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3377
  bool isNamedArg)
3378
  const
3379
157k
{
3380
157k
  Ty = useFirstFieldIfTransparentUnion(Ty);
3381
157k
3382
157k
  X86_64ABIInfo::Class Lo, Hi;
3383
157k
  classify(Ty, 0, Lo, Hi, isNamedArg);
3384
157k
3385
157k
  // Check some invariants.
3386
157k
  // FIXME: Enforce these by construction.
3387
157k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3388
157k
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3389
157k
3390
157k
  neededInt = 0;
3391
157k
  neededSSE = 0;
3392
157k
  llvm::Type *ResType = nullptr;
3393
157k
  switch (Lo) {
3394
157k
  case NoClass:
3395
1.54k
    if (Hi == NoClass)
3396
1.53k
      return ABIArgInfo::getIgnore();
3397
2
    // If the low part is just padding, it takes no register, leave ResType
3398
2
    // null.
3399
2
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3400
2
           "Unknown missing lo part");
3401
2
    break;
3402
2
3403
2
    // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3404
2
    // on the stack.
3405
1.12k
  case Memory:
3406
1.12k
3407
1.12k
    // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3408
1.12k
    // COMPLEX_X87, it is passed in memory.
3409
1.12k
  case X87:
3410
1.12k
  case ComplexX87:
3411
1.12k
    if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3412
237
      ++neededInt;
3413
1.12k
    return getIndirectResult(Ty, freeIntRegs);
3414
1.12k
3415
1.12k
  case SSEUp:
3416
0
  case X87Up:
3417
0
    llvm_unreachable("Invalid classification for lo word.");
3418
0
3419
0
    // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3420
0
    // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3421
0
    // and %r9 is used.
3422
149k
  case Integer:
3423
149k
    ++neededInt;
3424
149k
3425
149k
    // Pick an 8-byte type based on the preferred type.
3426
149k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3427
149k
3428
149k
    // If we have a sign or zero extended integer, make sure to return Extend
3429
149k
    // so that the parameter gets the right LLVM IR attributes.
3430
149k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)148k
) {
3431
44.9k
      // Treat an enum type as its underlying type.
3432
44.9k
      if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3433
2.77k
        Ty = EnumTy->getDecl()->getIntegerType();
3434
44.9k
3435
44.9k
      if (Ty->isIntegralOrEnumerationType() &&
3436
44.9k
          
Ty->isPromotableIntegerType()44.6k
)
3437
4.80k
        return ABIArgInfo::getExtend(Ty);
3438
144k
    }
3439
144k
3440
144k
    break;
3441
144k
3442
144k
    // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3443
144k
    // available SSE register is used, the registers are taken in the
3444
144k
    // order from %xmm0 to %xmm7.
3445
144k
  case SSE: {
3446
5.42k
    llvm::Type *IRType = CGT.ConvertType(Ty);
3447
5.42k
    ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3448
5.42k
    ++neededSSE;
3449
5.42k
    break;
3450
149k
  }
3451
149k
  }
3452
149k
3453
149k
  llvm::Type *HighPart = nullptr;
3454
149k
  switch (Hi) {
3455
149k
    // Memory was handled previously, ComplexX87 and X87 should
3456
149k
    // never occur as hi classes, and X87Up must be preceded by X87,
3457
149k
    // which is passed in memory.
3458
149k
  case Memory:
3459
0
  case X87:
3460
0
  case ComplexX87:
3461
0
    llvm_unreachable("Invalid classification for hi word.");
3462
0
3463
145k
  case NoClass: break;
3464
0
3465
820
  case Integer:
3466
820
    ++neededInt;
3467
820
    // Pick an 8-byte type based on the preferred type.
3468
820
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3469
820
3470
820
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3471
2
      return ABIArgInfo::getDirect(HighPart, 8);
3472
818
    break;
3473
818
3474
818
    // X87Up generally doesn't occur here (long double is passed in
3475
818
    // memory), except in situations involving unions.
3476
818
  case X87Up:
3477
91
  case SSE:
3478
91
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3479
91
3480
91
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3481
0
      return ABIArgInfo::getDirect(HighPart, 8);
3482
91
3483
91
    ++neededSSE;
3484
91
    break;
3485
91
3486
91
    // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3487
91
    // eightbyte is passed in the upper half of the last used SSE
3488
91
    // register.  This only happens when 128-bit vectors are passed.
3489
3.11k
  case SSEUp:
3490
3.11k
    assert(Lo == SSE && "Unexpected SSEUp classification");
3491
3.11k
    ResType = GetByteVectorType(Ty);
3492
3.11k
    break;
3493
149k
  }
3494
149k
3495
149k
  // If a high part was specified, merge it together with the low part.  It is
3496
149k
  // known to pass in the high eightbyte of the result.  We do this by forming a
3497
149k
  // first class struct aggregate with the high and low part: {low, high}
3498
149k
  if (HighPart)
3499
909
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3500
149k
3501
149k
  return ABIArgInfo::getDirect(ResType);
3502
149k
}
3503
3504
ABIArgInfo
3505
X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3506
18
                                             unsigned &NeededSSE) const {
3507
18
  auto RT = Ty->getAs<RecordType>();
3508
18
  assert(RT && "classifyRegCallStructType only valid with struct types");
3509
18
3510
18
  if (RT->getDecl()->hasFlexibleArrayMember())
3511
0
    return getIndirectReturnResult(Ty);
3512
18
3513
18
  // Sum up bases
3514
18
  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3515
0
    if (CXXRD->isDynamicClass()) {
3516
0
      NeededInt = NeededSSE = 0;
3517
0
      return getIndirectReturnResult(Ty);
3518
0
    }
3519
0
3520
0
    for (const auto &I : CXXRD->bases())
3521
0
      if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3522
0
              .isIndirect()) {
3523
0
        NeededInt = NeededSSE = 0;
3524
0
        return getIndirectReturnResult(Ty);
3525
0
      }
3526
0
  }
3527
18
3528
18
  // Sum up members
3529
44
  
for (const auto *FD : RT->getDecl()->fields())18
{
3530
44
    if (FD->getType()->isRecordType() && 
!FD->getType()->isUnionType()0
) {
3531
0
      if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3532
0
              .isIndirect()) {
3533
0
        NeededInt = NeededSSE = 0;
3534
0
        return getIndirectReturnResult(Ty);
3535
0
      }
3536
44
    } else {
3537
44
      unsigned LocalNeededInt, LocalNeededSSE;
3538
44
      if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3539
44
                               LocalNeededSSE, true)
3540
44
              .isIndirect()) {
3541
0
        NeededInt = NeededSSE = 0;
3542
0
        return getIndirectReturnResult(Ty);
3543
0
      }
3544
44
      NeededInt += LocalNeededInt;
3545
44
      NeededSSE += LocalNeededSSE;
3546
44
    }
3547
44
  }
3548
18
3549
18
  return ABIArgInfo::getDirect();
3550
18
}
3551
3552
ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3553
                                                    unsigned &NeededInt,
3554
18
                                                    unsigned &NeededSSE) const {
3555
18
3556
18
  NeededInt = 0;
3557
18
  NeededSSE = 0;
3558
18
3559
18
  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3560
18
}
3561
3562
84.3k
void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3563
84.3k
3564
84.3k
  const unsigned CallingConv = FI.getCallingConvention();
3565
84.3k
  // It is possible to force Win64 calling convention on any x86_64 target by
3566
84.3k
  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3567
84.3k
  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3568
84.3k
  if (CallingConv == llvm::CallingConv::Win64) {
3569
11
    WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
3570
11
    Win64ABIInfo.computeInfo(FI);
3571
11
    return;
3572
11
  }
3573
84.3k
3574
84.3k
  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3575
84.3k
3576
84.3k
  // Keep track of the number of assigned registers.
3577
84.3k
  unsigned FreeIntRegs = IsRegCall ? 
1123
:
684.2k
;
3578
84.3k
  unsigned FreeSSERegs = IsRegCall ? 
1623
:
884.2k
;
3579
84.3k
  unsigned NeededInt, NeededSSE;
3580
84.3k
3581
84.3k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3582
83.7k
    if (IsRegCall && 
FI.getReturnType()->getTypePtr()->isRecordType()22
&&
3583
83.7k
        
!FI.getReturnType()->getTypePtr()->isUnionType()2
) {
3584
2
      FI.getReturnInfo() =
3585
2
          classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3586
2
      if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3587
2
        FreeIntRegs -= NeededInt;
3588
2
        FreeSSERegs -= NeededSSE;
3589
2
      } else {
3590
0
        FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3591
0
      }
3592
83.7k
    } else if (IsRegCall && 
FI.getReturnType()->getAs<ComplexType>()20
) {
3593
1
      // Complex Long Double Type is passed in Memory when Regcall
3594
1
      // calling convention is used.
3595
1
      const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3596
1
      if (getContext().getCanonicalType(CT->getElementType()) ==
3597
1
          getContext().LongDoubleTy)
3598
1
        FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3599
1
    } else
3600
83.7k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3601
83.7k
  }
3602
84.3k
3603
84.3k
  // If the return value is indirect, then the hidden argument is consuming one
3604
84.3k
  // integer register.
3605
84.3k
  if (FI.getReturnInfo().isIndirect())
3606
835
    --FreeIntRegs;
3607
84.3k
3608
84.3k
  // The chain argument effectively gives us another free register.
3609
84.3k
  if (FI.isChainCall())
3610
4
    ++FreeIntRegs;
3611
84.3k
3612
84.3k
  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3613
84.3k
  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3614
84.3k
  // get assigned (in left-to-right order) for passing as follows...
3615
84.3k
  unsigned ArgNo = 0;
3616
84.3k
  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3617
241k
       it != ie; 
++it, ++ArgNo157k
) {
3618
157k
    bool IsNamedArg = ArgNo < NumRequiredArgs;
3619
157k
3620
157k
    if (IsRegCall && 
it->type->isStructureOrClassType()53
)
3621
16
      it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3622
157k
    else
3623
157k
      it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3624
157k
                                      NeededSSE, IsNamedArg);
3625
157k
3626
157k
    // AMD64-ABI 3.2.3p3: If there are no registers available for any
3627
157k
    // eightbyte of an argument, the whole argument is passed on the
3628
157k
    // stack. If registers have already been assigned for some
3629
157k
    // eightbytes of such an argument, the assignments get reverted.
3630
157k
    if (FreeIntRegs >= NeededInt && 
FreeSSERegs >= NeededSSE154k
) {
3631
154k
      FreeIntRegs -= NeededInt;
3632
154k
      FreeSSERegs -= NeededSSE;
3633
154k
    } else {
3634
2.32k
      it->info = getIndirectResult(it->type, FreeIntRegs);
3635
2.32k
    }
3636
157k
  }
3637
84.3k
}
3638
3639
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3640
249
                                         Address VAListAddr, QualType Ty) {
3641
249
  Address overflow_arg_area_p =
3642
249
      CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
3643
249
  llvm::Value *overflow_arg_area =
3644
249
    CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3645
249
3646
249
  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3647
249
  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3648
249
  // It isn't stated explicitly in the standard, but in practice we use
3649
249
  // alignment greater than 16 where necessary.
3650
249
  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3651
249
  if (Align > CharUnits::fromQuantity(8)) {
3652
36
    overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3653
36
                                                      Align);
3654
36
  }
3655
249
3656
249
  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3657
249
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3658
249
  llvm::Value *Res =
3659
249
    CGF.Builder.CreateBitCast(overflow_arg_area,
3660
249
                              llvm::PointerType::getUnqual(LTy));
3661
249
3662
249
  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3663
249
  // l->overflow_arg_area + sizeof(type).
3664
249
  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3665
249
  // an 8 byte boundary.
3666
249
3667
249
  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3668
249
  llvm::Value *Offset =
3669
249
      llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7)  & ~7);
3670
249
  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3671
249
                                            "overflow_arg_area.next");
3672
249
  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3673
249
3674
249
  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3675
249
  return Address(Res, Align);
3676
249
}
3677
3678
Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3679
249
                                 QualType Ty) const {
3680
249
  // Assume that va_list type is correct; should be pointer to LLVM type:
3681
249
  // struct {
3682
249
  //   i32 gp_offset;
3683
249
  //   i32 fp_offset;
3684
249
  //   i8* overflow_arg_area;
3685
249
  //   i8* reg_save_area;
3686
249
  // };
3687
249
  unsigned neededInt, neededSSE;
3688
249
3689
249
  Ty = getContext().getCanonicalType(Ty);
3690
249
  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3691
249
                                       /*isNamedArg*/false);
3692
249
3693
249
  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3694
249
  // in the registers. If not go to step 7.
3695
249
  if (!neededInt && 
!neededSSE57
)
3696
32
    return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3697
217
3698
217
  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3699
217
  // general purpose registers needed to pass type and num_fp to hold
3700
217
  // the number of floating point registers needed.
3701
217
3702
217
  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3703
217
  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3704
217
  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3705
217
  //
3706
217
  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3707
217
  // register save space).
3708
217
3709
217
  llvm::Value *InRegs = nullptr;
3710
217
  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3711
217
  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3712
217
  if (neededInt) {
3713
192
    gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
3714
192
    gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3715
192
    InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3716
192
    InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3717
192
  }
3718
217
3719
217
  if (neededSSE) {
3720
29
    fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
3721
29
    fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3722
29
    llvm::Value *FitsInFP =
3723
29
      llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3724
29
    FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3725
29
    InRegs = InRegs ? 
CGF.Builder.CreateAnd(InRegs, FitsInFP)4
:
FitsInFP25
;
3726
29
  }
3727
217
3728
217
  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3729
217
  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3730
217
  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3731
217
  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3732
217
3733
217
  // Emit code to load the value if it was passed in registers.
3734
217
3735
217
  CGF.EmitBlock(InRegBlock);
3736
217
3737
217
  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3738
217
  // an offset of l->gp_offset and/or l->fp_offset. This may require
3739
217
  // copying to a temporary location in case the parameter is passed
3740
217
  // in different register classes or requires an alignment greater
3741
217
  // than 8 for general purpose registers and 16 for XMM registers.
3742
217
  //
3743
217
  // FIXME: This really results in shameful code when we end up needing to
3744
217
  // collect arguments from different places; often what should result in a
3745
217
  // simple assembling of a structure from scattered addresses has many more
3746
217
  // loads than necessary. Can we clean this up?
3747
217
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3748
217
  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3749
217
      CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
3750
217
3751
217
  Address RegAddr = Address::invalid();
3752
217
  if (neededInt && 
neededSSE192
) {
3753
4
    // FIXME: Cleanup.
3754
4
    assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3755
4
    llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3756
4
    Address Tmp = CGF.CreateMemTemp(Ty);
3757
4
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3758
4
    assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3759
4
    llvm::Type *TyLo = ST->getElementType(0);
3760
4
    llvm::Type *TyHi = ST->getElementType(1);
3761
4
    assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3762
4
           "Unexpected ABI info for mixed regs");
3763
4
    llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3764
4
    llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3765
4
    llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3766
4
    llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3767
4
    llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? 
FPAddr1
:
GPAddr3
;
3768
4
    llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? 
GPAddr1
:
FPAddr3
;
3769
4
3770
4
    // Copy the first element.
3771
4
    // FIXME: Our choice of alignment here and below is probably pessimistic.
3772
4
    llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3773
4
        TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3774
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3775
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3776
4
3777
4
    // Copy the second element.
3778
4
    V = CGF.Builder.CreateAlignedLoad(
3779
4
        TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3780
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3781
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3782
4
3783
4
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3784
213
  } else if (neededInt) {
3785
188
    RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3786
188
                      CharUnits::fromQuantity(8));
3787
188
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3788
188
3789
188
    // Copy to a temporary if necessary to ensure the appropriate alignment.
3790
188
    std::pair<CharUnits, CharUnits> SizeAlign =
3791
188
        getContext().getTypeInfoInChars(Ty);
3792
188
    uint64_t TySize = SizeAlign.first.getQuantity();
3793
188
    CharUnits TyAlign = SizeAlign.second;
3794
188
3795
188
    // Copy into a temporary if the type is more aligned than the
3796
188
    // register save area.
3797
188
    if (TyAlign.getQuantity() > 8) {
3798
3
      Address Tmp = CGF.CreateMemTemp(Ty);
3799
3
      CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3800
3
      RegAddr = Tmp;
3801
3
    }
3802
188
3803
188
  } else 
if (25
neededSSE == 125
) {
3804
16
    RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3805
16
                      CharUnits::fromQuantity(16));
3806
16
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3807
16
  } else {
3808
9
    assert(neededSSE == 2 && "Invalid number of needed registers!");
3809
9
    // SSE registers are spaced 16 bytes apart in the register save
3810
9
    // area, we need to collect the two eightbytes together.
3811
9
    // The ABI isn't explicit about this, but it seems reasonable
3812
9
    // to assume that the slots are 16-byte aligned, since the stack is
3813
9
    // naturally 16-byte aligned and the prologue is expected to store
3814
9
    // all the SSE registers to the RSA.
3815
9
    Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3816
9
                                CharUnits::fromQuantity(16));
3817
9
    Address RegAddrHi =
3818
9
      CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3819
9
                                             CharUnits::fromQuantity(16));
3820
9
    llvm::Type *ST = AI.canHaveCoerceToType()
3821
9
                         ? AI.getCoerceToType()
3822
9
                         : 
llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy)0
;
3823
9
    llvm::Value *V;
3824
9
    Address Tmp = CGF.CreateMemTemp(Ty);
3825
9
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3826
9
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3827
9
        RegAddrLo, ST->getStructElementType(0)));
3828
9
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3829
9
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3830
9
        RegAddrHi, ST->getStructElementType(1)));
3831
9
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3832
9
3833
9
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3834
9
  }
3835
217
3836
217
  // AMD64-ABI 3.5.7p5: Step 5. Set:
3837
217
  // l->gp_offset = l->gp_offset + num_gp * 8
3838
217
  // l->fp_offset = l->fp_offset + num_fp * 16.
3839
217
  if (neededInt) {
3840
192
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3841
192
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3842
192
                            gp_offset_p);
3843
192
  }
3844
217
  if (neededSSE) {
3845
29
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3846
29
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3847
29
                            fp_offset_p);
3848
29
  }
3849
217
  CGF.EmitBranch(ContBlock);
3850
217
3851
217
  // Emit code to load the value if it was passed in memory.
3852
217
3853
217
  CGF.EmitBlock(InMemBlock);
3854
217
  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3855
217
3856
217
  // Return the appropriate result.
3857
217
3858
217
  CGF.EmitBlock(ContBlock);
3859
217
  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3860
217
                                 "vaarg.addr");
3861
217
  return ResAddr;
3862
217
}
3863
3864
Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3865
8
                                   QualType Ty) const {
3866
8
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3867
8
                          CGF.getContext().getTypeInfoInChars(Ty),
3868
8
                          CharUnits::fromQuantity(8),
3869
8
                          /*allowHigherAlign*/ false);
3870
8
}
3871
3872
ABIArgInfo
3873
WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3874
97
                                    const ABIArgInfo &current) const {
3875
97
  // Assumes vectorCall calling convention.
3876
97
  const Type *Base = nullptr;
3877
97
  uint64_t NumElts = 0;
3878
97
3879
97
  if (!Ty->isBuiltinType() && 
!Ty->isVectorType()49
&&
3880
97
      
isHomogeneousAggregate(Ty, Base, NumElts)36
&&
FreeSSERegs >= NumElts27
) {
3881
18
    FreeSSERegs -= NumElts;
3882
18
    return getDirectX86Hva();
3883
18
  }
3884
79
  return current;
3885
79
}
3886
3887
ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3888
                                      bool IsReturnType, bool IsVectorCall,
3889
8.53k
                                      bool IsRegCall) const {
3890
8.53k
3891
8.53k
  if (Ty->isVoidType())
3892
1.33k
    return ABIArgInfo::getIgnore();
3893
7.19k
3894
7.19k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3895
13
    Ty = EnumTy->getDecl()->getIntegerType();
3896
7.19k
3897
7.19k
  TypeInfo Info = getContext().getTypeInfo(Ty);
3898
7.19k
  uint64_t Width = Info.Width;
3899
7.19k
  CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3900
7.19k
3901
7.19k
  const RecordType *RT = Ty->getAs<RecordType>();
3902
7.19k
  if (RT) {
3903
249
    if (!IsReturnType) {
3904
219
      if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3905
67
        return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3906
182
    }
3907
182
3908
182
    if (RT->getDecl()->hasFlexibleArrayMember())
3909
0
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3910
7.13k
3911
7.13k
  }
3912
7.13k
3913
7.13k
  const Type *Base = nullptr;
3914
7.13k
  uint64_t NumElts = 0;
3915
7.13k
  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3916
7.13k
  // other targets.
3917
7.13k
  if ((IsVectorCall || 
IsRegCall7.02k
) &&
3918
7.13k
      
isHomogeneousAggregate(Ty, Base, NumElts)169
) {
3919
92
    if (IsRegCall) {
3920
29
      if (FreeSSERegs >= NumElts) {
3921
29
        FreeSSERegs -= NumElts;
3922
29
        if (IsReturnType || 
Ty->isBuiltinType()26
||
Ty->isVectorType()20
)
3923
15
          return ABIArgInfo::getDirect();
3924
14
        return ABIArgInfo::getExpand();
3925
14
      }
3926
0
      return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3927
63
    } else if (IsVectorCall) {
3928
63
      if (FreeSSERegs >= NumElts &&
3929
63
          
(57
IsReturnType57
||
Ty->isBuiltinType()45
||
Ty->isVectorType()36
)) {
3930
34
        FreeSSERegs -= NumElts;
3931
34
        return ABIArgInfo::getDirect();
3932
34
      } else 
if (29
IsReturnType29
) {
3933
0
        return ABIArgInfo::getExpand();
3934
29
      } else if (!Ty->isBuiltinType() && 
!Ty->isVectorType()27
) {
3935
27
        // HVAs are delayed and reclassified in the 2nd step.
3936
27
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3937
27
      }
3938
7.04k
    }
3939
92
  }
3940
7.04k
3941
7.04k
  if (Ty->isMemberPointerType()) {
3942
156
    // If the member pointer is represented by an LLVM int or ptr, pass it
3943
156
    // directly.
3944
156
    llvm::Type *LLTy = CGT.ConvertType(Ty);
3945
156
    if (LLTy->isPointerTy() || 
LLTy->isIntegerTy()75
)
3946
88
      return ABIArgInfo::getDirect();
3947
6.95k
  }
3948
6.95k
3949
6.95k
  if (RT || 
Ty->isAnyComplexType()6.82k
||
Ty->isMemberPointerType()6.80k
) {
3950
214
    // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3951
214
    // not 1, 2, 4, or 8 bytes, must be passed by reference."
3952
214
    if (Width > 64 || 
!llvm::isPowerOf2_64(Width)114
)
3953
100
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3954
114
3955
114
    // Otherwise, coerce it to a small integer.
3956
114
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3957
114
  }
3958
6.74k
3959
6.74k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3960
1.84k
    switch (BT->getKind()) {
3961
1.84k
    case BuiltinType::Bool:
3962
25
      // Bool type is always extended to the ABI, other builtin types are not
3963
25
      // extended.
3964
25
      return ABIArgInfo::getExtend(Ty);
3965
1.84k
3966
1.84k
    case BuiltinType::LongDouble:
3967
56
      // Mingw64 GCC uses the old 80 bit extended precision floating point
3968
56
      // unit. It passes them indirectly through memory.
3969
56
      if (IsMingw64) {
3970
6
        const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3971
6
        if (LDF == &llvm::APFloat::x87DoubleExtended())
3972
6
          return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3973
50
      }
3974
50
      break;
3975
50
3976
50
    case BuiltinType::Int128:
3977
8
    case BuiltinType::UInt128:
3978
8
      // If it's a parameter type, the normal ABI rule is that arguments larger
3979
8
      // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
3980
8
      // even though it isn't particularly efficient.
3981
8
      if (!IsReturnType)
3982
4
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3983
4
3984
4
      // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
3985
4
      // Clang matches them for compatibility.
3986
4
      return ABIArgInfo::getDirect(
3987
4
          llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2));
3988
4
3989
1.76k
    default:
3990
1.76k
      break;
3991
6.70k
    }
3992
6.70k
  }
3993
6.70k
3994
6.70k
  return ABIArgInfo::getDirect();
3995
6.70k
}
3996
3997
void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3998
                                             unsigned FreeSSERegs,
3999
                                             bool IsVectorCall,
4000
48
                                             bool IsRegCall) const {
4001
48
  unsigned Count = 0;
4002
97
  for (auto &I : FI.arguments()) {
4003
97
    // Vectorcall in x64 only permits the first 6 arguments to be passed
4004
97
    // as XMM/YMM registers.
4005
97
    if (Count < VectorcallMaxParamNumAsReg)
4006
92
      I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4007
5
    else {
4008
5
      // Since these cannot be passed in registers, pretend no registers
4009
5
      // are left.
4010
5
      unsigned ZeroSSERegsAvail = 0;
4011
5
      I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
4012
5
                        IsVectorCall, IsRegCall);
4013
5
    }
4014
97
    ++Count;
4015
97
  }
4016
48
4017
97
  for (auto &I : FI.arguments()) {
4018
97
    I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
4019
97
  }
4020
48
}
4021
4022
3.46k
void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4023
3.46k
  const unsigned CC = FI.getCallingConvention();
4024
3.46k
  bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
4025
3.46k
  bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
4026
3.46k
4027
3.46k
  // If __attribute__((sysv_abi)) is in use, use the SysV argument
4028
3.46k
  // classification rules.
4029
3.46k
  if (CC == llvm::CallingConv::X86_64_SysV) {
4030
14
    X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
4031
14
    SysVABIInfo.computeInfo(FI);
4032
14
    return;
4033
14
  }
4034
3.45k
4035
3.45k
  unsigned FreeSSERegs = 0;
4036
3.45k
  if (IsVectorCall) {
4037
48
    // We can use up to 4 SSE return registers with vectorcall.
4038
48
    FreeSSERegs = 4;
4039
3.40k
  } else if (IsRegCall) {
4040
22
    // RegCall gives us 16 SSE registers.
4041
22
    FreeSSERegs = 16;
4042
22
  }
4043
3.45k
4044
3.45k
  if (!getCXXABI().classifyReturnType(FI))
4045
3.41k
    FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4046
3.41k
                                  IsVectorCall, IsRegCall);
4047
3.45k
4048
3.45k
  if (IsVectorCall) {
4049
48
    // We can use up to 6 SSE register parameters with vectorcall.
4050
48
    FreeSSERegs = 6;
4051
3.40k
  } else if (IsRegCall) {
4052
22
    // RegCall gives us 16 SSE registers, we can reuse the return registers.
4053
22
    FreeSSERegs = 16;
4054
22
  }
4055
3.45k
4056
3.45k
  if (IsVectorCall) {
4057
48
    computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4058
3.40k
  } else {
4059
3.40k
    for (auto &I : FI.arguments())
4060
5.02k
      I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4061
3.40k
  }
4062
3.45k
4063
3.45k
}
4064
4065
Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4066
9
                                    QualType Ty) const {
4067
9
4068
9
  bool IsIndirect = false;
4069
9
4070
9
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4071
9
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4072
9
  if (isAggregateTypeForABI(Ty) || 
Ty->isMemberPointerType()3
) {
4073
6
    uint64_t Width = getContext().getTypeSize(Ty);
4074
6
    IsIndirect = Width > 64 || 
!llvm::isPowerOf2_64(Width)0
;
4075
6
  }
4076
9
4077
9
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4078
9
                          CGF.getContext().getTypeInfoInChars(Ty),
4079
9
                          CharUnits::fromQuantity(8),
4080
9
                          /*allowHigherAlign*/ false);
4081
9
}
4082
4083
// PowerPC-32
4084
namespace {
4085
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4086
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4087
  bool IsSoftFloatABI;
4088
4089
  CharUnits getParamTypeAlignment(QualType Ty) const;
4090
4091
public:
4092
  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4093
28
      : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4094
4095
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4096
                    QualType Ty) const override;
4097
};
4098
4099
class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4100
public:
4101
  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4102
28
      : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4103
4104
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4105
0
    // This is recovered from gcc output.
4106
0
    return 1; // r1 is the dedicated stack pointer
4107
0
  }
4108
4109
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4110
                               llvm::Value *Address) const override;
4111
};
4112
}
4113
4114
0
CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4115
0
  // Complex types are passed just like their elements
4116
0
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4117
0
    Ty = CTy->getElementType();
4118
0
4119
0
  if (Ty->isVectorType())
4120
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4121
0
                                                                       : 4);
4122
0
4123
0
  // For single-element float/vector structs, we consider the whole type
4124
0
  // to have the same alignment requirements as its single element.
4125
0
  const Type *AlignTy = nullptr;
4126
0
  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4127
0
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
4128
0
    if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4129
0
        (BT && BT->isFloatingPoint()))
4130
0
      AlignTy = EltType;
4131
0
  }
4132
0
4133
0
  if (AlignTy)
4134
0
    return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4135
0
  return CharUnits::fromQuantity(4);
4136
0
}
4137
4138
// TODO: this implementation is now likely redundant with
4139
// DefaultABIInfo::EmitVAArg.
4140
Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4141
1
                                      QualType Ty) const {
4142
1
  if (getTarget().getTriple().isOSDarwin()) {
4143
0
    auto TI = getContext().getTypeInfoInChars(Ty);
4144
0
    TI.second = getParamTypeAlignment(Ty);
4145
0
4146
0
    CharUnits SlotSize = CharUnits::fromQuantity(4);
4147
0
    return emitVoidPtrVAArg(CGF, VAList, Ty,
4148
0
                            classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4149
0
                            /*AllowHigherAlign=*/true);
4150
0
  }
4151
1
4152
1
  const unsigned OverflowLimit = 8;
4153
1
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4154
0
    // TODO: Implement this. For now ignore.
4155
0
    (void)CTy;
4156
0
    return Address::invalid(); // FIXME?
4157
0
  }
4158
1
4159
1
  // struct __va_list_tag {
4160
1
  //   unsigned char gpr;
4161
1
  //   unsigned char fpr;
4162
1
  //   unsigned short reserved;
4163
1
  //   void *overflow_arg_area;
4164
1
  //   void *reg_save_area;
4165
1
  // };
4166
1
4167
1
  bool isI64 = Ty->isIntegerType() && 
getContext().getTypeSize(Ty) == 640
;
4168
1
  bool isInt =
4169
1
      Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4170
1
  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4171
1
4172
1
  // All aggregates are passed indirectly?  That doesn't seem consistent
4173
1
  // with the argument-lowering code.
4174
1
  bool isIndirect = Ty->isAggregateType();
4175
1
4176
1
  CGBuilderTy &Builder = CGF.Builder;
4177
1
4178
1
  // The calling convention either uses 1-2 GPRs or 1 FPR.
4179
1
  Address NumRegsAddr = Address::invalid();
4180
1
  if (isInt || IsSoftFloatABI) {
4181
1
    NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4182
1
  } else {
4183
0
    NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4184
0
  }
4185
1
4186
1
  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4187
1
4188
1
  // "Align" the register count when TY is i64.
4189
1
  if (isI64 || (isF64 && IsSoftFloatABI)) {
4190
1
    NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4191
1
    NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4192
1
  }
4193
1
4194
1
  llvm::Value *CC =
4195
1
      Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4196
1
4197
1
  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4198
1
  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4199
1
  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4200
1
4201
1
  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4202
1
4203
1
  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4204
1
  if (isIndirect) 
DirectTy = DirectTy->getPointerTo(0)0
;
4205
1
4206
1
  // Case 1: consume registers.
4207
1
  Address RegAddr = Address::invalid();
4208
1
  {
4209
1
    CGF.EmitBlock(UsingRegs);
4210
1
4211
1
    Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4212
1
    RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4213
1
                      CharUnits::fromQuantity(8));
4214
1
    assert(RegAddr.getElementType() == CGF.Int8Ty);
4215
1
4216
1
    // Floating-point registers start after the general-purpose registers.
4217
1
    if (!(isInt || IsSoftFloatABI)) {
4218
0
      RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4219
0
                                                   CharUnits::fromQuantity(32));
4220
0
    }
4221
1
4222
1
    // Get the address of the saved value by scaling the number of
4223
1
    // registers we've used by the number of
4224
1
    CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 
80
);
4225
1
    llvm::Value *RegOffset =
4226
1
      Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4227
1
    RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4228
1
                                            RegAddr.getPointer(), RegOffset),
4229
1
                      RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4230
1
    RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4231
1
4232
1
    // Increase the used-register count.
4233
1
    NumRegs =
4234
1
      Builder.CreateAdd(NumRegs,
4235
1
                        Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 
10
));
4236
1
    Builder.CreateStore(NumRegs, NumRegsAddr);
4237
1
4238
1
    CGF.EmitBranch(Cont);
4239
1
  }
4240
1
4241
1
  // Case 2: consume space in the overflow area.
4242
1
  Address MemAddr = Address::invalid();
4243
1
  {
4244
1
    CGF.EmitBlock(UsingOverflow);
4245
1
4246
1
    Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4247
1
4248
1
    // Everything in the overflow area is rounded up to a size of at least 4.
4249
1
    CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4250
1
4251
1
    CharUnits Size;
4252
1
    if (!isIndirect) {
4253
1
      auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4254
1
      Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4255
1
    } else {
4256
0
      Size = CGF.getPointerSize();
4257
0
    }
4258
1
4259
1
    Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4260
1
    Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4261
1
                         OverflowAreaAlign);
4262
1
    // Round up address of argument to alignment
4263
1
    CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4264
1
    if (Align > OverflowAreaAlign) {
4265
1
      llvm::Value *Ptr = OverflowArea.getPointer();
4266
1
      OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4267
1
                                                           Align);
4268
1
    }
4269
1
4270
1
    MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4271
1
4272
1
    // Increase the overflow area.
4273
1
    OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4274
1
    Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4275
1
    CGF.EmitBranch(Cont);
4276
1
  }
4277
1
4278
1
  CGF.EmitBlock(Cont);
4279
1
4280
1
  // Merge the cases with a phi.
4281
1
  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4282
1
                                "vaarg.addr");
4283
1
4284
1
  // Load the pointer if the argument was passed indirectly.
4285
1
  if (isIndirect) {
4286
0
    Result = Address(Builder.CreateLoad(Result, "aggr"),
4287
0
                     getContext().getTypeAlignInChars(Ty));
4288
0
  }
4289
1
4290
1
  return Result;
4291
1
}
4292
4293
bool
4294
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4295
0
                                                llvm::Value *Address) const {
4296
0
  // This is calculated from the LLVM and GCC tables and verified
4297
0
  // against gcc output.  AFAIK all ABIs use the same encoding.
4298
0
4299
0
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4300
0
4301
0
  llvm::IntegerType *i8 = CGF.Int8Ty;
4302
0
  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4303
0
  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4304
0
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4305
0
4306
0
  // 0-31: r0-31, the 4-byte general-purpose registers
4307
0
  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4308
0
4309
0
  // 32-63: fp0-31, the 8-byte floating-point registers
4310
0
  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4311
0
4312
0
  // 64-76 are various 4-byte special-purpose registers:
4313
0
  // 64: mq
4314
0
  // 65: lr
4315
0
  // 66: ctr
4316
0
  // 67: ap
4317
0
  // 68-75 cr0-7
4318
0
  // 76: xer
4319
0
  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4320
0
4321
0
  // 77-108: v0-31, the 16-byte vector registers
4322
0
  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4323
0
4324
0
  // 109: vrsave
4325
0
  // 110: vscr
4326
0
  // 111: spe_acc
4327
0
  // 112: spefscr
4328
0
  // 113: sfp
4329
0
  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4330
0
4331
0
  return false;
4332
0
}
4333
4334
// PowerPC-64
4335
4336
namespace {
4337
/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4338
class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4339
public:
4340
  enum ABIKind {
4341
    ELFv1 = 0,
4342
    ELFv2
4343
  };
4344
4345
private:
4346
  static const unsigned GPRBits = 64;
4347
  ABIKind Kind;
4348
  bool HasQPX;
4349
  bool IsSoftFloatABI;
4350
4351
  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4352
  // will be passed in a QPX register.
4353
4.09k
  bool IsQPXVectorTy(const Type *Ty) const {
4354
4.09k
    if (!HasQPX)
4355
4.08k
      return false;
4356
9
4357
9
    if (const VectorType *VT = Ty->getAs<VectorType>()) {
4358
6
      unsigned NumElements = VT->getNumElements();
4359
6
      if (NumElements == 1)
4360
0
        return false;
4361
6
4362
6
      if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4363
3
        if (getContext().getTypeSize(Ty) <= 256)
4364
3
          return true;
4365
3
      } else if (VT->getElementType()->
4366
3
                   isSpecificBuiltinType(BuiltinType::Float)) {
4367
3
        if (getContext().getTypeSize(Ty) <= 128)
4368
3
          return true;
4369
3
      }
4370
6
    }
4371
3
4372
3
    return false;
4373
3
  }
4374
4375
4.02k
  bool IsQPXVectorTy(QualType Ty) const {
4376
4.02k
    return IsQPXVectorTy(Ty.getTypePtr());
4377
4.02k
  }
4378
4379
public:
4380
  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4381
                     bool SoftFloatABI)
4382
      : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4383
1.64k
        IsSoftFloatABI(SoftFloatABI) {}
4384
4385
  bool isPromotableTypeForABI(QualType Ty) const;
4386
  CharUnits getParamTypeAlignment(QualType Ty) const;
4387
4388
  ABIArgInfo classifyReturnType(QualType RetTy) const;
4389
  ABIArgInfo classifyArgumentType(QualType Ty) const;
4390
4391
  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4392
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4393
                                         uint64_t Members) const override;
4394
4395
  // TODO: We can add more logic to computeInfo to improve performance.
4396
  // Example: For aggregate arguments that fit in a register, we could
4397
  // use getDirectInReg (as is done below for structs containing a single
4398
  // floating-point value) to avoid pushing them to memory on function
4399
  // entry.  This would require changing the logic in PPCISelLowering
4400
  // when lowering the parameters in the caller and args in the callee.
4401
11.3k
  void computeInfo(CGFunctionInfo &FI) const override {
4402
11.3k
    if (!getCXXABI().classifyReturnType(FI))
4403
11.3k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4404
22.2k
    for (auto &I : FI.arguments()) {
4405
22.2k
      // We rely on the default argument classification for the most part.
4406
22.2k
      // One exception:  An aggregate containing a single floating-point
4407
22.2k
      // or vector item must be passed in a register if one is available.
4408
22.2k
      const Type *T = isSingleElementStruct(I.type, getContext());
4409
22.2k
      if (T) {
4410
18
        const BuiltinType *BT = T->getAs<BuiltinType>();
4411
18
        if (IsQPXVectorTy(T) ||
4412
18
            
(16
T->isVectorType()16
&&
getContext().getTypeSize(T) == 1286
) ||
4413
18
            
(12
BT12
&&
BT->isFloatingPoint()8
)) {
4414
14
          QualType QT(T, 0);
4415
14
          I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4416
14
          continue;
4417
14
        }
4418
22.2k
      }
4419
22.2k
      I.info = classifyArgumentType(I.type);
4420
22.2k
    }
4421
11.3k
  }
4422
4423
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4424
                    QualType Ty) const override;
4425
4426
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4427
0
                                    bool asReturnValue) const override {
4428
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4429
0
  }
4430
4431
0
  bool isSwiftErrorInRegister() const override {
4432
0
    return false;
4433
0
  }
4434
};
4435
4436
class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4437
4438
public:
4439
  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4440
                               PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4441
                               bool SoftFloatABI)
4442
      : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4443
1.64k
                                                 SoftFloatABI)) {}
4444
4445
1
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4446
1
    // This is recovered from gcc output.
4447
1
    return 1; // r1 is the dedicated stack pointer
4448
1
  }
4449
4450
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4451
                               llvm::Value *Address) const override;
4452
};
4453
4454
class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4455
public:
4456
0
  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4457
4458
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4459
0
    // This is recovered from gcc output.
4460
0
    return 1; // r1 is the dedicated stack pointer
4461
0
  }
4462
4463
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4464
                               llvm::Value *Address) const override;
4465
};
4466
4467
}
4468
4469
// Return true if the ABI requires Ty to be passed sign- or zero-
4470
// extended to 64 bits.
4471
bool
4472
25.6k
PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4473
25.6k
  // Treat an enum type as its underlying type.
4474
25.6k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4475
2
    Ty = EnumTy->getDecl()->getIntegerType();
4476
25.6k
4477
25.6k
  // Promotable integer types are required to be promoted by the ABI.
4478
25.6k
  if (Ty->isPromotableIntegerType())
4479
250
    return true;
4480
25.3k
4481
25.3k
  // In addition to the usual promotable integer types, we also need to
4482
25.3k
  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4483
25.3k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4484
9.09k
    switch (BT->getKind()) {
4485
9.09k
    case BuiltinType::Int:
4486
3.95k
    case BuiltinType::UInt:
4487
3.95k
      return true;
4488
5.14k
    default:
4489
5.14k
      break;
4490
21.4k
    }
4491
21.4k
4492
21.4k
  return false;
4493
21.4k
}
4494
4495
/// isAlignedParamType - Determine whether a type requires 16-byte or
4496
/// higher alignment in the parameter area.  Always returns at least 8.
4497
116
CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4498
116
  // Complex types are passed just like their elements.
4499
116
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4500
8
    Ty = CTy->getElementType();
4501
116
4502
116
  // Only vector types of size 16 bytes need alignment (larger types are
4503
116
  // passed via reference, smaller types are not aligned).
4504
116
  if (IsQPXVectorTy(Ty)) {
4505
0
    if (getContext().getTypeSize(Ty) > 128)
4506
0
      return CharUnits::fromQuantity(32);
4507
0
4508
0
    return CharUnits::fromQuantity(16);
4509
116
  } else if (Ty->isVectorType()) {
4510
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4511
0
  }
4512
116
4513
116
  // For single-element float/vector structs, we consider the whole type
4514
116
  // to have the same alignment requirements as its single element.
4515
116
  const Type *AlignAsType = nullptr;
4516
116
  const Type *EltType = isSingleElementStruct(Ty, getContext());
4517
116
  if (EltType) {
4518
4
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
4519
4
    if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4520
4
         
getContext().getTypeSize(EltType) == 1283
) ||
4521
4
        
(3
BT3
&&
BT->isFloatingPoint()1
))
4522
2
      AlignAsType = EltType;
4523
4
  }
4524
116
4525
116
  // Likewise for ELFv2 homogeneous aggregates.
4526
116
  const Type *Base = nullptr;
4527
116
  uint64_t Members = 0;
4528
116
  if (!AlignAsType && 
Kind == ELFv2114
&&
4529
116
      
isAggregateTypeForABI(Ty)78
&&
isHomogeneousAggregate(Ty, Base, Members)74
)
4530
46
    AlignAsType = Base;
4531
116
4532
116
  // With special case aggregates, only vector base types need alignment.
4533
116
  if (AlignAsType && 
IsQPXVectorTy(AlignAsType)48
) {
4534
0
    if (getContext().getTypeSize(AlignAsType) > 128)
4535
0
      return CharUnits::fromQuantity(32);
4536
0
4537
0
    return CharUnits::fromQuantity(16);
4538
116
  } else if (AlignAsType) {
4539
48
    return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 
1619
:
829
);
4540
48
  }
4541
68
4542
68
  // Otherwise, we only need alignment for any aggregate type that
4543
68
  // has an alignment requirement of >= 16 bytes.
4544
68
  if (isAggregateTypeForABI(Ty) && 
getContext().getTypeAlign(Ty) >= 12860
) {
4545
19
    if (HasQPX && 
getContext().getTypeAlign(Ty) >= 2562
)
4546
1
      return CharUnits::fromQuantity(32);
4547
18
    return CharUnits::fromQuantity(16);
4548
18
  }
4549
49
4550
49
  return CharUnits::fromQuantity(8);
4551
49
}
4552
4553
/// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4554
/// aggregate.  Base is set to the base element type, and Members is set
4555
/// to the number of base elements.
4556
bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4557
20.8k
                                     uint64_t &Members) const {
4558
20.8k
  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4559
1.89k
    uint64_t NElements = AT->getSize().getZExtValue();
4560
1.89k
    if (NElements == 0)
4561
0
      return false;
4562
1.89k
    if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4563
400
      return false;
4564
1.49k
    Members *= NElements;
4565
18.9k
  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4566
10.6k
    const RecordDecl *RD = RT->getDecl();
4567
10.6k
    if (RD->hasFlexibleArrayMember())
4568
0
      return false;
4569
10.6k
4570
10.6k
    Members = 0;
4571
10.6k
4572
10.6k
    // If this is a C++ record, check the bases first.
4573
10.6k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4574
8.80k
      for (const auto &I : CXXRD->bases()) {
4575
3.16k
        // Ignore empty records.
4576
3.16k
        if (isEmptyRecord(getContext(), I.getType(), true))
4577
1.60k
          continue;
4578
1.56k
4579
1.56k
        uint64_t FldMembers;
4580
1.56k
        if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4581
1.39k
          return false;
4582
166
4583
166
        Members += FldMembers;
4584
166
      }
4585
8.80k
    }
4586
10.6k
4587
10.6k
    
for (const auto *FD : RD->fields())9.21k
{
4588
10.0k
      // Ignore (non-zero arrays of) empty records.
4589
10.0k
      QualType FT = FD->getType();
4590
11.8k
      while (const ConstantArrayType *AT =
4591
1.89k
             getContext().getAsConstantArrayType(FT)) {
4592
1.89k
        if (AT->getSize().getZExtValue() == 0)
4593
0
          return false;
4594
1.89k
        FT = AT->getElementType();
4595
1.89k
      }
4596
10.0k
      if (isEmptyRecord(getContext(), FT, true))
4597
31
        continue;
4598
9.96k
4599
9.96k
      // For compatibility with GCC, ignore empty bitfields in C++ mode.
4600
9.96k
      if (getContext().getLangOpts().CPlusPlus &&
4601
9.96k
          
FD->isZeroLengthBitField(getContext())7.45k
)
4602
6
        continue;
4603
9.96k
4604
9.96k
      uint64_t FldMembers;
4605
9.96k
      if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4606
6.95k
        return false;
4607
3.01k
4608
3.01k
      Members = (RD->isUnion() ?
4609
2.98k
                 
std::max(Members, FldMembers)27
: Members + FldMembers);
4610
3.01k
    }
4611
9.21k
4612
9.21k
    
if (2.26k
!Base2.26k
)
4613
44
      return false;
4614
2.21k
4615
2.21k
    // Ensure there is no padding.
4616
2.21k
    if (getContext().getTypeSize(Base) * Members !=
4617
2.21k
        getContext().getTypeSize(Ty))
4618
0
      return false;
4619
8.37k
  } else {
4620
8.37k
    Members = 1;
4621
8.37k
    if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4622
194
      Members = 2;
4623
194
      Ty = CT->getElementType();
4624
194
    }
4625
8.37k
4626
8.37k
    // Most ABIs only support float, double, and some vector type widths.
4627
8.37k
    if (!isHomogeneousAggregateBaseType(Ty))
4628
5.24k
      return false;
4629
3.13k
4630
3.13k
    // The base type must be the same for all members.  Types that
4631
3.13k
    // agree in both total size and mode (float vs. vector) are
4632
3.13k
    // treated as being equivalent here.
4633
3.13k
    const Type *TyPtr = Ty.getTypePtr();
4634
3.13k
    if (!Base) {
4635
2.25k
      Base = TyPtr;
4636
2.25k
      // If it's a non-power-of-2 vector, its size is already a power-of-2,
4637
2.25k
      // so make sure to widen it explicitly.
4638
2.25k
      if (const VectorType *VT = Base->getAs<VectorType>()) {
4639
1.01k
        QualType EltTy = VT->getElementType();
4640
1.01k
        unsigned NumElements =
4641
1.01k
            getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4642
1.01k
        Base = getContext()
4643
1.01k
                   .getVectorType(EltTy, NumElements, VT->getVectorKind())
4644
1.01k
                   .getTypePtr();
4645
1.01k
      }
4646
2.25k
    }
4647
3.13k
4648
3.13k
    if (Base->isVectorType() != TyPtr->isVectorType() ||
4649
3.13k
        getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4650
7
      return false;
4651
6.84k
  }
4652
6.84k
  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4653
6.84k
}
4654
4655
301
bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4656
301
  // Homogeneous aggregates for ELFv2 must have base types of float,
4657
301
  // double, long double, or 128-bit vectors.
4658
301
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4659
217
    if (BT->getKind() == BuiltinType::Float ||
4660
217
        
BT->getKind() == BuiltinType::Double107
||
4661
217
        
BT->getKind() == BuiltinType::LongDouble77
||
4662
217
        
(77
getContext().getTargetInfo().hasFloat128Type()77
&&
4663
186
          
(BT->getKind() == BuiltinType::Float128)46
)) {
4664
186
      if (IsSoftFloatABI)
4665
34
        return false;
4666
152
      return true;
4667
152
    }
4668
217
  }
4669
115
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4670
80
    if (getContext().getTypeSize(VT) == 128 || 
IsQPXVectorTy(Ty)0
)
4671
80
      return true;
4672
35
  }
4673
35
  return false;
4674
35
}
4675
4676
bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4677
519
    const Type *Base, uint64_t Members) const {
4678
519
  // Vector and fp128 types require one register, other floating point types
4679
519
  // require one or two registers depending on their size.
4680
519
  uint32_t NumRegs =
4681
519
      ((getContext().getTargetInfo().hasFloat128Type() &&
4682
519
          
Base->isFloat128Type()108
) ||
4683
519
        
Base->isVectorType()411
) ?
1294
4684
519
                              : 
(getContext().getTypeSize(Base) + 63) / 64225
;
4685
519
4686
519
  // Homogeneous Aggregates may occupy at most 8 registers.
4687
519
  return Members * NumRegs <= 8;
4688
519
}
4689
4690
ABIArgInfo
4691
22.2k
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4692
22.2k
  Ty = useFirstFieldIfTransparentUnion(Ty);
4693
22.2k
4694
22.2k
  if (Ty->isAnyComplexType())
4695
17
    return ABIArgInfo::getDirect();
4696
22.2k
4697
22.2k
  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4698
22.2k
  // or via reference (larger than 16 bytes).
4699
22.2k
  if (Ty->isVectorType() && 
!IsQPXVectorTy(Ty)2.50k
) {
4700
2.49k
    uint64_t Size = getContext().getTypeSize(Ty);
4701
2.49k
    if (Size > 128)
4702
2
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4703
2.49k
    else if (Size < 128) {
4704
3
      llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4705
3
      return ABIArgInfo::getDirect(CoerceTy);
4706
3
    }
4707
22.1k
  }
4708
22.1k
4709
22.1k
  if (isAggregateTypeForABI(Ty)) {
4710
150
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4711
48
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4712
102
4713
102
    uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4714
102
    uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4715
102
4716
102
    // ELFv2 homogeneous aggregates are passed as array types.
4717
102
    const Type *Base = nullptr;
4718
102
    uint64_t Members = 0;
4719
102
    if (Kind == ELFv2 &&
4720
102
        
isHomogeneousAggregate(Ty, Base, Members)74
) {
4721
46
      llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4722
46
      llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4723
46
      return ABIArgInfo::getDirect(CoerceTy);
4724
46
    }
4725
56
4726
56
    // If an aggregate may end up fully in registers, we do not
4727
56
    // use the ByVal method, but pass the aggregate as array.
4728
56
    // This is usually beneficial since we avoid forcing the
4729
56
    // back-end to store the argument to memory.
4730
56
    uint64_t Bits = getContext().getTypeSize(Ty);
4731
56
    if (Bits > 0 && Bits <= 8 * GPRBits) {
4732
50
      llvm::Type *CoerceTy;
4733
50
4734
50
      // Types up to 8 bytes are passed as integer type (which will be
4735
50
      // properly aligned in the argument save area doubleword).
4736
50
      if (Bits <= GPRBits)
4737
14
        CoerceTy =
4738
14
            llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4739
36
      // Larger types are passed as arrays, with the base type selected
4740
36
      // according to the required alignment in the save area.
4741
36
      else {
4742
36
        uint64_t RegBits = ABIAlign * 8;
4743
36
        uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4744
36
        llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4745
36
        CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4746
36
      }
4747
50
4748
50
      return ABIArgInfo::getDirect(CoerceTy);
4749
50
    }
4750
6
4751
6
    // All other aggregates are passed ByVal.
4752
6
    return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4753
6
                                   /*ByVal=*/true,
4754
6
                                   /*Realign=*/TyAlign > ABIAlign);
4755
6
  }
4756
22.0k
4757
22.0k
  return (isPromotableTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)2.21k
4758
22.0k
                                     : 
ABIArgInfo::getDirect()19.8k
);
4759
22.0k
}
4760
4761
ABIArgInfo
4762
11.3k
PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4763
11.3k
  if (RetTy->isVoidType())
4764
7.61k
    return ABIArgInfo::getIgnore();
4765
3.71k
4766
3.71k
  if (RetTy->isAnyComplexType())
4767
17
    return ABIArgInfo::getDirect();
4768
3.69k
4769
3.69k
  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4770
3.69k
  // or via reference (larger than 16 bytes).
4771
3.69k
  if (RetTy->isVectorType() && 
!IsQPXVectorTy(RetTy)1.40k
) {
4772
1.40k
    uint64_t Size = getContext().getTypeSize(RetTy);
4773
1.40k
    if (Size > 128)
4774
2
      return getNaturalAlignIndirect(RetTy);
4775
1.40k
    else if (Size < 128) {
4776
3
      llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4777
3
      return ABIArgInfo::getDirect(CoerceTy);
4778
3
    }
4779
3.69k
  }
4780
3.69k
4781
3.69k
  if (isAggregateTypeForABI(RetTy)) {
4782
113
    // ELFv2 homogeneous aggregates are returned as array types.
4783
113
    const Type *Base = nullptr;
4784
113
    uint64_t Members = 0;
4785
113
    if (Kind == ELFv2 &&
4786
113
        
isHomogeneousAggregate(RetTy, Base, Members)90
) {
4787
48
      llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4788
48
      llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4789
48
      return ABIArgInfo::getDirect(CoerceTy);
4790
48
    }
4791
65
4792
65
    // ELFv2 small aggregates are returned in up to two registers.
4793
65
    uint64_t Bits = getContext().getTypeSize(RetTy);
4794
65
    if (Kind == ELFv2 && 
Bits <= 2 * GPRBits42
) {
4795
26
      if (Bits == 0)
4796
0
        return ABIArgInfo::getIgnore();
4797
26
4798
26
      llvm::Type *CoerceTy;
4799
26
      if (Bits > GPRBits) {
4800
6
        CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4801
6
        CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4802
6
      } else
4803
20
        CoerceTy =
4804
20
            llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4805
26
      return ABIArgInfo::getDirect(CoerceTy);
4806
26
    }
4807
39
4808
39
    // All other aggregates are returned indirectly.
4809
39
    return getNaturalAlignIndirect(RetTy);
4810
39
  }
4811
3.58k
4812
3.58k
  return (isPromotableTypeForABI(RetTy) ? 
ABIArgInfo::getExtend(RetTy)1.98k
4813
3.58k
                                        : 
ABIArgInfo::getDirect()1.59k
);
4814
3.58k
}
4815
4816
// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4817
Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4818
14
                                      QualType Ty) const {
4819
14
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4820
14
  TypeInfo.second = getParamTypeAlignment(Ty);
4821
14
4822
14
  CharUnits SlotSize = CharUnits::fromQuantity(8);
4823
14
4824
14
  // If we have a complex type and the base type is smaller than 8 bytes,
4825
14
  // the ABI calls for the real and imaginary parts to be right-adjusted
4826
14
  // in separate doublewords.  However, Clang expects us to produce a
4827
14
  // pointer to a structure with the two parts packed tightly.  So generate
4828
14
  // loads of the real and imaginary parts relative to the va_list pointer,
4829
14
  // and store them to a temporary structure.
4830
14
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4831
8
    CharUnits EltSize = TypeInfo.first / 2;
4832
8
    if (EltSize < SlotSize) {
4833
8
      Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4834
8
                                            SlotSize * 2, SlotSize,
4835
8
                                            SlotSize, /*AllowHigher*/ true);
4836
8
4837
8
      Address RealAddr = Addr;
4838
8
      Address ImagAddr = RealAddr;
4839
8
      if (CGF.CGM.getDataLayout().isBigEndian()) {
4840
4
        RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4841
4
                                                          SlotSize - EltSize);
4842
4
        ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4843
4
                                                      2 * SlotSize - EltSize);
4844
4
      } else {
4845
4
        ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4846
4
      }
4847
8
4848
8
      llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4849
8
      RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4850
8
      ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4851
8
      llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4852
8
      llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4853
8
4854
8
      Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4855
8
      CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4856
8
                             /*init*/ true);
4857
8
      return Temp;
4858
8
    }
4859
6
  }
4860
6
4861
6
  // Otherwise, just use the general rule.
4862
6
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4863
6
                          TypeInfo, SlotSize, /*AllowHigher*/ true);
4864
6
}
4865
4866
static bool
4867
PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4868
1
                              llvm::Value *Address) {
4869
1
  // This is calculated from the LLVM and GCC tables and verified
4870
1
  // against gcc output.  AFAIK all ABIs use the same encoding.
4871
1
4872
1
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4873
1
4874
1
  llvm::IntegerType *i8 = CGF.Int8Ty;
4875
1
  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4876
1
  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4877
1
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4878
1
4879
1
  // 0-31: r0-31, the 8-byte general-purpose registers
4880
1
  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4881
1
4882
1
  // 32-63: fp0-31, the 8-byte floating-point registers
4883
1
  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4884
1
4885
1
  // 64-67 are various 8-byte special-purpose registers:
4886
1
  // 64: mq
4887
1
  // 65: lr
4888
1
  // 66: ctr
4889
1
  // 67: ap
4890
1
  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4891
1
4892
1
  // 68-76 are various 4-byte special-purpose registers:
4893
1
  // 68-75 cr0-7
4894
1
  // 76: xer
4895
1
  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4896
1
4897
1
  // 77-108: v0-31, the 16-byte vector registers
4898
1
  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4899
1
4900
1
  // 109: vrsave
4901
1
  // 110: vscr
4902
1
  // 111: spe_acc
4903
1
  // 112: spefscr
4904
1
  // 113: sfp
4905
1
  // 114: tfhar
4906
1
  // 115: tfiar
4907
1
  // 116: texasr
4908
1
  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4909
1
4910
1
  return false;
4911
1
}
4912
4913
bool
4914
PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4915
  CodeGen::CodeGenFunction &CGF,
4916
1
  llvm::Value *Address) const {
4917
1
4918
1
  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4919
1
}
4920
4921
bool
4922
PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4923
0
                                                llvm::Value *Address) const {
4924
0
4925
0
  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4926
0
}
4927
4928
//===----------------------------------------------------------------------===//
4929
// AArch64 ABI Implementation
4930
//===----------------------------------------------------------------------===//
4931
4932
namespace {
4933
4934
class AArch64ABIInfo : public SwiftABIInfo {
4935
public:
4936
  enum ABIKind {
4937
    AAPCS = 0,
4938
    DarwinPCS,
4939
    Win64
4940
  };
4941
4942
private:
4943
  ABIKind Kind;
4944
4945
public:
4946
  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4947
3.38k
    : SwiftABIInfo(CGT), Kind(Kind) {}
4948
4949
private:
4950
0
  ABIKind getABIKind() const { return Kind; }
4951
12.8k
  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4952
4953
  ABIArgInfo classifyReturnType(QualType RetTy) const;
4954
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
4955
  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4956
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4957
                                         uint64_t Members) const override;
4958
4959
  bool isIllegalVectorType(QualType Ty) const;
4960
4961
146k
  void computeInfo(CGFunctionInfo &FI) const override {
4962
146k
    if (!::classifyReturnType(getCXXABI(), FI, *this))
4963
144k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4964
146k
4965
146k
    for (auto &it : FI.arguments())
4966
293k
      it.info = classifyArgumentType(it.type);
4967
146k
  }
4968
4969
  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4970
                          CodeGenFunction &CGF) const;
4971
4972
  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4973
                         CodeGenFunction &CGF) const;
4974
4975
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4976
247
                    QualType Ty) const override {
4977
247
    return Kind == Win64 ? 
EmitMSVAArg(CGF, VAListAddr, Ty)3
4978
247
                         : 
isDarwinPCS() 244
?
EmitDarwinVAArg(VAListAddr, Ty, CGF)174
4979
244
                                         : 
EmitAAPCSVAArg(VAListAddr, Ty, CGF)70
;
4980
247
  }
4981
4982
  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4983
                      QualType Ty) const override;
4984
4985
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4986
298
                                    bool asReturnValue) const override {
4987
298
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4988
298
  }
4989
0
  bool isSwiftErrorInRegister() const override {
4990
0
    return true;
4991
0
  }
4992
4993
  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4994
                                 unsigned elts) const override;
4995
};
4996
4997
class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4998
public:
4999
  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
5000
3.38k
      : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
5001
5002
16
  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5003
16
    return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
5004
16
  }
5005
5006
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5007
0
    return 31;
5008
0
  }
5009
5010
22
  bool doesReturnSlotInterfereWithArgs() const override { return false; }
5011
5012
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5013
413k
                           CodeGen::CodeGenModule &CGM) const override {
5014
413k
    const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5015
413k
    if (!FD)
5016
53.1k
      return;
5017
360k
    llvm::Function *Fn = cast<llvm::Function>(GV);
5018
360k
5019
360k
    auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
5020
360k
    if (Kind != CodeGenOptions::SignReturnAddressScope::None) {
5021
62
      Fn->addFnAttr("sign-return-address",
5022
62
                    Kind == CodeGenOptions::SignReturnAddressScope::All
5023
62
                        ? 
"all"34
5024
62
                        : 
"non-leaf"28
);
5025
62
5026
62
      auto Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
5027
62
      Fn->addFnAttr("sign-return-address-key",
5028
62
                    Key == CodeGenOptions::SignReturnAddressKeyValue::AKey
5029
62
                        ? 
"a_key"40
5030
62
                        : 
"b_key"22
);
5031
62
    }
5032
360k
5033
360k
    if (CGM.getCodeGenOpts().BranchTargetEnforcement)
5034
20
      Fn->addFnAttr("branch-target-enforcement");
5035
360k
  }
5036
};
5037
5038
class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5039
public:
5040
  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
5041
28
      : AArch64TargetCodeGenInfo(CGT, K) {}
5042
5043
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5044
                           CodeGen::CodeGenModule &CGM) const override;
5045
5046
  void getDependentLibraryOption(llvm::StringRef Lib,
5047
4
                                 llvm::SmallString<24> &Opt) const override {
5048
4
    Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5049
4
  }
5050
5051
  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5052
0
                               llvm::SmallString<32> &Opt) const override {
5053
0
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5054
0
  }
5055
};
5056
5057
void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
5058
917
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5059
917
  AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5060
917
  if (GV->isDeclaration())
5061
492
    return;
5062
425
  addStackProbeTargetAttributes(D, GV, CGM);
5063
425
}
5064
}
5065
5066
293k
ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
5067
293k
  Ty = useFirstFieldIfTransparentUnion(Ty);
5068
293k
5069
293k
  // Handle illegal vector types here.
5070
293k
  if (isIllegalVectorType(Ty)) {
5071
80
    uint64_t Size = getContext().getTypeSize(Ty);
5072
80
    // Android promotes <2 x i8> to i16, not i32
5073
80
    if (isAndroid() && 
(Size <= 16)49
) {
5074
2
      llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5075
2
      return ABIArgInfo::getDirect(ResType);
5076
2
    }
5077
78
    if (Size <= 32) {
5078
12
      llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5079
12
      return ABIArgInfo::getDirect(ResType);
5080
12
    }
5081
66
    if (Size == 64) {
5082
16
      llvm::Type *ResType =
5083
16
          llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5084
16
      return ABIArgInfo::getDirect(ResType);
5085
16
    }
5086
50
    if (Size == 128) {
5087
24
      llvm::Type *ResType =
5088
24
          llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5089
24
      return ABIArgInfo::getDirect(ResType);
5090
24
    }
5091
26
    return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5092
26
  }
5093
293k
5094
293k
  if (!isAggregateTypeForABI(Ty)) {
5095
287k
    // Treat an enum type as its underlying type.
5096
287k
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5097
1.88k
      Ty = EnumTy->getDecl()->getIntegerType();
5098
287k
5099
287k
    return (Ty->isPromotableIntegerType() && 
isDarwinPCS()4.13k
5100
287k
                ? 
ABIArgInfo::getExtend(Ty)3.99k
5101
287k
                : 
ABIArgInfo::getDirect()283k
);
5102
287k
  }
5103
6.27k
5104
6.27k
  // Structures with either a non-trivial destructor or a non-trivial
5105
6.27k
  // copy constructor are always indirect.
5106
6.27k
  if (CGCXXABI::RecordArg