Coverage Report

Created: 2022-01-25 06:29

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/TargetID.cpp
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//===--- TargetID.cpp - Utilities for parsing target ID -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "clang/Basic/TargetID.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/Support/raw_ostream.h"
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#include <map>
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namespace clang {
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static llvm::SmallVector<llvm::StringRef, 4>
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getAllPossibleAMDGPUTargetIDFeatures(const llvm::Triple &T,
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                                     llvm::StringRef Proc) {
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  // Entries in returned vector should be in alphabetical order.
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  llvm::SmallVector<llvm::StringRef, 4> Ret;
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  auto ProcKind = T.isAMDGCN() ? 
llvm::AMDGPU::parseArchAMDGCN(Proc)524
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                               : 
llvm::AMDGPU::parseArchR600(Proc)79
;
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  if (ProcKind == llvm::AMDGPU::GK_NONE)
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    return Ret;
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  auto Features = T.isAMDGCN() ? 
llvm::AMDGPU::getArchAttrAMDGCN(ProcKind)524
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                               : 
llvm::AMDGPU::getArchAttrR600(ProcKind)52
;
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  if (Features & llvm::AMDGPU::FEATURE_SRAMECC)
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    Ret.push_back("sramecc");
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  if (Features & llvm::AMDGPU::FEATURE_XNACK)
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    Ret.push_back("xnack");
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  return Ret;
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}
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llvm::SmallVector<llvm::StringRef, 4>
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getAllPossibleTargetIDFeatures(const llvm::Triple &T,
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                               llvm::StringRef Processor) {
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  llvm::SmallVector<llvm::StringRef, 4> Ret;
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  if (T.isAMDGPU())
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    return getAllPossibleAMDGPUTargetIDFeatures(T, Processor);
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  return Ret;
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}
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/// Returns canonical processor name or empty string if \p Processor is invalid.
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static llvm::StringRef getCanonicalProcessorName(const llvm::Triple &T,
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                                                 llvm::StringRef Processor) {
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  if (T.isAMDGPU())
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    return llvm::AMDGPU::getCanonicalArchName(T, Processor);
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  return Processor;
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}
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llvm::StringRef getProcessorFromTargetID(const llvm::Triple &T,
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                                         llvm::StringRef TargetID) {
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  auto Split = TargetID.split(':');
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  return getCanonicalProcessorName(T, Split.first);
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}
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// Parse a target ID with format checking only. Do not check whether processor
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// name or features are valid for the processor.
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//
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// A target ID is a processor name followed by a list of target features
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// delimited by colon. Each target feature is a string post-fixed by a plus
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// or minus sign, e.g. gfx908:sramecc+:xnack-.
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static llvm::Optional<llvm::StringRef>
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parseTargetIDWithFormatCheckingOnly(llvm::StringRef TargetID,
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                                    llvm::StringMap<bool> *FeatureMap) {
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  llvm::StringRef Processor;
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  if (TargetID.empty())
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    return llvm::StringRef();
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  auto Split = TargetID.split(':');
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  Processor = Split.first;
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  if (Processor.empty())
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    return llvm::None;
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  auto Features = Split.second;
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  if (Features.empty())
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    return Processor;
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  llvm::StringMap<bool> LocalFeatureMap;
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  if (!FeatureMap)
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    FeatureMap = &LocalFeatureMap;
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  while (!Features.empty()) {
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    auto Splits = Features.split(':');
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    auto Sign = Splits.first.back();
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    auto Feature = Splits.first.drop_back();
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    if (Sign != '+' && 
Sign != '-'4
)
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      return llvm::None;
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    bool IsOn = Sign == '+';
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    auto Loc = FeatureMap->find(Feature);
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    // Each feature can only show up at most once in target ID.
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    if (Loc != FeatureMap->end())
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      return llvm::None;
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    (*FeatureMap)[Feature] = IsOn;
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    Features = Splits.second;
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  }
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  return Processor;
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}
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llvm::Optional<llvm::StringRef>
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parseTargetID(const llvm::Triple &T, llvm::StringRef TargetID,
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              llvm::StringMap<bool> *FeatureMap) {
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  auto OptionalProcessor =
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      parseTargetIDWithFormatCheckingOnly(TargetID, FeatureMap);
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  if (!OptionalProcessor)
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    return llvm::None;
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  llvm::StringRef Processor =
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      getCanonicalProcessorName(T, OptionalProcessor.getValue());
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  if (Processor.empty())
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    return llvm::None;
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  llvm::SmallSet<llvm::StringRef, 4> AllFeatures;
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  for (auto &&F : getAllPossibleTargetIDFeatures(T, Processor))
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    AllFeatures.insert(F);
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  for (auto &&F : *FeatureMap)
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    if (!AllFeatures.count(F.first()))
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      return llvm::None;
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  return Processor;
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}
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// A canonical target ID is a target ID containing a canonical processor name
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// and features in alphabetical order.
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std::string getCanonicalTargetID(llvm::StringRef Processor,
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                                 const llvm::StringMap<bool> &Features) {
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  std::string TargetID = Processor.str();
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  std::map<const llvm::StringRef, bool> OrderedMap;
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  for (const auto &F : Features)
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    OrderedMap[F.first()] = F.second;
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  for (auto F : OrderedMap)
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    TargetID = TargetID + ':' + F.first.str() + (F.second ? "+" : "-");
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  return TargetID;
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}
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// For a specific processor, a feature either shows up in all target IDs, or
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// does not show up in any target IDs. Otherwise the target ID combination
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// is invalid.
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llvm::Optional<std::pair<llvm::StringRef, llvm::StringRef>>
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getConflictTargetIDCombination(const std::set<llvm::StringRef> &TargetIDs) {
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  struct Info {
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    llvm::StringRef TargetID;
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    llvm::StringMap<bool> Features;
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  };
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  llvm::StringMap<Info> FeatureMap;
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  for (auto &&ID : TargetIDs) {
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    llvm::StringMap<bool> Features;
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    llvm::StringRef Proc =
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        parseTargetIDWithFormatCheckingOnly(ID, &Features).getValue();
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    auto Loc = FeatureMap.find(Proc);
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    if (Loc == FeatureMap.end())
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      FeatureMap[Proc] = Info{ID, Features};
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    else {
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      auto &ExistingFeatures = Loc->second.Features;
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      if (llvm::any_of(Features, [&](auto &F) {
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            return ExistingFeatures.count(F.first()) == 0;
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          }))
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        return std::make_pair(Loc->second.TargetID, ID);
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    }
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  }
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  return llvm::None;
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}
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} // namespace clang