Coverage Report

Created: 2021-01-26 06:56

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64.h"
14
#include "clang/Basic/LangOptions.h"
15
#include "clang/Basic/TargetBuiltins.h"
16
#include "clang/Basic/TargetInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/AArch64TargetParser.h"
21
22
using namespace clang;
23
using namespace clang::targets;
24
25
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#include "clang/Basic/BuiltinsNEON.def"
29
30
#define BUILTIN(ID, TYPE, ATTRS)                                               \
31
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
32
#include "clang/Basic/BuiltinsSVE.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
37
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsAArch64.def"
41
};
42
43
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
44
                                     const TargetOptions &Opts)
45
2.42k
    : TargetInfo(Triple), ABI("aapcs") {
46
2.42k
  if (getTriple().isOSOpenBSD()) {
47
4
    Int64Type = SignedLongLong;
48
4
    IntMaxType = SignedLongLong;
49
2.42k
  } else {
50
2.42k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()2.26k
)
51
2.25k
      WCharType = UnsignedInt;
52
53
2.42k
    Int64Type = SignedLong;
54
2.42k
    IntMaxType = SignedLong;
55
2.42k
  }
56
57
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
58
2.42k
  HasLegalHalfType = true;
59
2.42k
  HasFloat16 = true;
60
61
2.42k
  if (Triple.isArch64Bit())
62
2.41k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
63
14
  else
64
14
    LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
65
66
2.42k
  MaxVectorAlign = 128;
67
2.42k
  MaxAtomicInlineWidth = 128;
68
2.42k
  MaxAtomicPromoteWidth = 128;
69
70
2.42k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
71
2.42k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
72
73
2.42k
  BFloat16Width = BFloat16Align = 16;
74
2.42k
  BFloat16Format = &llvm::APFloat::BFloat();
75
76
  // Make __builtin_ms_va_list available.
77
2.42k
  HasBuiltinMSVaList = true;
78
79
  // Make the SVE types available.  Note that this deliberately doesn't
80
  // depend on SveMode, since in principle it should be possible to turn
81
  // SVE on and off within a translation unit.  It should also be possible
82
  // to compile the global declaration:
83
  //
84
  // __SVInt8_t *ptr;
85
  //
86
  // even without SVE.
87
2.42k
  HasAArch64SVETypes = true;
88
89
  // {} in inline assembly are neon specifiers, not assembly variant
90
  // specifiers.
91
2.42k
  NoAsmVariants = true;
92
93
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
94
  // contributes to the alignment of the containing aggregate in the same way
95
  // a plain (non bit-field) member of that type would, without exception for
96
  // zero-sized or anonymous bit-fields."
97
2.42k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
98
2.42k
  UseZeroLengthBitfieldAlignment = true;
99
100
  // AArch64 targets default to using the ARM C++ ABI.
101
2.42k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
102
103
2.42k
  if (Triple.getOS() == llvm::Triple::Linux)
104
1.92k
    this->MCountName = "\01_mcount";
105
503
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
106
254
    this->MCountName =
107
253
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
: "mcount";
108
2.42k
}
109
110
3.15k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
111
112
232
bool AArch64TargetInfo::setABI(const std::string &Name) {
113
232
  if (Name != "aapcs" && 
Name != "darwinpcs"22
)
114
0
    return false;
115
116
232
  ABI = Name;
117
232
  return true;
118
232
}
119
120
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec,
121
                                                 BranchProtectionInfo &BPI,
122
40
                                                 StringRef &Err) const {
123
40
  llvm::AArch64::ParsedBranchProtection PBP;
124
40
  if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
125
7
    return false;
126
127
33
  BPI.SignReturnAddr =
128
33
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
129
33
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
130
33
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
131
33
          .Default(LangOptions::SignReturnAddressScopeKind::None);
132
133
33
  if (PBP.Key == "a_key")
134
24
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
135
9
  else
136
9
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
137
138
33
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
139
33
  return true;
140
33
}
141
142
243
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
143
243
  return Name == "generic" ||
144
34
         llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
145
243
}
146
147
242
bool AArch64TargetInfo::setCPU(const std::string &Name) {
148
242
  return isValidCPUName(Name);
149
242
}
150
151
void AArch64TargetInfo::fillValidCPUList(
152
2
    SmallVectorImpl<StringRef> &Values) const {
153
2
  llvm::AArch64::fillValidCPUArchList(Values);
154
2
}
155
156
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
157
77
                                                MacroBuilder &Builder) const {
158
77
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
159
77
  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
160
77
  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
161
77
}
162
163
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
164
69
                                                MacroBuilder &Builder) const {
165
  // Also include the ARMv8.1 defines
166
69
  getTargetDefinesARMV81A(Opts, Builder);
167
69
}
168
169
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
170
24
                                                MacroBuilder &Builder) const {
171
24
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
172
24
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
173
  // Also include the Armv8.2 defines
174
24
  getTargetDefinesARMV82A(Opts, Builder);
175
24
}
176
177
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
178
22
                                                MacroBuilder &Builder) const {
179
  // Also include the Armv8.3 defines
180
22
  getTargetDefinesARMV83A(Opts, Builder);
181
22
}
182
183
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
184
11
                                                MacroBuilder &Builder) const {
185
  // Also include the Armv8.4 defines
186
11
  getTargetDefinesARMV84A(Opts, Builder);
187
11
}
188
189
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
190
6
                                                MacroBuilder &Builder) const {
191
  // Also include the Armv8.5 defines
192
  // FIXME: Armv8.6 makes the following extensions mandatory:
193
  // - __ARM_FEATURE_BF16
194
  // - __ARM_FEATURE_MATMUL_INT8
195
  // Handle them here.
196
6
  getTargetDefinesARMV85A(Opts, Builder);
197
6
}
198
199
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
200
2
                                                MacroBuilder &Builder) const {
201
  // Also include the Armv8.6 defines
202
2
  getTargetDefinesARMV86A(Opts, Builder);
203
2
}
204
205
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
206
2.41k
                                         MacroBuilder &Builder) const {
207
  // Target identification.
208
2.41k
  Builder.defineMacro("__aarch64__");
209
  // For bare-metal.
210
2.41k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
211
250
      getTriple().isOSBinFormatELF())
212
249
    Builder.defineMacro("__ELF__");
213
214
  // Target properties.
215
2.41k
  if (!getTriple().isOSWindows() && 
getTriple().isArch64Bit()2.37k
) {
216
2.35k
    Builder.defineMacro("_LP64");
217
2.35k
    Builder.defineMacro("__LP64__");
218
2.35k
  }
219
220
2.41k
  std::string CodeModel = getTargetOpts().CodeModel;
221
2.41k
  if (CodeModel == "default")
222
2.41k
    CodeModel = "small";
223
2.41k
  for (char &c : CodeModel)
224
12.0k
    c = toupper(c);
225
2.41k
  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
226
227
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
228
2.41k
  Builder.defineMacro("__ARM_ACLE", "200");
229
2.41k
  Builder.defineMacro("__ARM_ARCH", "8");
230
2.41k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
231
232
2.41k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
233
2.41k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
234
2.41k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
235
236
2.41k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
237
2.41k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
238
2.41k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
239
2.41k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
240
2.41k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
241
2.41k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
242
2.41k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
243
244
2.41k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
245
246
  // 0xe implies support for half, single and double precision operations.
247
2.41k
  Builder.defineMacro("__ARM_FP", "0xE");
248
249
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
250
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
251
2.41k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
252
2.41k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
253
254
2.41k
  if (Opts.UnsafeFPMath)
255
4
    Builder.defineMacro("__ARM_FP_FAST", "1");
256
257
2.41k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
258
2.41k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
: 4));
259
260
2.41k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
: "4");
261
262
2.41k
  if (FPU & NeonMode) {
263
331
    Builder.defineMacro("__ARM_NEON", "1");
264
    // 64-bit NEON supports half, single and double precision operations.
265
331
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
266
331
  }
267
268
2.41k
  if (FPU & SveMode)
269
1.63k
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
270
271
2.41k
  if (HasSVE2)
272
409
    Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
273
274
2.41k
  if (HasSVE2 && 
HasSVE2AES409
)
275
13
    Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
276
277
2.41k
  if (HasSVE2 && 
HasSVE2BitPerm409
)
278
7
    Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
279
280
2.41k
  if (HasSVE2 && 
HasSVE2SHA3409
)
281
3
    Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
282
283
2.41k
  if (HasSVE2 && 
HasSVE2SM4409
)
284
5
    Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
285
286
2.41k
  if (HasCRC)
287
4
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
288
289
2.41k
  if (HasCrypto)
290
17
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
291
292
2.41k
  if (HasUnaligned)
293
2.41k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
294
295
2.41k
  if ((FPU & NeonMode) && 
HasFullFP16331
)
296
76
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
297
2.41k
  if (HasFullFP16)
298
1.68k
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
299
300
2.41k
  if (HasDotProd)
301
5
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
302
303
2.41k
  if (HasMTE)
304
24
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
305
306
2.41k
  if (HasTME)
307
4
    Builder.defineMacro("__ARM_FEATURE_TME", "1");
308
309
2.41k
  if (HasMatMul)
310
11
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
311
312
2.41k
  if (HasLSE)
313
2
    Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
314
315
2.41k
  if (HasBFloat16) {
316
198
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
317
198
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
318
198
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
319
198
    Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
320
198
  }
321
322
2.41k
  if ((FPU & SveMode) && 
HasBFloat161.63k
) {
323
182
    Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
324
182
  }
325
326
2.41k
  if ((FPU & SveMode) && 
HasMatmulFP641.63k
)
327
31
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
328
329
2.41k
  if ((FPU & SveMode) && 
HasMatmulFP321.63k
)
330
4
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
331
332
2.41k
  if ((FPU & SveMode) && 
HasMatMul1.63k
)
333
8
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
334
335
2.41k
  if ((FPU & NeonMode) && 
HasFP16FML331
)
336
9
    Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
337
338
2.41k
  if (Opts.hasSignReturnAddress()) {
339
    // Bitmask:
340
    // 0: Protection using the A key
341
    // 1: Protection using the B key
342
    // 2: Protection including leaf functions
343
15
    unsigned Value = 0;
344
345
15
    if (Opts.isSignReturnAddressWithAKey())
346
10
      Value |= (1 << 0);
347
5
    else
348
5
      Value |= (1 << 1);
349
350
15
    if (Opts.isSignReturnAddressScopeAll())
351
6
      Value |= (1 << 2);
352
353
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
354
15
  }
355
356
2.41k
  if (Opts.BranchTargetEnforcement)
357
6
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
358
359
2.41k
  if (HasLS64)
360
5
    Builder.defineMacro("__ARM_FEATURE_LS64", "1");
361
362
2.41k
  switch (ArchKind) {
363
2.34k
  default:
364
2.34k
    break;
365
8
  case llvm::AArch64::ArchKind::ARMV8_1A:
366
8
    getTargetDefinesARMV81A(Opts, Builder);
367
8
    break;
368
45
  case llvm::AArch64::ArchKind::ARMV8_2A:
369
45
    getTargetDefinesARMV82A(Opts, Builder);
370
45
    break;
371
2
  case llvm::AArch64::ArchKind::ARMV8_3A:
372
2
    getTargetDefinesARMV83A(Opts, Builder);
373
2
    break;
374
11
  case llvm::AArch64::ArchKind::ARMV8_4A:
375
11
    getTargetDefinesARMV84A(Opts, Builder);
376
11
    break;
377
5
  case llvm::AArch64::ArchKind::ARMV8_5A:
378
5
    getTargetDefinesARMV85A(Opts, Builder);
379
5
    break;
380
4
  case llvm::AArch64::ArchKind::ARMV8_6A:
381
4
    getTargetDefinesARMV86A(Opts, Builder);
382
4
    break;
383
2
  case llvm::AArch64::ArchKind::ARMV8_7A:
384
2
    getTargetDefinesARMV87A(Opts, Builder);
385
2
    break;
386
2.41k
  }
387
388
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
389
2.41k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
390
2.41k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
391
2.41k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
392
2.41k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
393
394
2.41k
  if (Opts.ArmSveVectorBits) {
395
62
    Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits));
396
62
    Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS");
397
62
  }
398
2.41k
}
399
400
2.41k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
401
2.41k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
402
2.41k
                                             Builtin::FirstTSBuiltin);
403
2.41k
}
404
405
4.14k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
406
4.14k
  return Feature == "aarch64" || 
Feature == "arm64"4.13k
||
Feature == "arm"4.13k
||
407
4.12k
         (Feature == "neon" && 
(FPU & NeonMode)3.42k
) ||
408
774
         ((Feature == "sve" || 
Feature == "sve2"172
||
Feature == "sve2-bitperm"172
||
409
172
           Feature == "sve2-aes" || Feature == "sve2-sha3" ||
410
172
           Feature == "sve2-sm4" || Feature == "f64mm" || Feature == "f32mm" ||
411
172
           Feature == "i8mm" || Feature == "bf16") &&
412
602
          (FPU & SveMode));
413
4.14k
}
414
415
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
416
2.42k
                                             DiagnosticsEngine &Diags) {
417
2.42k
  FPU = FPUMode;
418
2.42k
  HasCRC = false;
419
2.42k
  HasCrypto = false;
420
2.42k
  HasUnaligned = true;
421
2.42k
  HasFullFP16 = false;
422
2.42k
  HasDotProd = false;
423
2.42k
  HasFP16FML = false;
424
2.42k
  HasMTE = false;
425
2.42k
  HasTME = false;
426
2.42k
  HasLS64 = false;
427
2.42k
  HasMatMul = false;
428
2.42k
  HasBFloat16 = false;
429
2.42k
  HasSVE2 = false;
430
2.42k
  HasSVE2AES = false;
431
2.42k
  HasSVE2SHA3 = false;
432
2.42k
  HasSVE2SM4 = false;
433
2.42k
  HasSVE2BitPerm = false;
434
2.42k
  HasMatmulFP64 = false;
435
2.42k
  HasMatmulFP32 = false;
436
2.42k
  HasLSE = false;
437
438
2.42k
  ArchKind = llvm::AArch64::ArchKind::ARMV8A;
439
440
2.50k
  for (const auto &Feature : Features) {
441
2.50k
    if (Feature == "+neon")
442
331
      FPU |= NeonMode;
443
2.50k
    if (Feature == "+sve") {
444
1.22k
      FPU |= SveMode;
445
1.22k
      HasFullFP16 = 1;
446
1.22k
    }
447
2.50k
    if (Feature == "+sve2") {
448
381
      FPU |= SveMode;
449
381
      HasFullFP16 = 1;
450
381
      HasSVE2 = 1;
451
381
    }
452
2.50k
    if (Feature == "+sve2-aes") {
453
13
      FPU |= SveMode;
454
13
      HasFullFP16 = 1;
455
13
      HasSVE2 = 1;
456
13
      HasSVE2AES = 1;
457
13
    }
458
2.50k
    if (Feature == "+sve2-sha3") {
459
3
      FPU |= SveMode;
460
3
      HasFullFP16 = 1;
461
3
      HasSVE2 = 1;
462
3
      HasSVE2SHA3 = 1;
463
3
    }
464
2.50k
    if (Feature == "+sve2-sm4") {
465
5
      FPU |= SveMode;
466
5
      HasFullFP16 = 1;
467
5
      HasSVE2 = 1;
468
5
      HasSVE2SM4 = 1;
469
5
    }
470
2.50k
    if (Feature == "+sve2-bitperm") {
471
7
      FPU |= SveMode;
472
7
      HasFullFP16 = 1;
473
7
      HasSVE2 = 1;
474
7
      HasSVE2BitPerm = 1;
475
7
    }
476
2.50k
    if (Feature == "+f32mm") {
477
4
      FPU |= SveMode;
478
4
      HasMatmulFP32 = true;
479
4
    }
480
2.50k
    if (Feature == "+f64mm") {
481
31
      FPU |= SveMode;
482
31
      HasMatmulFP64 = true;
483
31
    }
484
2.50k
    if (Feature == "+crc")
485
4
      HasCRC = true;
486
2.50k
    if (Feature == "+crypto")
487
17
      HasCrypto = true;
488
2.50k
    if (Feature == "+strict-align")
489
2
      HasUnaligned = false;
490
2.50k
    if (Feature == "+v8.1a")
491
8
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
492
2.50k
    if (Feature == "+v8.2a")
493
45
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
494
2.50k
    if (Feature == "+v8.3a")
495
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
496
2.50k
    if (Feature == "+v8.4a")
497
11
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
498
2.50k
    if (Feature == "+v8.5a")
499
5
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
500
2.50k
    if (Feature == "+v8.6a")
501
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
502
2.50k
    if (Feature == "+v8.7a")
503
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
504
2.50k
    if (Feature == "+v8r")
505
0
      ArchKind = llvm::AArch64::ArchKind::ARMV8R;
506
2.50k
    if (Feature == "+fullfp16")
507
56
      HasFullFP16 = true;
508
2.50k
    if (Feature == "+dotprod")
509
5
      HasDotProd = true;
510
2.50k
    if (Feature == "+fp16fml")
511
12
      HasFP16FML = true;
512
2.50k
    if (Feature == "+mte")
513
24
      HasMTE = true;
514
2.50k
    if (Feature == "+tme")
515
4
      HasTME = true;
516
2.50k
    if (Feature == "+pauth")
517
0
      HasPAuth = true;
518
2.50k
    if (Feature == "+i8mm")
519
11
      HasMatMul = true;
520
2.50k
    if (Feature == "+bf16")
521
198
      HasBFloat16 = true;
522
2.50k
    if (Feature == "+lse")
523
2
      HasLSE = true;
524
2.50k
    if (Feature == "+ls64")
525
5
      HasLS64 = true;
526
2.50k
    if (Feature == "+flagm")
527
0
      HasFlagM = true;
528
2.50k
  }
529
530
2.42k
  setDataLayout();
531
532
2.42k
  return true;
533
2.42k
}
534
535
TargetInfo::CallingConvCheckResult
536
343
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
537
343
  switch (CC) {
538
3
  case CC_C:
539
321
  case CC_Swift:
540
326
  case CC_PreserveMost:
541
332
  case CC_PreserveAll:
542
332
  case CC_OpenCLKernel:
543
340
  case CC_AArch64VectorCall:
544
343
  case CC_Win64:
545
343
    return CCCR_OK;
546
0
  default:
547
0
    return CCCR_Warning;
548
343
  }
549
343
}
550
551
24
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
552
553
2.18k
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
554
2.18k
  return TargetInfo::AArch64ABIBuiltinVaList;
555
2.18k
}
556
557
const char *const AArch64TargetInfo::GCCRegNames[] = {
558
    // 32-bit Integer registers
559
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
560
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
561
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
562
563
    // 64-bit Integer registers
564
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
565
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
566
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
567
568
    // 32-bit floating point regsisters
569
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
570
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
571
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
572
573
    // 64-bit floating point regsisters
574
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
575
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
576
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
577
578
    // Neon vector registers
579
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
580
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
581
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
582
583
    // SVE vector registers
584
    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
585
    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
586
    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
587
588
    // SVE predicate registers
589
    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
590
    "p11", "p12", "p13", "p14", "p15"
591
};
592
593
1.99k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
594
1.99k
  return llvm::makeArrayRef(GCCRegNames);
595
1.99k
}
596
597
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
598
    {{"w31"}, "wsp"},
599
    {{"x31"}, "sp"},
600
    // GCC rN registers are aliases of xN registers.
601
    {{"r0"}, "x0"},
602
    {{"r1"}, "x1"},
603
    {{"r2"}, "x2"},
604
    {{"r3"}, "x3"},
605
    {{"r4"}, "x4"},
606
    {{"r5"}, "x5"},
607
    {{"r6"}, "x6"},
608
    {{"r7"}, "x7"},
609
    {{"r8"}, "x8"},
610
    {{"r9"}, "x9"},
611
    {{"r10"}, "x10"},
612
    {{"r11"}, "x11"},
613
    {{"r12"}, "x12"},
614
    {{"r13"}, "x13"},
615
    {{"r14"}, "x14"},
616
    {{"r15"}, "x15"},
617
    {{"r16"}, "x16"},
618
    {{"r17"}, "x17"},
619
    {{"r18"}, "x18"},
620
    {{"r19"}, "x19"},
621
    {{"r20"}, "x20"},
622
    {{"r21"}, "x21"},
623
    {{"r22"}, "x22"},
624
    {{"r23"}, "x23"},
625
    {{"r24"}, "x24"},
626
    {{"r25"}, "x25"},
627
    {{"r26"}, "x26"},
628
    {{"r27"}, "x27"},
629
    {{"r28"}, "x28"},
630
    {{"r29", "x29"}, "fp"},
631
    {{"r30", "x30"}, "lr"},
632
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
633
    // don't want to substitute one of these for a different-sized one.
634
};
635
636
825
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
637
825
  return llvm::makeArrayRef(GCCRegAliases);
638
825
}
639
640
bool AArch64TargetInfo::validateAsmConstraint(
641
338
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
642
338
  switch (*Name) {
643
0
  default:
644
0
    return false;
645
284
  case 'w': // Floating point and SIMD registers (V0-V31)
646
284
    Info.setAllowsRegister();
647
284
    return true;
648
2
  case 'I': // Constant that can be used with an ADD instruction
649
2
  case 'J': // Constant that can be used with a SUB instruction
650
4
  case 'K': // Constant that can be used with a 32-bit logical instruction
651
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
652
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
653
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
654
6
  case 'Y': // Floating point constant zero
655
6
  case 'Z': // Integer constant zero
656
6
    return true;
657
4
  case 'Q': // A memory reference with base register and no offset
658
4
    Info.setAllowsMemory();
659
4
    return true;
660
2
  case 'S': // A symbolic address
661
2
    Info.setAllowsRegister();
662
2
    return true;
663
32
  case 'U':
664
32
    if (Name[1] == 'p' && (Name[2] == 'l' || 
Name[2] == 'a'24
)) {
665
      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
666
32
      Info.setAllowsRegister();
667
32
      Name += 2;
668
32
      return true;
669
32
    }
670
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
671
    // Utf: A memory address suitable for ldp/stp in TF mode.
672
    // Usa: An absolute symbolic address.
673
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
674
675
    // Better to return an error saying that it's an unrecognised constraint
676
    // even if this is a valid constraint in gcc.
677
0
    return false;
678
4
  case 'z': // Zero register, wzr or xzr
679
4
    Info.setAllowsRegister();
680
4
    return true;
681
0
  case 'x': // Floating point and SIMD registers (V0-V15)
682
0
    Info.setAllowsRegister();
683
0
    return true;
684
6
  case 'y': // SVE registers (V0-V7)
685
6
    Info.setAllowsRegister();
686
6
    return true;
687
0
  }
688
0
  return false;
689
0
}
690
691
bool AArch64TargetInfo::validateConstraintModifier(
692
    StringRef Constraint, char Modifier, unsigned Size,
693
226
    std::string &SuggestedModifier) const {
694
  // Strip off constraint modifiers.
695
334
  while (Constraint[0] == '=' || 
Constraint[0] == '+'234
||
Constraint[0] == '&'227
)
696
108
    Constraint = Constraint.substr(1);
697
698
226
  switch (Constraint[0]) {
699
185
  default:
700
185
    return true;
701
4
  case 'z':
702
41
  case 'r': {
703
41
    switch (Modifier) {
704
1
    case 'x':
705
7
    case 'w':
706
      // For now assume that the person knows what they're
707
      // doing with the modifier.
708
7
      return true;
709
34
    default:
710
      // By default an 'r' constraint will be in the 'x'
711
      // registers.
712
34
      if (Size == 64)
713
18
        return true;
714
715
16
      SuggestedModifier = "w";
716
16
      return false;
717
41
    }
718
41
  }
719
226
  }
720
226
}
721
722
100
const char *AArch64TargetInfo::getClobbers() const { return ""; }
723
724
0
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
725
0
  if (RegNo == 0)
726
0
    return 0;
727
0
  if (RegNo == 1)
728
0
    return 1;
729
0
  return -1;
730
0
}
731
732
7.17k
bool AArch64TargetInfo::hasInt128Type() const { return true; }
733
734
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
735
                                         const TargetOptions &Opts)
736
2.39k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
736
2.16k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
736
233
    : AArch64TargetInfo(Triple, Opts) {}
737
738
2.34k
void AArch64leTargetInfo::setDataLayout() {
739
2.34k
  if (getTriple().isOSBinFormatMachO()) {
740
161
    if(getTriple().isArch32Bit())
741
14
      resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128");
742
147
    else
743
147
      resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
744
161
  } else
745
2.18k
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
746
2.34k
}
747
748
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
749
2.38k
                                           MacroBuilder &Builder) const {
750
2.38k
  Builder.defineMacro("__AARCH64EL__");
751
2.38k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
752
2.38k
}
753
754
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
755
                                         const TargetOptions &Opts)
756
32
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
756
9
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
756
23
    : AArch64TargetInfo(Triple, Opts) {}
757
758
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
759
32
                                           MacroBuilder &Builder) const {
760
32
  Builder.defineMacro("__AARCH64EB__");
761
32
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
762
32
  Builder.defineMacro("__ARM_BIG_ENDIAN");
763
32
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
764
32
}
765
766
32
void AArch64beTargetInfo::setDataLayout() {
767
32
  assert(!getTriple().isOSBinFormatMachO());
768
32
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
769
32
}
770
771
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
772
                                               const TargetOptions &Opts)
773
45
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
774
775
  // This is an LLP64 platform.
776
  // int:4, long:4, long long:8, long double:8.
777
45
  IntWidth = IntAlign = 32;
778
45
  LongWidth = LongAlign = 32;
779
45
  DoubleAlign = LongLongAlign = 64;
780
45
  LongDoubleWidth = LongDoubleAlign = 64;
781
45
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
782
45
  IntMaxType = SignedLongLong;
783
45
  Int64Type = SignedLongLong;
784
45
  SizeType = UnsignedLongLong;
785
45
  PtrDiffType = SignedLongLong;
786
45
  IntPtrType = SignedLongLong;
787
45
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
773
45
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
774
775
  // This is an LLP64 platform.
776
  // int:4, long:4, long long:8, long double:8.
777
45
  IntWidth = IntAlign = 32;
778
45
  LongWidth = LongAlign = 32;
779
45
  DoubleAlign = LongLongAlign = 64;
780
45
  LongDoubleWidth = LongDoubleAlign = 64;
781
45
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
782
45
  IntMaxType = SignedLongLong;
783
45
  Int64Type = SignedLongLong;
784
45
  SizeType = UnsignedLongLong;
785
45
  PtrDiffType = SignedLongLong;
786
45
  IntPtrType = SignedLongLong;
787
45
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
788
789
45
void WindowsARM64TargetInfo::setDataLayout() {
790
45
  resetDataLayout(Triple.isOSBinFormatMachO()
791
1
                      ? "e-m:o-i64:64-i128:128-n32:64-S128"
792
44
                      : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128");
793
45
}
794
795
TargetInfo::BuiltinVaListKind
796
44
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
797
44
  return TargetInfo::CharPtrBuiltinVaList;
798
44
}
799
800
TargetInfo::CallingConvCheckResult
801
53
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
802
53
  switch (CC) {
803
3
  case CC_X86StdCall:
804
5
  case CC_X86ThisCall:
805
6
  case CC_X86FastCall:
806
7
  case CC_X86VectorCall:
807
7
    return CCCR_Ignore;
808
34
  case CC_C:
809
34
  case CC_OpenCLKernel:
810
39
  case CC_PreserveMost:
811
44
  case CC_PreserveAll:
812
46
  case CC_Swift:
813
46
  case CC_Win64:
814
46
    return CCCR_OK;
815
0
  default:
816
0
    return CCCR_Warning;
817
53
  }
818
53
}
819
820
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
821
                                                   const TargetOptions &Opts)
822
42
    : WindowsARM64TargetInfo(Triple, Opts) {
823
42
  TheCXXABI.set(TargetCXXABI::Microsoft);
824
42
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
822
42
    : WindowsARM64TargetInfo(Triple, Opts) {
823
42
  TheCXXABI.set(TargetCXXABI::Microsoft);
824
42
}
825
826
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
827
42
                                                MacroBuilder &Builder) const {
828
42
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
829
42
  Builder.defineMacro("_M_ARM64", "1");
830
42
}
831
832
TargetInfo::CallingConvKind
833
99
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
834
99
  return CCK_MicrosoftWin64;
835
99
}
836
837
163
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
838
163
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
839
840
  // MSVC does size based alignment for arm64 based on alignment section in
841
  // below document, replicate that to keep alignment consistent with object
842
  // files compiled by MSVC.
843
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
844
163
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
845
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
846
153
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
847
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
848
96
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
849
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
850
45
  }
851
163
  return Align;
852
163
}
853
854
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
855
                                           const TargetOptions &Opts)
856
3
    : WindowsARM64TargetInfo(Triple, Opts) {
857
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
858
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
856
3
    : WindowsARM64TargetInfo(Triple, Opts) {
857
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
858
3
}
859
860
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
861
                                                 const TargetOptions &Opts)
862
160
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
863
160
  Int64Type = SignedLongLong;
864
160
  if (getTriple().isArch32Bit())
865
14
    IntMaxType = SignedLongLong;
866
867
160
  WCharType = SignedInt;
868
160
  UseSignedCharForObjCBool = false;
869
870
160
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
871
160
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
872
873
160
  UseZeroLengthBitfieldAlignment = false;
874
875
160
  if (getTriple().isArch32Bit()) {
876
14
    UseBitFieldTypeAlignment = false;
877
14
    ZeroLengthBitfieldBoundary = 32;
878
14
    UseZeroLengthBitfieldAlignment = true;
879
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
880
14
  } else
881
146
    TheCXXABI.set(TargetCXXABI::AppleARM64);
882
160
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
862
160
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
863
160
  Int64Type = SignedLongLong;
864
160
  if (getTriple().isArch32Bit())
865
14
    IntMaxType = SignedLongLong;
866
867
160
  WCharType = SignedInt;
868
160
  UseSignedCharForObjCBool = false;
869
870
160
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
871
160
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
872
873
160
  UseZeroLengthBitfieldAlignment = false;
874
875
160
  if (getTriple().isArch32Bit()) {
876
14
    UseBitFieldTypeAlignment = false;
877
14
    ZeroLengthBitfieldBoundary = 32;
878
14
    UseZeroLengthBitfieldAlignment = true;
879
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
880
14
  } else
881
146
    TheCXXABI.set(TargetCXXABI::AppleARM64);
882
160
}
883
884
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
885
                                           const llvm::Triple &Triple,
886
160
                                           MacroBuilder &Builder) const {
887
160
  Builder.defineMacro("__AARCH64_SIMD__");
888
160
  if (Triple.isArch32Bit())
889
14
    Builder.defineMacro("__ARM64_ARCH_8_32__");
890
146
  else
891
146
    Builder.defineMacro("__ARM64_ARCH_8__");
892
160
  Builder.defineMacro("__ARM_NEON__");
893
160
  Builder.defineMacro("__LITTLE_ENDIAN__");
894
160
  Builder.defineMacro("__REGISTER_PREFIX__", "");
895
160
  Builder.defineMacro("__arm64", "1");
896
160
  Builder.defineMacro("__arm64__", "1");
897
898
160
  if (Triple.isArm64e())
899
3
    Builder.defineMacro("__arm64e__", "1");
900
901
160
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
902
160
}
903
904
TargetInfo::BuiltinVaListKind
905
177
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
906
177
  return TargetInfo::CharPtrBuiltinVaList;
907
177
}
908
909
// 64-bit RenderScript is aarch64
910
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
911
                                                   const TargetOptions &Opts)
912
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
913
                                       Triple.getOSName(),
914
                                       Triple.getEnvironmentName()),
915
1
                          Opts) {
916
1
  IsRenderScriptTarget = true;
917
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
915
1
                          Opts) {
916
1
  IsRenderScriptTarget = true;
917
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
918
919
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
920
1
                                                MacroBuilder &Builder) const {
921
1
  Builder.defineMacro("__RENDERSCRIPT__");
922
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
923
1
}