Coverage Report

Created: 2021-09-21 08:58

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64.h"
14
#include "clang/Basic/LangOptions.h"
15
#include "clang/Basic/TargetBuiltins.h"
16
#include "clang/Basic/TargetInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/AArch64TargetParser.h"
21
22
using namespace clang;
23
using namespace clang::targets;
24
25
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#include "clang/Basic/BuiltinsNEON.def"
29
30
#define BUILTIN(ID, TYPE, ATTRS)                                               \
31
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
32
#include "clang/Basic/BuiltinsSVE.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
37
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsAArch64.def"
41
};
42
43
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
44
                                     const TargetOptions &Opts)
45
3.33k
    : TargetInfo(Triple), ABI("aapcs") {
46
3.33k
  if (getTriple().isOSOpenBSD()) {
47
4
    Int64Type = SignedLongLong;
48
4
    IntMaxType = SignedLongLong;
49
3.33k
  } else {
50
3.33k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()3.15k
)
51
3.14k
      WCharType = UnsignedInt;
52
53
3.33k
    Int64Type = SignedLong;
54
3.33k
    IntMaxType = SignedLong;
55
3.33k
  }
56
57
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
58
3.33k
  HasLegalHalfType = true;
59
3.33k
  HasFloat16 = true;
60
61
3.33k
  if (Triple.isArch64Bit())
62
3.32k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
63
14
  else
64
14
    LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
65
66
3.33k
  MaxVectorAlign = 128;
67
3.33k
  MaxAtomicInlineWidth = 128;
68
3.33k
  MaxAtomicPromoteWidth = 128;
69
70
3.33k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
71
3.33k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
72
73
3.33k
  BFloat16Width = BFloat16Align = 16;
74
3.33k
  BFloat16Format = &llvm::APFloat::BFloat();
75
76
  // Make __builtin_ms_va_list available.
77
3.33k
  HasBuiltinMSVaList = true;
78
79
  // Make the SVE types available.  Note that this deliberately doesn't
80
  // depend on SveMode, since in principle it should be possible to turn
81
  // SVE on and off within a translation unit.  It should also be possible
82
  // to compile the global declaration:
83
  //
84
  // __SVInt8_t *ptr;
85
  //
86
  // even without SVE.
87
3.33k
  HasAArch64SVETypes = true;
88
89
  // {} in inline assembly are neon specifiers, not assembly variant
90
  // specifiers.
91
3.33k
  NoAsmVariants = true;
92
93
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
94
  // contributes to the alignment of the containing aggregate in the same way
95
  // a plain (non bit-field) member of that type would, without exception for
96
  // zero-sized or anonymous bit-fields."
97
3.33k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
98
0
  UseZeroLengthBitfieldAlignment = true;
99
100
  // AArch64 targets default to using the ARM C++ ABI.
101
3.33k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
102
103
3.33k
  if (Triple.getOS() == llvm::Triple::Linux)
104
2.80k
    this->MCountName = "\01_mcount";
105
533
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
106
264
    this->MCountName =
107
264
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
:
"mcount"263
;
108
3.33k
}
109
110
4.16k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
111
112
275
bool AArch64TargetInfo::setABI(const std::string &Name) {
113
275
  if (Name != "aapcs" && 
Name != "darwinpcs"25
)
114
0
    return false;
115
116
275
  ABI = Name;
117
275
  return true;
118
275
}
119
120
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec,
121
                                                 BranchProtectionInfo &BPI,
122
40
                                                 StringRef &Err) const {
123
40
  llvm::AArch64::ParsedBranchProtection PBP;
124
40
  if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
125
7
    return false;
126
127
33
  BPI.SignReturnAddr =
128
33
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
129
33
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
130
33
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
131
33
          .Default(LangOptions::SignReturnAddressScopeKind::None);
132
133
33
  if (PBP.Key == "a_key")
134
24
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
135
9
  else
136
9
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
137
138
33
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
139
33
  return true;
140
40
}
141
142
295
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
143
295
  return Name == "generic" ||
144
295
         
llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID46
;
145
295
}
146
147
294
bool AArch64TargetInfo::setCPU(const std::string &Name) {
148
294
  return isValidCPUName(Name);
149
294
}
150
151
void AArch64TargetInfo::fillValidCPUList(
152
2
    SmallVectorImpl<StringRef> &Values) const {
153
2
  llvm::AArch64::fillValidCPUArchList(Values);
154
2
}
155
156
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
157
88
                                                MacroBuilder &Builder) const {
158
88
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
159
88
  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
160
88
  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
161
88
}
162
163
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
164
80
                                                MacroBuilder &Builder) const {
165
  // Also include the ARMv8.1 defines
166
80
  getTargetDefinesARMV81A(Opts, Builder);
167
80
}
168
169
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
170
35
                                                MacroBuilder &Builder) const {
171
35
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
172
35
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
173
  // Also include the Armv8.2 defines
174
35
  getTargetDefinesARMV82A(Opts, Builder);
175
35
}
176
177
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
178
32
                                                MacroBuilder &Builder) const {
179
  // Also include the Armv8.3 defines
180
32
  getTargetDefinesARMV83A(Opts, Builder);
181
32
}
182
183
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
184
18
                                                MacroBuilder &Builder) const {
185
18
  Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
186
  // Also include the Armv8.4 defines
187
18
  getTargetDefinesARMV84A(Opts, Builder);
188
18
}
189
190
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
191
6
                                                MacroBuilder &Builder) const {
192
  // Also include the Armv8.5 defines
193
  // FIXME: Armv8.6 makes the following extensions mandatory:
194
  // - __ARM_FEATURE_BF16
195
  // - __ARM_FEATURE_MATMUL_INT8
196
  // Handle them here.
197
6
  getTargetDefinesARMV85A(Opts, Builder);
198
6
}
199
200
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
201
2
                                                MacroBuilder &Builder) const {
202
  // Also include the Armv8.6 defines
203
2
  getTargetDefinesARMV86A(Opts, Builder);
204
2
}
205
206
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
207
3.33k
                                         MacroBuilder &Builder) const {
208
  // Target identification.
209
3.33k
  Builder.defineMacro("__aarch64__");
210
  // For bare-metal.
211
3.33k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
212
3.33k
      
getTriple().isOSBinFormatELF()259
)
213
258
    Builder.defineMacro("__ELF__");
214
215
  // Target properties.
216
3.33k
  if (!getTriple().isOSWindows() && 
getTriple().isArch64Bit()3.28k
) {
217
3.26k
    Builder.defineMacro("_LP64");
218
3.26k
    Builder.defineMacro("__LP64__");
219
3.26k
  }
220
221
3.33k
  std::string CodeModel = getTargetOpts().CodeModel;
222
3.33k
  if (CodeModel == "default")
223
3.32k
    CodeModel = "small";
224
3.33k
  for (char &c : CodeModel)
225
16.6k
    c = toupper(c);
226
3.33k
  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
227
228
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
229
3.33k
  Builder.defineMacro("__ARM_ACLE", "200");
230
3.33k
  Builder.defineMacro("__ARM_ARCH", "8");
231
3.33k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
232
233
3.33k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
234
3.33k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
235
3.33k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
236
237
3.33k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
238
3.33k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
239
3.33k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
240
3.33k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
241
3.33k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
242
3.33k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
243
3.33k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
244
245
3.33k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
246
247
  // 0xe implies support for half, single and double precision operations.
248
3.33k
  Builder.defineMacro("__ARM_FP", "0xE");
249
250
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
251
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
252
3.33k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
253
3.33k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
254
255
3.33k
  if (Opts.UnsafeFPMath)
256
4
    Builder.defineMacro("__ARM_FP_FAST", "1");
257
258
3.33k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
259
3.33k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
43.32k
));
260
261
3.33k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"3.32k
);
262
263
3.33k
  if (FPU & NeonMode) {
264
380
    Builder.defineMacro("__ARM_NEON", "1");
265
    // 64-bit NEON supports half, single and double precision operations.
266
380
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
267
380
  }
268
269
3.33k
  if (FPU & SveMode)
270
2.46k
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
271
272
3.33k
  if (HasSVE2)
273
724
    Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
274
275
3.33k
  if (HasSVE2 && 
HasSVE2AES724
)
276
25
    Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
277
278
3.33k
  if (HasSVE2 && 
HasSVE2BitPerm724
)
279
13
    Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
280
281
3.33k
  if (HasSVE2 && 
HasSVE2SHA3724
)
282
5
    Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
283
284
3.33k
  if (HasSVE2 && 
HasSVE2SM4724
)
285
9
    Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
286
287
3.33k
  if (HasCRC)
288
6
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
289
290
  // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
291
  // macros for AES, SHA2, SHA3 and SM4
292
3.33k
  if (HasAES && 
HasSHA221
)
293
20
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
294
295
3.33k
  if (HasAES)
296
21
    Builder.defineMacro("__ARM_FEATURE_AES", "1");
297
298
3.33k
  if (HasSHA2)
299
24
    Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
300
301
3.33k
  if (HasSHA3) {
302
5
    Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
303
5
    Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
304
5
  }
305
306
3.33k
  if (HasSM4) {
307
5
    Builder.defineMacro("__ARM_FEATURE_SM3", "1");
308
5
    Builder.defineMacro("__ARM_FEATURE_SM4", "1");
309
5
  }
310
311
3.33k
  if (HasUnaligned)
312
3.32k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
313
314
3.33k
  if ((FPU & NeonMode) && 
HasFullFP16380
)
315
77
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
316
3.33k
  if (HasFullFP16)
317
2.51k
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
318
319
3.33k
  if (HasDotProd)
320
6
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
321
322
3.33k
  if (HasMTE)
323
24
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
324
325
3.33k
  if (HasTME)
326
4
    Builder.defineMacro("__ARM_FEATURE_TME", "1");
327
328
3.33k
  if (HasMatMul)
329
17
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
330
331
3.33k
  if (HasLSE)
332
3
    Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
333
334
3.33k
  if (HasBFloat16) {
335
322
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
336
322
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
337
322
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
338
322
    Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
339
322
  }
340
341
3.33k
  if ((FPU & SveMode) && 
HasBFloat162.46k
) {
342
306
    Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
343
306
  }
344
345
3.33k
  if ((FPU & SveMode) && 
HasMatmulFP642.46k
)
346
61
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
347
348
3.33k
  if ((FPU & SveMode) && 
HasMatmulFP322.46k
)
349
6
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
350
351
3.33k
  if ((FPU & SveMode) && 
HasMatMul2.46k
)
352
14
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
353
354
3.33k
  if ((FPU & NeonMode) && 
HasFP16FML380
)
355
10
    Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
356
357
3.33k
  if (Opts.hasSignReturnAddress()) {
358
    // Bitmask:
359
    // 0: Protection using the A key
360
    // 1: Protection using the B key
361
    // 2: Protection including leaf functions
362
15
    unsigned Value = 0;
363
364
15
    if (Opts.isSignReturnAddressWithAKey())
365
10
      Value |= (1 << 0);
366
5
    else
367
5
      Value |= (1 << 1);
368
369
15
    if (Opts.isSignReturnAddressScopeAll())
370
6
      Value |= (1 << 2);
371
372
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
373
15
  }
374
375
3.33k
  if (Opts.BranchTargetEnforcement)
376
6
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
377
378
3.33k
  if (HasLS64)
379
6
    Builder.defineMacro("__ARM_FEATURE_LS64", "1");
380
381
3.33k
  if (HasRandGen)
382
2
    Builder.defineMacro("__ARM_FEATURE_RNG", "1");
383
384
3.33k
  switch (ArchKind) {
385
3.24k
  default:
386
3.24k
    break;
387
3.24k
  case llvm::AArch64::ArchKind::ARMV8_1A:
388
8
    getTargetDefinesARMV81A(Opts, Builder);
389
8
    break;
390
45
  case llvm::AArch64::ArchKind::ARMV8_2A:
391
45
    getTargetDefinesARMV82A(Opts, Builder);
392
45
    break;
393
3
  case llvm::AArch64::ArchKind::ARMV8_3A:
394
3
    getTargetDefinesARMV83A(Opts, Builder);
395
3
    break;
396
14
  case llvm::AArch64::ArchKind::ARMV8_4A:
397
14
    getTargetDefinesARMV84A(Opts, Builder);
398
14
    break;
399
12
  case llvm::AArch64::ArchKind::ARMV8_5A:
400
12
    getTargetDefinesARMV85A(Opts, Builder);
401
12
    break;
402
4
  case llvm::AArch64::ArchKind::ARMV8_6A:
403
4
    getTargetDefinesARMV86A(Opts, Builder);
404
4
    break;
405
2
  case llvm::AArch64::ArchKind::ARMV8_7A:
406
2
    getTargetDefinesARMV87A(Opts, Builder);
407
2
    break;
408
3.33k
  }
409
410
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
411
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
412
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
413
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
414
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
415
416
3.33k
  if (Opts.ArmSveVectorBits) {
417
73
    Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits));
418
73
    Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS");
419
73
  }
420
3.33k
}
421
422
3.33k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
423
3.33k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
424
3.33k
                                             Builtin::FirstTSBuiltin);
425
3.33k
}
426
427
Optional<std::pair<unsigned, unsigned>>
428
41.8k
AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
429
41.8k
  if (LangOpts.ArmSveVectorBits) {
430
177
    unsigned VScale = LangOpts.ArmSveVectorBits / 128;
431
177
    return std::pair<unsigned, unsigned>(VScale, VScale);
432
177
  }
433
41.6k
  if (hasFeature("sve"))
434
29.4k
    return std::pair<unsigned, unsigned>(0, 16);
435
12.1k
  return None;
436
41.6k
}
437
438
46.0k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
439
46.0k
  return Feature == "aarch64" || 
Feature == "arm64"46.0k
||
Feature == "arm"46.0k
||
440
46.0k
         
(46.0k
Feature == "neon"46.0k
&&
(FPU & NeonMode)3.62k
) ||
441
46.0k
         
(42.4k
(42.4k
Feature == "sve"42.4k
||
Feature == "sve2"261
||
Feature == "sve2-bitperm"261
||
442
42.4k
           
Feature == "sve2-aes"261
||
Feature == "sve2-sha3"261
||
443
42.4k
           
Feature == "sve2-sm4"261
||
Feature == "f64mm"261
||
Feature == "f32mm"261
||
444
42.4k
           
Feature == "i8mm"261
||
Feature == "bf16"261
) &&
445
42.4k
          
(FPU & SveMode)42.2k
) ||
446
46.0k
         
(12.4k
Feature == "ls64"12.4k
&&
HasLS6489
);
447
46.0k
}
448
449
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
450
3.33k
                                             DiagnosticsEngine &Diags) {
451
3.33k
  FPU = FPUMode;
452
3.33k
  HasCRC = false;
453
3.33k
  HasCrypto = false;
454
3.33k
  HasAES = false;
455
3.33k
  HasSHA2 = false;
456
3.33k
  HasSHA3 = false;
457
3.33k
  HasSM4 = false;
458
3.33k
  HasUnaligned = true;
459
3.33k
  HasFullFP16 = false;
460
3.33k
  HasDotProd = false;
461
3.33k
  HasFP16FML = false;
462
3.33k
  HasMTE = false;
463
3.33k
  HasTME = false;
464
3.33k
  HasLS64 = false;
465
3.33k
  HasRandGen = false;
466
3.33k
  HasMatMul = false;
467
3.33k
  HasBFloat16 = false;
468
3.33k
  HasSVE2 = false;
469
3.33k
  HasSVE2AES = false;
470
3.33k
  HasSVE2SHA3 = false;
471
3.33k
  HasSVE2SM4 = false;
472
3.33k
  HasSVE2BitPerm = false;
473
3.33k
  HasMatmulFP64 = false;
474
3.33k
  HasMatmulFP32 = false;
475
3.33k
  HasLSE = false;
476
477
3.33k
  ArchKind = llvm::AArch64::ArchKind::ARMV8A;
478
479
3.61k
  for (const auto &Feature : Features) {
480
3.61k
    if (Feature == "+neon")
481
380
      FPU |= NeonMode;
482
3.61k
    if (Feature == "+sve") {
483
1.73k
      FPU |= SveMode;
484
1.73k
      HasFullFP16 = 1;
485
1.73k
    }
486
3.61k
    if (Feature == "+sve2") {
487
672
      FPU |= SveMode;
488
672
      HasFullFP16 = 1;
489
672
      HasSVE2 = 1;
490
672
    }
491
3.61k
    if (Feature == "+sve2-aes") {
492
25
      FPU |= SveMode;
493
25
      HasFullFP16 = 1;
494
25
      HasSVE2 = 1;
495
25
      HasSVE2AES = 1;
496
25
    }
497
3.61k
    if (Feature == "+sve2-sha3") {
498
5
      FPU |= SveMode;
499
5
      HasFullFP16 = 1;
500
5
      HasSVE2 = 1;
501
5
      HasSVE2SHA3 = 1;
502
5
    }
503
3.61k
    if (Feature == "+sve2-sm4") {
504
9
      FPU |= SveMode;
505
9
      HasFullFP16 = 1;
506
9
      HasSVE2 = 1;
507
9
      HasSVE2SM4 = 1;
508
9
    }
509
3.61k
    if (Feature == "+sve2-bitperm") {
510
13
      FPU |= SveMode;
511
13
      HasFullFP16 = 1;
512
13
      HasSVE2 = 1;
513
13
      HasSVE2BitPerm = 1;
514
13
    }
515
3.61k
    if (Feature == "+f32mm") {
516
6
      FPU |= SveMode;
517
6
      HasMatmulFP32 = true;
518
6
    }
519
3.61k
    if (Feature == "+f64mm") {
520
61
      FPU |= SveMode;
521
61
      HasMatmulFP64 = true;
522
61
    }
523
3.61k
    if (Feature == "+crc")
524
6
      HasCRC = true;
525
3.61k
    if (Feature == "+crypto")
526
18
      HasCrypto = true;
527
3.61k
    if (Feature == "+aes")
528
21
      HasAES = true;
529
3.61k
    if (Feature == "+sha2")
530
21
      HasSHA2 = true;
531
3.61k
    if (Feature == "+sha3") {
532
5
      HasSHA2 = true;
533
5
      HasSHA3 = true;
534
5
    }
535
3.61k
    if (Feature == "+sm4")
536
5
      HasSM4 = true;
537
3.61k
    if (Feature == "+strict-align")
538
2
      HasUnaligned = false;
539
3.61k
    if (Feature == "+v8.1a")
540
8
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
541
3.61k
    if (Feature == "+v8.2a")
542
45
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
543
3.61k
    if (Feature == "+v8.3a")
544
3
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
545
3.61k
    if (Feature == "+v8.4a")
546
14
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
547
3.61k
    if (Feature == "+v8.5a")
548
12
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
549
3.61k
    if (Feature == "+v8.6a")
550
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
551
3.61k
    if (Feature == "+v8.7a")
552
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
553
3.61k
    if (Feature == "+v8r")
554
0
      ArchKind = llvm::AArch64::ArchKind::ARMV8R;
555
3.61k
    if (Feature == "+fullfp16")
556
57
      HasFullFP16 = true;
557
3.61k
    if (Feature == "+dotprod")
558
6
      HasDotProd = true;
559
3.61k
    if (Feature == "+fp16fml")
560
13
      HasFP16FML = true;
561
3.61k
    if (Feature == "+mte")
562
24
      HasMTE = true;
563
3.61k
    if (Feature == "+tme")
564
4
      HasTME = true;
565
3.61k
    if (Feature == "+pauth")
566
0
      HasPAuth = true;
567
3.61k
    if (Feature == "+i8mm")
568
17
      HasMatMul = true;
569
3.61k
    if (Feature == "+bf16")
570
322
      HasBFloat16 = true;
571
3.61k
    if (Feature == "+lse")
572
3
      HasLSE = true;
573
3.61k
    if (Feature == "+ls64")
574
6
      HasLS64 = true;
575
3.61k
    if (Feature == "+rand")
576
2
      HasRandGen = true;
577
3.61k
    if (Feature == "+flagm")
578
0
      HasFlagM = true;
579
3.61k
  }
580
581
3.33k
  setDataLayout();
582
583
3.33k
  return true;
584
3.33k
}
585
586
TargetInfo::CallingConvCheckResult
587
438
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
588
438
  switch (CC) {
589
3
  case CC_C:
590
323
  case CC_Swift:
591
412
  case CC_SwiftAsync:
592
417
  case CC_PreserveMost:
593
423
  case CC_PreserveAll:
594
423
  case CC_OpenCLKernel:
595
431
  case CC_AArch64VectorCall:
596
438
  case CC_Win64:
597
438
    return CCCR_OK;
598
0
  default:
599
0
    return CCCR_Warning;
600
438
  }
601
438
}
602
603
33
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
604
605
3.07k
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
606
3.07k
  return TargetInfo::AArch64ABIBuiltinVaList;
607
3.07k
}
608
609
const char *const AArch64TargetInfo::GCCRegNames[] = {
610
    // 32-bit Integer registers
611
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
612
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
613
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
614
615
    // 64-bit Integer registers
616
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
617
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
618
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
619
620
    // 32-bit floating point regsisters
621
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
622
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
623
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
624
625
    // 64-bit floating point regsisters
626
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
627
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
628
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
629
630
    // Neon vector registers
631
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
632
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
633
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
634
635
    // SVE vector registers
636
    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
637
    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
638
    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
639
640
    // SVE predicate registers
641
    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
642
    "p11", "p12", "p13", "p14", "p15"
643
};
644
645
2.00k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
646
2.00k
  return llvm::makeArrayRef(GCCRegNames);
647
2.00k
}
648
649
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
650
    {{"w31"}, "wsp"},
651
    {{"x31"}, "sp"},
652
    // GCC rN registers are aliases of xN registers.
653
    {{"r0"}, "x0"},
654
    {{"r1"}, "x1"},
655
    {{"r2"}, "x2"},
656
    {{"r3"}, "x3"},
657
    {{"r4"}, "x4"},
658
    {{"r5"}, "x5"},
659
    {{"r6"}, "x6"},
660
    {{"r7"}, "x7"},
661
    {{"r8"}, "x8"},
662
    {{"r9"}, "x9"},
663
    {{"r10"}, "x10"},
664
    {{"r11"}, "x11"},
665
    {{"r12"}, "x12"},
666
    {{"r13"}, "x13"},
667
    {{"r14"}, "x14"},
668
    {{"r15"}, "x15"},
669
    {{"r16"}, "x16"},
670
    {{"r17"}, "x17"},
671
    {{"r18"}, "x18"},
672
    {{"r19"}, "x19"},
673
    {{"r20"}, "x20"},
674
    {{"r21"}, "x21"},
675
    {{"r22"}, "x22"},
676
    {{"r23"}, "x23"},
677
    {{"r24"}, "x24"},
678
    {{"r25"}, "x25"},
679
    {{"r26"}, "x26"},
680
    {{"r27"}, "x27"},
681
    {{"r28"}, "x28"},
682
    {{"r29", "x29"}, "fp"},
683
    {{"r30", "x30"}, "lr"},
684
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
685
    // don't want to substitute one of these for a different-sized one.
686
};
687
688
828
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
689
828
  return llvm::makeArrayRef(GCCRegAliases);
690
828
}
691
692
bool AArch64TargetInfo::validateAsmConstraint(
693
338
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
694
338
  switch (*Name) {
695
0
  default:
696
0
    return false;
697
284
  case 'w': // Floating point and SIMD registers (V0-V31)
698
284
    Info.setAllowsRegister();
699
284
    return true;
700
2
  case 'I': // Constant that can be used with an ADD instruction
701
2
  case 'J': // Constant that can be used with a SUB instruction
702
4
  case 'K': // Constant that can be used with a 32-bit logical instruction
703
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
704
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
705
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
706
6
  case 'Y': // Floating point constant zero
707
6
  case 'Z': // Integer constant zero
708
6
    return true;
709
4
  case 'Q': // A memory reference with base register and no offset
710
4
    Info.setAllowsMemory();
711
4
    return true;
712
2
  case 'S': // A symbolic address
713
2
    Info.setAllowsRegister();
714
2
    return true;
715
32
  case 'U':
716
32
    if (Name[1] == 'p' && (Name[2] == 'l' || 
Name[2] == 'a'24
)) {
717
      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
718
32
      Info.setAllowsRegister();
719
32
      Name += 2;
720
32
      return true;
721
32
    }
722
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
723
    // Utf: A memory address suitable for ldp/stp in TF mode.
724
    // Usa: An absolute symbolic address.
725
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
726
727
    // Better to return an error saying that it's an unrecognised constraint
728
    // even if this is a valid constraint in gcc.
729
0
    return false;
730
4
  case 'z': // Zero register, wzr or xzr
731
4
    Info.setAllowsRegister();
732
4
    return true;
733
0
  case 'x': // Floating point and SIMD registers (V0-V15)
734
0
    Info.setAllowsRegister();
735
0
    return true;
736
6
  case 'y': // SVE registers (V0-V7)
737
6
    Info.setAllowsRegister();
738
6
    return true;
739
338
  }
740
0
  return false;
741
338
}
742
743
bool AArch64TargetInfo::validateConstraintModifier(
744
    StringRef Constraint, char Modifier, unsigned Size,
745
232
    std::string &SuggestedModifier) const {
746
  // Strip off constraint modifiers.
747
341
  while (Constraint[0] == '=' || 
Constraint[0] == '+'240
||
Constraint[0] == '&'233
)
748
109
    Constraint = Constraint.substr(1);
749
750
232
  switch (Constraint[0]) {
751
185
  default:
752
185
    return true;
753
4
  case 'z':
754
47
  case 'r': {
755
47
    switch (Modifier) {
756
1
    case 'x':
757
7
    case 'w':
758
      // For now assume that the person knows what they're
759
      // doing with the modifier.
760
7
      return true;
761
40
    default:
762
      // By default an 'r' constraint will be in the 'x'
763
      // registers.
764
40
      if (Size == 64)
765
21
        return true;
766
767
19
      if (Size == 512)
768
3
        return HasLS64;
769
770
16
      SuggestedModifier = "w";
771
16
      return false;
772
47
    }
773
47
  }
774
232
  }
775
232
}
776
777
103
const char *AArch64TargetInfo::getClobbers() const { return ""; }
778
779
0
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
780
0
  if (RegNo == 0)
781
0
    return 0;
782
0
  if (RegNo == 1)
783
0
    return 1;
784
0
  return -1;
785
0
}
786
787
9.89k
bool AArch64TargetInfo::hasInt128Type() const { return true; }
788
789
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
790
                                         const TargetOptions &Opts)
791
3.30k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
791
3.06k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
791
243
    : AArch64TargetInfo(Triple, Opts) {}
792
793
3.25k
void AArch64leTargetInfo::setDataLayout() {
794
3.25k
  if (getTriple().isOSBinFormatMachO()) {
795
179
    if(getTriple().isArch32Bit())
796
14
      resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
797
165
    else
798
165
      resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
799
179
  } else
800
3.07k
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
801
3.25k
}
802
803
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
804
3.29k
                                           MacroBuilder &Builder) const {
805
3.29k
  Builder.defineMacro("__AARCH64EL__");
806
3.29k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
807
3.29k
}
808
809
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
810
                                         const TargetOptions &Opts)
811
33
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
811
10
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
811
23
    : AArch64TargetInfo(Triple, Opts) {}
812
813
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
814
33
                                           MacroBuilder &Builder) const {
815
33
  Builder.defineMacro("__AARCH64EB__");
816
33
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
817
33
  Builder.defineMacro("__ARM_BIG_ENDIAN");
818
33
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
819
33
}
820
821
33
void AArch64beTargetInfo::setDataLayout() {
822
33
  assert(!getTriple().isOSBinFormatMachO());
823
0
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
824
33
}
825
826
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
827
                                               const TargetOptions &Opts)
828
47
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
829
830
  // This is an LLP64 platform.
831
  // int:4, long:4, long long:8, long double:8.
832
47
  IntWidth = IntAlign = 32;
833
47
  LongWidth = LongAlign = 32;
834
47
  DoubleAlign = LongLongAlign = 64;
835
47
  LongDoubleWidth = LongDoubleAlign = 64;
836
47
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
837
47
  IntMaxType = SignedLongLong;
838
47
  Int64Type = SignedLongLong;
839
47
  SizeType = UnsignedLongLong;
840
47
  PtrDiffType = SignedLongLong;
841
47
  IntPtrType = SignedLongLong;
842
47
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
828
47
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
829
830
  // This is an LLP64 platform.
831
  // int:4, long:4, long long:8, long double:8.
832
47
  IntWidth = IntAlign = 32;
833
47
  LongWidth = LongAlign = 32;
834
47
  DoubleAlign = LongLongAlign = 64;
835
47
  LongDoubleWidth = LongDoubleAlign = 64;
836
47
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
837
47
  IntMaxType = SignedLongLong;
838
47
  Int64Type = SignedLongLong;
839
47
  SizeType = UnsignedLongLong;
840
47
  PtrDiffType = SignedLongLong;
841
47
  IntPtrType = SignedLongLong;
842
47
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
843
844
47
void WindowsARM64TargetInfo::setDataLayout() {
845
47
  resetDataLayout(Triple.isOSBinFormatMachO()
846
47
                      ? 
"e-m:o-i64:64-i128:128-n32:64-S128"1
847
47
                      : 
"e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"46
,
848
47
                  Triple.isOSBinFormatMachO() ? 
"_"1
:
""46
);
849
47
}
850
851
TargetInfo::BuiltinVaListKind
852
49
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
853
49
  return TargetInfo::CharPtrBuiltinVaList;
854
49
}
855
856
TargetInfo::CallingConvCheckResult
857
62
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
858
62
  switch (CC) {
859
3
  case CC_X86StdCall:
860
5
  case CC_X86ThisCall:
861
6
  case CC_X86FastCall:
862
7
  case CC_X86VectorCall:
863
7
    return CCCR_Ignore;
864
42
  case CC_C:
865
42
  case CC_OpenCLKernel:
866
47
  case CC_PreserveMost:
867
52
  case CC_PreserveAll:
868
54
  case CC_Swift:
869
55
  case CC_SwiftAsync:
870
55
  case CC_Win64:
871
55
    return CCCR_OK;
872
0
  default:
873
0
    return CCCR_Warning;
874
62
  }
875
62
}
876
877
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
878
                                                   const TargetOptions &Opts)
879
44
    : WindowsARM64TargetInfo(Triple, Opts) {
880
44
  TheCXXABI.set(TargetCXXABI::Microsoft);
881
44
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
879
44
    : WindowsARM64TargetInfo(Triple, Opts) {
880
44
  TheCXXABI.set(TargetCXXABI::Microsoft);
881
44
}
882
883
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
884
44
                                                MacroBuilder &Builder) const {
885
44
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
886
44
  Builder.defineMacro("_M_ARM64", "1");
887
44
}
888
889
TargetInfo::CallingConvKind
890
105
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
891
105
  return CCK_MicrosoftWin64;
892
105
}
893
894
163
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
895
163
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
896
897
  // MSVC does size based alignment for arm64 based on alignment section in
898
  // below document, replicate that to keep alignment consistent with object
899
  // files compiled by MSVC.
900
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
901
163
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
902
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
903
153
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
904
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
905
96
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
906
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
907
45
  }
908
163
  return Align;
909
163
}
910
911
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
912
                                           const TargetOptions &Opts)
913
3
    : WindowsARM64TargetInfo(Triple, Opts) {
914
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
915
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
913
3
    : WindowsARM64TargetInfo(Triple, Opts) {
914
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
915
3
}
916
917
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
918
                                                 const TargetOptions &Opts)
919
178
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
920
178
  Int64Type = SignedLongLong;
921
178
  if (getTriple().isArch32Bit())
922
14
    IntMaxType = SignedLongLong;
923
924
178
  WCharType = SignedInt;
925
178
  UseSignedCharForObjCBool = false;
926
927
178
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
928
178
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
929
930
178
  UseZeroLengthBitfieldAlignment = false;
931
932
178
  if (getTriple().isArch32Bit()) {
933
14
    UseBitFieldTypeAlignment = false;
934
14
    ZeroLengthBitfieldBoundary = 32;
935
14
    UseZeroLengthBitfieldAlignment = true;
936
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
937
14
  } else
938
164
    TheCXXABI.set(TargetCXXABI::AppleARM64);
939
178
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
919
178
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
920
178
  Int64Type = SignedLongLong;
921
178
  if (getTriple().isArch32Bit())
922
14
    IntMaxType = SignedLongLong;
923
924
178
  WCharType = SignedInt;
925
178
  UseSignedCharForObjCBool = false;
926
927
178
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
928
178
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
929
930
178
  UseZeroLengthBitfieldAlignment = false;
931
932
178
  if (getTriple().isArch32Bit()) {
933
14
    UseBitFieldTypeAlignment = false;
934
14
    ZeroLengthBitfieldBoundary = 32;
935
14
    UseZeroLengthBitfieldAlignment = true;
936
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
937
14
  } else
938
164
    TheCXXABI.set(TargetCXXABI::AppleARM64);
939
178
}
940
941
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
942
                                           const llvm::Triple &Triple,
943
178
                                           MacroBuilder &Builder) const {
944
178
  Builder.defineMacro("__AARCH64_SIMD__");
945
178
  if (Triple.isArch32Bit())
946
14
    Builder.defineMacro("__ARM64_ARCH_8_32__");
947
164
  else
948
164
    Builder.defineMacro("__ARM64_ARCH_8__");
949
178
  Builder.defineMacro("__ARM_NEON__");
950
178
  Builder.defineMacro("__LITTLE_ENDIAN__");
951
178
  Builder.defineMacro("__REGISTER_PREFIX__", "");
952
178
  Builder.defineMacro("__arm64", "1");
953
178
  Builder.defineMacro("__arm64__", "1");
954
955
178
  if (Triple.isArm64e())
956
3
    Builder.defineMacro("__arm64e__", "1");
957
958
178
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
959
178
}
960
961
TargetInfo::BuiltinVaListKind
962
193
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
963
193
  return TargetInfo::CharPtrBuiltinVaList;
964
193
}
965
966
// 64-bit RenderScript is aarch64
967
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
968
                                                   const TargetOptions &Opts)
969
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
970
                                       Triple.getOSName(),
971
                                       Triple.getEnvironmentName()),
972
1
                          Opts) {
973
1
  IsRenderScriptTarget = true;
974
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
972
1
                          Opts) {
973
1
  IsRenderScriptTarget = true;
974
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
975
976
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
977
1
                                                MacroBuilder &Builder) const {
978
1
  Builder.defineMacro("__RENDERSCRIPT__");
979
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
980
1
}