Coverage Report

Created: 2020-09-19 12:23

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64.h"
14
#include "clang/Basic/LangOptions.h"
15
#include "clang/Basic/TargetBuiltins.h"
16
#include "clang/Basic/TargetInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/AArch64TargetParser.h"
21
22
using namespace clang;
23
using namespace clang::targets;
24
25
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#include "clang/Basic/BuiltinsNEON.def"
29
30
#define BUILTIN(ID, TYPE, ATTRS)                                               \
31
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
32
#include "clang/Basic/BuiltinsSVE.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
37
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsAArch64.def"
41
};
42
43
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
44
                                     const TargetOptions &Opts)
45
2.28k
    : TargetInfo(Triple), ABI("aapcs") {
46
2.28k
  if (getTriple().isOSOpenBSD()) {
47
4
    Int64Type = SignedLongLong;
48
4
    IntMaxType = SignedLongLong;
49
2.28k
  } else {
50
2.28k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()2.13k
)
51
2.12k
      WCharType = UnsignedInt;
52
2.28k
53
2.28k
    Int64Type = SignedLong;
54
2.28k
    IntMaxType = SignedLong;
55
2.28k
  }
56
2.28k
57
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
58
2.28k
  HasLegalHalfType = true;
59
2.28k
  HasFloat16 = true;
60
2.28k
61
2.28k
  if (Triple.isArch64Bit())
62
2.27k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
63
14
  else
64
14
    LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
65
2.28k
66
2.28k
  MaxVectorAlign = 128;
67
2.28k
  MaxAtomicInlineWidth = 128;
68
2.28k
  MaxAtomicPromoteWidth = 128;
69
2.28k
70
2.28k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
71
2.28k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
72
2.28k
73
2.28k
  BFloat16Width = BFloat16Align = 16;
74
2.28k
  BFloat16Format = &llvm::APFloat::BFloat();
75
2.28k
76
  // Make __builtin_ms_va_list available.
77
2.28k
  HasBuiltinMSVaList = true;
78
2.28k
79
  // Make the SVE types available.  Note that this deliberately doesn't
80
  // depend on SveMode, since in principle it should be possible to turn
81
  // SVE on and off within a translation unit.  It should also be possible
82
  // to compile the global declaration:
83
  //
84
  // __SVInt8_t *ptr;
85
  //
86
  // even without SVE.
87
2.28k
  HasAArch64SVETypes = true;
88
2.28k
89
  // {} in inline assembly are neon specifiers, not assembly variant
90
  // specifiers.
91
2.28k
  NoAsmVariants = true;
92
2.28k
93
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
94
  // contributes to the alignment of the containing aggregate in the same way
95
  // a plain (non bit-field) member of that type would, without exception for
96
  // zero-sized or anonymous bit-fields."
97
2.28k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
98
2.28k
  UseZeroLengthBitfieldAlignment = true;
99
2.28k
100
  // AArch64 targets default to using the ARM C++ ABI.
101
2.28k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
102
2.28k
103
2.28k
  if (Triple.getOS() == llvm::Triple::Linux)
104
1.88k
    this->MCountName = "\01_mcount";
105
403
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
106
161
    this->MCountName =
107
160
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
: "mcount";
108
2.28k
}
109
110
1.47k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
111
112
235
bool AArch64TargetInfo::setABI(const std::string &Name) {
113
235
  if (Name != "aapcs" && 
Name != "darwinpcs"21
)
114
0
    return false;
115
235
116
235
  ABI = Name;
117
235
  return true;
118
235
}
119
120
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec,
121
                                                 BranchProtectionInfo &BPI,
122
73
                                                 StringRef &Err) const {
123
73
  llvm::AArch64::ParsedBranchProtection PBP;
124
73
  if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
125
7
    return false;
126
66
127
66
  BPI.SignReturnAddr =
128
66
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
129
66
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
130
66
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
131
66
          .Default(LangOptions::SignReturnAddressScopeKind::None);
132
66
133
66
  if (PBP.Key == "a_key")
134
48
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
135
18
  else
136
18
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
137
66
138
66
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
139
66
  return true;
140
66
}
141
142
248
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
143
248
  return Name == "generic" ||
144
33
         llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID;
145
248
}
146
147
247
bool AArch64TargetInfo::setCPU(const std::string &Name) {
148
247
  return isValidCPUName(Name);
149
247
}
150
151
void AArch64TargetInfo::fillValidCPUList(
152
2
    SmallVectorImpl<StringRef> &Values) const {
153
2
  llvm::AArch64::fillValidCPUArchList(Values);
154
2
}
155
156
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
157
80
                                                MacroBuilder &Builder) const {
158
  // FIXME: Armv8.1 makes __ARM_FEATURE_CRC32 mandatory. Handle it here.
159
80
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
160
80
}
161
162
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
163
76
                                                MacroBuilder &Builder) const {
164
  // Also include the ARMv8.1 defines
165
76
  getTargetDefinesARMV81A(Opts, Builder);
166
76
}
167
168
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
169
30
                                                MacroBuilder &Builder) const {
170
30
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
171
30
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
172
  // Also include the Armv8.2 defines
173
30
  getTargetDefinesARMV82A(Opts, Builder);
174
30
}
175
176
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
177
22
                                                MacroBuilder &Builder) const {
178
  // Also include the Armv8.3 defines
179
  // FIXME: Armv8.4 makes __ARM_FEATURE_ATOMICS, defined in GCC, mandatory.
180
  // Add and handle it here.
181
22
  getTargetDefinesARMV83A(Opts, Builder);
182
22
}
183
184
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
185
10
                                                MacroBuilder &Builder) const {
186
  // Also include the Armv8.4 defines
187
10
  getTargetDefinesARMV84A(Opts, Builder);
188
10
}
189
190
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
191
4
                                                MacroBuilder &Builder) const {
192
  // Also include the Armv8.5 defines
193
  // FIXME: Armv8.6 makes the following extensions mandatory:
194
  // - __ARM_FEATURE_BF16
195
  // - __ARM_FEATURE_MATMUL_INT8
196
  // Handle them here.
197
4
  getTargetDefinesARMV85A(Opts, Builder);
198
4
}
199
200
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
201
2.27k
                                         MacroBuilder &Builder) const {
202
  // Target identification.
203
2.27k
  Builder.defineMacro("__aarch64__");
204
  // For bare-metal.
205
2.27k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
206
158
      getTriple().isOSBinFormatELF())
207
157
    Builder.defineMacro("__ELF__");
208
2.27k
209
  // Target properties.
210
2.27k
  if (!getTriple().isOSWindows() && 
getTriple().isArch64Bit()2.23k
) {
211
2.22k
    Builder.defineMacro("_LP64");
212
2.22k
    Builder.defineMacro("__LP64__");
213
2.22k
  }
214
2.27k
215
2.27k
  std::string CodeModel = getTargetOpts().CodeModel;
216
2.27k
  if (CodeModel == "default")
217
2.27k
    CodeModel = "small";
218
2.27k
  for (char &c : CodeModel)
219
11.3k
    c = toupper(c);
220
2.27k
  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
221
2.27k
222
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
223
2.27k
  Builder.defineMacro("__ARM_ACLE", "200");
224
2.27k
  Builder.defineMacro("__ARM_ARCH", "8");
225
2.27k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
226
2.27k
227
2.27k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
228
2.27k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
229
2.27k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
230
2.27k
231
2.27k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
232
2.27k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
233
2.27k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
234
2.27k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
235
2.27k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
236
2.27k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
237
2.27k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
238
2.27k
239
2.27k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
240
2.27k
241
  // 0xe implies support for half, single and double precision operations.
242
2.27k
  Builder.defineMacro("__ARM_FP", "0xE");
243
2.27k
244
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
245
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
246
2.27k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
247
2.27k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
248
2.27k
249
2.27k
  if (Opts.UnsafeFPMath)
250
4
    Builder.defineMacro("__ARM_FP_FAST", "1");
251
2.27k
252
2.27k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
253
2.27k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
: 4));
254
2.27k
255
2.27k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
: "4");
256
2.27k
257
2.27k
  if (FPU & NeonMode) {
258
334
    Builder.defineMacro("__ARM_NEON", "1");
259
    // 64-bit NEON supports half, single and double precision operations.
260
334
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
261
334
  }
262
2.27k
263
2.27k
  if (FPU & SveMode)
264
1.60k
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
265
2.27k
266
2.27k
  if (HasSVE2)
267
409
    Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
268
2.27k
269
2.27k
  if (HasSVE2 && 
HasSVE2AES409
)
270
13
    Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
271
2.27k
272
2.27k
  if (HasSVE2 && 
HasSVE2BitPerm409
)
273
7
    Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
274
2.27k
275
2.27k
  if (HasSVE2 && 
HasSVE2SHA3409
)
276
3
    Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
277
2.27k
278
2.27k
  if (HasSVE2 && 
HasSVE2SM4409
)
279
5
    Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
280
2.27k
281
2.27k
  if (HasCRC)
282
4
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
283
2.27k
284
2.27k
  if (HasCrypto)
285
16
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
286
2.27k
287
2.27k
  if (HasUnaligned)
288
2.27k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
289
2.27k
290
2.27k
  if ((FPU & NeonMode) && 
HasFullFP16334
)
291
76
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
292
2.27k
  if (HasFullFP16)
293
1.66k
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
294
2.27k
295
2.27k
  if (HasDotProd)
296
5
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
297
2.27k
298
2.27k
  if (HasMTE)
299
24
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
300
2.27k
301
2.27k
  if (HasTME)
302
4
    Builder.defineMacro("__ARM_FEATURE_TME", "1");
303
2.27k
304
2.27k
  if (HasMatMul)
305
11
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
306
2.27k
307
2.27k
  if (HasBFloat16) {
308
198
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
309
198
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
310
198
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
311
198
    Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
312
198
  }
313
2.27k
314
2.27k
  if ((FPU & SveMode) && 
HasBFloat161.60k
) {
315
182
    Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
316
182
  }
317
2.27k
318
2.27k
  if ((FPU & SveMode) && 
HasMatmulFP641.60k
)
319
31
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
320
2.27k
321
2.27k
  if ((FPU & SveMode) && 
HasMatmulFP321.60k
)
322
4
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
323
2.27k
324
2.27k
  if ((FPU & SveMode) && 
HasMatMul1.60k
)
325
8
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
326
2.27k
327
2.27k
  if ((FPU & NeonMode) && 
HasFP16FML334
)
328
9
    Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
329
2.27k
330
2.27k
  if (Opts.hasSignReturnAddress()) {
331
    // Bitmask:
332
    // 0: Protection using the A key
333
    // 1: Protection using the B key
334
    // 2: Protection including leaf functions
335
27
    unsigned Value = 0;
336
27
337
27
    if (Opts.isSignReturnAddressWithAKey())
338
18
      Value |= (1 << 0);
339
9
    else
340
9
      Value |= (1 << 1);
341
27
342
27
    if (Opts.isSignReturnAddressScopeAll())
343
13
      Value |= (1 << 2);
344
27
345
27
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
346
27
  }
347
2.27k
348
2.27k
  if (Opts.BranchTargetEnforcement)
349
10
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
350
2.27k
351
2.27k
  switch (ArchKind) {
352
2.19k
  default:
353
2.19k
    break;
354
4
  case llvm::AArch64::ArchKind::ARMV8_1A:
355
4
    getTargetDefinesARMV81A(Opts, Builder);
356
4
    break;
357
46
  case llvm::AArch64::ArchKind::ARMV8_2A:
358
46
    getTargetDefinesARMV82A(Opts, Builder);
359
46
    break;
360
8
  case llvm::AArch64::ArchKind::ARMV8_3A:
361
8
    getTargetDefinesARMV83A(Opts, Builder);
362
8
    break;
363
12
  case llvm::AArch64::ArchKind::ARMV8_4A:
364
12
    getTargetDefinesARMV84A(Opts, Builder);
365
12
    break;
366
6
  case llvm::AArch64::ArchKind::ARMV8_5A:
367
6
    getTargetDefinesARMV85A(Opts, Builder);
368
6
    break;
369
4
  case llvm::AArch64::ArchKind::ARMV8_6A:
370
4
    getTargetDefinesARMV86A(Opts, Builder);
371
4
    break;
372
2.27k
  }
373
2.27k
374
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
375
2.27k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
376
2.27k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
377
2.27k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
378
2.27k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
379
2.27k
380
2.27k
  if (Opts.ArmSveVectorBits)
381
37
    Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits));
382
2.27k
}
383
384
2.27k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
385
2.27k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
386
2.27k
                                             Builtin::FirstTSBuiltin);
387
2.27k
}
388
389
4.00k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
390
4.00k
  return Feature == "aarch64" || 
Feature == "arm64"3.99k
||
Feature == "arm"3.99k
||
391
3.99k
         (Feature == "neon" && 
(FPU & NeonMode)3.36k
) ||
392
691
         ((Feature == "sve" || 
Feature == "sve2"172
||
Feature == "sve2-bitperm"172
||
393
172
           Feature == "sve2-aes" || Feature == "sve2-sha3" ||
394
172
           Feature == "sve2-sm4" || Feature == "f64mm" || Feature == "f32mm" ||
395
172
           Feature == "i8mm" || Feature == "bf16") &&
396
519
          (FPU & SveMode));
397
4.00k
}
398
399
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
400
2.28k
                                             DiagnosticsEngine &Diags) {
401
2.28k
  FPU = FPUMode;
402
2.28k
  HasCRC = false;
403
2.28k
  HasCrypto = false;
404
2.28k
  HasUnaligned = true;
405
2.28k
  HasFullFP16 = false;
406
2.28k
  HasDotProd = false;
407
2.28k
  HasFP16FML = false;
408
2.28k
  HasMTE = false;
409
2.28k
  HasTME = false;
410
2.28k
  HasMatMul = false;
411
2.28k
  HasBFloat16 = false;
412
2.28k
  HasSVE2 = false;
413
2.28k
  HasSVE2AES = false;
414
2.28k
  HasSVE2SHA3 = false;
415
2.28k
  HasSVE2SM4 = false;
416
2.28k
  HasSVE2BitPerm = false;
417
2.28k
  HasMatmulFP64 = false;
418
2.28k
  HasMatmulFP32 = false;
419
2.28k
420
2.28k
  ArchKind = llvm::AArch64::ArchKind::ARMV8A;
421
2.28k
422
2.46k
  for (const auto &Feature : Features) {
423
2.46k
    if (Feature == "+neon")
424
334
      FPU |= NeonMode;
425
2.46k
    if (Feature == "+sve") {
426
1.19k
      FPU |= SveMode;
427
1.19k
      HasFullFP16 = 1;
428
1.19k
    }
429
2.46k
    if (Feature == "+sve2") {
430
381
      FPU |= SveMode;
431
381
      HasFullFP16 = 1;
432
381
      HasSVE2 = 1;
433
381
    }
434
2.46k
    if (Feature == "+sve2-aes") {
435
13
      FPU |= SveMode;
436
13
      HasFullFP16 = 1;
437
13
      HasSVE2 = 1;
438
13
      HasSVE2AES = 1;
439
13
    }
440
2.46k
    if (Feature == "+sve2-sha3") {
441
3
      FPU |= SveMode;
442
3
      HasFullFP16 = 1;
443
3
      HasSVE2 = 1;
444
3
      HasSVE2SHA3 = 1;
445
3
    }
446
2.46k
    if (Feature == "+sve2-sm4") {
447
5
      FPU |= SveMode;
448
5
      HasFullFP16 = 1;
449
5
      HasSVE2 = 1;
450
5
      HasSVE2SM4 = 1;
451
5
    }
452
2.46k
    if (Feature == "+sve2-bitperm") {
453
7
      FPU |= SveMode;
454
7
      HasFullFP16 = 1;
455
7
      HasSVE2 = 1;
456
7
      HasSVE2BitPerm = 1;
457
7
    }
458
2.46k
    if (Feature == "+f32mm") {
459
4
      FPU |= SveMode;
460
4
      HasMatmulFP32 = true;
461
4
    }
462
2.46k
    if (Feature == "+f64mm") {
463
31
      FPU |= SveMode;
464
31
      HasMatmulFP64 = true;
465
31
    }
466
2.46k
    if (Feature == "+crc")
467
4
      HasCRC = true;
468
2.46k
    if (Feature == "+crypto")
469
16
      HasCrypto = true;
470
2.46k
    if (Feature == "+strict-align")
471
2
      HasUnaligned = false;
472
2.46k
    if (Feature == "+v8.1a")
473
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
474
2.46k
    if (Feature == "+v8.2a")
475
46
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
476
2.46k
    if (Feature == "+v8.3a")
477
8
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
478
2.46k
    if (Feature == "+v8.4a")
479
12
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
480
2.46k
    if (Feature == "+v8.5a")
481
6
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
482
2.46k
    if (Feature == "+v8.6a")
483
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
484
2.46k
    if (Feature == "+fullfp16")
485
55
      HasFullFP16 = true;
486
2.46k
    if (Feature == "+dotprod")
487
5
      HasDotProd = true;
488
2.46k
    if (Feature == "+fp16fml")
489
12
      HasFP16FML = true;
490
2.46k
    if (Feature == "+mte")
491
24
      HasMTE = true;
492
2.46k
    if (Feature == "+tme")
493
4
      HasTME = true;
494
2.46k
    if (Feature == "+i8mm")
495
11
      HasMatMul = true;
496
2.46k
    if (Feature == "+bf16")
497
198
      HasBFloat16 = true;
498
2.46k
  }
499
2.28k
500
2.28k
  setDataLayout();
501
2.28k
502
2.28k
  return true;
503
2.28k
}
504
505
TargetInfo::CallingConvCheckResult
506
343
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
507
343
  switch (CC) {
508
343
  case CC_C:
509
343
  case CC_Swift:
510
343
  case CC_PreserveMost:
511
343
  case CC_PreserveAll:
512
343
  case CC_OpenCLKernel:
513
343
  case CC_AArch64VectorCall:
514
343
  case CC_Win64:
515
343
    return CCCR_OK;
516
0
  default:
517
0
    return CCCR_Warning;
518
343
  }
519
343
}
520
521
24
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
522
523
2.06k
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
524
2.06k
  return TargetInfo::AArch64ABIBuiltinVaList;
525
2.06k
}
526
527
const char *const AArch64TargetInfo::GCCRegNames[] = {
528
    // 32-bit Integer registers
529
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
530
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
531
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
532
533
    // 64-bit Integer registers
534
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
535
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
536
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
537
538
    // 32-bit floating point regsisters
539
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
540
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
541
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
542
543
    // 64-bit floating point regsisters
544
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
545
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
546
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
547
548
    // Neon vector registers
549
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
550
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
551
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
552
553
    // SVE vector registers
554
    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
555
    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
556
    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
557
558
    // SVE predicate registers
559
    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
560
    "p11", "p12", "p13", "p14", "p15"
561
};
562
563
1.99k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
564
1.99k
  return llvm::makeArrayRef(GCCRegNames);
565
1.99k
}
566
567
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
568
    {{"w31"}, "wsp"},
569
    {{"x31"}, "sp"},
570
    // GCC rN registers are aliases of xN registers.
571
    {{"r0"}, "x0"},
572
    {{"r1"}, "x1"},
573
    {{"r2"}, "x2"},
574
    {{"r3"}, "x3"},
575
    {{"r4"}, "x4"},
576
    {{"r5"}, "x5"},
577
    {{"r6"}, "x6"},
578
    {{"r7"}, "x7"},
579
    {{"r8"}, "x8"},
580
    {{"r9"}, "x9"},
581
    {{"r10"}, "x10"},
582
    {{"r11"}, "x11"},
583
    {{"r12"}, "x12"},
584
    {{"r13"}, "x13"},
585
    {{"r14"}, "x14"},
586
    {{"r15"}, "x15"},
587
    {{"r16"}, "x16"},
588
    {{"r17"}, "x17"},
589
    {{"r18"}, "x18"},
590
    {{"r19"}, "x19"},
591
    {{"r20"}, "x20"},
592
    {{"r21"}, "x21"},
593
    {{"r22"}, "x22"},
594
    {{"r23"}, "x23"},
595
    {{"r24"}, "x24"},
596
    {{"r25"}, "x25"},
597
    {{"r26"}, "x26"},
598
    {{"r27"}, "x27"},
599
    {{"r28"}, "x28"},
600
    {{"r29", "x29"}, "fp"},
601
    {{"r30", "x30"}, "lr"},
602
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
603
    // don't want to substitute one of these for a different-sized one.
604
};
605
606
823
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
607
823
  return llvm::makeArrayRef(GCCRegAliases);
608
823
}
609
610
bool AArch64TargetInfo::validateAsmConstraint(
611
338
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
612
338
  switch (*Name) {
613
0
  default:
614
0
    return false;
615
284
  case 'w': // Floating point and SIMD registers (V0-V31)
616
284
    Info.setAllowsRegister();
617
284
    return true;
618
6
  case 'I': // Constant that can be used with an ADD instruction
619
6
  case 'J': // Constant that can be used with a SUB instruction
620
6
  case 'K': // Constant that can be used with a 32-bit logical instruction
621
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
622
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
623
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
624
6
  case 'Y': // Floating point constant zero
625
6
  case 'Z': // Integer constant zero
626
6
    return true;
627
4
  case 'Q': // A memory reference with base register and no offset
628
4
    Info.setAllowsMemory();
629
4
    return true;
630
2
  case 'S': // A symbolic address
631
2
    Info.setAllowsRegister();
632
2
    return true;
633
32
  case 'U':
634
32
    if (Name[1] == 'p' && (Name[2] == 'l' || 
Name[2] == 'a'24
)) {
635
      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
636
32
      Info.setAllowsRegister();
637
32
      Name += 2;
638
32
      return true;
639
32
    }
640
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
641
    // Utf: A memory address suitable for ldp/stp in TF mode.
642
    // Usa: An absolute symbolic address.
643
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
644
0
645
    // Better to return an error saying that it's an unrecognised constraint
646
    // even if this is a valid constraint in gcc.
647
0
    return false;
648
4
  case 'z': // Zero register, wzr or xzr
649
4
    Info.setAllowsRegister();
650
4
    return true;
651
0
  case 'x': // Floating point and SIMD registers (V0-V15)
652
0
    Info.setAllowsRegister();
653
0
    return true;
654
6
  case 'y': // SVE registers (V0-V7)
655
6
    Info.setAllowsRegister();
656
6
    return true;
657
0
  }
658
0
  return false;
659
0
}
660
661
bool AArch64TargetInfo::validateConstraintModifier(
662
    StringRef Constraint, char Modifier, unsigned Size,
663
226
    std::string &SuggestedModifier) const {
664
  // Strip off constraint modifiers.
665
334
  while (Constraint[0] == '=' || 
Constraint[0] == '+'234
||
Constraint[0] == '&'227
)
666
108
    Constraint = Constraint.substr(1);
667
226
668
226
  switch (Constraint[0]) {
669
185
  default:
670
185
    return true;
671
41
  case 'z':
672
41
  case 'r': {
673
41
    switch (Modifier) {
674
7
    case 'x':
675
7
    case 'w':
676
      // For now assume that the person knows what they're
677
      // doing with the modifier.
678
7
      return true;
679
34
    default:
680
      // By default an 'r' constraint will be in the 'x'
681
      // registers.
682
34
      if (Size == 64)
683
18
        return true;
684
16
685
16
      SuggestedModifier = "w";
686
16
      return false;
687
41
    }
688
41
  }
689
226
  }
690
226
}
691
692
99
const char *AArch64TargetInfo::getClobbers() const { return ""; }
693
694
0
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
695
0
  if (RegNo == 0)
696
0
    return 0;
697
0
  if (RegNo == 1)
698
0
    return 1;
699
0
  return -1;
700
0
}
701
702
6.75k
bool AArch64TargetInfo::hasInt128Type() const { return true; }
703
704
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
705
                                         const TargetOptions &Opts)
706
2.25k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
706
2.11k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
706
142
    : AArch64TargetInfo(Triple, Opts) {}
707
708
2.21k
void AArch64leTargetInfo::setDataLayout() {
709
2.21k
  if (getTriple().isOSBinFormatMachO()) {
710
151
    if(getTriple().isArch32Bit())
711
14
      resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128");
712
137
    else
713
137
      resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
714
151
  } else
715
2.05k
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
716
2.21k
}
717
718
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
719
2.24k
                                           MacroBuilder &Builder) const {
720
2.24k
  Builder.defineMacro("__AARCH64EL__");
721
2.24k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
722
2.24k
}
723
724
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
725
                                         const TargetOptions &Opts)
726
30
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
726
9
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
726
21
    : AArch64TargetInfo(Triple, Opts) {}
727
728
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
729
30
                                           MacroBuilder &Builder) const {
730
30
  Builder.defineMacro("__AARCH64EB__");
731
30
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
732
30
  Builder.defineMacro("__ARM_BIG_ENDIAN");
733
30
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
734
30
}
735
736
30
void AArch64beTargetInfo::setDataLayout() {
737
30
  assert(!getTriple().isOSBinFormatMachO());
738
30
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
739
30
}
740
741
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
742
                                               const TargetOptions &Opts)
743
43
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
744
43
745
  // This is an LLP64 platform.
746
  // int:4, long:4, long long:8, long double:8.
747
43
  IntWidth = IntAlign = 32;
748
43
  LongWidth = LongAlign = 32;
749
43
  DoubleAlign = LongLongAlign = 64;
750
43
  LongDoubleWidth = LongDoubleAlign = 64;
751
43
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
752
43
  IntMaxType = SignedLongLong;
753
43
  Int64Type = SignedLongLong;
754
43
  SizeType = UnsignedLongLong;
755
43
  PtrDiffType = SignedLongLong;
756
43
  IntPtrType = SignedLongLong;
757
43
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
743
43
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
744
43
745
  // This is an LLP64 platform.
746
  // int:4, long:4, long long:8, long double:8.
747
43
  IntWidth = IntAlign = 32;
748
43
  LongWidth = LongAlign = 32;
749
43
  DoubleAlign = LongLongAlign = 64;
750
43
  LongDoubleWidth = LongDoubleAlign = 64;
751
43
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
752
43
  IntMaxType = SignedLongLong;
753
43
  Int64Type = SignedLongLong;
754
43
  SizeType = UnsignedLongLong;
755
43
  PtrDiffType = SignedLongLong;
756
43
  IntPtrType = SignedLongLong;
757
43
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
758
759
43
void WindowsARM64TargetInfo::setDataLayout() {
760
43
  resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128");
761
43
}
762
763
TargetInfo::BuiltinVaListKind
764
42
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
765
42
  return TargetInfo::CharPtrBuiltinVaList;
766
42
}
767
768
TargetInfo::CallingConvCheckResult
769
53
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
770
53
  switch (CC) {
771
7
  case CC_X86StdCall:
772
7
  case CC_X86ThisCall:
773
7
  case CC_X86FastCall:
774
7
  case CC_X86VectorCall:
775
7
    return CCCR_Ignore;
776
46
  case CC_C:
777
46
  case CC_OpenCLKernel:
778
46
  case CC_PreserveMost:
779
46
  case CC_PreserveAll:
780
46
  case CC_Swift:
781
46
  case CC_Win64:
782
46
    return CCCR_OK;
783
0
  default:
784
0
    return CCCR_Warning;
785
53
  }
786
53
}
787
788
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
789
                                                   const TargetOptions &Opts)
790
40
    : WindowsARM64TargetInfo(Triple, Opts) {
791
40
  TheCXXABI.set(TargetCXXABI::Microsoft);
792
40
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
790
40
    : WindowsARM64TargetInfo(Triple, Opts) {
791
40
  TheCXXABI.set(TargetCXXABI::Microsoft);
792
40
}
793
794
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
795
40
                                                MacroBuilder &Builder) const {
796
40
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
797
40
  Builder.defineMacro("_M_ARM64", "1");
798
40
}
799
800
TargetInfo::CallingConvKind
801
77
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
802
77
  return CCK_MicrosoftWin64;
803
77
}
804
805
163
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
806
163
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
807
163
808
  // MSVC does size based alignment for arm64 based on alignment section in
809
  // below document, replicate that to keep alignment consistent with object
810
  // files compiled by MSVC.
811
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
812
163
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
813
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
814
153
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
815
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
816
96
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
817
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
818
45
  }
819
163
  return Align;
820
163
}
821
822
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
823
                                           const TargetOptions &Opts)
824
3
    : WindowsARM64TargetInfo(Triple, Opts) {
825
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
826
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
824
3
    : WindowsARM64TargetInfo(Triple, Opts) {
825
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
826
3
}
827
828
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
829
                                                 const TargetOptions &Opts)
830
150
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
831
150
  Int64Type = SignedLongLong;
832
150
  if (getTriple().isArch32Bit())
833
14
    IntMaxType = SignedLongLong;
834
150
835
150
  WCharType = SignedInt;
836
150
  UseSignedCharForObjCBool = false;
837
150
838
150
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
839
150
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
840
150
841
150
  UseZeroLengthBitfieldAlignment = false;
842
150
843
150
  if (getTriple().isArch32Bit()) {
844
14
    UseBitFieldTypeAlignment = false;
845
14
    ZeroLengthBitfieldBoundary = 32;
846
14
    UseZeroLengthBitfieldAlignment = true;
847
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
848
14
  } else
849
136
    TheCXXABI.set(TargetCXXABI::iOS64);
850
150
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
830
150
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
831
150
  Int64Type = SignedLongLong;
832
150
  if (getTriple().isArch32Bit())
833
14
    IntMaxType = SignedLongLong;
834
150
835
150
  WCharType = SignedInt;
836
150
  UseSignedCharForObjCBool = false;
837
150
838
150
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
839
150
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
840
150
841
150
  UseZeroLengthBitfieldAlignment = false;
842
150
843
150
  if (getTriple().isArch32Bit()) {
844
14
    UseBitFieldTypeAlignment = false;
845
14
    ZeroLengthBitfieldBoundary = 32;
846
14
    UseZeroLengthBitfieldAlignment = true;
847
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
848
14
  } else
849
136
    TheCXXABI.set(TargetCXXABI::iOS64);
850
150
}
851
852
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
853
                                           const llvm::Triple &Triple,
854
150
                                           MacroBuilder &Builder) const {
855
150
  Builder.defineMacro("__AARCH64_SIMD__");
856
150
  if (Triple.isArch32Bit())
857
14
    Builder.defineMacro("__ARM64_ARCH_8_32__");
858
136
  else
859
136
    Builder.defineMacro("__ARM64_ARCH_8__");
860
150
  Builder.defineMacro("__ARM_NEON__");
861
150
  Builder.defineMacro("__LITTLE_ENDIAN__");
862
150
  Builder.defineMacro("__REGISTER_PREFIX__", "");
863
150
  Builder.defineMacro("__arm64", "1");
864
150
  Builder.defineMacro("__arm64__", "1");
865
150
866
150
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
867
150
}
868
869
TargetInfo::BuiltinVaListKind
870
166
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
871
166
  return TargetInfo::CharPtrBuiltinVaList;
872
166
}
873
874
// 64-bit RenderScript is aarch64
875
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
876
                                                   const TargetOptions &Opts)
877
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
878
                                       Triple.getOSName(),
879
                                       Triple.getEnvironmentName()),
880
1
                          Opts) {
881
1
  IsRenderScriptTarget = true;
882
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
880
1
                          Opts) {
881
1
  IsRenderScriptTarget = true;
882
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
883
884
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
885
1
                                                MacroBuilder &Builder) const {
886
1
  Builder.defineMacro("__RENDERSCRIPT__");
887
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
888
1
}