Coverage Report

Created: 2022-01-18 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64.h"
14
#include "clang/Basic/LangOptions.h"
15
#include "clang/Basic/TargetBuiltins.h"
16
#include "clang/Basic/TargetInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/AArch64TargetParser.h"
21
22
using namespace clang;
23
using namespace clang::targets;
24
25
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#include "clang/Basic/BuiltinsNEON.def"
29
30
#define BUILTIN(ID, TYPE, ATTRS)                                               \
31
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
32
#include "clang/Basic/BuiltinsSVE.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
37
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsAArch64.def"
41
};
42
43
3.33k
static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
44
3.33k
  switch (Kind) {
45
6
  case llvm::AArch64::ArchKind::ARMV9A:
46
6
  case llvm::AArch64::ArchKind::ARMV9_1A:
47
6
  case llvm::AArch64::ArchKind::ARMV9_2A:
48
6
  case llvm::AArch64::ArchKind::ARMV9_3A:
49
6
    return "9";
50
3.33k
  default:
51
3.33k
    return "8";
52
3.33k
  }
53
3.33k
}
54
55
3.33k
StringRef AArch64TargetInfo::getArchProfile() const {
56
3.33k
  switch (ArchKind) {
57
2
  case llvm::AArch64::ArchKind::ARMV8R:
58
2
    return "R";
59
3.33k
  default:
60
3.33k
    return "A";
61
3.33k
  }
62
3.33k
}
63
64
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
65
                                     const TargetOptions &Opts)
66
3.34k
    : TargetInfo(Triple), ABI("aapcs") {
67
3.34k
  if (getTriple().isOSOpenBSD()) {
68
4
    Int64Type = SignedLongLong;
69
4
    IntMaxType = SignedLongLong;
70
3.34k
  } else {
71
3.34k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()3.16k
)
72
3.15k
      WCharType = UnsignedInt;
73
74
3.34k
    Int64Type = SignedLong;
75
3.34k
    IntMaxType = SignedLong;
76
3.34k
  }
77
78
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
79
3.34k
  HasLegalHalfType = true;
80
3.34k
  HasFloat16 = true;
81
82
3.34k
  if (Triple.isArch64Bit())
83
3.33k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
84
14
  else
85
14
    LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
86
87
3.34k
  MaxVectorAlign = 128;
88
3.34k
  MaxAtomicInlineWidth = 128;
89
3.34k
  MaxAtomicPromoteWidth = 128;
90
91
3.34k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
92
3.34k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
93
94
3.34k
  BFloat16Width = BFloat16Align = 16;
95
3.34k
  BFloat16Format = &llvm::APFloat::BFloat();
96
97
  // Make __builtin_ms_va_list available.
98
3.34k
  HasBuiltinMSVaList = true;
99
100
  // Make the SVE types available.  Note that this deliberately doesn't
101
  // depend on SveMode, since in principle it should be possible to turn
102
  // SVE on and off within a translation unit.  It should also be possible
103
  // to compile the global declaration:
104
  //
105
  // __SVInt8_t *ptr;
106
  //
107
  // even without SVE.
108
3.34k
  HasAArch64SVETypes = true;
109
110
  // {} in inline assembly are neon specifiers, not assembly variant
111
  // specifiers.
112
3.34k
  NoAsmVariants = true;
113
114
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
115
  // contributes to the alignment of the containing aggregate in the same way
116
  // a plain (non bit-field) member of that type would, without exception for
117
  // zero-sized or anonymous bit-fields."
118
3.34k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
119
0
  UseZeroLengthBitfieldAlignment = true;
120
121
  // AArch64 targets default to using the ARM C++ ABI.
122
3.34k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
123
124
3.34k
  if (Triple.getOS() == llvm::Triple::Linux)
125
2.80k
    this->MCountName = "\01_mcount";
126
544
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
127
265
    this->MCountName =
128
265
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
:
"mcount"264
;
129
3.34k
}
130
131
4.15k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
132
133
261
bool AArch64TargetInfo::setABI(const std::string &Name) {
134
261
  if (Name != "aapcs" && 
Name != "darwinpcs"25
)
135
0
    return false;
136
137
261
  ABI = Name;
138
261
  return true;
139
261
}
140
141
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec,
142
                                                 BranchProtectionInfo &BPI,
143
40
                                                 StringRef &Err) const {
144
40
  llvm::ARM::ParsedBranchProtection PBP;
145
40
  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
146
7
    return false;
147
148
33
  BPI.SignReturnAddr =
149
33
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
150
33
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
151
33
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
152
33
          .Default(LangOptions::SignReturnAddressScopeKind::None);
153
154
33
  if (PBP.Key == "a_key")
155
24
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
156
9
  else
157
9
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
158
159
33
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
160
33
  return true;
161
40
}
162
163
281
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
164
281
  return Name == "generic" ||
165
281
         
llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID46
;
166
281
}
167
168
280
bool AArch64TargetInfo::setCPU(const std::string &Name) {
169
280
  return isValidCPUName(Name);
170
280
}
171
172
void AArch64TargetInfo::fillValidCPUList(
173
2
    SmallVectorImpl<StringRef> &Values) const {
174
2
  llvm::AArch64::fillValidCPUArchList(Values);
175
2
}
176
177
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
178
94
                                                MacroBuilder &Builder) const {
179
94
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
180
94
  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
181
94
  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
182
94
}
183
184
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
185
86
                                                MacroBuilder &Builder) const {
186
  // Also include the ARMv8.1 defines
187
86
  getTargetDefinesARMV81A(Opts, Builder);
188
86
}
189
190
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
191
41
                                                MacroBuilder &Builder) const {
192
41
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
193
41
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
194
  // Also include the Armv8.2 defines
195
41
  getTargetDefinesARMV82A(Opts, Builder);
196
41
}
197
198
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
199
38
                                                MacroBuilder &Builder) const {
200
  // Also include the Armv8.3 defines
201
38
  getTargetDefinesARMV83A(Opts, Builder);
202
38
}
203
204
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
205
24
                                                MacroBuilder &Builder) const {
206
24
  Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
207
  // Also include the Armv8.4 defines
208
24
  getTargetDefinesARMV84A(Opts, Builder);
209
24
}
210
211
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
212
6
                                                MacroBuilder &Builder) const {
213
  // Also include the Armv8.5 defines
214
  // FIXME: Armv8.6 makes the following extensions mandatory:
215
  // - __ARM_FEATURE_BF16
216
  // - __ARM_FEATURE_MATMUL_INT8
217
  // Handle them here.
218
6
  getTargetDefinesARMV85A(Opts, Builder);
219
6
}
220
221
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
222
2
                                                MacroBuilder &Builder) const {
223
  // Also include the Armv8.6 defines
224
2
  getTargetDefinesARMV86A(Opts, Builder);
225
2
}
226
227
void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts,
228
0
                                                MacroBuilder &Builder) const {
229
  // Also include the Armv8.7 defines
230
0
  getTargetDefinesARMV87A(Opts, Builder);
231
0
}
232
233
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
234
6
                                               MacroBuilder &Builder) const {
235
  // Armv9-A maps to Armv8.5-A
236
6
  getTargetDefinesARMV85A(Opts, Builder);
237
6
}
238
239
void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts,
240
0
                                                MacroBuilder &Builder) const {
241
  // Armv9.1-A maps to Armv8.6-A
242
0
  getTargetDefinesARMV86A(Opts, Builder);
243
0
}
244
245
void AArch64TargetInfo::getTargetDefinesARMV92A(const LangOptions &Opts,
246
0
                                                MacroBuilder &Builder) const {
247
  // Armv9.2-A maps to Armv8.7-A
248
0
  getTargetDefinesARMV87A(Opts, Builder);
249
0
}
250
251
void AArch64TargetInfo::getTargetDefinesARMV93A(const LangOptions &Opts,
252
0
                                                MacroBuilder &Builder) const {
253
  // Armv9.3-A maps to Armv8.8-A
254
0
  getTargetDefinesARMV88A(Opts, Builder);
255
0
}
256
257
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
258
3.33k
                                         MacroBuilder &Builder) const {
259
  // Target identification.
260
3.33k
  Builder.defineMacro("__aarch64__");
261
  // For bare-metal.
262
3.33k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
263
3.33k
      
getTriple().isOSBinFormatELF()260
)
264
259
    Builder.defineMacro("__ELF__");
265
266
  // Target properties.
267
3.33k
  if (!getTriple().isOSWindows() && 
getTriple().isArch64Bit()3.28k
) {
268
3.26k
    Builder.defineMacro("_LP64");
269
3.26k
    Builder.defineMacro("__LP64__");
270
3.26k
  }
271
272
3.33k
  std::string CodeModel = getTargetOpts().CodeModel;
273
3.33k
  if (CodeModel == "default")
274
3.33k
    CodeModel = "small";
275
3.33k
  for (char &c : CodeModel)
276
16.6k
    c = toupper(c);
277
3.33k
  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
278
279
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
280
3.33k
  Builder.defineMacro("__ARM_ACLE", "200");
281
3.33k
  Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
282
3.33k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
283
284
3.33k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
285
3.33k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
286
3.33k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
287
288
3.33k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
289
3.33k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
290
3.33k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
291
3.33k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
292
3.33k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
293
3.33k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
294
3.33k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
295
296
3.33k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
297
298
  // 0xe implies support for half, single and double precision operations.
299
3.33k
  Builder.defineMacro("__ARM_FP", "0xE");
300
301
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
302
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
303
3.33k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
304
3.33k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
305
306
3.33k
  if (Opts.UnsafeFPMath)
307
4
    Builder.defineMacro("__ARM_FP_FAST", "1");
308
309
3.33k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
310
3.33k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
43.33k
));
311
312
3.33k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"3.33k
);
313
314
3.33k
  if (FPU & NeonMode) {
315
381
    Builder.defineMacro("__ARM_NEON", "1");
316
    // 64-bit NEON supports half, single and double precision operations.
317
381
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
318
381
  }
319
320
3.33k
  if (FPU & SveMode)
321
2.48k
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
322
323
3.33k
  if ((FPU & NeonMode) && 
(FPU & SveMode)381
)
324
44
    Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
325
326
3.33k
  if (HasSVE2)
327
725
    Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
328
329
3.33k
  if (HasSVE2 && 
HasSVE2AES725
)
330
25
    Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
331
332
3.33k
  if (HasSVE2 && 
HasSVE2BitPerm725
)
333
13
    Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
334
335
3.33k
  if (HasSVE2 && 
HasSVE2SHA3725
)
336
5
    Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
337
338
3.33k
  if (HasSVE2 && 
HasSVE2SM4725
)
339
9
    Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
340
341
3.33k
  if (HasCRC)
342
6
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
343
344
  // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
345
  // macros for AES, SHA2, SHA3 and SM4
346
3.33k
  if (HasAES && 
HasSHA221
)
347
20
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
348
349
3.33k
  if (HasAES)
350
21
    Builder.defineMacro("__ARM_FEATURE_AES", "1");
351
352
3.33k
  if (HasSHA2)
353
24
    Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
354
355
3.33k
  if (HasSHA3) {
356
5
    Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
357
5
    Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
358
5
  }
359
360
3.33k
  if (HasSM4) {
361
5
    Builder.defineMacro("__ARM_FEATURE_SM3", "1");
362
5
    Builder.defineMacro("__ARM_FEATURE_SM4", "1");
363
5
  }
364
365
3.33k
  if (HasUnaligned)
366
3.33k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
367
368
3.33k
  if ((FPU & NeonMode) && 
HasFullFP16381
)
369
95
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
370
3.33k
  if (HasFullFP16)
371
2.54k
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
372
373
3.33k
  if (HasDotProd)
374
6
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
375
376
3.33k
  if (HasMTE)
377
14
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
378
379
3.33k
  if (HasTME)
380
4
    Builder.defineMacro("__ARM_FEATURE_TME", "1");
381
382
3.33k
  if (HasMatMul)
383
19
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
384
385
3.33k
  if (HasLSE)
386
3
    Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
387
388
3.33k
  if (HasBFloat16) {
389
339
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
390
339
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
391
339
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
392
339
    Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
393
339
  }
394
395
3.33k
  if ((FPU & SveMode) && 
HasBFloat162.48k
) {
396
321
    Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
397
321
  }
398
399
3.33k
  if ((FPU & SveMode) && 
HasMatmulFP642.48k
)
400
61
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
401
402
3.33k
  if ((FPU & SveMode) && 
HasMatmulFP322.48k
)
403
6
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
404
405
3.33k
  if ((FPU & SveMode) && 
HasMatMul2.48k
)
406
14
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
407
408
3.33k
  if ((FPU & NeonMode) && 
HasFP16FML381
)
409
10
    Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
410
411
3.33k
  if (Opts.hasSignReturnAddress()) {
412
    // Bitmask:
413
    // 0: Protection using the A key
414
    // 1: Protection using the B key
415
    // 2: Protection including leaf functions
416
15
    unsigned Value = 0;
417
418
15
    if (Opts.isSignReturnAddressWithAKey())
419
10
      Value |= (1 << 0);
420
5
    else
421
5
      Value |= (1 << 1);
422
423
15
    if (Opts.isSignReturnAddressScopeAll())
424
6
      Value |= (1 << 2);
425
426
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
427
15
  }
428
429
3.33k
  if (Opts.BranchTargetEnforcement)
430
6
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
431
432
3.33k
  if (HasLS64)
433
6
    Builder.defineMacro("__ARM_FEATURE_LS64", "1");
434
435
3.33k
  if (HasRandGen)
436
2
    Builder.defineMacro("__ARM_FEATURE_RNG", "1");
437
438
3.33k
  switch (ArchKind) {
439
3.24k
  default:
440
3.24k
    break;
441
3.24k
  case llvm::AArch64::ArchKind::ARMV8_1A:
442
8
    getTargetDefinesARMV81A(Opts, Builder);
443
8
    break;
444
45
  case llvm::AArch64::ArchKind::ARMV8_2A:
445
45
    getTargetDefinesARMV82A(Opts, Builder);
446
45
    break;
447
3
  case llvm::AArch64::ArchKind::ARMV8_3A:
448
3
    getTargetDefinesARMV83A(Opts, Builder);
449
3
    break;
450
14
  case llvm::AArch64::ArchKind::ARMV8_4A:
451
14
    getTargetDefinesARMV84A(Opts, Builder);
452
14
    break;
453
12
  case llvm::AArch64::ArchKind::ARMV8_5A:
454
12
    getTargetDefinesARMV85A(Opts, Builder);
455
12
    break;
456
4
  case llvm::AArch64::ArchKind::ARMV8_6A:
457
4
    getTargetDefinesARMV86A(Opts, Builder);
458
4
    break;
459
2
  case llvm::AArch64::ArchKind::ARMV8_7A:
460
2
    getTargetDefinesARMV87A(Opts, Builder);
461
2
    break;
462
0
  case llvm::AArch64::ArchKind::ARMV8_8A:
463
0
    getTargetDefinesARMV88A(Opts, Builder);
464
0
    break;
465
6
  case llvm::AArch64::ArchKind::ARMV9A:
466
6
    getTargetDefinesARMV9A(Opts, Builder);
467
6
    break;
468
0
  case llvm::AArch64::ArchKind::ARMV9_1A:
469
0
    getTargetDefinesARMV91A(Opts, Builder);
470
0
    break;
471
0
  case llvm::AArch64::ArchKind::ARMV9_2A:
472
0
    getTargetDefinesARMV92A(Opts, Builder);
473
0
    break;
474
0
  case llvm::AArch64::ArchKind::ARMV9_3A:
475
0
    getTargetDefinesARMV93A(Opts, Builder);
476
0
    break;
477
3.33k
  }
478
479
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
480
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
481
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
482
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
483
3.33k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
484
485
3.33k
  if (Opts.VScaleMin && 
Opts.VScaleMin == Opts.VScaleMax82
) {
486
73
    Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
487
73
    Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS");
488
73
  }
489
3.33k
}
490
491
3.33k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
492
3.33k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
493
3.33k
                                             Builtin::FirstTSBuiltin);
494
3.33k
}
495
496
Optional<std::pair<unsigned, unsigned>>
497
41.9k
AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
498
41.9k
  if (LangOpts.VScaleMin || 
LangOpts.VScaleMax41.7k
)
499
184
    return std::pair<unsigned, unsigned>(
500
184
        LangOpts.VScaleMin ? LangOpts.VScaleMin : 
10
, LangOpts.VScaleMax);
501
502
41.7k
  if (hasFeature("sve"))
503
29.6k
    return std::pair<unsigned, unsigned>(1, 16);
504
505
12.1k
  return None;
506
41.7k
}
507
508
49.0k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
509
49.0k
  return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" ||
510
49.0k
         
(49.0k
Feature == "neon"49.0k
&&
(FPU & NeonMode)4.07k
) ||
511
49.0k
         
(45.0k
(45.0k
Feature == "sve"45.0k
||
Feature == "sve2"2.64k
||
Feature == "sve2-bitperm"2.64k
||
512
45.0k
           
Feature == "sve2-aes"2.64k
||
Feature == "sve2-sha3"2.64k
||
513
45.0k
           
Feature == "sve2-sm4"2.64k
||
Feature == "f64mm"2.64k
||
Feature == "f32mm"2.64k
||
514
45.0k
           
Feature == "i8mm"2.64k
||
Feature == "bf16"2.64k
) &&
515
45.0k
          
(FPU & SveMode)42.4k
) ||
516
49.0k
         
(14.8k
Feature == "ls64"14.8k
&&
HasLS6489
);
517
49.0k
}
518
519
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
520
3.34k
                                             DiagnosticsEngine &Diags) {
521
3.34k
  FPU = FPUMode;
522
3.34k
  HasCRC = false;
523
3.34k
  HasCrypto = false;
524
3.34k
  HasAES = false;
525
3.34k
  HasSHA2 = false;
526
3.34k
  HasSHA3 = false;
527
3.34k
  HasSM4 = false;
528
3.34k
  HasUnaligned = true;
529
3.34k
  HasFullFP16 = false;
530
3.34k
  HasDotProd = false;
531
3.34k
  HasFP16FML = false;
532
3.34k
  HasMTE = false;
533
3.34k
  HasTME = false;
534
3.34k
  HasLS64 = false;
535
3.34k
  HasRandGen = false;
536
3.34k
  HasMatMul = false;
537
3.34k
  HasBFloat16 = false;
538
3.34k
  HasSVE2 = false;
539
3.34k
  HasSVE2AES = false;
540
3.34k
  HasSVE2SHA3 = false;
541
3.34k
  HasSVE2SM4 = false;
542
3.34k
  HasSVE2BitPerm = false;
543
3.34k
  HasMatmulFP64 = false;
544
3.34k
  HasMatmulFP32 = false;
545
3.34k
  HasLSE = false;
546
3.34k
  HasHBC = false;
547
3.34k
  HasMOPS = false;
548
549
3.34k
  ArchKind = llvm::AArch64::ArchKind::INVALID;
550
551
3.82k
  for (const auto &Feature : Features) {
552
3.82k
    if (Feature == "+neon")
553
381
      FPU |= NeonMode;
554
3.82k
    if (Feature == "+sve") {
555
1.76k
      FPU |= SveMode;
556
1.76k
      HasFullFP16 = true;
557
1.76k
    }
558
3.82k
    if (Feature == "+sve2") {
559
677
      FPU |= SveMode;
560
677
      HasFullFP16 = true;
561
677
      HasSVE2 = true;
562
677
    }
563
3.82k
    if (Feature == "+sve2-aes") {
564
25
      FPU |= SveMode;
565
25
      HasFullFP16 = true;
566
25
      HasSVE2 = true;
567
25
      HasSVE2AES = true;
568
25
    }
569
3.82k
    if (Feature == "+sve2-sha3") {
570
5
      FPU |= SveMode;
571
5
      HasFullFP16 = true;
572
5
      HasSVE2 = true;
573
5
      HasSVE2SHA3 = true;
574
5
    }
575
3.82k
    if (Feature == "+sve2-sm4") {
576
9
      FPU |= SveMode;
577
9
      HasFullFP16 = true;
578
9
      HasSVE2 = true;
579
9
      HasSVE2SM4 = true;
580
9
    }
581
3.82k
    if (Feature == "+sve2-bitperm") {
582
13
      FPU |= SveMode;
583
13
      HasFullFP16 = true;
584
13
      HasSVE2 = true;
585
13
      HasSVE2BitPerm = true;
586
13
    }
587
3.82k
    if (Feature == "+f32mm") {
588
6
      FPU |= SveMode;
589
6
      HasMatmulFP32 = true;
590
6
    }
591
3.82k
    if (Feature == "+f64mm") {
592
61
      FPU |= SveMode;
593
61
      HasMatmulFP64 = true;
594
61
    }
595
3.82k
    if (Feature == "+crc")
596
6
      HasCRC = true;
597
3.82k
    if (Feature == "+crypto")
598
18
      HasCrypto = true;
599
3.82k
    if (Feature == "+aes")
600
21
      HasAES = true;
601
3.82k
    if (Feature == "+sha2")
602
21
      HasSHA2 = true;
603
3.82k
    if (Feature == "+sha3") {
604
5
      HasSHA2 = true;
605
5
      HasSHA3 = true;
606
5
    }
607
3.82k
    if (Feature == "+sm4")
608
5
      HasSM4 = true;
609
3.82k
    if (Feature == "+strict-align")
610
2
      HasUnaligned = false;
611
3.82k
    if (Feature == "+v8a")
612
165
      ArchKind = llvm::AArch64::ArchKind::ARMV8A;
613
3.82k
    if (Feature == "+v8.1a")
614
8
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
615
3.82k
    if (Feature == "+v8.2a")
616
45
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
617
3.82k
    if (Feature == "+v8.3a")
618
3
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
619
3.82k
    if (Feature == "+v8.4a")
620
14
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
621
3.82k
    if (Feature == "+v8.5a")
622
12
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
623
3.82k
    if (Feature == "+v8.6a")
624
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
625
3.82k
    if (Feature == "+v8.7a")
626
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
627
3.82k
    if (Feature == "+v8.8a")
628
0
      ArchKind = llvm::AArch64::ArchKind::ARMV8_8A;
629
3.82k
    if (Feature == "+v9a")
630
6
      ArchKind = llvm::AArch64::ArchKind::ARMV9A;
631
3.82k
    if (Feature == "+v9.1a")
632
0
      ArchKind = llvm::AArch64::ArchKind::ARMV9_1A;
633
3.82k
    if (Feature == "+v9.2a")
634
0
      ArchKind = llvm::AArch64::ArchKind::ARMV9_2A;
635
3.82k
    if (Feature == "+v9.3a")
636
0
      ArchKind = llvm::AArch64::ArchKind::ARMV9_3A;
637
3.82k
    if (Feature == "+v8r")
638
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8R;
639
3.82k
    if (Feature == "+fullfp16")
640
57
      HasFullFP16 = true;
641
3.82k
    if (Feature == "+dotprod")
642
6
      HasDotProd = true;
643
3.82k
    if (Feature == "+fp16fml")
644
13
      HasFP16FML = true;
645
3.82k
    if (Feature == "+mte")
646
14
      HasMTE = true;
647
3.82k
    if (Feature == "+tme")
648
4
      HasTME = true;
649
3.82k
    if (Feature == "+pauth")
650
0
      HasPAuth = true;
651
3.82k
    if (Feature == "+i8mm")
652
19
      HasMatMul = true;
653
3.82k
    if (Feature == "+bf16")
654
339
      HasBFloat16 = true;
655
3.82k
    if (Feature == "+lse")
656
3
      HasLSE = true;
657
3.82k
    if (Feature == "+ls64")
658
6
      HasLS64 = true;
659
3.82k
    if (Feature == "+rand")
660
2
      HasRandGen = true;
661
3.82k
    if (Feature == "+flagm")
662
0
      HasFlagM = true;
663
3.82k
    if (Feature == "+hbc")
664
0
      HasHBC = true;
665
3.82k
  }
666
667
3.34k
  setDataLayout();
668
669
3.34k
  return true;
670
3.34k
}
671
672
TargetInfo::CallingConvCheckResult
673
438
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
674
438
  switch (CC) {
675
3
  case CC_C:
676
323
  case CC_Swift:
677
412
  case CC_SwiftAsync:
678
417
  case CC_PreserveMost:
679
423
  case CC_PreserveAll:
680
423
  case CC_OpenCLKernel:
681
431
  case CC_AArch64VectorCall:
682
438
  case CC_Win64:
683
438
    return CCCR_OK;
684
0
  default:
685
0
    return CCCR_Warning;
686
438
  }
687
438
}
688
689
33
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
690
691
3.06k
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
692
3.06k
  return TargetInfo::AArch64ABIBuiltinVaList;
693
3.06k
}
694
695
const char *const AArch64TargetInfo::GCCRegNames[] = {
696
    // 32-bit Integer registers
697
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
698
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
699
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
700
701
    // 64-bit Integer registers
702
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
703
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
704
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
705
706
    // 32-bit floating point regsisters
707
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
708
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
709
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
710
711
    // 64-bit floating point regsisters
712
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
713
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
714
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
715
716
    // Neon vector registers
717
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
718
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
719
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
720
721
    // SVE vector registers
722
    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
723
    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
724
    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
725
726
    // SVE predicate registers
727
    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
728
    "p11", "p12", "p13", "p14", "p15"
729
};
730
731
2.00k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
732
2.00k
  return llvm::makeArrayRef(GCCRegNames);
733
2.00k
}
734
735
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
736
    {{"w31"}, "wsp"},
737
    {{"x31"}, "sp"},
738
    // GCC rN registers are aliases of xN registers.
739
    {{"r0"}, "x0"},
740
    {{"r1"}, "x1"},
741
    {{"r2"}, "x2"},
742
    {{"r3"}, "x3"},
743
    {{"r4"}, "x4"},
744
    {{"r5"}, "x5"},
745
    {{"r6"}, "x6"},
746
    {{"r7"}, "x7"},
747
    {{"r8"}, "x8"},
748
    {{"r9"}, "x9"},
749
    {{"r10"}, "x10"},
750
    {{"r11"}, "x11"},
751
    {{"r12"}, "x12"},
752
    {{"r13"}, "x13"},
753
    {{"r14"}, "x14"},
754
    {{"r15"}, "x15"},
755
    {{"r16"}, "x16"},
756
    {{"r17"}, "x17"},
757
    {{"r18"}, "x18"},
758
    {{"r19"}, "x19"},
759
    {{"r20"}, "x20"},
760
    {{"r21"}, "x21"},
761
    {{"r22"}, "x22"},
762
    {{"r23"}, "x23"},
763
    {{"r24"}, "x24"},
764
    {{"r25"}, "x25"},
765
    {{"r26"}, "x26"},
766
    {{"r27"}, "x27"},
767
    {{"r28"}, "x28"},
768
    {{"r29", "x29"}, "fp"},
769
    {{"r30", "x30"}, "lr"},
770
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
771
    // don't want to substitute one of these for a different-sized one.
772
};
773
774
828
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
775
828
  return llvm::makeArrayRef(GCCRegAliases);
776
828
}
777
778
bool AArch64TargetInfo::validateAsmConstraint(
779
338
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
780
338
  switch (*Name) {
781
0
  default:
782
0
    return false;
783
284
  case 'w': // Floating point and SIMD registers (V0-V31)
784
284
    Info.setAllowsRegister();
785
284
    return true;
786
2
  case 'I': // Constant that can be used with an ADD instruction
787
2
  case 'J': // Constant that can be used with a SUB instruction
788
4
  case 'K': // Constant that can be used with a 32-bit logical instruction
789
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
790
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
791
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
792
6
  case 'Y': // Floating point constant zero
793
6
  case 'Z': // Integer constant zero
794
6
    return true;
795
4
  case 'Q': // A memory reference with base register and no offset
796
4
    Info.setAllowsMemory();
797
4
    return true;
798
2
  case 'S': // A symbolic address
799
2
    Info.setAllowsRegister();
800
2
    return true;
801
32
  case 'U':
802
32
    if (Name[1] == 'p' && (Name[2] == 'l' || 
Name[2] == 'a'24
)) {
803
      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
804
32
      Info.setAllowsRegister();
805
32
      Name += 2;
806
32
      return true;
807
32
    }
808
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
809
    // Utf: A memory address suitable for ldp/stp in TF mode.
810
    // Usa: An absolute symbolic address.
811
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
812
813
    // Better to return an error saying that it's an unrecognised constraint
814
    // even if this is a valid constraint in gcc.
815
0
    return false;
816
4
  case 'z': // Zero register, wzr or xzr
817
4
    Info.setAllowsRegister();
818
4
    return true;
819
0
  case 'x': // Floating point and SIMD registers (V0-V15)
820
0
    Info.setAllowsRegister();
821
0
    return true;
822
6
  case 'y': // SVE registers (V0-V7)
823
6
    Info.setAllowsRegister();
824
6
    return true;
825
338
  }
826
0
  return false;
827
338
}
828
829
bool AArch64TargetInfo::validateConstraintModifier(
830
    StringRef Constraint, char Modifier, unsigned Size,
831
242
    std::string &SuggestedModifier) const {
832
  // Strip off constraint modifiers.
833
356
  while (Constraint[0] == '=' || 
Constraint[0] == '+'250
||
Constraint[0] == '&'243
)
834
114
    Constraint = Constraint.substr(1);
835
836
242
  switch (Constraint[0]) {
837
185
  default:
838
185
    return true;
839
4
  case 'z':
840
57
  case 'r': {
841
57
    switch (Modifier) {
842
1
    case 'x':
843
7
    case 'w':
844
      // For now assume that the person knows what they're
845
      // doing with the modifier.
846
7
      return true;
847
50
    default:
848
      // By default an 'r' constraint will be in the 'x'
849
      // registers.
850
50
      if (Size == 64)
851
26
        return true;
852
853
24
      if (Size == 512)
854
3
        return HasLS64;
855
856
21
      SuggestedModifier = "w";
857
21
      return false;
858
57
    }
859
57
  }
860
242
  }
861
242
}
862
863
103
const char *AArch64TargetInfo::getClobbers() const { return ""; }
864
865
0
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
866
0
  if (RegNo == 0)
867
0
    return 0;
868
0
  if (RegNo == 1)
869
0
    return 1;
870
0
  return -1;
871
0
}
872
873
9.90k
bool AArch64TargetInfo::hasInt128Type() const { return true; }
874
875
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
876
                                         const TargetOptions &Opts)
877
3.31k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
877
3.06k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
877
244
    : AArch64TargetInfo(Triple, Opts) {}
878
879
3.25k
void AArch64leTargetInfo::setDataLayout() {
880
3.25k
  if (getTriple().isOSBinFormatMachO()) {
881
180
    if(getTriple().isArch32Bit())
882
14
      resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
883
166
    else
884
166
      resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
885
180
  } else
886
3.07k
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
887
3.25k
}
888
889
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
890
3.30k
                                           MacroBuilder &Builder) const {
891
3.30k
  Builder.defineMacro("__AARCH64EL__");
892
3.30k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
893
3.30k
}
894
895
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
896
                                         const TargetOptions &Opts)
897
33
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
897
10
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
897
23
    : AArch64TargetInfo(Triple, Opts) {}
898
899
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
900
33
                                           MacroBuilder &Builder) const {
901
33
  Builder.defineMacro("__AARCH64EB__");
902
33
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
903
33
  Builder.defineMacro("__ARM_BIG_ENDIAN");
904
33
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
905
33
}
906
907
33
void AArch64beTargetInfo::setDataLayout() {
908
33
  assert(!getTriple().isOSBinFormatMachO());
909
0
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
910
33
}
911
912
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
913
                                               const TargetOptions &Opts)
914
56
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
915
916
  // This is an LLP64 platform.
917
  // int:4, long:4, long long:8, long double:8.
918
56
  IntWidth = IntAlign = 32;
919
56
  LongWidth = LongAlign = 32;
920
56
  DoubleAlign = LongLongAlign = 64;
921
56
  LongDoubleWidth = LongDoubleAlign = 64;
922
56
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
923
56
  IntMaxType = SignedLongLong;
924
56
  Int64Type = SignedLongLong;
925
56
  SizeType = UnsignedLongLong;
926
56
  PtrDiffType = SignedLongLong;
927
56
  IntPtrType = SignedLongLong;
928
56
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
914
56
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
915
916
  // This is an LLP64 platform.
917
  // int:4, long:4, long long:8, long double:8.
918
56
  IntWidth = IntAlign = 32;
919
56
  LongWidth = LongAlign = 32;
920
56
  DoubleAlign = LongLongAlign = 64;
921
56
  LongDoubleWidth = LongDoubleAlign = 64;
922
56
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
923
56
  IntMaxType = SignedLongLong;
924
56
  Int64Type = SignedLongLong;
925
56
  SizeType = UnsignedLongLong;
926
56
  PtrDiffType = SignedLongLong;
927
56
  IntPtrType = SignedLongLong;
928
56
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
929
930
56
void WindowsARM64TargetInfo::setDataLayout() {
931
56
  resetDataLayout(Triple.isOSBinFormatMachO()
932
56
                      ? 
"e-m:o-i64:64-i128:128-n32:64-S128"1
933
56
                      : 
"e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"55
,
934
56
                  Triple.isOSBinFormatMachO() ? 
"_"1
:
""55
);
935
56
}
936
937
TargetInfo::BuiltinVaListKind
938
58
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
939
58
  return TargetInfo::CharPtrBuiltinVaList;
940
58
}
941
942
TargetInfo::CallingConvCheckResult
943
62
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
944
62
  switch (CC) {
945
3
  case CC_X86StdCall:
946
5
  case CC_X86ThisCall:
947
6
  case CC_X86FastCall:
948
7
  case CC_X86VectorCall:
949
7
    return CCCR_Ignore;
950
42
  case CC_C:
951
42
  case CC_OpenCLKernel:
952
47
  case CC_PreserveMost:
953
52
  case CC_PreserveAll:
954
54
  case CC_Swift:
955
55
  case CC_SwiftAsync:
956
55
  case CC_Win64:
957
55
    return CCCR_OK;
958
0
  default:
959
0
    return CCCR_Warning;
960
62
  }
961
62
}
962
963
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
964
                                                   const TargetOptions &Opts)
965
53
    : WindowsARM64TargetInfo(Triple, Opts) {
966
53
  TheCXXABI.set(TargetCXXABI::Microsoft);
967
53
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
965
53
    : WindowsARM64TargetInfo(Triple, Opts) {
966
53
  TheCXXABI.set(TargetCXXABI::Microsoft);
967
53
}
968
969
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
970
53
                                                MacroBuilder &Builder) const {
971
53
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
972
53
  Builder.defineMacro("_M_ARM64", "1");
973
53
}
974
975
TargetInfo::CallingConvKind
976
109
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
977
109
  return CCK_MicrosoftWin64;
978
109
}
979
980
163
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
981
163
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
982
983
  // MSVC does size based alignment for arm64 based on alignment section in
984
  // below document, replicate that to keep alignment consistent with object
985
  // files compiled by MSVC.
986
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
987
163
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
988
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
989
153
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
990
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
991
96
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
992
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
993
45
  }
994
163
  return Align;
995
163
}
996
997
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
998
                                           const TargetOptions &Opts)
999
3
    : WindowsARM64TargetInfo(Triple, Opts) {
1000
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
1001
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
999
3
    : WindowsARM64TargetInfo(Triple, Opts) {
1000
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
1001
3
}
1002
1003
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
1004
                                                 const TargetOptions &Opts)
1005
179
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1006
179
  Int64Type = SignedLongLong;
1007
179
  if (getTriple().isArch32Bit())
1008
14
    IntMaxType = SignedLongLong;
1009
1010
179
  WCharType = SignedInt;
1011
179
  UseSignedCharForObjCBool = false;
1012
1013
179
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
1014
179
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1015
1016
179
  UseZeroLengthBitfieldAlignment = false;
1017
1018
179
  if (getTriple().isArch32Bit()) {
1019
14
    UseBitFieldTypeAlignment = false;
1020
14
    ZeroLengthBitfieldBoundary = 32;
1021
14
    UseZeroLengthBitfieldAlignment = true;
1022
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
1023
14
  } else
1024
165
    TheCXXABI.set(TargetCXXABI::AppleARM64);
1025
179
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1005
179
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1006
179
  Int64Type = SignedLongLong;
1007
179
  if (getTriple().isArch32Bit())
1008
14
    IntMaxType = SignedLongLong;
1009
1010
179
  WCharType = SignedInt;
1011
179
  UseSignedCharForObjCBool = false;
1012
1013
179
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
1014
179
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1015
1016
179
  UseZeroLengthBitfieldAlignment = false;
1017
1018
179
  if (getTriple().isArch32Bit()) {
1019
14
    UseBitFieldTypeAlignment = false;
1020
14
    ZeroLengthBitfieldBoundary = 32;
1021
14
    UseZeroLengthBitfieldAlignment = true;
1022
14
    TheCXXABI.set(TargetCXXABI::WatchOS);
1023
14
  } else
1024
165
    TheCXXABI.set(TargetCXXABI::AppleARM64);
1025
179
}
1026
1027
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
1028
                                           const llvm::Triple &Triple,
1029
179
                                           MacroBuilder &Builder) const {
1030
179
  Builder.defineMacro("__AARCH64_SIMD__");
1031
179
  if (Triple.isArch32Bit())
1032
14
    Builder.defineMacro("__ARM64_ARCH_8_32__");
1033
165
  else
1034
165
    Builder.defineMacro("__ARM64_ARCH_8__");
1035
179
  Builder.defineMacro("__ARM_NEON__");
1036
179
  Builder.defineMacro("__LITTLE_ENDIAN__");
1037
179
  Builder.defineMacro("__REGISTER_PREFIX__", "");
1038
179
  Builder.defineMacro("__arm64", "1");
1039
179
  Builder.defineMacro("__arm64__", "1");
1040
1041
179
  if (Triple.isArm64e())
1042
3
    Builder.defineMacro("__arm64e__", "1");
1043
1044
179
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1045
179
}
1046
1047
TargetInfo::BuiltinVaListKind
1048
194
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
1049
194
  return TargetInfo::CharPtrBuiltinVaList;
1050
194
}
1051
1052
// 64-bit RenderScript is aarch64
1053
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
1054
                                                   const TargetOptions &Opts)
1055
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
1056
                                       Triple.getOSName(),
1057
                                       Triple.getEnvironmentName()),
1058
1
                          Opts) {
1059
1
  IsRenderScriptTarget = true;
1060
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1058
1
                          Opts) {
1059
1
  IsRenderScriptTarget = true;
1060
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1061
1062
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
1063
1
                                                MacroBuilder &Builder) const {
1064
1
  Builder.defineMacro("__RENDERSCRIPT__");
1065
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
1066
1
}