Coverage Report

Created: 2022-01-25 06:29

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AMDGPU.h
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Source (jump to first uncovered line)
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//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares AMDGPU TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#include "clang/Basic/TargetID.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/TargetParser.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
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  static const Builtin::Info BuiltinInfo[];
30
  static const char *const GCCRegNames[];
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32
  enum AddrSpace {
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    Generic = 0,
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    Global = 1,
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    Local = 3,
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    Constant = 4,
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    Private = 5
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  };
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  static const LangASMap AMDGPUDefIsGenMap;
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  static const LangASMap AMDGPUDefIsPrivMap;
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42
  llvm::AMDGPU::GPUKind GPUKind;
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  unsigned GPUFeatures;
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  unsigned WavefrontSize;
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  /// Target ID is device name followed by optional feature name postfixed
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  /// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-.
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  /// If the target ID contains feature+, map it to true.
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  /// If the target ID contains feature-, map it to false.
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  /// If the target ID does not contain a feature (default), do not map it.
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  llvm::StringMap<bool> OffloadArchFeatures;
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  std::string TargetID;
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54
540
  bool hasFP64() const {
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540
    return getTriple().getArch() == llvm::Triple::amdgcn ||
56
540
           
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64)81
;
57
540
  }
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  /// Has fast fma f32
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180
  bool hasFastFMAF() const {
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180
    return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32);
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180
  }
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  /// Has fast fma f64
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180
  bool hasFastFMA() const {
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180
    return getTriple().getArch() == llvm::Triple::amdgcn;
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180
  }
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180
  bool hasFMAF() const {
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180
    return getTriple().getArch() == llvm::Triple::amdgcn ||
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180
           
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA)27
;
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180
  }
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0
  bool hasFullRateDenormalsF32() const {
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0
    return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32);
76
0
  }
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180
  bool hasLDEXPF() const {
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180
    return getTriple().getArch() == llvm::Triple::amdgcn ||
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180
           
!!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP)27
;
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180
  }
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1.55k
  static bool isAMDGCN(const llvm::Triple &TT) {
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1.55k
    return TT.getArch() == llvm::Triple::amdgcn;
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1.55k
  }
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842
  static bool isR600(const llvm::Triple &TT) {
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842
    return TT.getArch() == llvm::Triple::r600;
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842
  }
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public:
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  AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void setAddressSpaceMap(bool DefaultIsPrivate);
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  void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
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842
  uint64_t getPointerWidthV(unsigned AddrSpace) const override {
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842
    if (isR600(getTriple()))
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94
      return 32;
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102
748
    if (AddrSpace == Private || 
AddrSpace == Local555
)
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      return 32;
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453
    return 64;
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748
  }
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301
  uint64_t getPointerAlignV(unsigned AddrSpace) const override {
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    return getPointerWidthV(AddrSpace);
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  }
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1.47k
  uint64_t getMaxPointerWidth() const override {
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1.47k
    return getTriple().getArch() == llvm::Triple::amdgcn ? 
641.36k
:
32109
;
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1.47k
  }
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0
  const char *getClobbers() const override { return ""; }
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  ArrayRef<const char *> getGCCRegNames() const override;
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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    return None;
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  }
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  /// Accepted register names: (n, m is unsigned integer, n < m)
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  /// v
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  /// s
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  /// a
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  /// {vn}, {v[n]}
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  /// {sn}, {s[n]}
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  /// {an}, {a[n]}
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  /// {S} , where S is a special register name
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  ////{v[n:m]}
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  /// {s[n:m]}
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  /// {a[n:m]}
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  bool validateAsmConstraint(const char *&Name,
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0
                             TargetInfo::ConstraintInfo &Info) const override {
137
0
    static const ::llvm::StringSet<> SpecialRegs({
138
0
        "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",
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        "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",
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        "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",
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    });
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    switch (*Name) {
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    case 'I':
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      Info.setRequiresImmediate(-16, 64);
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      return true;
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0
    case 'J':
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      Info.setRequiresImmediate(-32768, 32767);
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0
      return true;
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    case 'A':
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0
    case 'B':
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0
    case 'C':
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      Info.setRequiresImmediate();
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      return true;
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0
    default:
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      break;
157
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    }
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159
0
    StringRef S(Name);
160
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0
    if (S == "DA" || S == "DB") {
162
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      Name++;
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      Info.setRequiresImmediate();
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      return true;
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0
    }
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    bool HasLeftParen = false;
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0
    if (S.front() == '{') {
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      HasLeftParen = true;
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      S = S.drop_front();
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    }
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    if (S.empty())
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      return false;
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0
    if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') {
175
0
      if (!HasLeftParen)
176
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        return false;
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0
      auto E = S.find('}');
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0
      if (!SpecialRegs.count(S.substr(0, E)))
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        return false;
180
0
      S = S.drop_front(E + 1);
181
0
      if (!S.empty())
182
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        return false;
183
      // Found {S} where S is a special register.
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0
      Info.setAllowsRegister();
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0
      Name = S.data() - 1;
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      return true;
187
0
    }
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    S = S.drop_front();
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    if (!HasLeftParen) {
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0
      if (!S.empty())
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        return false;
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      // Found s, v or a.
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      Info.setAllowsRegister();
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      Name = S.data() - 1;
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      return true;
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    }
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    bool HasLeftBracket = false;
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    if (!S.empty() && S.front() == '[') {
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      HasLeftBracket = true;
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      S = S.drop_front();
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    }
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0
    unsigned long long N;
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    if (S.empty() || consumeUnsignedInteger(S, 10, N))
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      return false;
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    if (!S.empty() && S.front() == ':') {
206
0
      if (!HasLeftBracket)
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        return false;
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      S = S.drop_front();
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      unsigned long long M;
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      if (consumeUnsignedInteger(S, 10, M) || N >= M)
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        return false;
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0
    }
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    if (HasLeftBracket) {
214
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      if (S.empty() || S.front() != ']')
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        return false;
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      S = S.drop_front();
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    }
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    if (S.empty() || S.front() != '}')
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      return false;
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    S = S.drop_front();
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    if (!S.empty())
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      return false;
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    // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}
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    // or {a[n:m]}.
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    Info.setAllowsRegister();
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0
    Name = S.data() - 1;
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    return true;
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  }
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  // \p Constraint will be left pointing at the last character of
231
  // the constraint.  In practice, it won't be changed unless the
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  // constraint is longer than one character.
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0
  std::string convertConstraint(const char *&Constraint) const override {
234
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0
    StringRef S(Constraint);
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0
    if (S == "DA" || S == "DB") {
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      return std::string("^") + std::string(Constraint++, 2);
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    }
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    const char *Begin = Constraint;
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    TargetInfo::ConstraintInfo Info("", "");
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    if (validateAsmConstraint(Constraint, Info))
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      return std::string(Begin).substr(0, Constraint - Begin + 1);
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    Constraint = Begin;
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    return std::string(1, *Constraint);
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  }
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  bool
250
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
251
                 StringRef CPU,
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                 const std::vector<std::string> &FeatureVec) const override;
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
255
256
1.47k
  bool useFP16ConversionIntrinsics() const override { return false; }
257
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  void getTargetDefines(const LangOptions &Opts,
259
                        MacroBuilder &Builder) const override;
260
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160
  BuiltinVaListKind getBuiltinVaListKind() const override {
262
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    return TargetInfo::CharPtrBuiltinVaList;
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  }
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0
  bool isValidCPUName(StringRef Name) const override {
266
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    if (getTriple().getArch() == llvm::Triple::amdgcn)
267
0
      return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
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0
    return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
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0
  }
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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273
37
  bool setCPU(const std::string &Name) override {
274
37
    if (getTriple().getArch() == llvm::Triple::amdgcn) {
275
22
      GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
276
22
      GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
277
22
    } else {
278
15
      GPUKind = llvm::AMDGPU::parseArchR600(Name);
279
15
      GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind);
280
15
    }
281
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37
    return GPUKind != llvm::AMDGPU::GK_NONE;
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  }
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  void setSupportedOpenCLOpts() override {
286
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    auto &Opts = getSupportedOpenCLOpts();
287
180
    Opts["cl_clang_storage_class_specifiers"] = true;
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180
    Opts["__cl_clang_variadic_functions"] = true;
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    Opts["__cl_clang_function_pointers"] = true;
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    Opts["__cl_clang_non_portable_kernel_param_types"] = true;
291
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    Opts["__cl_clang_bitfields"] = true;
292
293
180
    bool IsAMDGCN = isAMDGCN(getTriple());
294
295
180
    Opts["cl_khr_fp64"] = hasFP64();
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180
    Opts["__opencl_c_fp64"] = hasFP64();
297
298
180
    if (IsAMDGCN || 
GPUKind >= llvm::AMDGPU::GK_CEDAR27
) {
299
155
      Opts["cl_khr_byte_addressable_store"] = true;
300
155
      Opts["cl_khr_global_int32_base_atomics"] = true;
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155
      Opts["cl_khr_global_int32_extended_atomics"] = true;
302
155
      Opts["cl_khr_local_int32_base_atomics"] = true;
303
155
      Opts["cl_khr_local_int32_extended_atomics"] = true;
304
155
    }
305
306
180
    if (IsAMDGCN) {
307
153
      Opts["cl_khr_fp16"] = true;
308
153
      Opts["cl_khr_int64_base_atomics"] = true;
309
153
      Opts["cl_khr_int64_extended_atomics"] = true;
310
153
      Opts["cl_khr_mipmap_image"] = true;
311
153
      Opts["cl_khr_mipmap_image_writes"] = true;
312
153
      Opts["cl_khr_subgroups"] = true;
313
153
      Opts["cl_amd_media_ops"] = true;
314
153
      Opts["cl_amd_media_ops2"] = true;
315
316
153
      Opts["__opencl_c_images"] = true;
317
153
      Opts["__opencl_c_3d_image_writes"] = true;
318
153
      Opts["cl_khr_3d_image_writes"] = true;
319
153
    }
320
180
  }
321
322
40
  LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {
323
40
    switch (TK) {
324
18
    case OCLTK_Image:
325
18
      return LangAS::opencl_constant;
326
327
2
    case OCLTK_ClkEvent:
328
10
    case OCLTK_Queue:
329
12
    case OCLTK_ReserveID:
330
12
      return LangAS::opencl_global;
331
332
10
    default:
333
10
      return TargetInfo::getOpenCLTypeAddrSpace(TK);
334
40
    }
335
40
  }
336
337
2
  LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {
338
2
    switch (AS) {
339
0
    case 0:
340
0
      return LangAS::opencl_generic;
341
0
    case 1:
342
0
      return LangAS::opencl_global;
343
2
    case 3:
344
2
      return LangAS::opencl_local;
345
0
    case 4:
346
0
      return LangAS::opencl_constant;
347
0
    case 5:
348
0
      return LangAS::opencl_private;
349
0
    default:
350
0
      return getLangASFromTargetAS(AS);
351
2
    }
352
2
  }
353
354
30
  LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {
355
30
    switch (AS) {
356
6
    case 0:
357
6
      return LangAS::Default;
358
0
    case 1:
359
0
      return LangAS::cuda_device;
360
18
    case 3:
361
18
      return LangAS::cuda_shared;
362
6
    case 4:
363
6
      return LangAS::cuda_constant;
364
0
    default:
365
0
      return getLangASFromTargetAS(AS);
366
30
    }
367
30
  }
368
369
38
  llvm::Optional<LangAS> getConstantAddressSpace() const override {
370
38
    return getLangASFromTargetAS(Constant);
371
38
  }
372
373
165
  const llvm::omp::GV &getGridValue() const override {
374
165
    switch (WavefrontSize) {
375
0
    case 32:
376
0
      return llvm::omp::getAMDGPUGridValues<32>();
377
165
    case 64:
378
165
      return llvm::omp::getAMDGPUGridValues<64>();
379
0
    default:
380
0
      llvm_unreachable("getGridValue not implemented for this wavesize");
381
165
    }
382
165
  }
383
384
  /// \returns Target specific vtbl ptr address space.
385
0
  unsigned getVtblPtrAddressSpace() const override {
386
0
    return static_cast<unsigned>(Constant);
387
0
  }
388
389
  /// \returns If a target requires an address within a target specific address
390
  /// space \p AddressSpace to be converted in order to be used, then return the
391
  /// corresponding target specific DWARF address space.
392
  ///
393
  /// \returns Otherwise return None and no conversion will be emitted in the
394
  /// DWARF.
395
  Optional<unsigned>
396
20
  getDWARFAddressSpace(unsigned AddressSpace) const override {
397
20
    const unsigned DWARF_Private = 1;
398
20
    const unsigned DWARF_Local = 2;
399
20
    if (AddressSpace == Private) {
400
9
      return DWARF_Private;
401
11
    } else if (AddressSpace == Local) {
402
2
      return DWARF_Local;
403
9
    } else {
404
9
      return None;
405
9
    }
406
20
  }
407
408
192
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
409
192
    switch (CC) {
410
192
    default:
411
192
      return CCCR_Warning;
412
0
    case CC_C:
413
0
    case CC_OpenCLKernel:
414
0
      return CCCR_OK;
415
192
    }
416
192
  }
417
418
  // In amdgcn target the null pointer in global, constant, and generic
419
  // address space has value 0 but in private and local address space has
420
  // value ~0.
421
3.16k
  uint64_t getNullPointerValue(LangAS AS) const override {
422
    // FIXME: Also should handle region.
423
3.16k
    return (AS == LangAS::opencl_local || 
AS == LangAS::opencl_private2.71k
)
424
3.16k
      ? 
~0978
:
02.18k
;
425
3.16k
  }
426
427
  void setAuxTarget(const TargetInfo *Aux) override;
428
429
15
  bool hasBitIntType() const override { return true; }
430
431
  // Record offload arch features since they are needed for defining the
432
  // pre-defined macros.
433
  bool handleTargetFeatures(std::vector<std::string> &Features,
434
180
                            DiagnosticsEngine &Diags) override {
435
180
    auto TargetIDFeatures =
436
180
        getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind));
437
199
    llvm::for_each(Features, [&](const auto &F) {
438
199
      assert(F.front() == '+' || F.front() == '-');
439
199
      if (F == "+wavefrontsize64")
440
0
        WavefrontSize = 64;
441
199
      bool IsOn = F.front() == '+';
442
199
      StringRef Name = StringRef(F).drop_front();
443
199
      if (!llvm::is_contained(TargetIDFeatures, Name))
444
199
        return;
445
0
      assert(OffloadArchFeatures.find(Name) == OffloadArchFeatures.end());
446
0
      OffloadArchFeatures[Name] = IsOn;
447
0
    });
448
180
    return true;
449
180
  }
450
451
21
  Optional<std::string> getTargetID() const override {
452
21
    if (!isAMDGCN(getTriple()))
453
0
      return llvm::None;
454
    // When -target-cpu is not set, we assume generic code that it is valid
455
    // for all GPU and use an empty string as target ID to represent that.
456
21
    if (GPUKind == llvm::AMDGPU::GK_NONE)
457
0
      return std::string("");
458
21
    return getCanonicalTargetID(getArchNameAMDGCN(GPUKind),
459
21
                                OffloadArchFeatures);
460
21
  }
461
};
462
463
} // namespace targets
464
} // namespace clang
465
466
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H