Coverage Report

Created: 2020-09-15 12:33

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AMDGPU.h
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//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares AMDGPU TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#include "clang/Basic/TargetID.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/TargetParser.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
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  static const Builtin::Info BuiltinInfo[];
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  static const char *const GCCRegNames[];
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  enum AddrSpace {
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    Generic = 0,
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    Global = 1,
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    Local = 3,
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    Constant = 4,
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    Private = 5
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  };
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  static const LangASMap AMDGPUDefIsGenMap;
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  static const LangASMap AMDGPUDefIsPrivMap;
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  llvm::AMDGPU::GPUKind GPUKind;
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  unsigned GPUFeatures;
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  /// Target ID is device name followed by optional feature name postfixed
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  /// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sram-ecc-.
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  /// If the target ID contains feature+, map it to true.
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  /// If the target ID contains feature-, map it to false.
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  /// If the target ID does not contain a feature (default), do not map it.
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  llvm::StringMap<bool> OffloadArchFeatures;
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  std::string TargetID;
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642
  bool hasFP64() const {
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642
    return getTriple().getArch() == llvm::Triple::amdgcn ||
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           !!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
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642
  }
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  /// Has fast fma f32
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320
  bool hasFastFMAF() const {
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    return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32);
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320
  }
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  /// Has fast fma f64
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320
  bool hasFastFMA() const {
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320
    return getTriple().getArch() == llvm::Triple::amdgcn;
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320
  }
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  bool hasFMAF() const {
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320
    return getTriple().getArch() == llvm::Triple::amdgcn ||
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           !!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);
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320
  }
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0
  bool hasFullRateDenormalsF32() const {
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0
    return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32);
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0
  }
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320
  bool hasLDEXPF() const {
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320
    return getTriple().getArch() == llvm::Triple::amdgcn ||
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66
           !!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);
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  }
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2.87k
  static bool isAMDGCN(const llvm::Triple &TT) {
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2.87k
    return TT.getArch() == llvm::Triple::amdgcn;
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2.87k
  }
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1.05k
  static bool isR600(const llvm::Triple &TT) {
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1.05k
    return TT.getArch() == llvm::Triple::r600;
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1.05k
  }
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public:
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  AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void setAddressSpaceMap(bool DefaultIsPrivate);
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  void adjust(LangOptions &Opts) override;
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1.05k
  uint64_t getPointerWidthV(unsigned AddrSpace) const override {
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1.05k
    if (isR600(getTriple()))
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50
      return 32;
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1.00k
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1.00k
    if (AddrSpace == Private || 
AddrSpace == Local870
)
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      return 32;
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    return 64;
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  }
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  uint64_t getPointerAlignV(unsigned AddrSpace) const override {
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    return getPointerWidthV(AddrSpace);
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  }
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2.64k
  uint64_t getMaxPointerWidth() const override {
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2.42k
    return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 
32217
;
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2.64k
  }
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  const char *getClobbers() const override { return ""; }
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  ArrayRef<const char *> getGCCRegNames() const override;
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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    return None;
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  }
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  /// Accepted register names: (n, m is unsigned integer, n < m)
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  /// v
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  /// s
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  /// a
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  /// {vn}, {v[n]}
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  /// {sn}, {s[n]}
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  /// {an}, {a[n]}
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  /// {S} , where S is a special register name
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  ////{v[n:m]}
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  /// {s[n:m]}
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  /// {a[n:m]}
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  bool validateAsmConstraint(const char *&Name,
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                             TargetInfo::ConstraintInfo &Info) const override {
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    static const ::llvm::StringSet<> SpecialRegs({
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        "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",
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        "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",
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        "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",
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    });
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    switch (*Name) {
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5
    case 'I':
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      Info.setRequiresImmediate(-16, 64);
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      return true;
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    case 'J':
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      Info.setRequiresImmediate(-32768, 32767);
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      return true;
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    case 'A':
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3
    case 'B':
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3
    case 'C':
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      Info.setRequiresImmediate();
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      return true;
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    default:
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      break;
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    }
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    StringRef S(Name);
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    if (S == "DA" || 
S == "DB"114
) {
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      Name++;
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      Info.setRequiresImmediate();
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      return true;
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    }
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    bool HasLeftParen = false;
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    if (S.front() == '{') {
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      HasLeftParen = true;
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      S = S.drop_front();
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    }
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    if (S.empty())
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1
      return false;
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    if (S.front() != 'v' && 
S.front() != 's'47
&&
S.front() != 'a'26
) {
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      if (!HasLeftParen)
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0
        return false;
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5
      auto E = S.find('}');
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5
      if (!SpecialRegs.count(S.substr(0, E)))
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2
        return false;
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3
      S = S.drop_front(E + 1);
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3
      if (!S.empty())
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        return false;
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      // Found {S} where S is a special register.
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1
      Info.setAllowsRegister();
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1
      Name = S.data() - 1;
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      return true;
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1
    }
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    S = S.drop_front();
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    if (!HasLeftParen) {
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      if (!S.empty())
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        return false;
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      // Found s, v or a.
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      Info.setAllowsRegister();
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      Name = S.data() - 1;
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      return true;
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    }
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    bool HasLeftBracket = false;
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    if (!S.empty() && 
S.front() == '['50
) {
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      HasLeftBracket = true;
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      S = S.drop_front();
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    }
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    unsigned long long N;
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    if (S.empty() || 
consumeUnsignedInteger(S, 10, N)50
)
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      return false;
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    if (!S.empty() && 
S.front() == ':'43
) {
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      if (!HasLeftBracket)
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        return false;
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      S = S.drop_front();
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      unsigned long long M;
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      if (consumeUnsignedInteger(S, 10, M) || 
N >= M18
)
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        return false;
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    }
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    if (HasLeftBracket) {
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      if (S.empty() || S.front() != ']')
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        return false;
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      S = S.drop_front();
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    }
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    if (S.empty() || 
S.front() != '}'36
)
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      return false;
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    S = S.drop_front();
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    if (!S.empty())
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      return false;
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    // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}
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    // or {a[n:m]}.
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    Info.setAllowsRegister();
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    Name = S.data() - 1;
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    return true;
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  }
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  // \p Constraint will be left pointing at the last character of
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  // the constraint.  In practice, it won't be changed unless the
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  // constraint is longer than one character.
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  std::string convertConstraint(const char *&Constraint) const override {
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    StringRef S(Constraint);
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    if (S == "DA" || 
S == "DB"15
) {
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      return std::string("^") + std::string(Constraint++, 2);
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    }
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    const char *Begin = Constraint;
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    TargetInfo::ConstraintInfo Info("", "");
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    if (validateAsmConstraint(Constraint, Info))
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      return std::string(Begin).substr(0, Constraint - Begin + 1);
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0
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0
    Constraint = Begin;
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    return std::string(1, *Constraint);
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  }
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  bool
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  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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                 StringRef CPU,
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                 const std::vector<std::string> &FeatureVec) const override;
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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111
  bool useFP16ConversionIntrinsics() const override { return false; }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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234
  BuiltinVaListKind getBuiltinVaListKind() const override {
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    return TargetInfo::CharPtrBuiltinVaList;
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  }
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  bool isValidCPUName(StringRef Name) const override {
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    if (getTriple().getArch() == llvm::Triple::amdgcn)
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      return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
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0
    return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
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0
  }
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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171
  bool setCPU(const std::string &Name) override {
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    if (getTriple().getArch() == llvm::Triple::amdgcn) {
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      GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
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      GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
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    } else {
277
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      GPUKind = llvm::AMDGPU::parseArchR600(Name);
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      GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind);
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    }
280
171
281
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    return GPUKind != llvm::AMDGPU::GK_NONE;
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  }
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  void setSupportedOpenCLOpts() override {
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    auto &Opts = getSupportedOpenCLOpts();
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    Opts.support("cl_clang_storage_class_specifiers");
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    Opts.support("cl_khr_icd");
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289
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    bool IsAMDGCN = isAMDGCN(getTriple());
290
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291
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    if (hasFP64())
292
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      Opts.support("cl_khr_fp64");
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322
294
322
    if (IsAMDGCN || 
GPUKind >= llvm::AMDGPU::GK_CEDAR67
) {
295
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      Opts.support("cl_khr_byte_addressable_store");
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      Opts.support("cl_khr_global_int32_base_atomics");
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      Opts.support("cl_khr_global_int32_extended_atomics");
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      Opts.support("cl_khr_local_int32_base_atomics");
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      Opts.support("cl_khr_local_int32_extended_atomics");
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    }
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302
322
    if (IsAMDGCN) {
303
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      Opts.support("cl_khr_fp16");
304
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      Opts.support("cl_khr_int64_base_atomics");
305
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      Opts.support("cl_khr_int64_extended_atomics");
306
255
      Opts.support("cl_khr_mipmap_image");
307
255
      Opts.support("cl_khr_mipmap_image_writes");
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      Opts.support("cl_khr_subgroups");
309
255
      Opts.support("cl_khr_3d_image_writes");
310
255
      Opts.support("cl_amd_media_ops");
311
255
      Opts.support("cl_amd_media_ops2");
312
255
    }
313
322
  }
314
315
40
  LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {
316
40
    switch (TK) {
317
18
    case OCLTK_Image:
318
18
      return LangAS::opencl_constant;
319
0
320
12
    case OCLTK_ClkEvent:
321
12
    case OCLTK_Queue:
322
12
    case OCLTK_ReserveID:
323
12
      return LangAS::opencl_global;
324
12
325
10
    default:
326
10
      return TargetInfo::getOpenCLTypeAddrSpace(TK);
327
40
    }
328
40
  }
329
330
118
  LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {
331
118
    switch (AS) {
332
46
    case 0:
333
46
      return LangAS::opencl_generic;
334
0
    case 1:
335
0
      return LangAS::opencl_global;
336
58
    case 3:
337
58
      return LangAS::opencl_local;
338
11
    case 4:
339
11
      return LangAS::opencl_constant;
340
0
    case 5:
341
0
      return LangAS::opencl_private;
342
3
    default:
343
3
      return getLangASFromTargetAS(AS);
344
118
    }
345
118
  }
346
347
5
  LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {
348
5
    return LangAS::Default;
349
5
  }
350
351
96
  llvm::Optional<LangAS> getConstantAddressSpace() const override {
352
96
    return getLangASFromTargetAS(Constant);
353
96
  }
354
355
  /// \returns Target specific vtbl ptr address space.
356
0
  unsigned getVtblPtrAddressSpace() const override {
357
0
    return static_cast<unsigned>(Constant);
358
0
  }
359
360
  /// \returns If a target requires an address within a target specific address
361
  /// space \p AddressSpace to be converted in order to be used, then return the
362
  /// corresponding target specific DWARF address space.
363
  ///
364
  /// \returns Otherwise return None and no conversion will be emitted in the
365
  /// DWARF.
366
  Optional<unsigned>
367
208
  getDWARFAddressSpace(unsigned AddressSpace) const override {
368
208
    const unsigned DWARF_Private = 1;
369
208
    const unsigned DWARF_Local = 2;
370
208
    if (AddressSpace == Private) {
371
77
      return DWARF_Private;
372
131
    } else if (AddressSpace == Local) {
373
26
      return DWARF_Local;
374
105
    } else {
375
105
      return None;
376
105
    }
377
208
  }
378
379
0
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
380
0
    switch (CC) {
381
0
    default:
382
0
      return CCCR_Warning;
383
0
    case CC_C:
384
0
    case CC_OpenCLKernel:
385
0
      return CCCR_OK;
386
0
    }
387
0
  }
388
389
  // In amdgcn target the null pointer in global, constant, and generic
390
  // address space has value 0 but in private and local address space has
391
  // value ~0.
392
3.31k
  uint64_t getNullPointerValue(LangAS AS) const override {
393
    // FIXME: Also should handle region.
394
3.31k
    return (AS == LangAS::opencl_local || 
AS == LangAS::opencl_private2.84k
)
395
2.30k
      ? 
~01.01k
: 0;
396
3.31k
  }
397
398
  void setAuxTarget(const TargetInfo *Aux) override;
399
400
15
  bool hasExtIntType() const override { return true; }
401
402
  // Record offload arch features since they are needed for defining the
403
  // pre-defined macros.
404
  bool handleTargetFeatures(std::vector<std::string> &Features,
405
322
                            DiagnosticsEngine &Diags) override {
406
322
    auto TargetIDFeatures =
407
322
        getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind));
408
740
    llvm::for_each(Features, [&](const auto &F) {
409
740
      assert(F.front() == '+' || F.front() == '-');
410
740
      bool IsOn = F.front() == '+';
411
740
      StringRef Name = StringRef(F).drop_front();
412
740
      if (llvm::find(TargetIDFeatures, Name) == TargetIDFeatures.end())
413
732
        return;
414
8
      assert(OffloadArchFeatures.find(Name) == OffloadArchFeatures.end());
415
8
      OffloadArchFeatures[Name] = IsOn;
416
8
    });
417
322
    return true;
418
322
  }
419
420
109
  Optional<std::string> getTargetID() const override {
421
109
    if (!isAMDGCN(getTriple()))
422
0
      return llvm::None;
423
    // When -target-cpu is not set, we assume generic code that it is valid
424
    // for all GPU and use an empty string as target ID to represent that.
425
109
    if (GPUKind == llvm::AMDGPU::GK_NONE)
426
0
      return std::string("");
427
109
    return getCanonicalTargetID(getArchNameAMDGCN(GPUKind),
428
109
                                OffloadArchFeatures);
429
109
  }
430
};
431
432
} // namespace targets
433
} // namespace clang
434
435
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H