Coverage Report

Created: 2020-02-15 09:57

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements ARM TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARM.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
21
using namespace clang;
22
using namespace clang::targets;
23
24
1.31k
void ARMTargetInfo::setABIAAPCS() {
25
1.31k
  IsAAPCS = true;
26
1.31k
27
1.31k
  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
28
1.31k
  const llvm::Triple &T = getTriple();
29
1.31k
30
1.31k
  bool IsNetBSD = T.isOSNetBSD();
31
1.31k
  bool IsOpenBSD = T.isOSOpenBSD();
32
1.31k
  if (!T.isOSWindows() && 
!IsNetBSD1.21k
&&
!IsOpenBSD1.20k
)
33
1.19k
    WCharType = UnsignedInt;
34
1.31k
35
1.31k
  UseBitFieldTypeAlignment = true;
36
1.31k
37
1.31k
  ZeroLengthBitfieldBoundary = 0;
38
1.31k
39
1.31k
  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
40
1.31k
  // so set preferred for small types to 32.
41
1.31k
  if (T.isOSBinFormatMachO()) {
42
31
    resetDataLayout(BigEndian
43
31
                        ? 
"E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"0
44
31
                        : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
45
1.28k
  } else if (T.isOSWindows()) {
46
97
    assert(!BigEndian && "Windows on ARM does not support big endian");
47
97
    resetDataLayout("e"
48
97
                    "-m:w"
49
97
                    "-p:32:32"
50
97
                    "-Fi8"
51
97
                    "-i64:64"
52
97
                    "-v128:64:128"
53
97
                    "-a:0:32"
54
97
                    "-n32"
55
97
                    "-S64");
56
1.18k
  } else if (T.isOSNaCl()) {
57
2
    assert(!BigEndian && "NaCl on ARM does not support big endian");
58
2
    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
59
1.18k
  } else {
60
1.18k
    resetDataLayout(BigEndian
61
1.18k
                        ? 
"E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"29
62
1.18k
                        : 
"e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"1.15k
);
63
1.18k
  }
64
1.31k
65
1.31k
  // FIXME: Enumerated types are variable width in straight AAPCS.
66
1.31k
}
67
68
267
void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
69
267
  const llvm::Triple &T = getTriple();
70
267
71
267
  IsAAPCS = false;
72
267
73
267
  if (IsAAPCS16)
74
35
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
75
232
  else
76
232
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
77
267
78
267
  WCharType = SignedInt;
79
267
80
267
  // Do not respect the alignment of bit-field types when laying out
81
267
  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
82
267
  UseBitFieldTypeAlignment = false;
83
267
84
267
  /// gcc forces the alignment to 4 bytes, regardless of the type of the
85
267
  /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
86
267
  /// gcc.
87
267
  ZeroLengthBitfieldBoundary = 32;
88
267
89
267
  if (T.isOSBinFormatMachO() && 
IsAAPCS16222
) {
90
35
    assert(!BigEndian && "AAPCS16 does not support big-endian");
91
35
    resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128");
92
232
  } else if (T.isOSBinFormatMachO())
93
187
    resetDataLayout(
94
187
        BigEndian
95
187
            ? 
"E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
96
187
            : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
97
45
  else
98
45
    resetDataLayout(
99
45
        BigEndian
100
45
            ? 
"E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
101
45
            : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
102
267
103
267
  // FIXME: Override "preferred align" for double and long long.
104
267
}
105
106
1.10k
void ARMTargetInfo::setArchInfo() {
107
1.10k
  StringRef ArchName = getTriple().getArchName();
108
1.10k
109
1.10k
  ArchISA = llvm::ARM::parseArchISA(ArchName);
110
1.10k
  CPU = std::string(llvm::ARM::getDefaultCPU(ArchName));
111
1.10k
  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName);
112
1.10k
  if (AK != llvm::ARM::ArchKind::INVALID)
113
980
    ArchKind = AK;
114
1.10k
  setArchInfo(ArchKind);
115
1.10k
}
116
117
1.44k
void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
118
1.44k
  StringRef SubArch;
119
1.44k
120
1.44k
  // cache TargetParser info
121
1.44k
  ArchKind = Kind;
122
1.44k
  SubArch = llvm::ARM::getSubArch(ArchKind);
123
1.44k
  ArchProfile = llvm::ARM::parseArchProfile(SubArch);
124
1.44k
  ArchVersion = llvm::ARM::parseArchVersion(SubArch);
125
1.44k
126
1.44k
  // cache CPU related strings
127
1.44k
  CPUAttr = getCPUAttr();
128
1.44k
  CPUProfile = getCPUProfile();
129
1.44k
}
130
131
1.58k
void ARMTargetInfo::setAtomic() {
132
1.58k
  // when triple does not specify a sub arch,
133
1.58k
  // then we are not using inline atomics
134
1.58k
  bool ShouldUseInlineAtomic =
135
1.58k
      (ArchISA == llvm::ARM::ISAKind::ARM && 
ArchVersion >= 6890
) ||
136
1.58k
      
(923
ArchISA == llvm::ARM::ISAKind::THUMB923
&&
ArchVersion >= 7698
);
137
1.58k
  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
138
1.58k
  if (ArchProfile == llvm::ARM::ProfileKind::M) {
139
272
    MaxAtomicPromoteWidth = 32;
140
272
    if (ShouldUseInlineAtomic)
141
244
      MaxAtomicInlineWidth = 32;
142
1.31k
  } else {
143
1.31k
    MaxAtomicPromoteWidth = 64;
144
1.31k
    if (ShouldUseInlineAtomic)
145
1.06k
      MaxAtomicInlineWidth = 64;
146
1.31k
  }
147
1.58k
}
148
149
4.56k
bool ARMTargetInfo::hasMVE() const {
150
4.56k
  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && 
MVE != 02.46k
;
151
4.56k
}
152
153
118
bool ARMTargetInfo::hasMVEFloat() const {
154
118
  return hasMVE() && (MVE & MVE_FP);
155
118
}
156
157
6.38k
bool ARMTargetInfo::isThumb() const {
158
6.38k
  return ArchISA == llvm::ARM::ISAKind::THUMB;
159
6.38k
}
160
161
243
bool ARMTargetInfo::supportsThumb() const {
162
243
  return CPUAttr.count('T') || 
ArchVersion >= 677
;
163
243
}
164
165
1.61k
bool ARMTargetInfo::supportsThumb2() const {
166
1.61k
  return CPUAttr.equals("6T2") ||
167
1.61k
         
(1.61k
ArchVersion >= 71.61k
&&
!CPUAttr.equals("8M_BASE")1.32k
);
168
1.61k
}
169
170
1.44k
StringRef ARMTargetInfo::getCPUAttr() const {
171
1.44k
  // For most sub-arches, the build attribute CPU name is enough.
172
1.44k
  // For Cortex variants, it's slightly different.
173
1.44k
  switch (ArchKind) {
174
334
  default:
175
334
    return llvm::ARM::getCPUAttr(ArchKind);
176
29
  case llvm::ARM::ArchKind::ARMV6M:
177
29
    return "6M";
178
24
  case llvm::ARM::ArchKind::ARMV7S:
179
24
    return "7S";
180
566
  case llvm::ARM::ArchKind::ARMV7A:
181
566
    return "7A";
182
57
  case llvm::ARM::ArchKind::ARMV7R:
183
57
    return "7R";
184
33
  case llvm::ARM::ArchKind::ARMV7M:
185
33
    return "7M";
186
30
  case llvm::ARM::ArchKind::ARMV7EM:
187
30
    return "7EM";
188
7
  case llvm::ARM::ArchKind::ARMV7VE:
189
7
    return "7VE";
190
144
  case llvm::ARM::ArchKind::ARMV8A:
191
144
    return "8A";
192
3
  case llvm::ARM::ArchKind::ARMV8_1A:
193
3
    return "8_1A";
194
29
  case llvm::ARM::ArchKind::ARMV8_2A:
195
29
    return "8_2A";
196
2
  case llvm::ARM::ArchKind::ARMV8_3A:
197
2
    return "8_3A";
198
16
  case llvm::ARM::ArchKind::ARMV8_4A:
199
16
    return "8_4A";
200
1
  case llvm::ARM::ArchKind::ARMV8_5A:
201
1
    return "8_5A";
202
19
  case llvm::ARM::ArchKind::ARMV8MBaseline:
203
19
    return "8M_BASE";
204
16
  case llvm::ARM::ArchKind::ARMV8MMainline:
205
16
    return "8M_MAIN";
206
10
  case llvm::ARM::ArchKind::ARMV8R:
207
10
    return "8R";
208
123
  case llvm::ARM::ArchKind::ARMV8_1MMainline:
209
123
    return "8_1M_MAIN";
210
1.44k
  }
211
1.44k
}
212
213
1.44k
StringRef ARMTargetInfo::getCPUProfile() const {
214
1.44k
  switch (ArchProfile) {
215
795
  case llvm::ARM::ProfileKind::A:
216
795
    return "A";
217
67
  case llvm::ARM::ProfileKind::R:
218
67
    return "R";
219
250
  case llvm::ARM::ProfileKind::M:
220
250
    return "M";
221
331
  default:
222
331
    return "";
223
1.44k
  }
224
1.44k
}
225
226
ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
227
                             const TargetOptions &Opts)
228
    : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
229
1.10k
      HW_FP(0) {
230
1.10k
  bool IsOpenBSD = Triple.isOSOpenBSD();
231
1.10k
  bool IsNetBSD = Triple.isOSNetBSD();
232
1.10k
233
1.10k
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
234
1.10k
  // environment where size_t is `unsigned long` rather than `unsigned int`
235
1.10k
236
1.10k
  PtrDiffType = IntPtrType =
237
1.10k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
||
IsOpenBSD903
||
238
1.10k
       
IsNetBSD898
)
239
1.10k
          ? 
SignedLong212
240
1.10k
          : 
SignedInt891
;
241
1.10k
242
1.10k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
||
IsOpenBSD903
||
243
1.10k
              
IsNetBSD898
)
244
1.10k
                 ? 
UnsignedLong212
245
1.10k
                 : 
UnsignedInt891
;
246
1.10k
247
1.10k
  // ptrdiff_t is inconsistent on Darwin
248
1.10k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
) &&
249
1.10k
      
!Triple.isWatchABI()200
)
250
173
    PtrDiffType = SignedInt;
251
1.10k
252
1.10k
  // Cache arch related info.
253
1.10k
  setArchInfo();
254
1.10k
255
1.10k
  // {} in inline assembly are neon specifiers, not assembly variant
256
1.10k
  // specifiers.
257
1.10k
  NoAsmVariants = true;
258
1.10k
259
1.10k
  // FIXME: This duplicates code from the driver that sets the -target-abi
260
1.10k
  // option - this code is used if -target-abi isn't passed and should
261
1.10k
  // be unified in some way.
262
1.10k
  if (Triple.isOSBinFormatMachO()) {
263
200
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
264
200
    // the frontend matches that.
265
200
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
266
200
        
Triple.getOS() == llvm::Triple::UnknownOS199
||
267
200
        
ArchProfile == llvm::ARM::ProfileKind::M185
) {
268
15
      setABI("aapcs");
269
185
    } else if (Triple.isWatchABI()) {
270
27
      setABI("aapcs16");
271
158
    } else {
272
158
      setABI("apcs-gnu");
273
158
    }
274
903
  } else if (Triple.isOSWindows()) {
275
95
    // FIXME: this is invalid for WindowsCE
276
95
    setABI("aapcs");
277
808
  } else {
278
808
    // Select the default based on the platform.
279
808
    switch (Triple.getEnvironment()) {
280
219
    case llvm::Triple::Android:
281
219
    case llvm::Triple::GNUEABI:
282
219
    case llvm::Triple::GNUEABIHF:
283
219
    case llvm::Triple::MuslEABI:
284
219
    case llvm::Triple::MuslEABIHF:
285
219
      setABI("aapcs-linux");
286
219
      break;
287
368
    case llvm::Triple::EABIHF:
288
368
    case llvm::Triple::EABI:
289
368
      setABI("aapcs");
290
368
      break;
291
368
    case llvm::Triple::GNU:
292
29
      setABI("apcs-gnu");
293
29
      break;
294
368
    default:
295
192
      if (IsNetBSD)
296
0
        setABI("apcs-gnu");
297
192
      else if (IsOpenBSD)
298
2
        setABI("aapcs-linux");
299
190
      else
300
190
        setABI("aapcs");
301
192
      break;
302
1.10k
    }
303
1.10k
  }
304
1.10k
305
1.10k
  // ARM targets default to using the ARM C++ ABI.
306
1.10k
  TheCXXABI.set(TargetCXXABI::GenericARM);
307
1.10k
308
1.10k
  // ARM has atomics up to 8 bytes
309
1.10k
  setAtomic();
310
1.10k
311
1.10k
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
312
1.10k
  // as well the default alignment
313
1.10k
  if (IsAAPCS && 
(Triple.getEnvironment() != llvm::Triple::Android)889
)
314
876
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
315
1.10k
316
1.10k
  // Do force alignment of members that follow zero length bitfields.  If
317
1.10k
  // the alignment of the zero-length bitfield is greater than the member
318
1.10k
  // that follows it, `bar', `bar' will be aligned as the  type of the
319
1.10k
  // zero length bitfield.
320
1.10k
  UseZeroLengthBitfieldAlignment = true;
321
1.10k
322
1.10k
  if (Triple.getOS() == llvm::Triple::Linux ||
323
1.10k
      
Triple.getOS() == llvm::Triple::UnknownOS832
)
324
797
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
325
797
                           ? 
"llvm.arm.gnu.eabi.mcount"9
326
797
                           : 
"\01mcount"788
;
327
1.10k
328
1.10k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
329
1.10k
}
clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
229
1.10k
      HW_FP(0) {
230
1.10k
  bool IsOpenBSD = Triple.isOSOpenBSD();
231
1.10k
  bool IsNetBSD = Triple.isOSNetBSD();
232
1.10k
233
1.10k
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
234
1.10k
  // environment where size_t is `unsigned long` rather than `unsigned int`
235
1.10k
236
1.10k
  PtrDiffType = IntPtrType =
237
1.10k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
||
IsOpenBSD903
||
238
1.10k
       
IsNetBSD898
)
239
1.10k
          ? 
SignedLong212
240
1.10k
          : 
SignedInt891
;
241
1.10k
242
1.10k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
||
IsOpenBSD903
||
243
1.10k
              
IsNetBSD898
)
244
1.10k
                 ? 
UnsignedLong212
245
1.10k
                 : 
UnsignedInt891
;
246
1.10k
247
1.10k
  // ptrdiff_t is inconsistent on Darwin
248
1.10k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()917
) &&
249
1.10k
      
!Triple.isWatchABI()200
)
250
173
    PtrDiffType = SignedInt;
251
1.10k
252
1.10k
  // Cache arch related info.
253
1.10k
  setArchInfo();
254
1.10k
255
1.10k
  // {} in inline assembly are neon specifiers, not assembly variant
256
1.10k
  // specifiers.
257
1.10k
  NoAsmVariants = true;
258
1.10k
259
1.10k
  // FIXME: This duplicates code from the driver that sets the -target-abi
260
1.10k
  // option - this code is used if -target-abi isn't passed and should
261
1.10k
  // be unified in some way.
262
1.10k
  if (Triple.isOSBinFormatMachO()) {
263
200
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
264
200
    // the frontend matches that.
265
200
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
266
200
        
Triple.getOS() == llvm::Triple::UnknownOS199
||
267
200
        
ArchProfile == llvm::ARM::ProfileKind::M185
) {
268
15
      setABI("aapcs");
269
185
    } else if (Triple.isWatchABI()) {
270
27
      setABI("aapcs16");
271
158
    } else {
272
158
      setABI("apcs-gnu");
273
158
    }
274
903
  } else if (Triple.isOSWindows()) {
275
95
    // FIXME: this is invalid for WindowsCE
276
95
    setABI("aapcs");
277
808
  } else {
278
808
    // Select the default based on the platform.
279
808
    switch (Triple.getEnvironment()) {
280
219
    case llvm::Triple::Android:
281
219
    case llvm::Triple::GNUEABI:
282
219
    case llvm::Triple::GNUEABIHF:
283
219
    case llvm::Triple::MuslEABI:
284
219
    case llvm::Triple::MuslEABIHF:
285
219
      setABI("aapcs-linux");
286
219
      break;
287
368
    case llvm::Triple::EABIHF:
288
368
    case llvm::Triple::EABI:
289
368
      setABI("aapcs");
290
368
      break;
291
368
    case llvm::Triple::GNU:
292
29
      setABI("apcs-gnu");
293
29
      break;
294
368
    default:
295
192
      if (IsNetBSD)
296
0
        setABI("apcs-gnu");
297
192
      else if (IsOpenBSD)
298
2
        setABI("aapcs-linux");
299
190
      else
300
190
        setABI("aapcs");
301
192
      break;
302
1.10k
    }
303
1.10k
  }
304
1.10k
305
1.10k
  // ARM targets default to using the ARM C++ ABI.
306
1.10k
  TheCXXABI.set(TargetCXXABI::GenericARM);
307
1.10k
308
1.10k
  // ARM has atomics up to 8 bytes
309
1.10k
  setAtomic();
310
1.10k
311
1.10k
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
312
1.10k
  // as well the default alignment
313
1.10k
  if (IsAAPCS && 
(Triple.getEnvironment() != llvm::Triple::Android)889
)
314
876
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
315
1.10k
316
1.10k
  // Do force alignment of members that follow zero length bitfields.  If
317
1.10k
  // the alignment of the zero-length bitfield is greater than the member
318
1.10k
  // that follows it, `bar', `bar' will be aligned as the  type of the
319
1.10k
  // zero length bitfield.
320
1.10k
  UseZeroLengthBitfieldAlignment = true;
321
1.10k
322
1.10k
  if (Triple.getOS() == llvm::Triple::Linux ||
323
1.10k
      
Triple.getOS() == llvm::Triple::UnknownOS832
)
324
797
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
325
797
                           ? 
"llvm.arm.gnu.eabi.mcount"9
326
797
                           : 
"\01mcount"788
;
327
1.10k
328
1.10k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
329
1.10k
}
Unexecuted instantiation: clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
330
331
481
StringRef ARMTargetInfo::getABI() const { return ABI; }
332
333
1.58k
bool ARMTargetInfo::setABI(const std::string &Name) {
334
1.58k
  ABI = Name;
335
1.58k
336
1.58k
  // The defaults (above) are for AAPCS, check if we need to change them.
337
1.58k
  //
338
1.58k
  // FIXME: We need support for -meabi... we could just mangle it into the
339
1.58k
  // name.
340
1.58k
  if (Name == "apcs-gnu" || 
Name == "aapcs16"1.34k
) {
341
267
    setABIAPCS(Name == "aapcs16");
342
267
    return true;
343
267
  }
344
1.31k
  if (Name == "aapcs" || 
Name == "aapcs-vfp"315
||
Name == "aapcs-linux"314
) {
345
1.31k
    setABIAAPCS();
346
1.31k
    return true;
347
1.31k
  }
348
0
  return false;
349
0
}
350
351
// FIXME: This should be based on Arch attributes, not CPU names.
352
bool ARMTargetInfo::initFeatureMap(
353
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
354
1.40k
    const std::vector<std::string> &FeaturesVec) const {
355
1.40k
356
1.40k
  std::string ArchFeature;
357
1.40k
  std::vector<StringRef> TargetFeatures;
358
1.40k
  llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName());
359
1.40k
360
1.40k
  // Map the base architecture to an appropriate target feature, so we don't
361
1.40k
  // rely on the target triple.
362
1.40k
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU);
363
1.40k
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
364
1.06k
    CPUArch = Arch;
365
1.40k
  if (CPUArch != llvm::ARM::ArchKind::INVALID) {
366
1.18k
    ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str();
367
1.18k
    TargetFeatures.push_back(ArchFeature);
368
1.18k
  }
369
1.40k
370
1.40k
  // get default FPU features
371
1.40k
  unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
372
1.40k
  llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
373
1.40k
374
1.40k
  // get default Extension features
375
1.40k
  uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
376
1.40k
  llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
377
1.40k
378
1.40k
  for (auto Feature : TargetFeatures)
379
18.3k
    if (Feature[0] == '+')
380
7.25k
      Features[Feature.drop_front(1)] = true;
381
1.40k
382
1.40k
  // Enable or disable thumb-mode explicitly per function to enable mixed
383
1.40k
  // ARM and Thumb code generation.
384
1.40k
  if (isThumb())
385
633
    Features["thumb-mode"] = true;
386
772
  else
387
772
    Features["thumb-mode"] = false;
388
1.40k
389
1.40k
  // Convert user-provided arm and thumb GNU target attributes to
390
1.40k
  // [-|+]thumb-mode target features respectively.
391
1.40k
  std::vector<std::string> UpdatedFeaturesVec;
392
7.61k
  for (const auto &Feature : FeaturesVec) {
393
7.61k
    // Skip soft-float-abi; it's something we only use to initialize a bit of
394
7.61k
    // class state, and is otherwise unrecognized.
395
7.61k
    if (Feature == "+soft-float-abi")
396
377
      continue;
397
7.23k
398
7.23k
    StringRef FixedFeature;
399
7.23k
    if (Feature == "+arm")
400
8
      FixedFeature = "-thumb-mode";
401
7.22k
    else if (Feature == "+thumb")
402
8
      FixedFeature = "+thumb-mode";
403
7.21k
    else
404
7.21k
      FixedFeature = Feature;
405
7.23k
    UpdatedFeaturesVec.push_back(FixedFeature.str());
406
7.23k
  }
407
1.40k
408
1.40k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
409
1.40k
}
410
411
412
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
413
1.10k
                                         DiagnosticsEngine &Diags) {
414
1.10k
  FPU = 0;
415
1.10k
  MVE = 0;
416
1.10k
  CRC = 0;
417
1.10k
  Crypto = 0;
418
1.10k
  DSP = 0;
419
1.10k
  Unaligned = 1;
420
1.10k
  SoftFloat = false;
421
1.10k
  // Note that SoftFloatABI is initialized in our constructor.
422
1.10k
  HWDiv = 0;
423
1.10k
  DotProd = 0;
424
1.10k
  HasFloat16 = true;
425
1.10k
426
1.10k
  // This does not diagnose illegal cases like having both
427
1.10k
  // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
428
12.6k
  for (const auto &Feature : Features) {
429
12.6k
    if (Feature == "+soft-float") {
430
121
      SoftFloat = true;
431
12.5k
    } else if (Feature == "+vfp2sp" || 
Feature == "+vfp2"12.2k
) {
432
580
      FPU |= VFP2FPU;
433
580
      HW_FP |= HW_FP_SP;
434
580
      if (Feature == "+vfp2")
435
279
          HW_FP |= HW_FP_DP;
436
11.9k
    } else if (Feature == "+vfp3sp" || 
Feature == "+vfp3d16sp"11.7k
||
437
11.9k
               
Feature == "+vfp3"11.4k
||
Feature == "+vfp3d16"11.1k
) {
438
1.03k
      FPU |= VFP3FPU;
439
1.03k
      HW_FP |= HW_FP_SP;
440
1.03k
      if (Feature == "+vfp3" || 
Feature == "+vfp3d16"792
)
441
504
          HW_FP |= HW_FP_DP;
442
10.9k
    } else if (Feature == "+vfp4sp" || 
Feature == "+vfp4d16sp"10.7k
||
443
10.9k
               
Feature == "+vfp4"10.5k
||
Feature == "+vfp4d16"10.4k
) {
444
667
      FPU |= VFP4FPU;
445
667
      HW_FP |= HW_FP_SP | HW_FP_HP;
446
667
      if (Feature == "+vfp4" || 
Feature == "+vfp4d16"510
)
447
324
          HW_FP |= HW_FP_DP;
448
10.2k
    } else if (Feature == "+fp-armv8sp" || 
Feature == "+fp-armv8d16sp"10.1k
||
449
10.2k
               
Feature == "+fp-armv8"10.0k
||
Feature == "+fp-armv8d16"9.95k
) {
450
391
      FPU |= FPARMV8;
451
391
      HW_FP |= HW_FP_SP | HW_FP_HP;
452
391
      if (Feature == "+fp-armv8" || 
Feature == "+fp-armv8d16"300
)
453
190
          HW_FP |= HW_FP_DP;
454
9.85k
    } else if (Feature == "+neon") {
455
253
      FPU |= NeonFPU;
456
253
      HW_FP |= HW_FP_SP;
457
9.60k
    } else if (Feature == "+hwdiv") {
458
297
      HWDiv |= HWDivThumb;
459
9.30k
    } else if (Feature == "+hwdiv-arm") {
460
222
      HWDiv |= HWDivARM;
461
9.08k
    } else if (Feature == "+crc") {
462
129
      CRC = 1;
463
8.95k
    } else if (Feature == "+crypto") {
464
64
      Crypto = 1;
465
8.89k
    } else if (Feature == "+dsp") {
466
381
      DSP = 1;
467
8.51k
    } else if (Feature == "+fp64") {
468
278
      HW_FP |= HW_FP_DP;
469
8.23k
    } else if (Feature == "+8msecext") {
470
7
      if (CPUProfile != "M" || ArchVersion != 8) {
471
1
        Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
472
1
        return false;
473
1
      }
474
8.22k
    } else if (Feature == "+strict-align") {
475
289
      Unaligned = 0;
476
7.93k
    } else if (Feature == "+fp16") {
477
210
      HW_FP |= HW_FP_HP;
478
7.72k
    } else if (Feature == "+fullfp16") {
479
33
      HasLegalHalfType = true;
480
7.69k
    } else if (Feature == "+dotprod") {
481
21
      DotProd = true;
482
7.67k
    } else if (Feature == "+mve") {
483
9
      MVE |= MVE_INT;
484
7.66k
    } else if (Feature == "+mve.fp") {
485
110
      HasLegalHalfType = true;
486
110
      FPU |= FPARMV8;
487
110
      MVE |= MVE_INT | MVE_FP;
488
110
      HW_FP |= HW_FP_SP | HW_FP_HP;
489
110
    }
490
12.6k
  }
491
1.10k
492
1.10k
  
switch (ArchVersion) 1.10k
{
493
59
  case 6:
494
59
    if (ArchProfile == llvm::ARM::ProfileKind::M)
495
16
      LDREX = 0;
496
43
    else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
497
3
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
498
40
    else
499
40
      LDREX = LDREX_W;
500
59
    break;
501
562
  case 7:
502
562
    if (ArchProfile == llvm::ARM::ProfileKind::M)
503
35
      LDREX = LDREX_W | LDREX_H | LDREX_B;
504
527
    else
505
527
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
506
562
    break;
507
303
  case 8:
508
303
    LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
509
1.10k
  }
510
1.10k
511
1.10k
  if (!(FPU & NeonFPU) && 
FPMath == FP_Neon847
) {
512
2
    Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
513
2
    return false;
514
2
  }
515
1.09k
516
1.09k
  if (FPMath == FP_Neon)
517
1
    Features.push_back("+neonfp");
518
1.09k
  else if (FPMath == FP_VFP)
519
5
    Features.push_back("-neonfp");
520
1.09k
521
1.09k
  return true;
522
1.09k
}
523
524
3.35k
bool ARMTargetInfo::hasFeature(StringRef Feature) const {
525
3.35k
  return llvm::StringSwitch<bool>(Feature)
526
3.35k
      .Case("arm", true)
527
3.35k
      .Case("aarch32", true)
528
3.35k
      .Case("softfloat", SoftFloat)
529
3.35k
      .Case("thumb", isThumb())
530
3.35k
      .Case("neon", (FPU & NeonFPU) && 
!SoftFloat1.03k
)
531
3.35k
      .Case("vfp", FPU && 
!SoftFloat3.20k
)
532
3.35k
      .Case("hwdiv", HWDiv & HWDivThumb)
533
3.35k
      .Case("hwdiv-arm", HWDiv & HWDivARM)
534
3.35k
      .Case("mve", hasMVE())
535
3.35k
      .Default(false);
536
3.35k
}
537
538
0
bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
539
0
  return Name == "generic" ||
540
0
         llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
541
0
}
542
543
2
void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
544
2
  llvm::ARM::fillValidCPUArchList(Values);
545
2
}
546
547
487
bool ARMTargetInfo::setCPU(const std::string &Name) {
548
487
  if (Name != "generic")
549
340
    setArchInfo(llvm::ARM::parseCPUArch(Name));
550
487
551
487
  if (ArchKind == llvm::ARM::ArchKind::INVALID)
552
2
    return false;
553
485
  setAtomic();
554
485
  CPU = Name;
555
485
  return true;
556
485
}
557
558
8
bool ARMTargetInfo::setFPMath(StringRef Name) {
559
8
  if (Name == "neon") {
560
3
    FPMath = FP_Neon;
561
3
    return true;
562
5
  } else if (Name == "vfp" || 
Name == "vfp2"3
||
Name == "vfp3"2
||
563
5
             
Name == "vfp4"1
) {
564
5
    FPMath = FP_VFP;
565
5
    return true;
566
5
  }
567
0
  return false;
568
0
}
569
570
void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
571
43
                                            MacroBuilder &Builder) const {
572
43
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
573
43
}
574
575
void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
576
40
                                            MacroBuilder &Builder) const {
577
40
  // Also include the ARMv8.1-A defines
578
40
  getTargetDefinesARMV81A(Opts, Builder);
579
40
}
580
581
void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
582
19
                                            MacroBuilder &Builder) const {
583
19
  // Also include the ARMv8.2-A defines
584
19
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
585
19
  getTargetDefinesARMV82A(Opts, Builder);
586
19
}
587
588
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
589
1.08k
                                     MacroBuilder &Builder) const {
590
1.08k
  // Target identification.
591
1.08k
  Builder.defineMacro("__arm");
592
1.08k
  Builder.defineMacro("__arm__");
593
1.08k
  // For bare-metal none-eabi.
594
1.08k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
595
1.08k
      
(519
getTriple().getEnvironment() == llvm::Triple::EABI519
||
596
519
       
getTriple().getEnvironment() == llvm::Triple::EABIHF195
))
597
332
    Builder.defineMacro("__ELF__");
598
1.08k
599
1.08k
  // Target properties.
600
1.08k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
601
1.08k
602
1.08k
  // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
603
1.08k
  // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
604
1.08k
  if (getTriple().isWatchABI())
605
27
    Builder.defineMacro("__ARM_ARCH_7K__", "2");
606
1.08k
607
1.08k
  if (!CPUAttr.empty())
608
1.08k
    Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
609
1.08k
610
1.08k
  // ACLE 6.4.1 ARM/Thumb instruction set architecture
611
1.08k
  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
612
1.08k
  Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
613
1.08k
614
1.08k
  if (ArchVersion >= 8) {
615
303
    // ACLE 6.5.7 Crypto Extension
616
303
    if (Crypto)
617
64
      Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
618
303
    // ACLE 6.5.8 CRC32 Extension
619
303
    if (CRC)
620
129
      Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
621
303
    // ACLE 6.5.10 Numeric Maximum and Minimum
622
303
    Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
623
303
    // ACLE 6.5.9 Directed Rounding
624
303
    Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
625
303
  }
626
1.08k
627
1.08k
  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
628
1.08k
  // is not defined for the M-profile.
629
1.08k
  // NOTE that the default profile is assumed to be 'A'
630
1.08k
  if (CPUProfile.empty() || 
ArchProfile != llvm::ARM::ProfileKind::M859
)
631
884
    Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
632
1.08k
633
1.08k
  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
634
1.08k
  // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the
635
1.08k
  // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
636
1.08k
  // v7 and v8 architectures excluding v8-M Baseline.
637
1.08k
  if (supportsThumb2())
638
843
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
639
243
  else if (supportsThumb())
640
237
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
641
1.08k
642
1.08k
  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
643
1.08k
  // instruction set such as ARM or Thumb.
644
1.08k
  Builder.defineMacro("__ARM_32BIT_STATE", "1");
645
1.08k
646
1.08k
  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
647
1.08k
648
1.08k
  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
649
1.08k
  if (!CPUProfile.empty())
650
859
    Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
651
1.08k
652
1.08k
  // ACLE 6.4.3 Unaligned access supported in hardware
653
1.08k
  if (Unaligned)
654
797
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
655
1.08k
656
1.08k
  // ACLE 6.4.4 LDREX/STREX
657
1.08k
  if (LDREX)
658
898
    Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
659
1.08k
660
1.08k
  // ACLE 6.4.5 CLZ
661
1.08k
  if (ArchVersion == 5 || 
(1.07k
ArchVersion == 61.07k
&&
CPUProfile != "M"58
) ||
662
1.08k
      
ArchVersion > 61.03k
)
663
912
    Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
664
1.08k
665
1.08k
  // ACLE 6.5.1 Hardware Floating Point
666
1.08k
  if (HW_FP)
667
445
    Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
668
1.08k
669
1.08k
  // ACLE predefines.
670
1.08k
  Builder.defineMacro("__ARM_ACLE", "200");
671
1.08k
672
1.08k
  // FP16 support (we currently only support IEEE format).
673
1.08k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
674
1.08k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
675
1.08k
676
1.08k
  // ACLE 6.5.3 Fused multiply-accumulate (FMA)
677
1.08k
  if (ArchVersion >= 7 && 
(FPU & VFP4FPU)856
)
678
180
    Builder.defineMacro("__ARM_FEATURE_FMA", "1");
679
1.08k
680
1.08k
  // Subtarget options.
681
1.08k
682
1.08k
  // FIXME: It's more complicated than this and we don't really support
683
1.08k
  // interworking.
684
1.08k
  // Windows on ARM does not "support" interworking
685
1.08k
  if (5 <= ArchVersion && 
ArchVersion <= 8928
&&
!getTriple().isOSWindows()928
)
686
835
    Builder.defineMacro("__THUMB_INTERWORK__");
687
1.08k
688
1.08k
  if (ABI == "aapcs" || 
ABI == "aapcs-linux"403
||
ABI == "aapcs-vfp"190
) {
689
897
    // Embedded targets on Darwin follow AAPCS, but not EABI.
690
897
    // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
691
897
    if (!getTriple().isOSBinFormatMachO() && 
!getTriple().isOSWindows()873
)
692
778
      Builder.defineMacro("__ARM_EABI__");
693
897
    Builder.defineMacro("__ARM_PCS", "1");
694
897
  }
695
1.08k
696
1.08k
  if ((!SoftFloat && 
!SoftFloatABI965
) ||
ABI == "aapcs-vfp"378
||
ABI == "aapcs16"378
)
697
708
    Builder.defineMacro("__ARM_PCS_VFP", "1");
698
1.08k
699
1.08k
  if (SoftFloat)
700
121
    Builder.defineMacro("__SOFTFP__");
701
1.08k
702
1.08k
  // ACLE position independent code macros.
703
1.08k
  if (Opts.ROPI)
704
2
    Builder.defineMacro("__ARM_ROPI", "1");
705
1.08k
  if (Opts.RWPI)
706
2
    Builder.defineMacro("__ARM_RWPI", "1");
707
1.08k
708
1.08k
  if (ArchKind == llvm::ARM::ArchKind::XSCALE)
709
0
    Builder.defineMacro("__XSCALE__");
710
1.08k
711
1.08k
  if (isThumb()) {
712
487
    Builder.defineMacro("__THUMBEL__");
713
487
    Builder.defineMacro("__thumb__");
714
487
    if (supportsThumb2())
715
435
      Builder.defineMacro("__thumb2__");
716
487
  }
717
1.08k
718
1.08k
  // ACLE 6.4.9 32-bit SIMD instructions
719
1.08k
  if ((CPUProfile != "M" && 
ArchVersion >= 6884
) ||
(374
CPUProfile == "M"374
&&
DSP202
))
720
741
    Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
721
1.08k
722
1.08k
  // ACLE 6.4.10 Hardware Integer Divide
723
1.08k
  if (((HWDiv & HWDivThumb) && 
isThumb()297
) ||
724
1.08k
      
(937
(HWDiv & HWDivARM)937
&&
!isThumb()140
)) {
725
286
    Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
726
286
    Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
727
286
  }
728
1.08k
729
1.08k
  // Note, this is always on in gcc, even though it doesn't make sense.
730
1.08k
  Builder.defineMacro("__APCS_32__");
731
1.08k
732
1.08k
  if (FPUModeIsVFP((FPUMode)FPU)) {
733
445
    Builder.defineMacro("__VFP_FP__");
734
445
    if (FPU & VFP2FPU)
735
301
      Builder.defineMacro("__ARM_VFPV2__");
736
445
    if (FPU & VFP3FPU)
737
289
      Builder.defineMacro("__ARM_VFPV3__");
738
445
    if (FPU & VFP4FPU)
739
190
      Builder.defineMacro("__ARM_VFPV4__");
740
445
    if (FPU & FPARMV8)
741
219
      Builder.defineMacro("__ARM_FPV5__");
742
445
  }
743
1.08k
744
1.08k
  // This only gets set when Neon instructions are actually available, unlike
745
1.08k
  // the VFP define, hence the soft float and arch check. This is subtly
746
1.08k
  // different from gcc, we follow the intent which was that it should be set
747
1.08k
  // when Neon instructions are actually available.
748
1.08k
  if ((FPU & NeonFPU) && 
!SoftFloat253
&&
ArchVersion >= 7252
) {
749
243
    Builder.defineMacro("__ARM_NEON", "1");
750
243
    Builder.defineMacro("__ARM_NEON__");
751
243
    // current AArch32 NEON implementations do not support double-precision
752
243
    // floating-point even when it is present in VFP.
753
243
    Builder.defineMacro("__ARM_NEON_FP",
754
243
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
755
243
  }
756
1.08k
757
1.08k
  if (hasMVE()) {
758
118
    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? 
"3"110
:
"1"8
);
759
118
  }
760
1.08k
761
1.08k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
762
1.08k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
41.08k
));
763
1.08k
764
1.08k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"1.08k
);
765
1.08k
766
1.08k
  // CMSE
767
1.08k
  if (ArchVersion == 8 && 
ArchProfile == llvm::ARM::ProfileKind::M303
)
768
151
    Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? 
"3"8
:
"1"143
);
769
1.08k
770
1.08k
  if (ArchVersion >= 6 && 
CPUAttr != "6M"914
&&
CPUAttr != "8M_BASE"898
) {
771
882
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
772
882
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
773
882
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
774
882
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
775
882
  }
776
1.08k
777
1.08k
  // ACLE 6.4.7 DSP instructions
778
1.08k
  if (DSP) {
779
379
    Builder.defineMacro("__ARM_FEATURE_DSP", "1");
780
379
  }
781
1.08k
782
1.08k
  // ACLE 6.4.8 Saturation instructions
783
1.08k
  bool SAT = false;
784
1.08k
  if ((ArchVersion == 6 && 
CPUProfile != "M"58
) ||
ArchVersion > 61.04k
) {
785
898
    Builder.defineMacro("__ARM_FEATURE_SAT", "1");
786
898
    SAT = true;
787
898
  }
788
1.08k
789
1.08k
  // ACLE 6.4.6 Q (saturation) flag
790
1.08k
  if (DSP || 
SAT707
)
791
901
    Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
792
1.08k
793
1.08k
  if (Opts.UnsafeFPMath)
794
2
    Builder.defineMacro("__ARM_FP_FAST", "1");
795
1.08k
796
1.08k
  // Armv8.2-A FP16 vector intrinsic
797
1.08k
  if ((FPU & NeonFPU) && 
HasLegalHalfType253
)
798
22
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
799
1.08k
800
1.08k
  // Armv8.2-A FP16 scalar intrinsics
801
1.08k
  if (HasLegalHalfType)
802
142
    Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
803
1.08k
804
1.08k
  // Armv8.2-A dot product intrinsics
805
1.08k
  if (DotProd)
806
21
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
807
1.08k
808
1.08k
  switch (ArchKind) {
809
1.04k
  default:
810
1.04k
    break;
811
3
  case llvm::ARM::ArchKind::ARMV8_1A:
812
3
    getTargetDefinesARMV81A(Opts, Builder);
813
3
    break;
814
21
  case llvm::ARM::ArchKind::ARMV8_2A:
815
21
    getTargetDefinesARMV82A(Opts, Builder);
816
21
    break;
817
19
  case llvm::ARM::ArchKind::ARMV8_3A:
818
19
  case llvm::ARM::ArchKind::ARMV8_4A:
819
19
  case llvm::ARM::ArchKind::ARMV8_5A:
820
19
    getTargetDefinesARMV83A(Opts, Builder);
821
19
    break;
822
1.08k
  }
823
1.08k
}
824
825
const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
826
#define BUILTIN(ID, TYPE, ATTRS)                                               \
827
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
828
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
829
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
830
#include "clang/Basic/BuiltinsNEON.def"
831
832
#define BUILTIN(ID, TYPE, ATTRS)                                               \
833
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
834
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
835
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
836
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
837
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
838
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
839
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
840
#include "clang/Basic/BuiltinsARM.def"
841
};
842
843
1.08k
ArrayRef<Builtin::Info> ARMTargetInfo::getTargetBuiltins() const {
844
1.08k
  return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin -
845
1.08k
                                             Builtin::FirstTSBuiltin);
846
1.08k
}
847
848
14
bool ARMTargetInfo::isCLZForZeroUndef() const { return false; }
849
588
TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const {
850
588
  return IsAAPCS
851
588
             ? 
AAPCSABIBuiltinVaList423
852
588
             : 
(getTriple().isWatchABI() 165
?
TargetInfo::CharPtrBuiltinVaList22
853
165
                                         : 
TargetInfo::VoidPtrBuiltinVaList143
);
854
588
}
855
856
const char *const ARMTargetInfo::GCCRegNames[] = {
857
    // Integer registers
858
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
859
    "r12", "sp", "lr", "pc",
860
861
    // Float registers
862
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
863
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
864
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
865
866
    // Double registers
867
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
868
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
869
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
870
871
    // Quad registers
872
    "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11",
873
    "q12", "q13", "q14", "q15"};
874
875
347
ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
876
347
  return llvm::makeArrayRef(GCCRegNames);
877
347
}
878
879
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
880
    {{"a1"}, "r0"},  {{"a2"}, "r1"},        {{"a3"}, "r2"},  {{"a4"}, "r3"},
881
    {{"v1"}, "r4"},  {{"v2"}, "r5"},        {{"v3"}, "r6"},  {{"v4"}, "r7"},
882
    {{"v5"}, "r8"},  {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"},
883
    {{"ip"}, "r12"}, {{"r13"}, "sp"},       {{"r14"}, "lr"}, {{"r15"}, "pc"},
884
    // The S, D and Q registers overlap, but aren't really aliases; we
885
    // don't want to substitute one of these for a different-sized one.
886
};
887
888
177
ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
889
177
  return llvm::makeArrayRef(GCCRegAliases);
890
177
}
891
892
bool ARMTargetInfo::validateAsmConstraint(
893
184
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
894
184
  switch (*Name) {
895
1
  default:
896
1
    break;
897
9
  case 'l': // r0-r7 if thumb, r0-r15 if ARM
898
9
    Info.setAllowsRegister();
899
9
    return true;
900
6
  case 'h': // r8-r15, thumb only
901
6
    if (isThumb()) {
902
4
      Info.setAllowsRegister();
903
4
      return true;
904
4
    }
905
2
    break;
906
4
  case 's': // An integer constant, but allowing only relocatable values.
907
4
    return true;
908
44
  case 't': // s0-s31, d0-d31, or q0-q15
909
44
  case 'w': // s0-s15, d0-d7, or q0-q3
910
44
  case 'x': // s0-s31, d0-d15, or q0-q7
911
44
    Info.setAllowsRegister();
912
44
    return true;
913
44
  case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)
914
16
    // only available in ARMv6T2 and above
915
16
    if (CPUAttr.equals("6T2") || ArchVersion >= 7) {
916
8
      Info.setRequiresImmediate(0, 65535);
917
8
      return true;
918
8
    }
919
8
    break;
920
16
  case 'I':
921
16
    if (isThumb()) {
922
8
      if (!supportsThumb2())
923
4
        Info.setRequiresImmediate(0, 255);
924
4
      else
925
4
        // FIXME: should check if immediate value would be valid for a Thumb2
926
4
        // data-processing instruction
927
4
        Info.setRequiresImmediate();
928
8
    } else
929
8
      // FIXME: should check if immediate value would be valid for an ARM
930
8
      // data-processing instruction
931
8
      Info.setRequiresImmediate();
932
16
    return true;
933
32
  case 'J':
934
32
    if (isThumb() && 
!supportsThumb2()16
)
935
8
      Info.setRequiresImmediate(-255, -1);
936
24
    else
937
24
      Info.setRequiresImmediate(-4095, 4095);
938
32
    return true;
939
8
  case 'K':
940
4
    if (isThumb()) {
941
2
      if (!supportsThumb2())
942
1
        // FIXME: should check if immediate value can be obtained from shifting
943
1
        // a value between 0 and 255 left by any amount
944
1
        Info.setRequiresImmediate();
945
1
      else
946
1
        // FIXME: should check if immediate value would be valid for a Thumb2
947
1
        // data-processing instruction when inverted
948
1
        Info.setRequiresImmediate();
949
2
    } else
950
2
      // FIXME: should check if immediate value would be valid for an ARM
951
2
      // data-processing instruction when inverted
952
2
      Info.setRequiresImmediate();
953
4
    return true;
954
16
  case 'L':
955
16
    if (isThumb()) {
956
8
      if (!supportsThumb2())
957
4
        Info.setRequiresImmediate(-7, 7);
958
4
      else
959
4
        // FIXME: should check if immediate value would be valid for a Thumb2
960
4
        // data-processing instruction when negated
961
4
        Info.setRequiresImmediate();
962
8
    } else
963
8
      // FIXME: should check if immediate value  would be valid for an ARM
964
8
      // data-processing instruction when negated
965
8
      Info.setRequiresImmediate();
966
16
    return true;
967
8
  case 'M':
968
4
    if (isThumb() && 
!supportsThumb2()2
)
969
1
      // FIXME: should check if immediate value is a multiple of 4 between 0 and
970
1
      // 1020
971
1
      Info.setRequiresImmediate();
972
3
    else
973
3
      // FIXME: should check if immediate value is a power of two or a integer
974
3
      // between 0 and 32
975
3
      Info.setRequiresImmediate();
976
4
    return true;
977
16
  case 'N':
978
16
    // Thumb1 only
979
16
    if (isThumb() && 
!supportsThumb2()8
) {
980
4
      Info.setRequiresImmediate(0, 31);
981
4
      return true;
982
4
    }
983
12
    break;
984
12
  case 'O':
985
4
    // Thumb1 only
986
4
    if (isThumb() && 
!supportsThumb2()2
) {
987
1
      // FIXME: should check if immediate value is a multiple of 4 between -508
988
1
      // and 508
989
1
      Info.setRequiresImmediate();
990
1
      return true;
991
1
    }
992
3
    break;
993
4
  case 'Q': // A memory address that is a single base register.
994
4
    Info.setAllowsMemory();
995
4
    return true;
996
6
  case 'T':
997
6
    switch (Name[1]) {
998
0
    default:
999
0
      break;
1000
6
    case 'e': // Even general-purpose register
1001
6
    case 'o': // Odd general-purpose register
1002
6
      Info.setAllowsRegister();
1003
6
      Name++;
1004
6
      return true;
1005
0
    }
1006
0
    break;
1007
2
  case 'U': // a memory reference...
1008
2
    switch (Name[1]) {
1009
2
    case 'q': // ...ARMV4 ldrsb
1010
2
    case 'v': // ...VFP load/store (reg+constant offset)
1011
2
    case 'y': // ...iWMMXt load/store
1012
2
    case 't': // address valid for load/store opaque types wider
1013
2
              // than 128-bits
1014
2
    case 'n': // valid address for Neon doubleword vector load/store
1015
2
    case 'm': // valid address for Neon element and structure load/store
1016
2
    case 's': // valid address for non-offset loads/stores of quad-word
1017
2
              // values in four ARM registers
1018
2
      Info.setAllowsMemory();
1019
2
      Name++;
1020
2
      return true;
1021
0
    }
1022
0
    break;
1023
26
  }
1024
26
  return false;
1025
26
}
1026
1027
306
std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
1028
306
  std::string R;
1029
306
  switch (*Constraint) {
1030
4
  case 'U': // Two-character constraint; add "^" hint for later parsing.
1031
4
  case 'T':
1032
4
    R = std::string("^") + std::string(Constraint, 2);
1033
4
    Constraint++;
1034
4
    break;
1035
5
  case 'p': // 'p' should be translated to 'r' by default.
1036
5
    R = std::string("r");
1037
5
    break;
1038
297
  default:
1039
297
    return std::string(1, *Constraint);
1040
9
  }
1041
9
  return R;
1042
9
}
1043
1044
bool ARMTargetInfo::validateConstraintModifier(
1045
    StringRef Constraint, char Modifier, unsigned Size,
1046
386
    std::string &SuggestedModifier) const {
1047
386
  bool isOutput = (Constraint[0] == '=');
1048
386
  bool isInOut = (Constraint[0] == '+');
1049
386
1050
386
  // Strip off constraint modifiers.
1051
586
  while (Constraint[0] == '=' || 
Constraint[0] == '+'393
||
Constraint[0] == '&'388
)
1052
200
    Constraint = Constraint.substr(1);
1053
386
1054
386
  switch (Constraint[0]) {
1055
161
  default:
1056
161
    break;
1057
225
  case 'r': {
1058
225
    switch (Modifier) {
1059
217
    default:
1060
217
      return (isInOut || 
isOutput215
||
Size <= 6461
);
1061
8
    case 'q':
1062
8
      // A register of size 32 cannot fit a vector type.
1063
8
      return false;
1064
161
    }
1065
161
  }
1066
161
  }
1067
161
1068
161
  return true;
1069
161
}
1070
117
const char *ARMTargetInfo::getClobbers() const {
1071
117
  // FIXME: Is this really right?
1072
117
  return "";
1073
117
}
1074
1075
TargetInfo::CallingConvCheckResult
1076
479
ARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1077
479
  switch (CC) {
1078
479
  case CC_AAPCS:
1079
479
  case CC_AAPCS_VFP:
1080
479
  case CC_Swift:
1081
479
  case CC_OpenCLKernel:
1082
479
    return CCCR_OK;
1083
479
  default:
1084
0
    return CCCR_Warning;
1085
479
  }
1086
479
}
1087
1088
4
int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
1089
4
  if (RegNo == 0)
1090
2
    return 0;
1091
2
  if (RegNo == 1)
1092
2
    return 1;
1093
0
  return -1;
1094
0
}
1095
1096
0
bool ARMTargetInfo::hasSjLjLowering() const { return true; }
1097
1098
ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple,
1099
                                 const TargetOptions &Opts)
1100
1.07k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1100
582
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1100
496
    : ARMTargetInfo(Triple, Opts) {}
1101
1102
void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1103
1.06k
                                       MacroBuilder &Builder) const {
1104
1.06k
  Builder.defineMacro("__ARMEL__");
1105
1.06k
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1106
1.06k
}
1107
1108
ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple,
1109
                                 const TargetOptions &Opts)
1110
25
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1110
9
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1110
16
    : ARMTargetInfo(Triple, Opts) {}
1111
1112
void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts,
1113
25
                                       MacroBuilder &Builder) const {
1114
25
  Builder.defineMacro("__ARMEB__");
1115
25
  Builder.defineMacro("__ARM_BIG_ENDIAN");
1116
25
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1117
25
}
1118
1119
WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
1120
                                           const TargetOptions &Opts)
1121
94
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1122
94
}
clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1121
94
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1122
94
}
Unexecuted instantiation: clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1123
1124
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
1125
81
                                                  MacroBuilder &Builder) const {
1126
81
  // FIXME: this is invalid for WindowsCE
1127
81
  Builder.defineMacro("_M_ARM_NT", "1");
1128
81
  Builder.defineMacro("_M_ARMT", "_M_ARM");
1129
81
  Builder.defineMacro("_M_THUMB", "_M_ARM");
1130
81
1131
81
  assert((Triple.getArch() == llvm::Triple::arm ||
1132
81
          Triple.getArch() == llvm::Triple::thumb) &&
1133
81
         "invalid architecture for Windows ARM target info");
1134
81
  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 
48
:
673
;
1135
81
  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
1136
81
1137
81
  // TODO map the complete set of values
1138
81
  // 31: VFPv3 40: VFPv4
1139
81
  Builder.defineMacro("_M_ARM_FP", "31");
1140
81
}
1141
1142
TargetInfo::BuiltinVaListKind
1143
84
WindowsARMTargetInfo::getBuiltinVaListKind() const {
1144
84
  return TargetInfo::CharPtrBuiltinVaList;
1145
84
}
1146
1147
TargetInfo::CallingConvCheckResult
1148
30
WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1149
30
  switch (CC) {
1150
1
  case CC_X86StdCall:
1151
1
  case CC_X86ThisCall:
1152
1
  case CC_X86FastCall:
1153
1
  case CC_X86VectorCall:
1154
1
    return CCCR_Ignore;
1155
29
  case CC_C:
1156
29
  case CC_OpenCLKernel:
1157
29
  case CC_PreserveMost:
1158
29
  case CC_PreserveAll:
1159
29
  case CC_Swift:
1160
29
    return CCCR_OK;
1161
29
  default:
1162
0
    return CCCR_Warning;
1163
30
  }
1164
30
}
1165
1166
// Windows ARM + Itanium C++ ABI Target
1167
ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(
1168
    const llvm::Triple &Triple, const TargetOptions &Opts)
1169
10
    : WindowsARMTargetInfo(Triple, Opts) {
1170
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1171
10
}
Unexecuted instantiation: clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1169
10
    : WindowsARMTargetInfo(Triple, Opts) {
1170
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1171
10
}
1172
1173
void ItaniumWindowsARMleTargetInfo::getTargetDefines(
1174
10
    const LangOptions &Opts, MacroBuilder &Builder) const {
1175
10
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1176
10
1177
10
  if (Opts.MSVCCompat)
1178
1
    WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1179
10
}
1180
1181
// Windows ARM, MS (C++) ABI
1182
MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
1183
                                                   const TargetOptions &Opts)
1184
80
    : WindowsARMTargetInfo(Triple, Opts) {
1185
80
  TheCXXABI.set(TargetCXXABI::Microsoft);
1186
80
}
Unexecuted instantiation: clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1184
80
    : WindowsARMTargetInfo(Triple, Opts) {
1185
80
  TheCXXABI.set(TargetCXXABI::Microsoft);
1186
80
}
1187
1188
void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1189
80
                                                MacroBuilder &Builder) const {
1190
80
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1191
80
  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1192
80
}
1193
1194
MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple,
1195
                                       const TargetOptions &Opts)
1196
4
    : WindowsARMTargetInfo(Triple, Opts) {
1197
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1198
4
}
Unexecuted instantiation: clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1196
4
    : WindowsARMTargetInfo(Triple, Opts) {
1197
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1198
4
}
1199
1200
void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1201
4
                                          MacroBuilder &Builder) const {
1202
4
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1203
4
  Builder.defineMacro("_ARM_");
1204
4
}
1205
1206
CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
1207
                                         const TargetOptions &Opts)
1208
1
    : ARMleTargetInfo(Triple, Opts) {
1209
1
  this->WCharType = TargetInfo::UnsignedShort;
1210
1
  TLSSupported = false;
1211
1
  DoubleAlign = LongLongAlign = 64;
1212
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1213
1
}
Unexecuted instantiation: clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1208
1
    : ARMleTargetInfo(Triple, Opts) {
1209
1
  this->WCharType = TargetInfo::UnsignedShort;
1210
1
  TLSSupported = false;
1211
1
  DoubleAlign = LongLongAlign = 64;
1212
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1213
1
}
1214
1215
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1216
1
                                           MacroBuilder &Builder) const {
1217
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1218
1
  Builder.defineMacro("_ARM_");
1219
1
  Builder.defineMacro("__CYGWIN__");
1220
1
  Builder.defineMacro("__CYGWIN32__");
1221
1
  DefineStd(Builder, "unix", Opts);
1222
1
  if (Opts.CPlusPlus)
1223
0
    Builder.defineMacro("_GNU_SOURCE");
1224
1
}
1225
1226
DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
1227
                                         const TargetOptions &Opts)
1228
200
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1229
200
  HasAlignMac68kSupport = true;
1230
200
  // iOS always has 64-bit atomic instructions.
1231
200
  // FIXME: This should be based off of the target features in
1232
200
  // ARMleTargetInfo.
1233
200
  MaxAtomicInlineWidth = 64;
1234
200
1235
200
  if (Triple.isWatchABI()) {
1236
27
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1237
27
    TheCXXABI.set(TargetCXXABI::WatchOS);
1238
27
1239
27
    // BOOL should be a real boolean on the new ABI
1240
27
    UseSignedCharForObjCBool = false;
1241
27
  } else
1242
173
    TheCXXABI.set(TargetCXXABI::iOS);
1243
200
}
Unexecuted instantiation: clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1228
200
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1229
200
  HasAlignMac68kSupport = true;
1230
200
  // iOS always has 64-bit atomic instructions.
1231
200
  // FIXME: This should be based off of the target features in
1232
200
  // ARMleTargetInfo.
1233
200
  MaxAtomicInlineWidth = 64;
1234
200
1235
200
  if (Triple.isWatchABI()) {
1236
27
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1237
27
    TheCXXABI.set(TargetCXXABI::WatchOS);
1238
27
1239
27
    // BOOL should be a real boolean on the new ABI
1240
27
    UseSignedCharForObjCBool = false;
1241
27
  } else
1242
173
    TheCXXABI.set(TargetCXXABI::iOS);
1243
200
}
1244
1245
void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts,
1246
                                       const llvm::Triple &Triple,
1247
190
                                       MacroBuilder &Builder) const {
1248
190
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1249
190
}
1250
1251
RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple,
1252
                                                   const TargetOptions &Opts)
1253
    : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
1254
                                   Triple.getOSName(),
1255
                                   Triple.getEnvironmentName()),
1256
1
                      Opts) {
1257
1
  IsRenderScriptTarget = true;
1258
1
  LongWidth = LongAlign = 64;
1259
1
}
clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1256
1
                      Opts) {
1257
1
  IsRenderScriptTarget = true;
1258
1
  LongWidth = LongAlign = 64;
1259
1
}
Unexecuted instantiation: clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1260
1261
void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts,
1262
1
                                                MacroBuilder &Builder) const {
1263
1
  Builder.defineMacro("__RENDERSCRIPT__");
1264
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1265
1
}