Coverage Report

Created: 2022-01-18 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements ARM TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARM.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
21
using namespace clang;
22
using namespace clang::targets;
23
24
1.57k
void ARMTargetInfo::setABIAAPCS() {
25
1.57k
  IsAAPCS = true;
26
27
1.57k
  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
28
1.57k
  BFloat16Width = BFloat16Align = 16;
29
1.57k
  BFloat16Format = &llvm::APFloat::BFloat();
30
31
1.57k
  const llvm::Triple &T = getTriple();
32
33
1.57k
  bool IsNetBSD = T.isOSNetBSD();
34
1.57k
  bool IsOpenBSD = T.isOSOpenBSD();
35
1.57k
  if (!T.isOSWindows() && 
!IsNetBSD1.43k
&&
!IsOpenBSD1.42k
)
36
1.41k
    WCharType = UnsignedInt;
37
38
1.57k
  UseBitFieldTypeAlignment = true;
39
40
1.57k
  ZeroLengthBitfieldBoundary = 0;
41
42
  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
43
  // so set preferred for small types to 32.
44
1.57k
  if (T.isOSBinFormatMachO()) {
45
32
    resetDataLayout(BigEndian
46
32
                        ? 
"E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"0
47
32
                        : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
48
32
                    "_");
49
1.53k
  } else if (T.isOSWindows()) {
50
136
    assert(!BigEndian && "Windows on ARM does not support big endian");
51
0
    resetDataLayout("e"
52
136
                    "-m:w"
53
136
                    "-p:32:32"
54
136
                    "-Fi8"
55
136
                    "-i64:64"
56
136
                    "-v128:64:128"
57
136
                    "-a:0:32"
58
136
                    "-n32"
59
136
                    "-S64");
60
1.40k
  } else if (T.isOSNaCl()) {
61
2
    assert(!BigEndian && "NaCl on ARM does not support big endian");
62
0
    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
63
1.40k
  } else {
64
1.40k
    resetDataLayout(BigEndian
65
1.40k
                        ? 
"E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"41
66
1.40k
                        : 
"e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"1.35k
);
67
1.40k
  }
68
69
  // FIXME: Enumerated types are variable width in straight AAPCS.
70
1.57k
}
71
72
281
void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
73
281
  const llvm::Triple &T = getTriple();
74
75
281
  IsAAPCS = false;
76
77
281
  if (IsAAPCS16)
78
37
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
79
244
  else
80
244
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
81
281
  BFloat16Width = BFloat16Align = 16;
82
281
  BFloat16Format = &llvm::APFloat::BFloat();
83
84
281
  WCharType = SignedInt;
85
86
  // Do not respect the alignment of bit-field types when laying out
87
  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
88
281
  UseBitFieldTypeAlignment = false;
89
90
  /// gcc forces the alignment to 4 bytes, regardless of the type of the
91
  /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
92
  /// gcc.
93
281
  ZeroLengthBitfieldBoundary = 32;
94
95
281
  if (T.isOSBinFormatMachO() && 
IsAAPCS16234
) {
96
37
    assert(!BigEndian && "AAPCS16 does not support big-endian");
97
0
    resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_");
98
244
  } else if (T.isOSBinFormatMachO())
99
197
    resetDataLayout(
100
197
        BigEndian
101
197
            ? 
"E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
102
197
            : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32",
103
197
        "_");
104
47
  else
105
47
    resetDataLayout(
106
47
        BigEndian
107
47
            ? 
"E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
108
47
            : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
109
110
  // FIXME: Override "preferred align" for double and long long.
111
281
}
112
113
1.30k
void ARMTargetInfo::setArchInfo() {
114
1.30k
  StringRef ArchName = getTriple().getArchName();
115
116
1.30k
  ArchISA = llvm::ARM::parseArchISA(ArchName);
117
1.30k
  CPU = std::string(llvm::ARM::getDefaultCPU(ArchName));
118
1.30k
  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName);
119
1.30k
  if (AK != llvm::ARM::ArchKind::INVALID)
120
1.16k
    ArchKind = AK;
121
1.30k
  setArchInfo(ArchKind);
122
1.30k
}
123
124
1.69k
void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
125
1.69k
  StringRef SubArch;
126
127
  // cache TargetParser info
128
1.69k
  ArchKind = Kind;
129
1.69k
  SubArch = llvm::ARM::getSubArch(ArchKind);
130
1.69k
  ArchProfile = llvm::ARM::parseArchProfile(SubArch);
131
1.69k
  ArchVersion = llvm::ARM::parseArchVersion(SubArch);
132
133
  // cache CPU related strings
134
1.69k
  CPUAttr = getCPUAttr();
135
1.69k
  CPUProfile = getCPUProfile();
136
1.69k
}
137
138
1.86k
void ARMTargetInfo::setAtomic() {
139
  // when triple does not specify a sub arch,
140
  // then we are not using inline atomics
141
1.86k
  bool ShouldUseInlineAtomic =
142
1.86k
      (ArchISA == llvm::ARM::ISAKind::ARM && 
ArchVersion >= 6984
) ||
143
1.86k
      
(1.12k
ArchISA == llvm::ARM::ISAKind::THUMB1.12k
&&
ArchVersion >= 7878
);
144
  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
145
1.86k
  if (ArchProfile == llvm::ARM::ProfileKind::M) {
146
404
    MaxAtomicPromoteWidth = 32;
147
404
    if (ShouldUseInlineAtomic)
148
376
      MaxAtomicInlineWidth = 32;
149
1.45k
  } else {
150
1.45k
    MaxAtomicPromoteWidth = 64;
151
1.45k
    if (ShouldUseInlineAtomic)
152
1.17k
      MaxAtomicInlineWidth = 64;
153
1.45k
  }
154
1.86k
}
155
156
6.92k
bool ARMTargetInfo::hasMVE() const {
157
6.92k
  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && 
MVE != 03.65k
;
158
6.92k
}
159
160
164
bool ARMTargetInfo::hasMVEFloat() const {
161
164
  return hasMVE() && (MVE & MVE_FP);
162
164
}
163
164
1.28k
bool ARMTargetInfo::hasCDE() const { return getARMCDECoprocMask() != 0; }
165
166
8.72k
bool ARMTargetInfo::isThumb() const {
167
8.72k
  return ArchISA == llvm::ARM::ISAKind::THUMB;
168
8.72k
}
169
170
277
bool ARMTargetInfo::supportsThumb() const {
171
277
  return CPUAttr.count('T') || 
ArchVersion >= 690
;
172
277
}
173
174
1.95k
bool ARMTargetInfo::supportsThumb2() const {
175
1.95k
  return CPUAttr.equals("6T2") ||
176
1.95k
         
(1.94k
ArchVersion >= 71.94k
&&
!CPUAttr.equals("8M_BASE")1.63k
);
177
1.95k
}
178
179
1.69k
StringRef ARMTargetInfo::getCPUAttr() const {
180
  // For most sub-arches, the build attribute CPU name is enough.
181
  // For Cortex variants, it's slightly different.
182
1.69k
  switch (ArchKind) {
183
361
  default:
184
361
    return llvm::ARM::getCPUAttr(ArchKind);
185
29
  case llvm::ARM::ArchKind::ARMV6M:
186
29
    return "6M";
187
26
  case llvm::ARM::ArchKind::ARMV7S:
188
26
    return "7S";
189
619
  case llvm::ARM::ArchKind::ARMV7A:
190
619
    return "7A";
191
57
  case llvm::ARM::ArchKind::ARMV7R:
192
57
    return "7R";
193
55
  case llvm::ARM::ArchKind::ARMV7M:
194
55
    return "7M";
195
31
  case llvm::ARM::ArchKind::ARMV7EM:
196
31
    return "7EM";
197
7
  case llvm::ARM::ArchKind::ARMV7VE:
198
7
    return "7VE";
199
172
  case llvm::ARM::ArchKind::ARMV8A:
200
172
    return "8A";
201
4
  case llvm::ARM::ArchKind::ARMV8_1A:
202
4
    return "8_1A";
203
32
  case llvm::ARM::ArchKind::ARMV8_2A:
204
32
    return "8_2A";
205
2
  case llvm::ARM::ArchKind::ARMV8_3A:
206
2
    return "8_3A";
207
16
  case llvm::ARM::ArchKind::ARMV8_4A:
208
16
    return "8_4A";
209
1
  case llvm::ARM::ArchKind::ARMV8_5A:
210
1
    return "8_5A";
211
10
  case llvm::ARM::ArchKind::ARMV8_6A:
212
10
    return "8_6A";
213
1
  case llvm::ARM::ArchKind::ARMV8_7A:
214
1
    return "8_7A";
215
1
  case llvm::ARM::ArchKind::ARMV8_8A:
216
1
    return "8_8A";
217
1
  case llvm::ARM::ArchKind::ARMV9A:
218
1
    return "9A";
219
1
  case llvm::ARM::ArchKind::ARMV9_1A:
220
1
    return "9_1A";
221
1
  case llvm::ARM::ArchKind::ARMV9_2A:
222
1
    return "9_2A";
223
1
  case llvm::ARM::ArchKind::ARMV9_3A:
224
1
    return "9_3A";
225
32
  case llvm::ARM::ArchKind::ARMV8MBaseline:
226
32
    return "8M_BASE";
227
39
  case llvm::ARM::ArchKind::ARMV8MMainline:
228
39
    return "8M_MAIN";
229
10
  case llvm::ARM::ArchKind::ARMV8R:
230
10
    return "8R";
231
186
  case llvm::ARM::ArchKind::ARMV8_1MMainline:
232
186
    return "8_1M_MAIN";
233
1.69k
  }
234
1.69k
}
235
236
1.69k
StringRef ARMTargetInfo::getCPUProfile() const {
237
1.69k
  switch (ArchProfile) {
238
898
  case llvm::ARM::ProfileKind::A:
239
898
    return "A";
240
67
  case llvm::ARM::ProfileKind::R:
241
67
    return "R";
242
372
  case llvm::ARM::ProfileKind::M:
243
372
    return "M";
244
358
  default:
245
358
    return "";
246
1.69k
  }
247
1.69k
}
248
249
ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
250
                             const TargetOptions &Opts)
251
    : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
252
1.30k
      HW_FP(0) {
253
1.30k
  bool IsOpenBSD = Triple.isOSOpenBSD();
254
1.30k
  bool IsNetBSD = Triple.isOSNetBSD();
255
256
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
257
  // environment where size_t is `unsigned long` rather than `unsigned int`
258
259
1.30k
  PtrDiffType = IntPtrType =
260
1.30k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
||
IsOpenBSD1.09k
||
261
1.30k
       
IsNetBSD1.08k
)
262
1.30k
          ? 
SignedLong225
263
1.30k
          : 
SignedInt1.07k
;
264
265
1.30k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
||
IsOpenBSD1.09k
||
266
1.30k
              
IsNetBSD1.08k
)
267
1.30k
                 ? 
UnsignedLong225
268
1.30k
                 : 
UnsignedInt1.07k
;
269
270
  // ptrdiff_t is inconsistent on Darwin
271
1.30k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
) &&
272
1.30k
      
!Triple.isWatchABI()213
)
273
184
    PtrDiffType = SignedInt;
274
275
  // Cache arch related info.
276
1.30k
  setArchInfo();
277
278
  // {} in inline assembly are neon specifiers, not assembly variant
279
  // specifiers.
280
1.30k
  NoAsmVariants = true;
281
282
  // FIXME: This duplicates code from the driver that sets the -target-abi
283
  // option - this code is used if -target-abi isn't passed and should
284
  // be unified in some way.
285
1.30k
  if (Triple.isOSBinFormatMachO()) {
286
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
287
    // the frontend matches that.
288
213
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
289
213
        
Triple.getOS() == llvm::Triple::UnknownOS212
||
290
213
        
ArchProfile == llvm::ARM::ProfileKind::M197
) {
291
16
      setABI("aapcs");
292
197
    } else if (Triple.isWatchABI()) {
293
29
      setABI("aapcs16");
294
168
    } else {
295
168
      setABI("apcs-gnu");
296
168
    }
297
1.09k
  } else if (Triple.isOSWindows()) {
298
    // FIXME: this is invalid for WindowsCE
299
116
    setABI("aapcs");
300
974
  } else {
301
    // Select the default based on the platform.
302
974
    switch (Triple.getEnvironment()) {
303
14
    case llvm::Triple::Android:
304
163
    case llvm::Triple::GNUEABI:
305
225
    case llvm::Triple::GNUEABIHF:
306
229
    case llvm::Triple::MuslEABI:
307
231
    case llvm::Triple::MuslEABIHF:
308
231
      setABI("aapcs-linux");
309
231
      break;
310
16
    case llvm::Triple::EABIHF:
311
509
    case llvm::Triple::EABI:
312
509
      setABI("aapcs");
313
509
      break;
314
31
    case llvm::Triple::GNU:
315
31
      setABI("apcs-gnu");
316
31
      break;
317
203
    default:
318
203
      if (IsNetBSD)
319
0
        setABI("apcs-gnu");
320
203
      else if (IsOpenBSD)
321
2
        setABI("aapcs-linux");
322
201
      else
323
201
        setABI("aapcs");
324
203
      break;
325
974
    }
326
974
  }
327
328
  // ARM targets default to using the ARM C++ ABI.
329
1.30k
  TheCXXABI.set(TargetCXXABI::GenericARM);
330
331
  // ARM has atomics up to 8 bytes
332
1.30k
  setAtomic();
333
334
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
335
  // as well the default alignment
336
1.30k
  if (IsAAPCS && 
!Triple.isAndroid()1.07k
)
337
1.06k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
338
339
  // Do force alignment of members that follow zero length bitfields.  If
340
  // the alignment of the zero-length bitfield is greater than the member
341
  // that follows it, `bar', `bar' will be aligned as the  type of the
342
  // zero length bitfield.
343
1.30k
  UseZeroLengthBitfieldAlignment = true;
344
345
1.30k
  if (Triple.getOS() == llvm::Triple::Linux ||
346
1.30k
      
Triple.getOS() == llvm::Triple::UnknownOS1.01k
)
347
964
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
348
964
                           ? 
"llvm.arm.gnu.eabi.mcount"9
349
964
                           : 
"\01mcount"955
;
350
351
1.30k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
352
1.30k
}
clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
252
1.30k
      HW_FP(0) {
253
1.30k
  bool IsOpenBSD = Triple.isOSOpenBSD();
254
1.30k
  bool IsNetBSD = Triple.isOSNetBSD();
255
256
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
257
  // environment where size_t is `unsigned long` rather than `unsigned int`
258
259
1.30k
  PtrDiffType = IntPtrType =
260
1.30k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
||
IsOpenBSD1.09k
||
261
1.30k
       
IsNetBSD1.08k
)
262
1.30k
          ? 
SignedLong225
263
1.30k
          : 
SignedInt1.07k
;
264
265
1.30k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
||
IsOpenBSD1.09k
||
266
1.30k
              
IsNetBSD1.08k
)
267
1.30k
                 ? 
UnsignedLong225
268
1.30k
                 : 
UnsignedInt1.07k
;
269
270
  // ptrdiff_t is inconsistent on Darwin
271
1.30k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.10k
) &&
272
1.30k
      
!Triple.isWatchABI()213
)
273
184
    PtrDiffType = SignedInt;
274
275
  // Cache arch related info.
276
1.30k
  setArchInfo();
277
278
  // {} in inline assembly are neon specifiers, not assembly variant
279
  // specifiers.
280
1.30k
  NoAsmVariants = true;
281
282
  // FIXME: This duplicates code from the driver that sets the -target-abi
283
  // option - this code is used if -target-abi isn't passed and should
284
  // be unified in some way.
285
1.30k
  if (Triple.isOSBinFormatMachO()) {
286
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
287
    // the frontend matches that.
288
213
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
289
213
        
Triple.getOS() == llvm::Triple::UnknownOS212
||
290
213
        
ArchProfile == llvm::ARM::ProfileKind::M197
) {
291
16
      setABI("aapcs");
292
197
    } else if (Triple.isWatchABI()) {
293
29
      setABI("aapcs16");
294
168
    } else {
295
168
      setABI("apcs-gnu");
296
168
    }
297
1.09k
  } else if (Triple.isOSWindows()) {
298
    // FIXME: this is invalid for WindowsCE
299
116
    setABI("aapcs");
300
974
  } else {
301
    // Select the default based on the platform.
302
974
    switch (Triple.getEnvironment()) {
303
14
    case llvm::Triple::Android:
304
163
    case llvm::Triple::GNUEABI:
305
225
    case llvm::Triple::GNUEABIHF:
306
229
    case llvm::Triple::MuslEABI:
307
231
    case llvm::Triple::MuslEABIHF:
308
231
      setABI("aapcs-linux");
309
231
      break;
310
16
    case llvm::Triple::EABIHF:
311
509
    case llvm::Triple::EABI:
312
509
      setABI("aapcs");
313
509
      break;
314
31
    case llvm::Triple::GNU:
315
31
      setABI("apcs-gnu");
316
31
      break;
317
203
    default:
318
203
      if (IsNetBSD)
319
0
        setABI("apcs-gnu");
320
203
      else if (IsOpenBSD)
321
2
        setABI("aapcs-linux");
322
201
      else
323
201
        setABI("aapcs");
324
203
      break;
325
974
    }
326
974
  }
327
328
  // ARM targets default to using the ARM C++ ABI.
329
1.30k
  TheCXXABI.set(TargetCXXABI::GenericARM);
330
331
  // ARM has atomics up to 8 bytes
332
1.30k
  setAtomic();
333
334
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
335
  // as well the default alignment
336
1.30k
  if (IsAAPCS && 
!Triple.isAndroid()1.07k
)
337
1.06k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
338
339
  // Do force alignment of members that follow zero length bitfields.  If
340
  // the alignment of the zero-length bitfield is greater than the member
341
  // that follows it, `bar', `bar' will be aligned as the  type of the
342
  // zero length bitfield.
343
1.30k
  UseZeroLengthBitfieldAlignment = true;
344
345
1.30k
  if (Triple.getOS() == llvm::Triple::Linux ||
346
1.30k
      
Triple.getOS() == llvm::Triple::UnknownOS1.01k
)
347
964
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
348
964
                           ? 
"llvm.arm.gnu.eabi.mcount"9
349
964
                           : 
"\01mcount"955
;
350
351
1.30k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
352
1.30k
}
Unexecuted instantiation: clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
353
354
2.70k
StringRef ARMTargetInfo::getABI() const { return ABI; }
355
356
1.85k
bool ARMTargetInfo::setABI(const std::string &Name) {
357
1.85k
  ABI = Name;
358
359
  // The defaults (above) are for AAPCS, check if we need to change them.
360
  //
361
  // FIXME: We need support for -meabi... we could just mangle it into the
362
  // name.
363
1.85k
  if (Name == "apcs-gnu" || 
Name == "aapcs16"1.60k
) {
364
281
    setABIAPCS(Name == "aapcs16");
365
281
    return true;
366
281
  }
367
1.57k
  if (Name == "aapcs" || 
Name == "aapcs-vfp"327
||
Name == "aapcs-linux"326
) {
368
1.57k
    setABIAAPCS();
369
1.57k
    return true;
370
1.57k
  }
371
0
  return false;
372
1.57k
}
373
374
bool ARMTargetInfo::validateBranchProtection(StringRef Spec,
375
                                             BranchProtectionInfo &BPI,
376
26
                                             StringRef &Err) const {
377
26
  llvm::ARM::ParsedBranchProtection PBP;
378
26
  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
379
7
    return false;
380
381
19
  BPI.SignReturnAddr =
382
19
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
383
19
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
384
19
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
385
19
          .Default(LangOptions::SignReturnAddressScopeKind::None);
386
387
  // Don't care for the sign key, beyond issuing a warning.
388
19
  if (PBP.Key == "b_key")
389
3
    Err = "b-key";
390
19
  BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
391
392
19
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
393
19
  return true;
394
26
}
395
396
// FIXME: This should be based on Arch attributes, not CPU names.
397
bool ARMTargetInfo::initFeatureMap(
398
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
399
1.35k
    const std::vector<std::string> &FeaturesVec) const {
400
401
1.35k
  std::string ArchFeature;
402
1.35k
  std::vector<StringRef> TargetFeatures;
403
1.35k
  llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName());
404
405
  // Map the base architecture to an appropriate target feature, so we don't
406
  // rely on the target triple.
407
1.35k
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU);
408
1.35k
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
409
967
    CPUArch = Arch;
410
1.35k
  if (CPUArch != llvm::ARM::ArchKind::INVALID) {
411
1.21k
    ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str();
412
1.21k
    TargetFeatures.push_back(ArchFeature);
413
1.21k
  }
414
415
  // get default FPU features
416
1.35k
  unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
417
1.35k
  llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
418
419
  // get default Extension features
420
1.35k
  uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
421
1.35k
  llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
422
423
1.35k
  for (auto Feature : TargetFeatures)
424
27.6k
    if (Feature[0] == '+')
425
8.37k
      Features[Feature.drop_front(1)] = true;
426
427
  // Enable or disable thumb-mode explicitly per function to enable mixed
428
  // ARM and Thumb code generation.
429
1.35k
  if (isThumb())
430
664
    Features["thumb-mode"] = true;
431
693
  else
432
693
    Features["thumb-mode"] = false;
433
434
  // Convert user-provided arm and thumb GNU target attributes to
435
  // [-|+]thumb-mode target features respectively.
436
1.35k
  std::vector<std::string> UpdatedFeaturesVec;
437
15.9k
  for (const auto &Feature : FeaturesVec) {
438
    // Skip soft-float-abi; it's something we only use to initialize a bit of
439
    // class state, and is otherwise unrecognized.
440
15.9k
    if (Feature == "+soft-float-abi")
441
421
      continue;
442
443
15.5k
    StringRef FixedFeature;
444
15.5k
    if (Feature == "+arm")
445
8
      FixedFeature = "-thumb-mode";
446
15.5k
    else if (Feature == "+thumb")
447
8
      FixedFeature = "+thumb-mode";
448
15.5k
    else
449
15.5k
      FixedFeature = Feature;
450
15.5k
    UpdatedFeaturesVec.push_back(FixedFeature.str());
451
15.5k
  }
452
453
1.35k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
454
1.35k
}
455
456
457
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
458
1.30k
                                         DiagnosticsEngine &Diags) {
459
1.30k
  FPU = 0;
460
1.30k
  MVE = 0;
461
1.30k
  CRC = 0;
462
1.30k
  Crypto = 0;
463
1.30k
  SHA2 = 0;
464
1.30k
  AES = 0;
465
1.30k
  DSP = 0;
466
1.30k
  Unaligned = 1;
467
1.30k
  SoftFloat = false;
468
  // Note that SoftFloatABI is initialized in our constructor.
469
1.30k
  HWDiv = 0;
470
1.30k
  DotProd = 0;
471
1.30k
  HasMatMul = 0;
472
1.30k
  HasPAC = 0;
473
1.30k
  HasBTI = 0;
474
1.30k
  HasFloat16 = true;
475
1.30k
  ARMCDECoprocMask = 0;
476
1.30k
  HasBFloat16 = false;
477
1.30k
  FPRegsDisabled = false;
478
479
  // This does not diagnose illegal cases like having both
480
  // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
481
19.6k
  for (const auto &Feature : Features) {
482
19.6k
    if (Feature == "+soft-float") {
483
124
      SoftFloat = true;
484
19.5k
    } else if (Feature == "+vfp2sp" || 
Feature == "+vfp2"19.2k
) {
485
680
      FPU |= VFP2FPU;
486
680
      HW_FP |= HW_FP_SP;
487
680
      if (Feature == "+vfp2")
488
321
          HW_FP |= HW_FP_DP;
489
18.8k
    } else if (Feature == "+vfp3sp" || 
Feature == "+vfp3d16sp"18.6k
||
490
18.8k
               
Feature == "+vfp3"18.2k
||
Feature == "+vfp3d16"17.9k
) {
491
1.20k
      FPU |= VFP3FPU;
492
1.20k
      HW_FP |= HW_FP_SP;
493
1.20k
      if (Feature == "+vfp3" || 
Feature == "+vfp3d16"929
)
494
583
          HW_FP |= HW_FP_DP;
495
17.6k
    } else if (Feature == "+vfp4sp" || 
Feature == "+vfp4d16sp"17.5k
||
496
17.6k
               
Feature == "+vfp4"17.2k
||
Feature == "+vfp4d16"17.1k
) {
497
769
      FPU |= VFP4FPU;
498
769
      HW_FP |= HW_FP_SP | HW_FP_HP;
499
769
      if (Feature == "+vfp4" || 
Feature == "+vfp4d16"593
)
500
367
          HW_FP |= HW_FP_DP;
501
16.9k
    } else if (Feature == "+fp-armv8sp" || 
Feature == "+fp-armv8d16sp"16.8k
||
502
16.9k
               
Feature == "+fp-armv8"16.6k
||
Feature == "+fp-armv8d16"16.5k
) {
503
493
      FPU |= FPARMV8;
504
493
      HW_FP |= HW_FP_SP | HW_FP_HP;
505
493
      if (Feature == "+fp-armv8" || 
Feature == "+fp-armv8d16"383
)
506
233
          HW_FP |= HW_FP_DP;
507
16.4k
    } else if (Feature == "+neon") {
508
304
      FPU |= NeonFPU;
509
304
      HW_FP |= HW_FP_SP;
510
16.1k
    } else if (Feature == "+hwdiv") {
511
348
      HWDiv |= HWDivThumb;
512
15.7k
    } else if (Feature == "+hwdiv-arm") {
513
245
      HWDiv |= HWDivARM;
514
15.5k
    } else if (Feature == "+crc") {
515
153
      CRC = 1;
516
15.3k
    } else if (Feature == "+crypto") {
517
19
      Crypto = 1;
518
15.3k
    } else if (Feature == "+sha2") {
519
96
      SHA2 = 1;
520
15.2k
    } else if (Feature == "+aes") {
521
96
      AES = 1;
522
15.1k
    } else if (Feature == "+dsp") {
523
431
      DSP = 1;
524
14.7k
    } else if (Feature == "+fp64") {
525
320
      HW_FP |= HW_FP_DP;
526
14.4k
    } else if (Feature == "+8msecext") {
527
6
      if (CPUProfile != "M" || ArchVersion != 8) {
528
1
        Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
529
1
        return false;
530
1
      }
531
14.3k
    } else if (Feature == "+strict-align") {
532
336
      Unaligned = 0;
533
14.0k
    } else if (Feature == "+fp16") {
534
268
      HW_FP |= HW_FP_HP;
535
13.7k
    } else if (Feature == "+fullfp16") {
536
43
      HasLegalHalfType = true;
537
13.7k
    } else if (Feature == "+dotprod") {
538
30
      DotProd = true;
539
13.7k
    } else if (Feature == "+mve") {
540
27
      MVE |= MVE_INT;
541
13.6k
    } else if (Feature == "+mve.fp") {
542
140
      HasLegalHalfType = true;
543
140
      FPU |= FPARMV8;
544
140
      MVE |= MVE_INT | MVE_FP;
545
140
      HW_FP |= HW_FP_SP | HW_FP_HP;
546
13.5k
    } else if (Feature == "+i8mm") {
547
8
      HasMatMul = 1;
548
13.5k
    } else if (Feature.size() == strlen("+cdecp0") && 
Feature >= "+cdecp0"3.02k
&&
549
13.5k
               
Feature <= "+cdecp7"2.92k
) {
550
26
      unsigned Coproc = Feature.back() - '0';
551
26
      ARMCDECoprocMask |= (1U << Coproc);
552
13.5k
    } else if (Feature == "+bf16") {
553
22
      HasBFloat16 = true;
554
13.4k
    } else if (Feature == "-fpregs") {
555
183
      FPRegsDisabled = true;
556
13.3k
    } else if (Feature == "+pacbti") {
557
1
      HasPAC = 1;
558
1
      HasBTI = 1;
559
1
    }
560
19.6k
  }
561
562
1.30k
  switch (ArchVersion) {
563
59
  case 6:
564
59
    if (ArchProfile == llvm::ARM::ProfileKind::M)
565
16
      LDREX = 0;
566
43
    else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
567
3
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
568
40
    else
569
40
      LDREX = LDREX_W;
570
59
    break;
571
608
  case 7:
572
608
    if (ArchProfile == llvm::ARM::ProfileKind::M)
573
48
      LDREX = LDREX_W | LDREX_H | LDREX_B;
574
560
    else
575
560
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
576
608
    break;
577
435
  case 8:
578
439
  case 9:
579
439
    LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
580
1.30k
  }
581
582
1.30k
  if (!(FPU & NeonFPU) && 
FPMath == FP_Neon996
) {
583
2
    Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
584
2
    return false;
585
2
  }
586
587
1.29k
  if (FPMath == FP_Neon)
588
1
    Features.push_back("+neonfp");
589
1.29k
  else if (FPMath == FP_VFP)
590
5
    Features.push_back("-neonfp");
591
592
1.29k
  return true;
593
1.30k
}
594
595
5.47k
bool ARMTargetInfo::hasFeature(StringRef Feature) const {
596
5.47k
  return llvm::StringSwitch<bool>(Feature)
597
5.47k
      .Case("arm", true)
598
5.47k
      .Case("aarch32", true)
599
5.47k
      .Case("softfloat", SoftFloat)
600
5.47k
      .Case("thumb", isThumb())
601
5.47k
      .Case("neon", (FPU & NeonFPU) && 
!SoftFloat1.74k
)
602
5.47k
      .Case("vfp", FPU && 
!SoftFloat4.70k
)
603
5.47k
      .Case("hwdiv", HWDiv & HWDivThumb)
604
5.47k
      .Case("hwdiv-arm", HWDiv & HWDivARM)
605
5.47k
      .Case("mve", hasMVE())
606
5.47k
      .Default(false);
607
5.47k
}
608
609
1.77k
bool ARMTargetInfo::hasBFloat16Type() const {
610
1.77k
  return HasBFloat16 && 
!SoftFloat189
;
611
1.77k
}
612
613
0
bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
614
0
  return Name == "generic" ||
615
0
         llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
616
0
}
617
618
2
void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
619
2
  llvm::ARM::fillValidCPUArchList(Values);
620
2
}
621
622
561
bool ARMTargetInfo::setCPU(const std::string &Name) {
623
561
  if (Name != "generic")
624
392
    setArchInfo(llvm::ARM::parseCPUArch(Name));
625
626
561
  if (ArchKind == llvm::ARM::ArchKind::INVALID)
627
2
    return false;
628
559
  setAtomic();
629
559
  CPU = Name;
630
559
  return true;
631
561
}
632
633
8
bool ARMTargetInfo::setFPMath(StringRef Name) {
634
8
  if (Name == "neon") {
635
3
    FPMath = FP_Neon;
636
3
    return true;
637
5
  } else if (Name == "vfp" || 
Name == "vfp2"3
||
Name == "vfp3"2
||
638
5
             
Name == "vfp4"1
) {
639
5
    FPMath = FP_VFP;
640
5
    return true;
641
5
  }
642
0
  return false;
643
8
}
644
645
void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
646
62
                                            MacroBuilder &Builder) const {
647
62
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
648
62
}
649
650
void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
651
58
                                            MacroBuilder &Builder) const {
652
  // Also include the ARMv8.1-A defines
653
58
  getTargetDefinesARMV81A(Opts, Builder);
654
58
}
655
656
void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
657
34
                                            MacroBuilder &Builder) const {
658
  // Also include the ARMv8.2-A defines
659
34
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
660
34
  getTargetDefinesARMV82A(Opts, Builder);
661
34
}
662
663
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
664
1.28k
                                     MacroBuilder &Builder) const {
665
  // Target identification.
666
1.28k
  Builder.defineMacro("__arm");
667
1.28k
  Builder.defineMacro("__arm__");
668
  // For bare-metal none-eabi.
669
1.28k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
670
1.28k
      
(672
getTriple().getEnvironment() == llvm::Triple::EABI672
||
671
672
       
getTriple().getEnvironment() == llvm::Triple::EABIHF218
))
672
468
    Builder.defineMacro("__ELF__");
673
674
  // Target properties.
675
1.28k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
676
677
  // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
678
  // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
679
1.28k
  if (getTriple().isWatchABI())
680
29
    Builder.defineMacro("__ARM_ARCH_7K__", "2");
681
682
1.28k
  if (!CPUAttr.empty())
683
1.28k
    Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
684
685
  // ACLE 6.4.1 ARM/Thumb instruction set architecture
686
  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
687
1.28k
  Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
688
689
1.28k
  if (ArchVersion >= 8) {
690
    // ACLE 6.5.7 Crypto Extension
691
    // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained
692
    // feature macros for AES and SHA2
693
439
    if (SHA2 && 
AES96
)
694
95
      Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
695
439
    if (SHA2)
696
96
      Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
697
439
    if (AES)
698
96
      Builder.defineMacro("__ARM_FEATURE_AES", "1");
699
    // ACLE 6.5.8 CRC32 Extension
700
439
    if (CRC)
701
153
      Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
702
    // ACLE 6.5.10 Numeric Maximum and Minimum
703
439
    Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
704
    // ACLE 6.5.9 Directed Rounding
705
439
    Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
706
439
  }
707
708
  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
709
  // is not defined for the M-profile.
710
  // NOTE that the default profile is assumed to be 'A'
711
1.28k
  if (CPUProfile.empty() || 
ArchProfile != llvm::ARM::ProfileKind::M1.03k
)
712
981
    Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
713
714
  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
715
  // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the
716
  // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
717
  // v7 and v8 architectures excluding v8-M Baseline.
718
1.28k
  if (supportsThumb2())
719
1.01k
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
720
277
  else if (supportsThumb())
721
271
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
722
723
  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
724
  // instruction set such as ARM or Thumb.
725
1.28k
  Builder.defineMacro("__ARM_32BIT_STATE", "1");
726
727
  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
728
729
  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
730
1.28k
  if (!CPUProfile.empty())
731
1.03k
    Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
732
733
  // ACLE 6.4.3 Unaligned access supported in hardware
734
1.28k
  if (Unaligned)
735
953
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
736
737
  // ACLE 6.4.4 LDREX/STREX
738
1.28k
  if (LDREX)
739
1.07k
    Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
740
741
  // ACLE 6.4.5 CLZ
742
1.28k
  if (ArchVersion == 5 || 
(1.27k
ArchVersion == 61.27k
&&
CPUProfile != "M"58
) ||
743
1.28k
      
ArchVersion > 61.23k
)
744
1.09k
    Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
745
746
  // ACLE 6.5.1 Hardware Floating Point
747
1.28k
  if (HW_FP)
748
545
    Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
749
750
  // ACLE predefines.
751
1.28k
  Builder.defineMacro("__ARM_ACLE", "200");
752
753
  // FP16 support (we currently only support IEEE format).
754
1.28k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
755
1.28k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
756
757
  // ACLE 6.5.3 Fused multiply-accumulate (FMA)
758
1.28k
  if (ArchVersion >= 7 && 
(FPU & VFP4FPU)1.03k
)
759
220
    Builder.defineMacro("__ARM_FEATURE_FMA", "1");
760
761
  // Subtarget options.
762
763
  // FIXME: It's more complicated than this and we don't really support
764
  // interworking.
765
  // Windows on ARM does not "support" interworking
766
1.28k
  if (5 <= ArchVersion && 
ArchVersion <= 81.10k
&&
!getTriple().isOSWindows()1.10k
)
767
991
    Builder.defineMacro("__THUMB_INTERWORK__");
768
769
1.28k
  if (ABI == "aapcs" || 
ABI == "aapcs-linux"427
||
ABI == "aapcs-vfp"202
) {
770
    // Embedded targets on Darwin follow AAPCS, but not EABI.
771
    // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
772
1.08k
    if (!getTriple().isOSBinFormatMachO() && 
!getTriple().isOSWindows()1.06k
)
773
946
      Builder.defineMacro("__ARM_EABI__");
774
1.08k
    Builder.defineMacro("__ARM_PCS", "1");
775
1.08k
  }
776
777
1.28k
  if ((!SoftFloat && 
!SoftFloatABI1.16k
) ||
ABI == "aapcs-vfp"421
||
ABI == "aapcs16"421
)
778
867
    Builder.defineMacro("__ARM_PCS_VFP", "1");
779
780
1.28k
  if (SoftFloat)
781
124
    Builder.defineMacro("__SOFTFP__");
782
783
  // ACLE position independent code macros.
784
1.28k
  if (Opts.ROPI)
785
2
    Builder.defineMacro("__ARM_ROPI", "1");
786
1.28k
  if (Opts.RWPI)
787
2
    Builder.defineMacro("__ARM_RWPI", "1");
788
789
1.28k
  if (ArchKind == llvm::ARM::ArchKind::XSCALE)
790
0
    Builder.defineMacro("__XSCALE__");
791
792
1.28k
  if (isThumb()) {
793
616
    Builder.defineMacro("__THUMBEL__");
794
616
    Builder.defineMacro("__thumb__");
795
616
    if (supportsThumb2())
796
553
      Builder.defineMacro("__thumb2__");
797
616
  }
798
799
  // ACLE 6.4.9 32-bit SIMD instructions
800
1.28k
  if ((CPUProfile != "M" && 
ArchVersion >= 6981
) ||
(500
CPUProfile == "M"500
&&
DSP307
))
801
825
    Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
802
803
  // ACLE 6.4.10 Hardware Integer Divide
804
1.28k
  if (((HWDiv & HWDivThumb) && 
isThumb()348
) ||
805
1.28k
      
(1.10k
(HWDiv & HWDivARM)1.10k
&&
!isThumb()159
)) {
806
337
    Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
807
337
    Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
808
337
  }
809
810
  // Note, this is always on in gcc, even though it doesn't make sense.
811
1.28k
  Builder.defineMacro("__APCS_32__");
812
813
  // __VFP_FP__ means that the floating-point format is VFP, not that a hardware
814
  // FPU is present. Moreover, the VFP format is the only one supported by
815
  // clang. For these reasons, this macro is always defined.
816
1.28k
  Builder.defineMacro("__VFP_FP__");
817
818
1.28k
  if (FPUModeIsVFP((FPUMode)FPU)) {
819
545
    if (FPU & VFP2FPU)
820
359
      Builder.defineMacro("__ARM_VFPV2__");
821
545
    if (FPU & VFP3FPU)
822
347
      Builder.defineMacro("__ARM_VFPV3__");
823
545
    if (FPU & VFP4FPU)
824
230
      Builder.defineMacro("__ARM_VFPV4__");
825
545
    if (FPU & FPARMV8)
826
287
      Builder.defineMacro("__ARM_FPV5__");
827
545
  }
828
829
  // This only gets set when Neon instructions are actually available, unlike
830
  // the VFP define, hence the soft float and arch check. This is subtly
831
  // different from gcc, we follow the intent which was that it should be set
832
  // when Neon instructions are actually available.
833
1.28k
  if ((FPU & NeonFPU) && 
!SoftFloat304
&&
ArchVersion >= 7303
) {
834
294
    Builder.defineMacro("__ARM_NEON", "1");
835
294
    Builder.defineMacro("__ARM_NEON__");
836
    // current AArch32 NEON implementations do not support double-precision
837
    // floating-point even when it is present in VFP.
838
294
    Builder.defineMacro("__ARM_NEON_FP",
839
294
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
840
294
  }
841
842
1.28k
  if (hasMVE()) {
843
164
    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? 
"3"140
:
"1"24
);
844
164
  }
845
846
1.28k
  if (hasCDE()) {
847
14
    Builder.defineMacro("__ARM_FEATURE_CDE", "1");
848
14
    Builder.defineMacro("__ARM_FEATURE_CDE_COPROC",
849
14
                        "0x" + Twine::utohexstr(getARMCDECoprocMask()));
850
14
  }
851
852
1.28k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
853
1.28k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
41.28k
));
854
855
1.28k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"1.28k
);
856
857
  // CMSE
858
1.28k
  if (ArchVersion == 8 && 
ArchProfile == llvm::ARM::ProfileKind::M435
)
859
243
    Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? 
"3"30
:
"1"213
);
860
861
1.28k
  if (ArchVersion >= 6 && 
CPUAttr != "6M"1.09k
&&
CPUAttr != "8M_BASE"1.07k
) {
862
1.05k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
863
1.05k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
864
1.05k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
865
1.05k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
866
1.05k
  }
867
868
  // ACLE 6.4.7 DSP instructions
869
1.28k
  if (DSP) {
870
429
    Builder.defineMacro("__ARM_FEATURE_DSP", "1");
871
429
  }
872
873
  // ACLE 6.4.8 Saturation instructions
874
1.28k
  bool SAT = false;
875
1.28k
  if ((ArchVersion == 6 && 
CPUProfile != "M"58
) ||
ArchVersion > 61.24k
) {
876
1.07k
    Builder.defineMacro("__ARM_FEATURE_SAT", "1");
877
1.07k
    SAT = true;
878
1.07k
  }
879
880
  // ACLE 6.4.6 Q (saturation) flag
881
1.28k
  if (DSP || 
SAT859
)
882
1.08k
    Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
883
884
1.28k
  if (Opts.UnsafeFPMath)
885
2
    Builder.defineMacro("__ARM_FP_FAST", "1");
886
887
  // Armv8.2-A FP16 vector intrinsic
888
1.28k
  if ((FPU & NeonFPU) && 
HasLegalHalfType304
)
889
19
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
890
891
  // Armv8.2-A FP16 scalar intrinsics
892
1.28k
  if (HasLegalHalfType)
893
180
    Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
894
895
  // Armv8.2-A dot product intrinsics
896
1.28k
  if (DotProd)
897
30
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
898
899
1.28k
  if (HasMatMul)
900
8
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
901
902
1.28k
  if (HasPAC)
903
1
    Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
904
905
1.28k
  if (HasBTI)
906
1
    Builder.defineMacro("__ARM_FEATURE_BTI", "1");
907
908
1.28k
  if (HasBFloat16) {
909
22
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
910
22
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
911
22
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
912
22
  }
913
914
1.28k
  if (Opts.BranchTargetEnforcement)
915
8
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
916
917
1.28k
  if (Opts.hasSignReturnAddress()) {
918
15
    unsigned Value = 1;
919
15
    if (Opts.isSignReturnAddressScopeAll())
920
7
      Value |= 1 << 2;
921
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
922
15
  }
923
924
1.28k
  switch (ArchKind) {
925
1.22k
  default:
926
1.22k
    break;
927
1.22k
  case llvm::ARM::ArchKind::ARMV8_1A:
928
4
    getTargetDefinesARMV81A(Opts, Builder);
929
4
    break;
930
24
  case llvm::ARM::ArchKind::ARMV8_2A:
931
24
    getTargetDefinesARMV82A(Opts, Builder);
932
24
    break;
933
2
  case llvm::ARM::ArchKind::ARMV8_3A:
934
18
  case llvm::ARM::ArchKind::ARMV8_4A:
935
19
  case llvm::ARM::ArchKind::ARMV8_5A:
936
29
  case llvm::ARM::ArchKind::ARMV8_6A:
937
30
  case llvm::ARM::ArchKind::ARMV8_8A:
938
31
  case llvm::ARM::ArchKind::ARMV9A:
939
32
  case llvm::ARM::ArchKind::ARMV9_1A:
940
33
  case llvm::ARM::ArchKind::ARMV9_2A:
941
34
  case llvm::ARM::ArchKind::ARMV9_3A:
942
34
    getTargetDefinesARMV83A(Opts, Builder);
943
34
    break;
944
1.28k
  }
945
1.28k
}
946
947
const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
948
#define BUILTIN(ID, TYPE, ATTRS)                                               \
949
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
950
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
951
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
952
#include "clang/Basic/BuiltinsNEON.def"
953
954
#define BUILTIN(ID, TYPE, ATTRS)                                               \
955
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
956
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
957
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
958
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
959
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
960
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
961
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
962
#include "clang/Basic/BuiltinsARM.def"
963
};
964
965
1.28k
ArrayRef<Builtin::Info> ARMTargetInfo::getTargetBuiltins() const {
966
1.28k
  return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin -
967
1.28k
                                             Builtin::FirstTSBuiltin);
968
1.28k
}
969
970
17
bool ARMTargetInfo::isCLZForZeroUndef() const { return false; }
971
736
TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const {
972
736
  return IsAAPCS
973
736
             ? 
AAPCSABIBuiltinVaList560
974
736
             : 
(176
getTriple().isWatchABI()176
?
TargetInfo::CharPtrBuiltinVaList24
975
176
                                         : 
TargetInfo::VoidPtrBuiltinVaList152
);
976
736
}
977
978
const char *const ARMTargetInfo::GCCRegNames[] = {
979
    // Integer registers
980
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
981
    "r12", "sp", "lr", "pc",
982
983
    // Float registers
984
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
985
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
986
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
987
988
    // Double registers
989
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
990
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
991
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
992
993
    // Quad registers
994
    "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11",
995
    "q12", "q13", "q14", "q15"};
996
997
352
ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
998
352
  return llvm::makeArrayRef(GCCRegNames);
999
352
}
1000
1001
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
1002
    {{"a1"}, "r0"},  {{"a2"}, "r1"},        {{"a3"}, "r2"},  {{"a4"}, "r3"},
1003
    {{"v1"}, "r4"},  {{"v2"}, "r5"},        {{"v3"}, "r6"},  {{"v4"}, "r7"},
1004
    {{"v5"}, "r8"},  {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"},
1005
    {{"ip"}, "r12"}, {{"r13"}, "sp"},       {{"r14"}, "lr"}, {{"r15"}, "pc"},
1006
    // The S, D and Q registers overlap, but aren't really aliases; we
1007
    // don't want to substitute one of these for a different-sized one.
1008
};
1009
1010
179
ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
1011
179
  return llvm::makeArrayRef(GCCRegAliases);
1012
179
}
1013
1014
bool ARMTargetInfo::validateAsmConstraint(
1015
187
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1016
187
  switch (*Name) {
1017
1
  default:
1018
1
    break;
1019
9
  case 'l': // r0-r7 if thumb, r0-r15 if ARM
1020
9
    Info.setAllowsRegister();
1021
9
    return true;
1022
6
  case 'h': // r8-r15, thumb only
1023
6
    if (isThumb()) {
1024
4
      Info.setAllowsRegister();
1025
4
      return true;
1026
4
    }
1027
2
    break;
1028
4
  case 's': // An integer constant, but allowing only relocatable values.
1029
4
    return true;
1030
17
  case 't': // s0-s31, d0-d31, or q0-q15
1031
38
  case 'w': // s0-s15, d0-d7, or q0-q3
1032
47
  case 'x': // s0-s31, d0-d15, or q0-q7
1033
47
    if (FPRegsDisabled)
1034
3
      return false;
1035
44
    Info.setAllowsRegister();
1036
44
    return true;
1037
16
  case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)
1038
    // only available in ARMv6T2 and above
1039
16
    if (CPUAttr.equals("6T2") || ArchVersion >= 7) {
1040
8
      Info.setRequiresImmediate(0, 65535);
1041
8
      return true;
1042
8
    }
1043
8
    break;
1044
16
  case 'I':
1045
16
    if (isThumb()) {
1046
8
      if (!supportsThumb2())
1047
4
        Info.setRequiresImmediate(0, 255);
1048
4
      else
1049
        // FIXME: should check if immediate value would be valid for a Thumb2
1050
        // data-processing instruction
1051
4
        Info.setRequiresImmediate();
1052
8
    } else
1053
      // FIXME: should check if immediate value would be valid for an ARM
1054
      // data-processing instruction
1055
8
      Info.setRequiresImmediate();
1056
16
    return true;
1057
32
  case 'J':
1058
32
    if (isThumb() && 
!supportsThumb2()16
)
1059
8
      Info.setRequiresImmediate(-255, -1);
1060
24
    else
1061
24
      Info.setRequiresImmediate(-4095, 4095);
1062
32
    return true;
1063
4
  case 'K':
1064
4
    if (isThumb()) {
1065
2
      if (!supportsThumb2())
1066
        // FIXME: should check if immediate value can be obtained from shifting
1067
        // a value between 0 and 255 left by any amount
1068
1
        Info.setRequiresImmediate();
1069
1
      else
1070
        // FIXME: should check if immediate value would be valid for a Thumb2
1071
        // data-processing instruction when inverted
1072
1
        Info.setRequiresImmediate();
1073
2
    } else
1074
      // FIXME: should check if immediate value would be valid for an ARM
1075
      // data-processing instruction when inverted
1076
2
      Info.setRequiresImmediate();
1077
4
    return true;
1078
16
  case 'L':
1079
16
    if (isThumb()) {
1080
8
      if (!supportsThumb2())
1081
4
        Info.setRequiresImmediate(-7, 7);
1082
4
      else
1083
        // FIXME: should check if immediate value would be valid for a Thumb2
1084
        // data-processing instruction when negated
1085
4
        Info.setRequiresImmediate();
1086
8
    } else
1087
      // FIXME: should check if immediate value  would be valid for an ARM
1088
      // data-processing instruction when negated
1089
8
      Info.setRequiresImmediate();
1090
16
    return true;
1091
4
  case 'M':
1092
4
    if (isThumb() && 
!supportsThumb2()2
)
1093
      // FIXME: should check if immediate value is a multiple of 4 between 0 and
1094
      // 1020
1095
1
      Info.setRequiresImmediate();
1096
3
    else
1097
      // FIXME: should check if immediate value is a power of two or a integer
1098
      // between 0 and 32
1099
3
      Info.setRequiresImmediate();
1100
4
    return true;
1101
16
  case 'N':
1102
    // Thumb1 only
1103
16
    if (isThumb() && 
!supportsThumb2()8
) {
1104
4
      Info.setRequiresImmediate(0, 31);
1105
4
      return true;
1106
4
    }
1107
12
    break;
1108
12
  case 'O':
1109
    // Thumb1 only
1110
4
    if (isThumb() && 
!supportsThumb2()2
) {
1111
      // FIXME: should check if immediate value is a multiple of 4 between -508
1112
      // and 508
1113
1
      Info.setRequiresImmediate();
1114
1
      return true;
1115
1
    }
1116
3
    break;
1117
4
  case 'Q': // A memory address that is a single base register.
1118
4
    Info.setAllowsMemory();
1119
4
    return true;
1120
6
  case 'T':
1121
6
    switch (Name[1]) {
1122
0
    default:
1123
0
      break;
1124
4
    case 'e': // Even general-purpose register
1125
6
    case 'o': // Odd general-purpose register
1126
6
      Info.setAllowsRegister();
1127
6
      Name++;
1128
6
      return true;
1129
6
    }
1130
0
    break;
1131
2
  case 'U': // a memory reference...
1132
2
    switch (Name[1]) {
1133
0
    case 'q': // ...ARMV4 ldrsb
1134
2
    case 'v': // ...VFP load/store (reg+constant offset)
1135
2
    case 'y': // ...iWMMXt load/store
1136
2
    case 't': // address valid for load/store opaque types wider
1137
              // than 128-bits
1138
2
    case 'n': // valid address for Neon doubleword vector load/store
1139
2
    case 'm': // valid address for Neon element and structure load/store
1140
2
    case 's': // valid address for non-offset loads/stores of quad-word
1141
              // values in four ARM registers
1142
2
      Info.setAllowsMemory();
1143
2
      Name++;
1144
2
      return true;
1145
2
    }
1146
0
    break;
1147
187
  }
1148
26
  return false;
1149
187
}
1150
1151
306
std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
1152
306
  std::string R;
1153
306
  switch (*Constraint) {
1154
1
  case 'U': // Two-character constraint; add "^" hint for later parsing.
1155
4
  case 'T':
1156
4
    R = std::string("^") + std::string(Constraint, 2);
1157
4
    Constraint++;
1158
4
    break;
1159
5
  case 'p': // 'p' should be translated to 'r' by default.
1160
5
    R = std::string("r");
1161
5
    break;
1162
297
  default:
1163
297
    return std::string(1, *Constraint);
1164
306
  }
1165
9
  return R;
1166
306
}
1167
1168
bool ARMTargetInfo::validateConstraintModifier(
1169
    StringRef Constraint, char Modifier, unsigned Size,
1170
396
    std::string &SuggestedModifier) const {
1171
396
  bool isOutput = (Constraint[0] == '=');
1172
396
  bool isInOut = (Constraint[0] == '+');
1173
1174
  // Strip off constraint modifiers.
1175
601
  while (Constraint[0] == '=' || 
Constraint[0] == '+'403
||
Constraint[0] == '&'398
)
1176
205
    Constraint = Constraint.substr(1);
1177
1178
396
  switch (Constraint[0]) {
1179
161
  default:
1180
161
    break;
1181
235
  case 'r': {
1182
235
    switch (Modifier) {
1183
227
    default:
1184
227
      return (isInOut || 
isOutput225
||
Size <= 6466
);
1185
8
    case 'q':
1186
      // A register of size 32 cannot fit a vector type.
1187
8
      return false;
1188
235
    }
1189
235
  }
1190
396
  }
1191
1192
161
  return true;
1193
396
}
1194
118
const char *ARMTargetInfo::getClobbers() const {
1195
  // FIXME: Is this really right?
1196
118
  return "";
1197
118
}
1198
1199
TargetInfo::CallingConvCheckResult
1200
700
ARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1201
700
  switch (CC) {
1202
14
  case CC_AAPCS:
1203
25
  case CC_AAPCS_VFP:
1204
485
  case CC_Swift:
1205
700
  case CC_SwiftAsync:
1206
700
  case CC_OpenCLKernel:
1207
700
    return CCCR_OK;
1208
0
  default:
1209
0
    return CCCR_Warning;
1210
700
  }
1211
700
}
1212
1213
4
int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
1214
4
  if (RegNo == 0)
1215
2
    return 0;
1216
2
  if (RegNo == 1)
1217
2
    return 1;
1218
0
  return -1;
1219
2
}
1220
1221
0
bool ARMTargetInfo::hasSjLjLowering() const { return true; }
1222
1223
ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple,
1224
                                 const TargetOptions &Opts)
1225
1.26k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1225
631
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1225
633
    : ARMTargetInfo(Triple, Opts) {}
1226
1227
void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1228
1.24k
                                       MacroBuilder &Builder) const {
1229
1.24k
  Builder.defineMacro("__ARMEL__");
1230
1.24k
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1231
1.24k
}
1232
1233
ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple,
1234
                                 const TargetOptions &Opts)
1235
39
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1235
11
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1235
28
    : ARMTargetInfo(Triple, Opts) {}
1236
1237
void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts,
1238
39
                                       MacroBuilder &Builder) const {
1239
39
  Builder.defineMacro("__ARMEB__");
1240
39
  Builder.defineMacro("__ARM_BIG_ENDIAN");
1241
39
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1242
39
}
1243
1244
WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
1245
                                           const TargetOptions &Opts)
1246
115
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1247
115
}
clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1246
115
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1247
115
}
Unexecuted instantiation: clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1248
1249
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
1250
102
                                                  MacroBuilder &Builder) const {
1251
  // FIXME: this is invalid for WindowsCE
1252
102
  Builder.defineMacro("_M_ARM_NT", "1");
1253
102
  Builder.defineMacro("_M_ARMT", "_M_ARM");
1254
102
  Builder.defineMacro("_M_THUMB", "_M_ARM");
1255
1256
102
  assert((Triple.getArch() == llvm::Triple::arm ||
1257
102
          Triple.getArch() == llvm::Triple::thumb) &&
1258
102
         "invalid architecture for Windows ARM target info");
1259
102
  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 
48
:
694
;
1260
102
  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
1261
1262
  // TODO map the complete set of values
1263
  // 31: VFPv3 40: VFPv4
1264
102
  Builder.defineMacro("_M_ARM_FP", "31");
1265
102
}
1266
1267
TargetInfo::BuiltinVaListKind
1268
105
WindowsARMTargetInfo::getBuiltinVaListKind() const {
1269
105
  return TargetInfo::CharPtrBuiltinVaList;
1270
105
}
1271
1272
TargetInfo::CallingConvCheckResult
1273
33
WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1274
33
  switch (CC) {
1275
1
  case CC_X86StdCall:
1276
1
  case CC_X86ThisCall:
1277
1
  case CC_X86FastCall:
1278
1
  case CC_X86VectorCall:
1279
1
    return CCCR_Ignore;
1280
21
  case CC_C:
1281
21
  case CC_OpenCLKernel:
1282
26
  case CC_PreserveMost:
1283
31
  case CC_PreserveAll:
1284
32
  case CC_Swift:
1285
32
  case CC_SwiftAsync:
1286
32
    return CCCR_OK;
1287
0
  default:
1288
0
    return CCCR_Warning;
1289
33
  }
1290
33
}
1291
1292
// Windows ARM + Itanium C++ ABI Target
1293
ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(
1294
    const llvm::Triple &Triple, const TargetOptions &Opts)
1295
10
    : WindowsARMTargetInfo(Triple, Opts) {
1296
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1297
10
}
Unexecuted instantiation: clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1295
10
    : WindowsARMTargetInfo(Triple, Opts) {
1296
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1297
10
}
1298
1299
void ItaniumWindowsARMleTargetInfo::getTargetDefines(
1300
10
    const LangOptions &Opts, MacroBuilder &Builder) const {
1301
10
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1302
1303
10
  if (Opts.MSVCCompat)
1304
1
    WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1305
10
}
1306
1307
// Windows ARM, MS (C++) ABI
1308
MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
1309
                                                   const TargetOptions &Opts)
1310
101
    : WindowsARMTargetInfo(Triple, Opts) {
1311
101
  TheCXXABI.set(TargetCXXABI::Microsoft);
1312
101
}
Unexecuted instantiation: clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1310
101
    : WindowsARMTargetInfo(Triple, Opts) {
1311
101
  TheCXXABI.set(TargetCXXABI::Microsoft);
1312
101
}
1313
1314
void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1315
101
                                                MacroBuilder &Builder) const {
1316
101
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1317
101
  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1318
101
}
1319
1320
MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple,
1321
                                       const TargetOptions &Opts)
1322
4
    : WindowsARMTargetInfo(Triple, Opts) {
1323
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1324
4
}
Unexecuted instantiation: clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1322
4
    : WindowsARMTargetInfo(Triple, Opts) {
1323
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1324
4
}
1325
1326
void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1327
4
                                          MacroBuilder &Builder) const {
1328
4
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1329
4
  Builder.defineMacro("_ARM_");
1330
4
}
1331
1332
CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
1333
                                         const TargetOptions &Opts)
1334
1
    : ARMleTargetInfo(Triple, Opts) {
1335
1
  this->WCharType = TargetInfo::UnsignedShort;
1336
1
  TLSSupported = false;
1337
1
  DoubleAlign = LongLongAlign = 64;
1338
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1339
1
}
Unexecuted instantiation: clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1334
1
    : ARMleTargetInfo(Triple, Opts) {
1335
1
  this->WCharType = TargetInfo::UnsignedShort;
1336
1
  TLSSupported = false;
1337
1
  DoubleAlign = LongLongAlign = 64;
1338
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1339
1
}
1340
1341
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1342
1
                                           MacroBuilder &Builder) const {
1343
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1344
1
  Builder.defineMacro("_ARM_");
1345
1
  Builder.defineMacro("__CYGWIN__");
1346
1
  Builder.defineMacro("__CYGWIN32__");
1347
1
  DefineStd(Builder, "unix", Opts);
1348
1
  if (Opts.CPlusPlus)
1349
0
    Builder.defineMacro("_GNU_SOURCE");
1350
1
}
1351
1352
DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
1353
                                         const TargetOptions &Opts)
1354
213
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1355
213
  HasAlignMac68kSupport = true;
1356
  // iOS always has 64-bit atomic instructions.
1357
  // FIXME: This should be based off of the target features in
1358
  // ARMleTargetInfo.
1359
213
  MaxAtomicInlineWidth = 64;
1360
1361
213
  if (Triple.isWatchABI()) {
1362
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1363
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1364
1365
    // BOOL should be a real boolean on the new ABI
1366
29
    UseSignedCharForObjCBool = false;
1367
29
  } else
1368
184
    TheCXXABI.set(TargetCXXABI::iOS);
1369
213
}
Unexecuted instantiation: clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1354
213
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1355
213
  HasAlignMac68kSupport = true;
1356
  // iOS always has 64-bit atomic instructions.
1357
  // FIXME: This should be based off of the target features in
1358
  // ARMleTargetInfo.
1359
213
  MaxAtomicInlineWidth = 64;
1360
1361
213
  if (Triple.isWatchABI()) {
1362
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1363
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1364
1365
    // BOOL should be a real boolean on the new ABI
1366
29
    UseSignedCharForObjCBool = false;
1367
29
  } else
1368
184
    TheCXXABI.set(TargetCXXABI::iOS);
1369
213
}
1370
1371
void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts,
1372
                                       const llvm::Triple &Triple,
1373
202
                                       MacroBuilder &Builder) const {
1374
202
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1375
202
}
1376
1377
RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple,
1378
                                                   const TargetOptions &Opts)
1379
    : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
1380
                                   Triple.getOSName(),
1381
                                   Triple.getEnvironmentName()),
1382
1
                      Opts) {
1383
1
  IsRenderScriptTarget = true;
1384
1
  LongWidth = LongAlign = 64;
1385
1
}
clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1382
1
                      Opts) {
1383
1
  IsRenderScriptTarget = true;
1384
1
  LongWidth = LongAlign = 64;
1385
1
}
Unexecuted instantiation: clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1386
1387
void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts,
1388
1
                                                MacroBuilder &Builder) const {
1389
1
  Builder.defineMacro("__RENDERSCRIPT__");
1390
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1391
1
}