Coverage Report

Created: 2021-08-24 07:12

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements ARM TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARM.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
21
using namespace clang;
22
using namespace clang::targets;
23
24
1.47k
void ARMTargetInfo::setABIAAPCS() {
25
1.47k
  IsAAPCS = true;
26
27
1.47k
  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
28
1.47k
  BFloat16Width = BFloat16Align = 16;
29
1.47k
  BFloat16Format = &llvm::APFloat::BFloat();
30
31
1.47k
  const llvm::Triple &T = getTriple();
32
33
1.47k
  bool IsNetBSD = T.isOSNetBSD();
34
1.47k
  bool IsOpenBSD = T.isOSOpenBSD();
35
1.47k
  if (!T.isOSWindows() && 
!IsNetBSD1.37k
&&
!IsOpenBSD1.36k
)
36
1.36k
    WCharType = UnsignedInt;
37
38
1.47k
  UseBitFieldTypeAlignment = true;
39
40
1.47k
  ZeroLengthBitfieldBoundary = 0;
41
42
  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
43
  // so set preferred for small types to 32.
44
1.47k
  if (T.isOSBinFormatMachO()) {
45
32
    resetDataLayout(BigEndian
46
32
                        ? 
"E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"0
47
32
                        : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
48
32
                    "_");
49
1.44k
  } else if (T.isOSWindows()) {
50
98
    assert(!BigEndian && "Windows on ARM does not support big endian");
51
0
    resetDataLayout("e"
52
98
                    "-m:w"
53
98
                    "-p:32:32"
54
98
                    "-Fi8"
55
98
                    "-i64:64"
56
98
                    "-v128:64:128"
57
98
                    "-a:0:32"
58
98
                    "-n32"
59
98
                    "-S64");
60
1.34k
  } else if (T.isOSNaCl()) {
61
2
    assert(!BigEndian && "NaCl on ARM does not support big endian");
62
0
    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
63
1.34k
  } else {
64
1.34k
    resetDataLayout(BigEndian
65
1.34k
                        ? 
"E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"41
66
1.34k
                        : 
"e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"1.30k
);
67
1.34k
  }
68
69
  // FIXME: Enumerated types are variable width in straight AAPCS.
70
1.47k
}
71
72
281
void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
73
281
  const llvm::Triple &T = getTriple();
74
75
281
  IsAAPCS = false;
76
77
281
  if (IsAAPCS16)
78
37
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
79
244
  else
80
244
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
81
281
  BFloat16Width = BFloat16Align = 16;
82
281
  BFloat16Format = &llvm::APFloat::BFloat();
83
84
281
  WCharType = SignedInt;
85
86
  // Do not respect the alignment of bit-field types when laying out
87
  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
88
281
  UseBitFieldTypeAlignment = false;
89
90
  /// gcc forces the alignment to 4 bytes, regardless of the type of the
91
  /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
92
  /// gcc.
93
281
  ZeroLengthBitfieldBoundary = 32;
94
95
281
  if (T.isOSBinFormatMachO() && 
IsAAPCS16234
) {
96
37
    assert(!BigEndian && "AAPCS16 does not support big-endian");
97
0
    resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_");
98
244
  } else if (T.isOSBinFormatMachO())
99
197
    resetDataLayout(
100
197
        BigEndian
101
197
            ? 
"E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
102
197
            : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32",
103
197
        "_");
104
47
  else
105
47
    resetDataLayout(
106
47
        BigEndian
107
47
            ? 
"E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
108
47
            : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
109
110
  // FIXME: Override "preferred align" for double and long long.
111
281
}
112
113
1.25k
void ARMTargetInfo::setArchInfo() {
114
1.25k
  StringRef ArchName = getTriple().getArchName();
115
116
1.25k
  ArchISA = llvm::ARM::parseArchISA(ArchName);
117
1.25k
  CPU = std::string(llvm::ARM::getDefaultCPU(ArchName));
118
1.25k
  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName);
119
1.25k
  if (AK != llvm::ARM::ArchKind::INVALID)
120
1.11k
    ArchKind = AK;
121
1.25k
  setArchInfo(ArchKind);
122
1.25k
}
123
124
1.61k
void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
125
1.61k
  StringRef SubArch;
126
127
  // cache TargetParser info
128
1.61k
  ArchKind = Kind;
129
1.61k
  SubArch = llvm::ARM::getSubArch(ArchKind);
130
1.61k
  ArchProfile = llvm::ARM::parseArchProfile(SubArch);
131
1.61k
  ArchVersion = llvm::ARM::parseArchVersion(SubArch);
132
133
  // cache CPU related strings
134
1.61k
  CPUAttr = getCPUAttr();
135
1.61k
  CPUProfile = getCPUProfile();
136
1.61k
}
137
138
1.76k
void ARMTargetInfo::setAtomic() {
139
  // when triple does not specify a sub arch,
140
  // then we are not using inline atomics
141
1.76k
  bool ShouldUseInlineAtomic =
142
1.76k
      (ArchISA == llvm::ARM::ISAKind::ARM && 
ArchVersion >= 6966
) ||
143
1.76k
      
(1.04k
ArchISA == llvm::ARM::ISAKind::THUMB1.04k
&&
ArchVersion >= 7803
);
144
  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
145
1.76k
  if (ArchProfile == llvm::ARM::ProfileKind::M) {
146
368
    MaxAtomicPromoteWidth = 32;
147
368
    if (ShouldUseInlineAtomic)
148
340
      MaxAtomicInlineWidth = 32;
149
1.40k
  } else {
150
1.40k
    MaxAtomicPromoteWidth = 64;
151
1.40k
    if (ShouldUseInlineAtomic)
152
1.13k
      MaxAtomicInlineWidth = 64;
153
1.40k
  }
154
1.76k
}
155
156
6.28k
bool ARMTargetInfo::hasMVE() const {
157
6.28k
  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && 
MVE != 03.49k
;
158
6.28k
}
159
160
164
bool ARMTargetInfo::hasMVEFloat() const {
161
164
  return hasMVE() && (MVE & MVE_FP);
162
164
}
163
164
1.23k
bool ARMTargetInfo::hasCDE() const { return getARMCDECoprocMask() != 0; }
165
166
7.98k
bool ARMTargetInfo::isThumb() const {
167
7.98k
  return ArchISA == llvm::ARM::ISAKind::THUMB;
168
7.98k
}
169
170
269
bool ARMTargetInfo::supportsThumb() const {
171
269
  return CPUAttr.count('T') || 
ArchVersion >= 690
;
172
269
}
173
174
1.85k
bool ARMTargetInfo::supportsThumb2() const {
175
1.85k
  return CPUAttr.equals("6T2") ||
176
1.85k
         
(1.85k
ArchVersion >= 71.85k
&&
!CPUAttr.equals("8M_BASE")1.55k
);
177
1.85k
}
178
179
1.61k
StringRef ARMTargetInfo::getCPUAttr() const {
180
  // For most sub-arches, the build attribute CPU name is enough.
181
  // For Cortex variants, it's slightly different.
182
1.61k
  switch (ArchKind) {
183
351
  default:
184
351
    return llvm::ARM::getCPUAttr(ArchKind);
185
29
  case llvm::ARM::ArchKind::ARMV6M:
186
29
    return "6M";
187
26
  case llvm::ARM::ArchKind::ARMV7S:
188
26
    return "7S";
189
580
  case llvm::ARM::ArchKind::ARMV7A:
190
580
    return "7A";
191
57
  case llvm::ARM::ArchKind::ARMV7R:
192
57
    return "7R";
193
41
  case llvm::ARM::ArchKind::ARMV7M:
194
41
    return "7M";
195
31
  case llvm::ARM::ArchKind::ARMV7EM:
196
31
    return "7EM";
197
7
  case llvm::ARM::ArchKind::ARMV7VE:
198
7
    return "7VE";
199
172
  case llvm::ARM::ArchKind::ARMV8A:
200
172
    return "8A";
201
4
  case llvm::ARM::ArchKind::ARMV8_1A:
202
4
    return "8_1A";
203
32
  case llvm::ARM::ArchKind::ARMV8_2A:
204
32
    return "8_2A";
205
2
  case llvm::ARM::ArchKind::ARMV8_3A:
206
2
    return "8_3A";
207
16
  case llvm::ARM::ArchKind::ARMV8_4A:
208
16
    return "8_4A";
209
1
  case llvm::ARM::ArchKind::ARMV8_5A:
210
1
    return "8_5A";
211
10
  case llvm::ARM::ArchKind::ARMV8_6A:
212
10
    return "8_6A";
213
1
  case llvm::ARM::ArchKind::ARMV8_7A:
214
1
    return "8_7A";
215
32
  case llvm::ARM::ArchKind::ARMV8MBaseline:
216
32
    return "8M_BASE";
217
39
  case llvm::ARM::ArchKind::ARMV8MMainline:
218
39
    return "8M_MAIN";
219
10
  case llvm::ARM::ArchKind::ARMV8R:
220
10
    return "8R";
221
175
  case llvm::ARM::ArchKind::ARMV8_1MMainline:
222
175
    return "8_1M_MAIN";
223
1.61k
  }
224
1.61k
}
225
226
1.61k
StringRef ARMTargetInfo::getCPUProfile() const {
227
1.61k
  switch (ArchProfile) {
228
854
  case llvm::ARM::ProfileKind::A:
229
854
    return "A";
230
67
  case llvm::ARM::ProfileKind::R:
231
67
    return "R";
232
347
  case llvm::ARM::ProfileKind::M:
233
347
    return "M";
234
348
  default:
235
348
    return "";
236
1.61k
  }
237
1.61k
}
238
239
ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
240
                             const TargetOptions &Opts)
241
    : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
242
1.25k
      HW_FP(0) {
243
1.25k
  bool IsOpenBSD = Triple.isOSOpenBSD();
244
1.25k
  bool IsNetBSD = Triple.isOSNetBSD();
245
246
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
247
  // environment where size_t is `unsigned long` rather than `unsigned int`
248
249
1.25k
  PtrDiffType = IntPtrType =
250
1.25k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
||
IsOpenBSD1.04k
||
251
1.25k
       
IsNetBSD1.03k
)
252
1.25k
          ? 
SignedLong225
253
1.25k
          : 
SignedInt1.03k
;
254
255
1.25k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
||
IsOpenBSD1.04k
||
256
1.25k
              
IsNetBSD1.03k
)
257
1.25k
                 ? 
UnsignedLong225
258
1.25k
                 : 
UnsignedInt1.03k
;
259
260
  // ptrdiff_t is inconsistent on Darwin
261
1.25k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
) &&
262
1.25k
      
!Triple.isWatchABI()213
)
263
184
    PtrDiffType = SignedInt;
264
265
  // Cache arch related info.
266
1.25k
  setArchInfo();
267
268
  // {} in inline assembly are neon specifiers, not assembly variant
269
  // specifiers.
270
1.25k
  NoAsmVariants = true;
271
272
  // FIXME: This duplicates code from the driver that sets the -target-abi
273
  // option - this code is used if -target-abi isn't passed and should
274
  // be unified in some way.
275
1.25k
  if (Triple.isOSBinFormatMachO()) {
276
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
277
    // the frontend matches that.
278
213
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
279
213
        
Triple.getOS() == llvm::Triple::UnknownOS212
||
280
213
        
ArchProfile == llvm::ARM::ProfileKind::M197
) {
281
16
      setABI("aapcs");
282
197
    } else if (Triple.isWatchABI()) {
283
29
      setABI("aapcs16");
284
168
    } else {
285
168
      setABI("apcs-gnu");
286
168
    }
287
1.04k
  } else if (Triple.isOSWindows()) {
288
    // FIXME: this is invalid for WindowsCE
289
96
    setABI("aapcs");
290
946
  } else {
291
    // Select the default based on the platform.
292
946
    switch (Triple.getEnvironment()) {
293
13
    case llvm::Triple::Android:
294
160
    case llvm::Triple::GNUEABI:
295
222
    case llvm::Triple::GNUEABIHF:
296
226
    case llvm::Triple::MuslEABI:
297
228
    case llvm::Triple::MuslEABIHF:
298
228
      setABI("aapcs-linux");
299
228
      break;
300
16
    case llvm::Triple::EABIHF:
301
481
    case llvm::Triple::EABI:
302
481
      setABI("aapcs");
303
481
      break;
304
31
    case llvm::Triple::GNU:
305
31
      setABI("apcs-gnu");
306
31
      break;
307
206
    default:
308
206
      if (IsNetBSD)
309
0
        setABI("apcs-gnu");
310
206
      else if (IsOpenBSD)
311
2
        setABI("aapcs-linux");
312
204
      else
313
204
        setABI("aapcs");
314
206
      break;
315
946
    }
316
946
  }
317
318
  // ARM targets default to using the ARM C++ ABI.
319
1.25k
  TheCXXABI.set(TargetCXXABI::GenericARM);
320
321
  // ARM has atomics up to 8 bytes
322
1.25k
  setAtomic();
323
324
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
325
  // as well the default alignment
326
1.25k
  if (IsAAPCS && 
!Triple.isAndroid()1.02k
)
327
1.01k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
328
329
  // Do force alignment of members that follow zero length bitfields.  If
330
  // the alignment of the zero-length bitfield is greater than the member
331
  // that follows it, `bar', `bar' will be aligned as the  type of the
332
  // zero length bitfield.
333
1.25k
  UseZeroLengthBitfieldAlignment = true;
334
335
1.25k
  if (Triple.getOS() == llvm::Triple::Linux ||
336
1.25k
      
Triple.getOS() == llvm::Triple::UnknownOS970
)
337
936
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
338
936
                           ? 
"llvm.arm.gnu.eabi.mcount"9
339
936
                           : 
"\01mcount"927
;
340
341
1.25k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
342
1.25k
}
clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
242
1.25k
      HW_FP(0) {
243
1.25k
  bool IsOpenBSD = Triple.isOSOpenBSD();
244
1.25k
  bool IsNetBSD = Triple.isOSNetBSD();
245
246
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
247
  // environment where size_t is `unsigned long` rather than `unsigned int`
248
249
1.25k
  PtrDiffType = IntPtrType =
250
1.25k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
||
IsOpenBSD1.04k
||
251
1.25k
       
IsNetBSD1.03k
)
252
1.25k
          ? 
SignedLong225
253
1.25k
          : 
SignedInt1.03k
;
254
255
1.25k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
||
IsOpenBSD1.04k
||
256
1.25k
              
IsNetBSD1.03k
)
257
1.25k
                 ? 
UnsignedLong225
258
1.25k
                 : 
UnsignedInt1.03k
;
259
260
  // ptrdiff_t is inconsistent on Darwin
261
1.25k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.05k
) &&
262
1.25k
      
!Triple.isWatchABI()213
)
263
184
    PtrDiffType = SignedInt;
264
265
  // Cache arch related info.
266
1.25k
  setArchInfo();
267
268
  // {} in inline assembly are neon specifiers, not assembly variant
269
  // specifiers.
270
1.25k
  NoAsmVariants = true;
271
272
  // FIXME: This duplicates code from the driver that sets the -target-abi
273
  // option - this code is used if -target-abi isn't passed and should
274
  // be unified in some way.
275
1.25k
  if (Triple.isOSBinFormatMachO()) {
276
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
277
    // the frontend matches that.
278
213
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
279
213
        
Triple.getOS() == llvm::Triple::UnknownOS212
||
280
213
        
ArchProfile == llvm::ARM::ProfileKind::M197
) {
281
16
      setABI("aapcs");
282
197
    } else if (Triple.isWatchABI()) {
283
29
      setABI("aapcs16");
284
168
    } else {
285
168
      setABI("apcs-gnu");
286
168
    }
287
1.04k
  } else if (Triple.isOSWindows()) {
288
    // FIXME: this is invalid for WindowsCE
289
96
    setABI("aapcs");
290
946
  } else {
291
    // Select the default based on the platform.
292
946
    switch (Triple.getEnvironment()) {
293
13
    case llvm::Triple::Android:
294
160
    case llvm::Triple::GNUEABI:
295
222
    case llvm::Triple::GNUEABIHF:
296
226
    case llvm::Triple::MuslEABI:
297
228
    case llvm::Triple::MuslEABIHF:
298
228
      setABI("aapcs-linux");
299
228
      break;
300
16
    case llvm::Triple::EABIHF:
301
481
    case llvm::Triple::EABI:
302
481
      setABI("aapcs");
303
481
      break;
304
31
    case llvm::Triple::GNU:
305
31
      setABI("apcs-gnu");
306
31
      break;
307
206
    default:
308
206
      if (IsNetBSD)
309
0
        setABI("apcs-gnu");
310
206
      else if (IsOpenBSD)
311
2
        setABI("aapcs-linux");
312
204
      else
313
204
        setABI("aapcs");
314
206
      break;
315
946
    }
316
946
  }
317
318
  // ARM targets default to using the ARM C++ ABI.
319
1.25k
  TheCXXABI.set(TargetCXXABI::GenericARM);
320
321
  // ARM has atomics up to 8 bytes
322
1.25k
  setAtomic();
323
324
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
325
  // as well the default alignment
326
1.25k
  if (IsAAPCS && 
!Triple.isAndroid()1.02k
)
327
1.01k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
328
329
  // Do force alignment of members that follow zero length bitfields.  If
330
  // the alignment of the zero-length bitfield is greater than the member
331
  // that follows it, `bar', `bar' will be aligned as the  type of the
332
  // zero length bitfield.
333
1.25k
  UseZeroLengthBitfieldAlignment = true;
334
335
1.25k
  if (Triple.getOS() == llvm::Triple::Linux ||
336
1.25k
      
Triple.getOS() == llvm::Triple::UnknownOS970
)
337
936
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
338
936
                           ? 
"llvm.arm.gnu.eabi.mcount"9
339
936
                           : 
"\01mcount"927
;
340
341
1.25k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
342
1.25k
}
Unexecuted instantiation: clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
343
344
2.69k
StringRef ARMTargetInfo::getABI() const { return ABI; }
345
346
1.75k
bool ARMTargetInfo::setABI(const std::string &Name) {
347
1.75k
  ABI = Name;
348
349
  // The defaults (above) are for AAPCS, check if we need to change them.
350
  //
351
  // FIXME: We need support for -meabi... we could just mangle it into the
352
  // name.
353
1.75k
  if (Name == "apcs-gnu" || 
Name == "aapcs16"1.51k
) {
354
281
    setABIAPCS(Name == "aapcs16");
355
281
    return true;
356
281
  }
357
1.47k
  if (Name == "aapcs" || 
Name == "aapcs-vfp"324
||
Name == "aapcs-linux"323
) {
358
1.47k
    setABIAAPCS();
359
1.47k
    return true;
360
1.47k
  }
361
0
  return false;
362
1.47k
}
363
364
// FIXME: This should be based on Arch attributes, not CPU names.
365
bool ARMTargetInfo::initFeatureMap(
366
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
367
1.29k
    const std::vector<std::string> &FeaturesVec) const {
368
369
1.29k
  std::string ArchFeature;
370
1.29k
  std::vector<StringRef> TargetFeatures;
371
1.29k
  llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName());
372
373
  // Map the base architecture to an appropriate target feature, so we don't
374
  // rely on the target triple.
375
1.29k
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU);
376
1.29k
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
377
932
    CPUArch = Arch;
378
1.29k
  if (CPUArch != llvm::ARM::ArchKind::INVALID) {
379
1.14k
    ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str();
380
1.14k
    TargetFeatures.push_back(ArchFeature);
381
1.14k
  }
382
383
  // get default FPU features
384
1.29k
  unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
385
1.29k
  llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
386
387
  // get default Extension features
388
1.29k
  uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
389
1.29k
  llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
390
391
1.29k
  for (auto Feature : TargetFeatures)
392
24.9k
    if (Feature[0] == '+')
393
7.87k
      Features[Feature.drop_front(1)] = true;
394
395
  // Enable or disable thumb-mode explicitly per function to enable mixed
396
  // ARM and Thumb code generation.
397
1.29k
  if (isThumb())
398
606
    Features["thumb-mode"] = true;
399
685
  else
400
685
    Features["thumb-mode"] = false;
401
402
  // Convert user-provided arm and thumb GNU target attributes to
403
  // [-|+]thumb-mode target features respectively.
404
1.29k
  std::vector<std::string> UpdatedFeaturesVec;
405
14.7k
  for (const auto &Feature : FeaturesVec) {
406
    // Skip soft-float-abi; it's something we only use to initialize a bit of
407
    // class state, and is otherwise unrecognized.
408
14.7k
    if (Feature == "+soft-float-abi")
409
394
      continue;
410
411
14.3k
    StringRef FixedFeature;
412
14.3k
    if (Feature == "+arm")
413
8
      FixedFeature = "-thumb-mode";
414
14.3k
    else if (Feature == "+thumb")
415
8
      FixedFeature = "+thumb-mode";
416
14.3k
    else
417
14.3k
      FixedFeature = Feature;
418
14.3k
    UpdatedFeaturesVec.push_back(FixedFeature.str());
419
14.3k
  }
420
421
1.29k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
422
1.29k
}
423
424
425
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
426
1.25k
                                         DiagnosticsEngine &Diags) {
427
1.25k
  FPU = 0;
428
1.25k
  MVE = 0;
429
1.25k
  CRC = 0;
430
1.25k
  Crypto = 0;
431
1.25k
  SHA2 = 0;
432
1.25k
  AES = 0;
433
1.25k
  DSP = 0;
434
1.25k
  Unaligned = 1;
435
1.25k
  SoftFloat = false;
436
  // Note that SoftFloatABI is initialized in our constructor.
437
1.25k
  HWDiv = 0;
438
1.25k
  DotProd = 0;
439
1.25k
  HasMatMul = 0;
440
1.25k
  HasFloat16 = true;
441
1.25k
  ARMCDECoprocMask = 0;
442
1.25k
  HasBFloat16 = false;
443
444
  // This does not diagnose illegal cases like having both
445
  // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
446
18.2k
  for (const auto &Feature : Features) {
447
18.2k
    if (Feature == "+soft-float") {
448
124
      SoftFloat = true;
449
18.1k
    } else if (Feature == "+vfp2sp" || 
Feature == "+vfp2"17.8k
) {
450
623
      FPU |= VFP2FPU;
451
623
      HW_FP |= HW_FP_SP;
452
623
      if (Feature == "+vfp2")
453
298
          HW_FP |= HW_FP_DP;
454
17.5k
    } else if (Feature == "+vfp3sp" || 
Feature == "+vfp3d16sp"17.2k
||
455
17.5k
               
Feature == "+vfp3"16.9k
||
Feature == "+vfp3d16"16.7k
) {
456
1.10k
      FPU |= VFP3FPU;
457
1.10k
      HW_FP |= HW_FP_SP;
458
1.10k
      if (Feature == "+vfp3" || 
Feature == "+vfp3d16"849
)
459
537
          HW_FP |= HW_FP_DP;
460
16.4k
    } else if (Feature == "+vfp4sp" || 
Feature == "+vfp4d16sp"16.2k
||
461
16.4k
               
Feature == "+vfp4"16.0k
||
Feature == "+vfp4d16"15.8k
) {
462
738
      FPU |= VFP4FPU;
463
738
      HW_FP |= HW_FP_SP | HW_FP_HP;
464
738
      if (Feature == "+vfp4" || 
Feature == "+vfp4d16"567
)
465
357
          HW_FP |= HW_FP_DP;
466
15.6k
    } else if (Feature == "+fp-armv8sp" || 
Feature == "+fp-armv8d16sp"15.5k
||
467
15.6k
               
Feature == "+fp-armv8"15.4k
||
Feature == "+fp-armv8d16"15.3k
) {
468
462
      FPU |= FPARMV8;
469
462
      HW_FP |= HW_FP_SP | HW_FP_HP;
470
462
      if (Feature == "+fp-armv8" || 
Feature == "+fp-armv8d16"357
)
471
223
          HW_FP |= HW_FP_DP;
472
15.2k
    } else if (Feature == "+neon") {
473
281
      FPU |= NeonFPU;
474
281
      HW_FP |= HW_FP_SP;
475
14.9k
    } else if (Feature == "+hwdiv") {
476
326
      HWDiv |= HWDivThumb;
477
14.6k
    } else if (Feature == "+hwdiv-arm") {
478
240
      HWDiv |= HWDivARM;
479
14.3k
    } else if (Feature == "+crc") {
480
148
      CRC = 1;
481
14.2k
    } else if (Feature == "+crypto") {
482
19
      Crypto = 1;
483
14.2k
    } else if (Feature == "+sha2") {
484
94
      SHA2 = 1;
485
14.1k
    } else if (Feature == "+aes") {
486
94
      AES = 1;
487
14.0k
    } else if (Feature == "+dsp") {
488
408
      DSP = 1;
489
13.6k
    } else if (Feature == "+fp64") {
490
297
      HW_FP |= HW_FP_DP;
491
13.3k
    } else if (Feature == "+8msecext") {
492
6
      if (CPUProfile != "M" || ArchVersion != 8) {
493
1
        Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
494
1
        return false;
495
1
      }
496
13.3k
    } else if (Feature == "+strict-align") {
497
311
      Unaligned = 0;
498
13.0k
    } else if (Feature == "+fp16") {
499
234
      HW_FP |= HW_FP_HP;
500
12.7k
    } else if (Feature == "+fullfp16") {
501
32
      HasLegalHalfType = true;
502
12.7k
    } else if (Feature == "+dotprod") {
503
25
      DotProd = true;
504
12.7k
    } else if (Feature == "+mve") {
505
27
      MVE |= MVE_INT;
506
12.6k
    } else if (Feature == "+mve.fp") {
507
140
      HasLegalHalfType = true;
508
140
      FPU |= FPARMV8;
509
140
      MVE |= MVE_INT | MVE_FP;
510
140
      HW_FP |= HW_FP_SP | HW_FP_HP;
511
12.5k
    } else if (Feature == "+i8mm") {
512
4
      HasMatMul = 1;
513
12.5k
    } else if (Feature.size() == strlen("+cdecp0") && 
Feature >= "+cdecp0"2.75k
&&
514
12.5k
               
Feature <= "+cdecp7"2.66k
) {
515
26
      unsigned Coproc = Feature.back() - '0';
516
26
      ARMCDECoprocMask |= (1U << Coproc);
517
12.5k
    } else if (Feature == "+bf16") {
518
18
      HasBFloat16 = true;
519
18
    }
520
18.2k
  }
521
522
1.25k
  switch (ArchVersion) {
523
59
  case 6:
524
59
    if (ArchProfile == llvm::ARM::ProfileKind::M)
525
16
      LDREX = 0;
526
43
    else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
527
3
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
528
40
    else
529
40
      LDREX = LDREX_W;
530
59
    break;
531
581
  case 7:
532
581
    if (ArchProfile == llvm::ARM::ProfileKind::M)
533
40
      LDREX = LDREX_W | LDREX_H | LDREX_B;
534
541
    else
535
541
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
536
581
    break;
537
423
  case 8:
538
423
    LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
539
1.25k
  }
540
541
1.25k
  if (!(FPU & NeonFPU) && 
FPMath == FP_Neon971
) {
542
2
    Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
543
2
    return false;
544
2
  }
545
546
1.25k
  if (FPMath == FP_Neon)
547
1
    Features.push_back("+neonfp");
548
1.24k
  else if (FPMath == FP_VFP)
549
5
    Features.push_back("-neonfp");
550
551
1.25k
  return true;
552
1.25k
}
553
554
4.88k
bool ARMTargetInfo::hasFeature(StringRef Feature) const {
555
4.88k
  return llvm::StringSwitch<bool>(Feature)
556
4.88k
      .Case("arm", true)
557
4.88k
      .Case("aarch32", true)
558
4.88k
      .Case("softfloat", SoftFloat)
559
4.88k
      .Case("thumb", isThumb())
560
4.88k
      .Case("neon", (FPU & NeonFPU) && 
!SoftFloat1.63k
)
561
4.88k
      .Case("vfp", FPU && 
!SoftFloat4.44k
)
562
4.88k
      .Case("hwdiv", HWDiv & HWDivThumb)
563
4.88k
      .Case("hwdiv-arm", HWDiv & HWDivARM)
564
4.88k
      .Case("mve", hasMVE())
565
4.88k
      .Default(false);
566
4.88k
}
567
568
1.77k
bool ARMTargetInfo::hasBFloat16Type() const {
569
1.77k
  return HasBFloat16 && 
!SoftFloat189
;
570
1.77k
}
571
572
0
bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
573
0
  return Name == "generic" ||
574
0
         llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
575
0
}
576
577
2
void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
578
2
  llvm::ARM::fillValidCPUArchList(Values);
579
2
}
580
581
516
bool ARMTargetInfo::setCPU(const std::string &Name) {
582
516
  if (Name != "generic")
583
361
    setArchInfo(llvm::ARM::parseCPUArch(Name));
584
585
516
  if (ArchKind == llvm::ARM::ArchKind::INVALID)
586
2
    return false;
587
514
  setAtomic();
588
514
  CPU = Name;
589
514
  return true;
590
516
}
591
592
8
bool ARMTargetInfo::setFPMath(StringRef Name) {
593
8
  if (Name == "neon") {
594
3
    FPMath = FP_Neon;
595
3
    return true;
596
5
  } else if (Name == "vfp" || 
Name == "vfp2"3
||
Name == "vfp3"2
||
597
5
             
Name == "vfp4"1
) {
598
5
    FPMath = FP_VFP;
599
5
    return true;
600
5
  }
601
0
  return false;
602
8
}
603
604
void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
605
57
                                            MacroBuilder &Builder) const {
606
57
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
607
57
}
608
609
void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
610
53
                                            MacroBuilder &Builder) const {
611
  // Also include the ARMv8.1-A defines
612
53
  getTargetDefinesARMV81A(Opts, Builder);
613
53
}
614
615
void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
616
29
                                            MacroBuilder &Builder) const {
617
  // Also include the ARMv8.2-A defines
618
29
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
619
29
  getTargetDefinesARMV82A(Opts, Builder);
620
29
}
621
622
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
623
1.23k
                                     MacroBuilder &Builder) const {
624
  // Target identification.
625
1.23k
  Builder.defineMacro("__arm");
626
1.23k
  Builder.defineMacro("__arm__");
627
  // For bare-metal none-eabi.
628
1.23k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
629
1.23k
      
(644
getTriple().getEnvironment() == llvm::Triple::EABI644
||
630
644
       
getTriple().getEnvironment() == llvm::Triple::EABIHF217
))
631
441
    Builder.defineMacro("__ELF__");
632
633
  // Target properties.
634
1.23k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
635
636
  // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
637
  // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
638
1.23k
  if (getTriple().isWatchABI())
639
29
    Builder.defineMacro("__ARM_ARCH_7K__", "2");
640
641
1.23k
  if (!CPUAttr.empty())
642
1.23k
    Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
643
644
  // ACLE 6.4.1 ARM/Thumb instruction set architecture
645
  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
646
1.23k
  Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
647
648
1.23k
  if (ArchVersion >= 8) {
649
    // ACLE 6.5.7 Crypto Extension
650
    // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained
651
    // feature macros for AES and SHA2
652
423
    if (SHA2 && 
AES94
)
653
93
      Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
654
423
    if (SHA2)
655
94
      Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
656
423
    if (AES)
657
94
      Builder.defineMacro("__ARM_FEATURE_AES", "1");
658
    // ACLE 6.5.8 CRC32 Extension
659
423
    if (CRC)
660
148
      Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
661
    // ACLE 6.5.10 Numeric Maximum and Minimum
662
423
    Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
663
    // ACLE 6.5.9 Directed Rounding
664
423
    Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
665
423
  }
666
667
  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
668
  // is not defined for the M-profile.
669
  // NOTE that the default profile is assumed to be 'A'
670
1.23k
  if (CPUProfile.empty() || 
ArchProfile != llvm::ARM::ProfileKind::M995
)
671
949
    Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
672
673
  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
674
  // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the
675
  // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
676
  // v7 and v8 architectures excluding v8-M Baseline.
677
1.23k
  if (supportsThumb2())
678
968
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
679
269
  else if (supportsThumb())
680
263
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
681
682
  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
683
  // instruction set such as ARM or Thumb.
684
1.23k
  Builder.defineMacro("__ARM_32BIT_STATE", "1");
685
686
  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
687
688
  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
689
1.23k
  if (!CPUProfile.empty())
690
995
    Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
691
692
  // ACLE 6.4.3 Unaligned access supported in hardware
693
1.23k
  if (Unaligned)
694
926
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
695
696
  // ACLE 6.4.4 LDREX/STREX
697
1.23k
  if (LDREX)
698
1.03k
    Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
699
700
  // ACLE 6.4.5 CLZ
701
1.23k
  if (ArchVersion == 5 || 
(1.22k
ArchVersion == 61.22k
&&
CPUProfile != "M"58
) ||
702
1.23k
      
ArchVersion > 61.18k
)
703
1.05k
    Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
704
705
  // ACLE 6.5.1 Hardware Floating Point
706
1.23k
  if (HW_FP)
707
511
    Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
708
709
  // ACLE predefines.
710
1.23k
  Builder.defineMacro("__ARM_ACLE", "200");
711
712
  // FP16 support (we currently only support IEEE format).
713
1.23k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
714
1.23k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
715
716
  // ACLE 6.5.3 Fused multiply-accumulate (FMA)
717
1.23k
  if (ArchVersion >= 7 && 
(FPU & VFP4FPU)994
)
718
204
    Builder.defineMacro("__ARM_FEATURE_FMA", "1");
719
720
  // Subtarget options.
721
722
  // FIXME: It's more complicated than this and we don't really support
723
  // interworking.
724
  // Windows on ARM does not "support" interworking
725
1.23k
  if (5 <= ArchVersion && 
ArchVersion <= 81.06k
&&
!getTriple().isOSWindows()1.06k
)
726
972
    Builder.defineMacro("__THUMB_INTERWORK__");
727
728
1.23k
  if (ABI == "aapcs" || 
ABI == "aapcs-linux"424
||
ABI == "aapcs-vfp"202
) {
729
    // Embedded targets on Darwin follow AAPCS, but not EABI.
730
    // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
731
1.03k
    if (!getTriple().isOSBinFormatMachO() && 
!getTriple().isOSWindows()1.01k
)
732
915
      Builder.defineMacro("__ARM_EABI__");
733
1.03k
    Builder.defineMacro("__ARM_PCS", "1");
734
1.03k
  }
735
736
1.23k
  if ((!SoftFloat && 
!SoftFloatABI1.11k
) ||
ABI == "aapcs-vfp"395
||
ABI == "aapcs16"395
)
737
842
    Builder.defineMacro("__ARM_PCS_VFP", "1");
738
739
1.23k
  if (SoftFloat)
740
124
    Builder.defineMacro("__SOFTFP__");
741
742
  // ACLE position independent code macros.
743
1.23k
  if (Opts.ROPI)
744
2
    Builder.defineMacro("__ARM_ROPI", "1");
745
1.23k
  if (Opts.RWPI)
746
2
    Builder.defineMacro("__ARM_RWPI", "1");
747
748
1.23k
  if (ArchKind == llvm::ARM::ArchKind::XSCALE)
749
0
    Builder.defineMacro("__XSCALE__");
750
751
1.23k
  if (isThumb()) {
752
576
    Builder.defineMacro("__THUMBEL__");
753
576
    Builder.defineMacro("__thumb__");
754
576
    if (supportsThumb2())
755
513
      Builder.defineMacro("__thumb2__");
756
576
  }
757
758
  // ACLE 6.4.9 32-bit SIMD instructions
759
1.23k
  if ((CPUProfile != "M" && 
ArchVersion >= 6949
) ||
(473
CPUProfile == "M"473
&&
DSP288
))
760
801
    Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
761
762
  // ACLE 6.4.10 Hardware Integer Divide
763
1.23k
  if (((HWDiv & HWDivThumb) && 
isThumb()326
) ||
764
1.23k
      
(1.07k
(HWDiv & HWDivARM)1.07k
&&
!isThumb()154
)) {
765
315
    Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
766
315
    Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
767
315
  }
768
769
  // Note, this is always on in gcc, even though it doesn't make sense.
770
1.23k
  Builder.defineMacro("__APCS_32__");
771
772
  // __VFP_FP__ means that the floating-point format is VFP, not that a hardware
773
  // FPU is present. Moreover, the VFP format is the only one supported by
774
  // clang. For these reasons, this macro is always defined.
775
1.23k
  Builder.defineMacro("__VFP_FP__");
776
777
1.23k
  if (FPUModeIsVFP((FPUMode)FPU)) {
778
511
    if (FPU & VFP2FPU)
779
325
      Builder.defineMacro("__ARM_VFPV2__");
780
511
    if (FPU & VFP3FPU)
781
313
      Builder.defineMacro("__ARM_VFPV3__");
782
511
    if (FPU & VFP4FPU)
783
214
      Builder.defineMacro("__ARM_VFPV4__");
784
511
    if (FPU & FPARMV8)
785
271
      Builder.defineMacro("__ARM_FPV5__");
786
511
  }
787
788
  // This only gets set when Neon instructions are actually available, unlike
789
  // the VFP define, hence the soft float and arch check. This is subtly
790
  // different from gcc, we follow the intent which was that it should be set
791
  // when Neon instructions are actually available.
792
1.23k
  if ((FPU & NeonFPU) && 
!SoftFloat281
&&
ArchVersion >= 7280
) {
793
271
    Builder.defineMacro("__ARM_NEON", "1");
794
271
    Builder.defineMacro("__ARM_NEON__");
795
    // current AArch32 NEON implementations do not support double-precision
796
    // floating-point even when it is present in VFP.
797
271
    Builder.defineMacro("__ARM_NEON_FP",
798
271
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
799
271
  }
800
801
1.23k
  if (hasMVE()) {
802
164
    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? 
"3"140
:
"1"24
);
803
164
  }
804
805
1.23k
  if (hasCDE()) {
806
14
    Builder.defineMacro("__ARM_FEATURE_CDE", "1");
807
14
    Builder.defineMacro("__ARM_FEATURE_CDE_COPROC",
808
14
                        "0x" + Twine::utohexstr(getARMCDECoprocMask()));
809
14
  }
810
811
1.23k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
812
1.23k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
41.23k
));
813
814
1.23k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"1.23k
);
815
816
  // CMSE
817
1.23k
  if (ArchVersion == 8 && 
ArchProfile == llvm::ARM::ProfileKind::M423
)
818
232
    Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? 
"3"30
:
"1"202
);
819
820
1.23k
  if (ArchVersion >= 6 && 
CPUAttr != "6M"1.05k
&&
CPUAttr != "8M_BASE"1.03k
) {
821
1.00k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
822
1.00k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
823
1.00k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
824
1.00k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
825
1.00k
  }
826
827
  // ACLE 6.4.7 DSP instructions
828
1.23k
  if (DSP) {
829
406
    Builder.defineMacro("__ARM_FEATURE_DSP", "1");
830
406
  }
831
832
  // ACLE 6.4.8 Saturation instructions
833
1.23k
  bool SAT = false;
834
1.23k
  if ((ArchVersion == 6 && 
CPUProfile != "M"58
) ||
ArchVersion > 61.19k
) {
835
1.03k
    Builder.defineMacro("__ARM_FEATURE_SAT", "1");
836
1.03k
    SAT = true;
837
1.03k
  }
838
839
  // ACLE 6.4.6 Q (saturation) flag
840
1.23k
  if (DSP || 
SAT831
)
841
1.03k
    Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
842
843
1.23k
  if (Opts.UnsafeFPMath)
844
2
    Builder.defineMacro("__ARM_FP_FAST", "1");
845
846
  // Armv8.2-A FP16 vector intrinsic
847
1.23k
  if ((FPU & NeonFPU) && 
HasLegalHalfType281
)
848
19
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
849
850
  // Armv8.2-A FP16 scalar intrinsics
851
1.23k
  if (HasLegalHalfType)
852
169
    Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
853
854
  // Armv8.2-A dot product intrinsics
855
1.23k
  if (DotProd)
856
25
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
857
858
1.23k
  if (HasMatMul)
859
4
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
860
861
1.23k
  if (HasBFloat16) {
862
18
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
863
18
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
864
18
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
865
18
  }
866
867
1.23k
  switch (ArchKind) {
868
1.18k
  default:
869
1.18k
    break;
870
1.18k
  case llvm::ARM::ArchKind::ARMV8_1A:
871
4
    getTargetDefinesARMV81A(Opts, Builder);
872
4
    break;
873
24
  case llvm::ARM::ArchKind::ARMV8_2A:
874
24
    getTargetDefinesARMV82A(Opts, Builder);
875
24
    break;
876
2
  case llvm::ARM::ArchKind::ARMV8_3A:
877
18
  case llvm::ARM::ArchKind::ARMV8_4A:
878
19
  case llvm::ARM::ArchKind::ARMV8_5A:
879
29
  case llvm::ARM::ArchKind::ARMV8_6A:
880
29
    getTargetDefinesARMV83A(Opts, Builder);
881
29
    break;
882
1.23k
  }
883
1.23k
}
884
885
const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
886
#define BUILTIN(ID, TYPE, ATTRS)                                               \
887
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
888
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
889
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
890
#include "clang/Basic/BuiltinsNEON.def"
891
892
#define BUILTIN(ID, TYPE, ATTRS)                                               \
893
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
894
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
895
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
896
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
897
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
898
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
899
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
900
#include "clang/Basic/BuiltinsARM.def"
901
};
902
903
1.23k
ArrayRef<Builtin::Info> ARMTargetInfo::getTargetBuiltins() const {
904
1.23k
  return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin -
905
1.23k
                                             Builtin::FirstTSBuiltin);
906
1.23k
}
907
908
17
bool ARMTargetInfo::isCLZForZeroUndef() const { return false; }
909
722
TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const {
910
722
  return IsAAPCS
911
722
             ? 
AAPCSABIBuiltinVaList546
912
722
             : 
(176
getTriple().isWatchABI()176
?
TargetInfo::CharPtrBuiltinVaList24
913
176
                                         : 
TargetInfo::VoidPtrBuiltinVaList152
);
914
722
}
915
916
const char *const ARMTargetInfo::GCCRegNames[] = {
917
    // Integer registers
918
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
919
    "r12", "sp", "lr", "pc",
920
921
    // Float registers
922
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
923
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
924
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
925
926
    // Double registers
927
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
928
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
929
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
930
931
    // Quad registers
932
    "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11",
933
    "q12", "q13", "q14", "q15"};
934
935
352
ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
936
352
  return llvm::makeArrayRef(GCCRegNames);
937
352
}
938
939
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
940
    {{"a1"}, "r0"},  {{"a2"}, "r1"},        {{"a3"}, "r2"},  {{"a4"}, "r3"},
941
    {{"v1"}, "r4"},  {{"v2"}, "r5"},        {{"v3"}, "r6"},  {{"v4"}, "r7"},
942
    {{"v5"}, "r8"},  {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"},
943
    {{"ip"}, "r12"}, {{"r13"}, "sp"},       {{"r14"}, "lr"}, {{"r15"}, "pc"},
944
    // The S, D and Q registers overlap, but aren't really aliases; we
945
    // don't want to substitute one of these for a different-sized one.
946
};
947
948
179
ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
949
179
  return llvm::makeArrayRef(GCCRegAliases);
950
179
}
951
952
bool ARMTargetInfo::validateAsmConstraint(
953
184
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
954
184
  switch (*Name) {
955
1
  default:
956
1
    break;
957
9
  case 'l': // r0-r7 if thumb, r0-r15 if ARM
958
9
    Info.setAllowsRegister();
959
9
    return true;
960
6
  case 'h': // r8-r15, thumb only
961
6
    if (isThumb()) {
962
4
      Info.setAllowsRegister();
963
4
      return true;
964
4
    }
965
2
    break;
966
4
  case 's': // An integer constant, but allowing only relocatable values.
967
4
    return true;
968
16
  case 't': // s0-s31, d0-d31, or q0-q15
969
36
  case 'w': // s0-s15, d0-d7, or q0-q3
970
44
  case 'x': // s0-s31, d0-d15, or q0-q7
971
44
    Info.setAllowsRegister();
972
44
    return true;
973
16
  case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)
974
    // only available in ARMv6T2 and above
975
16
    if (CPUAttr.equals("6T2") || ArchVersion >= 7) {
976
8
      Info.setRequiresImmediate(0, 65535);
977
8
      return true;
978
8
    }
979
8
    break;
980
16
  case 'I':
981
16
    if (isThumb()) {
982
8
      if (!supportsThumb2())
983
4
        Info.setRequiresImmediate(0, 255);
984
4
      else
985
        // FIXME: should check if immediate value would be valid for a Thumb2
986
        // data-processing instruction
987
4
        Info.setRequiresImmediate();
988
8
    } else
989
      // FIXME: should check if immediate value would be valid for an ARM
990
      // data-processing instruction
991
8
      Info.setRequiresImmediate();
992
16
    return true;
993
32
  case 'J':
994
32
    if (isThumb() && 
!supportsThumb2()16
)
995
8
      Info.setRequiresImmediate(-255, -1);
996
24
    else
997
24
      Info.setRequiresImmediate(-4095, 4095);
998
32
    return true;
999
4
  case 'K':
1000
4
    if (isThumb()) {
1001
2
      if (!supportsThumb2())
1002
        // FIXME: should check if immediate value can be obtained from shifting
1003
        // a value between 0 and 255 left by any amount
1004
1
        Info.setRequiresImmediate();
1005
1
      else
1006
        // FIXME: should check if immediate value would be valid for a Thumb2
1007
        // data-processing instruction when inverted
1008
1
        Info.setRequiresImmediate();
1009
2
    } else
1010
      // FIXME: should check if immediate value would be valid for an ARM
1011
      // data-processing instruction when inverted
1012
2
      Info.setRequiresImmediate();
1013
4
    return true;
1014
16
  case 'L':
1015
16
    if (isThumb()) {
1016
8
      if (!supportsThumb2())
1017
4
        Info.setRequiresImmediate(-7, 7);
1018
4
      else
1019
        // FIXME: should check if immediate value would be valid for a Thumb2
1020
        // data-processing instruction when negated
1021
4
        Info.setRequiresImmediate();
1022
8
    } else
1023
      // FIXME: should check if immediate value  would be valid for an ARM
1024
      // data-processing instruction when negated
1025
8
      Info.setRequiresImmediate();
1026
16
    return true;
1027
4
  case 'M':
1028
4
    if (isThumb() && 
!supportsThumb2()2
)
1029
      // FIXME: should check if immediate value is a multiple of 4 between 0 and
1030
      // 1020
1031
1
      Info.setRequiresImmediate();
1032
3
    else
1033
      // FIXME: should check if immediate value is a power of two or a integer
1034
      // between 0 and 32
1035
3
      Info.setRequiresImmediate();
1036
4
    return true;
1037
16
  case 'N':
1038
    // Thumb1 only
1039
16
    if (isThumb() && 
!supportsThumb2()8
) {
1040
4
      Info.setRequiresImmediate(0, 31);
1041
4
      return true;
1042
4
    }
1043
12
    break;
1044
12
  case 'O':
1045
    // Thumb1 only
1046
4
    if (isThumb() && 
!supportsThumb2()2
) {
1047
      // FIXME: should check if immediate value is a multiple of 4 between -508
1048
      // and 508
1049
1
      Info.setRequiresImmediate();
1050
1
      return true;
1051
1
    }
1052
3
    break;
1053
4
  case 'Q': // A memory address that is a single base register.
1054
4
    Info.setAllowsMemory();
1055
4
    return true;
1056
6
  case 'T':
1057
6
    switch (Name[1]) {
1058
0
    default:
1059
0
      break;
1060
4
    case 'e': // Even general-purpose register
1061
6
    case 'o': // Odd general-purpose register
1062
6
      Info.setAllowsRegister();
1063
6
      Name++;
1064
6
      return true;
1065
6
    }
1066
0
    break;
1067
2
  case 'U': // a memory reference...
1068
2
    switch (Name[1]) {
1069
0
    case 'q': // ...ARMV4 ldrsb
1070
2
    case 'v': // ...VFP load/store (reg+constant offset)
1071
2
    case 'y': // ...iWMMXt load/store
1072
2
    case 't': // address valid for load/store opaque types wider
1073
              // than 128-bits
1074
2
    case 'n': // valid address for Neon doubleword vector load/store
1075
2
    case 'm': // valid address for Neon element and structure load/store
1076
2
    case 's': // valid address for non-offset loads/stores of quad-word
1077
              // values in four ARM registers
1078
2
      Info.setAllowsMemory();
1079
2
      Name++;
1080
2
      return true;
1081
2
    }
1082
0
    break;
1083
184
  }
1084
26
  return false;
1085
184
}
1086
1087
306
std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
1088
306
  std::string R;
1089
306
  switch (*Constraint) {
1090
1
  case 'U': // Two-character constraint; add "^" hint for later parsing.
1091
4
  case 'T':
1092
4
    R = std::string("^") + std::string(Constraint, 2);
1093
4
    Constraint++;
1094
4
    break;
1095
5
  case 'p': // 'p' should be translated to 'r' by default.
1096
5
    R = std::string("r");
1097
5
    break;
1098
297
  default:
1099
297
    return std::string(1, *Constraint);
1100
306
  }
1101
9
  return R;
1102
306
}
1103
1104
bool ARMTargetInfo::validateConstraintModifier(
1105
    StringRef Constraint, char Modifier, unsigned Size,
1106
386
    std::string &SuggestedModifier) const {
1107
386
  bool isOutput = (Constraint[0] == '=');
1108
386
  bool isInOut = (Constraint[0] == '+');
1109
1110
  // Strip off constraint modifiers.
1111
586
  while (Constraint[0] == '=' || 
Constraint[0] == '+'393
||
Constraint[0] == '&'388
)
1112
200
    Constraint = Constraint.substr(1);
1113
1114
386
  switch (Constraint[0]) {
1115
161
  default:
1116
161
    break;
1117
225
  case 'r': {
1118
225
    switch (Modifier) {
1119
217
    default:
1120
217
      return (isInOut || 
isOutput215
||
Size <= 6461
);
1121
8
    case 'q':
1122
      // A register of size 32 cannot fit a vector type.
1123
8
      return false;
1124
225
    }
1125
225
  }
1126
386
  }
1127
1128
161
  return true;
1129
386
}
1130
118
const char *ARMTargetInfo::getClobbers() const {
1131
  // FIXME: Is this really right?
1132
118
  return "";
1133
118
}
1134
1135
TargetInfo::CallingConvCheckResult
1136
700
ARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1137
700
  switch (CC) {
1138
14
  case CC_AAPCS:
1139
25
  case CC_AAPCS_VFP:
1140
485
  case CC_Swift:
1141
700
  case CC_SwiftAsync:
1142
700
  case CC_OpenCLKernel:
1143
700
    return CCCR_OK;
1144
0
  default:
1145
0
    return CCCR_Warning;
1146
700
  }
1147
700
}
1148
1149
4
int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
1150
4
  if (RegNo == 0)
1151
2
    return 0;
1152
2
  if (RegNo == 1)
1153
2
    return 1;
1154
0
  return -1;
1155
2
}
1156
1157
0
bool ARMTargetInfo::hasSjLjLowering() const { return true; }
1158
1159
ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple,
1160
                                 const TargetOptions &Opts)
1161
1.21k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1161
608
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1161
608
    : ARMTargetInfo(Triple, Opts) {}
1162
1163
void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1164
1.19k
                                       MacroBuilder &Builder) const {
1165
1.19k
  Builder.defineMacro("__ARMEL__");
1166
1.19k
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1167
1.19k
}
1168
1169
ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple,
1170
                                 const TargetOptions &Opts)
1171
39
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1171
11
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1171
28
    : ARMTargetInfo(Triple, Opts) {}
1172
1173
void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts,
1174
39
                                       MacroBuilder &Builder) const {
1175
39
  Builder.defineMacro("__ARMEB__");
1176
39
  Builder.defineMacro("__ARM_BIG_ENDIAN");
1177
39
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1178
39
}
1179
1180
WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
1181
                                           const TargetOptions &Opts)
1182
95
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1183
95
}
clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1182
95
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1183
95
}
Unexecuted instantiation: clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1184
1185
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
1186
82
                                                  MacroBuilder &Builder) const {
1187
  // FIXME: this is invalid for WindowsCE
1188
82
  Builder.defineMacro("_M_ARM_NT", "1");
1189
82
  Builder.defineMacro("_M_ARMT", "_M_ARM");
1190
82
  Builder.defineMacro("_M_THUMB", "_M_ARM");
1191
1192
82
  assert((Triple.getArch() == llvm::Triple::arm ||
1193
82
          Triple.getArch() == llvm::Triple::thumb) &&
1194
82
         "invalid architecture for Windows ARM target info");
1195
82
  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 
48
:
674
;
1196
82
  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
1197
1198
  // TODO map the complete set of values
1199
  // 31: VFPv3 40: VFPv4
1200
82
  Builder.defineMacro("_M_ARM_FP", "31");
1201
82
}
1202
1203
TargetInfo::BuiltinVaListKind
1204
85
WindowsARMTargetInfo::getBuiltinVaListKind() const {
1205
85
  return TargetInfo::CharPtrBuiltinVaList;
1206
85
}
1207
1208
TargetInfo::CallingConvCheckResult
1209
29
WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1210
29
  switch (CC) {
1211
1
  case CC_X86StdCall:
1212
1
  case CC_X86ThisCall:
1213
1
  case CC_X86FastCall:
1214
1
  case CC_X86VectorCall:
1215
1
    return CCCR_Ignore;
1216
17
  case CC_C:
1217
17
  case CC_OpenCLKernel:
1218
22
  case CC_PreserveMost:
1219
27
  case CC_PreserveAll:
1220
28
  case CC_Swift:
1221
28
  case CC_SwiftAsync:
1222
28
    return CCCR_OK;
1223
0
  default:
1224
0
    return CCCR_Warning;
1225
29
  }
1226
29
}
1227
1228
// Windows ARM + Itanium C++ ABI Target
1229
ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(
1230
    const llvm::Triple &Triple, const TargetOptions &Opts)
1231
10
    : WindowsARMTargetInfo(Triple, Opts) {
1232
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1233
10
}
Unexecuted instantiation: clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1231
10
    : WindowsARMTargetInfo(Triple, Opts) {
1232
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1233
10
}
1234
1235
void ItaniumWindowsARMleTargetInfo::getTargetDefines(
1236
10
    const LangOptions &Opts, MacroBuilder &Builder) const {
1237
10
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1238
1239
10
  if (Opts.MSVCCompat)
1240
1
    WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1241
10
}
1242
1243
// Windows ARM, MS (C++) ABI
1244
MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
1245
                                                   const TargetOptions &Opts)
1246
81
    : WindowsARMTargetInfo(Triple, Opts) {
1247
81
  TheCXXABI.set(TargetCXXABI::Microsoft);
1248
81
}
Unexecuted instantiation: clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1246
81
    : WindowsARMTargetInfo(Triple, Opts) {
1247
81
  TheCXXABI.set(TargetCXXABI::Microsoft);
1248
81
}
1249
1250
void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1251
81
                                                MacroBuilder &Builder) const {
1252
81
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1253
81
  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1254
81
}
1255
1256
MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple,
1257
                                       const TargetOptions &Opts)
1258
4
    : WindowsARMTargetInfo(Triple, Opts) {
1259
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1260
4
}
Unexecuted instantiation: clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1258
4
    : WindowsARMTargetInfo(Triple, Opts) {
1259
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1260
4
}
1261
1262
void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1263
4
                                          MacroBuilder &Builder) const {
1264
4
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1265
4
  Builder.defineMacro("_ARM_");
1266
4
}
1267
1268
CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
1269
                                         const TargetOptions &Opts)
1270
1
    : ARMleTargetInfo(Triple, Opts) {
1271
1
  this->WCharType = TargetInfo::UnsignedShort;
1272
1
  TLSSupported = false;
1273
1
  DoubleAlign = LongLongAlign = 64;
1274
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1275
1
}
Unexecuted instantiation: clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1270
1
    : ARMleTargetInfo(Triple, Opts) {
1271
1
  this->WCharType = TargetInfo::UnsignedShort;
1272
1
  TLSSupported = false;
1273
1
  DoubleAlign = LongLongAlign = 64;
1274
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1275
1
}
1276
1277
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1278
1
                                           MacroBuilder &Builder) const {
1279
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1280
1
  Builder.defineMacro("_ARM_");
1281
1
  Builder.defineMacro("__CYGWIN__");
1282
1
  Builder.defineMacro("__CYGWIN32__");
1283
1
  DefineStd(Builder, "unix", Opts);
1284
1
  if (Opts.CPlusPlus)
1285
0
    Builder.defineMacro("_GNU_SOURCE");
1286
1
}
1287
1288
DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
1289
                                         const TargetOptions &Opts)
1290
213
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1291
213
  HasAlignMac68kSupport = true;
1292
  // iOS always has 64-bit atomic instructions.
1293
  // FIXME: This should be based off of the target features in
1294
  // ARMleTargetInfo.
1295
213
  MaxAtomicInlineWidth = 64;
1296
1297
213
  if (Triple.isWatchABI()) {
1298
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1299
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1300
1301
    // BOOL should be a real boolean on the new ABI
1302
29
    UseSignedCharForObjCBool = false;
1303
29
  } else
1304
184
    TheCXXABI.set(TargetCXXABI::iOS);
1305
213
}
Unexecuted instantiation: clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1290
213
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1291
213
  HasAlignMac68kSupport = true;
1292
  // iOS always has 64-bit atomic instructions.
1293
  // FIXME: This should be based off of the target features in
1294
  // ARMleTargetInfo.
1295
213
  MaxAtomicInlineWidth = 64;
1296
1297
213
  if (Triple.isWatchABI()) {
1298
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1299
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1300
1301
    // BOOL should be a real boolean on the new ABI
1302
29
    UseSignedCharForObjCBool = false;
1303
29
  } else
1304
184
    TheCXXABI.set(TargetCXXABI::iOS);
1305
213
}
1306
1307
void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts,
1308
                                       const llvm::Triple &Triple,
1309
202
                                       MacroBuilder &Builder) const {
1310
202
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1311
202
}
1312
1313
RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple,
1314
                                                   const TargetOptions &Opts)
1315
    : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
1316
                                   Triple.getOSName(),
1317
                                   Triple.getEnvironmentName()),
1318
1
                      Opts) {
1319
1
  IsRenderScriptTarget = true;
1320
1
  LongWidth = LongAlign = 64;
1321
1
}
clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1318
1
                      Opts) {
1319
1
  IsRenderScriptTarget = true;
1320
1
  LongWidth = LongAlign = 64;
1321
1
}
Unexecuted instantiation: clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1322
1323
void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts,
1324
1
                                                MacroBuilder &Builder) const {
1325
1
  Builder.defineMacro("__RENDERSCRIPT__");
1326
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1327
1
}