Coverage Report

Created: 2022-07-16 07:03

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/ARM.h
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//===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares ARM TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
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#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ARMTargetParser.h"
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#include "llvm/Support/TargetParser.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
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  // Possible FPU choices.
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  enum FPUMode {
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    VFP2FPU = (1 << 0),
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    VFP3FPU = (1 << 1),
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    VFP4FPU = (1 << 2),
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    NeonFPU = (1 << 3),
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    FPARMV8 = (1 << 4)
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  };
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  enum MVEMode {
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      MVE_INT = (1 << 0),
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      MVE_FP  = (1 << 1)
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  };
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  // Possible HWDiv features.
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  enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };
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  static bool FPUModeIsVFP(FPUMode Mode) {
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    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
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  }
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  static const TargetInfo::GCCRegAlias GCCRegAliases[];
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  static const char *const GCCRegNames[];
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  std::string ABI, CPU;
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  StringRef CPUProfile;
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  StringRef CPUAttr;
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  enum { FP_Default, FP_VFP, FP_Neon } FPMath;
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  llvm::ARM::ISAKind ArchISA;
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  llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
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  llvm::ARM::ProfileKind ArchProfile;
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  unsigned ArchVersion;
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  unsigned FPU : 5;
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  unsigned MVE : 2;
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  unsigned IsAAPCS : 1;
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  unsigned HWDiv : 2;
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  // Initialized via features.
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  unsigned SoftFloat : 1;
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  unsigned SoftFloatABI : 1;
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  unsigned CRC : 1;
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  unsigned Crypto : 1;
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  unsigned SHA2 : 1;
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  unsigned AES : 1;
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  unsigned DSP : 1;
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  unsigned Unaligned : 1;
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  unsigned DotProd : 1;
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  unsigned HasMatMul : 1;
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  unsigned FPRegsDisabled : 1;
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  unsigned HasPAC : 1;
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  unsigned HasBTI : 1;
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  enum {
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    LDREX_B = (1 << 0), /// byte (8-bit)
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    LDREX_H = (1 << 1), /// half (16-bit)
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    LDREX_W = (1 << 2), /// word (32-bit)
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    LDREX_D = (1 << 3), /// double (64-bit)
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  };
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  uint32_t LDREX;
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  // ACLE 6.5.1 Hardware floating point
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  enum {
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    HW_FP_HP = (1 << 1), /// half (16-bit)
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    HW_FP_SP = (1 << 2), /// single (32-bit)
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    HW_FP_DP = (1 << 3), /// double (64-bit)
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  };
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  uint32_t HW_FP;
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  static const Builtin::Info BuiltinInfo[];
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  void setABIAAPCS();
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  void setABIAPCS(bool IsAAPCS16);
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  void setArchInfo();
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  void setArchInfo(llvm::ARM::ArchKind Kind);
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  void setAtomic();
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  bool isThumb() const;
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  bool supportsThumb() const;
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  bool supportsThumb2() const;
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  bool hasMVE() const;
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  bool hasMVEFloat() const;
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  bool hasCDE() const;
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  StringRef getCPUAttr() const;
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  StringRef getCPUProfile() const;
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public:
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  ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  StringRef getABI() const override;
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  bool setABI(const std::string &Name) override;
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  bool isBranchProtectionSupportedArch(StringRef Arch) const override;
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  bool validateBranchProtection(StringRef Spec, StringRef Arch,
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                                BranchProtectionInfo &BPI,
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                                StringRef &Err) const override;
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  // FIXME: This should be based on Arch attributes, not CPU names.
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  bool
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  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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                 StringRef CPU,
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                 const std::vector<std::string> &FeaturesVec) const override;
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  bool isValidFeatureName(StringRef Feature) const override {
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    // We pass soft-float-abi in as a -target-feature, but the backend figures
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    // this out through other means.
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    return Feature != "soft-float-abi";
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  }
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  bool handleTargetFeatures(std::vector<std::string> &Features,
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                            DiagnosticsEngine &Diags) override;
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  bool hasFeature(StringRef Feature) const override;
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  bool hasBFloat16Type() const override;
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  bool isValidCPUName(StringRef Name) const override;
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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  bool setCPU(const std::string &Name) override;
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  bool setFPMath(StringRef Name) override;
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  bool useFP16ConversionIntrinsics() const override {
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    return false;
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  }
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  void getTargetDefinesARMV81A(const LangOptions &Opts,
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                               MacroBuilder &Builder) const;
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  void getTargetDefinesARMV82A(const LangOptions &Opts,
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                               MacroBuilder &Builder) const;
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  void getTargetDefinesARMV83A(const LangOptions &Opts,
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                                 MacroBuilder &Builder) const;
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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  bool isCLZForZeroUndef() const override;
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  BuiltinVaListKind getBuiltinVaListKind() const override;
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  ArrayRef<const char *> getGCCRegNames() const override;
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
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  bool validateAsmConstraint(const char *&Name,
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                             TargetInfo::ConstraintInfo &Info) const override;
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  std::string convertConstraint(const char *&Constraint) const override;
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  bool
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  validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
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                             std::string &SuggestedModifier) const override;
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  const char *getClobbers() const override;
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  StringRef getConstraintRegister(StringRef Constraint,
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                                  StringRef Expression) const override {
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    return Expression;
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  }
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  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
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  int getEHDataRegisterNumber(unsigned RegNo) const override;
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  bool hasSjLjLowering() const override;
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  bool hasBitIntType() const override { return true; }
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  const char *getBFloat16Mangling() const override { return "u6__bf16"; };
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};
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class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo {
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public:
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  ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY ARMbeTargetInfo : public ARMTargetInfo {
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public:
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  ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY WindowsARMTargetInfo
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    : public WindowsTargetInfo<ARMleTargetInfo> {
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  const llvm::Triple Triple;
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public:
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  WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void getVisualStudioDefines(const LangOptions &Opts,
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                              MacroBuilder &Builder) const;
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  BuiltinVaListKind getBuiltinVaListKind() const override;
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  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
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};
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// Windows ARM + Itanium C++ ABI Target
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class LLVM_LIBRARY_VISIBILITY ItaniumWindowsARMleTargetInfo
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    : public WindowsARMTargetInfo {
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public:
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  ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
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                                const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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// Windows ARM, MS (C++) ABI
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class LLVM_LIBRARY_VISIBILITY MicrosoftARMleTargetInfo
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    : public WindowsARMTargetInfo {
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public:
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  MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
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                           const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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// ARM MinGW target
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class LLVM_LIBRARY_VISIBILITY MinGWARMTargetInfo : public WindowsARMTargetInfo {
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public:
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  MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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// ARM Cygwin target
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class LLVM_LIBRARY_VISIBILITY CygwinARMTargetInfo : public ARMleTargetInfo {
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public:
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  CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY DarwinARMTargetInfo
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    : public DarwinTargetInfo<ARMleTargetInfo> {
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protected:
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  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
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                    MacroBuilder &Builder) const override;
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public:
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  DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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};
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// 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
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class LLVM_LIBRARY_VISIBILITY RenderScript32TargetInfo
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    : public ARMleTargetInfo {
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public:
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  RenderScript32TargetInfo(const llvm::Triple &Triple,
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                           const TargetOptions &Opts);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H