Coverage Report

Created: 2020-02-25 14:32

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/Hexagon.h
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//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Hexagon TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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namespace clang {
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namespace targets {
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// Hexagon abstract base class
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class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
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  static const Builtin::Info BuiltinInfo[];
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  static const char *const GCCRegNames[];
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  static const TargetInfo::GCCRegAlias GCCRegAliases[];
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  std::string CPU;
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  std::string HVXVersion;
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  bool HasHVX = false;
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  bool HasHVX64B = false;
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  bool HasHVX128B = false;
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  bool HasAudio = false;
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  bool UseLongCalls = false;
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public:
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  HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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      : TargetInfo(Triple) {
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    // Specify the vector alignment explicitly. For v512x1, the calculated
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    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
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    // the required minimum of 64 bytes.
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    resetDataLayout(
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        "e-m:e-p:32:32:32-a:0-n16:32-"
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        "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
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        "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
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    SizeType = UnsignedInt;
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    PtrDiffType = SignedInt;
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    IntPtrType = SignedInt;
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    // {} in inline assembly are packet specifiers, not assembly variant
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    // specifiers.
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    NoAsmVariants = true;
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    LargeArrayMinWidth = 64;
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    LargeArrayAlign = 64;
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    UseBitFieldTypeAlignment = true;
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    ZeroLengthBitfieldBoundary = 32;
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    // These are the default values anyway, but explicitly make sure
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    // that the size of the boolean type is 8 bits. Bool vectors are used
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    // for modeling predicate registers in HVX, and the bool -> byte
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    // correspondence matches the HVX architecture.
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    BoolWidth = BoolAlign = 8;
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  }
clang::targets::HexagonTargetInfo::HexagonTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
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      : TargetInfo(Triple) {
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    // Specify the vector alignment explicitly. For v512x1, the calculated
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    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
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    // the required minimum of 64 bytes.
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    resetDataLayout(
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        "e-m:e-p:32:32:32-a:0-n16:32-"
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        "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
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        "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
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    SizeType = UnsignedInt;
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    PtrDiffType = SignedInt;
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    IntPtrType = SignedInt;
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    // {} in inline assembly are packet specifiers, not assembly variant
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    // specifiers.
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    NoAsmVariants = true;
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    LargeArrayMinWidth = 64;
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    LargeArrayAlign = 64;
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    UseBitFieldTypeAlignment = true;
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    ZeroLengthBitfieldBoundary = 32;
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    // These are the default values anyway, but explicitly make sure
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    // that the size of the boolean type is 8 bits. Bool vectors are used
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    // for modeling predicate registers in HVX, and the bool -> byte
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    // correspondence matches the HVX architecture.
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    BoolWidth = BoolAlign = 8;
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  }
Unexecuted instantiation: clang::targets::HexagonTargetInfo::HexagonTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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  bool validateAsmConstraint(const char *&Name,
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                             TargetInfo::ConstraintInfo &Info) const override {
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    switch (*Name) {
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    case 'v':
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    case 'q':
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      if (HasHVX) {
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        Info.setAllowsRegister();
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        return true;
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      }
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      break;
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    case 'a': // Modifier register m0-m1.
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      Info.setAllowsRegister();
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      return true;
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    case 's':
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      // Relocatable constant.
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      return true;
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    }
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    return false;
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  bool isCLZForZeroUndef() const override { return false; }
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  bool hasFeature(StringRef Feature) const override;
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  bool
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  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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                 StringRef CPU,
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                 const std::vector<std::string> &FeaturesVec) const override;
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  bool handleTargetFeatures(std::vector<std::string> &Features,
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                            DiagnosticsEngine &Diags) override;
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  BuiltinVaListKind getBuiltinVaListKind() const override {
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    return TargetInfo::CharPtrBuiltinVaList;
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  }
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  ArrayRef<const char *> getGCCRegNames() const override;
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
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  const char *getClobbers() const override { return ""; }
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  static const char *getHexagonCPUSuffix(StringRef Name);
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  bool isValidCPUName(StringRef Name) const override {
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    return getHexagonCPUSuffix(Name);
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  }
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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  bool setCPU(const std::string &Name) override {
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    if (!isValidCPUName(Name))
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      return false;
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    CPU = Name;
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    return true;
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  }
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  int getEHDataRegisterNumber(unsigned RegNo) const override {
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    return RegNo < 2 ? RegNo : -1;
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  }
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  bool isTinyCore() const {
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    // We can write more stricter checks later.
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    return CPU.find('t') != std::string::npos;
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  }
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H