Coverage Report

Created: 2020-09-15 12:33

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/Mips.h
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//===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Mips TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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260
  void setDataLayout() {
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260
    StringRef Layout;
27
260
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    if (ABI == "o32")
29
123
      Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
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137
    else if (ABI == "n32")
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      Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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    else if (ABI == "n64")
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      Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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    else
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0
      llvm_unreachable("Invalid ABI");
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260
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260
    if (BigEndian)
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      resetDataLayout(("E-" + Layout).str());
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    else
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      resetDataLayout(("e-" + Layout).str());
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  }
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  static const Builtin::Info BuiltinInfo[];
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  std::string CPU;
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  bool IsMips16;
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  bool IsMicromips;
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  bool IsNan2008;
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  bool IsAbs2008;
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  bool IsSingleFloat;
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  bool IsNoABICalls;
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  bool CanUseBSDABICalls;
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  enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
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  enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
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  bool HasMSA;
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  bool DisableMadd4;
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  bool UseIndirectJumpHazard;
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protected:
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  enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
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  std::string ABI;
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public:
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  MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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      : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
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        IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
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        IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
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        DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
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264
        UseIndirectJumpHazard(false), FPMode(FPXX) {
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    TheCXXABI.set(TargetCXXABI::GenericMIPS);
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264
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    if (Triple.isMIPS32())
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126
      setABI("o32");
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    else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
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13
      setABI("n32");
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125
    else
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      setABI("n64");
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    CPU = ABI == "o32" ? 
"mips32r2"126
: "mips64r2";
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    CanUseBSDABICalls = Triple.isOSFreeBSD() ||
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                        Triple.isOSOpenBSD();
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  }
clang::targets::MipsTargetInfo::MipsTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
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        UseIndirectJumpHazard(false), FPMode(FPXX) {
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    TheCXXABI.set(TargetCXXABI::GenericMIPS);
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    if (Triple.isMIPS32())
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      setABI("o32");
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27
    else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
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0
      setABI("n32");
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27
    else
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      setABI("n64");
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    CPU = ABI == "o32" ? "mips32r2" : 
"mips64r2"27
;
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    CanUseBSDABICalls = Triple.isOSFreeBSD() ||
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                        Triple.isOSOpenBSD();
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  }
clang::targets::MipsTargetInfo::MipsTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
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        UseIndirectJumpHazard(false), FPMode(FPXX) {
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    TheCXXABI.set(TargetCXXABI::GenericMIPS);
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    if (Triple.isMIPS32())
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      setABI("o32");
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    else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
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      setABI("n32");
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    else
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      setABI("n64");
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189
78
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    CPU = ABI == "o32" ? 
"mips32r2"78
: "mips64r2";
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    CanUseBSDABICalls = Triple.isOSFreeBSD() ||
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                        Triple.isOSOpenBSD();
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189
  }
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520
  bool isIEEE754_2008Default() const {
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    return CPU == "mips32r6" || 
CPU == "mips64r6"510
;
86
520
  }
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260
  bool isFP64Default() const {
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260
    return CPU == "mips32r6" || 
ABI == "n32"255
||
ABI == "n64"224
||
ABI == "64"118
;
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  }
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  bool isNan2008() const override { return IsNan2008; }
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  bool processorSupportsGPR64() const;
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  StringRef getABI() const override { return ABI; }
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325
  bool setABI(const std::string &Name) override {
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325
    if (Name == "o32") {
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      setO32ABITypes();
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      ABI = Name;
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      return true;
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    }
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    if (Name == "n32") {
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      setN32ABITypes();
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      ABI = Name;
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      return true;
109
31
    }
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    if (Name == "n64") {
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      setN64ABITypes();
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      ABI = Name;
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      return true;
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    }
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    return false;
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2
  }
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  void setO32ABITypes() {
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    Int64Type = SignedLongLong;
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    IntMaxType = Int64Type;
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    LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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    LongDoubleWidth = LongDoubleAlign = 64;
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    LongWidth = LongAlign = 32;
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    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
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    PointerWidth = PointerAlign = 32;
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144
    PtrDiffType = SignedInt;
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144
    SizeType = UnsignedInt;
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    SuitableAlign = 64;
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  }
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  void setN32N64ABITypes() {
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    LongDoubleWidth = LongDoubleAlign = 128;
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    LongDoubleFormat = &llvm::APFloat::IEEEquad();
134
179
    if (getTriple().isOSFreeBSD()) {
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2
      LongDoubleWidth = LongDoubleAlign = 64;
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2
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
137
2
    }
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    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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    SuitableAlign = 128;
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  }
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  void setN64ABITypes() {
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    setN32N64ABITypes();
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    if (getTriple().isOSOpenBSD()) {
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3
      Int64Type = SignedLongLong;
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145
    } else {
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      Int64Type = SignedLong;
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145
    }
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    IntMaxType = Int64Type;
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    LongWidth = LongAlign = 64;
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    PointerWidth = PointerAlign = 64;
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    PtrDiffType = SignedLong;
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    SizeType = UnsignedLong;
154
148
  }
155
156
31
  void setN32ABITypes() {
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31
    setN32N64ABITypes();
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31
    Int64Type = SignedLongLong;
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    IntMaxType = Int64Type;
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31
    LongWidth = LongAlign = 32;
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    PointerWidth = PointerAlign = 32;
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    PtrDiffType = SignedInt;
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    SizeType = UnsignedInt;
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31
  }
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  bool isValidCPUName(StringRef Name) const override;
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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  bool setCPU(const std::string &Name) override {
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    CPU = Name;
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    return isValidCPUName(Name);
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  }
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  const std::string &getCPU() const { return CPU; }
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  bool
176
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
177
                 StringRef CPU,
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                 const std::vector<std::string> &FeaturesVec) const override {
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    if (CPU.empty())
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      CPU = getCPU();
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    if (CPU == "octeon")
182
1
      Features["mips64r2"] = Features["cnmips"] = true;
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259
    else if (CPU == "octeon+")
184
1
      Features["mips64r2"] = Features["cnmips"] = Features["cnmipsp"] = true;
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    else
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      Features[CPU] = true;
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    return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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  }
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  unsigned getISARev() const;
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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  bool hasFeature(StringRef Feature) const override;
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185
  BuiltinVaListKind getBuiltinVaListKind() const override {
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    return TargetInfo::VoidPtrBuiltinVaList;
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  }
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691
  ArrayRef<const char *> getGCCRegNames() const override {
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    static const char *const GCCRegNames[] = {
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        // CPU register names
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        // Must match second column of GCCRegAliases
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691
        "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
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        "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
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        "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
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        "$31",
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        // Floating point register names
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        "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
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        "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
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        "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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        "$f28", "$f29", "$f30", "$f31",
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        // Hi/lo and condition register names
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        "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
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        "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
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        "$ac3lo",
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        // MSA register names
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        "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
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        "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
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        "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
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        "$w28", "$w29", "$w30", "$w31",
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        // MSA control register names
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        "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
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        "$msarequest", "$msamap", "$msaunmap"
228
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    };
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    return llvm::makeArrayRef(GCCRegNames);
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  }
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  bool validateAsmConstraint(const char *&Name,
233
18
                             TargetInfo::ConstraintInfo &Info) const override {
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18
    switch (*Name) {
235
0
    default:
236
0
      return false;
237
10
    case 'r': // CPU registers.
238
10
    case 'd': // Equivalent to "r" unless generating MIPS16 code.
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10
    case 'y': // Equivalent to "r", backward compatibility only.
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10
    case 'f': // floating-point registers.
241
10
    case 'c': // $25 for indirect jumps
242
10
    case 'l': // lo register
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10
    case 'x': // hilo register pair
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10
      Info.setAllowsRegister();
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10
      return true;
246
2
    case 'I': // Signed 16-bit constant
247
2
    case 'J': // Integer 0
248
2
    case 'K': // Unsigned 16-bit constant
249
2
    case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
250
2
    case 'M': // Constants not loadable via lui, addiu, or ori
251
2
    case 'N': // Constant -1 to -65535
252
2
    case 'O': // A signed 15-bit constant
253
2
    case 'P': // A constant between 1 go 65535
254
2
      return true;
255
4
    case 'R': // An address that can be used in a non-macro load or store
256
4
      Info.setAllowsMemory();
257
4
      return true;
258
2
    case 'Z':
259
2
      if (Name[1] == 'C') { // An address usable by ll, and sc.
260
2
        Info.setAllowsMemory();
261
2
        Name++; // Skip over 'Z'.
262
2
        return true;
263
2
      }
264
0
      return false;
265
18
    }
266
18
  }
267
268
263
  std::string convertConstraint(const char *&Constraint) const override {
269
263
    std::string R;
270
263
    switch (*Constraint) {
271
1
    case 'Z': // Two-character constraint; add "^" hint for later parsing.
272
1
      if (Constraint[1] == 'C') {
273
1
        R = std::string("^") + std::string(Constraint, 2);
274
1
        Constraint++;
275
1
        return R;
276
1
      }
277
0
      break;
278
262
    }
279
262
    return TargetInfo::convertConstraint(Constraint);
280
262
  }
281
282
220
  const char *getClobbers() const override {
283
    // In GCC, $1 is not widely used in generated code (it's used only in a few
284
    // specific situations), so there is no real need for users to add it to
285
    // the clobbers list if they want to use it in their inline assembly code.
286
    //
287
    // In LLVM, $1 is treated as a normal GPR and is always allocatable during
288
    // code generation, so using it in inline assembly without adding it to the
289
    // clobbers list can cause conflicts between the inline assembly code and
290
    // the surrounding generated code.
291
    //
292
    // Another problem is that LLVM is allowed to choose $1 for inline assembly
293
    // operands, which will conflict with the ".set at" assembler option (which
294
    // we use only for inline assembly, in order to maintain compatibility with
295
    // GCC) and will also conflict with the user's usage of $1.
296
    //
297
    // The easiest way to avoid these conflicts and keep $1 as an allocatable
298
    // register for generated code is to automatically clobber $1 for all inline
299
    // assembly code.
300
    //
301
    // FIXME: We should automatically clobber $1 only for inline assembly code
302
    // which actually uses it. This would allow LLVM to use $1 for inline
303
    // assembly operands if the user's assembly code doesn't use it.
304
220
    return "~{$1}";
305
220
  }
306
307
  bool handleTargetFeatures(std::vector<std::string> &Features,
308
260
                            DiagnosticsEngine &Diags) override {
309
260
    IsMips16 = false;
310
260
    IsMicromips = false;
311
260
    IsNan2008 = isIEEE754_2008Default();
312
260
    IsAbs2008 = isIEEE754_2008Default();
313
260
    IsSingleFloat = false;
314
260
    FloatABI = HardFloat;
315
260
    DspRev = NoDSP;
316
142
    FPMode = isFP64Default() ? FP64 : 
FPXX118
;
317
260
318
347
    for (const auto &Feature : Features) {
319
347
      if (Feature == "+single-float")
320
4
        IsSingleFloat = true;
321
343
      else if (Feature == "+soft-float")
322
3
        FloatABI = SoftFloat;
323
340
      else if (Feature == "+mips16")
324
1
        IsMips16 = true;
325
339
      else if (Feature == "+micromips")
326
1
        IsMicromips = true;
327
338
      else if (Feature == "+dsp")
328
1
        DspRev = std::max(DspRev, DSP1);
329
337
      else if (Feature == "+dspr2")
330
3
        DspRev = std::max(DspRev, DSP2);
331
334
      else if (Feature == "+msa")
332
3
        HasMSA = true;
333
331
      else if (Feature == "+nomadd4")
334
3
        DisableMadd4 = true;
335
328
      else if (Feature == "+fp64")
336
5
        FPMode = FP64;
337
323
      else if (Feature == "-fp64")
338
3
        FPMode = FP32;
339
320
      else if (Feature == "+fpxx")
340
4
        FPMode = FPXX;
341
316
      else if (Feature == "+nan2008")
342
6
        IsNan2008 = true;
343
310
      else if (Feature == "-nan2008")
344
7
        IsNan2008 = false;
345
303
      else if (Feature == "+abs2008")
346
2
        IsAbs2008 = true;
347
301
      else if (Feature == "-abs2008")
348
2
        IsAbs2008 = false;
349
299
      else if (Feature == "+noabicalls")
350
0
        IsNoABICalls = true;
351
299
      else if (Feature == "+use-indirect-jump-hazard")
352
0
        UseIndirectJumpHazard = true;
353
347
    }
354
260
355
260
    setDataLayout();
356
260
357
260
    return true;
358
260
  }
359
360
4
  int getEHDataRegisterNumber(unsigned RegNo) const override {
361
4
    if (RegNo == 0)
362
2
      return 4;
363
2
    if (RegNo == 1)
364
2
      return 5;
365
0
    return -1;
366
0
  }
367
368
6
  bool isCLZForZeroUndef() const override { return false; }
369
370
382
  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
371
382
    static const TargetInfo::GCCRegAlias O32RegAliases[] = {
372
382
        {{"at"}, "$1"},  {{"v0"}, "$2"},         {{"v1"}, "$3"},
373
382
        {{"a0"}, "$4"},  {{"a1"}, "$5"},         {{"a2"}, "$6"},
374
382
        {{"a3"}, "$7"},  {{"t0"}, "$8"},         {{"t1"}, "$9"},
375
382
        {{"t2"}, "$10"}, {{"t3"}, "$11"},        {{"t4"}, "$12"},
376
382
        {{"t5"}, "$13"}, {{"t6"}, "$14"},        {{"t7"}, "$15"},
377
382
        {{"s0"}, "$16"}, {{"s1"}, "$17"},        {{"s2"}, "$18"},
378
382
        {{"s3"}, "$19"}, {{"s4"}, "$20"},        {{"s5"}, "$21"},
379
382
        {{"s6"}, "$22"}, {{"s7"}, "$23"},        {{"t8"}, "$24"},
380
382
        {{"t9"}, "$25"}, {{"k0"}, "$26"},        {{"k1"}, "$27"},
381
382
        {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
382
382
        {{"ra"}, "$31"}
383
382
    };
384
382
    static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
385
382
        {{"at"}, "$1"},  {{"v0"}, "$2"},         {{"v1"}, "$3"},
386
382
        {{"a0"}, "$4"},  {{"a1"}, "$5"},         {{"a2"}, "$6"},
387
382
        {{"a3"}, "$7"},  {{"a4"}, "$8"},         {{"a5"}, "$9"},
388
382
        {{"a6"}, "$10"}, {{"a7"}, "$11"},        {{"t0"}, "$12"},
389
382
        {{"t1"}, "$13"}, {{"t2"}, "$14"},        {{"t3"}, "$15"},
390
382
        {{"s0"}, "$16"}, {{"s1"}, "$17"},        {{"s2"}, "$18"},
391
382
        {{"s3"}, "$19"}, {{"s4"}, "$20"},        {{"s5"}, "$21"},
392
382
        {{"s6"}, "$22"}, {{"s7"}, "$23"},        {{"t8"}, "$24"},
393
382
        {{"t9"}, "$25"}, {{"k0"}, "$26"},        {{"k1"}, "$27"},
394
382
        {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
395
382
        {{"ra"}, "$31"}
396
382
    };
397
382
    if (ABI == "o32")
398
382
      return llvm::makeArrayRef(O32RegAliases);
399
0
    return llvm::makeArrayRef(NewABIRegAliases);
400
0
  }
401
402
703
  bool hasInt128Type() const override {
403
703
    return (ABI == "n32" || 
ABI == "n64"612
) ||
getTargetOpts().ForceEnableInt128330
;
404
703
  }
405
406
  unsigned getUnwindWordWidth() const override;
407
408
  bool validateTarget(DiagnosticsEngine &Diags) const override;
409
30
  bool hasExtIntType() const override { return true; }
410
};
411
} // namespace targets
412
} // namespace clang
413
414
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H