Coverage Report

Created: 2022-01-18 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp
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Source (jump to first uncovered line)
1
//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements NVPTX TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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13
#include "NVPTX.h"
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#include "Targets.h"
15
#include "clang/Basic/Builtins.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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20
using namespace clang;
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using namespace clang::targets;
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const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS)                                               \
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  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
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  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
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  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsNVPTX.def"
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};
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const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
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NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
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                                 const TargetOptions &Opts,
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                                 unsigned TargetPointerWidth)
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    : TargetInfo(Triple) {
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  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
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         "NVPTX only supports 32- and 64-bit modes.");
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0
  PTXVersion = 32;
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  for (const StringRef Feature : Opts.FeaturesAsWritten) {
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11
    if (!Feature.startswith("+ptx"))
45
0
      continue;
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11
    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
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11
                     .Case("+ptx75", 75)
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11
                     .Case("+ptx74", 74)
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11
                     .Case("+ptx73", 73)
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11
                     .Case("+ptx72", 72)
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11
                     .Case("+ptx71", 71)
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11
                     .Case("+ptx70", 70)
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11
                     .Case("+ptx65", 65)
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11
                     .Case("+ptx64", 64)
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11
                     .Case("+ptx63", 63)
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11
                     .Case("+ptx61", 61)
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11
                     .Case("+ptx60", 60)
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11
                     .Case("+ptx50", 50)
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11
                     .Case("+ptx43", 43)
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11
                     .Case("+ptx42", 42)
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11
                     .Case("+ptx41", 41)
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                     .Case("+ptx40", 40)
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                     .Case("+ptx32", 32)
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11
                     .Default(32);
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  }
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  TLSSupported = false;
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308
  VLASupported = false;
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308
  AddrSpaceMap = &NVPTXAddrSpaceMap;
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  UseAddrSpaceMapMangling = true;
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  // Define available target features
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  // These must be defined in sorted order!
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  NoAsmVariants = true;
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  GPU = CudaArch::SM_20;
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  if (TargetPointerWidth == 32)
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    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else if (Opts.NVPTXUseShortPointers)
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0
    resetDataLayout(
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        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else
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    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  // If possible, get a TargetInfo for our host triple, so we can match its
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  // types.
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  llvm::Triple HostTriple(Opts.HostTriple);
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  if (!HostTriple.isNVPTX())
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    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
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  // If no host target, make some guesses about the data layout and return.
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  if (!HostTarget) {
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    LongWidth = LongAlign = TargetPointerWidth;
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    PointerWidth = PointerAlign = TargetPointerWidth;
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    switch (TargetPointerWidth) {
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    case 32:
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      SizeType = TargetInfo::UnsignedInt;
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      PtrDiffType = TargetInfo::SignedInt;
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      IntPtrType = TargetInfo::SignedInt;
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      break;
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    case 64:
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      SizeType = TargetInfo::UnsignedLong;
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      PtrDiffType = TargetInfo::SignedLong;
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      IntPtrType = TargetInfo::SignedLong;
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      break;
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0
    default:
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0
      llvm_unreachable("TargetPointerWidth must be 32 or 64");
108
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    }
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231
    return;
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  }
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  // Copy properties from host target.
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  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
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  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
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  BoolWidth = HostTarget->getBoolWidth();
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  BoolAlign = HostTarget->getBoolAlign();
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  IntWidth = HostTarget->getIntWidth();
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  IntAlign = HostTarget->getIntAlign();
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  HalfWidth = HostTarget->getHalfWidth();
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  HalfAlign = HostTarget->getHalfAlign();
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  FloatWidth = HostTarget->getFloatWidth();
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  FloatAlign = HostTarget->getFloatAlign();
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  DoubleWidth = HostTarget->getDoubleWidth();
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  DoubleAlign = HostTarget->getDoubleAlign();
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  LongWidth = HostTarget->getLongWidth();
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  LongAlign = HostTarget->getLongAlign();
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  LongLongWidth = HostTarget->getLongLongWidth();
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  LongLongAlign = HostTarget->getLongLongAlign();
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  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
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  NewAlign = HostTarget->getNewAlign();
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  DefaultAlignForAttributeAligned =
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      HostTarget->getDefaultAlignForAttributeAligned();
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  SizeType = HostTarget->getSizeType();
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  IntMaxType = HostTarget->getIntMaxType();
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  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
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  IntPtrType = HostTarget->getIntPtrType();
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  WCharType = HostTarget->getWCharType();
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  WIntType = HostTarget->getWIntType();
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  Char16Type = HostTarget->getChar16Type();
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  Char32Type = HostTarget->getChar32Type();
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  Int64Type = HostTarget->getInt64Type();
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  SigAtomicType = HostTarget->getSigAtomicType();
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  ProcessIDType = HostTarget->getProcessIDType();
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  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
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  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
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  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
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  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
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  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
151
  // we need those macros to be identical on host and device, because (among
152
  // other things) they affect which standard library classes are defined, and
153
  // we need all classes to be defined on both the host and device.
154
77
  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
155
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  // Properties intentionally not copied from host:
157
  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
158
  //   host/device boundary.
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  // - SuitableAlign: Not visible across the host/device boundary, and may
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  //   correctly be different on host/device, e.g. if host has wider vector
161
  //   types than device.
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  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
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  //   as its double type, but that's not necessarily true on the host.
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  //   TODO: nvcc emits a warning when using long double on device; we should
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  //   do the same.
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}
Unexecuted instantiation: clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
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Source
38
308
    : TargetInfo(Triple) {
39
308
  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
40
308
         "NVPTX only supports 32- and 64-bit modes.");
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42
0
  PTXVersion = 32;
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308
  for (const StringRef Feature : Opts.FeaturesAsWritten) {
44
11
    if (!Feature.startswith("+ptx"))
45
0
      continue;
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11
    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
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                     .Case("+ptx75", 75)
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11
                     .Case("+ptx74", 74)
49
11
                     .Case("+ptx73", 73)
50
11
                     .Case("+ptx72", 72)
51
11
                     .Case("+ptx71", 71)
52
11
                     .Case("+ptx70", 70)
53
11
                     .Case("+ptx65", 65)
54
11
                     .Case("+ptx64", 64)
55
11
                     .Case("+ptx63", 63)
56
11
                     .Case("+ptx61", 61)
57
11
                     .Case("+ptx60", 60)
58
11
                     .Case("+ptx50", 50)
59
11
                     .Case("+ptx43", 43)
60
11
                     .Case("+ptx42", 42)
61
11
                     .Case("+ptx41", 41)
62
11
                     .Case("+ptx40", 40)
63
11
                     .Case("+ptx32", 32)
64
11
                     .Default(32);
65
11
  }
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308
  TLSSupported = false;
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  VLASupported = false;
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  AddrSpaceMap = &NVPTXAddrSpaceMap;
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  UseAddrSpaceMapMangling = true;
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  // Define available target features
73
  // These must be defined in sorted order!
74
308
  NoAsmVariants = true;
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308
  GPU = CudaArch::SM_20;
76
77
308
  if (TargetPointerWidth == 32)
78
137
    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
79
171
  else if (Opts.NVPTXUseShortPointers)
80
0
    resetDataLayout(
81
0
        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
82
171
  else
83
171
    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
84
85
  // If possible, get a TargetInfo for our host triple, so we can match its
86
  // types.
87
308
  llvm::Triple HostTriple(Opts.HostTriple);
88
308
  if (!HostTriple.isNVPTX())
89
308
    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
90
91
  // If no host target, make some guesses about the data layout and return.
92
308
  if (!HostTarget) {
93
231
    LongWidth = LongAlign = TargetPointerWidth;
94
231
    PointerWidth = PointerAlign = TargetPointerWidth;
95
231
    switch (TargetPointerWidth) {
96
122
    case 32:
97
122
      SizeType = TargetInfo::UnsignedInt;
98
122
      PtrDiffType = TargetInfo::SignedInt;
99
122
      IntPtrType = TargetInfo::SignedInt;
100
122
      break;
101
109
    case 64:
102
109
      SizeType = TargetInfo::UnsignedLong;
103
109
      PtrDiffType = TargetInfo::SignedLong;
104
109
      IntPtrType = TargetInfo::SignedLong;
105
109
      break;
106
0
    default:
107
0
      llvm_unreachable("TargetPointerWidth must be 32 or 64");
108
231
    }
109
231
    return;
110
231
  }
111
112
  // Copy properties from host target.
113
77
  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
114
77
  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
115
77
  BoolWidth = HostTarget->getBoolWidth();
116
77
  BoolAlign = HostTarget->getBoolAlign();
117
77
  IntWidth = HostTarget->getIntWidth();
118
77
  IntAlign = HostTarget->getIntAlign();
119
77
  HalfWidth = HostTarget->getHalfWidth();
120
77
  HalfAlign = HostTarget->getHalfAlign();
121
77
  FloatWidth = HostTarget->getFloatWidth();
122
77
  FloatAlign = HostTarget->getFloatAlign();
123
77
  DoubleWidth = HostTarget->getDoubleWidth();
124
77
  DoubleAlign = HostTarget->getDoubleAlign();
125
77
  LongWidth = HostTarget->getLongWidth();
126
77
  LongAlign = HostTarget->getLongAlign();
127
77
  LongLongWidth = HostTarget->getLongLongWidth();
128
77
  LongLongAlign = HostTarget->getLongLongAlign();
129
77
  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
130
77
  NewAlign = HostTarget->getNewAlign();
131
77
  DefaultAlignForAttributeAligned =
132
77
      HostTarget->getDefaultAlignForAttributeAligned();
133
77
  SizeType = HostTarget->getSizeType();
134
77
  IntMaxType = HostTarget->getIntMaxType();
135
77
  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
136
77
  IntPtrType = HostTarget->getIntPtrType();
137
77
  WCharType = HostTarget->getWCharType();
138
77
  WIntType = HostTarget->getWIntType();
139
77
  Char16Type = HostTarget->getChar16Type();
140
77
  Char32Type = HostTarget->getChar32Type();
141
77
  Int64Type = HostTarget->getInt64Type();
142
77
  SigAtomicType = HostTarget->getSigAtomicType();
143
77
  ProcessIDType = HostTarget->getProcessIDType();
144
145
77
  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
146
77
  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
147
77
  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
148
77
  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
149
150
  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
151
  // we need those macros to be identical on host and device, because (among
152
  // other things) they affect which standard library classes are defined, and
153
  // we need all classes to be defined on both the host and device.
154
77
  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
155
156
  // Properties intentionally not copied from host:
157
  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
158
  //   host/device boundary.
159
  // - SuitableAlign: Not visible across the host/device boundary, and may
160
  //   correctly be different on host/device, e.g. if host has wider vector
161
  //   types than device.
162
  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
163
  //   as its double type, but that's not necessarily true on the host.
164
  //   TODO: nvcc emits a warning when using long double on device; we should
165
  //   do the same.
166
77
}
167
168
0
ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
169
0
  return llvm::makeArrayRef(GCCRegNames);
170
0
}
171
172
225
bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
173
225
  return llvm::StringSwitch<bool>(Feature)
174
225
      .Cases("ptx", "nvptx", true)
175
225
      .Default(false);
176
225
}
177
178
void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
179
307
                                       MacroBuilder &Builder) const {
180
307
  Builder.defineMacro("__PTX__");
181
307
  Builder.defineMacro("__NVPTX__");
182
307
  if (Opts.CUDAIsDevice) {
183
    // Set __CUDA_ARCH__ for the GPU specified.
184
78
    std::string CUDAArchCode = [this] {
185
78
      switch (GPU) {
186
0
      case CudaArch::GFX600:
187
0
      case CudaArch::GFX601:
188
0
      case CudaArch::GFX602:
189
0
      case CudaArch::GFX700:
190
0
      case CudaArch::GFX701:
191
0
      case CudaArch::GFX702:
192
0
      case CudaArch::GFX703:
193
0
      case CudaArch::GFX704:
194
0
      case CudaArch::GFX705:
195
0
      case CudaArch::GFX801:
196
0
      case CudaArch::GFX802:
197
0
      case CudaArch::GFX803:
198
0
      case CudaArch::GFX805:
199
0
      case CudaArch::GFX810:
200
0
      case CudaArch::GFX900:
201
0
      case CudaArch::GFX902:
202
0
      case CudaArch::GFX904:
203
0
      case CudaArch::GFX906:
204
0
      case CudaArch::GFX908:
205
0
      case CudaArch::GFX909:
206
0
      case CudaArch::GFX90a:
207
0
      case CudaArch::GFX90c:
208
0
      case CudaArch::GFX1010:
209
0
      case CudaArch::GFX1011:
210
0
      case CudaArch::GFX1012:
211
0
      case CudaArch::GFX1013:
212
0
      case CudaArch::GFX1030:
213
0
      case CudaArch::GFX1031:
214
0
      case CudaArch::GFX1032:
215
0
      case CudaArch::GFX1033:
216
0
      case CudaArch::GFX1034:
217
0
      case CudaArch::GFX1035:
218
0
      case CudaArch::Generic:
219
0
      case CudaArch::LAST:
220
0
        break;
221
0
      case CudaArch::UNUSED:
222
0
      case CudaArch::UNKNOWN:
223
0
        assert(false && "No GPU arch when compiling CUDA device code.");
224
0
        return "";
225
51
      case CudaArch::SM_20:
226
51
        return "200";
227
0
      case CudaArch::SM_21:
228
0
        return "210";
229
0
      case CudaArch::SM_30:
230
0
        return "300";
231
0
      case CudaArch::SM_32:
232
0
        return "320";
233
12
      case CudaArch::SM_35:
234
12
        return "350";
235
0
      case CudaArch::SM_37:
236
0
        return "370";
237
1
      case CudaArch::SM_50:
238
1
        return "500";
239
0
      case CudaArch::SM_52:
240
0
        return "520";
241
0
      case CudaArch::SM_53:
242
0
        return "530";
243
5
      case CudaArch::SM_60:
244
5
        return "600";
245
0
      case CudaArch::SM_61:
246
0
        return "610";
247
0
      case CudaArch::SM_62:
248
0
        return "620";
249
3
      case CudaArch::SM_70:
250
3
        return "700";
251
0
      case CudaArch::SM_72:
252
0
        return "720";
253
0
      case CudaArch::SM_75:
254
0
        return "750";
255
5
      case CudaArch::SM_80:
256
5
        return "800";
257
1
      case CudaArch::SM_86:
258
1
        return "860";
259
78
      }
260
0
      llvm_unreachable("unhandled CudaArch");
261
0
    }();
262
78
    Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
263
78
  }
264
307
}
265
266
307
ArrayRef<Builtin::Info> NVPTXTargetInfo::getTargetBuiltins() const {
267
307
  return llvm::makeArrayRef(BuiltinInfo, clang::NVPTX::LastTSBuiltin -
268
307
                                             Builtin::FirstTSBuiltin);
269
307
}