Coverage Report

Created: 2020-09-19 12:23

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp
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//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements NVPTX TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "Targets.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Frontend/OpenMP/OMPGridValues.h"
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using namespace clang;
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using namespace clang::targets;
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const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS)                                               \
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  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
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  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
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  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsNVPTX.def"
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};
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const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
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NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
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                                 const TargetOptions &Opts,
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                                 unsigned TargetPointerWidth)
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    : TargetInfo(Triple) {
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  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
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         "NVPTX only supports 32- and 64-bit modes.");
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  PTXVersion = 32;
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  for (const StringRef Feature : Opts.FeaturesAsWritten) {
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8
    if (!Feature.startswith("+ptx"))
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0
      continue;
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    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
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8
                     .Case("+ptx70", 70)
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                     .Case("+ptx65", 65)
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                     .Case("+ptx64", 64)
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8
                     .Case("+ptx63", 63)
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8
                     .Case("+ptx61", 61)
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                     .Case("+ptx60", 60)
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                     .Case("+ptx50", 50)
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8
                     .Case("+ptx43", 43)
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                     .Case("+ptx42", 42)
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                     .Case("+ptx41", 41)
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                     .Case("+ptx40", 40)
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                     .Case("+ptx32", 32)
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                     .Default(32);
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  }
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  TLSSupported = false;
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  VLASupported = false;
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  AddrSpaceMap = &NVPTXAddrSpaceMap;
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  GridValues = llvm::omp::NVPTXGpuGridValues;
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  UseAddrSpaceMapMangling = true;
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  // Define available target features
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  // These must be defined in sorted order!
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  NoAsmVariants = true;
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  GPU = CudaArch::SM_20;
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  if (TargetPointerWidth == 32)
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    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else if (Opts.NVPTXUseShortPointers)
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    resetDataLayout(
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        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else
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    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  // If possible, get a TargetInfo for our host triple, so we can match its
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  // types.
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  llvm::Triple HostTriple(Opts.HostTriple);
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  if (!HostTriple.isNVPTX())
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    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
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  // If no host target, make some guesses about the data layout and return.
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  if (!HostTarget) {
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    LongWidth = LongAlign = TargetPointerWidth;
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    PointerWidth = PointerAlign = TargetPointerWidth;
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    switch (TargetPointerWidth) {
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    case 32:
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      SizeType = TargetInfo::UnsignedInt;
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      PtrDiffType = TargetInfo::SignedInt;
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      IntPtrType = TargetInfo::SignedInt;
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      break;
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    case 64:
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      SizeType = TargetInfo::UnsignedLong;
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      PtrDiffType = TargetInfo::SignedLong;
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      IntPtrType = TargetInfo::SignedLong;
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      break;
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    default:
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      llvm_unreachable("TargetPointerWidth must be 32 or 64");
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    }
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    return;
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  }
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  // Copy properties from host target.
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  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
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  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
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  BoolWidth = HostTarget->getBoolWidth();
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  BoolAlign = HostTarget->getBoolAlign();
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  IntWidth = HostTarget->getIntWidth();
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  IntAlign = HostTarget->getIntAlign();
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  HalfWidth = HostTarget->getHalfWidth();
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  HalfAlign = HostTarget->getHalfAlign();
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  FloatWidth = HostTarget->getFloatWidth();
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  FloatAlign = HostTarget->getFloatAlign();
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  DoubleWidth = HostTarget->getDoubleWidth();
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  DoubleAlign = HostTarget->getDoubleAlign();
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  LongWidth = HostTarget->getLongWidth();
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  LongAlign = HostTarget->getLongAlign();
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  LongLongWidth = HostTarget->getLongLongWidth();
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  LongLongAlign = HostTarget->getLongLongAlign();
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  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
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  NewAlign = HostTarget->getNewAlign();
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  DefaultAlignForAttributeAligned =
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      HostTarget->getDefaultAlignForAttributeAligned();
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  SizeType = HostTarget->getSizeType();
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  IntMaxType = HostTarget->getIntMaxType();
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  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
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  IntPtrType = HostTarget->getIntPtrType();
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  WCharType = HostTarget->getWCharType();
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  WIntType = HostTarget->getWIntType();
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  Char16Type = HostTarget->getChar16Type();
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  Char32Type = HostTarget->getChar32Type();
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  Int64Type = HostTarget->getInt64Type();
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  SigAtomicType = HostTarget->getSigAtomicType();
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  ProcessIDType = HostTarget->getProcessIDType();
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  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
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  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
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  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
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  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
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  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
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  // we need those macros to be identical on host and device, because (among
149
  // other things) they affect which standard library classes are defined, and
150
  // we need all classes to be defined on both the host and device.
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  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
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  // Properties intentionally not copied from host:
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  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
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  //   host/device boundary.
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  // - SuitableAlign: Not visible across the host/device boundary, and may
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  //   correctly be different on host/device, e.g. if host has wider vector
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  //   types than device.
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  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
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  //   as its double type, but that's not necessarily true on the host.
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  //   TODO: nvcc emits a warning when using long double on device; we should
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  //   do the same.
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}
Unexecuted instantiation: clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
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Source
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    : TargetInfo(Triple) {
40
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  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
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         "NVPTX only supports 32- and 64-bit modes.");
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  PTXVersion = 32;
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  for (const StringRef Feature : Opts.FeaturesAsWritten) {
45
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    if (!Feature.startswith("+ptx"))
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0
      continue;
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    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
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                     .Case("+ptx70", 70)
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                     .Case("+ptx65", 65)
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                     .Case("+ptx64", 64)
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                     .Case("+ptx63", 63)
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                     .Case("+ptx61", 61)
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                     .Case("+ptx60", 60)
54
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                     .Case("+ptx50", 50)
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                     .Case("+ptx43", 43)
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                     .Case("+ptx42", 42)
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                     .Case("+ptx41", 41)
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                     .Case("+ptx40", 40)
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                     .Case("+ptx32", 32)
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                     .Default(32);
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  }
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63
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  TLSSupported = false;
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  VLASupported = false;
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  AddrSpaceMap = &NVPTXAddrSpaceMap;
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  GridValues = llvm::omp::NVPTXGpuGridValues;
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  UseAddrSpaceMapMangling = true;
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  // Define available target features
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  // These must be defined in sorted order!
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  NoAsmVariants = true;
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  GPU = CudaArch::SM_20;
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74
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  if (TargetPointerWidth == 32)
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    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else if (Opts.NVPTXUseShortPointers)
77
0
    resetDataLayout(
78
0
        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else
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    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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424
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  // If possible, get a TargetInfo for our host triple, so we can match its
83
  // types.
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  llvm::Triple HostTriple(Opts.HostTriple);
85
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  if (!HostTriple.isNVPTX())
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    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
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  // If no host target, make some guesses about the data layout and return.
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  if (!HostTarget) {
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    LongWidth = LongAlign = TargetPointerWidth;
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    PointerWidth = PointerAlign = TargetPointerWidth;
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    switch (TargetPointerWidth) {
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    case 32:
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      SizeType = TargetInfo::UnsignedInt;
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      PtrDiffType = TargetInfo::SignedInt;
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      IntPtrType = TargetInfo::SignedInt;
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      break;
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    case 64:
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146
      SizeType = TargetInfo::UnsignedLong;
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      PtrDiffType = TargetInfo::SignedLong;
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      IntPtrType = TargetInfo::SignedLong;
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      break;
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0
    default:
104
0
      llvm_unreachable("TargetPointerWidth must be 32 or 64");
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312
    }
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    return;
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  }
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112
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  // Copy properties from host target.
110
112
  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
111
112
  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
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  BoolWidth = HostTarget->getBoolWidth();
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  BoolAlign = HostTarget->getBoolAlign();
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  IntWidth = HostTarget->getIntWidth();
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  IntAlign = HostTarget->getIntAlign();
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  HalfWidth = HostTarget->getHalfWidth();
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  HalfAlign = HostTarget->getHalfAlign();
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  FloatWidth = HostTarget->getFloatWidth();
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  FloatAlign = HostTarget->getFloatAlign();
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  DoubleWidth = HostTarget->getDoubleWidth();
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  DoubleAlign = HostTarget->getDoubleAlign();
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  LongWidth = HostTarget->getLongWidth();
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  LongAlign = HostTarget->getLongAlign();
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112
  LongLongWidth = HostTarget->getLongLongWidth();
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  LongLongAlign = HostTarget->getLongLongAlign();
126
112
  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
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112
  NewAlign = HostTarget->getNewAlign();
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112
  DefaultAlignForAttributeAligned =
129
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      HostTarget->getDefaultAlignForAttributeAligned();
130
112
  SizeType = HostTarget->getSizeType();
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  IntMaxType = HostTarget->getIntMaxType();
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112
  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
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  IntPtrType = HostTarget->getIntPtrType();
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  WCharType = HostTarget->getWCharType();
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  WIntType = HostTarget->getWIntType();
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112
  Char16Type = HostTarget->getChar16Type();
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112
  Char32Type = HostTarget->getChar32Type();
138
112
  Int64Type = HostTarget->getInt64Type();
139
112
  SigAtomicType = HostTarget->getSigAtomicType();
140
112
  ProcessIDType = HostTarget->getProcessIDType();
141
112
142
112
  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
143
112
  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
144
112
  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
145
112
  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
146
112
147
  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
148
  // we need those macros to be identical on host and device, because (among
149
  // other things) they affect which standard library classes are defined, and
150
  // we need all classes to be defined on both the host and device.
151
112
  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
152
112
153
  // Properties intentionally not copied from host:
154
  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
155
  //   host/device boundary.
156
  // - SuitableAlign: Not visible across the host/device boundary, and may
157
  //   correctly be different on host/device, e.g. if host has wider vector
158
  //   types than device.
159
  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
160
  //   as its double type, but that's not necessarily true on the host.
161
  //   TODO: nvcc emits a warning when using long double on device; we should
162
  //   do the same.
163
112
}
164
165
33
ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
166
33
  return llvm::makeArrayRef(GCCRegNames);
167
33
}
168
169
17
bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
170
17
  return llvm::StringSwitch<bool>(Feature)
171
17
      .Cases("ptx", "nvptx", true)
172
17
      .Default(false);
173
17
}
174
175
void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
176
422
                                       MacroBuilder &Builder) const {
177
422
  Builder.defineMacro("__PTX__");
178
422
  Builder.defineMacro("__NVPTX__");
179
422
  if (Opts.CUDAIsDevice) {
180
    // Set __CUDA_ARCH__ for the GPU specified.
181
114
    std::string CUDAArchCode = [this] {
182
114
      switch (GPU) {
183
0
      case CudaArch::GFX600:
184
0
      case CudaArch::GFX601:
185
0
      case CudaArch::GFX700:
186
0
      case CudaArch::GFX701:
187
0
      case CudaArch::GFX702:
188
0
      case CudaArch::GFX703:
189
0
      case CudaArch::GFX704:
190
0
      case CudaArch::GFX801:
191
0
      case CudaArch::GFX802:
192
0
      case CudaArch::GFX803:
193
0
      case CudaArch::GFX810:
194
0
      case CudaArch::GFX900:
195
0
      case CudaArch::GFX902:
196
0
      case CudaArch::GFX904:
197
0
      case CudaArch::GFX906:
198
0
      case CudaArch::GFX908:
199
0
      case CudaArch::GFX909:
200
0
      case CudaArch::GFX1010:
201
0
      case CudaArch::GFX1011:
202
0
      case CudaArch::GFX1012:
203
0
      case CudaArch::GFX1030:
204
0
      case CudaArch::GFX1031:
205
0
      case CudaArch::LAST:
206
0
        break;
207
0
      case CudaArch::UNKNOWN:
208
0
        assert(false && "No GPU arch when compiling CUDA device code.");
209
0
        return "";
210
90
      case CudaArch::SM_20:
211
90
        return "200";
212
0
      case CudaArch::SM_21:
213
0
        return "210";
214
2
      case CudaArch::SM_30:
215
2
        return "300";
216
0
      case CudaArch::SM_32:
217
0
        return "320";
218
5
      case CudaArch::SM_35:
219
5
        return "350";
220
0
      case CudaArch::SM_37:
221
0
        return "370";
222
1
      case CudaArch::SM_50:
223
1
        return "500";
224
0
      case CudaArch::SM_52:
225
0
        return "520";
226
1
      case CudaArch::SM_53:
227
1
        return "530";
228
8
      case CudaArch::SM_60:
229
8
        return "600";
230
1
      case CudaArch::SM_61:
231
1
        return "610";
232
0
      case CudaArch::SM_62:
233
0
        return "620";
234
3
      case CudaArch::SM_70:
235
3
        return "700";
236
0
      case CudaArch::SM_72:
237
0
        return "720";
238
1
      case CudaArch::SM_75:
239
1
        return "750";
240
2
      case CudaArch::SM_80:
241
2
        return "800";
242
0
      }
243
0
      llvm_unreachable("unhandled CudaArch");
244
0
    }();
245
114
    Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
246
114
  }
247
422
}
248
249
422
ArrayRef<Builtin::Info> NVPTXTargetInfo::getTargetBuiltins() const {
250
422
  return llvm::makeArrayRef(BuiltinInfo, clang::NVPTX::LastTSBuiltin -
251
422
                                             Builtin::FirstTSBuiltin);
252
422
}