Coverage Report

Created: 2020-02-25 14:32

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/NVPTX.h
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//===--- NVPTX.h - Declare NVPTX target feature support ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares NVPTX TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H
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#include "clang/Basic/Cuda.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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namespace clang {
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namespace targets {
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static const unsigned NVPTXAddrSpaceMap[] = {
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    0, // Default
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    1, // opencl_global
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    3, // opencl_local
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    4, // opencl_constant
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    0, // opencl_private
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    // FIXME: generic has to be added to the target
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    0, // opencl_generic
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    1, // cuda_device
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    4, // cuda_constant
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    3, // cuda_shared
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    0, // ptr32_sptr
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    0, // ptr32_uptr
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    0  // ptr64
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};
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/// The DWARF address class. Taken from
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/// https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf
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static const int NVPTXDWARFAddrSpaceMap[] = {
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    -1, // Default, opencl_private or opencl_generic - not defined
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    5,  // opencl_global
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    -1,
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    8,  // opencl_local or cuda_shared
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    4,  // opencl_constant or cuda_constant
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};
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class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo {
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  static const char *const GCCRegNames[];
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  static const Builtin::Info BuiltinInfo[];
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  CudaArch GPU;
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  uint32_t PTXVersion;
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  std::unique_ptr<TargetInfo> HostTarget;
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public:
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  NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
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                  unsigned TargetPointerWidth);
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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  bool
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  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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                 StringRef CPU,
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1.89k
                 const std::vector<std::string> &FeaturesVec) const override {
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    Features[CudaArchToString(GPU)] = true;
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    Features["ptx" + std::to_string(PTXVersion)] = true;
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    return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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  }
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  bool hasFeature(StringRef Feature) const override;
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  ArrayRef<const char *> getGCCRegNames() const override;
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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    // No aliases.
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    return None;
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  }
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  bool validateAsmConstraint(const char *&Name,
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                             TargetInfo::ConstraintInfo &Info) const override {
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    switch (*Name) {
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    default:
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      return false;
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    case 'c':
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    case 'h':
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    case 'r':
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    case 'l':
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    case 'f':
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    case 'd':
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      Info.setAllowsRegister();
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      return true;
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    }
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  }
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  const char *getClobbers() const override {
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    // FIXME: Is this really right?
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    return "";
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  }
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  BuiltinVaListKind getBuiltinVaListKind() const override {
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    // FIXME: implement
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    return TargetInfo::CharPtrBuiltinVaList;
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  }
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  bool isValidCPUName(StringRef Name) const override {
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    return StringToCudaArch(Name) != CudaArch::UNKNOWN;
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  }
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  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
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    for (int i = static_cast<int>(CudaArch::SM_20);
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         i < static_cast<int>(CudaArch::LAST); 
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)
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      Values.emplace_back(CudaArchToString(static_cast<CudaArch>(i)));
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  }
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  bool setCPU(const std::string &Name) override {
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    GPU = StringToCudaArch(Name);
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    return GPU != CudaArch::UNKNOWN;
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  }
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  void setSupportedOpenCLOpts() override {
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    auto &Opts = getSupportedOpenCLOpts();
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    Opts.support("cl_clang_storage_class_specifiers");
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    Opts.support("cl_khr_gl_sharing");
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    Opts.support("cl_khr_icd");
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    Opts.support("cl_khr_fp64");
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    Opts.support("cl_khr_byte_addressable_store");
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    Opts.support("cl_khr_global_int32_base_atomics");
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    Opts.support("cl_khr_global_int32_extended_atomics");
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    Opts.support("cl_khr_local_int32_base_atomics");
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    Opts.support("cl_khr_local_int32_extended_atomics");
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  }
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  /// \returns If a target requires an address within a target specific address
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  /// space \p AddressSpace to be converted in order to be used, then return the
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  /// corresponding target specific DWARF address space.
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  ///
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  /// \returns Otherwise return None and no conversion will be emitted in the
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  /// DWARF.
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  Optional<unsigned>
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  getDWARFAddressSpace(unsigned AddressSpace) const override {
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    if (AddressSpace >= llvm::array_lengthof(NVPTXDWARFAddrSpaceMap) ||
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NVPTXDWARFAddrSpaceMap[AddressSpace] < 0241
)
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      return llvm::None;
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    return NVPTXDWARFAddrSpaceMap[AddressSpace];
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  }
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  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
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    // CUDA compilations support all of the host's calling conventions.
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    //
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    // TODO: We should warn if you apply a non-default CC to anything other than
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    // a host function.
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    if (HostTarget)
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      return HostTarget->checkCallingConvention(CC);
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    return CCCR_Warning;
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  }
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_NVPTX_H