Coverage Report

Created: 2022-01-18 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/PPC.cpp
Line
Count
Source (jump to first uncovered line)
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//===--- PPC.cpp - Implement PPC target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
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13
#include "PPC.h"
14
#include "clang/Basic/Diagnostic.h"
15
#include "clang/Basic/MacroBuilder.h"
16
#include "clang/Basic/TargetBuiltins.h"
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18
using namespace clang;
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using namespace clang::targets;
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const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS)                                               \
23
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
25
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
26
#include "clang/Basic/BuiltinsPPC.def"
27
};
28
29
/// handleTargetFeatures - Perform initialization based on the user
30
/// configured set of features.
31
bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
32
4.04k
                                         DiagnosticsEngine &Diags) {
33
4.04k
  FloatABI = HardFloat;
34
60.9k
  for (const auto &Feature : Features) {
35
60.9k
    if (Feature == "+altivec") {
36
269
      HasAltivec = true;
37
60.6k
    } else if (Feature == "+vsx") {
38
202
      HasVSX = true;
39
60.4k
    } else if (Feature == "+bpermd") {
40
168
      HasBPERMD = true;
41
60.3k
    } else if (Feature == "+extdiv") {
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168
      HasExtDiv = true;
43
60.1k
    } else if (Feature == "+power8-vector") {
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123
      HasP8Vector = true;
45
60.0k
    } else if (Feature == "+crypto") {
46
124
      HasP8Crypto = true;
47
59.9k
    } else if (Feature == "+direct-move") {
48
123
      HasDirectMove = true;
49
59.7k
    } else if (Feature == "+htm") {
50
87
      HasHTM = true;
51
59.6k
    } else if (Feature == "+float128") {
52
18
      HasFloat128 = true;
53
59.6k
    } else if (Feature == "+power9-vector") {
54
68
      HasP9Vector = true;
55
59.6k
    } else if (Feature == "+power10-vector") {
56
39
      HasP10Vector = true;
57
59.5k
    } else if (Feature == "+pcrelative-memops") {
58
40
      HasPCRelativeMemops = true;
59
59.5k
    } else if (Feature == "+prefix-instrs") {
60
40
      HasPrefixInstrs = true;
61
59.4k
    } else if (Feature == "+spe" || 
Feature == "+efpu2"59.4k
) {
62
2
      HasStrictFP = false;
63
2
      HasSPE = true;
64
2
      LongDoubleWidth = LongDoubleAlign = 64;
65
2
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
66
59.4k
    } else if (Feature == "-hard-float") {
67
2
      FloatABI = SoftFloat;
68
59.4k
    } else if (Feature == "+paired-vector-memops") {
69
40
      PairedVectorMemops = true;
70
59.4k
    } else if (Feature == "+mma") {
71
40
      HasMMA = true;
72
59.4k
    } else if (Feature == "+rop-protect") {
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9
      HasROPProtect = true;
74
59.3k
    } else if (Feature == "+privileged") {
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6
      HasPrivileged = true;
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59.3k
    } else if (Feature == "+isa-v206-instructions") {
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168
      IsISA2_06 = true;
78
59.2k
    } else if (Feature == "+isa-v207-instructions") {
79
124
      IsISA2_07 = true;
80
59.0k
    } else if (Feature == "+isa-v30-instructions") {
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69
      IsISA3_0 = true;
82
59.0k
    } else if (Feature == "+isa-v31-instructions") {
83
41
      IsISA3_1 = true;
84
41
    }
85
    // TODO: Finish this list and add an assert that we've handled them
86
    // all.
87
60.9k
  }
88
89
4.04k
  return true;
90
4.04k
}
91
92
493
static void defineXLCompatMacros(MacroBuilder &Builder) {
93
493
  Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
94
493
  Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
95
493
  Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
96
493
  Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
97
493
  Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
98
493
  Builder.defineMacro("__isync", "__builtin_ppc_isync");
99
493
  Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
100
493
  Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
101
493
  Builder.defineMacro("__sync", "__builtin_ppc_sync");
102
493
  Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
103
493
  Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
104
493
  Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
105
493
  Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
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493
  Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
107
493
  Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
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493
  Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
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493
  Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
110
493
  Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
111
493
  Builder.defineMacro("__compare_and_swaplp",
112
493
                      "__builtin_ppc_compare_and_swaplp");
113
493
  Builder.defineMacro("__fetch_and_add", "__builtin_ppc_fetch_and_add");
114
493
  Builder.defineMacro("__fetch_and_addlp", "__builtin_ppc_fetch_and_addlp");
115
493
  Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and");
116
493
  Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp");
117
493
  Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or");
118
493
  Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
119
493
  Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
120
493
  Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
121
493
  Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
122
493
  Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
123
493
  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
124
493
  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
125
493
  Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw");
126
493
  Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
127
493
  Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
128
493
  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
129
493
  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
130
493
  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
131
493
  Builder.defineMacro("__tw", "__builtin_ppc_tw");
132
493
  Builder.defineMacro("__trap", "__builtin_ppc_trap");
133
493
  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
134
493
  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
135
493
  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
136
493
  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
137
493
  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
138
493
  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
139
493
  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
140
493
  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
141
493
  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
142
493
  Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
143
493
  Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
144
493
  Builder.defineMacro("__setb", "__builtin_ppc_setb");
145
493
  Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
146
493
  Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
147
493
  Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
148
493
  Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
149
493
  Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
150
493
  Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
151
493
  Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
152
493
  Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
153
493
  Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
154
493
  Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
155
493
  Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
156
493
  Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
157
493
  Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
158
493
  Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
159
493
  Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
160
493
  Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
161
493
  Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
162
493
  Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp");
163
493
  Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig");
164
493
  Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0");
165
493
  Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1");
166
493
  Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf");
167
493
  Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi");
168
493
  Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp");
169
493
  Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub");
170
493
  Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs");
171
493
  Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd");
172
493
  Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds");
173
493
  Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub");
174
493
  Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
175
493
  Builder.defineMacro("__fre", "__builtin_ppc_fre");
176
493
  Builder.defineMacro("__fres", "__builtin_ppc_fres");
177
493
  Builder.defineMacro("__swdiv_nochk", "__builtin_ppc_swdiv_nochk");
178
493
  Builder.defineMacro("__swdivs_nochk", "__builtin_ppc_swdivs_nochk");
179
493
  Builder.defineMacro("__alloca", "__builtin_alloca");
180
493
  Builder.defineMacro("__vcipher", "__builtin_altivec_crypto_vcipher");
181
493
  Builder.defineMacro("__vcipherlast", "__builtin_altivec_crypto_vcipherlast");
182
493
  Builder.defineMacro("__vncipher", "__builtin_altivec_crypto_vncipher");
183
493
  Builder.defineMacro("__vncipherlast",
184
493
                      "__builtin_altivec_crypto_vncipherlast");
185
493
  Builder.defineMacro("__vpermxor", "__builtin_altivec_crypto_vpermxor");
186
493
  Builder.defineMacro("__vpmsumb", "__builtin_altivec_crypto_vpmsumb");
187
493
  Builder.defineMacro("__vpmsumd", "__builtin_altivec_crypto_vpmsumd");
188
493
  Builder.defineMacro("__vpmsumh", "__builtin_altivec_crypto_vpmsumh");
189
493
  Builder.defineMacro("__vpmsumw", "__builtin_altivec_crypto_vpmsumw");
190
493
  Builder.defineMacro("__divde", "__builtin_divde");
191
493
  Builder.defineMacro("__divwe", "__builtin_divwe");
192
493
  Builder.defineMacro("__divdeu", "__builtin_divdeu");
193
493
  Builder.defineMacro("__divweu", "__builtin_divweu");
194
493
  Builder.defineMacro("__alignx", "__builtin_ppc_alignx");
195
493
  Builder.defineMacro("__bcopy", "bcopy");
196
493
  Builder.defineMacro("__bpermd", "__builtin_bpermd");
197
493
  Builder.defineMacro("__cntlz4", "__builtin_clz");
198
493
  Builder.defineMacro("__cntlz8", "__builtin_clzll");
199
493
  Builder.defineMacro("__cmplx", "__builtin_complex");
200
493
  Builder.defineMacro("__cmplxf", "__builtin_complex");
201
493
  Builder.defineMacro("__cnttz4", "__builtin_ctz");
202
493
  Builder.defineMacro("__cnttz8", "__builtin_ctzll");
203
493
  Builder.defineMacro("__darn", "__builtin_darn");
204
493
  Builder.defineMacro("__darn_32", "__builtin_darn_32");
205
493
  Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
206
493
  Builder.defineMacro("__dcbf", "__builtin_dcbf");
207
493
  Builder.defineMacro("__fmadd", "__builtin_fma");
208
493
  Builder.defineMacro("__fmadds", "__builtin_fmaf");
209
493
  Builder.defineMacro("__labs", "__builtin_labs");
210
493
  Builder.defineMacro("__llabs", "__builtin_llabs");
211
493
  Builder.defineMacro("__popcnt4", "__builtin_popcount");
212
493
  Builder.defineMacro("__popcnt8", "__builtin_popcountll");
213
493
  Builder.defineMacro("__readflm", "__builtin_readflm");
214
493
  Builder.defineMacro("__rotatel4", "__builtin_rotateleft32");
215
493
  Builder.defineMacro("__rotatel8", "__builtin_rotateleft64");
216
493
  Builder.defineMacro("__rdlam", "__builtin_ppc_rdlam");
217
493
  Builder.defineMacro("__setflm", "__builtin_setflm");
218
493
  Builder.defineMacro("__setrnd", "__builtin_setrnd");
219
493
  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
220
493
  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
221
493
  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
222
493
  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
223
493
  Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr");
224
493
  Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
225
493
  Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr");
226
493
  Builder.defineMacro("__fric", "__builtin_ppc_fric");
227
493
  Builder.defineMacro("__frim", "__builtin_ppc_frim");
228
493
  Builder.defineMacro("__frims", "__builtin_ppc_frims");
229
493
  Builder.defineMacro("__frin", "__builtin_ppc_frin");
230
493
  Builder.defineMacro("__frins", "__builtin_ppc_frins");
231
493
  Builder.defineMacro("__frip", "__builtin_ppc_frip");
232
493
  Builder.defineMacro("__frips", "__builtin_ppc_frips");
233
493
  Builder.defineMacro("__friz", "__builtin_ppc_friz");
234
493
  Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
235
493
  Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
236
493
  Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
237
493
  Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
238
493
  Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
239
493
  Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
240
493
  Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
241
493
  Builder.defineMacro("__addex", "__builtin_ppc_addex");
242
493
  Builder.defineMacro("__cmplxl", "__builtin_complex");
243
493
  Builder.defineMacro("__compare_exp_uo", "__builtin_ppc_compare_exp_uo");
244
493
  Builder.defineMacro("__compare_exp_lt", "__builtin_ppc_compare_exp_lt");
245
493
  Builder.defineMacro("__compare_exp_gt", "__builtin_ppc_compare_exp_gt");
246
493
  Builder.defineMacro("__compare_exp_eq", "__builtin_ppc_compare_exp_eq");
247
493
  Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
248
493
  Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
249
493
  Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
250
493
}
251
252
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
253
/// #defines that are not tied to a specific subtarget.
254
void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
255
4.04k
                                     MacroBuilder &Builder) const {
256
257
  // We define the XLC compatibility macros only on AIX and Linux since XLC
258
  // was never available on any other platforms.
259
4.04k
  if (getTriple().isOSAIX() || 
getTriple().isOSLinux()3.83k
)
260
493
    defineXLCompatMacros(Builder);
261
262
  // Target identification.
263
4.04k
  Builder.defineMacro("__ppc__");
264
4.04k
  Builder.defineMacro("__PPC__");
265
4.04k
  Builder.defineMacro("_ARCH_PPC");
266
4.04k
  Builder.defineMacro("__powerpc__");
267
4.04k
  Builder.defineMacro("__POWERPC__");
268
4.04k
  if (PointerWidth == 64) {
269
3.83k
    Builder.defineMacro("_ARCH_PPC64");
270
3.83k
    Builder.defineMacro("__powerpc64__");
271
3.83k
    Builder.defineMacro("__ppc64__");
272
3.83k
    Builder.defineMacro("__PPC64__");
273
3.83k
  } else 
if (214
getTriple().isOSAIX()214
) {
274
    // The XL compilers on AIX define _ARCH_PPC64 for both 32 and 64-bit modes.
275
117
    Builder.defineMacro("_ARCH_PPC64");
276
117
  }
277
4.04k
  if (getTriple().isOSAIX()) {
278
214
    Builder.defineMacro("__THW_PPC__");
279
    // Define __PPC and __powerpc for AIX XL C/C++ compatibility
280
214
    Builder.defineMacro("__PPC");
281
214
    Builder.defineMacro("__powerpc");
282
214
  }
283
284
  // Target properties.
285
4.04k
  if (getTriple().getArch() == llvm::Triple::ppc64le ||
286
4.04k
      
getTriple().getArch() == llvm::Triple::ppcle466
) {
287
3.58k
    Builder.defineMacro("_LITTLE_ENDIAN");
288
3.58k
  } else {
289
464
    if (!getTriple().isOSNetBSD() &&
290
464
        
!getTriple().isOSOpenBSD()458
)
291
453
      Builder.defineMacro("_BIG_ENDIAN");
292
464
  }
293
294
  // ABI options.
295
4.04k
  if (ABI == "elfv1")
296
153
    Builder.defineMacro("_CALL_ELF", "1");
297
4.04k
  if (ABI == "elfv2")
298
3.58k
    Builder.defineMacro("_CALL_ELF", "2");
299
300
  // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
301
  // our support post-dates this and it should work on all 64-bit ppc linux
302
  // platforms. It is guaranteed to work on all elfv2 platforms.
303
4.04k
  if (getTriple().getOS() == llvm::Triple::Linux && 
PointerWidth == 64279
)
304
253
    Builder.defineMacro("_CALL_LINUX", "1");
305
306
  // Subtarget options.
307
4.04k
  if (!getTriple().isOSAIX()){
308
3.83k
    Builder.defineMacro("__NATURAL_ALIGNMENT__");
309
3.83k
  }
310
4.04k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
311
312
  // FIXME: Should be controlled by command line option.
313
4.04k
  if (LongDoubleWidth == 128) {
314
3.80k
    Builder.defineMacro("__LONG_DOUBLE_128__");
315
3.80k
    Builder.defineMacro("__LONGDOUBLE128");
316
3.80k
    if (Opts.PPCIEEELongDouble)
317
8
      Builder.defineMacro("__LONG_DOUBLE_IEEE128__");
318
3.79k
    else
319
3.79k
      Builder.defineMacro("__LONG_DOUBLE_IBM128__");
320
3.80k
  }
321
322
4.04k
  if (getTriple().isOSAIX() && 
Opts.LongDoubleSize == 64214
) {
323
1
    assert(LongDoubleWidth == 64);
324
0
    Builder.defineMacro("__LONGDOUBLE64");
325
1
  }
326
327
  // Define this for elfv2 (64-bit only) or 64-bit darwin.
328
4.04k
  if (ABI == "elfv2" ||
329
4.04k
      
(463
getTriple().getOS() == llvm::Triple::Darwin463
&&
PointerWidth == 645
))
330
3.58k
    Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
331
332
4.04k
  if (ArchDefs & ArchDefineName)
333
3
    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
334
4.04k
  if (ArchDefs & ArchDefinePpcgr)
335
191
    Builder.defineMacro("_ARCH_PPCGR");
336
4.04k
  if (ArchDefs & ArchDefinePpcsq)
337
186
    Builder.defineMacro("_ARCH_PPCSQ");
338
4.04k
  if (ArchDefs & ArchDefine440)
339
0
    Builder.defineMacro("_ARCH_440");
340
4.04k
  if (ArchDefs & ArchDefine603)
341
2
    Builder.defineMacro("_ARCH_603");
342
4.04k
  if (ArchDefs & ArchDefine604)
343
0
    Builder.defineMacro("_ARCH_604");
344
4.04k
  if (ArchDefs & ArchDefinePwr4)
345
186
    Builder.defineMacro("_ARCH_PWR4");
346
4.04k
  if (ArchDefs & ArchDefinePwr5)
347
184
    Builder.defineMacro("_ARCH_PWR5");
348
4.04k
  if (ArchDefs & ArchDefinePwr5x)
349
182
    Builder.defineMacro("_ARCH_PWR5X");
350
4.04k
  if (ArchDefs & ArchDefinePwr6)
351
180
    Builder.defineMacro("_ARCH_PWR6");
352
4.04k
  if (ArchDefs & ArchDefinePwr6x)
353
2
    Builder.defineMacro("_ARCH_PWR6X");
354
4.04k
  if (ArchDefs & ArchDefinePwr7)
355
175
    Builder.defineMacro("_ARCH_PWR7");
356
4.04k
  if (ArchDefs & ArchDefinePwr8)
357
130
    Builder.defineMacro("_ARCH_PWR8");
358
4.04k
  if (ArchDefs & ArchDefinePwr9)
359
72
    Builder.defineMacro("_ARCH_PWR9");
360
4.04k
  if (ArchDefs & ArchDefinePwr10)
361
41
    Builder.defineMacro("_ARCH_PWR10");
362
4.04k
  if (ArchDefs & ArchDefineA2)
363
0
    Builder.defineMacro("_ARCH_A2");
364
4.04k
  if (ArchDefs & ArchDefineE500)
365
1
    Builder.defineMacro("__NO_LWSYNC__");
366
4.04k
  if (ArchDefs & ArchDefineFuture)
367
3
    Builder.defineMacro("_ARCH_PWR_FUTURE");
368
369
4.04k
  if (HasAltivec) {
370
269
    Builder.defineMacro("__VEC__", "10206");
371
269
    Builder.defineMacro("__ALTIVEC__");
372
269
  }
373
4.04k
  if (HasSPE) {
374
2
    Builder.defineMacro("__SPE__");
375
2
    Builder.defineMacro("__NO_FPRS__");
376
2
  }
377
4.04k
  if (HasVSX)
378
202
    Builder.defineMacro("__VSX__");
379
4.04k
  if (HasP8Vector)
380
123
    Builder.defineMacro("__POWER8_VECTOR__");
381
4.04k
  if (HasP8Crypto)
382
124
    Builder.defineMacro("__CRYPTO__");
383
4.04k
  if (HasHTM)
384
87
    Builder.defineMacro("__HTM__");
385
4.04k
  if (HasFloat128)
386
18
    Builder.defineMacro("__FLOAT128__");
387
4.04k
  if (HasP9Vector)
388
68
    Builder.defineMacro("__POWER9_VECTOR__");
389
4.04k
  if (HasMMA)
390
40
    Builder.defineMacro("__MMA__");
391
4.04k
  if (HasROPProtect)
392
9
    Builder.defineMacro("__ROP_PROTECT__");
393
4.04k
  if (HasP10Vector)
394
39
    Builder.defineMacro("__POWER10_VECTOR__");
395
4.04k
  if (HasPCRelativeMemops)
396
40
    Builder.defineMacro("__PCREL__");
397
398
4.04k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
399
4.04k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
400
4.04k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
401
4.04k
  if (PointerWidth == 64)
402
3.83k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
403
404
  // We have support for the bswap intrinsics so we can define this.
405
4.04k
  Builder.defineMacro("__HAVE_BSWAP__", "1");
406
407
  // FIXME: The following are not yet generated here by Clang, but are
408
  //        generated by GCC:
409
  //
410
  //   _SOFT_FLOAT_
411
  //   __RECIP_PRECISION__
412
  //   __APPLE_ALTIVEC__
413
  //   __RECIP__
414
  //   __RECIPF__
415
  //   __RSQRTE__
416
  //   __RSQRTEF__
417
  //   _SOFT_DOUBLE_
418
  //   __NO_LWSYNC__
419
  //   __CMODEL_MEDIUM__
420
  //   __CMODEL_LARGE__
421
  //   _CALL_SYSV
422
  //   _CALL_DARWIN
423
4.04k
}
424
425
// Handle explicit options being passed to the compiler here: if we've
426
// explicitly turned off vsx and turned on any of:
427
// - power8-vector
428
// - direct-move
429
// - float128
430
// - power9-vector
431
// - paired-vector-memops
432
// - mma
433
// - power10-vector
434
// then go ahead and error since the customer has expressed an incompatible
435
// set of options.
436
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
437
4.14k
                                 const std::vector<std::string> &FeaturesVec) {
438
439
  // vsx was not explicitly turned off.
440
4.14k
  if (!llvm::is_contained(FeaturesVec, "-vsx"))
441
4.10k
    return true;
442
443
301
  
auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) 43
{
444
301
    if (llvm::is_contained(FeaturesVec, Feature)) {
445
3
      Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
446
3
      return true;
447
3
    }
448
298
    return false;
449
301
  };
450
451
43
  bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
452
43
  Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
453
43
  Found |= FindVSXSubfeature("+float128", "-mfloat128");
454
43
  Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
455
43
  Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
456
43
  Found |= FindVSXSubfeature("+mma", "-mmma");
457
43
  Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
458
459
  // Return false if any vsx subfeatures was found.
460
43
  return !Found;
461
4.14k
}
462
463
bool PPCTargetInfo::initFeatureMap(
464
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
465
4.14k
    const std::vector<std::string> &FeaturesVec) const {
466
4.14k
  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
467
4.14k
                            .Case("7400", true)
468
4.14k
                            .Case("g4", true)
469
4.14k
                            .Case("7450", true)
470
4.14k
                            .Case("g4+", true)
471
4.14k
                            .Case("970", true)
472
4.14k
                            .Case("g5", true)
473
4.14k
                            .Case("pwr6", true)
474
4.14k
                            .Case("pwr7", true)
475
4.14k
                            .Case("pwr8", true)
476
4.14k
                            .Case("pwr9", true)
477
4.14k
                            .Case("ppc64", true)
478
4.14k
                            .Case("ppc64le", true)
479
4.14k
                            .Default(false);
480
481
4.14k
  Features["power9-vector"] = (CPU == "pwr9");
482
4.14k
  Features["crypto"] = llvm::StringSwitch<bool>(CPU)
483
4.14k
                           .Case("ppc64le", true)
484
4.14k
                           .Case("pwr9", true)
485
4.14k
                           .Case("pwr8", true)
486
4.14k
                           .Default(false);
487
4.14k
  Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
488
4.14k
                                  .Case("ppc64le", true)
489
4.14k
                                  .Case("pwr9", true)
490
4.14k
                                  .Case("pwr8", true)
491
4.14k
                                  .Default(false);
492
4.14k
  Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
493
4.14k
                           .Case("ppc64le", true)
494
4.14k
                           .Case("pwr9", true)
495
4.14k
                           .Case("pwr8", true)
496
4.14k
                           .Case("pwr7", true)
497
4.14k
                           .Default(false);
498
4.14k
  Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
499
4.14k
                           .Case("ppc64le", true)
500
4.14k
                           .Case("pwr9", true)
501
4.14k
                           .Case("pwr8", true)
502
4.14k
                           .Case("pwr7", true)
503
4.14k
                           .Default(false);
504
4.14k
  Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
505
4.14k
                                .Case("ppc64le", true)
506
4.14k
                                .Case("pwr9", true)
507
4.14k
                                .Case("pwr8", true)
508
4.14k
                                .Default(false);
509
4.14k
  Features["vsx"] = llvm::StringSwitch<bool>(CPU)
510
4.14k
                        .Case("ppc64le", true)
511
4.14k
                        .Case("pwr9", true)
512
4.14k
                        .Case("pwr8", true)
513
4.14k
                        .Case("pwr7", true)
514
4.14k
                        .Default(false);
515
4.14k
  Features["htm"] = llvm::StringSwitch<bool>(CPU)
516
4.14k
                        .Case("ppc64le", true)
517
4.14k
                        .Case("pwr9", true)
518
4.14k
                        .Case("pwr8", true)
519
4.14k
                        .Default(false);
520
521
  // ROP Protect is off by default.
522
4.14k
  Features["rop-protect"] = false;
523
  // Privileged instructions are off by default.
524
4.14k
  Features["privileged"] = false;
525
526
4.14k
  Features["spe"] = llvm::StringSwitch<bool>(CPU)
527
4.14k
                        .Case("8548", true)
528
4.14k
                        .Case("e500", true)
529
4.14k
                        .Default(false);
530
531
4.14k
  Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
532
4.14k
                                          .Case("ppc64le", true)
533
4.14k
                                          .Case("pwr9", true)
534
4.14k
                                          .Case("pwr8", true)
535
4.14k
                                          .Case("pwr7", true)
536
4.14k
                                          .Default(false);
537
538
4.14k
  Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
539
4.14k
                                          .Case("ppc64le", true)
540
4.14k
                                          .Case("pwr9", true)
541
4.14k
                                          .Case("pwr8", true)
542
4.14k
                                          .Default(false);
543
544
4.14k
  Features["isa-v30-instructions"] =
545
4.14k
      llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);
546
547
  // Power10 includes all the same features as Power9 plus any features specific
548
  // to the Power10 core.
549
4.14k
  if (CPU == "pwr10" || 
CPU == "power10"4.10k
) {
550
41
    initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
551
41
    addP10SpecificFeatures(Features);
552
41
  }
553
554
  // Future CPU should include all of the features of Power 10 as well as any
555
  // additional features (yet to be determined) specific to it.
556
4.14k
  if (CPU == "future") {
557
3
    initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
558
3
    addFutureSpecificFeatures(Features);
559
3
  }
560
561
4.14k
  if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
562
3
    return false;
563
564
4.14k
  if (!(ArchDefs & ArchDefinePwr7) && 
(ArchDefs & ArchDefinePpcgr)3.90k
&&
565
4.14k
      
llvm::is_contained(FeaturesVec, "+float128")17
) {
566
    // We have __float128 on PPC but not pre-VSX targets.
567
1
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
568
1
    return false;
569
1
  }
570
571
4.14k
  if (!(ArchDefs & ArchDefinePwr10)) {
572
4.05k
    if (llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
573
      // MMA operations are not available pre-Power10.
574
4
      Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
575
4
      return false;
576
4
    }
577
4.05k
    if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) {
578
      // PC-Relative instructions are not available pre-Power10,
579
      // and these instructions also require prefixed instructions support.
580
4
      Diags.Report(diag::err_opt_not_valid_without_opt)
581
4
          << "-mpcrel"
582
4
          << "-mcpu=pwr10 -mprefixed";
583
4
      return false;
584
4
    }
585
4.04k
    if (llvm::find(FeaturesVec, "+prefixed") != FeaturesVec.end()) {
586
      // Prefixed instructions are not available pre-Power10.
587
2
      Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed"
588
2
                                                        << "-mcpu=pwr10";
589
2
      return false;
590
2
    }
591
4.04k
    if (llvm::find(FeaturesVec, "+paired-vector-memops") != FeaturesVec.end()) {
592
      // Paired vector memops are not available pre-Power10.
593
2
      Diags.Report(diag::err_opt_not_valid_without_opt)
594
2
          << "-mpaired-vector-memops"
595
2
          << "-mcpu=pwr10";
596
2
      return false;
597
2
    }
598
4.04k
  }
599
600
4.12k
  if (!(ArchDefs & ArchDefinePwr8) &&
601
4.12k
      
llvm::is_contained(FeaturesVec, "+rop-protect")3.95k
) {
602
    // We can turn on ROP Protect on Power 8 and above.
603
2
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mrop-protect" << CPU;
604
2
    return false;
605
2
  }
606
607
4.12k
  if (!(ArchDefs & ArchDefinePwr8) &&
608
4.12k
      
llvm::is_contained(FeaturesVec, "+privileged")3.95k
) {
609
2
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mprivileged" << CPU;
610
2
    return false;
611
2
  }
612
613
4.12k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
614
4.12k
}
615
616
// Add any Power10 specific features.
617
void PPCTargetInfo::addP10SpecificFeatures(
618
41
    llvm::StringMap<bool> &Features) const {
619
41
  Features["htm"] = false; // HTM was removed for P10.
620
41
  Features["paired-vector-memops"] = true;
621
41
  Features["mma"] = true;
622
41
  Features["power10-vector"] = true;
623
41
  Features["pcrelative-memops"] = true;
624
41
  Features["prefix-instrs"] = true;
625
41
  Features["isa-v31-instructions"] = true;
626
41
}
627
628
// Add features specific to the "Future" CPU.
629
void PPCTargetInfo::addFutureSpecificFeatures(
630
3
    llvm::StringMap<bool> &Features) const {}
631
632
7.35k
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
633
7.35k
  return llvm::StringSwitch<bool>(Feature)
634
7.35k
      .Case("powerpc", true)
635
7.35k
      .Case("altivec", HasAltivec)
636
7.35k
      .Case("vsx", HasVSX)
637
7.35k
      .Case("power8-vector", HasP8Vector)
638
7.35k
      .Case("crypto", HasP8Crypto)
639
7.35k
      .Case("direct-move", HasDirectMove)
640
7.35k
      .Case("htm", HasHTM)
641
7.35k
      .Case("bpermd", HasBPERMD)
642
7.35k
      .Case("extdiv", HasExtDiv)
643
7.35k
      .Case("float128", HasFloat128)
644
7.35k
      .Case("power9-vector", HasP9Vector)
645
7.35k
      .Case("paired-vector-memops", PairedVectorMemops)
646
7.35k
      .Case("power10-vector", HasP10Vector)
647
7.35k
      .Case("pcrelative-memops", HasPCRelativeMemops)
648
7.35k
      .Case("prefix-instrs", HasPrefixInstrs)
649
7.35k
      .Case("spe", HasSPE)
650
7.35k
      .Case("mma", HasMMA)
651
7.35k
      .Case("rop-protect", HasROPProtect)
652
7.35k
      .Case("privileged", HasPrivileged)
653
7.35k
      .Case("isa-v206-instructions", IsISA2_06)
654
7.35k
      .Case("isa-v207-instructions", IsISA2_07)
655
7.35k
      .Case("isa-v30-instructions", IsISA3_0)
656
7.35k
      .Case("isa-v31-instructions", IsISA3_1)
657
7.35k
      .Default(false);
658
7.35k
}
659
660
void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
661
742
                                      StringRef Name, bool Enabled) const {
662
742
  if (Enabled) {
663
202
    if (Name == "efpu2")
664
0
      Features["spe"] = true;
665
    // If we're enabling any of the vsx based features then enable vsx and
666
    // altivec. We'll diagnose any problems later.
667
202
    bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
668
202
                             .Case("vsx", true)
669
202
                             .Case("direct-move", true)
670
202
                             .Case("power8-vector", true)
671
202
                             .Case("power9-vector", true)
672
202
                             .Case("paired-vector-memops", true)
673
202
                             .Case("power10-vector", true)
674
202
                             .Case("float128", true)
675
202
                             .Case("mma", true)
676
202
                             .Default(false);
677
202
    if (FeatureHasVSX)
678
66
      Features["vsx"] = Features["altivec"] = true;
679
202
    if (Name == "power9-vector")
680
0
      Features["power8-vector"] = true;
681
202
    else if (Name == "power10-vector")
682
4
      Features["power8-vector"] = Features["power9-vector"] = true;
683
202
    if (Name == "pcrel")
684
6
      Features["pcrelative-memops"] = true;
685
196
    else if (Name == "prefixed")
686
6
      Features["prefix-instrs"] = true;
687
190
    else
688
190
      Features[Name] = true;
689
540
  } else {
690
540
    if (Name == "spe")
691
35
      Features["efpu2"] = false;
692
    // If we're disabling altivec or vsx go ahead and disable all of the vsx
693
    // features.
694
540
    if ((Name == "altivec") || 
(Name == "vsx")505
)
695
75
      Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
696
75
          Features["float128"] = Features["power9-vector"] =
697
75
              Features["paired-vector-memops"] = Features["mma"] =
698
75
                  Features["power10-vector"] = false;
699
540
    if (Name == "power8-vector")
700
35
      Features["power9-vector"] = Features["paired-vector-memops"] =
701
35
          Features["mma"] = Features["power10-vector"] = false;
702
505
    else if (Name == "power9-vector")
703
35
      Features["paired-vector-memops"] = Features["mma"] =
704
35
          Features["power10-vector"] = false;
705
540
    if (Name == "pcrel")
706
2
      Features["pcrelative-memops"] = false;
707
538
    else if (Name == "prefixed")
708
2
      Features["prefix-instrs"] = false;
709
536
    else
710
536
      Features[Name] = false;
711
540
  }
712
742
}
713
714
const char *const PPCTargetInfo::GCCRegNames[] = {
715
    "r0",  "r1",     "r2",   "r3",      "r4",      "r5",  "r6",  "r7",  "r8",
716
    "r9",  "r10",    "r11",  "r12",     "r13",     "r14", "r15", "r16", "r17",
717
    "r18", "r19",    "r20",  "r21",     "r22",     "r23", "r24", "r25", "r26",
718
    "r27", "r28",    "r29",  "r30",     "r31",     "f0",  "f1",  "f2",  "f3",
719
    "f4",  "f5",     "f6",   "f7",      "f8",      "f9",  "f10", "f11", "f12",
720
    "f13", "f14",    "f15",  "f16",     "f17",     "f18", "f19", "f20", "f21",
721
    "f22", "f23",    "f24",  "f25",     "f26",     "f27", "f28", "f29", "f30",
722
    "f31", "mq",     "lr",   "ctr",     "ap",      "cr0", "cr1", "cr2", "cr3",
723
    "cr4", "cr5",    "cr6",  "cr7",     "xer",     "v0",  "v1",  "v2",  "v3",
724
    "v4",  "v5",     "v6",   "v7",      "v8",      "v9",  "v10", "v11", "v12",
725
    "v13", "v14",    "v15",  "v16",     "v17",     "v18", "v19", "v20", "v21",
726
    "v22", "v23",    "v24",  "v25",     "v26",     "v27", "v28", "v29", "v30",
727
    "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp"
728
};
729
730
15
ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
731
15
  return llvm::makeArrayRef(GCCRegNames);
732
15
}
733
734
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
735
    // While some of these aliases do map to different registers
736
    // they still share the same register name.
737
    {{"0"}, "r0"},     {{"1"}, "r1"},     {{"2"}, "r2"},     {{"3"}, "r3"},
738
    {{"4"}, "r4"},     {{"5"}, "r5"},     {{"6"}, "r6"},     {{"7"}, "r7"},
739
    {{"8"}, "r8"},     {{"9"}, "r9"},     {{"10"}, "r10"},   {{"11"}, "r11"},
740
    {{"12"}, "r12"},   {{"13"}, "r13"},   {{"14"}, "r14"},   {{"15"}, "r15"},
741
    {{"16"}, "r16"},   {{"17"}, "r17"},   {{"18"}, "r18"},   {{"19"}, "r19"},
742
    {{"20"}, "r20"},   {{"21"}, "r21"},   {{"22"}, "r22"},   {{"23"}, "r23"},
743
    {{"24"}, "r24"},   {{"25"}, "r25"},   {{"26"}, "r26"},   {{"27"}, "r27"},
744
    {{"28"}, "r28"},   {{"29"}, "r29"},   {{"30"}, "r30"},   {{"31"}, "r31"},
745
    {{"fr0"}, "f0"},   {{"fr1"}, "f1"},   {{"fr2"}, "f2"},   {{"fr3"}, "f3"},
746
    {{"fr4"}, "f4"},   {{"fr5"}, "f5"},   {{"fr6"}, "f6"},   {{"fr7"}, "f7"},
747
    {{"fr8"}, "f8"},   {{"fr9"}, "f9"},   {{"fr10"}, "f10"}, {{"fr11"}, "f11"},
748
    {{"fr12"}, "f12"}, {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"},
749
    {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, {{"fr19"}, "f19"},
750
    {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"},
751
    {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
752
    {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"},
753
    {{"cc"}, "cr0"},
754
};
755
756
6
ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
757
6
  return llvm::makeArrayRef(GCCRegAliases);
758
6
}
759
760
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
761
// vs0 ~ vs31 is mapping to 32 - 63,
762
// vs32 ~ vs63 is mapping to 77 - 108. 
763
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
764
    // Table of additional register names to use in user input.
765
    {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35}, 
766
    {{"vs4"}, 36},   {{"vs5"}, 37},   {{"vs6"}, 38},   {{"vs7"}, 39},
767
    {{"vs8"}, 40},   {{"vs9"}, 41},   {{"vs10"}, 42},  {{"vs11"}, 43},
768
    {{"vs12"}, 44},  {{"vs13"}, 45},  {{"vs14"}, 46},  {{"vs15"}, 47},
769
    {{"vs16"}, 48},  {{"vs17"}, 49},  {{"vs18"}, 50},  {{"vs19"}, 51},
770
    {{"vs20"}, 52},  {{"vs21"}, 53},  {{"vs22"}, 54},  {{"vs23"}, 55},
771
    {{"vs24"}, 56},  {{"vs25"}, 57},  {{"vs26"}, 58},  {{"vs27"}, 59},
772
    {{"vs28"}, 60},  {{"vs29"}, 61},  {{"vs30"}, 62},  {{"vs31"}, 63},
773
    {{"vs32"}, 77},  {{"vs33"}, 78},  {{"vs34"}, 79},  {{"vs35"}, 80},
774
    {{"vs36"}, 81},  {{"vs37"}, 82},  {{"vs38"}, 83},  {{"vs39"}, 84},
775
    {{"vs40"}, 85},  {{"vs41"}, 86},  {{"vs42"}, 87},  {{"vs43"}, 88},
776
    {{"vs44"}, 89},  {{"vs45"}, 90},  {{"vs46"}, 91},  {{"vs47"}, 92},
777
    {{"vs48"}, 93},  {{"vs49"}, 94},  {{"vs50"}, 95},  {{"vs51"}, 96},
778
    {{"vs52"}, 97},  {{"vs53"}, 98},  {{"vs54"}, 99},  {{"vs55"}, 100},
779
    {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
780
    {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
781
};
782
783
6
ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
784
6
  if (ABI == "elfv2")
785
4
    return llvm::makeArrayRef(GCCAddlRegNames);
786
2
  else 
787
2
    return TargetInfo::getGCCAddlRegNames(); 
788
6
}
789
790
static constexpr llvm::StringLiteral ValidCPUNames[] = {
791
    {"generic"},     {"440"},     {"450"},    {"601"},       {"602"},
792
    {"603"},         {"603e"},    {"603ev"},  {"604"},       {"604e"},
793
    {"620"},         {"630"},     {"g3"},     {"7400"},      {"g4"},
794
    {"7450"},        {"g4+"},     {"750"},    {"8548"},      {"970"},
795
    {"g5"},          {"a2"},      {"e500"},   {"e500mc"},    {"e5500"},
796
    {"power3"},      {"pwr3"},    {"power4"}, {"pwr4"},      {"power5"},
797
    {"pwr5"},        {"power5x"}, {"pwr5x"},  {"power6"},    {"pwr6"},
798
    {"power6x"},     {"pwr6x"},   {"power7"}, {"pwr7"},      {"power8"},
799
    {"pwr8"},        {"power9"},  {"pwr9"},   {"power10"},   {"pwr10"},
800
    {"powerpc"},     {"ppc"},     {"ppc32"},  {"powerpc64"}, {"ppc64"},
801
    {"powerpc64le"}, {"ppc64le"}, {"future"}};
802
803
231
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
804
231
  return llvm::is_contained(ValidCPUNames, Name);
805
231
}
806
807
1
void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
808
1
  Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
809
1
}
810
811
7.99k
void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
812
7.99k
  if (HasAltivec)
813
536
    Opts.AltiVec = 1;
814
7.99k
  TargetInfo::adjust(Diags, Opts);
815
7.99k
  if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
816
7.51k
    LongDoubleFormat = Opts.PPCIEEELongDouble
817
7.51k
                           ? 
&llvm::APFloat::IEEEquad()16
818
7.51k
                           : 
&llvm::APFloat::PPCDoubleDouble()7.50k
;
819
7.99k
  Opts.IEEE128 = 1;
820
7.99k
}
821
822
4.04k
ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
823
4.04k
  return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
824
4.04k
                                             Builtin::FirstTSBuiltin);
825
4.04k
}