Coverage Report

Created: 2022-01-25 06:29

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/PPC.h
Line
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Source (jump to first uncovered line)
1
//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14
#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16
#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
18
#include "clang/Basic/TargetOptions.h"
19
#include "llvm/ADT/Triple.h"
20
#include "llvm/ADT/StringSwitch.h"
21
#include "llvm/Support/Compiler.h"
22
23
namespace clang {
24
namespace targets {
25
26
// PPC abstract base class
27
class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29
  /// Flags for architecture specific defines.
30
  typedef enum {
31
    ArchDefineNone = 0,
32
    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33
    ArchDefinePpcgr = 1 << 1,
34
    ArchDefinePpcsq = 1 << 2,
35
    ArchDefine440 = 1 << 3,
36
    ArchDefine603 = 1 << 4,
37
    ArchDefine604 = 1 << 5,
38
    ArchDefinePwr4 = 1 << 6,
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    ArchDefinePwr5 = 1 << 7,
40
    ArchDefinePwr5x = 1 << 8,
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    ArchDefinePwr6 = 1 << 9,
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    ArchDefinePwr6x = 1 << 10,
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    ArchDefinePwr7 = 1 << 11,
44
    ArchDefinePwr8 = 1 << 12,
45
    ArchDefinePwr9 = 1 << 13,
46
    ArchDefinePwr10 = 1 << 14,
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    ArchDefineFuture = 1 << 15,
48
    ArchDefineA2 = 1 << 16,
49
    ArchDefineE500 = 1 << 18
50
  } ArchDefineTypes;
51
52
  ArchDefineTypes ArchDefs = ArchDefineNone;
53
  static const Builtin::Info BuiltinInfo[];
54
  static const char *const GCCRegNames[];
55
  static const TargetInfo::GCCRegAlias GCCRegAliases[];
56
  std::string CPU;
57
  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58
59
  // Target cpu features.
60
  bool HasAltivec = false;
61
  bool HasMMA = false;
62
  bool HasROPProtect = false;
63
  bool HasPrivileged = false;
64
  bool HasVSX = false;
65
  bool HasP8Vector = false;
66
  bool HasP8Crypto = false;
67
  bool HasDirectMove = false;
68
  bool HasHTM = false;
69
  bool HasBPERMD = false;
70
  bool HasExtDiv = false;
71
  bool HasP9Vector = false;
72
  bool HasSPE = false;
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  bool PairedVectorMemops = false;
74
  bool HasP10Vector = false;
75
  bool HasPCRelativeMemops = false;
76
  bool HasPrefixInstrs = false;
77
  bool IsISA2_06 = false;
78
  bool IsISA2_07 = false;
79
  bool IsISA3_0 = false;
80
  bool IsISA3_1 = false;
81
82
protected:
83
  std::string ABI;
84
85
public:
86
  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
87
4.10k
      : TargetInfo(Triple) {
88
4.10k
    SuitableAlign = 128;
89
4.10k
    SimdDefaultAlign = 128;
90
4.10k
    LongDoubleWidth = LongDoubleAlign = 128;
91
4.10k
    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
92
4.10k
    HasStrictFP = true;
93
4.10k
    HasIbm128 = true;
94
4.10k
  }
95
96
  // Set the language option for altivec based on our value.
97
  void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
98
99
  // Note: GCC recognizes the following additional cpus:
100
  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
101
  //  821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
102
  bool isValidCPUName(StringRef Name) const override;
103
  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
104
105
233
  bool setCPU(const std::string &Name) override {
106
233
    bool CPUKnown = isValidCPUName(Name);
107
233
    if (CPUKnown) {
108
232
      CPU = Name;
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110
      // CPU identification.
111
232
      ArchDefs =
112
232
          (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
113
232
              .Case("440", ArchDefineName)
114
232
              .Case("450", ArchDefineName | ArchDefine440)
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232
              .Case("601", ArchDefineName)
116
232
              .Case("602", ArchDefineName | ArchDefinePpcgr)
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232
              .Case("603", ArchDefineName | ArchDefinePpcgr)
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232
              .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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232
              .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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232
              .Case("604", ArchDefineName | ArchDefinePpcgr)
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232
              .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
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232
              .Case("620", ArchDefineName | ArchDefinePpcgr)
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232
              .Case("630", ArchDefineName | ArchDefinePpcgr)
124
232
              .Case("7400", ArchDefineName | ArchDefinePpcgr)
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232
              .Case("7450", ArchDefineName | ArchDefinePpcgr)
126
232
              .Case("750", ArchDefineName | ArchDefinePpcgr)
127
232
              .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
128
232
                               ArchDefinePpcsq)
129
232
              .Case("a2", ArchDefineA2)
130
232
              .Cases("power3", "pwr3", ArchDefinePpcgr)
131
232
              .Cases("power4", "pwr4",
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232
                     ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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232
              .Cases("power5", "pwr5",
134
232
                     ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
135
232
                         ArchDefinePpcsq)
136
232
              .Cases("power5x", "pwr5x",
137
232
                     ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
138
232
                         ArchDefinePpcgr | ArchDefinePpcsq)
139
232
              .Cases("power6", "pwr6",
140
232
                     ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
141
232
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
142
232
              .Cases("power6x", "pwr6x",
143
232
                     ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
144
232
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
145
232
                         ArchDefinePpcsq)
146
232
              .Cases("power7", "pwr7",
147
232
                     ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
148
232
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
149
232
                         ArchDefinePpcsq)
150
              // powerpc64le automatically defaults to at least power8.
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232
              .Cases("power8", "pwr8", "ppc64le",
152
232
                     ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
153
232
                         ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
154
232
                         ArchDefinePpcgr | ArchDefinePpcsq)
155
232
              .Cases("power9", "pwr9",
156
232
                     ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
157
232
                         ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
158
232
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
159
232
              .Cases("power10", "pwr10",
160
232
                     ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
161
232
                         ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
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232
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
163
232
                         ArchDefinePpcsq)
164
232
              .Case("future",
165
232
                    ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
166
232
                        ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
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232
                        ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
168
232
                        ArchDefinePpcgr | ArchDefinePpcsq)
169
232
              .Cases("8548", "e500", ArchDefineE500)
170
232
              .Default(ArchDefineNone);
171
232
    }
172
233
    return CPUKnown;
173
233
  }
174
175
8.69k
  StringRef getABI() const override { return ABI; }
176
177
  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
178
179
0
  bool isCLZForZeroUndef() const override { return false; }
180
181
  void getTargetDefines(const LangOptions &Opts,
182
                        MacroBuilder &Builder) const override;
183
184
  bool
185
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
186
                 StringRef CPU,
187
                 const std::vector<std::string> &FeaturesVec) const override;
188
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  void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
190
  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
191
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  bool handleTargetFeatures(std::vector<std::string> &Features,
193
                            DiagnosticsEngine &Diags) override;
194
195
  bool hasFeature(StringRef Feature) const override;
196
197
  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
198
                         bool Enabled) const override;
199
200
  ArrayRef<const char *> getGCCRegNames() const override;
201
202
  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
203
204
  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
205
206
  bool validateAsmConstraint(const char *&Name,
207
37
                             TargetInfo::ConstraintInfo &Info) const override {
208
37
    switch (*Name) {
209
0
    default:
210
0
      return false;
211
0
    case 'O': // Zero
212
0
      break;
213
1
    case 'f': // Floating point register
214
      // Don't use floating point registers on soft float ABI.
215
1
      if (FloatABI == SoftFloat)
216
1
        return false;
217
1
      
LLVM_FALLTHROUGH0
;0
218
0
    case 'b': // Base register
219
0
      Info.setAllowsRegister();
220
0
      break;
221
    // FIXME: The following are added to allow parsing.
222
    // I just took a guess at what the actions should be.
223
    // Also, is more specific checking needed?  I.e. specific registers?
224
1
    case 'd': // Floating point register (containing 64-bit value)
225
2
    case 'v': // Altivec vector register
226
      // Don't use floating point and altivec vector registers
227
      // on soft float ABI
228
2
      if (FloatABI == SoftFloat)
229
2
        return false;
230
0
      Info.setAllowsRegister();
231
0
      break;
232
30
    case 'w':
233
30
      switch (Name[1]) {
234
0
      case 'd': // VSX vector register to hold vector double data
235
0
      case 'f': // VSX vector register to hold vector float data
236
6
      case 's': // VSX vector register to hold scalar double data
237
12
      case 'w': // VSX vector register to hold scalar double data
238
12
      case 'a': // Any VSX register
239
30
      case 'c': // An individual CR bit
240
30
      case 'i': // FP or VSX register to hold 64-bit integers data
241
30
        break;
242
0
      default:
243
0
        return false;
244
30
      }
245
30
      Info.setAllowsRegister();
246
30
      Name++; // Skip over 'w'.
247
30
      break;
248
0
    case 'h': // `MQ', `CTR', or `LINK' register
249
0
    case 'q': // `MQ' register
250
0
    case 'c': // `CTR' register
251
0
    case 'l': // `LINK' register
252
0
    case 'x': // `CR' register (condition register) number 0
253
0
    case 'y': // `CR' register (condition register)
254
0
    case 'z': // `XER[CA]' carry bit (part of the XER register)
255
0
      Info.setAllowsRegister();
256
0
      break;
257
0
    case 'I': // Signed 16-bit constant
258
0
    case 'J': // Unsigned 16-bit constant shifted left 16 bits
259
              //  (use `L' instead for SImode constants)
260
0
    case 'K': // Unsigned 16-bit constant
261
0
    case 'L': // Signed 16-bit constant shifted left 16 bits
262
0
    case 'M': // Constant larger than 31
263
0
    case 'N': // Exact power of 2
264
0
    case 'P': // Constant whose negation is a signed 16-bit constant
265
0
    case 'G': // Floating point constant that can be loaded into a
266
              // register with one instruction per word
267
0
    case 'H': // Integer/Floating point constant that can be loaded
268
              // into a register using three instructions
269
0
      break;
270
0
    case 'm': // Memory operand. Note that on PowerPC targets, m can
271
              // include addresses that update the base register. It
272
              // is therefore only safe to use `m' in an asm statement
273
              // if that asm statement accesses the operand exactly once.
274
              // The asm statement must also use `%U<opno>' as a
275
              // placeholder for the "update" flag in the corresponding
276
              // load or store instruction. For example:
277
              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
278
              // is correct but:
279
              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
280
              // is not. Use es rather than m if you don't want the base
281
              // register to be updated.
282
0
    case 'e':
283
0
      if (Name[1] != 's')
284
0
        return false;
285
      // es: A "stable" memory operand; that is, one which does not
286
      // include any automodification of the base register. Unlike
287
      // `m', this constraint can be used in asm statements that
288
      // might access the operand several times, or that might not
289
      // access it at all.
290
0
      Info.setAllowsMemory();
291
0
      Name++; // Skip over 'e'.
292
0
      break;
293
0
    case 'Q': // Memory operand that is an offset from a register (it is
294
              // usually better to use `m' or `es' in asm statements)
295
0
      Info.setAllowsRegister();
296
0
      LLVM_FALLTHROUGH;
297
4
    case 'Z': // Memory operand that is an indexed or indirect from a
298
              // register (it is usually better to use `m' or `es' in
299
              // asm statements)
300
4
      Info.setAllowsMemory();
301
4
      break;
302
0
    case 'R': // AIX TOC entry
303
0
    case 'a': // Address operand that is an indexed or indirect from a
304
              // register (`p' is preferable for asm statements)
305
0
    case 'S': // Constant suitable as a 64-bit mask operand
306
0
    case 'T': // Constant suitable as a 32-bit mask operand
307
0
    case 'U': // System V Release 4 small data area reference
308
0
    case 't': // AND masks that can be performed by two rldic{l, r}
309
              // instructions
310
0
    case 'W': // Vector constant that does not require memory
311
0
    case 'j': // Vector constant that is all zeros.
312
0
      break;
313
      // End FIXME.
314
37
    }
315
34
    return true;
316
37
  }
317
318
263
  std::string convertConstraint(const char *&Constraint) const override {
319
263
    std::string R;
320
263
    switch (*Constraint) {
321
0
    case 'e':
322
15
    case 'w':
323
      // Two-character constraint; add "^" hint for later parsing.
324
15
      R = std::string("^") + std::string(Constraint, 2);
325
15
      Constraint++;
326
15
      break;
327
248
    default:
328
248
      return TargetInfo::convertConstraint(Constraint);
329
263
    }
330
15
    return R;
331
263
  }
332
333
88
  const char *getClobbers() const override { return ""; }
334
0
  int getEHDataRegisterNumber(unsigned RegNo) const override {
335
0
    if (RegNo == 0)
336
0
      return 3;
337
0
    if (RegNo == 1)
338
0
      return 4;
339
0
    return -1;
340
0
  }
341
342
4
  bool hasSjLjLowering() const override { return true; }
343
344
163
  const char *getLongDoubleMangling() const override {
345
163
    if (LongDoubleWidth == 64)
346
6
      return "e";
347
157
    return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
348
157
               ? 
"g"151
349
157
               : 
"u9__ieee128"6
;
350
163
  }
351
44
  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
352
52
  const char *getIbm128Mangling() const override { return "g"; }
353
354
33
  bool hasBitIntType() const override { return true; }
355
356
0
  bool isSPRegName(StringRef RegName) const override {
357
0
    return RegName.equals("r1") || RegName.equals("x1");
358
0
  }
359
};
360
361
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
362
public:
363
  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
364
216
      : PPCTargetInfo(Triple, Opts) {
365
216
    if (Triple.isOSAIX())
366
119
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
367
97
    else if (Triple.getArch() == llvm::Triple::ppcle)
368
2
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
369
95
    else
370
95
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
371
372
216
    switch (getTriple().getOS()) {
373
26
    case llvm::Triple::Linux:
374
28
    case llvm::Triple::FreeBSD:
375
30
    case llvm::Triple::NetBSD:
376
30
      SizeType = UnsignedInt;
377
30
      PtrDiffType = SignedInt;
378
30
      IntPtrType = SignedInt;
379
30
      break;
380
119
    case llvm::Triple::AIX:
381
119
      SizeType = UnsignedLong;
382
119
      PtrDiffType = SignedLong;
383
119
      IntPtrType = SignedLong;
384
119
      LongDoubleWidth = 64;
385
119
      LongDoubleAlign = DoubleAlign = 32;
386
119
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
387
119
      break;
388
67
    default:
389
67
      break;
390
216
    }
391
392
216
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()214
||
Triple.isOSOpenBSD()212
||
393
216
        
Triple.isMusl()209
) {
394
7
      LongDoubleWidth = LongDoubleAlign = 64;
395
7
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
396
7
    }
397
398
    // PPC32 supports atomics up to 4 bytes.
399
216
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
400
216
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
364
158
      : PPCTargetInfo(Triple, Opts) {
365
158
    if (Triple.isOSAIX())
366
119
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
367
39
    else if (Triple.getArch() == llvm::Triple::ppcle)
368
0
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
369
39
    else
370
39
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
371
372
158
    switch (getTriple().getOS()) {
373
26
    case llvm::Triple::Linux:
374
28
    case llvm::Triple::FreeBSD:
375
30
    case llvm::Triple::NetBSD:
376
30
      SizeType = UnsignedInt;
377
30
      PtrDiffType = SignedInt;
378
30
      IntPtrType = SignedInt;
379
30
      break;
380
119
    case llvm::Triple::AIX:
381
119
      SizeType = UnsignedLong;
382
119
      PtrDiffType = SignedLong;
383
119
      IntPtrType = SignedLong;
384
119
      LongDoubleWidth = 64;
385
119
      LongDoubleAlign = DoubleAlign = 32;
386
119
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
387
119
      break;
388
9
    default:
389
9
      break;
390
158
    }
391
392
158
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()156
||
Triple.isOSOpenBSD()154
||
393
158
        
Triple.isMusl()151
) {
394
7
      LongDoubleWidth = LongDoubleAlign = 64;
395
7
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
396
7
    }
397
398
    // PPC32 supports atomics up to 4 bytes.
399
158
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
400
158
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
364
58
      : PPCTargetInfo(Triple, Opts) {
365
58
    if (Triple.isOSAIX())
366
0
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
367
58
    else if (Triple.getArch() == llvm::Triple::ppcle)
368
2
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
369
56
    else
370
56
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
371
372
58
    switch (getTriple().getOS()) {
373
0
    case llvm::Triple::Linux:
374
0
    case llvm::Triple::FreeBSD:
375
0
    case llvm::Triple::NetBSD:
376
0
      SizeType = UnsignedInt;
377
0
      PtrDiffType = SignedInt;
378
0
      IntPtrType = SignedInt;
379
0
      break;
380
0
    case llvm::Triple::AIX:
381
0
      SizeType = UnsignedLong;
382
0
      PtrDiffType = SignedLong;
383
0
      IntPtrType = SignedLong;
384
0
      LongDoubleWidth = 64;
385
0
      LongDoubleAlign = DoubleAlign = 32;
386
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
387
0
      break;
388
58
    default:
389
58
      break;
390
58
    }
391
392
58
    if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
393
58
        Triple.isMusl()) {
394
0
      LongDoubleWidth = LongDoubleAlign = 64;
395
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
396
0
    }
397
398
    // PPC32 supports atomics up to 4 bytes.
399
58
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
400
58
  }
401
402
81
  BuiltinVaListKind getBuiltinVaListKind() const override {
403
    // This is the ELF definition, and is overridden by the Darwin sub-target
404
81
    return TargetInfo::PowerABIBuiltinVaList;
405
81
  }
406
};
407
408
// Note: ABI differences may eventually require us to have a separate
409
// TargetInfo for little endian.
410
class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
411
public:
412
  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
413
3.89k
      : PPCTargetInfo(Triple, Opts) {
414
3.89k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
415
3.89k
    IntMaxType = SignedLong;
416
3.89k
    Int64Type = SignedLong;
417
3.89k
    std::string DataLayout;
418
419
3.89k
    if (Triple.isOSAIX()) {
420
      // TODO: Set appropriate ABI for AIX platform.
421
97
      DataLayout = "E-m:a-i64:64-n32:64";
422
97
      LongDoubleWidth = 64;
423
97
      LongDoubleAlign = DoubleAlign = 32;
424
97
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
425
3.79k
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
426
3.63k
      DataLayout = "e-m:e-i64:64-n32:64";
427
3.63k
      ABI = "elfv2";
428
3.63k
    } else {
429
158
      DataLayout = "E-m:e-i64:64-n32:64";
430
158
      ABI = "elfv1";
431
158
    }
432
433
3.89k
    if (Triple.isOSFreeBSD() || 
Triple.isOSOpenBSD()3.88k
||
Triple.isMusl()3.88k
) {
434
15
      LongDoubleWidth = LongDoubleAlign = 64;
435
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
436
15
    }
437
438
3.89k
    if (Triple.isOSAIX() || 
Triple.isOSLinux()3.79k
)
439
372
      DataLayout += "-S128-v256:256:256-v512:512:512";
440
3.89k
    resetDataLayout(DataLayout);
441
442
    // PPC64 supports atomics up to 8 bytes.
443
3.89k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
444
3.89k
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
413
390
      : PPCTargetInfo(Triple, Opts) {
414
390
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
415
390
    IntMaxType = SignedLong;
416
390
    Int64Type = SignedLong;
417
390
    std::string DataLayout;
418
419
390
    if (Triple.isOSAIX()) {
420
      // TODO: Set appropriate ABI for AIX platform.
421
97
      DataLayout = "E-m:a-i64:64-n32:64";
422
97
      LongDoubleWidth = 64;
423
97
      LongDoubleAlign = DoubleAlign = 32;
424
97
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
425
293
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
426
203
      DataLayout = "e-m:e-i64:64-n32:64";
427
203
      ABI = "elfv2";
428
203
    } else {
429
90
      DataLayout = "E-m:e-i64:64-n32:64";
430
90
      ABI = "elfv1";
431
90
    }
432
433
390
    if (Triple.isOSFreeBSD() || 
Triple.isOSOpenBSD()382
||
Triple.isMusl()379
) {
434
15
      LongDoubleWidth = LongDoubleAlign = 64;
435
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
436
15
    }
437
438
390
    if (Triple.isOSAIX() || 
Triple.isOSLinux()293
)
439
372
      DataLayout += "-S128-v256:256:256-v512:512:512";
440
390
    resetDataLayout(DataLayout);
441
442
    // PPC64 supports atomics up to 8 bytes.
443
390
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
444
390
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
413
3.50k
      : PPCTargetInfo(Triple, Opts) {
414
3.50k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
415
3.50k
    IntMaxType = SignedLong;
416
3.50k
    Int64Type = SignedLong;
417
3.50k
    std::string DataLayout;
418
419
3.50k
    if (Triple.isOSAIX()) {
420
      // TODO: Set appropriate ABI for AIX platform.
421
0
      DataLayout = "E-m:a-i64:64-n32:64";
422
0
      LongDoubleWidth = 64;
423
0
      LongDoubleAlign = DoubleAlign = 32;
424
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
425
3.50k
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
426
3.43k
      DataLayout = "e-m:e-i64:64-n32:64";
427
3.43k
      ABI = "elfv2";
428
3.43k
    } else {
429
68
      DataLayout = "E-m:e-i64:64-n32:64";
430
68
      ABI = "elfv1";
431
68
    }
432
433
3.50k
    if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
434
0
      LongDoubleWidth = LongDoubleAlign = 64;
435
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
436
0
    }
437
438
3.50k
    if (Triple.isOSAIX() || Triple.isOSLinux())
439
0
      DataLayout += "-S128-v256:256:256-v512:512:512";
440
3.50k
    resetDataLayout(DataLayout);
441
442
    // PPC64 supports atomics up to 8 bytes.
443
3.50k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
444
3.50k
  }
445
446
3.72k
  BuiltinVaListKind getBuiltinVaListKind() const override {
447
3.72k
    return TargetInfo::CharPtrBuiltinVaList;
448
3.72k
  }
449
450
  // PPC64 Linux-specific ABI options.
451
81
  bool setABI(const std::string &Name) override {
452
81
    if (Name == "elfv1" || 
Name == "elfv2"55
) {
453
81
      ABI = Name;
454
81
      return true;
455
81
    }
456
0
    return false;
457
81
  }
458
459
104
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
460
104
    switch (CC) {
461
0
    case CC_Swift:
462
0
      return CCCR_OK;
463
104
    case CC_SwiftAsync:
464
104
      return CCCR_Error;
465
0
    default:
466
0
      return CCCR_Warning;
467
104
    }
468
104
  }
469
};
470
471
class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
472
    : public DarwinTargetInfo<PPC32TargetInfo> {
473
public:
474
  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
475
6
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
476
6
    HasAlignMac68kSupport = true;
477
6
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
478
6
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
479
6
    LongLongAlign = 32;
480
6
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
481
6
  }
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
475
6
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
476
6
    HasAlignMac68kSupport = true;
477
6
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
478
6
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
479
6
    LongLongAlign = 32;
480
6
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
481
6
  }
Unexecuted instantiation: clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
482
483
5
  BuiltinVaListKind getBuiltinVaListKind() const override {
484
5
    return TargetInfo::CharPtrBuiltinVaList;
485
5
  }
486
};
487
488
class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
489
    : public DarwinTargetInfo<PPC64TargetInfo> {
490
public:
491
  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
492
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
493
1
    HasAlignMac68kSupport = true;
494
1
    resetDataLayout("E-m:o-i64:64-n32:64", "_");
495
1
  }
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
492
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
493
1
    HasAlignMac68kSupport = true;
494
1
    resetDataLayout("E-m:o-i64:64-n32:64", "_");
495
1
  }
Unexecuted instantiation: clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
496
};
497
498
class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
499
  public AIXTargetInfo<PPC32TargetInfo> {
500
public:
501
  using AIXTargetInfo::AIXTargetInfo;
502
95
  BuiltinVaListKind getBuiltinVaListKind() const override {
503
95
    return TargetInfo::CharPtrBuiltinVaList;
504
95
  }
505
};
506
507
class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
508
  public AIXTargetInfo<PPC64TargetInfo> {
509
public:
510
  using AIXTargetInfo::AIXTargetInfo;
511
};
512
513
} // namespace targets
514
} // namespace clang
515
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H