Coverage Report

Created: 2020-02-15 09:57

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/PPC.h
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Source (jump to first uncovered line)
1
//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14
#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16
#include "OSTargets.h"
17
#include "clang/Basic/TargetInfo.h"
18
#include "clang/Basic/TargetOptions.h"
19
#include "llvm/ADT/Triple.h"
20
#include "llvm/ADT/StringSwitch.h"
21
#include "llvm/Support/Compiler.h"
22
23
namespace clang {
24
namespace targets {
25
26
// PPC abstract base class
27
class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29
  /// Flags for architecture specific defines.
30
  typedef enum {
31
    ArchDefineNone = 0,
32
    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33
    ArchDefinePpcgr = 1 << 1,
34
    ArchDefinePpcsq = 1 << 2,
35
    ArchDefine440 = 1 << 3,
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    ArchDefine603 = 1 << 4,
37
    ArchDefine604 = 1 << 5,
38
    ArchDefinePwr4 = 1 << 6,
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    ArchDefinePwr5 = 1 << 7,
40
    ArchDefinePwr5x = 1 << 8,
41
    ArchDefinePwr6 = 1 << 9,
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    ArchDefinePwr6x = 1 << 10,
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    ArchDefinePwr7 = 1 << 11,
44
    ArchDefinePwr8 = 1 << 12,
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    ArchDefinePwr9 = 1 << 13,
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    ArchDefineFuture = 1 << 14,
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    ArchDefineA2 = 1 << 15,
48
    ArchDefineA2q = 1 << 16,
49
    ArchDefineE500 = 1 << 17
50
  } ArchDefineTypes;
51
52
53
  ArchDefineTypes ArchDefs = ArchDefineNone;
54
  static const Builtin::Info BuiltinInfo[];
55
  static const char *const GCCRegNames[];
56
  static const TargetInfo::GCCRegAlias GCCRegAliases[];
57
  std::string CPU;
58
  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
59
60
  // Target cpu features.
61
  bool HasAltivec = false;
62
  bool HasVSX = false;
63
  bool HasP8Vector = false;
64
  bool HasP8Crypto = false;
65
  bool HasDirectMove = false;
66
  bool HasQPX = false;
67
  bool HasHTM = false;
68
  bool HasBPERMD = false;
69
  bool HasExtDiv = false;
70
  bool HasP9Vector = false;
71
  bool HasSPE = false;
72
73
protected:
74
  std::string ABI;
75
76
public:
77
  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
78
2.89k
      : TargetInfo(Triple) {
79
2.89k
    SuitableAlign = 128;
80
2.89k
    SimdDefaultAlign = 128;
81
2.89k
    LongDoubleWidth = LongDoubleAlign = 128;
82
2.89k
    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
83
2.89k
  }
84
85
  // Set the language option for altivec based on our value.
86
  void adjust(LangOptions &Opts) override;
87
88
  // Note: GCC recognizes the following additional cpus:
89
  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
90
  //  821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
91
  bool isValidCPUName(StringRef Name) const override;
92
  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
93
94
119
  bool setCPU(const std::string &Name) override {
95
119
    bool CPUKnown = isValidCPUName(Name);
96
119
    if (CPUKnown) {
97
118
      CPU = Name;
98
118
99
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      // CPU identification.
100
118
      ArchDefs =
101
118
          (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
102
118
              .Case("440", ArchDefineName)
103
118
              .Case("450", ArchDefineName | ArchDefine440)
104
118
              .Case("601", ArchDefineName)
105
118
              .Case("602", ArchDefineName | ArchDefinePpcgr)
106
118
              .Case("603", ArchDefineName | ArchDefinePpcgr)
107
118
              .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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118
              .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
109
118
              .Case("604", ArchDefineName | ArchDefinePpcgr)
110
118
              .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
111
118
              .Case("620", ArchDefineName | ArchDefinePpcgr)
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118
              .Case("630", ArchDefineName | ArchDefinePpcgr)
113
118
              .Case("7400", ArchDefineName | ArchDefinePpcgr)
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118
              .Case("7450", ArchDefineName | ArchDefinePpcgr)
115
118
              .Case("750", ArchDefineName | ArchDefinePpcgr)
116
118
              .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
117
118
                               ArchDefinePpcsq)
118
118
              .Case("a2", ArchDefineA2)
119
118
              .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
120
118
              .Cases("power3", "pwr3", ArchDefinePpcgr)
121
118
              .Cases("power4", "pwr4",
122
118
                    ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
123
118
              .Cases("power5", "pwr5",
124
118
                    ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
125
118
                        ArchDefinePpcsq)
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118
              .Cases("power5x", "pwr5x",
127
118
                    ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
128
118
                        ArchDefinePpcgr | ArchDefinePpcsq)
129
118
              .Cases("power6", "pwr6",
130
118
                    ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
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118
                        ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
132
118
              .Cases("power6x", "pwr6x",
133
118
                    ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
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118
                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
135
118
                        ArchDefinePpcsq)
136
118
              .Cases("power7", "pwr7",
137
118
                     ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
138
118
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
139
118
                         ArchDefinePpcsq)
140
118
              // powerpc64le automatically defaults to at least power8.
141
118
              .Cases("power8", "pwr8", "ppc64le",
142
118
                     ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
143
118
                         ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
144
118
                         ArchDefinePpcgr | ArchDefinePpcsq)
145
118
              .Cases("power9", "pwr9",
146
118
                     ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
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118
                         ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
148
118
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
149
118
              .Case("future",
150
118
                    ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
151
118
                        ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
152
118
                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
153
118
                        ArchDefinePpcsq)
154
118
              .Cases("8548", "e500", ArchDefineE500)
155
118
              .Default(ArchDefineNone);
156
118
    }
157
119
    return CPUKnown;
158
119
  }
159
160
5.65k
  StringRef getABI() const override { return ABI; }
161
162
  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
163
164
0
  bool isCLZForZeroUndef() const override { return false; }
165
166
  void getTargetDefines(const LangOptions &Opts,
167
                        MacroBuilder &Builder) const override;
168
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  bool
170
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
171
                 StringRef CPU,
172
                 const std::vector<std::string> &FeaturesVec) const override;
173
174
  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
175
176
  bool handleTargetFeatures(std::vector<std::string> &Features,
177
                            DiagnosticsEngine &Diags) override;
178
179
  bool hasFeature(StringRef Feature) const override;
180
181
  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
182
                         bool Enabled) const override;
183
184
  ArrayRef<const char *> getGCCRegNames() const override;
185
186
  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
187
188
  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
189
190
  bool validateAsmConstraint(const char *&Name,
191
351
                             TargetInfo::ConstraintInfo &Info) const override {
192
351
    switch (*Name) {
193
0
    default:
194
0
      return false;
195
0
    case 'O': // Zero
196
0
      break;
197
31
    case 'f': // Floating point register
198
31
      // Don't use floating point registers on soft float ABI.
199
31
      if (FloatABI == SoftFloat)
200
1
        return false;
201
30
      LLVM_FALLTHROUGH;
202
125
    case 'b': // Base register
203
125
      Info.setAllowsRegister();
204
125
      break;
205
30
    // FIXME: The following are added to allow parsing.
206
30
    // I just took a guess at what the actions should be.
207
30
    // Also, is more specific checking needed?  I.e. specific registers?
208
41
    case 'd': // Floating point register (containing 64-bit value)
209
41
    case 'v': // Altivec vector register
210
41
      // Don't use floating point and altivec vector registers
211
41
      // on soft float ABI
212
41
      if (FloatABI == SoftFloat)
213
2
        return false;
214
39
      Info.setAllowsRegister();
215
39
      break;
216
184
    case 'w':
217
184
      switch (Name[1]) {
218
184
      case 'd': // VSX vector register to hold vector double data
219
184
      case 'f': // VSX vector register to hold vector float data
220
184
      case 's': // VSX vector register to hold scalar double data
221
184
      case 'w': // VSX vector register to hold scalar double data
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184
      case 'a': // Any VSX register
223
184
      case 'c': // An individual CR bit
224
184
      case 'i': // FP or VSX register to hold 64-bit integers data
225
184
        break;
226
184
      default:
227
0
        return false;
228
184
      }
229
184
      Info.setAllowsRegister();
230
184
      Name++; // Skip over 'w'.
231
184
      break;
232
184
    case 'h': // `MQ', `CTR', or `LINK' register
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0
    case 'q': // `MQ' register
234
0
    case 'c': // `CTR' register
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0
    case 'l': // `LINK' register
236
0
    case 'x': // `CR' register (condition register) number 0
237
0
    case 'y': // `CR' register (condition register)
238
0
    case 'z': // `XER[CA]' carry bit (part of the XER register)
239
0
      Info.setAllowsRegister();
240
0
      break;
241
0
    case 'I': // Signed 16-bit constant
242
0
    case 'J': // Unsigned 16-bit constant shifted left 16 bits
243
0
              //  (use `L' instead for SImode constants)
244
0
    case 'K': // Unsigned 16-bit constant
245
0
    case 'L': // Signed 16-bit constant shifted left 16 bits
246
0
    case 'M': // Constant larger than 31
247
0
    case 'N': // Exact power of 2
248
0
    case 'P': // Constant whose negation is a signed 16-bit constant
249
0
    case 'G': // Floating point constant that can be loaded into a
250
0
              // register with one instruction per word
251
0
    case 'H': // Integer/Floating point constant that can be loaded
252
0
              // into a register using three instructions
253
0
      break;
254
0
    case 'm': // Memory operand. Note that on PowerPC targets, m can
255
0
              // include addresses that update the base register. It
256
0
              // is therefore only safe to use `m' in an asm statement
257
0
              // if that asm statement accesses the operand exactly once.
258
0
              // The asm statement must also use `%U<opno>' as a
259
0
              // placeholder for the "update" flag in the corresponding
260
0
              // load or store instruction. For example:
261
0
              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
262
0
              // is correct but:
263
0
              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
264
0
              // is not. Use es rather than m if you don't want the base
265
0
              // register to be updated.
266
0
    case 'e':
267
0
      if (Name[1] != 's')
268
0
        return false;
269
0
      // es: A "stable" memory operand; that is, one which does not
270
0
      // include any automodification of the base register. Unlike
271
0
      // `m', this constraint can be used in asm statements that
272
0
      // might access the operand several times, or that might not
273
0
      // access it at all.
274
0
      Info.setAllowsMemory();
275
0
      Name++; // Skip over 'e'.
276
0
      break;
277
0
    case 'Q': // Memory operand that is an offset from a register (it is
278
0
              // usually better to use `m' or `es' in asm statements)
279
0
    case 'Z': // Memory operand that is an indexed or indirect from a
280
0
              // register (it is usually better to use `m' or `es' in
281
0
              // asm statements)
282
0
      Info.setAllowsMemory();
283
0
      Info.setAllowsRegister();
284
0
      break;
285
0
    case 'R': // AIX TOC entry
286
0
    case 'a': // Address operand that is an indexed or indirect from a
287
0
              // register (`p' is preferable for asm statements)
288
0
    case 'S': // Constant suitable as a 64-bit mask operand
289
0
    case 'T': // Constant suitable as a 32-bit mask operand
290
0
    case 'U': // System V Release 4 small data area reference
291
0
    case 't': // AND masks that can be performed by two rldic{l, r}
292
0
              // instructions
293
0
    case 'W': // Vector constant that does not require memory
294
0
    case 'j': // Vector constant that is all zeros.
295
0
      break;
296
348
      // End FIXME.
297
348
    }
298
348
    return true;
299
348
  }
300
301
336
  std::string convertConstraint(const char *&Constraint) const override {
302
336
    std::string R;
303
336
    switch (*Constraint) {
304
39
    case 'e':
305
39
    case 'w':
306
39
      // Two-character constraint; add "^" hint for later parsing.
307
39
      R = std::string("^") + std::string(Constraint, 2);
308
39
      Constraint++;
309
39
      break;
310
297
    default:
311
297
      return TargetInfo::convertConstraint(Constraint);
312
39
    }
313
39
    return R;
314
39
  }
315
316
125
  const char *getClobbers() const override { return ""; }
317
4
  int getEHDataRegisterNumber(unsigned RegNo) const override {
318
4
    if (RegNo == 0)
319
2
      return 3;
320
2
    if (RegNo == 1)
321
2
      return 4;
322
0
    return -1;
323
0
  }
324
325
4
  bool hasSjLjLowering() const override { return true; }
326
327
48
  const char *getLongDoubleMangling() const override {
328
48
    if (LongDoubleWidth == 64)
329
6
      return "e";
330
42
    return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
331
42
               ? 
"g"36
332
42
               : 
"u9__ieee128"6
;
333
42
  }
334
44
  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
335
};
336
337
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
338
public:
339
  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
340
76
      : PPCTargetInfo(Triple, Opts) {
341
76
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
342
76
343
76
    switch (getTriple().getOS()) {
344
30
    case llvm::Triple::Linux:
345
30
    case llvm::Triple::FreeBSD:
346
30
    case llvm::Triple::NetBSD:
347
30
      SizeType = UnsignedInt;
348
30
      PtrDiffType = SignedInt;
349
30
      IntPtrType = SignedInt;
350
30
      break;
351
30
    case llvm::Triple::AIX:
352
18
      SizeType = UnsignedLong;
353
18
      PtrDiffType = SignedLong;
354
18
      IntPtrType = SignedLong;
355
18
      SuitableAlign = 64;
356
18
      break;
357
30
    default:
358
28
      break;
359
76
    }
360
76
361
76
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()74
||
Triple.isOSOpenBSD()72
||
362
76
        
Triple.getOS() == llvm::Triple::AIX69
||
Triple.isMusl()51
) {
363
25
      LongDoubleWidth = LongDoubleAlign = 64;
364
25
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
365
25
    }
366
76
367
76
    // PPC32 supports atomics up to 4 bytes.
368
76
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
369
76
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
340
58
      : PPCTargetInfo(Triple, Opts) {
341
58
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
342
58
343
58
    switch (getTriple().getOS()) {
344
30
    case llvm::Triple::Linux:
345
30
    case llvm::Triple::FreeBSD:
346
30
    case llvm::Triple::NetBSD:
347
30
      SizeType = UnsignedInt;
348
30
      PtrDiffType = SignedInt;
349
30
      IntPtrType = SignedInt;
350
30
      break;
351
30
    case llvm::Triple::AIX:
352
18
      SizeType = UnsignedLong;
353
18
      PtrDiffType = SignedLong;
354
18
      IntPtrType = SignedLong;
355
18
      SuitableAlign = 64;
356
18
      break;
357
30
    default:
358
10
      break;
359
58
    }
360
58
361
58
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()56
||
Triple.isOSOpenBSD()54
||
362
58
        
Triple.getOS() == llvm::Triple::AIX51
||
Triple.isMusl()33
) {
363
25
      LongDoubleWidth = LongDoubleAlign = 64;
364
25
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
365
25
    }
366
58
367
58
    // PPC32 supports atomics up to 4 bytes.
368
58
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
369
58
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
340
18
      : PPCTargetInfo(Triple, Opts) {
341
18
    resetDataLayout("E-m:e-p:32:32-i64:64-n32");
342
18
343
18
    switch (getTriple().getOS()) {
344
0
    case llvm::Triple::Linux:
345
0
    case llvm::Triple::FreeBSD:
346
0
    case llvm::Triple::NetBSD:
347
0
      SizeType = UnsignedInt;
348
0
      PtrDiffType = SignedInt;
349
0
      IntPtrType = SignedInt;
350
0
      break;
351
0
    case llvm::Triple::AIX:
352
0
      SizeType = UnsignedLong;
353
0
      PtrDiffType = SignedLong;
354
0
      IntPtrType = SignedLong;
355
0
      SuitableAlign = 64;
356
0
      break;
357
18
    default:
358
18
      break;
359
18
    }
360
18
361
18
    if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
362
18
        Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
363
0
      LongDoubleWidth = LongDoubleAlign = 64;
364
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
365
0
    }
366
18
367
18
    // PPC32 supports atomics up to 4 bytes.
368
18
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
369
18
  }
370
371
40
  BuiltinVaListKind getBuiltinVaListKind() const override {
372
40
    // This is the ELF definition, and is overridden by the Darwin sub-target
373
40
    return TargetInfo::PowerABIBuiltinVaList;
374
40
  }
375
};
376
377
// Note: ABI differences may eventually require us to have a separate
378
// TargetInfo for little endian.
379
class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
380
public:
381
  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
382
2.81k
      : PPCTargetInfo(Triple, Opts) {
383
2.81k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
384
2.81k
    IntMaxType = SignedLong;
385
2.81k
    Int64Type = SignedLong;
386
2.81k
387
2.81k
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
388
2.65k
      resetDataLayout("e-m:e-i64:64-n32:64");
389
2.65k
      ABI = "elfv2";
390
2.65k
    } else {
391
159
      resetDataLayout("E-m:e-i64:64-n32:64");
392
159
      ABI = "elfv1";
393
159
    }
394
2.81k
395
2.81k
    if (Triple.getOS() == llvm::Triple::AIX)
396
3
      SuitableAlign = 64;
397
2.81k
398
2.81k
    if (Triple.isOSFreeBSD() || 
Triple.getOS() == llvm::Triple::AIX2.81k
||
399
2.81k
        
Triple.isMusl()2.80k
) {
400
12
      LongDoubleWidth = LongDoubleAlign = 64;
401
12
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
402
12
    }
403
2.81k
404
2.81k
    // PPC64 supports atomics up to 8 bytes.
405
2.81k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
406
2.81k
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
382
229
      : PPCTargetInfo(Triple, Opts) {
383
229
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
384
229
    IntMaxType = SignedLong;
385
229
    Int64Type = SignedLong;
386
229
387
229
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
388
132
      resetDataLayout("e-m:e-i64:64-n32:64");
389
132
      ABI = "elfv2";
390
132
    } else {
391
97
      resetDataLayout("E-m:e-i64:64-n32:64");
392
97
      ABI = "elfv1";
393
97
    }
394
229
395
229
    if (Triple.getOS() == llvm::Triple::AIX)
396
3
      SuitableAlign = 64;
397
229
398
229
    if (Triple.isOSFreeBSD() || 
Triple.getOS() == llvm::Triple::AIX224
||
399
229
        
Triple.isMusl()221
) {
400
12
      LongDoubleWidth = LongDoubleAlign = 64;
401
12
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
402
12
    }
403
229
404
229
    // PPC64 supports atomics up to 8 bytes.
405
229
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
406
229
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
382
2.58k
      : PPCTargetInfo(Triple, Opts) {
383
2.58k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
384
2.58k
    IntMaxType = SignedLong;
385
2.58k
    Int64Type = SignedLong;
386
2.58k
387
2.58k
    if ((Triple.getArch() == llvm::Triple::ppc64le)) {
388
2.52k
      resetDataLayout("e-m:e-i64:64-n32:64");
389
2.52k
      ABI = "elfv2";
390
2.52k
    } else {
391
62
      resetDataLayout("E-m:e-i64:64-n32:64");
392
62
      ABI = "elfv1";
393
62
    }
394
2.58k
395
2.58k
    if (Triple.getOS() == llvm::Triple::AIX)
396
0
      SuitableAlign = 64;
397
2.58k
398
2.58k
    if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||
399
2.58k
        Triple.isMusl()) {
400
0
      LongDoubleWidth = LongDoubleAlign = 64;
401
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
402
0
    }
403
2.58k
404
2.58k
    // PPC64 supports atomics up to 8 bytes.
405
2.58k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
406
2.58k
  }
407
408
2.68k
  BuiltinVaListKind getBuiltinVaListKind() const override {
409
2.68k
    return TargetInfo::CharPtrBuiltinVaList;
410
2.68k
  }
411
412
  // PPC64 Linux-specific ABI options.
413
81
  bool setABI(const std::string &Name) override {
414
81
    if (Name == "elfv1" || 
Name == "elfv1-qpx"51
||
Name == "elfv2"46
) {
415
81
      ABI = Name;
416
81
      return true;
417
81
    }
418
0
    return false;
419
0
  }
420
421
0
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
422
0
    switch (CC) {
423
0
    case CC_Swift:
424
0
      return CCCR_OK;
425
0
    default:
426
0
      return CCCR_Warning;
427
0
    }
428
0
  }
429
};
430
431
class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
432
    : public DarwinTargetInfo<PPC32TargetInfo> {
433
public:
434
  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
435
7
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
436
7
    HasAlignMac68kSupport = true;
437
7
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
438
7
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
439
7
    LongLongAlign = 32;
440
7
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
441
7
  }
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
435
7
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
436
7
    HasAlignMac68kSupport = true;
437
7
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
438
7
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
439
7
    LongLongAlign = 32;
440
7
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
441
7
  }
Unexecuted instantiation: clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
442
443
6
  BuiltinVaListKind getBuiltinVaListKind() const override {
444
6
    return TargetInfo::CharPtrBuiltinVaList;
445
6
  }
446
};
447
448
class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
449
    : public DarwinTargetInfo<PPC64TargetInfo> {
450
public:
451
  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
452
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
453
1
    HasAlignMac68kSupport = true;
454
1
    resetDataLayout("E-m:o-i64:64-n32:64");
455
1
  }
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
452
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
453
1
    HasAlignMac68kSupport = true;
454
1
    resetDataLayout("E-m:o-i64:64-n32:64");
455
1
  }
Unexecuted instantiation: clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
456
};
457
458
class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
459
  public AIXTargetInfo<PPC32TargetInfo> {
460
public:
461
  using AIXTargetInfo::AIXTargetInfo;
462
2
  BuiltinVaListKind getBuiltinVaListKind() const override {
463
2
    return TargetInfo::CharPtrBuiltinVaList;
464
2
  }
465
};
466
467
class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
468
  public AIXTargetInfo<PPC64TargetInfo> {
469
public:
470
  using AIXTargetInfo::AIXTargetInfo;
471
};
472
473
} // namespace targets
474
} // namespace clang
475
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H