Coverage Report

Created: 2021-09-21 08:58

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/PPC.h
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Source (jump to first uncovered line)
1
//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14
#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16
#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
18
#include "clang/Basic/TargetOptions.h"
19
#include "llvm/ADT/Triple.h"
20
#include "llvm/ADT/StringSwitch.h"
21
#include "llvm/Support/Compiler.h"
22
23
namespace clang {
24
namespace targets {
25
26
// PPC abstract base class
27
class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29
  /// Flags for architecture specific defines.
30
  typedef enum {
31
    ArchDefineNone = 0,
32
    ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33
    ArchDefinePpcgr = 1 << 1,
34
    ArchDefinePpcsq = 1 << 2,
35
    ArchDefine440 = 1 << 3,
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    ArchDefine603 = 1 << 4,
37
    ArchDefine604 = 1 << 5,
38
    ArchDefinePwr4 = 1 << 6,
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    ArchDefinePwr5 = 1 << 7,
40
    ArchDefinePwr5x = 1 << 8,
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    ArchDefinePwr6 = 1 << 9,
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    ArchDefinePwr6x = 1 << 10,
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    ArchDefinePwr7 = 1 << 11,
44
    ArchDefinePwr8 = 1 << 12,
45
    ArchDefinePwr9 = 1 << 13,
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    ArchDefinePwr10 = 1 << 14,
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    ArchDefineFuture = 1 << 15,
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    ArchDefineA2 = 1 << 16,
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    ArchDefineE500 = 1 << 18
50
  } ArchDefineTypes;
51
52
  ArchDefineTypes ArchDefs = ArchDefineNone;
53
  static const Builtin::Info BuiltinInfo[];
54
  static const char *const GCCRegNames[];
55
  static const TargetInfo::GCCRegAlias GCCRegAliases[];
56
  std::string CPU;
57
  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58
59
  // Target cpu features.
60
  bool HasAltivec = false;
61
  bool HasMMA = false;
62
  bool HasROPProtect = false;
63
  bool HasPrivileged = false;
64
  bool HasVSX = false;
65
  bool HasP8Vector = false;
66
  bool HasP8Crypto = false;
67
  bool HasDirectMove = false;
68
  bool HasHTM = false;
69
  bool HasBPERMD = false;
70
  bool HasExtDiv = false;
71
  bool HasP9Vector = false;
72
  bool HasSPE = false;
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  bool PairedVectorMemops = false;
74
  bool HasP10Vector = false;
75
  bool HasPCRelativeMemops = false;
76
  bool HasPrefixInstrs = false;
77
  bool IsISA2_07 = false;
78
  bool IsISA3_0 = false;
79
  bool IsISA3_1 = false;
80
81
protected:
82
  std::string ABI;
83
84
public:
85
  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
86
4.40k
      : TargetInfo(Triple) {
87
4.40k
    SuitableAlign = 128;
88
4.40k
    SimdDefaultAlign = 128;
89
4.40k
    LongDoubleWidth = LongDoubleAlign = 128;
90
4.40k
    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
91
4.40k
    HasStrictFP = true;
92
4.40k
    HasIbm128 = true;
93
4.40k
  }
94
95
  // Set the language option for altivec based on our value.
96
  void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
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  // Note: GCC recognizes the following additional cpus:
99
  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
100
  //  821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
101
  bool isValidCPUName(StringRef Name) const override;
102
  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
103
104
382
  bool setCPU(const std::string &Name) override {
105
382
    bool CPUKnown = isValidCPUName(Name);
106
382
    if (CPUKnown) {
107
381
      CPU = Name;
108
109
      // CPU identification.
110
381
      ArchDefs =
111
381
          (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
112
381
              .Case("440", ArchDefineName)
113
381
              .Case("450", ArchDefineName | ArchDefine440)
114
381
              .Case("601", ArchDefineName)
115
381
              .Case("602", ArchDefineName | ArchDefinePpcgr)
116
381
              .Case("603", ArchDefineName | ArchDefinePpcgr)
117
381
              .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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381
              .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
119
381
              .Case("604", ArchDefineName | ArchDefinePpcgr)
120
381
              .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
121
381
              .Case("620", ArchDefineName | ArchDefinePpcgr)
122
381
              .Case("630", ArchDefineName | ArchDefinePpcgr)
123
381
              .Case("7400", ArchDefineName | ArchDefinePpcgr)
124
381
              .Case("7450", ArchDefineName | ArchDefinePpcgr)
125
381
              .Case("750", ArchDefineName | ArchDefinePpcgr)
126
381
              .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
127
381
                               ArchDefinePpcsq)
128
381
              .Case("a2", ArchDefineA2)
129
381
              .Cases("power3", "pwr3", ArchDefinePpcgr)
130
381
              .Cases("power4", "pwr4",
131
381
                     ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
132
381
              .Cases("power5", "pwr5",
133
381
                     ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
134
381
                         ArchDefinePpcsq)
135
381
              .Cases("power5x", "pwr5x",
136
381
                     ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
137
381
                         ArchDefinePpcgr | ArchDefinePpcsq)
138
381
              .Cases("power6", "pwr6",
139
381
                     ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
140
381
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
141
381
              .Cases("power6x", "pwr6x",
142
381
                     ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
143
381
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
144
381
                         ArchDefinePpcsq)
145
381
              .Cases("power7", "pwr7",
146
381
                     ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
147
381
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
148
381
                         ArchDefinePpcsq)
149
              // powerpc64le automatically defaults to at least power8.
150
381
              .Cases("power8", "pwr8", "ppc64le",
151
381
                     ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
152
381
                         ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
153
381
                         ArchDefinePpcgr | ArchDefinePpcsq)
154
381
              .Cases("power9", "pwr9",
155
381
                     ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
156
381
                         ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
157
381
                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
158
381
              .Cases("power10", "pwr10",
159
381
                     ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
160
381
                         ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
161
381
                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
162
381
                         ArchDefinePpcsq)
163
381
              .Case("future",
164
381
                    ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
165
381
                        ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
166
381
                        ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
167
381
                        ArchDefinePpcgr | ArchDefinePpcsq)
168
381
              .Cases("8548", "e500", ArchDefineE500)
169
381
              .Default(ArchDefineNone);
170
381
    }
171
382
    return CPUKnown;
172
382
  }
173
174
9.03k
  StringRef getABI() const override { return ABI; }
175
176
  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
177
178
16
  bool isCLZForZeroUndef() const override { return false; }
179
180
  void getTargetDefines(const LangOptions &Opts,
181
                        MacroBuilder &Builder) const override;
182
183
  bool
184
  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
185
                 StringRef CPU,
186
                 const std::vector<std::string> &FeaturesVec) const override;
187
188
  void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
189
  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
190
191
  bool handleTargetFeatures(std::vector<std::string> &Features,
192
                            DiagnosticsEngine &Diags) override;
193
194
  bool hasFeature(StringRef Feature) const override;
195
196
  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
197
                         bool Enabled) const override;
198
199
  ArrayRef<const char *> getGCCRegNames() const override;
200
201
  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
202
203
  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
204
205
  bool validateAsmConstraint(const char *&Name,
206
367
                             TargetInfo::ConstraintInfo &Info) const override {
207
367
    switch (*Name) {
208
0
    default:
209
0
      return false;
210
0
    case 'O': // Zero
211
0
      break;
212
35
    case 'f': // Floating point register
213
      // Don't use floating point registers on soft float ABI.
214
35
      if (FloatABI == SoftFloat)
215
1
        return false;
216
35
      
LLVM_FALLTHROUGH34
;34
217
133
    case 'b': // Base register
218
133
      Info.setAllowsRegister();
219
133
      break;
220
    // FIXME: The following are added to allow parsing.
221
    // I just took a guess at what the actions should be.
222
    // Also, is more specific checking needed?  I.e. specific registers?
223
1
    case 'd': // Floating point register (containing 64-bit value)
224
41
    case 'v': // Altivec vector register
225
      // Don't use floating point and altivec vector registers
226
      // on soft float ABI
227
41
      if (FloatABI == SoftFloat)
228
2
        return false;
229
39
      Info.setAllowsRegister();
230
39
      break;
231
188
    case 'w':
232
188
      switch (Name[1]) {
233
0
      case 'd': // VSX vector register to hold vector double data
234
0
      case 'f': // VSX vector register to hold vector float data
235
6
      case 's': // VSX vector register to hold scalar double data
236
12
      case 'w': // VSX vector register to hold scalar double data
237
170
      case 'a': // Any VSX register
238
188
      case 'c': // An individual CR bit
239
188
      case 'i': // FP or VSX register to hold 64-bit integers data
240
188
        break;
241
0
      default:
242
0
        return false;
243
188
      }
244
188
      Info.setAllowsRegister();
245
188
      Name++; // Skip over 'w'.
246
188
      break;
247
0
    case 'h': // `MQ', `CTR', or `LINK' register
248
0
    case 'q': // `MQ' register
249
0
    case 'c': // `CTR' register
250
0
    case 'l': // `LINK' register
251
0
    case 'x': // `CR' register (condition register) number 0
252
0
    case 'y': // `CR' register (condition register)
253
0
    case 'z': // `XER[CA]' carry bit (part of the XER register)
254
0
      Info.setAllowsRegister();
255
0
      break;
256
0
    case 'I': // Signed 16-bit constant
257
0
    case 'J': // Unsigned 16-bit constant shifted left 16 bits
258
              //  (use `L' instead for SImode constants)
259
0
    case 'K': // Unsigned 16-bit constant
260
0
    case 'L': // Signed 16-bit constant shifted left 16 bits
261
0
    case 'M': // Constant larger than 31
262
0
    case 'N': // Exact power of 2
263
0
    case 'P': // Constant whose negation is a signed 16-bit constant
264
0
    case 'G': // Floating point constant that can be loaded into a
265
              // register with one instruction per word
266
0
    case 'H': // Integer/Floating point constant that can be loaded
267
              // into a register using three instructions
268
0
      break;
269
0
    case 'm': // Memory operand. Note that on PowerPC targets, m can
270
              // include addresses that update the base register. It
271
              // is therefore only safe to use `m' in an asm statement
272
              // if that asm statement accesses the operand exactly once.
273
              // The asm statement must also use `%U<opno>' as a
274
              // placeholder for the "update" flag in the corresponding
275
              // load or store instruction. For example:
276
              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
277
              // is correct but:
278
              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
279
              // is not. Use es rather than m if you don't want the base
280
              // register to be updated.
281
0
    case 'e':
282
0
      if (Name[1] != 's')
283
0
        return false;
284
      // es: A "stable" memory operand; that is, one which does not
285
      // include any automodification of the base register. Unlike
286
      // `m', this constraint can be used in asm statements that
287
      // might access the operand several times, or that might not
288
      // access it at all.
289
0
      Info.setAllowsMemory();
290
0
      Name++; // Skip over 'e'.
291
0
      break;
292
0
    case 'Q': // Memory operand that is an offset from a register (it is
293
              // usually better to use `m' or `es' in asm statements)
294
0
      Info.setAllowsRegister();
295
0
      LLVM_FALLTHROUGH;
296
4
    case 'Z': // Memory operand that is an indexed or indirect from a
297
              // register (it is usually better to use `m' or `es' in
298
              // asm statements)
299
4
      Info.setAllowsMemory();
300
4
      break;
301
0
    case 'R': // AIX TOC entry
302
0
    case 'a': // Address operand that is an indexed or indirect from a
303
              // register (`p' is preferable for asm statements)
304
0
    case 'S': // Constant suitable as a 64-bit mask operand
305
0
    case 'T': // Constant suitable as a 32-bit mask operand
306
0
    case 'U': // System V Release 4 small data area reference
307
0
    case 't': // AND masks that can be performed by two rldic{l, r}
308
              // instructions
309
0
    case 'W': // Vector constant that does not require memory
310
0
    case 'j': // Vector constant that is all zeros.
311
0
      break;
312
      // End FIXME.
313
367
    }
314
364
    return true;
315
367
  }
316
317
338
  std::string convertConstraint(const char *&Constraint) const override {
318
338
    std::string R;
319
338
    switch (*Constraint) {
320
0
    case 'e':
321
39
    case 'w':
322
      // Two-character constraint; add "^" hint for later parsing.
323
39
      R = std::string("^") + std::string(Constraint, 2);
324
39
      Constraint++;
325
39
      break;
326
299
    default:
327
299
      return TargetInfo::convertConstraint(Constraint);
328
338
    }
329
39
    return R;
330
338
  }
331
332
142
  const char *getClobbers() const override { return ""; }
333
4
  int getEHDataRegisterNumber(unsigned RegNo) const override {
334
4
    if (RegNo == 0)
335
2
      return 3;
336
2
    if (RegNo == 1)
337
2
      return 4;
338
0
    return -1;
339
2
  }
340
341
4
  bool hasSjLjLowering() const override { return true; }
342
343
241
  const char *getLongDoubleMangling() const override {
344
241
    if (LongDoubleWidth == 64)
345
6
      return "e";
346
235
    return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
347
235
               ? 
"g"229
348
235
               : 
"u9__ieee128"6
;
349
241
  }
350
44
  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
351
44
  const char *getIbm128Mangling() const override { return "g"; }
352
353
32
  bool hasExtIntType() const override { return true; }
354
355
0
  bool isSPRegName(StringRef RegName) const override {
356
0
    return RegName.equals("r1") || RegName.equals("x1");
357
0
  }
358
};
359
360
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
361
public:
362
  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
363
276
      : PPCTargetInfo(Triple, Opts) {
364
276
    if (Triple.isOSAIX())
365
144
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
366
132
    else if (Triple.getArch() == llvm::Triple::ppcle)
367
11
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
368
121
    else
369
121
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
370
371
276
    switch (getTriple().getOS()) {
372
38
    case llvm::Triple::Linux:
373
42
    case llvm::Triple::FreeBSD:
374
45
    case llvm::Triple::NetBSD:
375
45
      SizeType = UnsignedInt;
376
45
      PtrDiffType = SignedInt;
377
45
      IntPtrType = SignedInt;
378
45
      break;
379
144
    case llvm::Triple::AIX:
380
144
      SizeType = UnsignedLong;
381
144
      PtrDiffType = SignedLong;
382
144
      IntPtrType = SignedLong;
383
144
      LongDoubleWidth = 64;
384
144
      LongDoubleAlign = DoubleAlign = 32;
385
144
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
386
144
      break;
387
87
    default:
388
87
      break;
389
276
    }
390
391
276
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()272
||
Triple.isOSOpenBSD()269
||
392
276
        
Triple.isMusl()261
) {
393
15
      LongDoubleWidth = LongDoubleAlign = 64;
394
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
395
15
    }
396
397
    // PPC32 supports atomics up to 4 bytes.
398
276
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
399
276
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
363
203
      : PPCTargetInfo(Triple, Opts) {
364
203
    if (Triple.isOSAIX())
365
144
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
366
59
    else if (Triple.getArch() == llvm::Triple::ppcle)
367
4
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
368
55
    else
369
55
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
370
371
203
    switch (getTriple().getOS()) {
372
38
    case llvm::Triple::Linux:
373
42
    case llvm::Triple::FreeBSD:
374
45
    case llvm::Triple::NetBSD:
375
45
      SizeType = UnsignedInt;
376
45
      PtrDiffType = SignedInt;
377
45
      IntPtrType = SignedInt;
378
45
      break;
379
144
    case llvm::Triple::AIX:
380
144
      SizeType = UnsignedLong;
381
144
      PtrDiffType = SignedLong;
382
144
      IntPtrType = SignedLong;
383
144
      LongDoubleWidth = 64;
384
144
      LongDoubleAlign = DoubleAlign = 32;
385
144
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
386
144
      break;
387
14
    default:
388
14
      break;
389
203
    }
390
391
203
    if (Triple.isOSFreeBSD() || 
Triple.isOSNetBSD()199
||
Triple.isOSOpenBSD()196
||
392
203
        
Triple.isMusl()188
) {
393
15
      LongDoubleWidth = LongDoubleAlign = 64;
394
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
395
15
    }
396
397
    // PPC32 supports atomics up to 4 bytes.
398
203
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
399
203
  }
clang::targets::PPC32TargetInfo::PPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
363
73
      : PPCTargetInfo(Triple, Opts) {
364
73
    if (Triple.isOSAIX())
365
0
      resetDataLayout("E-m:a-p:32:32-i64:64-n32");
366
73
    else if (Triple.getArch() == llvm::Triple::ppcle)
367
7
      resetDataLayout("e-m:e-p:32:32-i64:64-n32");
368
66
    else
369
66
      resetDataLayout("E-m:e-p:32:32-i64:64-n32");
370
371
73
    switch (getTriple().getOS()) {
372
0
    case llvm::Triple::Linux:
373
0
    case llvm::Triple::FreeBSD:
374
0
    case llvm::Triple::NetBSD:
375
0
      SizeType = UnsignedInt;
376
0
      PtrDiffType = SignedInt;
377
0
      IntPtrType = SignedInt;
378
0
      break;
379
0
    case llvm::Triple::AIX:
380
0
      SizeType = UnsignedLong;
381
0
      PtrDiffType = SignedLong;
382
0
      IntPtrType = SignedLong;
383
0
      LongDoubleWidth = 64;
384
0
      LongDoubleAlign = DoubleAlign = 32;
385
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
386
0
      break;
387
73
    default:
388
73
      break;
389
73
    }
390
391
73
    if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
392
73
        Triple.isMusl()) {
393
0
      LongDoubleWidth = LongDoubleAlign = 64;
394
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
395
0
    }
396
397
    // PPC32 supports atomics up to 4 bytes.
398
73
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
399
73
  }
400
401
115
  BuiltinVaListKind getBuiltinVaListKind() const override {
402
    // This is the ELF definition, and is overridden by the Darwin sub-target
403
115
    return TargetInfo::PowerABIBuiltinVaList;
404
115
  }
405
};
406
407
// Note: ABI differences may eventually require us to have a separate
408
// TargetInfo for little endian.
409
class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
410
public:
411
  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
412
4.13k
      : PPCTargetInfo(Triple, Opts) {
413
4.13k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
414
4.13k
    IntMaxType = SignedLong;
415
4.13k
    Int64Type = SignedLong;
416
4.13k
    std::string DataLayout = "";
417
418
4.13k
    if (Triple.isOSAIX()) {
419
      // TODO: Set appropriate ABI for AIX platform.
420
119
      DataLayout = "E-m:a-i64:64-n32:64";
421
119
      LongDoubleWidth = 64;
422
119
      LongDoubleAlign = DoubleAlign = 32;
423
119
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
424
4.01k
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
425
3.78k
      DataLayout = "e-m:e-i64:64-n32:64";
426
3.78k
      ABI = "elfv2";
427
3.78k
    } else {
428
225
      DataLayout = "E-m:e-i64:64-n32:64";
429
225
      ABI = "elfv1";
430
225
    }
431
432
4.13k
    if (Triple.isOSFreeBSD() || 
Triple.isOSOpenBSD()4.12k
||
Triple.isMusl()4.12k
) {
433
15
      LongDoubleWidth = LongDoubleAlign = 64;
434
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
435
15
    }
436
437
4.13k
    if (Triple.isOSAIX() || 
Triple.isOSLinux()4.01k
)
438
442
      DataLayout += "-S128-v256:256:256-v512:512:512";
439
4.13k
    resetDataLayout(DataLayout);
440
441
    // PPC64 supports atomics up to 8 bytes.
442
4.13k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
443
4.13k
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
412
459
      : PPCTargetInfo(Triple, Opts) {
413
459
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
414
459
    IntMaxType = SignedLong;
415
459
    Int64Type = SignedLong;
416
459
    std::string DataLayout = "";
417
418
459
    if (Triple.isOSAIX()) {
419
      // TODO: Set appropriate ABI for AIX platform.
420
119
      DataLayout = "E-m:a-i64:64-n32:64";
421
119
      LongDoubleWidth = 64;
422
119
      LongDoubleAlign = DoubleAlign = 32;
423
119
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
424
340
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
425
228
      DataLayout = "e-m:e-i64:64-n32:64";
426
228
      ABI = "elfv2";
427
228
    } else {
428
112
      DataLayout = "E-m:e-i64:64-n32:64";
429
112
      ABI = "elfv1";
430
112
    }
431
432
459
    if (Triple.isOSFreeBSD() || 
Triple.isOSOpenBSD()451
||
Triple.isMusl()448
) {
433
15
      LongDoubleWidth = LongDoubleAlign = 64;
434
15
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
435
15
    }
436
437
459
    if (Triple.isOSAIX() || 
Triple.isOSLinux()340
)
438
442
      DataLayout += "-S128-v256:256:256-v512:512:512";
439
459
    resetDataLayout(DataLayout);
440
441
    // PPC64 supports atomics up to 8 bytes.
442
459
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
443
459
  }
clang::targets::PPC64TargetInfo::PPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
412
3.67k
      : PPCTargetInfo(Triple, Opts) {
413
3.67k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
414
3.67k
    IntMaxType = SignedLong;
415
3.67k
    Int64Type = SignedLong;
416
3.67k
    std::string DataLayout = "";
417
418
3.67k
    if (Triple.isOSAIX()) {
419
      // TODO: Set appropriate ABI for AIX platform.
420
0
      DataLayout = "E-m:a-i64:64-n32:64";
421
0
      LongDoubleWidth = 64;
422
0
      LongDoubleAlign = DoubleAlign = 32;
423
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
424
3.67k
    } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
425
3.56k
      DataLayout = "e-m:e-i64:64-n32:64";
426
3.56k
      ABI = "elfv2";
427
3.56k
    } else {
428
113
      DataLayout = "E-m:e-i64:64-n32:64";
429
113
      ABI = "elfv1";
430
113
    }
431
432
3.67k
    if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
433
0
      LongDoubleWidth = LongDoubleAlign = 64;
434
0
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
435
0
    }
436
437
3.67k
    if (Triple.isOSAIX() || Triple.isOSLinux())
438
0
      DataLayout += "-S128-v256:256:256-v512:512:512";
439
3.67k
    resetDataLayout(DataLayout);
440
441
    // PPC64 supports atomics up to 8 bytes.
442
3.67k
    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
443
3.67k
  }
444
445
3.89k
  BuiltinVaListKind getBuiltinVaListKind() const override {
446
3.89k
    return TargetInfo::CharPtrBuiltinVaList;
447
3.89k
  }
448
449
  // PPC64 Linux-specific ABI options.
450
119
  bool setABI(const std::string &Name) override {
451
119
    if (Name == "elfv1" || 
Name == "elfv2"81
) {
452
119
      ABI = Name;
453
119
      return true;
454
119
    }
455
0
    return false;
456
119
  }
457
458
552
  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
459
552
    switch (CC) {
460
0
    case CC_Swift:
461
0
      return CCCR_OK;
462
552
    case CC_SwiftAsync:
463
552
      return CCCR_Error;
464
0
    default:
465
0
      return CCCR_Warning;
466
552
    }
467
552
  }
468
};
469
470
class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
471
    : public DarwinTargetInfo<PPC32TargetInfo> {
472
public:
473
  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
474
6
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
475
6
    HasAlignMac68kSupport = true;
476
6
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
477
6
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
478
6
    LongLongAlign = 32;
479
6
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
480
6
  }
clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
474
6
      : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
475
6
    HasAlignMac68kSupport = true;
476
6
    BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
477
6
    PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
478
6
    LongLongAlign = 32;
479
6
    resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
480
6
  }
Unexecuted instantiation: clang::targets::DarwinPPC32TargetInfo::DarwinPPC32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
481
482
5
  BuiltinVaListKind getBuiltinVaListKind() const override {
483
5
    return TargetInfo::CharPtrBuiltinVaList;
484
5
  }
485
};
486
487
class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
488
    : public DarwinTargetInfo<PPC64TargetInfo> {
489
public:
490
  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
491
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
492
1
    HasAlignMac68kSupport = true;
493
1
    resetDataLayout("E-m:o-i64:64-n32:64", "_");
494
1
  }
clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
491
1
      : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
492
1
    HasAlignMac68kSupport = true;
493
1
    resetDataLayout("E-m:o-i64:64-n32:64", "_");
494
1
  }
Unexecuted instantiation: clang::targets::DarwinPPC64TargetInfo::DarwinPPC64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
495
};
496
497
class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
498
  public AIXTargetInfo<PPC32TargetInfo> {
499
public:
500
  using AIXTargetInfo::AIXTargetInfo;
501
123
  BuiltinVaListKind getBuiltinVaListKind() const override {
502
123
    return TargetInfo::CharPtrBuiltinVaList;
503
123
  }
504
};
505
506
class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
507
  public AIXTargetInfo<PPC64TargetInfo> {
508
public:
509
  using AIXTargetInfo::AIXTargetInfo;
510
};
511
512
} // namespace targets
513
} // namespace clang
514
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H