/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
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1 | | //===--- RISCV.cpp - Implement RISCV target feature support ---------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file implements RISCV TargetInfo objects. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "RISCV.h" |
14 | | #include "clang/Basic/MacroBuilder.h" |
15 | | #include "llvm/ADT/StringSwitch.h" |
16 | | #include "llvm/Support/TargetParser.h" |
17 | | |
18 | | using namespace clang; |
19 | | using namespace clang::targets; |
20 | | |
21 | 768 | ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const { |
22 | 768 | static const char *const GCCRegNames[] = { |
23 | | // Integer registers |
24 | 768 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", |
25 | 768 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", |
26 | 768 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", |
27 | 768 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", |
28 | | |
29 | | // Floating point registers |
30 | 768 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
31 | 768 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
32 | 768 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
33 | 768 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; |
34 | 768 | return llvm::makeArrayRef(GCCRegNames); |
35 | 768 | } |
36 | | |
37 | 512 | ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const { |
38 | 512 | static const TargetInfo::GCCRegAlias GCCRegAliases[] = { |
39 | 512 | {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"}, |
40 | 512 | {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"}, |
41 | 512 | {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"}, |
42 | 512 | {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"}, |
43 | 512 | {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"}, |
44 | 512 | {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"}, |
45 | 512 | {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"}, |
46 | 512 | {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"}, |
47 | 512 | {{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"}, |
48 | 512 | {{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"}, |
49 | 512 | {{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"}, |
50 | 512 | {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"}, |
51 | 512 | {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"}, |
52 | 512 | {{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"}, |
53 | 512 | {{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"}, |
54 | 512 | {{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}}; |
55 | 512 | return llvm::makeArrayRef(GCCRegAliases); |
56 | 512 | } |
57 | | |
58 | | bool RISCVTargetInfo::validateAsmConstraint( |
59 | 44 | const char *&Name, TargetInfo::ConstraintInfo &Info) const { |
60 | 44 | switch (*Name) { |
61 | 0 | default: |
62 | 0 | return false; |
63 | 12 | case 'I': |
64 | | // A 12-bit signed immediate. |
65 | 12 | Info.setRequiresImmediate(-2048, 2047); |
66 | 12 | return true; |
67 | 8 | case 'J': |
68 | | // Integer zero. |
69 | 8 | Info.setRequiresImmediate(0); |
70 | 8 | return true; |
71 | 12 | case 'K': |
72 | | // A 5-bit unsigned immediate for CSR access instructions. |
73 | 12 | Info.setRequiresImmediate(0, 31); |
74 | 12 | return true; |
75 | 8 | case 'f': |
76 | | // A floating-point register. |
77 | 8 | Info.setAllowsRegister(); |
78 | 8 | return true; |
79 | 4 | case 'A': |
80 | | // An address that is held in a general-purpose register. |
81 | 4 | Info.setAllowsMemory(); |
82 | 4 | return true; |
83 | 44 | } |
84 | 44 | } |
85 | | |
86 | | void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, |
87 | 151 | MacroBuilder &Builder) const { |
88 | 151 | Builder.defineMacro("__ELF__"); |
89 | 151 | Builder.defineMacro("__riscv"); |
90 | 151 | bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64; |
91 | 80 | Builder.defineMacro("__riscv_xlen", Is64Bit ? "64"71 : "32"); |
92 | 151 | StringRef CodeModel = getTargetOpts().CodeModel; |
93 | 151 | if (CodeModel == "default") |
94 | 141 | CodeModel = "small"; |
95 | | |
96 | 151 | if (CodeModel == "small") |
97 | 145 | Builder.defineMacro("__riscv_cmodel_medlow"); |
98 | 6 | else if (CodeModel == "medium") |
99 | 4 | Builder.defineMacro("__riscv_cmodel_medany"); |
100 | | |
101 | 151 | StringRef ABIName = getABI(); |
102 | 151 | if (ABIName == "ilp32f" || ABIName == "lp64f"145 ) |
103 | 11 | Builder.defineMacro("__riscv_float_abi_single"); |
104 | 140 | else if (ABIName == "ilp32d" || ABIName == "lp64d"128 ) |
105 | 18 | Builder.defineMacro("__riscv_float_abi_double"); |
106 | 122 | else |
107 | 122 | Builder.defineMacro("__riscv_float_abi_soft"); |
108 | | |
109 | 151 | if (ABIName == "ilp32e") |
110 | 0 | Builder.defineMacro("__riscv_abi_rve"); |
111 | | |
112 | 151 | Builder.defineMacro("__riscv_arch_test"); |
113 | 151 | Builder.defineMacro("__riscv_i", "2000000"); |
114 | | |
115 | 151 | if (HasM) { |
116 | 23 | Builder.defineMacro("__riscv_m", "2000000"); |
117 | 23 | Builder.defineMacro("__riscv_mul"); |
118 | 23 | Builder.defineMacro("__riscv_div"); |
119 | 23 | Builder.defineMacro("__riscv_muldiv"); |
120 | 23 | } |
121 | | |
122 | 151 | if (HasA) { |
123 | 25 | Builder.defineMacro("__riscv_a", "2000000"); |
124 | 25 | Builder.defineMacro("__riscv_atomic"); |
125 | 25 | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); |
126 | 25 | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); |
127 | 25 | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); |
128 | 25 | if (Is64Bit) |
129 | 12 | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); |
130 | 25 | } |
131 | | |
132 | 151 | if (HasF || HasD129 ) { |
133 | 31 | Builder.defineMacro("__riscv_f", "2000000"); |
134 | 20 | Builder.defineMacro("__riscv_flen", HasD ? "64" : "32"11 ); |
135 | 31 | Builder.defineMacro("__riscv_fdiv"); |
136 | 31 | Builder.defineMacro("__riscv_fsqrt"); |
137 | 31 | } |
138 | | |
139 | 151 | if (HasD) |
140 | 20 | Builder.defineMacro("__riscv_d", "2000000"); |
141 | | |
142 | 151 | if (HasC) { |
143 | 23 | Builder.defineMacro("__riscv_c", "2000000"); |
144 | 23 | Builder.defineMacro("__riscv_compressed"); |
145 | 23 | } |
146 | | |
147 | 151 | if (HasB) { |
148 | 2 | Builder.defineMacro("__riscv_b", "93000"); |
149 | 2 | Builder.defineMacro("__riscv_bitmanip"); |
150 | 2 | } |
151 | | |
152 | 151 | if (HasV) { |
153 | 6 | Builder.defineMacro("__riscv_v", "1000000"); |
154 | 6 | Builder.defineMacro("__riscv_vector"); |
155 | 6 | } |
156 | | |
157 | 151 | if (HasZba) |
158 | 4 | Builder.defineMacro("__riscv_zba", "93000"); |
159 | | |
160 | 151 | if (HasZbb) |
161 | 4 | Builder.defineMacro("__riscv_zbb", "93000"); |
162 | | |
163 | 151 | if (HasZbc) |
164 | 4 | Builder.defineMacro("__riscv_zbc", "93000"); |
165 | | |
166 | 151 | if (HasZbe) |
167 | 4 | Builder.defineMacro("__riscv_zbe", "93000"); |
168 | | |
169 | 151 | if (HasZbf) |
170 | 4 | Builder.defineMacro("__riscv_zbf", "93000"); |
171 | | |
172 | 151 | if (HasZbm) |
173 | 4 | Builder.defineMacro("__riscv_zbm", "93000"); |
174 | | |
175 | 151 | if (HasZbp) |
176 | 4 | Builder.defineMacro("__riscv_zbp", "93000"); |
177 | | |
178 | 151 | if (HasZbproposedc) |
179 | 2 | Builder.defineMacro("__riscv_zbproposedc", "93000"); |
180 | | |
181 | 151 | if (HasZbr) |
182 | 4 | Builder.defineMacro("__riscv_zbr", "93000"); |
183 | | |
184 | 151 | if (HasZbs) |
185 | 4 | Builder.defineMacro("__riscv_zbs", "93000"); |
186 | | |
187 | 151 | if (HasZbt) |
188 | 4 | Builder.defineMacro("__riscv_zbt", "93000"); |
189 | | |
190 | 151 | if (HasZfh) |
191 | 2 | Builder.defineMacro("__riscv_zfh", "1000"); |
192 | | |
193 | 151 | if (HasZvamo) |
194 | 6 | Builder.defineMacro("__riscv_zvamo", "1000000"); |
195 | | |
196 | 151 | if (HasZvlsseg) |
197 | 6 | Builder.defineMacro("__riscv_zvlsseg", "1000000"); |
198 | 151 | } |
199 | | |
200 | | /// Return true if has this feature, need to sync with handleTargetFeatures. |
201 | 80 | bool RISCVTargetInfo::hasFeature(StringRef Feature) const { |
202 | 80 | bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64; |
203 | 80 | return llvm::StringSwitch<bool>(Feature) |
204 | 80 | .Case("riscv", true) |
205 | 80 | .Case("riscv32", !Is64Bit) |
206 | 80 | .Case("riscv64", Is64Bit) |
207 | 80 | .Case("m", HasM) |
208 | 80 | .Case("a", HasA) |
209 | 80 | .Case("f", HasF) |
210 | 80 | .Case("d", HasD) |
211 | 80 | .Case("c", HasC) |
212 | 80 | .Case("experimental-b", HasB) |
213 | 80 | .Case("experimental-v", HasV) |
214 | 80 | .Case("experimental-zba", HasZba) |
215 | 80 | .Case("experimental-zbb", HasZbb) |
216 | 80 | .Case("experimental-zbc", HasZbc) |
217 | 80 | .Case("experimental-zbe", HasZbe) |
218 | 80 | .Case("experimental-zbf", HasZbf) |
219 | 80 | .Case("experimental-zbm", HasZbm) |
220 | 80 | .Case("experimental-zbp", HasZbp) |
221 | 80 | .Case("experimental-zbproposedc", HasZbproposedc) |
222 | 80 | .Case("experimental-zbr", HasZbr) |
223 | 80 | .Case("experimental-zbs", HasZbs) |
224 | 80 | .Case("experimental-zbt", HasZbt) |
225 | 80 | .Case("experimental-zfh", HasZfh) |
226 | 80 | .Case("experimental-zvamo", HasZvamo) |
227 | 80 | .Case("experimental-zvlsseg", HasZvlsseg) |
228 | 80 | .Default(false); |
229 | 80 | } |
230 | | |
231 | | /// Perform initialization based on the user configured set of features. |
232 | | bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, |
233 | 151 | DiagnosticsEngine &Diags) { |
234 | 340 | for (const auto &Feature : Features) { |
235 | 340 | if (Feature == "+m") |
236 | 23 | HasM = true; |
237 | 317 | else if (Feature == "+a") |
238 | 25 | HasA = true; |
239 | 292 | else if (Feature == "+f") |
240 | 22 | HasF = true; |
241 | 270 | else if (Feature == "+d") |
242 | 20 | HasD = true; |
243 | 250 | else if (Feature == "+c") |
244 | 23 | HasC = true; |
245 | 227 | else if (Feature == "+experimental-b") |
246 | 2 | HasB = true; |
247 | 225 | else if (Feature == "+experimental-v") |
248 | 6 | HasV = true; |
249 | 219 | else if (Feature == "+experimental-zba") |
250 | 4 | HasZba = true; |
251 | 215 | else if (Feature == "+experimental-zbb") |
252 | 4 | HasZbb = true; |
253 | 211 | else if (Feature == "+experimental-zbc") |
254 | 4 | HasZbc = true; |
255 | 207 | else if (Feature == "+experimental-zbe") |
256 | 4 | HasZbe = true; |
257 | 203 | else if (Feature == "+experimental-zbf") |
258 | 4 | HasZbf = true; |
259 | 199 | else if (Feature == "+experimental-zbm") |
260 | 4 | HasZbm = true; |
261 | 195 | else if (Feature == "+experimental-zbp") |
262 | 4 | HasZbp = true; |
263 | 191 | else if (Feature == "+experimental-zbproposedc") |
264 | 2 | HasZbproposedc = true; |
265 | 189 | else if (Feature == "+experimental-zbr") |
266 | 4 | HasZbr = true; |
267 | 185 | else if (Feature == "+experimental-zbs") |
268 | 4 | HasZbs = true; |
269 | 181 | else if (Feature == "+experimental-zbt") |
270 | 4 | HasZbt = true; |
271 | 177 | else if (Feature == "+experimental-zfh") |
272 | 2 | HasZfh = true; |
273 | 175 | else if (Feature == "+experimental-zvamo") |
274 | 6 | HasZvamo = true; |
275 | 169 | else if (Feature == "+experimental-zvlsseg") |
276 | 6 | HasZvlsseg = true; |
277 | 340 | } |
278 | | |
279 | 151 | return true; |
280 | 151 | } |
281 | | |
282 | 1 | bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const { |
283 | 1 | return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), |
284 | 1 | /*Is64Bit=*/false); |
285 | 1 | } |
286 | | |
287 | | void RISCV32TargetInfo::fillValidCPUList( |
288 | 1 | SmallVectorImpl<StringRef> &Values) const { |
289 | 1 | llvm::RISCV::fillValidCPUArchList(Values, false); |
290 | 1 | } |
291 | | |
292 | 1 | bool RISCV32TargetInfo::isValidTuneCPUName(StringRef Name) const { |
293 | 1 | return llvm::RISCV::checkTuneCPUKind( |
294 | 1 | llvm::RISCV::parseTuneCPUKind(Name, false), |
295 | 1 | /*Is64Bit=*/false); |
296 | 1 | } |
297 | | |
298 | | void RISCV32TargetInfo::fillValidTuneCPUList( |
299 | 1 | SmallVectorImpl<StringRef> &Values) const { |
300 | 1 | llvm::RISCV::fillValidTuneCPUArchList(Values, false); |
301 | 1 | } |
302 | | |
303 | 1 | bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const { |
304 | 1 | return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), |
305 | 1 | /*Is64Bit=*/true); |
306 | 1 | } |
307 | | |
308 | | void RISCV64TargetInfo::fillValidCPUList( |
309 | 1 | SmallVectorImpl<StringRef> &Values) const { |
310 | 1 | llvm::RISCV::fillValidCPUArchList(Values, true); |
311 | 1 | } |
312 | | |
313 | 1 | bool RISCV64TargetInfo::isValidTuneCPUName(StringRef Name) const { |
314 | 1 | return llvm::RISCV::checkTuneCPUKind( |
315 | 1 | llvm::RISCV::parseTuneCPUKind(Name, true), |
316 | 1 | /*Is64Bit=*/true); |
317 | 1 | } |
318 | | |
319 | | void RISCV64TargetInfo::fillValidTuneCPUList( |
320 | 1 | SmallVectorImpl<StringRef> &Values) const { |
321 | 1 | llvm::RISCV::fillValidTuneCPUArchList(Values, true); |
322 | 1 | } |