Coverage Report

Created: 2020-02-25 14:32

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements RISCV TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "RISCV.h"
14
#include "clang/Basic/MacroBuilder.h"
15
#include "llvm/ADT/StringSwitch.h"
16
17
using namespace clang;
18
using namespace clang::targets;
19
20
768
ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
21
768
  static const char *const GCCRegNames[] = {
22
768
      // Integer registers
23
768
      "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
24
768
      "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
25
768
      "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
26
768
      "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
27
768
28
768
      // Floating point registers
29
768
      "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
30
768
      "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
31
768
      "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
32
768
      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
33
768
  return llvm::makeArrayRef(GCCRegNames);
34
768
}
35
36
512
ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
37
512
  static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
38
512
      {{"zero"}, "x0"}, {{"ra"}, "x1"},   {{"sp"}, "x2"},    {{"gp"}, "x3"},
39
512
      {{"tp"}, "x4"},   {{"t0"}, "x5"},   {{"t1"}, "x6"},    {{"t2"}, "x7"},
40
512
      {{"s0"}, "x8"},   {{"s1"}, "x9"},   {{"a0"}, "x10"},   {{"a1"}, "x11"},
41
512
      {{"a2"}, "x12"},  {{"a3"}, "x13"},  {{"a4"}, "x14"},   {{"a5"}, "x15"},
42
512
      {{"a6"}, "x16"},  {{"a7"}, "x17"},  {{"s2"}, "x18"},   {{"s3"}, "x19"},
43
512
      {{"s4"}, "x20"},  {{"s5"}, "x21"},  {{"s6"}, "x22"},   {{"s7"}, "x23"},
44
512
      {{"s8"}, "x24"},  {{"s9"}, "x25"},  {{"s10"}, "x26"},  {{"s11"}, "x27"},
45
512
      {{"t3"}, "x28"},  {{"t4"}, "x29"},  {{"t5"}, "x30"},   {{"t6"}, "x31"},
46
512
      {{"ft0"}, "f0"},  {{"ft1"}, "f1"},  {{"ft2"}, "f2"},   {{"ft3"}, "f3"},
47
512
      {{"ft4"}, "f4"},  {{"ft5"}, "f5"},  {{"ft6"}, "f6"},   {{"ft7"}, "f7"},
48
512
      {{"fs0"}, "f8"},  {{"fs1"}, "f9"},  {{"fa0"}, "f10"},  {{"fa1"}, "f11"},
49
512
      {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"},  {{"fa5"}, "f15"},
50
512
      {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"},  {{"fs3"}, "f19"},
51
512
      {{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"},  {{"fs7"}, "f23"},
52
512
      {{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
53
512
      {{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}};
54
512
  return llvm::makeArrayRef(GCCRegAliases);
55
512
}
56
57
bool RISCVTargetInfo::validateAsmConstraint(
58
44
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
59
44
  switch (*Name) {
60
0
  default:
61
0
    return false;
62
12
  case 'I':
63
12
    // A 12-bit signed immediate.
64
12
    Info.setRequiresImmediate(-2048, 2047);
65
12
    return true;
66
8
  case 'J':
67
8
    // Integer zero.
68
8
    Info.setRequiresImmediate(0);
69
8
    return true;
70
12
  case 'K':
71
12
    // A 5-bit unsigned immediate for CSR access instructions.
72
12
    Info.setRequiresImmediate(0, 31);
73
12
    return true;
74
8
  case 'f':
75
8
    // A floating-point register.
76
8
    Info.setAllowsRegister();
77
8
    return true;
78
4
  case 'A':
79
4
    // An address that is held in a general-purpose register.
80
4
    Info.setAllowsMemory();
81
4
    return true;
82
44
  }
83
44
}
84
85
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
86
91
                                       MacroBuilder &Builder) const {
87
91
  Builder.defineMacro("__ELF__");
88
91
  Builder.defineMacro("__riscv");
89
91
  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
90
91
  Builder.defineMacro("__riscv_xlen", Is64Bit ? 
"64"42
:
"32"49
);
91
91
  StringRef CodeModel = getTargetOpts().CodeModel;
92
91
  if (CodeModel == "default")
93
83
    CodeModel = "small";
94
91
95
91
  if (CodeModel == "small")
96
87
    Builder.defineMacro("__riscv_cmodel_medlow");
97
4
  else if (CodeModel == "medium")
98
4
    Builder.defineMacro("__riscv_cmodel_medany");
99
91
100
91
  StringRef ABIName = getABI();
101
91
  if (ABIName == "ilp32f" || 
ABIName == "lp64f"85
)
102
11
    Builder.defineMacro("__riscv_float_abi_single");
103
80
  else if (ABIName == "ilp32d" || 
ABIName == "lp64d"71
)
104
15
    Builder.defineMacro("__riscv_float_abi_double");
105
65
  else
106
65
    Builder.defineMacro("__riscv_float_abi_soft");
107
91
108
91
  if (ABIName == "ilp32e")
109
0
    Builder.defineMacro("__riscv_abi_rve");
110
91
111
91
  if (HasM) {
112
7
    Builder.defineMacro("__riscv_mul");
113
7
    Builder.defineMacro("__riscv_div");
114
7
    Builder.defineMacro("__riscv_muldiv");
115
7
  }
116
91
117
91
  if (HasA)
118
9
    Builder.defineMacro("__riscv_atomic");
119
91
120
91
  if (HasF || 
HasD69
) {
121
30
    Builder.defineMacro("__riscv_flen", HasD ? 
"64"19
:
"32"11
);
122
30
    Builder.defineMacro("__riscv_fdiv");
123
30
    Builder.defineMacro("__riscv_fsqrt");
124
30
  }
125
91
126
91
  if (HasC)
127
7
    Builder.defineMacro("__riscv_compressed");
128
91
}
129
130
/// Return true if has this feature, need to sync with handleTargetFeatures.
131
80
bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
132
80
  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
133
80
  return llvm::StringSwitch<bool>(Feature)
134
80
      .Case("riscv", true)
135
80
      .Case("riscv32", !Is64Bit)
136
80
      .Case("riscv64", Is64Bit)
137
80
      .Case("m", HasM)
138
80
      .Case("a", HasA)
139
80
      .Case("f", HasF)
140
80
      .Case("d", HasD)
141
80
      .Case("c", HasC)
142
80
      .Default(false);
143
80
}
144
145
/// Perform initialization based on the user configured set of features.
146
bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
147
91
                                           DiagnosticsEngine &Diags) {
148
131
  for (const auto &Feature : Features) {
149
131
    if (Feature == "+m")
150
7
      HasM = true;
151
124
    else if (Feature == "+a")
152
9
      HasA = true;
153
115
    else if (Feature == "+f")
154
22
      HasF = true;
155
93
    else if (Feature == "+d")
156
19
      HasD = true;
157
74
    else if (Feature == "+c")
158
7
      HasC = true;
159
131
  }
160
91
161
91
  return true;
162
91
}