Coverage Report

Created: 2022-01-22 13:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
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Source (jump to first uncovered line)
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//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/X86TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
    "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
66
};
67
68
const TargetInfo::AddlRegName AddlRegNames[] = {
69
    {{"al", "ah", "eax", "rax"}, 0},
70
    {{"bl", "bh", "ebx", "rbx"}, 3},
71
    {{"cl", "ch", "ecx", "rcx"}, 2},
72
    {{"dl", "dh", "edx", "rdx"}, 1},
73
    {{"esi", "rsi"}, 4},
74
    {{"edi", "rdi"}, 5},
75
    {{"esp", "rsp"}, 7},
76
    {{"ebp", "rbp"}, 6},
77
    {{"r8d", "r8w", "r8b"}, 38},
78
    {{"r9d", "r9w", "r9b"}, 39},
79
    {{"r10d", "r10w", "r10b"}, 40},
80
    {{"r11d", "r11w", "r11b"}, 41},
81
    {{"r12d", "r12w", "r12b"}, 42},
82
    {{"r13d", "r13w", "r13b"}, 43},
83
    {{"r14d", "r14w", "r14b"}, 44},
84
    {{"r15d", "r15w", "r15b"}, 45},
85
};
86
87
} // namespace targets
88
} // namespace clang
89
90
using namespace clang;
91
using namespace clang::targets;
92
93
5
bool X86TargetInfo::setFPMath(StringRef Name) {
94
5
  if (Name == "387") {
95
2
    FPMath = FP_387;
96
2
    return true;
97
2
  }
98
3
  if (Name == "sse") {
99
2
    FPMath = FP_SSE;
100
2
    return true;
101
2
  }
102
1
  return false;
103
3
}
104
105
bool X86TargetInfo::initFeatureMap(
106
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107
137k
    const std::vector<std::string> &FeaturesVec) const {
108
  // FIXME: This *really* should not be here.
109
  // X86_64 always has SSE2.
110
137k
  if (getTriple().getArch() == llvm::Triple::x86_64)
111
121k
    setFeatureEnabled(Features, "sse2", true);
112
113
137k
  using namespace llvm::X86;
114
115
137k
  SmallVector<StringRef, 16> CPUFeatures;
116
137k
  getFeaturesForCPU(CPU, CPUFeatures);
117
137k
  for (auto &F : CPUFeatures)
118
530k
    setFeatureEnabled(Features, F, true);
119
120
137k
  std::vector<std::string> UpdatedFeaturesVec;
121
137k
  for (const auto &Feature : FeaturesVec) {
122
    // Expand general-regs-only to -x86, -mmx and -sse
123
132k
    if (Feature == "+general-regs-only") {
124
30
      UpdatedFeaturesVec.push_back("-x87");
125
30
      UpdatedFeaturesVec.push_back("-mmx");
126
30
      UpdatedFeaturesVec.push_back("-sse");
127
30
      continue;
128
30
    }
129
130
132k
    UpdatedFeaturesVec.push_back(Feature);
131
132k
  }
132
133
137k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134
0
    return false;
135
136
  // Can't do this earlier because we need to be able to explicitly enable
137
  // or disable these features and the things that they depend upon.
138
139
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140
137k
  auto I = Features.find("sse4.2");
141
137k
  if (I != Features.end() && 
I->getValue()44.9k
&&
142
137k
      
!llvm::is_contained(UpdatedFeaturesVec, "-popcnt")44.8k
)
143
44.8k
    Features["popcnt"] = true;
144
145
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146
  // then enable MMX.
147
137k
  I = Features.find("sse");
148
137k
  if (I != Features.end() && 
I->getValue()132k
&&
149
137k
      
!llvm::is_contained(UpdatedFeaturesVec, "-mmx")132k
)
150
132k
    Features["mmx"] = true;
151
152
  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153
137k
  I = Features.find("avx");
154
137k
  if (I != Features.end() && 
I->getValue()44.6k
&&
155
137k
      
!llvm::is_contained(UpdatedFeaturesVec, "-xsave")44.5k
)
156
44.5k
    Features["xsave"] = true;
157
158
  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
159
137k
  I = Features.find("sse4.2");
160
137k
  if (I != Features.end() && 
I->getValue()44.9k
&&
161
137k
      
!llvm::is_contained(UpdatedFeaturesVec, "-crc32")44.8k
)
162
44.7k
    Features["crc32"] = true;
163
164
137k
  return true;
165
137k
}
166
167
void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
168
4.38M
                                      StringRef Name, bool Enabled) const {
169
4.38M
  if (Name == "sse4") {
170
    // We can get here via the __target__ attribute since that's not controlled
171
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
172
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
173
    // disabled.
174
4
    if (Enabled)
175
2
      Name = "sse4.2";
176
2
    else
177
2
      Name = "sse4.1";
178
4
  }
179
180
4.38M
  Features[Name] = Enabled;
181
4.38M
  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
182
4.38M
}
183
184
/// handleTargetFeatures - Perform initialization based on the user
185
/// configured set of features.
186
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
187
85.6k
                                         DiagnosticsEngine &Diags) {
188
541k
  for (const auto &Feature : Features) {
189
541k
    if (Feature[0] != '+')
190
2.33k
      continue;
191
192
539k
    if (Feature == "+aes") {
193
58
      HasAES = true;
194
539k
    } else if (Feature == "+vaes") {
195
6
      HasVAES = true;
196
539k
    } else if (Feature == "+pclmul") {
197
73
      HasPCLMUL = true;
198
539k
    } else if (Feature == "+vpclmulqdq") {
199
6
      HasVPCLMULQDQ = true;
200
539k
    } else if (Feature == "+lzcnt") {
201
68
      HasLZCNT = true;
202
539k
    } else if (Feature == "+rdrnd") {
203
40
      HasRDRND = true;
204
539k
    } else if (Feature == "+fsgsbase") {
205
39
      HasFSGSBASE = true;
206
539k
    } else if (Feature == "+bmi") {
207
62
      HasBMI = true;
208
538k
    } else if (Feature == "+bmi2") {
209
41
      HasBMI2 = true;
210
538k
    } else if (Feature == "+popcnt") {
211
297
      HasPOPCNT = true;
212
538k
    } else if (Feature == "+rtm") {
213
1
      HasRTM = true;
214
538k
    } else if (Feature == "+prfchw") {
215
65
      HasPRFCHW = true;
216
538k
    } else if (Feature == "+rdseed") {
217
34
      HasRDSEED = true;
218
538k
    } else if (Feature == "+adx") {
219
34
      HasADX = true;
220
538k
    } else if (Feature == "+tbm") {
221
5
      HasTBM = true;
222
538k
    } else if (Feature == "+lwp") {
223
7
      HasLWP = true;
224
538k
    } else if (Feature == "+fma") {
225
160
      HasFMA = true;
226
538k
    } else if (Feature == "+f16c") {
227
178
      HasF16C = true;
228
538k
    } else if (Feature == "+gfni") {
229
6
      HasGFNI = true;
230
538k
    } else if (Feature == "+avx512cd") {
231
26
      HasAVX512CD = true;
232
538k
    } else if (Feature == "+avx512vpopcntdq") {
233
5
      HasAVX512VPOPCNTDQ = true;
234
538k
    } else if (Feature == "+avx512vnni") {
235
5
      HasAVX512VNNI = true;
236
538k
    } else if (Feature == "+avx512bf16") {
237
4
      HasAVX512BF16 = true;
238
538k
    } else if (Feature == "+avx512er") {
239
8
      HasAVX512ER = true;
240
538k
    } else if (Feature == "+avx512fp16") {
241
8
      HasAVX512FP16 = true;
242
8
      HasFloat16 = true;
243
538k
    } else if (Feature == "+avx512pf") {
244
7
      HasAVX512PF = true;
245
538k
    } else if (Feature == "+avx512dq") {
246
35
      HasAVX512DQ = true;
247
538k
    } else if (Feature == "+avx512bitalg") {
248
5
      HasAVX512BITALG = true;
249
538k
    } else if (Feature == "+avx512bw") {
250
47
      HasAVX512BW = true;
251
537k
    } else if (Feature == "+avx512vl") {
252
52
      HasAVX512VL = true;
253
537k
    } else if (Feature == "+avx512vbmi") {
254
6
      HasAVX512VBMI = true;
255
537k
    } else if (Feature == "+avx512vbmi2") {
256
5
      HasAVX512VBMI2 = true;
257
537k
    } else if (Feature == "+avx512ifma") {
258
6
      HasAVX512IFMA = true;
259
537k
    } else if (Feature == "+avx512vp2intersect") {
260
5
      HasAVX512VP2INTERSECT = true;
261
537k
    } else if (Feature == "+sha") {
262
8
      HasSHA = true;
263
537k
    } else if (Feature == "+shstk") {
264
6
      HasSHSTK = true;
265
537k
    } else if (Feature == "+movbe") {
266
121
      HasMOVBE = true;
267
537k
    } else if (Feature == "+sgx") {
268
13
      HasSGX = true;
269
537k
    } else if (Feature == "+cx8") {
270
85.6k
      HasCX8 = true;
271
452k
    } else if (Feature == "+cx16") {
272
17.0k
      HasCX16 = true;
273
435k
    } else if (Feature == "+fxsr") {
274
35.8k
      HasFXSR = true;
275
399k
    } else if (Feature == "+xsave") {
276
283
      HasXSAVE = true;
277
398k
    } else if (Feature == "+xsaveopt") {
278
72
      HasXSAVEOPT = true;
279
398k
    } else if (Feature == "+xsavec") {
280
31
      HasXSAVEC = true;
281
398k
    } else if (Feature == "+xsaves") {
282
31
      HasXSAVES = true;
283
398k
    } else if (Feature == "+mwaitx") {
284
8
      HasMWAITX = true;
285
398k
    } else if (Feature == "+pku") {
286
19
      HasPKU = true;
287
398k
    } else if (Feature == "+clflushopt") {
288
25
      HasCLFLUSHOPT = true;
289
398k
    } else if (Feature == "+clwb") {
290
18
      HasCLWB = true;
291
398k
    } else if (Feature == "+wbnoinvd") {
292
7
      HasWBNOINVD = true;
293
398k
    } else if (Feature == "+prefetchwt1") {
294
7
      HasPREFETCHWT1 = true;
295
398k
    } else if (Feature == "+clzero") {
296
8
      HasCLZERO = true;
297
398k
    } else if (Feature == "+cldemote") {
298
5
      HasCLDEMOTE = true;
299
398k
    } else if (Feature == "+rdpid") {
300
6
      HasRDPID = true;
301
398k
    } else if (Feature == "+kl") {
302
4
      HasKL = true;
303
398k
    } else if (Feature == "+widekl") {
304
3
      HasWIDEKL = true;
305
398k
    } else if (Feature == "+retpoline-external-thunk") {
306
0
      HasRetpolineExternalThunk = true;
307
398k
    } else if (Feature == "+sahf") {
308
17.0k
      HasLAHFSAHF = true;
309
381k
    } else if (Feature == "+waitpkg") {
310
2
      HasWAITPKG = true;
311
381k
    } else if (Feature == "+movdiri") {
312
3
      HasMOVDIRI = true;
313
381k
    } else if (Feature == "+movdir64b") {
314
3
      HasMOVDIR64B = true;
315
381k
    } else if (Feature == "+pconfig") {
316
9
      HasPCONFIG = true;
317
381k
    } else if (Feature == "+ptwrite") {
318
2
      HasPTWRITE = true;
319
381k
    } else if (Feature == "+invpcid") {
320
35
      HasINVPCID = true;
321
381k
    } else if (Feature == "+enqcmd") {
322
3
      HasENQCMD = true;
323
381k
    } else if (Feature == "+hreset") {
324
9
      HasHRESET = true;
325
381k
    } else if (Feature == "+amx-bf16") {
326
5
      HasAMXBF16 = true;
327
381k
    } else if (Feature == "+amx-int8") {
328
5
      HasAMXINT8 = true;
329
381k
    } else if (Feature == "+amx-tile") {
330
7
      HasAMXTILE = true;
331
381k
    } else if (Feature == "+avxvnni") {
332
2
      HasAVXVNNI = true;
333
381k
    } else if (Feature == "+serialize") {
334
3
      HasSERIALIZE = true;
335
381k
    } else if (Feature == "+tsxldtrk") {
336
3
      HasTSXLDTRK = true;
337
381k
    } else if (Feature == "+uintr") {
338
2
      HasUINTR = true;
339
381k
    } else if (Feature == "+crc32") {
340
298
      HasCRC32 = true;
341
381k
    } else if (Feature == "+x87") {
342
85.6k
      HasX87 = true;
343
85.6k
    }
344
345
539k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
346
539k
                           .Case("+avx512f", AVX512F)
347
539k
                           .Case("+avx2", AVX2)
348
539k
                           .Case("+avx", AVX)
349
539k
                           .Case("+sse4.2", SSE42)
350
539k
                           .Case("+sse4.1", SSE41)
351
539k
                           .Case("+ssse3", SSSE3)
352
539k
                           .Case("+sse3", SSE3)
353
539k
                           .Case("+sse2", SSE2)
354
539k
                           .Case("+sse", SSE1)
355
539k
                           .Default(NoSSE);
356
539k
    SSELevel = std::max(SSELevel, Level);
357
358
539k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
359
539k
                                      .Case("+3dnowa", AMD3DNowAthlon)
360
539k
                                      .Case("+3dnow", AMD3DNow)
361
539k
                                      .Case("+mmx", MMX)
362
539k
                                      .Default(NoMMX3DNow);
363
539k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
364
365
539k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
366
539k
                         .Case("+xop", XOP)
367
539k
                         .Case("+fma4", FMA4)
368
539k
                         .Case("+sse4a", SSE4A)
369
539k
                         .Default(NoXOP);
370
539k
    XOPLevel = std::max(XOPLevel, XLevel);
371
539k
  }
372
373
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
374
  // matches the selected sse level.
375
85.6k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
376
85.6k
      (FPMath == FP_387 && 
SSELevel >= SSE12
)) {
377
2
    Diags.Report(diag::err_target_unsupported_fpmath)
378
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
379
2
    return false;
380
2
  }
381
382
85.6k
  SimdDefaultAlign =
383
85.6k
      hasFeature("avx512f") ? 
512137
:
hasFeature("avx")85.5k
?
256118
:
12885.4k
;
384
385
  // FIXME: We should allow long double type on 32-bits to match with GCC.
386
  // This requires backend to be able to lower f80 without x87 first.
387
85.6k
  if (!HasX87 && 
LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()32
)
388
32
    HasLongDouble = false;
389
390
85.6k
  return true;
391
85.6k
}
392
393
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
394
/// definitions for this particular subtarget.
395
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
396
77.5k
                                     MacroBuilder &Builder) const {
397
  // Inline assembly supports X86 flag outputs.
398
77.5k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
399
400
77.5k
  std::string CodeModel = getTargetOpts().CodeModel;
401
77.5k
  if (CodeModel == "default")
402
62.1k
    CodeModel = "small";
403
77.5k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
404
405
  // Target identification.
406
77.5k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
407
62.9k
    Builder.defineMacro("__amd64__");
408
62.9k
    Builder.defineMacro("__amd64");
409
62.9k
    Builder.defineMacro("__x86_64");
410
62.9k
    Builder.defineMacro("__x86_64__");
411
62.9k
    if (getTriple().getArchName() == "x86_64h") {
412
2
      Builder.defineMacro("__x86_64h");
413
2
      Builder.defineMacro("__x86_64h__");
414
2
    }
415
62.9k
  } else {
416
14.6k
    DefineStd(Builder, "i386", Opts);
417
14.6k
  }
418
419
77.5k
  Builder.defineMacro("__SEG_GS");
420
77.5k
  Builder.defineMacro("__SEG_FS");
421
77.5k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
422
77.5k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
423
424
  // Subtarget options.
425
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
426
  // truly should be based on -mtune options.
427
77.5k
  using namespace llvm::X86;
428
77.5k
  switch (CPU) {
429
41.6k
  case CK_None:
430
41.6k
    break;
431
30
  case CK_i386:
432
    // The rest are coming from the i386 define above.
433
30
    Builder.defineMacro("__tune_i386__");
434
30
    break;
435
4
  case CK_i486:
436
4
  case CK_WinChipC6:
437
4
  case CK_WinChip2:
438
4
  case CK_C3:
439
4
    defineCPUMacros(Builder, "i486");
440
4
    break;
441
0
  case CK_PentiumMMX:
442
0
    Builder.defineMacro("__pentium_mmx__");
443
0
    Builder.defineMacro("__tune_pentium_mmx__");
444
0
    LLVM_FALLTHROUGH;
445
1
  case CK_i586:
446
4
  case CK_Pentium:
447
4
    defineCPUMacros(Builder, "i586");
448
4
    defineCPUMacros(Builder, "pentium");
449
4
    break;
450
2
  case CK_Pentium3:
451
5
  case CK_PentiumM:
452
5
    Builder.defineMacro("__tune_pentium3__");
453
5
    LLVM_FALLTHROUGH;
454
5
  case CK_Pentium2:
455
5
  case CK_C3_2:
456
5
    Builder.defineMacro("__tune_pentium2__");
457
5
    LLVM_FALLTHROUGH;
458
14
  case CK_PentiumPro:
459
29
  case CK_i686:
460
29
    defineCPUMacros(Builder, "i686");
461
29
    defineCPUMacros(Builder, "pentiumpro");
462
29
    break;
463
9.92k
  case CK_Pentium4:
464
9.92k
    defineCPUMacros(Builder, "pentium4");
465
9.92k
    break;
466
9
  case CK_Yonah:
467
9
  case CK_Prescott:
468
10
  case CK_Nocona:
469
10
    defineCPUMacros(Builder, "nocona");
470
10
    break;
471
178
  case CK_Core2:
472
16.8k
  case CK_Penryn:
473
16.8k
    defineCPUMacros(Builder, "core2");
474
16.8k
    break;
475
59
  case CK_Bonnell:
476
59
    defineCPUMacros(Builder, "atom");
477
59
    break;
478
2
  case CK_Silvermont:
479
2
    defineCPUMacros(Builder, "slm");
480
2
    break;
481
0
  case CK_Goldmont:
482
0
    defineCPUMacros(Builder, "goldmont");
483
0
    break;
484
0
  case CK_GoldmontPlus:
485
0
    defineCPUMacros(Builder, "goldmont_plus");
486
0
    break;
487
0
  case CK_Tremont:
488
0
    defineCPUMacros(Builder, "tremont");
489
0
    break;
490
5
  case CK_Nehalem:
491
6
  case CK_Westmere:
492
12
  case CK_SandyBridge:
493
13
  case CK_IvyBridge:
494
17
  case CK_Haswell:
495
19
  case CK_Broadwell:
496
21
  case CK_SkylakeClient:
497
35
  case CK_SkylakeServer:
498
35
  case CK_Cascadelake:
499
35
  case CK_Cooperlake:
500
36
  case CK_Cannonlake:
501
37
  case CK_IcelakeClient:
502
37
  case CK_Rocketlake:
503
38
  case CK_IcelakeServer:
504
38
  case CK_Tigerlake:
505
38
  case CK_SapphireRapids:
506
38
  case CK_Alderlake:
507
    // FIXME: Historically, we defined this legacy name, it would be nice to
508
    // remove it at some point. We've never exposed fine-grained names for
509
    // recent primary x86 CPUs, and we should keep it that way.
510
38
    defineCPUMacros(Builder, "corei7");
511
38
    break;
512
6
  case CK_KNL:
513
6
    defineCPUMacros(Builder, "knl");
514
6
    break;
515
1
  case CK_KNM:
516
1
    break;
517
0
  case CK_Lakemont:
518
0
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
519
0
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
520
0
    Builder.defineMacro("__tune_lakemont__");
521
0
    break;
522
0
  case CK_K6_2:
523
0
    Builder.defineMacro("__k6_2__");
524
0
    Builder.defineMacro("__tune_k6_2__");
525
0
    LLVM_FALLTHROUGH;
526
0
  case CK_K6_3:
527
0
    if (CPU != CK_K6_2) { // In case of fallthrough
528
      // FIXME: GCC may be enabling these in cases where some other k6
529
      // architecture is specified but -m3dnow is explicitly provided. The
530
      // exact semantics need to be determined and emulated here.
531
0
      Builder.defineMacro("__k6_3__");
532
0
      Builder.defineMacro("__tune_k6_3__");
533
0
    }
534
0
    LLVM_FALLTHROUGH;
535
0
  case CK_K6:
536
0
    defineCPUMacros(Builder, "k6");
537
0
    break;
538
0
  case CK_Athlon:
539
0
  case CK_AthlonXP:
540
0
    defineCPUMacros(Builder, "athlon");
541
0
    if (SSELevel != NoSSE) {
542
0
      Builder.defineMacro("__athlon_sse__");
543
0
      Builder.defineMacro("__tune_athlon_sse__");
544
0
    }
545
0
    break;
546
4
  case CK_K8:
547
7
  case CK_K8SSE3:
548
8.90k
  case CK_x86_64:
549
8.90k
    defineCPUMacros(Builder, "k8");
550
8.90k
    break;
551
1
  case CK_x86_64_v2:
552
2
  case CK_x86_64_v3:
553
3
  case CK_x86_64_v4:
554
3
    break;
555
2
  case CK_AMDFAM10:
556
2
    defineCPUMacros(Builder, "amdfam10");
557
2
    break;
558
2
  case CK_BTVER1:
559
2
    defineCPUMacros(Builder, "btver1");
560
2
    break;
561
17
  case CK_BTVER2:
562
17
    defineCPUMacros(Builder, "btver2");
563
17
    break;
564
2
  case CK_BDVER1:
565
2
    defineCPUMacros(Builder, "bdver1");
566
2
    break;
567
2
  case CK_BDVER2:
568
2
    defineCPUMacros(Builder, "bdver2");
569
2
    break;
570
1
  case CK_BDVER3:
571
1
    defineCPUMacros(Builder, "bdver3");
572
1
    break;
573
1
  case CK_BDVER4:
574
1
    defineCPUMacros(Builder, "bdver4");
575
1
    break;
576
2
  case CK_ZNVER1:
577
2
    defineCPUMacros(Builder, "znver1");
578
2
    break;
579
1
  case CK_ZNVER2:
580
1
    defineCPUMacros(Builder, "znver2");
581
1
    break;
582
1
  case CK_ZNVER3:
583
1
    defineCPUMacros(Builder, "znver3");
584
1
    break;
585
0
  case CK_Geode:
586
0
    defineCPUMacros(Builder, "geode");
587
0
    break;
588
77.5k
  }
589
590
  // Target properties.
591
77.5k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
592
593
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
594
  // functions in glibc header files that use FP Stack inline asm which the
595
  // backend can't deal with (PR879).
596
77.5k
  Builder.defineMacro("__NO_MATH_INLINES");
597
598
77.5k
  if (HasAES)
599
56
    Builder.defineMacro("__AES__");
600
601
77.5k
  if (HasVAES)
602
6
    Builder.defineMacro("__VAES__");
603
604
77.5k
  if (HasPCLMUL)
605
71
    Builder.defineMacro("__PCLMUL__");
606
607
77.5k
  if (HasVPCLMULQDQ)
608
6
    Builder.defineMacro("__VPCLMULQDQ__");
609
610
  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
611
  // the feature flag only applies to 64-bit mode.
612
77.5k
  if (HasLAHFSAHF || 
getTriple().getArch() == llvm::Triple::x8660.5k
)
613
31.4k
    Builder.defineMacro("__LAHF_SAHF__");
614
615
77.5k
  if (HasLZCNT)
616
66
    Builder.defineMacro("__LZCNT__");
617
618
77.5k
  if (HasRDRND)
619
40
    Builder.defineMacro("__RDRND__");
620
621
77.5k
  if (HasFSGSBASE)
622
39
    Builder.defineMacro("__FSGSBASE__");
623
624
77.5k
  if (HasBMI)
625
60
    Builder.defineMacro("__BMI__");
626
627
77.5k
  if (HasBMI2)
628
41
    Builder.defineMacro("__BMI2__");
629
630
77.5k
  if (HasPOPCNT)
631
295
    Builder.defineMacro("__POPCNT__");
632
633
77.5k
  if (HasRTM)
634
1
    Builder.defineMacro("__RTM__");
635
636
77.5k
  if (HasPRFCHW)
637
63
    Builder.defineMacro("__PRFCHW__");
638
639
77.5k
  if (HasRDSEED)
640
34
    Builder.defineMacro("__RDSEED__");
641
642
77.5k
  if (HasADX)
643
34
    Builder.defineMacro("__ADX__");
644
645
77.5k
  if (HasTBM)
646
5
    Builder.defineMacro("__TBM__");
647
648
77.5k
  if (HasLWP)
649
7
    Builder.defineMacro("__LWP__");
650
651
77.5k
  if (HasMWAITX)
652
8
    Builder.defineMacro("__MWAITX__");
653
654
77.5k
  if (HasMOVBE)
655
119
    Builder.defineMacro("__MOVBE__");
656
657
77.5k
  switch (XOPLevel) {
658
10
  case XOP:
659
10
    Builder.defineMacro("__XOP__");
660
10
    LLVM_FALLTHROUGH;
661
11
  case FMA4:
662
11
    Builder.defineMacro("__FMA4__");
663
11
    LLVM_FALLTHROUGH;
664
36
  case SSE4A:
665
36
    Builder.defineMacro("__SSE4A__");
666
36
    LLVM_FALLTHROUGH;
667
77.5k
  case NoXOP:
668
77.5k
    break;
669
77.5k
  }
670
671
77.5k
  if (HasFMA)
672
160
    Builder.defineMacro("__FMA__");
673
674
77.5k
  if (HasF16C)
675
176
    Builder.defineMacro("__F16C__");
676
677
77.5k
  if (HasGFNI)
678
6
    Builder.defineMacro("__GFNI__");
679
680
77.5k
  if (HasAVX512CD)
681
26
    Builder.defineMacro("__AVX512CD__");
682
77.5k
  if (HasAVX512VPOPCNTDQ)
683
5
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
684
77.5k
  if (HasAVX512VNNI)
685
5
    Builder.defineMacro("__AVX512VNNI__");
686
77.5k
  if (HasAVX512BF16)
687
4
    Builder.defineMacro("__AVX512BF16__");
688
77.5k
  if (HasAVX512ER)
689
8
    Builder.defineMacro("__AVX512ER__");
690
77.5k
  if (HasAVX512FP16)
691
8
    Builder.defineMacro("__AVX512FP16__");
692
77.5k
  if (HasAVX512PF)
693
7
    Builder.defineMacro("__AVX512PF__");
694
77.5k
  if (HasAVX512DQ)
695
35
    Builder.defineMacro("__AVX512DQ__");
696
77.5k
  if (HasAVX512BITALG)
697
5
    Builder.defineMacro("__AVX512BITALG__");
698
77.5k
  if (HasAVX512BW)
699
47
    Builder.defineMacro("__AVX512BW__");
700
77.5k
  if (HasAVX512VL)
701
52
    Builder.defineMacro("__AVX512VL__");
702
77.5k
  if (HasAVX512VBMI)
703
6
    Builder.defineMacro("__AVX512VBMI__");
704
77.5k
  if (HasAVX512VBMI2)
705
5
    Builder.defineMacro("__AVX512VBMI2__");
706
77.5k
  if (HasAVX512IFMA)
707
6
    Builder.defineMacro("__AVX512IFMA__");
708
77.5k
  if (HasAVX512VP2INTERSECT)
709
5
    Builder.defineMacro("__AVX512VP2INTERSECT__");
710
77.5k
  if (HasSHA)
711
8
    Builder.defineMacro("__SHA__");
712
713
77.5k
  if (HasFXSR)
714
35.8k
    Builder.defineMacro("__FXSR__");
715
77.5k
  if (HasXSAVE)
716
281
    Builder.defineMacro("__XSAVE__");
717
77.5k
  if (HasXSAVEOPT)
718
70
    Builder.defineMacro("__XSAVEOPT__");
719
77.5k
  if (HasXSAVEC)
720
31
    Builder.defineMacro("__XSAVEC__");
721
77.5k
  if (HasXSAVES)
722
31
    Builder.defineMacro("__XSAVES__");
723
77.5k
  if (HasPKU)
724
19
    Builder.defineMacro("__PKU__");
725
77.5k
  if (HasCLFLUSHOPT)
726
25
    Builder.defineMacro("__CLFLUSHOPT__");
727
77.5k
  if (HasCLWB)
728
18
    Builder.defineMacro("__CLWB__");
729
77.5k
  if (HasWBNOINVD)
730
7
    Builder.defineMacro("__WBNOINVD__");
731
77.5k
  if (HasSHSTK)
732
6
    Builder.defineMacro("__SHSTK__");
733
77.5k
  if (HasSGX)
734
13
    Builder.defineMacro("__SGX__");
735
77.5k
  if (HasPREFETCHWT1)
736
7
    Builder.defineMacro("__PREFETCHWT1__");
737
77.5k
  if (HasCLZERO)
738
8
    Builder.defineMacro("__CLZERO__");
739
77.5k
  if (HasKL)
740
4
    Builder.defineMacro("__KL__");
741
77.5k
  if (HasWIDEKL)
742
3
    Builder.defineMacro("__WIDEKL__");
743
77.5k
  if (HasRDPID)
744
6
    Builder.defineMacro("__RDPID__");
745
77.5k
  if (HasCLDEMOTE)
746
5
    Builder.defineMacro("__CLDEMOTE__");
747
77.5k
  if (HasWAITPKG)
748
2
    Builder.defineMacro("__WAITPKG__");
749
77.5k
  if (HasMOVDIRI)
750
3
    Builder.defineMacro("__MOVDIRI__");
751
77.5k
  if (HasMOVDIR64B)
752
3
    Builder.defineMacro("__MOVDIR64B__");
753
77.5k
  if (HasPCONFIG)
754
9
    Builder.defineMacro("__PCONFIG__");
755
77.5k
  if (HasPTWRITE)
756
2
    Builder.defineMacro("__PTWRITE__");
757
77.5k
  if (HasINVPCID)
758
35
    Builder.defineMacro("__INVPCID__");
759
77.5k
  if (HasENQCMD)
760
3
    Builder.defineMacro("__ENQCMD__");
761
77.5k
  if (HasHRESET)
762
9
    Builder.defineMacro("__HRESET__");
763
77.5k
  if (HasAMXTILE)
764
7
    Builder.defineMacro("__AMXTILE__");
765
77.5k
  if (HasAMXINT8)
766
5
    Builder.defineMacro("__AMXINT8__");
767
77.5k
  if (HasAMXBF16)
768
5
    Builder.defineMacro("__AMXBF16__");
769
77.5k
  if (HasAVXVNNI)
770
2
    Builder.defineMacro("__AVXVNNI__");
771
77.5k
  if (HasSERIALIZE)
772
3
    Builder.defineMacro("__SERIALIZE__");
773
77.5k
  if (HasTSXLDTRK)
774
3
    Builder.defineMacro("__TSXLDTRK__");
775
77.5k
  if (HasUINTR)
776
2
    Builder.defineMacro("__UINTR__");
777
77.5k
  if (HasCRC32)
778
296
    Builder.defineMacro("__CRC32__");
779
780
  // Each case falls through to the previous one here.
781
77.5k
  switch (SSELevel) {
782
137
  case AVX512F:
783
137
    Builder.defineMacro("__AVX512F__");
784
137
    LLVM_FALLTHROUGH;
785
165
  case AVX2:
786
165
    Builder.defineMacro("__AVX2__");
787
165
    LLVM_FALLTHROUGH;
788
253
  case AVX:
789
253
    Builder.defineMacro("__AVX__");
790
253
    LLVM_FALLTHROUGH;
791
284
  case SSE42:
792
284
    Builder.defineMacro("__SSE4_2__");
793
284
    LLVM_FALLTHROUGH;
794
16.9k
  case SSE41:
795
16.9k
    Builder.defineMacro("__SSE4_1__");
796
16.9k
    LLVM_FALLTHROUGH;
797
17.1k
  case SSSE3:
798
17.1k
    Builder.defineMacro("__SSSE3__");
799
17.1k
    LLVM_FALLTHROUGH;
800
17.1k
  case SSE3:
801
17.1k
    Builder.defineMacro("__SSE3__");
802
17.1k
    LLVM_FALLTHROUGH;
803
72.9k
  case SSE2:
804
72.9k
    Builder.defineMacro("__SSE2__");
805
72.9k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
806
72.9k
    LLVM_FALLTHROUGH;
807
72.9k
  case SSE1:
808
72.9k
    Builder.defineMacro("__SSE__");
809
72.9k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
810
72.9k
    LLVM_FALLTHROUGH;
811
77.5k
  case NoSSE:
812
77.5k
    break;
813
77.5k
  }
814
815
77.5k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x8611.1k
) {
816
344
    switch (SSELevel) {
817
2
    case AVX512F:
818
4
    case AVX2:
819
6
    case AVX:
820
6
    case SSE42:
821
6
    case SSE41:
822
6
    case SSSE3:
823
6
    case SSE3:
824
59
    case SSE2:
825
59
      Builder.defineMacro("_M_IX86_FP", Twine(2));
826
59
      break;
827
2
    case SSE1:
828
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
829
2
      break;
830
283
    default:
831
283
      Builder.defineMacro("_M_IX86_FP", Twine(0));
832
283
      break;
833
344
    }
834
344
  }
835
836
  // Each case falls through to the previous one here.
837
77.5k
  switch (MMX3DNowLevel) {
838
11
  case AMD3DNowAthlon:
839
11
    Builder.defineMacro("__3dNOW_A__");
840
11
    LLVM_FALLTHROUGH;
841
13
  case AMD3DNow:
842
13
    Builder.defineMacro("__3dNOW__");
843
13
    LLVM_FALLTHROUGH;
844
72.9k
  case MMX:
845
72.9k
    Builder.defineMacro("__MMX__");
846
72.9k
    LLVM_FALLTHROUGH;
847
77.5k
  case NoMMX3DNow:
848
77.5k
    break;
849
77.5k
  }
850
851
77.5k
  if (CPU >= CK_i486 || 
CPU == CK_None41.7k
) {
852
77.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
853
77.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
854
77.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
855
77.5k
  }
856
77.5k
  if (HasCX8)
857
77.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
858
77.5k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6416.9k
)
859
16.8k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
860
861
77.5k
  if (HasFloat128)
862
3.97k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
863
77.5k
}
864
865
1.41M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
866
1.41M
  return llvm::StringSwitch<bool>(Name)
867
1.41M
      .Case("3dnow", true)
868
1.41M
      .Case("3dnowa", true)
869
1.41M
      .Case("adx", true)
870
1.41M
      .Case("aes", true)
871
1.41M
      .Case("amx-bf16", true)
872
1.41M
      .Case("amx-int8", true)
873
1.41M
      .Case("amx-tile", true)
874
1.41M
      .Case("avx", true)
875
1.41M
      .Case("avx2", true)
876
1.41M
      .Case("avx512f", true)
877
1.41M
      .Case("avx512cd", true)
878
1.41M
      .Case("avx512vpopcntdq", true)
879
1.41M
      .Case("avx512vnni", true)
880
1.41M
      .Case("avx512bf16", true)
881
1.41M
      .Case("avx512er", true)
882
1.41M
      .Case("avx512fp16", true)
883
1.41M
      .Case("avx512pf", true)
884
1.41M
      .Case("avx512dq", true)
885
1.41M
      .Case("avx512bitalg", true)
886
1.41M
      .Case("avx512bw", true)
887
1.41M
      .Case("avx512vl", true)
888
1.41M
      .Case("avx512vbmi", true)
889
1.41M
      .Case("avx512vbmi2", true)
890
1.41M
      .Case("avx512ifma", true)
891
1.41M
      .Case("avx512vp2intersect", true)
892
1.41M
      .Case("avxvnni", true)
893
1.41M
      .Case("bmi", true)
894
1.41M
      .Case("bmi2", true)
895
1.41M
      .Case("cldemote", true)
896
1.41M
      .Case("clflushopt", true)
897
1.41M
      .Case("clwb", true)
898
1.41M
      .Case("clzero", true)
899
1.41M
      .Case("crc32", true)
900
1.41M
      .Case("cx16", true)
901
1.41M
      .Case("enqcmd", true)
902
1.41M
      .Case("f16c", true)
903
1.41M
      .Case("fma", true)
904
1.41M
      .Case("fma4", true)
905
1.41M
      .Case("fsgsbase", true)
906
1.41M
      .Case("fxsr", true)
907
1.41M
      .Case("general-regs-only", true)
908
1.41M
      .Case("gfni", true)
909
1.41M
      .Case("hreset", true)
910
1.41M
      .Case("invpcid", true)
911
1.41M
      .Case("kl", true)
912
1.41M
      .Case("widekl", true)
913
1.41M
      .Case("lwp", true)
914
1.41M
      .Case("lzcnt", true)
915
1.41M
      .Case("mmx", true)
916
1.41M
      .Case("movbe", true)
917
1.41M
      .Case("movdiri", true)
918
1.41M
      .Case("movdir64b", true)
919
1.41M
      .Case("mwaitx", true)
920
1.41M
      .Case("pclmul", true)
921
1.41M
      .Case("pconfig", true)
922
1.41M
      .Case("pku", true)
923
1.41M
      .Case("popcnt", true)
924
1.41M
      .Case("prefetchwt1", true)
925
1.41M
      .Case("prfchw", true)
926
1.41M
      .Case("ptwrite", true)
927
1.41M
      .Case("rdpid", true)
928
1.41M
      .Case("rdrnd", true)
929
1.41M
      .Case("rdseed", true)
930
1.41M
      .Case("rtm", true)
931
1.41M
      .Case("sahf", true)
932
1.41M
      .Case("serialize", true)
933
1.41M
      .Case("sgx", true)
934
1.41M
      .Case("sha", true)
935
1.41M
      .Case("shstk", true)
936
1.41M
      .Case("sse", true)
937
1.41M
      .Case("sse2", true)
938
1.41M
      .Case("sse3", true)
939
1.41M
      .Case("ssse3", true)
940
1.41M
      .Case("sse4", true)
941
1.41M
      .Case("sse4.1", true)
942
1.41M
      .Case("sse4.2", true)
943
1.41M
      .Case("sse4a", true)
944
1.41M
      .Case("tbm", true)
945
1.41M
      .Case("tsxldtrk", true)
946
1.41M
      .Case("uintr", true)
947
1.41M
      .Case("vaes", true)
948
1.41M
      .Case("vpclmulqdq", true)
949
1.41M
      .Case("wbnoinvd", true)
950
1.41M
      .Case("waitpkg", true)
951
1.41M
      .Case("x87", true)
952
1.41M
      .Case("xop", true)
953
1.41M
      .Case("xsave", true)
954
1.41M
      .Case("xsavec", true)
955
1.41M
      .Case("xsaves", true)
956
1.41M
      .Case("xsaveopt", true)
957
1.41M
      .Default(false);
958
1.41M
}
959
960
464k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
961
464k
  return llvm::StringSwitch<bool>(Feature)
962
464k
      .Case("adx", HasADX)
963
464k
      .Case("aes", HasAES)
964
464k
      .Case("amx-bf16", HasAMXBF16)
965
464k
      .Case("amx-int8", HasAMXINT8)
966
464k
      .Case("amx-tile", HasAMXTILE)
967
464k
      .Case("avxvnni", HasAVXVNNI)
968
464k
      .Case("avx", SSELevel >= AVX)
969
464k
      .Case("avx2", SSELevel >= AVX2)
970
464k
      .Case("avx512f", SSELevel >= AVX512F)
971
464k
      .Case("avx512cd", HasAVX512CD)
972
464k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
973
464k
      .Case("avx512vnni", HasAVX512VNNI)
974
464k
      .Case("avx512bf16", HasAVX512BF16)
975
464k
      .Case("avx512er", HasAVX512ER)
976
464k
      .Case("avx512fp16", HasAVX512FP16)
977
464k
      .Case("avx512pf", HasAVX512PF)
978
464k
      .Case("avx512dq", HasAVX512DQ)
979
464k
      .Case("avx512bitalg", HasAVX512BITALG)
980
464k
      .Case("avx512bw", HasAVX512BW)
981
464k
      .Case("avx512vl", HasAVX512VL)
982
464k
      .Case("avx512vbmi", HasAVX512VBMI)
983
464k
      .Case("avx512vbmi2", HasAVX512VBMI2)
984
464k
      .Case("avx512ifma", HasAVX512IFMA)
985
464k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
986
464k
      .Case("bmi", HasBMI)
987
464k
      .Case("bmi2", HasBMI2)
988
464k
      .Case("cldemote", HasCLDEMOTE)
989
464k
      .Case("clflushopt", HasCLFLUSHOPT)
990
464k
      .Case("clwb", HasCLWB)
991
464k
      .Case("clzero", HasCLZERO)
992
464k
      .Case("crc32", HasCRC32)
993
464k
      .Case("cx8", HasCX8)
994
464k
      .Case("cx16", HasCX16)
995
464k
      .Case("enqcmd", HasENQCMD)
996
464k
      .Case("f16c", HasF16C)
997
464k
      .Case("fma", HasFMA)
998
464k
      .Case("fma4", XOPLevel >= FMA4)
999
464k
      .Case("fsgsbase", HasFSGSBASE)
1000
464k
      .Case("fxsr", HasFXSR)
1001
464k
      .Case("gfni", HasGFNI)
1002
464k
      .Case("hreset", HasHRESET)
1003
464k
      .Case("invpcid", HasINVPCID)
1004
464k
      .Case("kl", HasKL)
1005
464k
      .Case("widekl", HasWIDEKL)
1006
464k
      .Case("lwp", HasLWP)
1007
464k
      .Case("lzcnt", HasLZCNT)
1008
464k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1009
464k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1010
464k
      .Case("mmx", MMX3DNowLevel >= MMX)
1011
464k
      .Case("movbe", HasMOVBE)
1012
464k
      .Case("movdiri", HasMOVDIRI)
1013
464k
      .Case("movdir64b", HasMOVDIR64B)
1014
464k
      .Case("mwaitx", HasMWAITX)
1015
464k
      .Case("pclmul", HasPCLMUL)
1016
464k
      .Case("pconfig", HasPCONFIG)
1017
464k
      .Case("pku", HasPKU)
1018
464k
      .Case("popcnt", HasPOPCNT)
1019
464k
      .Case("prefetchwt1", HasPREFETCHWT1)
1020
464k
      .Case("prfchw", HasPRFCHW)
1021
464k
      .Case("ptwrite", HasPTWRITE)
1022
464k
      .Case("rdpid", HasRDPID)
1023
464k
      .Case("rdrnd", HasRDRND)
1024
464k
      .Case("rdseed", HasRDSEED)
1025
464k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1026
464k
      .Case("rtm", HasRTM)
1027
464k
      .Case("sahf", HasLAHFSAHF)
1028
464k
      .Case("serialize", HasSERIALIZE)
1029
464k
      .Case("sgx", HasSGX)
1030
464k
      .Case("sha", HasSHA)
1031
464k
      .Case("shstk", HasSHSTK)
1032
464k
      .Case("sse", SSELevel >= SSE1)
1033
464k
      .Case("sse2", SSELevel >= SSE2)
1034
464k
      .Case("sse3", SSELevel >= SSE3)
1035
464k
      .Case("ssse3", SSELevel >= SSSE3)
1036
464k
      .Case("sse4.1", SSELevel >= SSE41)
1037
464k
      .Case("sse4.2", SSELevel >= SSE42)
1038
464k
      .Case("sse4a", XOPLevel >= SSE4A)
1039
464k
      .Case("tbm", HasTBM)
1040
464k
      .Case("tsxldtrk", HasTSXLDTRK)
1041
464k
      .Case("uintr", HasUINTR)
1042
464k
      .Case("vaes", HasVAES)
1043
464k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1044
464k
      .Case("wbnoinvd", HasWBNOINVD)
1045
464k
      .Case("waitpkg", HasWAITPKG)
1046
464k
      .Case("x86", true)
1047
464k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1048
464k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1049
464k
      .Case("x87", HasX87)
1050
464k
      .Case("xop", XOPLevel >= XOP)
1051
464k
      .Case("xsave", HasXSAVE)
1052
464k
      .Case("xsavec", HasXSAVEC)
1053
464k
      .Case("xsaves", HasXSAVES)
1054
464k
      .Case("xsaveopt", HasXSAVEOPT)
1055
464k
      .Default(false);
1056
464k
}
1057
1058
// We can't use a generic validation scheme for the features accepted here
1059
// versus subtarget features accepted in the target attribute because the
1060
// bitfield structure that's initialized in the runtime only supports the
1061
// below currently rather than the full range of subtarget features. (See
1062
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1063
944
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1064
944
  return llvm::StringSwitch<bool>(FeatureStr)
1065
35.8k
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1066
944
#include "llvm/Support/X86TargetParser.def"
1067
944
      .Default(false);
1068
944
}
1069
1070
177
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1071
177
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1072
177
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1073
6.72k
  .Case(STR, llvm::X86::FEATURE_##ENUM)
1074
1075
177
#include "llvm/Support/X86TargetParser.def"
1076
177
      ;
1077
  // Note, this function should only be used after ensuring the value is
1078
  // correct, so it asserts if the value is out of range.
1079
177
}
1080
1081
465
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1082
  // Valid CPUs have a 'key feature' that compares just better than its key
1083
  // feature.
1084
465
  using namespace llvm::X86;
1085
465
  CPUKind Kind = parseArchX86(Name);
1086
465
  if (Kind != CK_None) {
1087
288
    ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1088
288
    return (getFeaturePriority(KeyFeature) << 1) + 1;
1089
288
  }
1090
1091
  // Now we know we have a feature, so get its priority and shift it a few so
1092
  // that we have sufficient room for the CPUs (above).
1093
177
  return getFeaturePriority(getFeature(Name)) << 1;
1094
465
}
1095
1096
221
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1097
221
  return llvm::StringSwitch<bool>(Name)
1098
6.18k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1099
1.32k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1100
221
#include "llvm/Support/X86TargetParser.def"
1101
221
      .Default(false);
1102
221
}
1103
1104
518
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1105
518
  return llvm::StringSwitch<StringRef>(Name)
1106
3.10k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1107
518
#include "llvm/Support/X86TargetParser.def"
1108
518
      .Default(Name);
1109
518
}
1110
1111
342
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1112
342
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1113
9.57k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1114
342
#include "llvm/Support/X86TargetParser.def"
1115
342
      .Default(0);
1116
342
}
1117
1118
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1119
176
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1120
176
  StringRef WholeList =
1121
176
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1122
4.92k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1123
176
#include "llvm/Support/X86TargetParser.def"
1124
176
          .Default("");
1125
176
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1126
176
}
1127
1128
// We can't use a generic validation scheme for the cpus accepted here
1129
// versus subtarget cpus accepted in the target attribute because the
1130
// variables intitialized by the runtime only support the below currently
1131
// rather than the full range of cpus.
1132
190
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1133
190
  return llvm::StringSwitch<bool>(FeatureStr)
1134
380
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1135
760
#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1136
2.85k
#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1137
5.13k
#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1138
190
#include "llvm/Support/X86TargetParser.def"
1139
190
      .Default(false);
1140
190
}
1141
1142
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1143
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1144
87
                .Case("@cca", 4)
1145
87
                .Case("@ccae", 5)
1146
87
                .Case("@ccb", 4)
1147
87
                .Case("@ccbe", 5)
1148
87
                .Case("@ccc", 4)
1149
87
                .Case("@cce", 4)
1150
87
                .Case("@ccz", 4)
1151
87
                .Case("@ccg", 4)
1152
87
                .Case("@ccge", 5)
1153
87
                .Case("@ccl", 4)
1154
87
                .Case("@ccle", 5)
1155
87
                .Case("@ccna", 5)
1156
87
                .Case("@ccnae", 6)
1157
87
                .Case("@ccnb", 5)
1158
87
                .Case("@ccnbe", 6)
1159
87
                .Case("@ccnc", 5)
1160
87
                .Case("@ccne", 5)
1161
87
                .Case("@ccnz", 5)
1162
87
                .Case("@ccng", 5)
1163
87
                .Case("@ccnge", 6)
1164
87
                .Case("@ccnl", 5)
1165
87
                .Case("@ccnle", 6)
1166
87
                .Case("@ccno", 5)
1167
87
                .Case("@ccnp", 5)
1168
87
                .Case("@ccns", 5)
1169
87
                .Case("@cco", 4)
1170
87
                .Case("@ccp", 4)
1171
87
                .Case("@ccs", 4)
1172
87
                .Default(0);
1173
87
  return RV;
1174
87
}
1175
1176
bool X86TargetInfo::validateAsmConstraint(
1177
10.6k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1178
10.6k
  switch (*Name) {
1179
2
  default:
1180
2
    return false;
1181
  // Constant constraints.
1182
9
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1183
            // instructions.
1184
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1185
            // x86_64 instructions.
1186
17
  case 's':
1187
17
    Info.setRequiresImmediate();
1188
17
    return true;
1189
28
  case 'I':
1190
28
    Info.setRequiresImmediate(0, 31);
1191
28
    return true;
1192
14
  case 'J':
1193
14
    Info.setRequiresImmediate(0, 63);
1194
14
    return true;
1195
14
  case 'K':
1196
14
    Info.setRequiresImmediate(-128, 127);
1197
14
    return true;
1198
30
  case 'L':
1199
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1200
30
    return true;
1201
14
  case 'M':
1202
14
    Info.setRequiresImmediate(0, 3);
1203
14
    return true;
1204
16
  case 'N':
1205
16
    Info.setRequiresImmediate(0, 255);
1206
16
    return true;
1207
6
  case 'O':
1208
6
    Info.setRequiresImmediate(0, 127);
1209
6
    return true;
1210
  // Register constraints.
1211
52
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1212
    // Shift the pointer to the second character of the constraint.
1213
52
    Name++;
1214
52
    switch (*Name) {
1215
0
    default:
1216
0
      return false;
1217
20
    case 'z': // First SSE register.
1218
26
    case '2':
1219
32
    case 't': // Any SSE register, when SSE2 is enabled.
1220
42
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1221
44
    case 'm': // Any MMX register, when inter-unit moves enabled.
1222
52
    case 'k': // AVX512 arch mask registers: k1-k7.
1223
52
      Info.setAllowsRegister();
1224
52
      return true;
1225
52
    }
1226
3
  case 'f': // Any x87 floating point stack register.
1227
    // Constraint 'f' cannot be used for output operands.
1228
3
    if (Info.ConstraintStr[0] == '=')
1229
1
      return false;
1230
2
    Info.setAllowsRegister();
1231
2
    return true;
1232
2.78k
  case 'a': // eax.
1233
5.04k
  case 'b': // ebx.
1234
7.50k
  case 'c': // ecx.
1235
9.83k
  case 'd': // edx.
1236
9.91k
  case 'S': // esi.
1237
10.0k
  case 'D': // edi.
1238
10.1k
  case 'A': // edx:eax.
1239
10.1k
  case 't': // Top of floating point stack.
1240
10.1k
  case 'u': // Second from top of floating point stack.
1241
10.1k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1242
10.1k
  case 'y': // Any MMX register.
1243
10.2k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1244
10.3k
  case 'x': // Any SSE register.
1245
10.3k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1246
            // for intermideate k reg operations).
1247
10.3k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1248
10.4k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1249
10.4k
  case 'l': // "Index" registers: any general register that can be used as an
1250
            // index in a base+index memory access.
1251
10.4k
    Info.setAllowsRegister();
1252
10.4k
    return true;
1253
  // Floating point constant constraints.
1254
8
  case 'C': // SSE floating point constant.
1255
16
  case 'G': // x87 floating point constant.
1256
16
    return true;
1257
58
  case '@':
1258
    // CC condition changes.
1259
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1260
58
      Name += Len - 1;
1261
58
      Info.setAllowsRegister();
1262
58
      return true;
1263
58
    }
1264
0
    return false;
1265
10.6k
  }
1266
10.6k
}
1267
1268
// Below is based on the following information:
1269
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1270
// |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1271
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1272
// | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1273
// | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1274
// | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1275
// | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1276
// | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1277
// | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1278
// | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1279
// | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1280
// | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1281
// | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1282
// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1283
// | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1284
// | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1285
// | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1286
// | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1287
// | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1288
// | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1289
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1290
0
Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1291
0
  using namespace llvm::X86;
1292
0
  switch (CPU) {
1293
    // i386
1294
0
    case CK_i386:
1295
    // i486
1296
0
    case CK_i486:
1297
0
    case CK_WinChipC6:
1298
0
    case CK_WinChip2:
1299
0
    case CK_C3:
1300
    // Lakemont
1301
0
    case CK_Lakemont:
1302
0
      return 16;
1303
1304
    // i586
1305
0
    case CK_i586:
1306
0
    case CK_Pentium:
1307
0
    case CK_PentiumMMX:
1308
    // i686
1309
0
    case CK_PentiumPro:
1310
0
    case CK_i686:
1311
0
    case CK_Pentium2:
1312
0
    case CK_Pentium3:
1313
0
    case CK_PentiumM:
1314
0
    case CK_C3_2:
1315
    // K6
1316
0
    case CK_K6:
1317
0
    case CK_K6_2:
1318
0
    case CK_K6_3:
1319
    // Geode
1320
0
    case CK_Geode:
1321
0
      return 32;
1322
1323
    // Netburst
1324
0
    case CK_Pentium4:
1325
0
    case CK_Prescott:
1326
0
    case CK_Nocona:
1327
    // Atom
1328
0
    case CK_Bonnell:
1329
0
    case CK_Silvermont:
1330
0
    case CK_Goldmont:
1331
0
    case CK_GoldmontPlus:
1332
0
    case CK_Tremont:
1333
1334
0
    case CK_Westmere:
1335
0
    case CK_SandyBridge:
1336
0
    case CK_IvyBridge:
1337
0
    case CK_Haswell:
1338
0
    case CK_Broadwell:
1339
0
    case CK_SkylakeClient:
1340
0
    case CK_SkylakeServer:
1341
0
    case CK_Cascadelake:
1342
0
    case CK_Nehalem:
1343
0
    case CK_Cooperlake:
1344
0
    case CK_Cannonlake:
1345
0
    case CK_Tigerlake:
1346
0
    case CK_SapphireRapids:
1347
0
    case CK_IcelakeClient:
1348
0
    case CK_Rocketlake:
1349
0
    case CK_IcelakeServer:
1350
0
    case CK_Alderlake:
1351
0
    case CK_KNL:
1352
0
    case CK_KNM:
1353
    // K7
1354
0
    case CK_Athlon:
1355
0
    case CK_AthlonXP:
1356
    // K8
1357
0
    case CK_K8:
1358
0
    case CK_K8SSE3:
1359
0
    case CK_AMDFAM10:
1360
    // Bobcat
1361
0
    case CK_BTVER1:
1362
0
    case CK_BTVER2:
1363
    // Bulldozer
1364
0
    case CK_BDVER1:
1365
0
    case CK_BDVER2:
1366
0
    case CK_BDVER3:
1367
0
    case CK_BDVER4:
1368
    // Zen
1369
0
    case CK_ZNVER1:
1370
0
    case CK_ZNVER2:
1371
0
    case CK_ZNVER3:
1372
    // Deprecated
1373
0
    case CK_x86_64:
1374
0
    case CK_x86_64_v2:
1375
0
    case CK_x86_64_v3:
1376
0
    case CK_x86_64_v4:
1377
0
    case CK_Yonah:
1378
0
    case CK_Penryn:
1379
0
    case CK_Core2:
1380
0
      return 64;
1381
1382
    // The following currently have unknown cache line sizes (but they are probably all 64):
1383
    // Core
1384
0
    case CK_None:
1385
0
      return None;
1386
0
  }
1387
0
  llvm_unreachable("Unknown CPU kind");
1388
0
}
1389
1390
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1391
                                       StringRef Constraint,
1392
5.73k
                                       unsigned Size) const {
1393
  // Strip off constraint modifiers.
1394
11.4k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'6.31k
||
Constraint[0] == '&'5.75k
)
1395
5.75k
    Constraint = Constraint.substr(1);
1396
1397
5.73k
  return validateOperandSize(FeatureMap, Constraint, Size);
1398
5.73k
}
1399
1400
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1401
                                      StringRef Constraint,
1402
5.94k
                                      unsigned Size) const {
1403
5.94k
  return validateOperandSize(FeatureMap, Constraint, Size);
1404
5.94k
}
1405
1406
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1407
                                        StringRef Constraint,
1408
9.43k
                                        unsigned Size) const {
1409
9.43k
  switch (Constraint[0]) {
1410
9.26k
  default:
1411
9.26k
    break;
1412
9.26k
  case 'k':
1413
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1414
30
  case 'y':
1415
30
    return Size <= 64;
1416
2
  case 'f':
1417
9
  case 't':
1418
14
  case 'u':
1419
14
    return Size <= 128;
1420
26
  case 'Y':
1421
    // 'Y' is the first character for several 2-character constraints.
1422
26
    switch (Constraint[1]) {
1423
0
    default:
1424
0
      return false;
1425
1
    case 'm':
1426
      // 'Ym' is synonymous with 'y'.
1427
5
    case 'k':
1428
5
      return Size <= 64;
1429
10
    case 'z':
1430
      // XMM0/YMM/ZMM0
1431
10
      if (hasFeatureEnabled(FeatureMap, "avx512f"))
1432
        // ZMM0 can be used if target supports AVX512F.
1433
7
        return Size <= 512U;
1434
3
      else if (hasFeatureEnabled(FeatureMap, "avx"))
1435
        // YMM0 can be used if target supports AVX.
1436
2
        return Size <= 256U;
1437
1
      else if (hasFeatureEnabled(FeatureMap, "sse"))
1438
1
        return Size <= 128U;
1439
0
      return false;
1440
5
    case 'i':
1441
8
    case 't':
1442
11
    case '2':
1443
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1444
11
      if (SSELevel < SSE2)
1445
0
        return false;
1446
11
      break;
1447
26
    }
1448
11
    break;
1449
30
  case 'v':
1450
101
  case 'x':
1451
101
    if (hasFeatureEnabled(FeatureMap, "avx512f"))
1452
      // 512-bit zmm registers can be used if target supports AVX512F.
1453
46
      return Size <= 512U;
1454
55
    else if (hasFeatureEnabled(FeatureMap, "avx"))
1455
      // 256-bit ymm registers can be used if target supports AVX.
1456
27
      return Size <= 256U;
1457
28
    return Size <= 128U;
1458
1459
9.43k
  }
1460
1461
9.27k
  return true;
1462
9.43k
}
1463
1464
2.05k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1465
2.05k
  switch (*Constraint) {
1466
29
  case '@':
1467
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1468
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1469
29
      Constraint += Len - 1;
1470
29
      return Converted;
1471
29
    }
1472
0
    return std::string(1, *Constraint);
1473
145
  case 'a':
1474
145
    return std::string("{ax}");
1475
89
  case 'b':
1476
89
    return std::string("{bx}");
1477
131
  case 'c':
1478
131
    return std::string("{cx}");
1479
94
  case 'd':
1480
94
    return std::string("{dx}");
1481
29
  case 'S':
1482
29
    return std::string("{si}");
1483
51
  case 'D':
1484
51
    return std::string("{di}");
1485
4
  case 'p': // address
1486
4
    return std::string("im");
1487
3
  case 't': // top of floating point stack.
1488
3
    return std::string("{st}");
1489
1
  case 'u':                        // second from top of floating point stack.
1490
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1491
26
  case 'Y':
1492
26
    switch (Constraint[1]) {
1493
0
    default:
1494
      // Break from inner switch and fall through (copy single char),
1495
      // continue parsing after copying the current constraint into
1496
      // the return string.
1497
0
      break;
1498
4
    case 'k':
1499
5
    case 'm':
1500
10
    case 'i':
1501
13
    case 't':
1502
23
    case 'z':
1503
26
    case '2':
1504
      // "^" hints llvm that this is a 2 letter constraint.
1505
      // "Constraint++" is used to promote the string iterator
1506
      // to the next constraint.
1507
26
      return std::string("^") + std::string(Constraint++, 2);
1508
26
    }
1509
26
    
LLVM_FALLTHROUGH0
;0
1510
1.45k
  default:
1511
1.45k
    return std::string(1, *Constraint);
1512
2.05k
  }
1513
2.05k
}
1514
1515
2
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1516
2
  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1517
2
  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1518
2
}
1519
1520
5
void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1521
5
  llvm::X86::fillValidTuneCPUList(Values);
1522
5
}
1523
1524
3.40k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1525
3.40k
  return llvm::makeArrayRef(GCCRegNames);
1526
3.40k
}
1527
1528
2.93k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1529
2.93k
  return llvm::makeArrayRef(AddlRegNames);
1530
2.93k
}
1531
1532
14.6k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1533
14.6k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1534
14.6k
                                                Builtin::FirstTSBuiltin + 1);
1535
14.6k
}
1536
1537
63.1k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1538
63.1k
  return llvm::makeArrayRef(BuiltinInfoX86,
1539
63.1k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1540
63.1k
}