Coverage Report

Created: 2020-02-25 14:32

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
};
66
67
const TargetInfo::AddlRegName AddlRegNames[] = {
68
    {{"al", "ah", "eax", "rax"}, 0},
69
    {{"bl", "bh", "ebx", "rbx"}, 3},
70
    {{"cl", "ch", "ecx", "rcx"}, 2},
71
    {{"dl", "dh", "edx", "rdx"}, 1},
72
    {{"esi", "rsi"}, 4},
73
    {{"edi", "rdi"}, 5},
74
    {{"esp", "rsp"}, 7},
75
    {{"ebp", "rbp"}, 6},
76
    {{"r8d", "r8w", "r8b"}, 38},
77
    {{"r9d", "r9w", "r9b"}, 39},
78
    {{"r10d", "r10w", "r10b"}, 40},
79
    {{"r11d", "r11w", "r11b"}, 41},
80
    {{"r12d", "r12w", "r12b"}, 42},
81
    {{"r13d", "r13w", "r13b"}, 43},
82
    {{"r14d", "r14w", "r14b"}, 44},
83
    {{"r15d", "r15w", "r15b"}, 45},
84
};
85
86
} // namespace targets
87
} // namespace clang
88
89
using namespace clang;
90
using namespace clang::targets;
91
92
5
bool X86TargetInfo::setFPMath(StringRef Name) {
93
5
  if (Name == "387") {
94
2
    FPMath = FP_387;
95
2
    return true;
96
2
  }
97
3
  if (Name == "sse") {
98
2
    FPMath = FP_SSE;
99
2
    return true;
100
2
  }
101
1
  return false;
102
1
}
103
104
bool X86TargetInfo::initFeatureMap(
105
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106
113k
    const std::vector<std::string> &FeaturesVec) const {
107
113k
  // FIXME: This *really* should not be here.
108
113k
  // X86_64 always has SSE2.
109
113k
  if (getTriple().getArch() == llvm::Triple::x86_64)
110
106k
    setFeatureEnabledImpl(Features, "sse2", true);
111
113k
112
113k
  const CPUKind Kind = getCPUKind(CPU);
113
113k
114
113k
  // Enable X87 for all X86 processors but Lakemont.
115
113k
  if (Kind != CK_Lakemont)
116
113k
    setFeatureEnabledImpl(Features, "x87", true);
117
113k
118
113k
  // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
119
113k
  // compatibility.
120
113k
  if (Kind >= CK_i586 || 
Kind == CK_Generic91.7k
)
121
113k
    setFeatureEnabledImpl(Features, "cx8", true);
122
113k
123
113k
  switch (Kind) {
124
91.7k
  case CK_Generic:
125
91.7k
  case CK_i386:
126
91.7k
  case CK_i486:
127
91.7k
  case CK_i586:
128
91.7k
  case CK_Pentium:
129
91.7k
  case CK_PentiumPro:
130
91.7k
  case CK_i686:
131
91.7k
  case CK_Lakemont:
132
91.7k
    break;
133
91.7k
134
91.7k
  case CK_Cooperlake:
135
2
    // CPX inherits all CLX features plus AVX512BF16
136
2
    setFeatureEnabledImpl(Features, "avx512bf16", true);
137
2
    LLVM_FALLTHROUGH;
138
4
  case CK_Cascadelake:
139
4
    // CLX inherits all SKX features plus AVX512VNNI
140
4
    setFeatureEnabledImpl(Features, "avx512vnni", true);
141
4
    LLVM_FALLTHROUGH;
142
959
  case CK_SkylakeServer:
143
959
    setFeatureEnabledImpl(Features, "avx512f", true);
144
959
    setFeatureEnabledImpl(Features, "avx512cd", true);
145
959
    setFeatureEnabledImpl(Features, "avx512dq", true);
146
959
    setFeatureEnabledImpl(Features, "avx512bw", true);
147
959
    setFeatureEnabledImpl(Features, "avx512vl", true);
148
959
    setFeatureEnabledImpl(Features, "clwb", true);
149
959
    setFeatureEnabledImpl(Features, "pku", true);
150
959
    // SkylakeServer cores inherits all SKL features, except SGX
151
959
    goto SkylakeCommon;
152
4
153
4
  case CK_Tigerlake:
154
2
    setFeatureEnabledImpl(Features, "avx512vp2intersect", true);
155
2
    setFeatureEnabledImpl(Features, "movdiri", true);
156
2
    setFeatureEnabledImpl(Features, "movdir64b", true);
157
2
    setFeatureEnabledImpl(Features, "shstk", true);
158
2
    // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd
159
2
    goto IcelakeCommon;
160
4
161
4
  case CK_IcelakeServer:
162
3
    setFeatureEnabledImpl(Features, "pconfig", true);
163
3
    setFeatureEnabledImpl(Features, "wbnoinvd", true);
164
3
    LLVM_FALLTHROUGH;
165
6
  case CK_IcelakeClient:
166
8
IcelakeCommon:
167
8
    setFeatureEnabledImpl(Features, "vaes", true);
168
8
    setFeatureEnabledImpl(Features, "gfni", true);
169
8
    setFeatureEnabledImpl(Features, "vpclmulqdq", true);
170
8
    setFeatureEnabledImpl(Features, "avx512bitalg", true);
171
8
    setFeatureEnabledImpl(Features, "avx512vbmi2", true);
172
8
    setFeatureEnabledImpl(Features, "avx512vnni", true);
173
8
    setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
174
8
    setFeatureEnabledImpl(Features, "rdpid", true);
175
8
    setFeatureEnabledImpl(Features, "clwb", true);
176
8
    LLVM_FALLTHROUGH;
177
11
  case CK_Cannonlake:
178
11
    setFeatureEnabledImpl(Features, "avx512f", true);
179
11
    setFeatureEnabledImpl(Features, "avx512cd", true);
180
11
    setFeatureEnabledImpl(Features, "avx512dq", true);
181
11
    setFeatureEnabledImpl(Features, "avx512bw", true);
182
11
    setFeatureEnabledImpl(Features, "avx512vl", true);
183
11
    setFeatureEnabledImpl(Features, "avx512ifma", true);
184
11
    setFeatureEnabledImpl(Features, "avx512vbmi", true);
185
11
    setFeatureEnabledImpl(Features, "pku", true);
186
11
    setFeatureEnabledImpl(Features, "sha", true);
187
11
    LLVM_FALLTHROUGH;
188
17
  case CK_SkylakeClient:
189
17
    setFeatureEnabledImpl(Features, "sgx", true);
190
17
    // SkylakeServer cores inherits all SKL features, except SGX
191
976
SkylakeCommon:
192
976
    setFeatureEnabledImpl(Features, "xsavec", true);
193
976
    setFeatureEnabledImpl(Features, "xsaves", true);
194
976
    setFeatureEnabledImpl(Features, "clflushopt", true);
195
976
    setFeatureEnabledImpl(Features, "aes", true);
196
976
    LLVM_FALLTHROUGH;
197
996
  case CK_Broadwell:
198
996
    setFeatureEnabledImpl(Features, "rdseed", true);
199
996
    setFeatureEnabledImpl(Features, "adx", true);
200
996
    setFeatureEnabledImpl(Features, "prfchw", true);
201
996
    LLVM_FALLTHROUGH;
202
1.00k
  case CK_Haswell:
203
1.00k
    setFeatureEnabledImpl(Features, "avx2", true);
204
1.00k
    setFeatureEnabledImpl(Features, "lzcnt", true);
205
1.00k
    setFeatureEnabledImpl(Features, "bmi", true);
206
1.00k
    setFeatureEnabledImpl(Features, "bmi2", true);
207
1.00k
    setFeatureEnabledImpl(Features, "fma", true);
208
1.00k
    setFeatureEnabledImpl(Features, "invpcid", true);
209
1.00k
    setFeatureEnabledImpl(Features, "movbe", true);
210
1.00k
    LLVM_FALLTHROUGH;
211
1.08k
  case CK_IvyBridge:
212
1.08k
    setFeatureEnabledImpl(Features, "rdrnd", true);
213
1.08k
    setFeatureEnabledImpl(Features, "f16c", true);
214
1.08k
    setFeatureEnabledImpl(Features, "fsgsbase", true);
215
1.08k
    LLVM_FALLTHROUGH;
216
1.12k
  case CK_SandyBridge:
217
1.12k
    setFeatureEnabledImpl(Features, "avx", true);
218
1.12k
    setFeatureEnabledImpl(Features, "xsave", true);
219
1.12k
    setFeatureEnabledImpl(Features, "xsaveopt", true);
220
1.12k
    LLVM_FALLTHROUGH;
221
1.12k
  case CK_Westmere:
222
1.12k
    setFeatureEnabledImpl(Features, "pclmul", true);
223
1.12k
    LLVM_FALLTHROUGH;
224
1.16k
  case CK_Nehalem:
225
1.16k
    setFeatureEnabledImpl(Features, "sse4.2", true);
226
1.16k
    LLVM_FALLTHROUGH;
227
19.3k
  case CK_Penryn:
228
19.3k
    setFeatureEnabledImpl(Features, "sse4.1", true);
229
19.3k
    LLVM_FALLTHROUGH;
230
19.4k
  case CK_Core2:
231
19.4k
    setFeatureEnabledImpl(Features, "ssse3", true);
232
19.4k
    setFeatureEnabledImpl(Features, "sahf", true);
233
19.4k
    LLVM_FALLTHROUGH;
234
19.4k
  case CK_Nocona:
235
19.4k
    setFeatureEnabledImpl(Features, "cx16", true);
236
19.4k
    LLVM_FALLTHROUGH;
237
19.4k
  case CK_Yonah:
238
19.4k
  case CK_Prescott:
239
19.4k
    setFeatureEnabledImpl(Features, "sse3", true);
240
19.4k
    LLVM_FALLTHROUGH;
241
21.9k
  case CK_PentiumM:
242
21.9k
  case CK_Pentium4:
243
21.9k
  case CK_x86_64:
244
21.9k
    setFeatureEnabledImpl(Features, "sse2", true);
245
21.9k
    LLVM_FALLTHROUGH;
246
21.9k
  case CK_Pentium3:
247
21.9k
  case CK_C3_2:
248
21.9k
    setFeatureEnabledImpl(Features, "sse", true);
249
21.9k
    LLVM_FALLTHROUGH;
250
21.9k
  case CK_Pentium2:
251
21.9k
    setFeatureEnabledImpl(Features, "fxsr", true);
252
21.9k
    LLVM_FALLTHROUGH;
253
21.9k
  case CK_PentiumMMX:
254
21.9k
  case CK_K6:
255
21.9k
  case CK_WinChipC6:
256
21.9k
    setFeatureEnabledImpl(Features, "mmx", true);
257
21.9k
    break;
258
21.9k
259
21.9k
  case CK_Tremont:
260
2
    setFeatureEnabledImpl(Features, "cldemote", true);
261
2
    setFeatureEnabledImpl(Features, "movdiri", true);
262
2
    setFeatureEnabledImpl(Features, "movdir64b", true);
263
2
    setFeatureEnabledImpl(Features, "gfni", true);
264
2
    setFeatureEnabledImpl(Features, "waitpkg", true);
265
2
    LLVM_FALLTHROUGH;
266
4
  case CK_GoldmontPlus:
267
4
    setFeatureEnabledImpl(Features, "ptwrite", true);
268
4
    setFeatureEnabledImpl(Features, "rdpid", true);
269
4
    setFeatureEnabledImpl(Features, "sgx", true);
270
4
    LLVM_FALLTHROUGH;
271
6
  case CK_Goldmont:
272
6
    setFeatureEnabledImpl(Features, "sha", true);
273
6
    setFeatureEnabledImpl(Features, "rdseed", true);
274
6
    setFeatureEnabledImpl(Features, "xsave", true);
275
6
    setFeatureEnabledImpl(Features, "xsaveopt", true);
276
6
    setFeatureEnabledImpl(Features, "xsavec", true);
277
6
    setFeatureEnabledImpl(Features, "xsaves", true);
278
6
    setFeatureEnabledImpl(Features, "clflushopt", true);
279
6
    setFeatureEnabledImpl(Features, "fsgsbase", true);
280
6
    setFeatureEnabledImpl(Features, "aes", true);
281
6
    LLVM_FALLTHROUGH;
282
9
  case CK_Silvermont:
283
9
    setFeatureEnabledImpl(Features, "rdrnd", true);
284
9
    setFeatureEnabledImpl(Features, "pclmul", true);
285
9
    setFeatureEnabledImpl(Features, "sse4.2", true);
286
9
    setFeatureEnabledImpl(Features, "prfchw", true);
287
9
    LLVM_FALLTHROUGH;
288
57
  case CK_Bonnell:
289
57
    setFeatureEnabledImpl(Features, "movbe", true);
290
57
    setFeatureEnabledImpl(Features, "ssse3", true);
291
57
    setFeatureEnabledImpl(Features, "fxsr", true);
292
57
    setFeatureEnabledImpl(Features, "cx16", true);
293
57
    setFeatureEnabledImpl(Features, "sahf", true);
294
57
    setFeatureEnabledImpl(Features, "mmx", true);
295
57
    break;
296
9
297
9
  case CK_KNM:
298
3
    // TODO: Add avx5124fmaps/avx5124vnniw.
299
3
    setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
300
3
    LLVM_FALLTHROUGH;
301
13
  case CK_KNL:
302
13
    setFeatureEnabledImpl(Features, "avx512f", true);
303
13
    setFeatureEnabledImpl(Features, "avx512cd", true);
304
13
    setFeatureEnabledImpl(Features, "avx512er", true);
305
13
    setFeatureEnabledImpl(Features, "avx512pf", true);
306
13
    setFeatureEnabledImpl(Features, "prfchw", true);
307
13
    setFeatureEnabledImpl(Features, "prefetchwt1", true);
308
13
    setFeatureEnabledImpl(Features, "fxsr", true);
309
13
    setFeatureEnabledImpl(Features, "rdseed", true);
310
13
    setFeatureEnabledImpl(Features, "adx", true);
311
13
    setFeatureEnabledImpl(Features, "lzcnt", true);
312
13
    setFeatureEnabledImpl(Features, "bmi", true);
313
13
    setFeatureEnabledImpl(Features, "bmi2", true);
314
13
    setFeatureEnabledImpl(Features, "fma", true);
315
13
    setFeatureEnabledImpl(Features, "rdrnd", true);
316
13
    setFeatureEnabledImpl(Features, "f16c", true);
317
13
    setFeatureEnabledImpl(Features, "fsgsbase", true);
318
13
    setFeatureEnabledImpl(Features, "aes", true);
319
13
    setFeatureEnabledImpl(Features, "pclmul", true);
320
13
    setFeatureEnabledImpl(Features, "cx16", true);
321
13
    setFeatureEnabledImpl(Features, "xsaveopt", true);
322
13
    setFeatureEnabledImpl(Features, "xsave", true);
323
13
    setFeatureEnabledImpl(Features, "movbe", true);
324
13
    setFeatureEnabledImpl(Features, "sahf", true);
325
13
    setFeatureEnabledImpl(Features, "mmx", true);
326
13
    break;
327
3
328
4
  case CK_K6_2:
329
4
  case CK_K6_3:
330
4
  case CK_WinChip2:
331
4
  case CK_C3:
332
4
    setFeatureEnabledImpl(Features, "3dnow", true);
333
4
    break;
334
4
335
4
  case CK_AMDFAM10:
336
4
    setFeatureEnabledImpl(Features, "sse4a", true);
337
4
    setFeatureEnabledImpl(Features, "lzcnt", true);
338
4
    setFeatureEnabledImpl(Features, "popcnt", true);
339
4
    setFeatureEnabledImpl(Features, "sahf", true);
340
4
    LLVM_FALLTHROUGH;
341
13
  case CK_K8SSE3:
342
13
    setFeatureEnabledImpl(Features, "sse3", true);
343
13
    LLVM_FALLTHROUGH;
344
25
  case CK_K8:
345
25
    setFeatureEnabledImpl(Features, "sse2", true);
346
25
    LLVM_FALLTHROUGH;
347
28
  case CK_AthlonXP:
348
28
    setFeatureEnabledImpl(Features, "sse", true);
349
28
    setFeatureEnabledImpl(Features, "fxsr", true);
350
28
    LLVM_FALLTHROUGH;
351
31
  case CK_Athlon:
352
31
  case CK_Geode:
353
31
    setFeatureEnabledImpl(Features, "3dnowa", true);
354
31
    break;
355
31
356
31
  case CK_BTVER2:
357
12
    setFeatureEnabledImpl(Features, "avx", true);
358
12
    setFeatureEnabledImpl(Features, "aes", true);
359
12
    setFeatureEnabledImpl(Features, "pclmul", true);
360
12
    setFeatureEnabledImpl(Features, "bmi", true);
361
12
    setFeatureEnabledImpl(Features, "f16c", true);
362
12
    setFeatureEnabledImpl(Features, "xsaveopt", true);
363
12
    setFeatureEnabledImpl(Features, "movbe", true);
364
12
    LLVM_FALLTHROUGH;
365
16
  case CK_BTVER1:
366
16
    setFeatureEnabledImpl(Features, "ssse3", true);
367
16
    setFeatureEnabledImpl(Features, "sse4a", true);
368
16
    setFeatureEnabledImpl(Features, "lzcnt", true);
369
16
    setFeatureEnabledImpl(Features, "popcnt", true);
370
16
    setFeatureEnabledImpl(Features, "prfchw", true);
371
16
    setFeatureEnabledImpl(Features, "cx16", true);
372
16
    setFeatureEnabledImpl(Features, "fxsr", true);
373
16
    setFeatureEnabledImpl(Features, "sahf", true);
374
16
    setFeatureEnabledImpl(Features, "mmx", true);
375
16
    break;
376
12
377
12
  case CK_ZNVER2:
378
3
    setFeatureEnabledImpl(Features, "clwb", true);
379
3
    setFeatureEnabledImpl(Features, "rdpid", true);
380
3
    setFeatureEnabledImpl(Features, "wbnoinvd", true);
381
3
    LLVM_FALLTHROUGH;
382
7
  case CK_ZNVER1:
383
7
    setFeatureEnabledImpl(Features, "adx", true);
384
7
    setFeatureEnabledImpl(Features, "aes", true);
385
7
    setFeatureEnabledImpl(Features, "avx2", true);
386
7
    setFeatureEnabledImpl(Features, "bmi", true);
387
7
    setFeatureEnabledImpl(Features, "bmi2", true);
388
7
    setFeatureEnabledImpl(Features, "clflushopt", true);
389
7
    setFeatureEnabledImpl(Features, "clzero", true);
390
7
    setFeatureEnabledImpl(Features, "cx16", true);
391
7
    setFeatureEnabledImpl(Features, "f16c", true);
392
7
    setFeatureEnabledImpl(Features, "fma", true);
393
7
    setFeatureEnabledImpl(Features, "fsgsbase", true);
394
7
    setFeatureEnabledImpl(Features, "fxsr", true);
395
7
    setFeatureEnabledImpl(Features, "lzcnt", true);
396
7
    setFeatureEnabledImpl(Features, "mmx", true);
397
7
    setFeatureEnabledImpl(Features, "mwaitx", true);
398
7
    setFeatureEnabledImpl(Features, "movbe", true);
399
7
    setFeatureEnabledImpl(Features, "pclmul", true);
400
7
    setFeatureEnabledImpl(Features, "popcnt", true);
401
7
    setFeatureEnabledImpl(Features, "prfchw", true);
402
7
    setFeatureEnabledImpl(Features, "rdrnd", true);
403
7
    setFeatureEnabledImpl(Features, "rdseed", true);
404
7
    setFeatureEnabledImpl(Features, "sahf", true);
405
7
    setFeatureEnabledImpl(Features, "sha", true);
406
7
    setFeatureEnabledImpl(Features, "sse4a", true);
407
7
    setFeatureEnabledImpl(Features, "xsave", true);
408
7
    setFeatureEnabledImpl(Features, "xsavec", true);
409
7
    setFeatureEnabledImpl(Features, "xsaveopt", true);
410
7
    setFeatureEnabledImpl(Features, "xsaves", true);
411
7
    break;
412
3
413
3
  case CK_BDVER4:
414
3
    setFeatureEnabledImpl(Features, "avx2", true);
415
3
    setFeatureEnabledImpl(Features, "bmi2", true);
416
3
    setFeatureEnabledImpl(Features, "mwaitx", true);
417
3
    LLVM_FALLTHROUGH;
418
6
  case CK_BDVER3:
419
6
    setFeatureEnabledImpl(Features, "fsgsbase", true);
420
6
    setFeatureEnabledImpl(Features, "xsaveopt", true);
421
6
    LLVM_FALLTHROUGH;
422
10
  case CK_BDVER2:
423
10
    setFeatureEnabledImpl(Features, "bmi", true);
424
10
    setFeatureEnabledImpl(Features, "fma", true);
425
10
    setFeatureEnabledImpl(Features, "f16c", true);
426
10
    setFeatureEnabledImpl(Features, "tbm", true);
427
10
    LLVM_FALLTHROUGH;
428
14
  case CK_BDVER1:
429
14
    // xop implies avx, sse4a and fma4.
430
14
    setFeatureEnabledImpl(Features, "xop", true);
431
14
    setFeatureEnabledImpl(Features, "lwp", true);
432
14
    setFeatureEnabledImpl(Features, "lzcnt", true);
433
14
    setFeatureEnabledImpl(Features, "aes", true);
434
14
    setFeatureEnabledImpl(Features, "pclmul", true);
435
14
    setFeatureEnabledImpl(Features, "prfchw", true);
436
14
    setFeatureEnabledImpl(Features, "cx16", true);
437
14
    setFeatureEnabledImpl(Features, "fxsr", true);
438
14
    setFeatureEnabledImpl(Features, "xsave", true);
439
14
    setFeatureEnabledImpl(Features, "sahf", true);
440
14
    setFeatureEnabledImpl(Features, "mmx", true);
441
14
    break;
442
113k
  }
443
113k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
444
0
    return false;
445
113k
446
113k
  // Can't do this earlier because we need to be able to explicitly enable
447
113k
  // or disable these features and the things that they depend upon.
448
113k
449
113k
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
450
113k
  auto I = Features.find("sse4.2");
451
113k
  if (I != Features.end() && 
I->getValue()43.9k
&&
452
113k
      
llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()43.9k
)
453
43.9k
    Features["popcnt"] = true;
454
113k
455
113k
  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
456
113k
  I = Features.find("3dnow");
457
113k
  if (I != Features.end() && 
I->getValue()304
&&
458
113k
      
llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()297
)
459
296
    Features["prfchw"] = true;
460
113k
461
113k
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
462
113k
  // then enable MMX.
463
113k
  I = Features.find("sse");
464
113k
  if (I != Features.end() && 
I->getValue()109k
&&
465
113k
      
llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()109k
)
466
109k
    Features["mmx"] = true;
467
113k
468
113k
  return true;
469
113k
}
470
471
void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
472
448k
                                X86SSEEnum Level, bool Enabled) {
473
448k
  if (Enabled) {
474
448k
    switch (Level) {
475
87.5k
    case AVX512F:
476
87.5k
      Features["avx512f"] = true;
477
87.5k
      Features["fma"] = true;
478
87.5k
      Features["f16c"] = true;
479
87.5k
      LLVM_FALLTHROUGH;
480
100k
    case AVX2:
481
100k
      Features["avx2"] = true;
482
100k
      LLVM_FALLTHROUGH;
483
142k
    case AVX:
484
142k
      Features["avx"] = true;
485
142k
      Features["xsave"] = true;
486
142k
      LLVM_FALLTHROUGH;
487
155k
    case SSE42:
488
155k
      Features["sse4.2"] = true;
489
155k
      LLVM_FALLTHROUGH;
490
188k
    case SSE41:
491
188k
      Features["sse4.1"] = true;
492
188k
      LLVM_FALLTHROUGH;
493
221k
    case SSSE3:
494
221k
      Features["ssse3"] = true;
495
221k
      LLVM_FALLTHROUGH;
496
257k
    case SSE3:
497
257k
      Features["sse3"] = true;
498
257k
      LLVM_FALLTHROUGH;
499
409k
    case SSE2:
500
409k
      Features["sse2"] = true;
501
409k
      LLVM_FALLTHROUGH;
502
448k
    case SSE1:
503
448k
      Features["sse"] = true;
504
448k
      LLVM_FALLTHROUGH;
505
448k
    case NoSSE:
506
448k
      break;
507
448k
    }
508
448k
    return;
509
448k
  }
510
47
511
47
  switch (Level) {
512
11
  case NoSSE:
513
11
  case SSE1:
514
11
    Features["sse"] = false;
515
11
    LLVM_FALLTHROUGH;
516
29
  case SSE2:
517
29
    Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
518
29
    Features["sha"] = Features["gfni"] = false;
519
29
    LLVM_FALLTHROUGH;
520
30
  case SSE3:
521
30
    Features["sse3"] = false;
522
30
    setXOPLevel(Features, NoXOP, false);
523
30
    LLVM_FALLTHROUGH;
524
31
  case SSSE3:
525
31
    Features["ssse3"] = false;
526
31
    LLVM_FALLTHROUGH;
527
35
  case SSE41:
528
35
    Features["sse4.1"] = false;
529
35
    LLVM_FALLTHROUGH;
530
37
  case SSE42:
531
37
    Features["sse4.2"] = false;
532
37
    LLVM_FALLTHROUGH;
533
41
  case AVX:
534
41
    Features["fma"] = Features["avx"] = Features["f16c"] = false;
535
41
    Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false;
536
41
    Features["vpclmulqdq"] = false;
537
41
    setXOPLevel(Features, FMA4, false);
538
41
    LLVM_FALLTHROUGH;
539
42
  case AVX2:
540
42
    Features["avx2"] = false;
541
42
    LLVM_FALLTHROUGH;
542
47
  case AVX512F:
543
47
    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false;
544
47
    Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false;
545
47
    Features["avx512vl"] = Features["avx512vbmi"] = false;
546
47
    Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
547
47
    Features["avx512bitalg"] = Features["avx512vnni"] = false;
548
47
    Features["avx512vbmi2"] = Features["avx512bf16"] = false;
549
47
    Features["avx512vp2intersect"] = false;
550
47
    break;
551
47
  }
552
47
}
553
554
void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
555
38.3k
                                MMX3DNowEnum Level, bool Enabled) {
556
38.3k
  if (Enabled) {
557
38.3k
    switch (Level) {
558
339
    case AMD3DNowAthlon:
559
339
      Features["3dnowa"] = true;
560
339
      LLVM_FALLTHROUGH;
561
547
    case AMD3DNow:
562
547
      Features["3dnow"] = true;
563
547
      LLVM_FALLTHROUGH;
564
38.3k
    case MMX:
565
38.3k
      Features["mmx"] = true;
566
38.3k
      LLVM_FALLTHROUGH;
567
38.3k
    case NoMMX3DNow:
568
38.3k
      break;
569
38.3k
    }
570
38.3k
    return;
571
38.3k
  }
572
7
573
7
  switch (Level) {
574
6
  case NoMMX3DNow:
575
6
  case MMX:
576
6
    Features["mmx"] = false;
577
6
    LLVM_FALLTHROUGH;
578
7
  case AMD3DNow:
579
7
    Features["3dnow"] = false;
580
7
    LLVM_FALLTHROUGH;
581
7
  case AMD3DNowAthlon:
582
7
    Features["3dnowa"] = false;
583
7
    break;
584
7
  }
585
7
}
586
587
void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
588
3.07k
                                bool Enabled) {
589
3.07k
  if (Enabled) {
590
2.99k
    switch (Level) {
591
2.07k
    case XOP:
592
2.07k
      Features["xop"] = true;
593
2.07k
      LLVM_FALLTHROUGH;
594
2.63k
    case FMA4:
595
2.63k
      Features["fma4"] = true;
596
2.63k
      setSSELevel(Features, AVX, true);
597
2.63k
      LLVM_FALLTHROUGH;
598
2.99k
    case SSE4A:
599
2.99k
      Features["sse4a"] = true;
600
2.99k
      setSSELevel(Features, SSE3, true);
601
2.99k
      LLVM_FALLTHROUGH;
602
2.99k
    case NoXOP:
603
2.99k
      break;
604
2.99k
    }
605
2.99k
    return;
606
2.99k
  }
607
74
608
74
  switch (Level) {
609
31
  case NoXOP:
610
31
  case SSE4A:
611
31
    Features["sse4a"] = false;
612
31
    LLVM_FALLTHROUGH;
613
73
  case FMA4:
614
73
    Features["fma4"] = false;
615
73
    LLVM_FALLTHROUGH;
616
74
  case XOP:
617
74
    Features["xop"] = false;
618
74
    break;
619
74
  }
620
74
}
621
622
void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
623
857k
                                          StringRef Name, bool Enabled) {
624
857k
  // This is a bit of a hack to deal with the sse4 target feature when used
625
857k
  // as part of the target attribute. We handle sse4 correctly everywhere
626
857k
  // else. See below for more information on how we handle the sse4 options.
627
857k
  if (Name != "sse4")
628
857k
    Features[Name] = Enabled;
629
857k
630
857k
  if (Name == "mmx") {
631
37.7k
    setMMXLevel(Features, MMX, Enabled);
632
820k
  } else if (Name == "sse") {
633
39.0k
    setSSELevel(Features, SSE1, Enabled);
634
781k
  } else if (Name == "sse2") {
635
149k
    setSSELevel(Features, SSE2, Enabled);
636
631k
  } else if (Name == "sse3") {
637
32.3k
    setSSELevel(Features, SSE3, Enabled);
638
598k
  } else if (Name == "ssse3") {
639
33.5k
    setSSELevel(Features, SSSE3, Enabled);
640
565k
  } else if (Name == "sse4.2") {
641
12.9k
    setSSELevel(Features, SSE42, Enabled);
642
552k
  } else if (Name == "sse4.1") {
643
32.6k
    setSSELevel(Features, SSE41, Enabled);
644
519k
  } else if (Name == "3dnow") {
645
209
    setMMXLevel(Features, AMD3DNow, Enabled);
646
519k
  } else if (Name == "3dnowa") {
647
339
    setMMXLevel(Features, AMD3DNowAthlon, Enabled);
648
519k
  } else if (Name == "aes") {
649
1.12k
    if (Enabled)
650
1.11k
      setSSELevel(Features, SSE2, Enabled);
651
5
    else
652
5
      Features["vaes"] = false;
653
518k
  } else if (Name == "vaes") {
654
129
    if (Enabled) {
655
128
      setSSELevel(Features, AVX, Enabled);
656
128
      Features["aes"] = true;
657
128
    }
658
517k
  } else if (Name == "pclmul") {
659
1.28k
    if (Enabled)
660
1.27k
      setSSELevel(Features, SSE2, Enabled);
661
3
    else
662
3
      Features["vpclmulqdq"] = false;
663
516k
  } else if (Name == "vpclmulqdq") {
664
24
    if (Enabled) {
665
23
      setSSELevel(Features, AVX, Enabled);
666
23
      Features["pclmul"] = true;
667
23
    }
668
516k
  } else if (Name == "gfni") {
669
202
     if (Enabled)
670
201
      setSSELevel(Features, SSE2, Enabled);
671
516k
  } else if (Name == "avx") {
672
17.7k
    setSSELevel(Features, AVX, Enabled);
673
498k
  } else if (Name == "avx2") {
674
13.4k
    setSSELevel(Features, AVX2, Enabled);
675
485k
  } else if (Name == "avx512f") {
676
33.8k
    setSSELevel(Features, AVX512F, Enabled);
677
451k
  } else if (Name.startswith("avx512")) {
678
53.7k
    if (Enabled)
679
53.7k
      setSSELevel(Features, AVX512F, Enabled);
680
53.7k
    // Enable BWI instruction if certain features are being enabled.
681
53.7k
    if ((Name == "avx512vbmi" || 
Name == "avx512vbmi2"53.3k
||
682
53.7k
         
Name == "avx512bitalg"52.0k
||
Name == "avx512bf16"51.7k
) &&
Enabled2.53k
)
683
2.52k
      Features["avx512bw"] = true;
684
53.7k
    // Also disable some features if BWI is being disabled.
685
53.7k
    if (Name == "avx512bw" && 
!Enabled16.8k
) {
686
5
      Features["avx512vbmi"] = false;
687
5
      Features["avx512vbmi2"] = false;
688
5
      Features["avx512bitalg"] = false;
689
5
      Features["avx512bf16"] = false;
690
5
    }
691
397k
  } else if (Name == "fma") {
692
11.2k
    if (Enabled)
693
11.2k
      setSSELevel(Features, AVX, Enabled);
694
1
    else
695
1
      setSSELevel(Features, AVX512F, Enabled);
696
386k
  } else if (Name == "fma4") {
697
564
    setXOPLevel(Features, FMA4, Enabled);
698
385k
  } else if (Name == "xop") {
699
2.07k
    setXOPLevel(Features, XOP, Enabled);
700
383k
  } else if (Name == "sse4a") {
701
359
    setXOPLevel(Features, SSE4A, Enabled);
702
383k
  } else if (Name == "f16c") {
703
9.89k
    if (Enabled)
704
9.89k
      setSSELevel(Features, AVX, Enabled);
705
1
    else
706
1
      setSSELevel(Features, AVX512F, Enabled);
707
373k
  } else if (Name == "sha") {
708
88
    if (Enabled)
709
86
      setSSELevel(Features, SSE2, Enabled);
710
373k
  } else if (Name == "sse4") {
711
4
    // We can get here via the __target__ attribute since that's not controlled
712
4
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
713
4
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
714
4
    // disabled.
715
4
    if (Enabled)
716
2
      setSSELevel(Features, SSE42, Enabled);
717
2
    else
718
2
      setSSELevel(Features, SSE41, Enabled);
719
373k
  } else if (Name == "xsave") {
720
13.0k
    if (!Enabled)
721
2
      Features["xsaveopt"] = false;
722
360k
  } else if (Name == "xsaveopt" || 
Name == "xsavec"358k
||
Name == "xsaves"356k
) {
723
5.74k
    if (Enabled)
724
5.74k
      Features["xsave"] = true;
725
5.74k
  }
726
857k
}
727
728
/// handleTargetFeatures - Perform initialization based on the user
729
/// configured set of features.
730
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
731
60.4k
                                         DiagnosticsEngine &Diags) {
732
404k
  for (const auto &Feature : Features) {
733
404k
    if (Feature[0] != '+')
734
847
      continue;
735
403k
736
403k
    if (Feature == "+aes") {
737
87
      HasAES = true;
738
403k
    } else if (Feature == "+vaes") {
739
11
      HasVAES = true;
740
403k
    } else if (Feature == "+pclmul") {
741
111
      HasPCLMUL = true;
742
403k
    } else if (Feature == "+vpclmulqdq") {
743
11
      HasVPCLMULQDQ = true;
744
403k
    } else if (Feature == "+lzcnt") {
745
97
      HasLZCNT = true;
746
403k
    } else if (Feature == "+rdrnd") {
747
74
      HasRDRND = true;
748
403k
    } else if (Feature == "+fsgsbase") {
749
77
      HasFSGSBASE = true;
750
403k
    } else if (Feature == "+bmi") {
751
85
      HasBMI = true;
752
403k
    } else if (Feature == "+bmi2") {
753
67
      HasBMI2 = true;
754
403k
    } else if (Feature == "+popcnt") {
755
268
      HasPOPCNT = true;
756
402k
    } else if (Feature == "+rtm") {
757
1
      HasRTM = true;
758
402k
    } else if (Feature == "+prfchw") {
759
135
      HasPRFCHW = true;
760
402k
    } else if (Feature == "+rdseed") {
761
64
      HasRDSEED = true;
762
402k
    } else if (Feature == "+adx") {
763
58
      HasADX = true;
764
402k
    } else if (Feature == "+tbm") {
765
11
      HasTBM = true;
766
402k
    } else if (Feature == "+lwp") {
767
15
      HasLWP = true;
768
402k
    } else if (Feature == "+fma") {
769
157
      HasFMA = true;
770
402k
    } else if (Feature == "+f16c") {
771
169
      HasF16C = true;
772
402k
    } else if (Feature == "+gfni") {
773
14
      HasGFNI = true;
774
402k
    } else if (Feature == "+avx512cd") {
775
43
      HasAVX512CD = true;
776
402k
    } else if (Feature == "+avx512vpopcntdq") {
777
13
      HasAVX512VPOPCNTDQ = true;
778
402k
    } else if (Feature == "+avx512vnni") {
779
15
      HasAVX512VNNI = true;
780
402k
    } else if (Feature == "+avx512bf16") {
781
6
      HasAVX512BF16 = true;
782
402k
    } else if (Feature == "+avx512er") {
783
12
      HasAVX512ER = true;
784
402k
    } else if (Feature == "+avx512pf") {
785
11
      HasAVX512PF = true;
786
402k
    } else if (Feature == "+avx512dq") {
787
34
      HasAVX512DQ = true;
788
402k
    } else if (Feature == "+avx512bitalg") {
789
11
      HasAVX512BITALG = true;
790
402k
    } else if (Feature == "+avx512bw") {
791
50
      HasAVX512BW = true;
792
401k
    } else if (Feature == "+avx512vl") {
793
48
      HasAVX512VL = true;
794
401k
    } else if (Feature == "+avx512vbmi") {
795
14
      HasAVX512VBMI = true;
796
401k
    } else if (Feature == "+avx512vbmi2") {
797
11
      HasAVX512VBMI2 = true;
798
401k
    } else if (Feature == "+avx512ifma") {
799
14
      HasAVX512IFMA = true;
800
401k
    } else if (Feature == "+avx512vp2intersect") {
801
7
      HasAVX512VP2INTERSECT = true;
802
401k
    } else if (Feature == "+sha") {
803
25
      HasSHA = true;
804
401k
    } else if (Feature == "+shstk") {
805
8
      HasSHSTK = true;
806
401k
    } else if (Feature == "+movbe") {
807
133
      HasMOVBE = true;
808
401k
    } else if (Feature == "+sgx") {
809
21
      HasSGX = true;
810
401k
    } else if (Feature == "+cx8") {
811
60.4k
      HasCX8 = true;
812
341k
    } else if (Feature == "+cx16") {
813
17.6k
      HasCX16 = true;
814
323k
    } else if (Feature == "+fxsr") {
815
20.1k
      HasFXSR = true;
816
303k
    } else if (Feature == "+xsave") {
817
262
      HasXSAVE = true;
818
303k
    } else if (Feature == "+xsaveopt") {
819
102
      HasXSAVEOPT = true;
820
303k
    } else if (Feature == "+xsavec") {
821
56
      HasXSAVEC = true;
822
303k
    } else if (Feature == "+xsaves") {
823
56
      HasXSAVES = true;
824
303k
    } else if (Feature == "+mwaitx") {
825
13
      HasMWAITX = true;
826
302k
    } else if (Feature == "+pku") {
827
32
      HasPKU = true;
828
302k
    } else if (Feature == "+clflushopt") {
829
50
      HasCLFLUSHOPT = true;
830
302k
    } else if (Feature == "+clwb") {
831
32
      HasCLWB = true;
832
302k
    } else if (Feature == "+wbnoinvd") {
833
10
      HasWBNOINVD = true;
834
302k
    } else if (Feature == "+prefetchwt1") {
835
10
      HasPREFETCHWT1 = true;
836
302k
    } else if (Feature == "+clzero") {
837
11
      HasCLZERO = true;
838
302k
    } else if (Feature == "+cldemote") {
839
7
      HasCLDEMOTE = true;
840
302k
    } else if (Feature == "+rdpid") {
841
17
      HasRDPID = true;
842
302k
    } else if (Feature == "+retpoline-external-thunk") {
843
0
      HasRetpolineExternalThunk = true;
844
302k
    } else if (Feature == "+sahf") {
845
17.6k
      HasLAHFSAHF = true;
846
285k
    } else if (Feature == "+waitpkg") {
847
4
      HasWAITPKG = true;
848
285k
    } else if (Feature == "+movdiri") {
849
9
      HasMOVDIRI = true;
850
285k
    } else if (Feature == "+movdir64b") {
851
9
      HasMOVDIR64B = true;
852
285k
    } else if (Feature == "+pconfig") {
853
5
      HasPCONFIG = true;
854
285k
    } else if (Feature == "+ptwrite") {
855
6
      HasPTWRITE = true;
856
285k
    } else if (Feature == "+invpcid") {
857
47
      HasINVPCID = true;
858
285k
    } else if (Feature == "+enqcmd") {
859
3
      HasENQCMD = true;
860
3
    }
861
403k
862
403k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
863
403k
                           .Case("+avx512f", AVX512F)
864
403k
                           .Case("+avx2", AVX2)
865
403k
                           .Case("+avx", AVX)
866
403k
                           .Case("+sse4.2", SSE42)
867
403k
                           .Case("+sse4.1", SSE41)
868
403k
                           .Case("+ssse3", SSSE3)
869
403k
                           .Case("+sse3", SSE3)
870
403k
                           .Case("+sse2", SSE2)
871
403k
                           .Case("+sse", SSE1)
872
403k
                           .Default(NoSSE);
873
403k
    SSELevel = std::max(SSELevel, Level);
874
403k
875
403k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
876
403k
                                      .Case("+3dnowa", AMD3DNowAthlon)
877
403k
                                      .Case("+3dnow", AMD3DNow)
878
403k
                                      .Case("+mmx", MMX)
879
403k
                                      .Default(NoMMX3DNow);
880
403k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
881
403k
882
403k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
883
403k
                         .Case("+xop", XOP)
884
403k
                         .Case("+fma4", FMA4)
885
403k
                         .Case("+sse4a", SSE4A)
886
403k
                         .Default(NoXOP);
887
403k
    XOPLevel = std::max(XOPLevel, XLevel);
888
403k
  }
889
60.4k
890
60.4k
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
891
60.4k
  // matches the selected sse level.
892
60.4k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
893
60.4k
      (FPMath == FP_387 && 
SSELevel >= SSE12
)) {
894
2
    Diags.Report(diag::err_target_unsupported_fpmath)
895
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
896
2
    return false;
897
2
  }
898
60.4k
899
60.4k
  SimdDefaultAlign =
900
60.4k
      hasFeature("avx512f") ? 
512120
:
hasFeature("avx") 60.3k
?
256112
:
12860.2k
;
901
60.4k
  return true;
902
60.4k
}
903
904
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
905
/// definitions for this particular subtarget.
906
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
907
53.4k
                                     MacroBuilder &Builder) const {
908
53.4k
  // Inline assembly supports X86 flag outputs.
909
53.4k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
910
53.4k
911
53.4k
  std::string CodeModel = getTargetOpts().CodeModel;
912
53.4k
  if (CodeModel == "default")
913
42.0k
    CodeModel = "small";
914
53.4k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
915
53.4k
916
53.4k
  // Target identification.
917
53.4k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
918
47.4k
    Builder.defineMacro("__amd64__");
919
47.4k
    Builder.defineMacro("__amd64");
920
47.4k
    Builder.defineMacro("__x86_64");
921
47.4k
    Builder.defineMacro("__x86_64__");
922
47.4k
    if (getTriple().getArchName() == "x86_64h") {
923
2
      Builder.defineMacro("__x86_64h");
924
2
      Builder.defineMacro("__x86_64h__");
925
2
    }
926
47.4k
  } else {
927
5.94k
    DefineStd(Builder, "i386", Opts);
928
5.94k
  }
929
53.4k
930
53.4k
  Builder.defineMacro("__SEG_GS");
931
53.4k
  Builder.defineMacro("__SEG_FS");
932
53.4k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
933
53.4k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
934
53.4k
935
53.4k
  // Subtarget options.
936
53.4k
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
937
53.4k
  // truly should be based on -mtune options.
938
53.4k
  switch (CPU) {
939
33.3k
  case CK_Generic:
940
33.3k
    break;
941
14
  case CK_i386:
942
14
    // The rest are coming from the i386 define above.
943
14
    Builder.defineMacro("__tune_i386__");
944
14
    break;
945
8
  case CK_i486:
946
8
  case CK_WinChipC6:
947
8
  case CK_WinChip2:
948
8
  case CK_C3:
949
8
    defineCPUMacros(Builder, "i486");
950
8
    break;
951
8
  case CK_PentiumMMX:
952
1
    Builder.defineMacro("__pentium_mmx__");
953
1
    Builder.defineMacro("__tune_pentium_mmx__");
954
1
    LLVM_FALLTHROUGH;
955
7
  case CK_i586:
956
7
  case CK_Pentium:
957
7
    defineCPUMacros(Builder, "i586");
958
7
    defineCPUMacros(Builder, "pentium");
959
7
    break;
960
8
  case CK_Pentium3:
961
8
  case CK_PentiumM:
962
8
    Builder.defineMacro("__tune_pentium3__");
963
8
    LLVM_FALLTHROUGH;
964
10
  case CK_Pentium2:
965
10
  case CK_C3_2:
966
10
    Builder.defineMacro("__tune_pentium2__");
967
10
    LLVM_FALLTHROUGH;
968
26
  case CK_PentiumPro:
969
26
  case CK_i686:
970
26
    defineCPUMacros(Builder, "i686");
971
26
    defineCPUMacros(Builder, "pentiumpro");
972
26
    break;
973
2.14k
  case CK_Pentium4:
974
2.14k
    defineCPUMacros(Builder, "pentium4");
975
2.14k
    break;
976
26
  case CK_Yonah:
977
14
  case CK_Prescott:
978
14
  case CK_Nocona:
979
14
    defineCPUMacros(Builder, "nocona");
980
14
    break;
981
17.4k
  case CK_Core2:
982
17.4k
  case CK_Penryn:
983
17.4k
    defineCPUMacros(Builder, "core2");
984
17.4k
    break;
985
17.4k
  case CK_Bonnell:
986
48
    defineCPUMacros(Builder, "atom");
987
48
    break;
988
17.4k
  case CK_Silvermont:
989
3
    defineCPUMacros(Builder, "slm");
990
3
    break;
991
17.4k
  case CK_Goldmont:
992
2
    defineCPUMacros(Builder, "goldmont");
993
2
    break;
994
17.4k
  case CK_GoldmontPlus:
995
2
    defineCPUMacros(Builder, "goldmont_plus");
996
2
    break;
997
17.4k
  case CK_Tremont:
998
2
    defineCPUMacros(Builder, "tremont");
999
2
    break;
1000
17.4k
  case CK_Nehalem:
1001
63
  case CK_Westmere:
1002
63
  case CK_SandyBridge:
1003
63
  case CK_IvyBridge:
1004
63
  case CK_Haswell:
1005
63
  case CK_Broadwell:
1006
63
  case CK_SkylakeClient:
1007
63
  case CK_SkylakeServer:
1008
63
  case CK_Cascadelake:
1009
63
  case CK_Cooperlake:
1010
63
  case CK_Cannonlake:
1011
63
  case CK_IcelakeClient:
1012
63
  case CK_IcelakeServer:
1013
63
  case CK_Tigerlake:
1014
63
    // FIXME: Historically, we defined this legacy name, it would be nice to
1015
63
    // remove it at some point. We've never exposed fine-grained names for
1016
63
    // recent primary x86 CPUs, and we should keep it that way.
1017
63
    defineCPUMacros(Builder, "corei7");
1018
63
    break;
1019
63
  case CK_KNL:
1020
7
    defineCPUMacros(Builder, "knl");
1021
7
    break;
1022
63
  case CK_KNM:
1023
3
    break;
1024
63
  case CK_Lakemont:
1025
1
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
1026
1
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
1027
1
    Builder.defineMacro("__tune_lakemont__");
1028
1
    break;
1029
63
  case CK_K6_2:
1030
1
    Builder.defineMacro("__k6_2__");
1031
1
    Builder.defineMacro("__tune_k6_2__");
1032
1
    LLVM_FALLTHROUGH;
1033
2
  case CK_K6_3:
1034
2
    if (CPU != CK_K6_2) { // In case of fallthrough
1035
1
      // FIXME: GCC may be enabling these in cases where some other k6
1036
1
      // architecture is specified but -m3dnow is explicitly provided. The
1037
1
      // exact semantics need to be determined and emulated here.
1038
1
      Builder.defineMacro("__k6_3__");
1039
1
      Builder.defineMacro("__tune_k6_3__");
1040
1
    }
1041
2
    LLVM_FALLTHROUGH;
1042
3
  case CK_K6:
1043
3
    defineCPUMacros(Builder, "k6");
1044
3
    break;
1045
5
  case CK_Athlon:
1046
5
  case CK_AthlonXP:
1047
5
    defineCPUMacros(Builder, "athlon");
1048
5
    if (SSELevel != NoSSE) {
1049
3
      Builder.defineMacro("__athlon_sse__");
1050
3
      Builder.defineMacro("__tune_athlon_sse__");
1051
3
    }
1052
5
    break;
1053
235
  case CK_K8:
1054
235
  case CK_K8SSE3:
1055
235
  case CK_x86_64:
1056
235
    defineCPUMacros(Builder, "k8");
1057
235
    break;
1058
235
  case CK_AMDFAM10:
1059
4
    defineCPUMacros(Builder, "amdfam10");
1060
4
    break;
1061
235
  case CK_BTVER1:
1062
4
    defineCPUMacros(Builder, "btver1");
1063
4
    break;
1064
235
  case CK_BTVER2:
1065
10
    defineCPUMacros(Builder, "btver2");
1066
10
    break;
1067
235
  case CK_BDVER1:
1068
4
    defineCPUMacros(Builder, "bdver1");
1069
4
    break;
1070
235
  case CK_BDVER2:
1071
4
    defineCPUMacros(Builder, "bdver2");
1072
4
    break;
1073
235
  case CK_BDVER3:
1074
3
    defineCPUMacros(Builder, "bdver3");
1075
3
    break;
1076
235
  case CK_BDVER4:
1077
3
    defineCPUMacros(Builder, "bdver4");
1078
3
    break;
1079
235
  case CK_ZNVER1:
1080
4
    defineCPUMacros(Builder, "znver1");
1081
4
    break;
1082
235
  case CK_ZNVER2:
1083
3
    defineCPUMacros(Builder, "znver2");
1084
3
    break;
1085
235
  case CK_Geode:
1086
1
    defineCPUMacros(Builder, "geode");
1087
1
    break;
1088
53.4k
  }
1089
53.4k
1090
53.4k
  // Target properties.
1091
53.4k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
1092
53.4k
1093
53.4k
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1094
53.4k
  // functions in glibc header files that use FP Stack inline asm which the
1095
53.4k
  // backend can't deal with (PR879).
1096
53.4k
  Builder.defineMacro("__NO_MATH_INLINES");
1097
53.4k
1098
53.4k
  if (HasAES)
1099
85
    Builder.defineMacro("__AES__");
1100
53.4k
1101
53.4k
  if (HasVAES)
1102
11
    Builder.defineMacro("__VAES__");
1103
53.4k
1104
53.4k
  if (HasPCLMUL)
1105
109
    Builder.defineMacro("__PCLMUL__");
1106
53.4k
1107
53.4k
  if (HasVPCLMULQDQ)
1108
11
    Builder.defineMacro("__VPCLMULQDQ__");
1109
53.4k
1110
53.4k
  if (HasLZCNT)
1111
95
    Builder.defineMacro("__LZCNT__");
1112
53.4k
1113
53.4k
  if (HasRDRND)
1114
74
    Builder.defineMacro("__RDRND__");
1115
53.4k
1116
53.4k
  if (HasFSGSBASE)
1117
77
    Builder.defineMacro("__FSGSBASE__");
1118
53.4k
1119
53.4k
  if (HasBMI)
1120
83
    Builder.defineMacro("__BMI__");
1121
53.4k
1122
53.4k
  if (HasBMI2)
1123
67
    Builder.defineMacro("__BMI2__");
1124
53.4k
1125
53.4k
  if (HasPOPCNT)
1126
266
    Builder.defineMacro("__POPCNT__");
1127
53.4k
1128
53.4k
  if (HasRTM)
1129
1
    Builder.defineMacro("__RTM__");
1130
53.4k
1131
53.4k
  if (HasPRFCHW)
1132
133
    Builder.defineMacro("__PRFCHW__");
1133
53.4k
1134
53.4k
  if (HasRDSEED)
1135
64
    Builder.defineMacro("__RDSEED__");
1136
53.4k
1137
53.4k
  if (HasADX)
1138
58
    Builder.defineMacro("__ADX__");
1139
53.4k
1140
53.4k
  if (HasTBM)
1141
11
    Builder.defineMacro("__TBM__");
1142
53.4k
1143
53.4k
  if (HasLWP)
1144
15
    Builder.defineMacro("__LWP__");
1145
53.4k
1146
53.4k
  if (HasMWAITX)
1147
13
    Builder.defineMacro("__MWAITX__");
1148
53.4k
1149
53.4k
  if (HasMOVBE)
1150
131
    Builder.defineMacro("__MOVBE__");
1151
53.4k
1152
53.4k
  switch (XOPLevel) {
1153
18
  case XOP:
1154
18
    Builder.defineMacro("__XOP__");
1155
18
    LLVM_FALLTHROUGH;
1156
19
  case FMA4:
1157
19
    Builder.defineMacro("__FMA4__");
1158
19
    LLVM_FALLTHROUGH;
1159
44
  case SSE4A:
1160
44
    Builder.defineMacro("__SSE4A__");
1161
44
    LLVM_FALLTHROUGH;
1162
53.4k
  case NoXOP:
1163
53.4k
    break;
1164
53.4k
  }
1165
53.4k
1166
53.4k
  if (HasFMA)
1167
157
    Builder.defineMacro("__FMA__");
1168
53.4k
1169
53.4k
  if (HasF16C)
1170
167
    Builder.defineMacro("__F16C__");
1171
53.4k
1172
53.4k
  if (HasGFNI)
1173
14
    Builder.defineMacro("__GFNI__");
1174
53.4k
1175
53.4k
  if (HasAVX512CD)
1176
43
    Builder.defineMacro("__AVX512CD__");
1177
53.4k
  if (HasAVX512VPOPCNTDQ)
1178
13
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
1179
53.4k
  if (HasAVX512VNNI)
1180
15
    Builder.defineMacro("__AVX512VNNI__");
1181
53.4k
  if (HasAVX512BF16)
1182
6
    Builder.defineMacro("__AVX512BF16__");
1183
53.4k
  if (HasAVX512ER)
1184
12
    Builder.defineMacro("__AVX512ER__");
1185
53.4k
  if (HasAVX512PF)
1186
11
    Builder.defineMacro("__AVX512PF__");
1187
53.4k
  if (HasAVX512DQ)
1188
34
    Builder.defineMacro("__AVX512DQ__");
1189
53.4k
  if (HasAVX512BITALG)
1190
11
    Builder.defineMacro("__AVX512BITALG__");
1191
53.4k
  if (HasAVX512BW)
1192
50
    Builder.defineMacro("__AVX512BW__");
1193
53.4k
  if (HasAVX512VL)
1194
48
    Builder.defineMacro("__AVX512VL__");
1195
53.4k
  if (HasAVX512VBMI)
1196
14
    Builder.defineMacro("__AVX512VBMI__");
1197
53.4k
  if (HasAVX512VBMI2)
1198
11
    Builder.defineMacro("__AVX512VBMI2__");
1199
53.4k
  if (HasAVX512IFMA)
1200
14
    Builder.defineMacro("__AVX512IFMA__");
1201
53.4k
  if (HasAVX512VP2INTERSECT)
1202
7
    Builder.defineMacro("__AVX512VP2INTERSECT__");
1203
53.4k
  if (HasSHA)
1204
25
    Builder.defineMacro("__SHA__");
1205
53.4k
1206
53.4k
  if (HasFXSR)
1207
20.0k
    Builder.defineMacro("__FXSR__");
1208
53.4k
  if (HasXSAVE)
1209
260
    Builder.defineMacro("__XSAVE__");
1210
53.4k
  if (HasXSAVEOPT)
1211
100
    Builder.defineMacro("__XSAVEOPT__");
1212
53.4k
  if (HasXSAVEC)
1213
56
    Builder.defineMacro("__XSAVEC__");
1214
53.4k
  if (HasXSAVES)
1215
56
    Builder.defineMacro("__XSAVES__");
1216
53.4k
  if (HasPKU)
1217
32
    Builder.defineMacro("__PKU__");
1218
53.4k
  if (HasCLFLUSHOPT)
1219
50
    Builder.defineMacro("__CLFLUSHOPT__");
1220
53.4k
  if (HasCLWB)
1221
32
    Builder.defineMacro("__CLWB__");
1222
53.4k
  if (HasWBNOINVD)
1223
10
    Builder.defineMacro("__WBNOINVD__");
1224
53.4k
  if (HasSHSTK)
1225
8
    Builder.defineMacro("__SHSTK__");
1226
53.4k
  if (HasSGX)
1227
21
    Builder.defineMacro("__SGX__");
1228
53.4k
  if (HasPREFETCHWT1)
1229
10
    Builder.defineMacro("__PREFETCHWT1__");
1230
53.4k
  if (HasCLZERO)
1231
11
    Builder.defineMacro("__CLZERO__");
1232
53.4k
  if (HasRDPID)
1233
17
    Builder.defineMacro("__RDPID__");
1234
53.4k
  if (HasCLDEMOTE)
1235
7
    Builder.defineMacro("__CLDEMOTE__");
1236
53.4k
  if (HasWAITPKG)
1237
4
    Builder.defineMacro("__WAITPKG__");
1238
53.4k
  if (HasMOVDIRI)
1239
9
    Builder.defineMacro("__MOVDIRI__");
1240
53.4k
  if (HasMOVDIR64B)
1241
9
    Builder.defineMacro("__MOVDIR64B__");
1242
53.4k
  if (HasPCONFIG)
1243
5
    Builder.defineMacro("__PCONFIG__");
1244
53.4k
  if (HasPTWRITE)
1245
6
    Builder.defineMacro("__PTWRITE__");
1246
53.4k
  if (HasINVPCID)
1247
47
    Builder.defineMacro("__INVPCID__");
1248
53.4k
  if (HasENQCMD)
1249
3
    Builder.defineMacro("__ENQCMD__");
1250
53.4k
1251
53.4k
  // Each case falls through to the previous one here.
1252
53.4k
  switch (SSELevel) {
1253
120
  case AVX512F:
1254
120
    Builder.defineMacro("__AVX512F__");
1255
120
    LLVM_FALLTHROUGH;
1256
148
  case AVX2:
1257
148
    Builder.defineMacro("__AVX2__");
1258
148
    LLVM_FALLTHROUGH;
1259
230
  case AVX:
1260
230
    Builder.defineMacro("__AVX__");
1261
230
    LLVM_FALLTHROUGH;
1262
256
  case SSE42:
1263
256
    Builder.defineMacro("__SSE4_2__");
1264
256
    LLVM_FALLTHROUGH;
1265
17.5k
  case SSE41:
1266
17.5k
    Builder.defineMacro("__SSE4_1__");
1267
17.5k
    LLVM_FALLTHROUGH;
1268
17.7k
  case SSSE3:
1269
17.7k
    Builder.defineMacro("__SSSE3__");
1270
17.7k
    LLVM_FALLTHROUGH;
1271
17.7k
  case SSE3:
1272
17.7k
    Builder.defineMacro("__SSE3__");
1273
17.7k
    LLVM_FALLTHROUGH;
1274
49.7k
  case SSE2:
1275
49.7k
    Builder.defineMacro("__SSE2__");
1276
49.7k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1277
49.7k
    LLVM_FALLTHROUGH;
1278
49.7k
  case SSE1:
1279
49.7k
    Builder.defineMacro("__SSE__");
1280
49.7k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1281
49.7k
    LLVM_FALLTHROUGH;
1282
53.4k
  case NoSSE:
1283
53.4k
    break;
1284
53.4k
  }
1285
53.4k
1286
53.4k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x863.10k
) {
1287
308
    switch (SSELevel) {
1288
46
    case AVX512F:
1289
46
    case AVX2:
1290
46
    case AVX:
1291
46
    case SSE42:
1292
46
    case SSE41:
1293
46
    case SSSE3:
1294
46
    case SSE3:
1295
46
    case SSE2:
1296
46
      Builder.defineMacro("_M_IX86_FP", Twine(2));
1297
46
      break;
1298
46
    case SSE1:
1299
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
1300
2
      break;
1301
260
    default:
1302
260
      Builder.defineMacro("_M_IX86_FP", Twine(0));
1303
260
      break;
1304
53.4k
    }
1305
53.4k
  }
1306
53.4k
1307
53.4k
  // Each case falls through to the previous one here.
1308
53.4k
  switch (MMX3DNowLevel) {
1309
33
  case AMD3DNowAthlon:
1310
33
    Builder.defineMacro("__3dNOW_A__");
1311
33
    LLVM_FALLTHROUGH;
1312
39
  case AMD3DNow:
1313
39
    Builder.defineMacro("__3dNOW__");
1314
39
    LLVM_FALLTHROUGH;
1315
49.7k
  case MMX:
1316
49.7k
    Builder.defineMacro("__MMX__");
1317
49.7k
    LLVM_FALLTHROUGH;
1318
53.4k
  case NoMMX3DNow:
1319
53.4k
    break;
1320
53.4k
  }
1321
53.4k
1322
53.4k
  if (CPU >= CK_i486 || 
CPU == CK_Generic33.3k
) {
1323
53.3k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1324
53.3k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1325
53.3k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1326
53.3k
  }
1327
53.4k
  if (HasCX8)
1328
53.3k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1329
53.4k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6417.6k
)
1330
17.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1331
53.4k
1332
53.4k
  if (HasFloat128)
1333
1.97k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1334
53.4k
}
1335
1336
1.17M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1337
1.17M
  return llvm::StringSwitch<bool>(Name)
1338
1.17M
      .Case("3dnow", true)
1339
1.17M
      .Case("3dnowa", true)
1340
1.17M
      .Case("adx", true)
1341
1.17M
      .Case("aes", true)
1342
1.17M
      .Case("avx", true)
1343
1.17M
      .Case("avx2", true)
1344
1.17M
      .Case("avx512f", true)
1345
1.17M
      .Case("avx512cd", true)
1346
1.17M
      .Case("avx512vpopcntdq", true)
1347
1.17M
      .Case("avx512vnni", true)
1348
1.17M
      .Case("avx512bf16", true)
1349
1.17M
      .Case("avx512er", true)
1350
1.17M
      .Case("avx512pf", true)
1351
1.17M
      .Case("avx512dq", true)
1352
1.17M
      .Case("avx512bitalg", true)
1353
1.17M
      .Case("avx512bw", true)
1354
1.17M
      .Case("avx512vl", true)
1355
1.17M
      .Case("avx512vbmi", true)
1356
1.17M
      .Case("avx512vbmi2", true)
1357
1.17M
      .Case("avx512ifma", true)
1358
1.17M
      .Case("avx512vp2intersect", true)
1359
1.17M
      .Case("bmi", true)
1360
1.17M
      .Case("bmi2", true)
1361
1.17M
      .Case("cldemote", true)
1362
1.17M
      .Case("clflushopt", true)
1363
1.17M
      .Case("clwb", true)
1364
1.17M
      .Case("clzero", true)
1365
1.17M
      .Case("cx16", true)
1366
1.17M
      .Case("enqcmd", true)
1367
1.17M
      .Case("f16c", true)
1368
1.17M
      .Case("fma", true)
1369
1.17M
      .Case("fma4", true)
1370
1.17M
      .Case("fsgsbase", true)
1371
1.17M
      .Case("fxsr", true)
1372
1.17M
      .Case("gfni", true)
1373
1.17M
      .Case("invpcid", true)
1374
1.17M
      .Case("lwp", true)
1375
1.17M
      .Case("lzcnt", true)
1376
1.17M
      .Case("mmx", true)
1377
1.17M
      .Case("movbe", true)
1378
1.17M
      .Case("movdiri", true)
1379
1.17M
      .Case("movdir64b", true)
1380
1.17M
      .Case("mwaitx", true)
1381
1.17M
      .Case("pclmul", true)
1382
1.17M
      .Case("pconfig", true)
1383
1.17M
      .Case("pku", true)
1384
1.17M
      .Case("popcnt", true)
1385
1.17M
      .Case("prefetchwt1", true)
1386
1.17M
      .Case("prfchw", true)
1387
1.17M
      .Case("ptwrite", true)
1388
1.17M
      .Case("rdpid", true)
1389
1.17M
      .Case("rdrnd", true)
1390
1.17M
      .Case("rdseed", true)
1391
1.17M
      .Case("rtm", true)
1392
1.17M
      .Case("sahf", true)
1393
1.17M
      .Case("sgx", true)
1394
1.17M
      .Case("sha", true)
1395
1.17M
      .Case("shstk", true)
1396
1.17M
      .Case("sse", true)
1397
1.17M
      .Case("sse2", true)
1398
1.17M
      .Case("sse3", true)
1399
1.17M
      .Case("ssse3", true)
1400
1.17M
      .Case("sse4", true)
1401
1.17M
      .Case("sse4.1", true)
1402
1.17M
      .Case("sse4.2", true)
1403
1.17M
      .Case("sse4a", true)
1404
1.17M
      .Case("tbm", true)
1405
1.17M
      .Case("vaes", true)
1406
1.17M
      .Case("vpclmulqdq", true)
1407
1.17M
      .Case("wbnoinvd", true)
1408
1.17M
      .Case("waitpkg", true)
1409
1.17M
      .Case("x87", true)
1410
1.17M
      .Case("xop", true)
1411
1.17M
      .Case("xsave", true)
1412
1.17M
      .Case("xsavec", true)
1413
1.17M
      .Case("xsaves", true)
1414
1.17M
      .Case("xsaveopt", true)
1415
1.17M
      .Default(false);
1416
1.17M
}
1417
1418
359k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
1419
359k
  return llvm::StringSwitch<bool>(Feature)
1420
359k
      .Case("adx", HasADX)
1421
359k
      .Case("aes", HasAES)
1422
359k
      .Case("avx", SSELevel >= AVX)
1423
359k
      .Case("avx2", SSELevel >= AVX2)
1424
359k
      .Case("avx512f", SSELevel >= AVX512F)
1425
359k
      .Case("avx512cd", HasAVX512CD)
1426
359k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1427
359k
      .Case("avx512vnni", HasAVX512VNNI)
1428
359k
      .Case("avx512bf16", HasAVX512BF16)
1429
359k
      .Case("avx512er", HasAVX512ER)
1430
359k
      .Case("avx512pf", HasAVX512PF)
1431
359k
      .Case("avx512dq", HasAVX512DQ)
1432
359k
      .Case("avx512bitalg", HasAVX512BITALG)
1433
359k
      .Case("avx512bw", HasAVX512BW)
1434
359k
      .Case("avx512vl", HasAVX512VL)
1435
359k
      .Case("avx512vbmi", HasAVX512VBMI)
1436
359k
      .Case("avx512vbmi2", HasAVX512VBMI2)
1437
359k
      .Case("avx512ifma", HasAVX512IFMA)
1438
359k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1439
359k
      .Case("bmi", HasBMI)
1440
359k
      .Case("bmi2", HasBMI2)
1441
359k
      .Case("cldemote", HasCLDEMOTE)
1442
359k
      .Case("clflushopt", HasCLFLUSHOPT)
1443
359k
      .Case("clwb", HasCLWB)
1444
359k
      .Case("clzero", HasCLZERO)
1445
359k
      .Case("cx8", HasCX8)
1446
359k
      .Case("cx16", HasCX16)
1447
359k
      .Case("enqcmd", HasENQCMD)
1448
359k
      .Case("f16c", HasF16C)
1449
359k
      .Case("fma", HasFMA)
1450
359k
      .Case("fma4", XOPLevel >= FMA4)
1451
359k
      .Case("fsgsbase", HasFSGSBASE)
1452
359k
      .Case("fxsr", HasFXSR)
1453
359k
      .Case("gfni", HasGFNI)
1454
359k
      .Case("invpcid", HasINVPCID)
1455
359k
      .Case("lwp", HasLWP)
1456
359k
      .Case("lzcnt", HasLZCNT)
1457
359k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1458
359k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1459
359k
      .Case("mmx", MMX3DNowLevel >= MMX)
1460
359k
      .Case("movbe", HasMOVBE)
1461
359k
      .Case("movdiri", HasMOVDIRI)
1462
359k
      .Case("movdir64b", HasMOVDIR64B)
1463
359k
      .Case("mwaitx", HasMWAITX)
1464
359k
      .Case("pclmul", HasPCLMUL)
1465
359k
      .Case("pconfig", HasPCONFIG)
1466
359k
      .Case("pku", HasPKU)
1467
359k
      .Case("popcnt", HasPOPCNT)
1468
359k
      .Case("prefetchwt1", HasPREFETCHWT1)
1469
359k
      .Case("prfchw", HasPRFCHW)
1470
359k
      .Case("ptwrite", HasPTWRITE)
1471
359k
      .Case("rdpid", HasRDPID)
1472
359k
      .Case("rdrnd", HasRDRND)
1473
359k
      .Case("rdseed", HasRDSEED)
1474
359k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1475
359k
      .Case("rtm", HasRTM)
1476
359k
      .Case("sahf", HasLAHFSAHF)
1477
359k
      .Case("sgx", HasSGX)
1478
359k
      .Case("sha", HasSHA)
1479
359k
      .Case("shstk", HasSHSTK)
1480
359k
      .Case("sse", SSELevel >= SSE1)
1481
359k
      .Case("sse2", SSELevel >= SSE2)
1482
359k
      .Case("sse3", SSELevel >= SSE3)
1483
359k
      .Case("ssse3", SSELevel >= SSSE3)
1484
359k
      .Case("sse4.1", SSELevel >= SSE41)
1485
359k
      .Case("sse4.2", SSELevel >= SSE42)
1486
359k
      .Case("sse4a", XOPLevel >= SSE4A)
1487
359k
      .Case("tbm", HasTBM)
1488
359k
      .Case("vaes", HasVAES)
1489
359k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1490
359k
      .Case("wbnoinvd", HasWBNOINVD)
1491
359k
      .Case("waitpkg", HasWAITPKG)
1492
359k
      .Case("x86", true)
1493
359k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1494
359k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1495
359k
      .Case("xop", XOPLevel >= XOP)
1496
359k
      .Case("xsave", HasXSAVE)
1497
359k
      .Case("xsavec", HasXSAVEC)
1498
359k
      .Case("xsaves", HasXSAVES)
1499
359k
      .Case("xsaveopt", HasXSAVEOPT)
1500
359k
      .Default(false);
1501
359k
}
1502
1503
// We can't use a generic validation scheme for the features accepted here
1504
// versus subtarget features accepted in the target attribute because the
1505
// bitfield structure that's initialized in the runtime only supports the
1506
// below currently rather than the full range of subtarget features. (See
1507
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1508
710
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1509
710
  return llvm::StringSwitch<bool>(FeatureStr)
1510
26.2k
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1511
710
#include "llvm/Support/X86TargetParser.def"
1512
710
      .Default(false);
1513
710
}
1514
1515
139
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1516
139
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1517
5.14k
#define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1518
139
#include "llvm/Support/X86TargetParser.def"
1519
139
      ;
1520
139
  // Note, this function should only be used after ensuring the value is
1521
139
  // correct, so it asserts if the value is out of range.
1522
139
}
1523
1524
301
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1525
301
  enum class FeatPriority {
1526
301
#define FEATURE(FEAT) FEAT,
1527
301
#include "clang/Basic/X86Target.def"
1528
301
  };
1529
301
  switch (Feat) {
1530
0
#define FEATURE(FEAT)                                                          \
1531
301
  case llvm::X86::FEAT:                                                        \
1532
301
    return static_cast<unsigned>(FeatPriority::FEAT);
1533
0
#include "clang/Basic/X86Target.def"
1534
0
  default:
1535
0
    llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1536
301
  }
1537
301
}
1538
1539
301
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1540
301
  // Valid CPUs have a 'key feature' that compares just better than its key
1541
301
  // feature.
1542
301
  CPUKind Kind = getCPUKind(Name);
1543
301
  if (Kind != CK_Generic) {
1544
162
    switch (Kind) {
1545
0
    default:
1546
0
      llvm_unreachable(
1547
0
          "CPU Type without a key feature used in 'target' attribute");
1548
0
#define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT)                              \
1549
162
  case CK_##ENUM:                                                              \
1550
162
    return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1551
0
#include "clang/Basic/X86Target.def"
1552
162
    }
1553
162
  }
1554
301
1555
301
  // Now we know we have a feature, so get its priority and shift it a few so
1556
301
  // that we have sufficient room for the CPUs (above).
1557
301
  
return getFeaturePriority(getFeature(Name)) << 1139
;
1558
301
}
1559
1560
162
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1561
162
  return llvm::StringSwitch<bool>(Name)
1562
4.53k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1563
972
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1564
162
#include "clang/Basic/X86Target.def"
1565
162
      .Default(false);
1566
162
}
1567
1568
350
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1569
350
  return llvm::StringSwitch<StringRef>(Name)
1570
2.10k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1571
350
#include "clang/Basic/X86Target.def"
1572
350
      .Default(Name);
1573
350
}
1574
1575
250
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1576
250
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1577
7.00k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1578
250
#include "clang/Basic/X86Target.def"
1579
250
      .Default(0);
1580
250
}
1581
1582
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1583
100
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1584
100
  StringRef WholeList =
1585
100
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1586
2.80k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1587
100
#include "clang/Basic/X86Target.def"
1588
100
          .Default("");
1589
100
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1590
100
}
1591
1592
// We can't use a generic validation scheme for the cpus accepted here
1593
// versus subtarget cpus accepted in the target attribute because the
1594
// variables intitialized by the runtime only support the below currently
1595
// rather than the full range of cpus.
1596
150
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1597
150
  return llvm::StringSwitch<bool>(FeatureStr)
1598
300
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1599
150
#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS)             \
1600
600
  .Cases(STR, ALIAS, true)
1601
1.50k
#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1602
3.15k
#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1603
150
#include "llvm/Support/X86TargetParser.def"
1604
150
      .Default(false);
1605
150
}
1606
1607
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1608
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1609
87
                .Case("@cca", 4)
1610
87
                .Case("@ccae", 5)
1611
87
                .Case("@ccb", 4)
1612
87
                .Case("@ccbe", 5)
1613
87
                .Case("@ccc", 4)
1614
87
                .Case("@cce", 4)
1615
87
                .Case("@ccz", 4)
1616
87
                .Case("@ccg", 4)
1617
87
                .Case("@ccge", 5)
1618
87
                .Case("@ccl", 4)
1619
87
                .Case("@ccle", 5)
1620
87
                .Case("@ccna", 5)
1621
87
                .Case("@ccnae", 6)
1622
87
                .Case("@ccnb", 5)
1623
87
                .Case("@ccnbe", 6)
1624
87
                .Case("@ccnc", 5)
1625
87
                .Case("@ccne", 5)
1626
87
                .Case("@ccnz", 5)
1627
87
                .Case("@ccng", 5)
1628
87
                .Case("@ccnge", 6)
1629
87
                .Case("@ccnl", 5)
1630
87
                .Case("@ccnle", 6)
1631
87
                .Case("@ccno", 5)
1632
87
                .Case("@ccnp", 5)
1633
87
                .Case("@ccns", 5)
1634
87
                .Case("@cco", 4)
1635
87
                .Case("@ccp", 4)
1636
87
                .Case("@ccs", 4)
1637
87
                .Default(0);
1638
87
  return RV;
1639
87
}
1640
1641
bool X86TargetInfo::validateAsmConstraint(
1642
8.48k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1643
8.48k
  switch (*Name) {
1644
1
  default:
1645
1
    return false;
1646
0
  // Constant constraints.
1647
17
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1648
17
            // instructions.
1649
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1650
17
            // x86_64 instructions.
1651
17
  case 's':
1652
17
    Info.setRequiresImmediate();
1653
17
    return true;
1654
28
  case 'I':
1655
28
    Info.setRequiresImmediate(0, 31);
1656
28
    return true;
1657
17
  case 'J':
1658
14
    Info.setRequiresImmediate(0, 63);
1659
14
    return true;
1660
17
  case 'K':
1661
14
    Info.setRequiresImmediate(-128, 127);
1662
14
    return true;
1663
30
  case 'L':
1664
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1665
30
    return true;
1666
17
  case 'M':
1667
14
    Info.setRequiresImmediate(0, 3);
1668
14
    return true;
1669
17
  case 'N':
1670
16
    Info.setRequiresImmediate(0, 255);
1671
16
    return true;
1672
17
  case 'O':
1673
6
    Info.setRequiresImmediate(0, 127);
1674
6
    return true;
1675
17
  // Register constraints.
1676
40
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1677
40
    // Shift the pointer to the second character of the constraint.
1678
40
    Name++;
1679
40
    switch (*Name) {
1680
0
    default:
1681
0
      return false;
1682
40
    case 'z':
1683
40
    case '0': // First SSE register.
1684
40
    case '2':
1685
40
    case 't': // Any SSE register, when SSE2 is enabled.
1686
40
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1687
40
    case 'm': // Any MMX register, when inter-unit moves enabled.
1688
40
    case 'k': // AVX512 arch mask registers: k1-k7.
1689
40
      Info.setAllowsRegister();
1690
40
      return true;
1691
0
    }
1692
3
  case 'f': // Any x87 floating point stack register.
1693
3
    // Constraint 'f' cannot be used for output operands.
1694
3
    if (Info.ConstraintStr[0] == '=')
1695
1
      return false;
1696
2
    Info.setAllowsRegister();
1697
2
    return true;
1698
8.22k
  case 'a': // eax.
1699
8.22k
  case 'b': // ebx.
1700
8.22k
  case 'c': // ecx.
1701
8.22k
  case 'd': // edx.
1702
8.22k
  case 'S': // esi.
1703
8.22k
  case 'D': // edi.
1704
8.22k
  case 'A': // edx:eax.
1705
8.22k
  case 't': // Top of floating point stack.
1706
8.22k
  case 'u': // Second from top of floating point stack.
1707
8.22k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1708
8.22k
  case 'y': // Any MMX register.
1709
8.22k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1710
8.22k
  case 'x': // Any SSE register.
1711
8.22k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1712
8.22k
            // for intermideate k reg operations).
1713
8.22k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1714
8.22k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1715
8.22k
  case 'l': // "Index" registers: any general register that can be used as an
1716
8.22k
            // index in a base+index memory access.
1717
8.22k
    Info.setAllowsRegister();
1718
8.22k
    return true;
1719
8.22k
  // Floating point constant constraints.
1720
8.22k
  case 'C': // SSE floating point constant.
1721
16
  case 'G': // x87 floating point constant.
1722
16
    return true;
1723
58
  case '@':
1724
58
    // CC condition changes.
1725
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1726
58
      Name += Len - 1;
1727
58
      Info.setAllowsRegister();
1728
58
      return true;
1729
58
    }
1730
0
    return false;
1731
8.48k
  }
1732
8.48k
}
1733
1734
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1735
                                       StringRef Constraint,
1736
4.73k
                                       unsigned Size) const {
1737
4.73k
  // Strip off constraint modifiers.
1738
9.48k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'5.17k
||
Constraint[0] == '&'4.74k
)
1739
4.74k
    Constraint = Constraint.substr(1);
1740
4.73k
1741
4.73k
  return validateOperandSize(FeatureMap, Constraint, Size);
1742
4.73k
}
1743
1744
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1745
                                      StringRef Constraint,
1746
4.52k
                                      unsigned Size) const {
1747
4.52k
  return validateOperandSize(FeatureMap, Constraint, Size);
1748
4.52k
}
1749
1750
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1751
                                        StringRef Constraint,
1752
7.77k
                                        unsigned Size) const {
1753
7.77k
  switch (Constraint[0]) {
1754
7.59k
  default:
1755
7.59k
    break;
1756
30
  case 'k':
1757
30
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1758
30
  case 'y':
1759
30
    return Size <= 64;
1760
30
  case 'f':
1761
18
  case 't':
1762
18
  case 'u':
1763
18
    return Size <= 128;
1764
20
  case 'Y':
1765
20
    // 'Y' is the first character for several 2-character constraints.
1766
20
    switch (Constraint[1]) {
1767
0
    default:
1768
0
      return false;
1769
5
    case 'm':
1770
5
      // 'Ym' is synonymous with 'y'.
1771
5
    case 'k':
1772
5
      return Size <= 64;
1773
5
    case 'z':
1774
2
    case '0':
1775
2
      // XMM0
1776
2
      if (FeatureMap.lookup("sse"))
1777
2
        return Size <= 128U;
1778
0
      return false;
1779
13
    case 'i':
1780
13
    case 't':
1781
13
    case '2':
1782
13
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1783
13
      if (SSELevel < SSE2)
1784
0
        return false;
1785
13
      break;
1786
13
    }
1787
13
    LLVM_FALLTHROUGH;
1788
120
  case 'v':
1789
120
  case 'x':
1790
120
    if (FeatureMap.lookup("avx512f"))
1791
59
      // 512-bit zmm registers can be used if target supports AVX512F.
1792
59
      return Size <= 512U;
1793
61
    else if (FeatureMap.lookup("avx"))
1794
27
      // 256-bit ymm registers can be used if target supports AVX.
1795
27
      return Size <= 256U;
1796
34
    return Size <= 128U;
1797
7.59k
1798
7.59k
  }
1799
7.59k
1800
7.59k
  return true;
1801
7.59k
}
1802
1803
1.47k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1804
1.47k
  switch (*Constraint) {
1805
29
  case '@':
1806
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1807
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1808
29
      Constraint += Len - 1;
1809
29
      return Converted;
1810
29
    }
1811
0
    return std::string(1, *Constraint);
1812
78
  case 'a':
1813
78
    return std::string("{ax}");
1814
40
  case 'b':
1815
40
    return std::string("{bx}");
1816
73
  case 'c':
1817
73
    return std::string("{cx}");
1818
40
  case 'd':
1819
40
    return std::string("{dx}");
1820
31
  case 'S':
1821
31
    return std::string("{si}");
1822
39
  case 'D':
1823
39
    return std::string("{di}");
1824
4
  case 'p': // address
1825
4
    return std::string("im");
1826
5
  case 't': // top of floating point stack.
1827
5
    return std::string("{st}");
1828
1
  case 'u':                        // second from top of floating point stack.
1829
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1830
20
  case 'Y':
1831
20
    switch (Constraint[1]) {
1832
0
    default:
1833
0
      // Break from inner switch and fall through (copy single char),
1834
0
      // continue parsing after copying the current constraint into
1835
0
      // the return string.
1836
0
      break;
1837
20
    case 'k':
1838
20
    case 'm':
1839
20
    case 'i':
1840
20
    case 't':
1841
20
    case 'z':
1842
20
    case '0':
1843
20
    case '2':
1844
20
      // "^" hints llvm that this is a 2 letter constraint.
1845
20
      // "Constraint++" is used to promote the string iterator
1846
20
      // to the next constraint.
1847
20
      return std::string("^") + std::string(Constraint++, 2);
1848
0
    }
1849
0
    LLVM_FALLTHROUGH;
1850
1.11k
  default:
1851
1.11k
    return std::string(1, *Constraint);
1852
1.47k
  }
1853
1.47k
}
1854
1855
21.1k
bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1856
21.1k
  // Perform any per-CPU checks necessary to determine if this CPU is
1857
21.1k
  // acceptable.
1858
21.1k
  switch (Kind) {
1859
5
  case CK_Generic:
1860
5
    // No processor selected!
1861
5
    return false;
1862
0
#define PROC(ENUM, STRING, IS64BIT)                                            \
1863
21.1k
  case CK_##ENUM:                                                              \
1864
21.1k
    return IS64BIT || 
getTriple().getArch() == llvm::Triple::x862.42k
;
1865
0
#include "clang/Basic/X86Target.def"
1866
21.1k
  }
1867
21.1k
  
llvm_unreachable0
("Unhandled CPU kind");
1868
21.1k
}
1869
1870
31
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1871
31
#define PROC(ENUM, STRING, IS64BIT)                                            \
1872
1.86k
  if (IS64BIT || 
getTriple().getArch() == llvm::Triple::x86744
) \
1873
1.86k
    
Values.emplace_back(STRING)1.14k
;
1874
31
  // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
1875
31
#define PROC_ALIAS(ENUM, ALIAS)                                                \
1876
558
  if (checkCPUKind(CK_##ENUM))                                                      \
1877
558
    
Values.emplace_back(ALIAS)408
;
1878
31
#include "clang/Basic/X86Target.def"
1879
31
}
1880
1881
134k
X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1882
134k
  return llvm::StringSwitch<CPUKind>(CPU)
1883
8.08M
#define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1884
2.42M
#define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1885
134k
#include "clang/Basic/X86Target.def"
1886
134k
      .Default(CK_Generic);
1887
134k
}
1888
1889
3.31k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1890
3.31k
  return llvm::makeArrayRef(GCCRegNames);
1891
3.31k
}
1892
1893
2.74k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1894
2.74k
  return llvm::makeArrayRef(AddlRegNames);
1895
2.74k
}
1896
1897
5.95k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1898
5.95k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1899
5.95k
                                                Builtin::FirstTSBuiltin + 1);
1900
5.95k
}
1901
1902
47.6k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1903
47.6k
  return llvm::makeArrayRef(BuiltinInfoX86,
1904
47.6k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1905
47.6k
}