Coverage Report

Created: 2020-10-24 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/X86TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
    "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
66
};
67
68
const TargetInfo::AddlRegName AddlRegNames[] = {
69
    {{"al", "ah", "eax", "rax"}, 0},
70
    {{"bl", "bh", "ebx", "rbx"}, 3},
71
    {{"cl", "ch", "ecx", "rcx"}, 2},
72
    {{"dl", "dh", "edx", "rdx"}, 1},
73
    {{"esi", "rsi"}, 4},
74
    {{"edi", "rdi"}, 5},
75
    {{"esp", "rsp"}, 7},
76
    {{"ebp", "rbp"}, 6},
77
    {{"r8d", "r8w", "r8b"}, 38},
78
    {{"r9d", "r9w", "r9b"}, 39},
79
    {{"r10d", "r10w", "r10b"}, 40},
80
    {{"r11d", "r11w", "r11b"}, 41},
81
    {{"r12d", "r12w", "r12b"}, 42},
82
    {{"r13d", "r13w", "r13b"}, 43},
83
    {{"r14d", "r14w", "r14b"}, 44},
84
    {{"r15d", "r15w", "r15b"}, 45},
85
};
86
87
} // namespace targets
88
} // namespace clang
89
90
using namespace clang;
91
using namespace clang::targets;
92
93
5
bool X86TargetInfo::setFPMath(StringRef Name) {
94
5
  if (Name == "387") {
95
2
    FPMath = FP_387;
96
2
    return true;
97
2
  }
98
3
  if (Name == "sse") {
99
2
    FPMath = FP_SSE;
100
2
    return true;
101
2
  }
102
1
  return false;
103
1
}
104
105
bool X86TargetInfo::initFeatureMap(
106
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107
127k
    const std::vector<std::string> &FeaturesVec) const {
108
  // FIXME: This *really* should not be here.
109
  // X86_64 always has SSE2.
110
127k
  if (getTriple().getArch() == llvm::Triple::x86_64)
111
113k
    setFeatureEnabled(Features, "sse2", true);
112
113
127k
  using namespace llvm::X86;
114
115
127k
  SmallVector<StringRef, 16> CPUFeatures;
116
127k
  getFeaturesForCPU(CPU, CPUFeatures);
117
127k
  for (auto &F : CPUFeatures)
118
528k
    setFeatureEnabled(Features, F, true);
119
120
127k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
121
0
    return false;
122
123
  // Can't do this earlier because we need to be able to explicitly enable
124
  // or disable these features and the things that they depend upon.
125
126
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
127
127k
  auto I = Features.find("sse4.2");
128
127k
  if (I != Features.end() && 
I->getValue()40.2k
&&
129
40.2k
      llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
130
40.2k
    Features["popcnt"] = true;
131
132
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
133
  // then enable MMX.
134
127k
  I = Features.find("sse");
135
127k
  if (I != Features.end() && 
I->getValue()122k
&&
136
122k
      llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
137
122k
    Features["mmx"] = true;
138
139
  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
140
127k
  I = Features.find("avx");
141
127k
  if (I != Features.end() && 
I->getValue()40.0k
&&
142
39.9k
      llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end())
143
39.9k
    Features["xsave"] = true;
144
145
127k
  return true;
146
127k
}
147
148
void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
149
759k
                                      StringRef Name, bool Enabled) const {
150
759k
  if (Name == "sse4") {
151
    // We can get here via the __target__ attribute since that's not controlled
152
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
153
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
154
    // disabled.
155
4
    if (Enabled)
156
2
      Name = "sse4.2";
157
2
    else
158
2
      Name = "sse4.1";
159
4
  }
160
161
759k
  Features[Name] = Enabled;
162
759k
  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
163
759k
}
164
165
/// handleTargetFeatures - Perform initialization based on the user
166
/// configured set of features.
167
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
168
80.3k
                                         DiagnosticsEngine &Diags) {
169
523k
  for (const auto &Feature : Features) {
170
523k
    if (Feature[0] != '+')
171
932
      continue;
172
173
522k
    if (Feature == "+aes") {
174
90
      HasAES = true;
175
522k
    } else if (Feature == "+vaes") {
176
13
      HasVAES = true;
177
521k
    } else if (Feature == "+pclmul") {
178
115
      HasPCLMUL = true;
179
521k
    } else if (Feature == "+vpclmulqdq") {
180
13
      HasVPCLMULQDQ = true;
181
521k
    } else if (Feature == "+lzcnt") {
182
102
      HasLZCNT = true;
183
521k
    } else if (Feature == "+rdrnd") {
184
81
      HasRDRND = true;
185
521k
    } else if (Feature == "+fsgsbase") {
186
80
      HasFSGSBASE = true;
187
521k
    } else if (Feature == "+bmi") {
188
90
      HasBMI = true;
189
521k
    } else if (Feature == "+bmi2") {
190
72
      HasBMI2 = true;
191
521k
    } else if (Feature == "+popcnt") {
192
296
      HasPOPCNT = true;
193
521k
    } else if (Feature == "+rtm") {
194
1
      HasRTM = true;
195
521k
    } else if (Feature == "+prfchw") {
196
105
      HasPRFCHW = true;
197
521k
    } else if (Feature == "+rdseed") {
198
67
      HasRDSEED = true;
199
520k
    } else if (Feature == "+adx") {
200
61
      HasADX = true;
201
520k
    } else if (Feature == "+tbm") {
202
11
      HasTBM = true;
203
520k
    } else if (Feature == "+lwp") {
204
15
      HasLWP = true;
205
520k
    } else if (Feature == "+fma") {
206
174
      HasFMA = true;
207
520k
    } else if (Feature == "+f16c") {
208
187
      HasF16C = true;
209
520k
    } else if (Feature == "+gfni") {
210
16
      HasGFNI = true;
211
520k
    } else if (Feature == "+avx512cd") {
212
46
      HasAVX512CD = true;
213
520k
    } else if (Feature == "+avx512vpopcntdq") {
214
15
      HasAVX512VPOPCNTDQ = true;
215
520k
    } else if (Feature == "+avx512vnni") {
216
17
      HasAVX512VNNI = true;
217
520k
    } else if (Feature == "+avx512bf16") {
218
8
      HasAVX512BF16 = true;
219
520k
    } else if (Feature == "+avx512er") {
220
12
      HasAVX512ER = true;
221
520k
    } else if (Feature == "+avx512pf") {
222
11
      HasAVX512PF = true;
223
520k
    } else if (Feature == "+avx512dq") {
224
37
      HasAVX512DQ = true;
225
520k
    } else if (Feature == "+avx512bitalg") {
226
13
      HasAVX512BITALG = true;
227
520k
    } else if (Feature == "+avx512bw") {
228
53
      HasAVX512BW = true;
229
520k
    } else if (Feature == "+avx512vl") {
230
55
      HasAVX512VL = true;
231
520k
    } else if (Feature == "+avx512vbmi") {
232
16
      HasAVX512VBMI = true;
233
520k
    } else if (Feature == "+avx512vbmi2") {
234
13
      HasAVX512VBMI2 = true;
235
520k
    } else if (Feature == "+avx512ifma") {
236
16
      HasAVX512IFMA = true;
237
520k
    } else if (Feature == "+avx512vp2intersect") {
238
9
      HasAVX512VP2INTERSECT = true;
239
520k
    } else if (Feature == "+sha") {
240
27
      HasSHA = true;
241
520k
    } else if (Feature == "+shstk") {
242
10
      HasSHSTK = true;
243
520k
    } else if (Feature == "+movbe") {
244
148
      HasMOVBE = true;
245
519k
    } else if (Feature == "+sgx") {
246
23
      HasSGX = true;
247
519k
    } else if (Feature == "+cx8") {
248
80.2k
      HasCX8 = true;
249
439k
    } else if (Feature == "+cx16") {
250
18.6k
      HasCX16 = true;
251
421k
    } else if (Feature == "+fxsr") {
252
35.9k
      HasFXSR = true;
253
385k
    } else if (Feature == "+xsave") {
254
288
      HasXSAVE = true;
255
384k
    } else if (Feature == "+xsaveopt") {
256
108
      HasXSAVEOPT = true;
257
384k
    } else if (Feature == "+xsavec") {
258
58
      HasXSAVEC = true;
259
384k
    } else if (Feature == "+xsaves") {
260
58
      HasXSAVES = true;
261
384k
    } else if (Feature == "+mwaitx") {
262
13
      HasMWAITX = true;
263
384k
    } else if (Feature == "+pku") {
264
34
      HasPKU = true;
265
384k
    } else if (Feature == "+clflushopt") {
266
52
      HasCLFLUSHOPT = true;
267
384k
    } else if (Feature == "+clwb") {
268
36
      HasCLWB = true;
269
384k
    } else if (Feature == "+wbnoinvd") {
270
12
      HasWBNOINVD = true;
271
384k
    } else if (Feature == "+prefetchwt1") {
272
11
      HasPREFETCHWT1 = true;
273
384k
    } else if (Feature == "+clzero") {
274
11
      HasCLZERO = true;
275
384k
    } else if (Feature == "+cldemote") {
276
7
      HasCLDEMOTE = true;
277
384k
    } else if (Feature == "+rdpid") {
278
19
      HasRDPID = true;
279
384k
    } else if (Feature == "+kl") {
280
8
      HasKL = true;
281
384k
    } else if (Feature == "+widekl") {
282
7
      HasWIDEKL = true;
283
384k
    } else if (Feature == "+retpoline-external-thunk") {
284
0
      HasRetpolineExternalThunk = true;
285
384k
    } else if (Feature == "+sahf") {
286
18.6k
      HasLAHFSAHF = true;
287
365k
    } else if (Feature == "+waitpkg") {
288
4
      HasWAITPKG = true;
289
365k
    } else if (Feature == "+movdiri") {
290
9
      HasMOVDIRI = true;
291
365k
    } else if (Feature == "+movdir64b") {
292
9
      HasMOVDIR64B = true;
293
365k
    } else if (Feature == "+pconfig") {
294
7
      HasPCONFIG = true;
295
365k
    } else if (Feature == "+ptwrite") {
296
8
      HasPTWRITE = true;
297
365k
    } else if (Feature == "+invpcid") {
298
60
      HasINVPCID = true;
299
365k
    } else if (Feature == "+enqcmd") {
300
5
      HasENQCMD = true;
301
365k
    } else if (Feature == "+hreset") {
302
3
      HasHRESET = true;
303
365k
    } else if (Feature == "+amx-bf16") {
304
6
      HasAMXBF16 = true;
305
365k
    } else if (Feature == "+amx-int8") {
306
6
      HasAMXINT8 = true;
307
365k
    } else if (Feature == "+amx-tile") {
308
8
      HasAMXTILE = true;
309
365k
    } else if (Feature == "+serialize") {
310
5
      HasSERIALIZE = true;
311
365k
    } else if (Feature == "+tsxldtrk") {
312
5
      HasTSXLDTRK = true;
313
365k
    } else if (Feature == "+uintr") {
314
4
      HasUINTR = true;
315
4
    }
316
317
522k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
318
522k
                           .Case("+avx512f", AVX512F)
319
522k
                           .Case("+avx2", AVX2)
320
522k
                           .Case("+avx", AVX)
321
522k
                           .Case("+sse4.2", SSE42)
322
522k
                           .Case("+sse4.1", SSE41)
323
522k
                           .Case("+ssse3", SSSE3)
324
522k
                           .Case("+sse3", SSE3)
325
522k
                           .Case("+sse2", SSE2)
326
522k
                           .Case("+sse", SSE1)
327
522k
                           .Default(NoSSE);
328
522k
    SSELevel = std::max(SSELevel, Level);
329
330
522k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
331
522k
                                      .Case("+3dnowa", AMD3DNowAthlon)
332
522k
                                      .Case("+3dnow", AMD3DNow)
333
522k
                                      .Case("+mmx", MMX)
334
522k
                                      .Default(NoMMX3DNow);
335
522k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
336
337
522k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
338
522k
                         .Case("+xop", XOP)
339
522k
                         .Case("+fma4", FMA4)
340
522k
                         .Case("+sse4a", SSE4A)
341
522k
                         .Default(NoXOP);
342
522k
    XOPLevel = std::max(XOPLevel, XLevel);
343
522k
  }
344
345
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
346
  // matches the selected sse level.
347
80.3k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
348
80.3k
      (FPMath == FP_387 && 
SSELevel >= SSE12
)) {
349
2
    Diags.Report(diag::err_target_unsupported_fpmath)
350
1
        << (FPMath == FP_SSE ? "sse" : "387");
351
2
    return false;
352
2
  }
353
354
80.3k
  SimdDefaultAlign =
355
80.1k
      hasFeature("avx512f") ? 
512136
: hasFeature("avx") ?
256118
:
12880.0k
;
356
80.3k
  return true;
357
80.3k
}
358
359
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
360
/// definitions for this particular subtarget.
361
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
362
72.7k
                                     MacroBuilder &Builder) const {
363
  // Inline assembly supports X86 flag outputs.
364
72.7k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
365
366
72.7k
  std::string CodeModel = getTargetOpts().CodeModel;
367
72.7k
  if (CodeModel == "default")
368
60.2k
    CodeModel = "small";
369
72.7k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
370
371
  // Target identification.
372
72.7k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
373
59.3k
    Builder.defineMacro("__amd64__");
374
59.3k
    Builder.defineMacro("__amd64");
375
59.3k
    Builder.defineMacro("__x86_64");
376
59.3k
    Builder.defineMacro("__x86_64__");
377
59.3k
    if (getTriple().getArchName() == "x86_64h") {
378
2
      Builder.defineMacro("__x86_64h");
379
2
      Builder.defineMacro("__x86_64h__");
380
2
    }
381
13.3k
  } else {
382
13.3k
    DefineStd(Builder, "i386", Opts);
383
13.3k
  }
384
385
72.7k
  Builder.defineMacro("__SEG_GS");
386
72.7k
  Builder.defineMacro("__SEG_FS");
387
72.7k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
388
72.7k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
389
390
  // Subtarget options.
391
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
392
  // truly should be based on -mtune options.
393
72.7k
  using namespace llvm::X86;
394
72.7k
  switch (CPU) {
395
36.7k
  case CK_None:
396
36.7k
    break;
397
29
  case CK_i386:
398
    // The rest are coming from the i386 define above.
399
29
    Builder.defineMacro("__tune_i386__");
400
29
    break;
401
8
  case CK_i486:
402
8
  case CK_WinChipC6:
403
8
  case CK_WinChip2:
404
8
  case CK_C3:
405
8
    defineCPUMacros(Builder, "i486");
406
8
    break;
407
1
  case CK_PentiumMMX:
408
1
    Builder.defineMacro("__pentium_mmx__");
409
1
    Builder.defineMacro("__tune_pentium_mmx__");
410
1
    LLVM_FALLTHROUGH;
411
7
  case CK_i586:
412
7
  case CK_Pentium:
413
7
    defineCPUMacros(Builder, "i586");
414
7
    defineCPUMacros(Builder, "pentium");
415
7
    break;
416
8
  case CK_Pentium3:
417
8
  case CK_PentiumM:
418
8
    Builder.defineMacro("__tune_pentium3__");
419
8
    LLVM_FALLTHROUGH;
420
10
  case CK_Pentium2:
421
10
  case CK_C3_2:
422
10
    Builder.defineMacro("__tune_pentium2__");
423
10
    LLVM_FALLTHROUGH;
424
27
  case CK_PentiumPro:
425
27
  case CK_i686:
426
27
    defineCPUMacros(Builder, "i686");
427
27
    defineCPUMacros(Builder, "pentiumpro");
428
27
    break;
429
8.87k
  case CK_Pentium4:
430
8.87k
    defineCPUMacros(Builder, "pentium4");
431
8.87k
    break;
432
14
  case CK_Yonah:
433
14
  case CK_Prescott:
434
14
  case CK_Nocona:
435
14
    defineCPUMacros(Builder, "nocona");
436
14
    break;
437
18.4k
  case CK_Core2:
438
18.4k
  case CK_Penryn:
439
18.4k
    defineCPUMacros(Builder, "core2");
440
18.4k
    break;
441
54
  case CK_Bonnell:
442
54
    defineCPUMacros(Builder, "atom");
443
54
    break;
444
4
  case CK_Silvermont:
445
4
    defineCPUMacros(Builder, "slm");
446
4
    break;
447
2
  case CK_Goldmont:
448
2
    defineCPUMacros(Builder, "goldmont");
449
2
    break;
450
2
  case CK_GoldmontPlus:
451
2
    defineCPUMacros(Builder, "goldmont_plus");
452
2
    break;
453
2
  case CK_Tremont:
454
2
    defineCPUMacros(Builder, "tremont");
455
2
    break;
456
66
  case CK_Nehalem:
457
66
  case CK_Westmere:
458
66
  case CK_SandyBridge:
459
66
  case CK_IvyBridge:
460
66
  case CK_Haswell:
461
66
  case CK_Broadwell:
462
66
  case CK_SkylakeClient:
463
66
  case CK_SkylakeServer:
464
66
  case CK_Cascadelake:
465
66
  case CK_Cooperlake:
466
66
  case CK_Cannonlake:
467
66
  case CK_IcelakeClient:
468
66
  case CK_IcelakeServer:
469
66
  case CK_Tigerlake:
470
66
  case CK_SapphireRapids:
471
    // FIXME: Historically, we defined this legacy name, it would be nice to
472
    // remove it at some point. We've never exposed fine-grained names for
473
    // recent primary x86 CPUs, and we should keep it that way.
474
66
    defineCPUMacros(Builder, "corei7");
475
66
    break;
476
8
  case CK_KNL:
477
8
    defineCPUMacros(Builder, "knl");
478
8
    break;
479
3
  case CK_KNM:
480
3
    break;
481
1
  case CK_Lakemont:
482
1
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
483
1
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
484
1
    Builder.defineMacro("__tune_lakemont__");
485
1
    break;
486
1
  case CK_K6_2:
487
1
    Builder.defineMacro("__k6_2__");
488
1
    Builder.defineMacro("__tune_k6_2__");
489
1
    LLVM_FALLTHROUGH;
490
2
  case CK_K6_3:
491
2
    if (CPU != CK_K6_2) { // In case of fallthrough
492
      // FIXME: GCC may be enabling these in cases where some other k6
493
      // architecture is specified but -m3dnow is explicitly provided. The
494
      // exact semantics need to be determined and emulated here.
495
1
      Builder.defineMacro("__k6_3__");
496
1
      Builder.defineMacro("__tune_k6_3__");
497
1
    }
498
2
    LLVM_FALLTHROUGH;
499
3
  case CK_K6:
500
3
    defineCPUMacros(Builder, "k6");
501
3
    break;
502
5
  case CK_Athlon:
503
5
  case CK_AthlonXP:
504
5
    defineCPUMacros(Builder, "athlon");
505
5
    if (SSELevel != NoSSE) {
506
3
      Builder.defineMacro("__athlon_sse__");
507
3
      Builder.defineMacro("__tune_athlon_sse__");
508
3
    }
509
5
    break;
510
8.37k
  case CK_K8:
511
8.37k
  case CK_K8SSE3:
512
8.37k
  case CK_x86_64:
513
8.37k
  case CK_x86_64_v2:
514
8.37k
  case CK_x86_64_v3:
515
8.37k
  case CK_x86_64_v4:
516
8.37k
    defineCPUMacros(Builder, "k8");
517
8.37k
    break;
518
4
  case CK_AMDFAM10:
519
4
    defineCPUMacros(Builder, "amdfam10");
520
4
    break;
521
4
  case CK_BTVER1:
522
4
    defineCPUMacros(Builder, "btver1");
523
4
    break;
524
10
  case CK_BTVER2:
525
10
    defineCPUMacros(Builder, "btver2");
526
10
    break;
527
4
  case CK_BDVER1:
528
4
    defineCPUMacros(Builder, "bdver1");
529
4
    break;
530
4
  case CK_BDVER2:
531
4
    defineCPUMacros(Builder, "bdver2");
532
4
    break;
533
3
  case CK_BDVER3:
534
3
    defineCPUMacros(Builder, "bdver3");
535
3
    break;
536
3
  case CK_BDVER4:
537
3
    defineCPUMacros(Builder, "bdver4");
538
3
    break;
539
4
  case CK_ZNVER1:
540
4
    defineCPUMacros(Builder, "znver1");
541
4
    break;
542
3
  case CK_ZNVER2:
543
3
    defineCPUMacros(Builder, "znver2");
544
3
    break;
545
1
  case CK_Geode:
546
1
    defineCPUMacros(Builder, "geode");
547
1
    break;
548
72.7k
  }
549
550
  // Target properties.
551
72.7k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
552
553
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
554
  // functions in glibc header files that use FP Stack inline asm which the
555
  // backend can't deal with (PR879).
556
72.7k
  Builder.defineMacro("__NO_MATH_INLINES");
557
558
72.7k
  if (HasAES)
559
88
    Builder.defineMacro("__AES__");
560
561
72.7k
  if (HasVAES)
562
13
    Builder.defineMacro("__VAES__");
563
564
72.7k
  if (HasPCLMUL)
565
113
    Builder.defineMacro("__PCLMUL__");
566
567
72.7k
  if (HasVPCLMULQDQ)
568
13
    Builder.defineMacro("__VPCLMULQDQ__");
569
570
  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
571
  // the feature flag only applies to 64-bit mode.
572
72.7k
  if (HasLAHFSAHF || 
getTriple().getArch() == llvm::Triple::x8654.1k
)
573
31.8k
    Builder.defineMacro("__LAHF_SAHF__");
574
575
72.7k
  if (HasLZCNT)
576
100
    Builder.defineMacro("__LZCNT__");
577
578
72.7k
  if (HasRDRND)
579
81
    Builder.defineMacro("__RDRND__");
580
581
72.7k
  if (HasFSGSBASE)
582
80
    Builder.defineMacro("__FSGSBASE__");
583
584
72.7k
  if (HasBMI)
585
88
    Builder.defineMacro("__BMI__");
586
587
72.7k
  if (HasBMI2)
588
72
    Builder.defineMacro("__BMI2__");
589
590
72.7k
  if (HasPOPCNT)
591
294
    Builder.defineMacro("__POPCNT__");
592
593
72.7k
  if (HasRTM)
594
1
    Builder.defineMacro("__RTM__");
595
596
72.7k
  if (HasPRFCHW)
597
103
    Builder.defineMacro("__PRFCHW__");
598
599
72.7k
  if (HasRDSEED)
600
67
    Builder.defineMacro("__RDSEED__");
601
602
72.7k
  if (HasADX)
603
61
    Builder.defineMacro("__ADX__");
604
605
72.7k
  if (HasTBM)
606
11
    Builder.defineMacro("__TBM__");
607
608
72.7k
  if (HasLWP)
609
15
    Builder.defineMacro("__LWP__");
610
611
72.7k
  if (HasMWAITX)
612
13
    Builder.defineMacro("__MWAITX__");
613
614
72.7k
  if (HasMOVBE)
615
146
    Builder.defineMacro("__MOVBE__");
616
617
72.7k
  switch (XOPLevel) {
618
18
  case XOP:
619
18
    Builder.defineMacro("__XOP__");
620
18
    LLVM_FALLTHROUGH;
621
19
  case FMA4:
622
19
    Builder.defineMacro("__FMA4__");
623
19
    LLVM_FALLTHROUGH;
624
44
  case SSE4A:
625
44
    Builder.defineMacro("__SSE4A__");
626
44
    LLVM_FALLTHROUGH;
627
72.7k
  case NoXOP:
628
72.7k
    break;
629
72.7k
  }
630
631
72.7k
  if (HasFMA)
632
174
    Builder.defineMacro("__FMA__");
633
634
72.7k
  if (HasF16C)
635
185
    Builder.defineMacro("__F16C__");
636
637
72.7k
  if (HasGFNI)
638
16
    Builder.defineMacro("__GFNI__");
639
640
72.7k
  if (HasAVX512CD)
641
46
    Builder.defineMacro("__AVX512CD__");
642
72.7k
  if (HasAVX512VPOPCNTDQ)
643
15
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
644
72.7k
  if (HasAVX512VNNI)
645
17
    Builder.defineMacro("__AVX512VNNI__");
646
72.7k
  if (HasAVX512BF16)
647
8
    Builder.defineMacro("__AVX512BF16__");
648
72.7k
  if (HasAVX512ER)
649
12
    Builder.defineMacro("__AVX512ER__");
650
72.7k
  if (HasAVX512PF)
651
11
    Builder.defineMacro("__AVX512PF__");
652
72.7k
  if (HasAVX512DQ)
653
37
    Builder.defineMacro("__AVX512DQ__");
654
72.7k
  if (HasAVX512BITALG)
655
13
    Builder.defineMacro("__AVX512BITALG__");
656
72.7k
  if (HasAVX512BW)
657
53
    Builder.defineMacro("__AVX512BW__");
658
72.7k
  if (HasAVX512VL)
659
55
    Builder.defineMacro("__AVX512VL__");
660
72.7k
  if (HasAVX512VBMI)
661
16
    Builder.defineMacro("__AVX512VBMI__");
662
72.7k
  if (HasAVX512VBMI2)
663
13
    Builder.defineMacro("__AVX512VBMI2__");
664
72.7k
  if (HasAVX512IFMA)
665
16
    Builder.defineMacro("__AVX512IFMA__");
666
72.7k
  if (HasAVX512VP2INTERSECT)
667
9
    Builder.defineMacro("__AVX512VP2INTERSECT__");
668
72.7k
  if (HasSHA)
669
27
    Builder.defineMacro("__SHA__");
670
671
72.7k
  if (HasFXSR)
672
35.8k
    Builder.defineMacro("__FXSR__");
673
72.7k
  if (HasXSAVE)
674
286
    Builder.defineMacro("__XSAVE__");
675
72.7k
  if (HasXSAVEOPT)
676
106
    Builder.defineMacro("__XSAVEOPT__");
677
72.7k
  if (HasXSAVEC)
678
58
    Builder.defineMacro("__XSAVEC__");
679
72.7k
  if (HasXSAVES)
680
58
    Builder.defineMacro("__XSAVES__");
681
72.7k
  if (HasPKU)
682
34
    Builder.defineMacro("__PKU__");
683
72.7k
  if (HasCLFLUSHOPT)
684
52
    Builder.defineMacro("__CLFLUSHOPT__");
685
72.7k
  if (HasCLWB)
686
36
    Builder.defineMacro("__CLWB__");
687
72.7k
  if (HasWBNOINVD)
688
12
    Builder.defineMacro("__WBNOINVD__");
689
72.7k
  if (HasSHSTK)
690
10
    Builder.defineMacro("__SHSTK__");
691
72.7k
  if (HasSGX)
692
23
    Builder.defineMacro("__SGX__");
693
72.7k
  if (HasPREFETCHWT1)
694
11
    Builder.defineMacro("__PREFETCHWT1__");
695
72.7k
  if (HasCLZERO)
696
11
    Builder.defineMacro("__CLZERO__");
697
72.7k
  if (HasKL)
698
8
    Builder.defineMacro("__KL__");
699
72.7k
  if (HasWIDEKL)
700
7
    Builder.defineMacro("__WIDEKL__");
701
72.7k
  if (HasRDPID)
702
19
    Builder.defineMacro("__RDPID__");
703
72.7k
  if (HasCLDEMOTE)
704
7
    Builder.defineMacro("__CLDEMOTE__");
705
72.7k
  if (HasWAITPKG)
706
4
    Builder.defineMacro("__WAITPKG__");
707
72.7k
  if (HasMOVDIRI)
708
9
    Builder.defineMacro("__MOVDIRI__");
709
72.7k
  if (HasMOVDIR64B)
710
9
    Builder.defineMacro("__MOVDIR64B__");
711
72.7k
  if (HasPCONFIG)
712
7
    Builder.defineMacro("__PCONFIG__");
713
72.7k
  if (HasPTWRITE)
714
8
    Builder.defineMacro("__PTWRITE__");
715
72.7k
  if (HasINVPCID)
716
60
    Builder.defineMacro("__INVPCID__");
717
72.7k
  if (HasENQCMD)
718
5
    Builder.defineMacro("__ENQCMD__");
719
72.7k
  if (HasHRESET)
720
3
    Builder.defineMacro("__HRESET__");
721
72.7k
  if (HasAMXTILE)
722
8
    Builder.defineMacro("__AMXTILE__");
723
72.7k
  if (HasAMXINT8)
724
6
    Builder.defineMacro("__AMXINT8__");
725
72.7k
  if (HasAMXBF16)
726
6
    Builder.defineMacro("__AMXBF16__");
727
72.7k
  if (HasSERIALIZE)
728
5
    Builder.defineMacro("__SERIALIZE__");
729
72.7k
  if (HasTSXLDTRK)
730
5
    Builder.defineMacro("__TSXLDTRK__");
731
72.7k
  if (HasUINTR)
732
4
    Builder.defineMacro("__UINTR__");
733
734
  // Each case falls through to the previous one here.
735
72.7k
  switch (SSELevel) {
736
136
  case AVX512F:
737
136
    Builder.defineMacro("__AVX512F__");
738
136
    LLVM_FALLTHROUGH;
739
165
  case AVX2:
740
165
    Builder.defineMacro("__AVX2__");
741
165
    LLVM_FALLTHROUGH;
742
252
  case AVX:
743
252
    Builder.defineMacro("__AVX__");
744
252
    LLVM_FALLTHROUGH;
745
279
  case SSE42:
746
279
    Builder.defineMacro("__SSE4_2__");
747
279
    LLVM_FALLTHROUGH;
748
18.5k
  case SSE41:
749
18.5k
    Builder.defineMacro("__SSE4_1__");
750
18.5k
    LLVM_FALLTHROUGH;
751
18.7k
  case SSSE3:
752
18.7k
    Builder.defineMacro("__SSSE3__");
753
18.7k
    LLVM_FALLTHROUGH;
754
18.7k
  case SSE3:
755
18.7k
    Builder.defineMacro("__SSE3__");
756
18.7k
    LLVM_FALLTHROUGH;
757
68.3k
  case SSE2:
758
68.3k
    Builder.defineMacro("__SSE2__");
759
68.3k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
760
68.3k
    LLVM_FALLTHROUGH;
761
68.4k
  case SSE1:
762
68.4k
    Builder.defineMacro("__SSE__");
763
68.4k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
764
68.4k
    LLVM_FALLTHROUGH;
765
72.7k
  case NoSSE:
766
72.7k
    break;
767
72.7k
  }
768
769
72.7k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x8610.3k
) {
770
320
    switch (SSELevel) {
771
48
    case AVX512F:
772
48
    case AVX2:
773
48
    case AVX:
774
48
    case SSE42:
775
48
    case SSE41:
776
48
    case SSSE3:
777
48
    case SSE3:
778
48
    case SSE2:
779
48
      Builder.defineMacro("_M_IX86_FP", Twine(2));
780
48
      break;
781
2
    case SSE1:
782
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
783
2
      break;
784
270
    default:
785
270
      Builder.defineMacro("_M_IX86_FP", Twine(0));
786
270
      break;
787
72.7k
    }
788
72.7k
  }
789
790
  // Each case falls through to the previous one here.
791
72.7k
  switch (MMX3DNowLevel) {
792
33
  case AMD3DNowAthlon:
793
33
    Builder.defineMacro("__3dNOW_A__");
794
33
    LLVM_FALLTHROUGH;
795
39
  case AMD3DNow:
796
39
    Builder.defineMacro("__3dNOW__");
797
39
    LLVM_FALLTHROUGH;
798
68.4k
  case MMX:
799
68.4k
    Builder.defineMacro("__MMX__");
800
68.4k
    LLVM_FALLTHROUGH;
801
72.7k
  case NoMMX3DNow:
802
72.7k
    break;
803
72.7k
  }
804
805
72.7k
  if (CPU >= CK_i486 || 
CPU == CK_None36.8k
) {
806
72.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
807
72.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
808
72.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
809
72.7k
  }
810
72.7k
  if (HasCX8)
811
72.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
812
72.7k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6418.6k
)
813
18.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
814
815
72.7k
  if (HasFloat128)
816
3.37k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
817
72.7k
}
818
819
1.33M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
820
1.33M
  return llvm::StringSwitch<bool>(Name)
821
1.33M
      .Case("3dnow", true)
822
1.33M
      .Case("3dnowa", true)
823
1.33M
      .Case("adx", true)
824
1.33M
      .Case("aes", true)
825
1.33M
      .Case("amx-bf16", true)
826
1.33M
      .Case("amx-int8", true)
827
1.33M
      .Case("amx-tile", true)
828
1.33M
      .Case("avx", true)
829
1.33M
      .Case("avx2", true)
830
1.33M
      .Case("avx512f", true)
831
1.33M
      .Case("avx512cd", true)
832
1.33M
      .Case("avx512vpopcntdq", true)
833
1.33M
      .Case("avx512vnni", true)
834
1.33M
      .Case("avx512bf16", true)
835
1.33M
      .Case("avx512er", true)
836
1.33M
      .Case("avx512pf", true)
837
1.33M
      .Case("avx512dq", true)
838
1.33M
      .Case("avx512bitalg", true)
839
1.33M
      .Case("avx512bw", true)
840
1.33M
      .Case("avx512vl", true)
841
1.33M
      .Case("avx512vbmi", true)
842
1.33M
      .Case("avx512vbmi2", true)
843
1.33M
      .Case("avx512ifma", true)
844
1.33M
      .Case("avx512vp2intersect", true)
845
1.33M
      .Case("bmi", true)
846
1.33M
      .Case("bmi2", true)
847
1.33M
      .Case("cldemote", true)
848
1.33M
      .Case("clflushopt", true)
849
1.33M
      .Case("clwb", true)
850
1.33M
      .Case("clzero", true)
851
1.33M
      .Case("cx16", true)
852
1.33M
      .Case("enqcmd", true)
853
1.33M
      .Case("f16c", true)
854
1.33M
      .Case("fma", true)
855
1.33M
      .Case("fma4", true)
856
1.33M
      .Case("fsgsbase", true)
857
1.33M
      .Case("fxsr", true)
858
1.33M
      .Case("gfni", true)
859
1.33M
      .Case("hreset", true)
860
1.33M
      .Case("invpcid", true)
861
1.33M
      .Case("kl", true)
862
1.33M
      .Case("widekl", true)
863
1.33M
      .Case("lwp", true)
864
1.33M
      .Case("lzcnt", true)
865
1.33M
      .Case("mmx", true)
866
1.33M
      .Case("movbe", true)
867
1.33M
      .Case("movdiri", true)
868
1.33M
      .Case("movdir64b", true)
869
1.33M
      .Case("mwaitx", true)
870
1.33M
      .Case("pclmul", true)
871
1.33M
      .Case("pconfig", true)
872
1.33M
      .Case("pku", true)
873
1.33M
      .Case("popcnt", true)
874
1.33M
      .Case("prefetchwt1", true)
875
1.33M
      .Case("prfchw", true)
876
1.33M
      .Case("ptwrite", true)
877
1.33M
      .Case("rdpid", true)
878
1.33M
      .Case("rdrnd", true)
879
1.33M
      .Case("rdseed", true)
880
1.33M
      .Case("rtm", true)
881
1.33M
      .Case("sahf", true)
882
1.33M
      .Case("serialize", true)
883
1.33M
      .Case("sgx", true)
884
1.33M
      .Case("sha", true)
885
1.33M
      .Case("shstk", true)
886
1.33M
      .Case("sse", true)
887
1.33M
      .Case("sse2", true)
888
1.33M
      .Case("sse3", true)
889
1.33M
      .Case("ssse3", true)
890
1.33M
      .Case("sse4", true)
891
1.33M
      .Case("sse4.1", true)
892
1.33M
      .Case("sse4.2", true)
893
1.33M
      .Case("sse4a", true)
894
1.33M
      .Case("tbm", true)
895
1.33M
      .Case("tsxldtrk", true)
896
1.33M
      .Case("uintr", true)
897
1.33M
      .Case("vaes", true)
898
1.33M
      .Case("vpclmulqdq", true)
899
1.33M
      .Case("wbnoinvd", true)
900
1.33M
      .Case("waitpkg", true)
901
1.33M
      .Case("x87", true)
902
1.33M
      .Case("xop", true)
903
1.33M
      .Case("xsave", true)
904
1.33M
      .Case("xsavec", true)
905
1.33M
      .Case("xsaves", true)
906
1.33M
      .Case("xsaveopt", true)
907
1.33M
      .Default(false);
908
1.33M
}
909
910
431k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
911
431k
  return llvm::StringSwitch<bool>(Feature)
912
431k
      .Case("adx", HasADX)
913
431k
      .Case("aes", HasAES)
914
431k
      .Case("amx-bf16", HasAMXBF16)
915
431k
      .Case("amx-int8", HasAMXINT8)
916
431k
      .Case("amx-tile", HasAMXTILE)
917
431k
      .Case("avx", SSELevel >= AVX)
918
431k
      .Case("avx2", SSELevel >= AVX2)
919
431k
      .Case("avx512f", SSELevel >= AVX512F)
920
431k
      .Case("avx512cd", HasAVX512CD)
921
431k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
922
431k
      .Case("avx512vnni", HasAVX512VNNI)
923
431k
      .Case("avx512bf16", HasAVX512BF16)
924
431k
      .Case("avx512er", HasAVX512ER)
925
431k
      .Case("avx512pf", HasAVX512PF)
926
431k
      .Case("avx512dq", HasAVX512DQ)
927
431k
      .Case("avx512bitalg", HasAVX512BITALG)
928
431k
      .Case("avx512bw", HasAVX512BW)
929
431k
      .Case("avx512vl", HasAVX512VL)
930
431k
      .Case("avx512vbmi", HasAVX512VBMI)
931
431k
      .Case("avx512vbmi2", HasAVX512VBMI2)
932
431k
      .Case("avx512ifma", HasAVX512IFMA)
933
431k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
934
431k
      .Case("bmi", HasBMI)
935
431k
      .Case("bmi2", HasBMI2)
936
431k
      .Case("cldemote", HasCLDEMOTE)
937
431k
      .Case("clflushopt", HasCLFLUSHOPT)
938
431k
      .Case("clwb", HasCLWB)
939
431k
      .Case("clzero", HasCLZERO)
940
431k
      .Case("cx8", HasCX8)
941
431k
      .Case("cx16", HasCX16)
942
431k
      .Case("enqcmd", HasENQCMD)
943
431k
      .Case("f16c", HasF16C)
944
431k
      .Case("fma", HasFMA)
945
431k
      .Case("fma4", XOPLevel >= FMA4)
946
431k
      .Case("fsgsbase", HasFSGSBASE)
947
431k
      .Case("fxsr", HasFXSR)
948
431k
      .Case("gfni", HasGFNI)
949
431k
      .Case("hreset", HasHRESET)
950
431k
      .Case("invpcid", HasINVPCID)
951
431k
      .Case("kl", HasKL)
952
431k
      .Case("widekl", HasWIDEKL)
953
431k
      .Case("lwp", HasLWP)
954
431k
      .Case("lzcnt", HasLZCNT)
955
431k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
956
431k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
957
431k
      .Case("mmx", MMX3DNowLevel >= MMX)
958
431k
      .Case("movbe", HasMOVBE)
959
431k
      .Case("movdiri", HasMOVDIRI)
960
431k
      .Case("movdir64b", HasMOVDIR64B)
961
431k
      .Case("mwaitx", HasMWAITX)
962
431k
      .Case("pclmul", HasPCLMUL)
963
431k
      .Case("pconfig", HasPCONFIG)
964
431k
      .Case("pku", HasPKU)
965
431k
      .Case("popcnt", HasPOPCNT)
966
431k
      .Case("prefetchwt1", HasPREFETCHWT1)
967
431k
      .Case("prfchw", HasPRFCHW)
968
431k
      .Case("ptwrite", HasPTWRITE)
969
431k
      .Case("rdpid", HasRDPID)
970
431k
      .Case("rdrnd", HasRDRND)
971
431k
      .Case("rdseed", HasRDSEED)
972
431k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
973
431k
      .Case("rtm", HasRTM)
974
431k
      .Case("sahf", HasLAHFSAHF)
975
431k
      .Case("serialize", HasSERIALIZE)
976
431k
      .Case("sgx", HasSGX)
977
431k
      .Case("sha", HasSHA)
978
431k
      .Case("shstk", HasSHSTK)
979
431k
      .Case("sse", SSELevel >= SSE1)
980
431k
      .Case("sse2", SSELevel >= SSE2)
981
431k
      .Case("sse3", SSELevel >= SSE3)
982
431k
      .Case("ssse3", SSELevel >= SSSE3)
983
431k
      .Case("sse4.1", SSELevel >= SSE41)
984
431k
      .Case("sse4.2", SSELevel >= SSE42)
985
431k
      .Case("sse4a", XOPLevel >= SSE4A)
986
431k
      .Case("tbm", HasTBM)
987
431k
      .Case("tsxldtrk", HasTSXLDTRK)
988
431k
      .Case("uintr", HasUINTR)
989
431k
      .Case("vaes", HasVAES)
990
431k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
991
431k
      .Case("wbnoinvd", HasWBNOINVD)
992
431k
      .Case("waitpkg", HasWAITPKG)
993
431k
      .Case("x86", true)
994
431k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
995
431k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
996
431k
      .Case("xop", XOPLevel >= XOP)
997
431k
      .Case("xsave", HasXSAVE)
998
431k
      .Case("xsavec", HasXSAVEC)
999
431k
      .Case("xsaves", HasXSAVES)
1000
431k
      .Case("xsaveopt", HasXSAVEOPT)
1001
431k
      .Default(false);
1002
431k
}
1003
1004
// We can't use a generic validation scheme for the features accepted here
1005
// versus subtarget features accepted in the target attribute because the
1006
// bitfield structure that's initialized in the runtime only supports the
1007
// below currently rather than the full range of subtarget features. (See
1008
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1009
730
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1010
730
  return llvm::StringSwitch<bool>(FeatureStr)
1011
27.7k
#define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true)
1012
730
#include "llvm/Support/X86TargetParser.def"
1013
730
      .Default(false);
1014
730
}
1015
1016
158
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1017
158
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1018
6.00k
#define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM)
1019
158
#include "llvm/Support/X86TargetParser.def"
1020
158
      ;
1021
  // Note, this function should only be used after ensuring the value is
1022
  // correct, so it asserts if the value is out of range.
1023
158
}
1024
1025
408
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1026
408
  enum class FeatPriority {
1027
408
#define FEATURE(FEAT) FEAT,
1028
408
#include "clang/Basic/X86Target.def"
1029
408
  };
1030
408
  switch (Feat) {
1031
0
#define FEATURE(FEAT)                                                          \
1032
408
  case llvm::X86::FEAT:                                                        \
1033
408
    return static_cast<unsigned>(FeatPriority::FEAT);
1034
0
#include "clang/Basic/X86Target.def"
1035
0
  default:
1036
0
    llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1037
408
  }
1038
408
}
1039
1040
408
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1041
  // Valid CPUs have a 'key feature' that compares just better than its key
1042
  // feature.
1043
408
  using namespace llvm::X86;
1044
408
  CPUKind Kind = parseArchX86(Name);
1045
408
  if (Kind != CK_None) {
1046
250
    ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1047
250
    return (getFeaturePriority(KeyFeature) << 1) + 1;
1048
250
  }
1049
1050
  // Now we know we have a feature, so get its priority and shift it a few so
1051
  // that we have sufficient room for the CPUs (above).
1052
158
  return getFeaturePriority(getFeature(Name)) << 1;
1053
158
}
1054
1055
163
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1056
163
  return llvm::StringSwitch<bool>(Name)
1057
4.56k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1058
978
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1059
163
#include "clang/Basic/X86Target.def"
1060
163
      .Default(false);
1061
163
}
1062
1063
350
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1064
350
  return llvm::StringSwitch<StringRef>(Name)
1065
2.10k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1066
350
#include "clang/Basic/X86Target.def"
1067
350
      .Default(Name);
1068
350
}
1069
1070
250
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1071
250
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1072
7.00k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1073
250
#include "clang/Basic/X86Target.def"
1074
250
      .Default(0);
1075
250
}
1076
1077
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1078
100
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1079
100
  StringRef WholeList =
1080
100
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1081
2.80k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1082
100
#include "clang/Basic/X86Target.def"
1083
100
          .Default("");
1084
100
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1085
100
}
1086
1087
// We can't use a generic validation scheme for the cpus accepted here
1088
// versus subtarget cpus accepted in the target attribute because the
1089
// variables intitialized by the runtime only support the below currently
1090
// rather than the full range of cpus.
1091
177
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1092
177
  return llvm::StringSwitch<bool>(FeatureStr)
1093
354
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1094
708
#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1095
2.47k
#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1096
4.24k
#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1097
177
#include "llvm/Support/X86TargetParser.def"
1098
177
      .Default(false);
1099
177
}
1100
1101
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1102
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1103
87
                .Case("@cca", 4)
1104
87
                .Case("@ccae", 5)
1105
87
                .Case("@ccb", 4)
1106
87
                .Case("@ccbe", 5)
1107
87
                .Case("@ccc", 4)
1108
87
                .Case("@cce", 4)
1109
87
                .Case("@ccz", 4)
1110
87
                .Case("@ccg", 4)
1111
87
                .Case("@ccge", 5)
1112
87
                .Case("@ccl", 4)
1113
87
                .Case("@ccle", 5)
1114
87
                .Case("@ccna", 5)
1115
87
                .Case("@ccnae", 6)
1116
87
                .Case("@ccnb", 5)
1117
87
                .Case("@ccnbe", 6)
1118
87
                .Case("@ccnc", 5)
1119
87
                .Case("@ccne", 5)
1120
87
                .Case("@ccnz", 5)
1121
87
                .Case("@ccng", 5)
1122
87
                .Case("@ccnge", 6)
1123
87
                .Case("@ccnl", 5)
1124
87
                .Case("@ccnle", 6)
1125
87
                .Case("@ccno", 5)
1126
87
                .Case("@ccnp", 5)
1127
87
                .Case("@ccns", 5)
1128
87
                .Case("@cco", 4)
1129
87
                .Case("@ccp", 4)
1130
87
                .Case("@ccs", 4)
1131
87
                .Default(0);
1132
87
  return RV;
1133
87
}
1134
1135
bool X86TargetInfo::validateAsmConstraint(
1136
9.76k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1137
9.76k
  switch (*Name) {
1138
3
  default:
1139
3
    return false;
1140
  // Constant constraints.
1141
17
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1142
            // instructions.
1143
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1144
            // x86_64 instructions.
1145
17
  case 's':
1146
17
    Info.setRequiresImmediate();
1147
17
    return true;
1148
28
  case 'I':
1149
28
    Info.setRequiresImmediate(0, 31);
1150
28
    return true;
1151
14
  case 'J':
1152
14
    Info.setRequiresImmediate(0, 63);
1153
14
    return true;
1154
14
  case 'K':
1155
14
    Info.setRequiresImmediate(-128, 127);
1156
14
    return true;
1157
30
  case 'L':
1158
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1159
30
    return true;
1160
14
  case 'M':
1161
14
    Info.setRequiresImmediate(0, 3);
1162
14
    return true;
1163
16
  case 'N':
1164
16
    Info.setRequiresImmediate(0, 255);
1165
16
    return true;
1166
6
  case 'O':
1167
6
    Info.setRequiresImmediate(0, 127);
1168
6
    return true;
1169
  // Register constraints.
1170
52
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1171
    // Shift the pointer to the second character of the constraint.
1172
52
    Name++;
1173
52
    switch (*Name) {
1174
0
    default:
1175
0
      return false;
1176
52
    case 'z': // First SSE register.
1177
52
    case '2':
1178
52
    case 't': // Any SSE register, when SSE2 is enabled.
1179
52
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1180
52
    case 'm': // Any MMX register, when inter-unit moves enabled.
1181
52
    case 'k': // AVX512 arch mask registers: k1-k7.
1182
52
      Info.setAllowsRegister();
1183
52
      return true;
1184
0
    }
1185
3
  case 'f': // Any x87 floating point stack register.
1186
    // Constraint 'f' cannot be used for output operands.
1187
3
    if (Info.ConstraintStr[0] == '=')
1188
1
      return false;
1189
2
    Info.setAllowsRegister();
1190
2
    return true;
1191
9.49k
  case 'a': // eax.
1192
9.49k
  case 'b': // ebx.
1193
9.49k
  case 'c': // ecx.
1194
9.49k
  case 'd': // edx.
1195
9.49k
  case 'S': // esi.
1196
9.49k
  case 'D': // edi.
1197
9.49k
  case 'A': // edx:eax.
1198
9.49k
  case 't': // Top of floating point stack.
1199
9.49k
  case 'u': // Second from top of floating point stack.
1200
9.49k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1201
9.49k
  case 'y': // Any MMX register.
1202
9.49k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1203
9.49k
  case 'x': // Any SSE register.
1204
9.49k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1205
            // for intermideate k reg operations).
1206
9.49k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1207
9.49k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1208
9.49k
  case 'l': // "Index" registers: any general register that can be used as an
1209
            // index in a base+index memory access.
1210
9.49k
    Info.setAllowsRegister();
1211
9.49k
    return true;
1212
  // Floating point constant constraints.
1213
16
  case 'C': // SSE floating point constant.
1214
16
  case 'G': // x87 floating point constant.
1215
16
    return true;
1216
58
  case '@':
1217
    // CC condition changes.
1218
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1219
58
      Name += Len - 1;
1220
58
      Info.setAllowsRegister();
1221
58
      return true;
1222
58
    }
1223
0
    return false;
1224
9.76k
  }
1225
9.76k
}
1226
1227
// Below is based on the following information:
1228
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1229
// |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1230
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1231
// | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1232
// | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1233
// | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1234
// | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1235
// | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1236
// | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1237
// | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1238
// | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1239
// | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1240
// | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1241
// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1242
// | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1243
// | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1244
// | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1245
// | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1246
// | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1247
// | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1248
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1249
0
Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1250
0
  using namespace llvm::X86;
1251
0
  switch (CPU) {
1252
    // i386
1253
0
    case CK_i386:
1254
    // i486
1255
0
    case CK_i486:
1256
0
    case CK_WinChipC6:
1257
0
    case CK_WinChip2:
1258
0
    case CK_C3:
1259
    // Lakemont
1260
0
    case CK_Lakemont:
1261
0
      return 16;
1262
1263
    // i586
1264
0
    case CK_i586:
1265
0
    case CK_Pentium:
1266
0
    case CK_PentiumMMX:
1267
    // i686
1268
0
    case CK_PentiumPro:
1269
0
    case CK_i686:
1270
0
    case CK_Pentium2:
1271
0
    case CK_Pentium3:
1272
0
    case CK_PentiumM:
1273
0
    case CK_C3_2:
1274
    // K6
1275
0
    case CK_K6:
1276
0
    case CK_K6_2:
1277
0
    case CK_K6_3:
1278
    // Geode
1279
0
    case CK_Geode:
1280
0
      return 32;
1281
1282
    // Netburst
1283
0
    case CK_Pentium4:
1284
0
    case CK_Prescott:
1285
0
    case CK_Nocona:
1286
    // Atom
1287
0
    case CK_Bonnell:
1288
0
    case CK_Silvermont:
1289
0
    case CK_Goldmont:
1290
0
    case CK_GoldmontPlus:
1291
0
    case CK_Tremont:
1292
1293
0
    case CK_Westmere:
1294
0
    case CK_SandyBridge:
1295
0
    case CK_IvyBridge:
1296
0
    case CK_Haswell:
1297
0
    case CK_Broadwell:
1298
0
    case CK_SkylakeClient:
1299
0
    case CK_SkylakeServer:
1300
0
    case CK_Cascadelake:
1301
0
    case CK_Nehalem:
1302
0
    case CK_Cooperlake:
1303
0
    case CK_Cannonlake:
1304
0
    case CK_Tigerlake:
1305
0
    case CK_SapphireRapids:
1306
0
    case CK_IcelakeClient:
1307
0
    case CK_IcelakeServer:
1308
0
    case CK_KNL:
1309
0
    case CK_KNM:
1310
    // K7
1311
0
    case CK_Athlon:
1312
0
    case CK_AthlonXP:
1313
    // K8
1314
0
    case CK_K8:
1315
0
    case CK_K8SSE3:
1316
0
    case CK_AMDFAM10:
1317
    // Bobcat
1318
0
    case CK_BTVER1:
1319
0
    case CK_BTVER2:
1320
    // Bulldozer
1321
0
    case CK_BDVER1:
1322
0
    case CK_BDVER2:
1323
0
    case CK_BDVER3:
1324
0
    case CK_BDVER4:
1325
    // Zen
1326
0
    case CK_ZNVER1:
1327
0
    case CK_ZNVER2:
1328
    // Deprecated
1329
0
    case CK_x86_64:
1330
0
    case CK_x86_64_v2:
1331
0
    case CK_x86_64_v3:
1332
0
    case CK_x86_64_v4:
1333
0
    case CK_Yonah:
1334
0
    case CK_Penryn:
1335
0
    case CK_Core2:
1336
0
      return 64;
1337
1338
    // The following currently have unknown cache line sizes (but they are probably all 64):
1339
    // Core
1340
0
    case CK_None:
1341
0
      return None;
1342
0
  }
1343
0
  llvm_unreachable("Unknown CPU kind");
1344
0
}
1345
1346
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1347
                                       StringRef Constraint,
1348
5.27k
                                       unsigned Size) const {
1349
  // Strip off constraint modifiers.
1350
10.5k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'5.74k
||
Constraint[0] == '&'5.28k
)
1351
5.28k
    Constraint = Constraint.substr(1);
1352
1353
5.27k
  return validateOperandSize(FeatureMap, Constraint, Size);
1354
5.27k
}
1355
1356
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1357
                                      StringRef Constraint,
1358
5.55k
                                      unsigned Size) const {
1359
5.55k
  return validateOperandSize(FeatureMap, Constraint, Size);
1360
5.55k
}
1361
1362
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1363
                                        StringRef Constraint,
1364
8.93k
                                        unsigned Size) const {
1365
8.93k
  switch (Constraint[0]) {
1366
8.75k
  default:
1367
8.75k
    break;
1368
30
  case 'k':
1369
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1370
30
  case 'y':
1371
30
    return Size <= 64;
1372
18
  case 'f':
1373
18
  case 't':
1374
18
  case 'u':
1375
18
    return Size <= 128;
1376
26
  case 'Y':
1377
    // 'Y' is the first character for several 2-character constraints.
1378
26
    switch (Constraint[1]) {
1379
0
    default:
1380
0
      return false;
1381
5
    case 'm':
1382
      // 'Ym' is synonymous with 'y'.
1383
5
    case 'k':
1384
5
      return Size <= 64;
1385
10
    case 'z':
1386
      // XMM0/YMM/ZMM0
1387
10
      if (FeatureMap.lookup("avx512f"))
1388
        // ZMM0 can be used if target supports AVX512F.
1389
7
        return Size <= 512U;
1390
3
      else if (FeatureMap.lookup("avx"))
1391
        // YMM0 can be used if target supports AVX.
1392
2
        return Size <= 256U;
1393
1
      else if (FeatureMap.lookup("sse"))
1394
1
        return Size <= 128U;
1395
0
      return false;
1396
11
    case 'i':
1397
11
    case 't':
1398
11
    case '2':
1399
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1400
11
      if (SSELevel < SSE2)
1401
0
        return false;
1402
11
      break;
1403
11
    }
1404
11
    break;
1405
107
  case 'v':
1406
107
  case 'x':
1407
107
    if (FeatureMap.lookup("avx512f"))
1408
      // 512-bit zmm registers can be used if target supports AVX512F.
1409
46
      return Size <= 512U;
1410
61
    else if (FeatureMap.lookup("avx"))
1411
      // 256-bit ymm registers can be used if target supports AVX.
1412
27
      return Size <= 256U;
1413
34
    return Size <= 128U;
1414
1415
8.76k
  }
1416
1417
8.76k
  return true;
1418
8.76k
}
1419
1420
1.76k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1421
1.76k
  switch (*Constraint) {
1422
29
  case '@':
1423
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1424
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1425
29
      Constraint += Len - 1;
1426
29
      return Converted;
1427
29
    }
1428
0
    return std::string(1, *Constraint);
1429
84
  case 'a':
1430
84
    return std::string("{ax}");
1431
43
  case 'b':
1432
43
    return std::string("{bx}");
1433
73
  case 'c':
1434
73
    return std::string("{cx}");
1435
40
  case 'd':
1436
40
    return std::string("{dx}");
1437
31
  case 'S':
1438
31
    return std::string("{si}");
1439
39
  case 'D':
1440
39
    return std::string("{di}");
1441
4
  case 'p': // address
1442
4
    return std::string("im");
1443
5
  case 't': // top of floating point stack.
1444
5
    return std::string("{st}");
1445
1
  case 'u':                        // second from top of floating point stack.
1446
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1447
26
  case 'Y':
1448
26
    switch (Constraint[1]) {
1449
0
    default:
1450
      // Break from inner switch and fall through (copy single char),
1451
      // continue parsing after copying the current constraint into
1452
      // the return string.
1453
0
      break;
1454
26
    case 'k':
1455
26
    case 'm':
1456
26
    case 'i':
1457
26
    case 't':
1458
26
    case 'z':
1459
26
    case '2':
1460
      // "^" hints llvm that this is a 2 letter constraint.
1461
      // "Constraint++" is used to promote the string iterator
1462
      // to the next constraint.
1463
26
      return std::string("^") + std::string(Constraint++, 2);
1464
0
    }
1465
0
    LLVM_FALLTHROUGH;
1466
1.38k
  default:
1467
1.38k
    return std::string(1, *Constraint);
1468
1.76k
  }
1469
1.76k
}
1470
1471
31
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1472
31
  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1473
31
  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1474
31
}
1475
1476
5
void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1477
5
  llvm::X86::fillValidTuneCPUList(Values);
1478
5
}
1479
1480
3.55k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1481
3.55k
  return llvm::makeArrayRef(GCCRegNames);
1482
3.55k
}
1483
1484
2.96k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1485
2.96k
  return llvm::makeArrayRef(AddlRegNames);
1486
2.96k
}
1487
1488
13.4k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1489
13.4k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1490
13.4k
                                                Builtin::FirstTSBuiltin + 1);
1491
13.4k
}
1492
1493
59.5k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1494
59.5k
  return llvm::makeArrayRef(BuiltinInfoX86,
1495
59.5k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1496
59.5k
}