/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
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1 | | //===--- X86.cpp - Implement X86 target feature support -------------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file implements X86 TargetInfo objects. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "X86.h" |
14 | | #include "clang/Basic/Builtins.h" |
15 | | #include "clang/Basic/Diagnostic.h" |
16 | | #include "clang/Basic/TargetBuiltins.h" |
17 | | #include "llvm/ADT/StringExtras.h" |
18 | | #include "llvm/ADT/StringRef.h" |
19 | | #include "llvm/ADT/StringSwitch.h" |
20 | | #include "llvm/Support/X86TargetParser.h" |
21 | | |
22 | | namespace clang { |
23 | | namespace targets { |
24 | | |
25 | | const Builtin::Info BuiltinInfoX86[] = { |
26 | | #define BUILTIN(ID, TYPE, ATTRS) \ |
27 | | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, |
28 | | #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ |
29 | | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, |
30 | | #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ |
31 | | {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, |
32 | | #include "clang/Basic/BuiltinsX86.def" |
33 | | |
34 | | #define BUILTIN(ID, TYPE, ATTRS) \ |
35 | | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, |
36 | | #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ |
37 | | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, |
38 | | #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ |
39 | | {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, |
40 | | #include "clang/Basic/BuiltinsX86_64.def" |
41 | | }; |
42 | | |
43 | | static const char *const GCCRegNames[] = { |
44 | | "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", |
45 | | "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", |
46 | | "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", |
47 | | "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", |
48 | | "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", |
49 | | "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", |
50 | | "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", |
51 | | "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", |
52 | | "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", |
53 | | "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", |
54 | | "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", |
55 | | "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", |
56 | | "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", |
57 | | "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", |
58 | | "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", |
59 | | "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", |
60 | | "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", |
61 | | "k2", "k3", "k4", "k5", "k6", "k7", |
62 | | "cr0", "cr2", "cr3", "cr4", "cr8", |
63 | | "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", |
64 | | "bnd0", "bnd1", "bnd2", "bnd3", |
65 | | "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", |
66 | | }; |
67 | | |
68 | | const TargetInfo::AddlRegName AddlRegNames[] = { |
69 | | {{"al", "ah", "eax", "rax"}, 0}, |
70 | | {{"bl", "bh", "ebx", "rbx"}, 3}, |
71 | | {{"cl", "ch", "ecx", "rcx"}, 2}, |
72 | | {{"dl", "dh", "edx", "rdx"}, 1}, |
73 | | {{"esi", "rsi"}, 4}, |
74 | | {{"edi", "rdi"}, 5}, |
75 | | {{"esp", "rsp"}, 7}, |
76 | | {{"ebp", "rbp"}, 6}, |
77 | | {{"r8d", "r8w", "r8b"}, 38}, |
78 | | {{"r9d", "r9w", "r9b"}, 39}, |
79 | | {{"r10d", "r10w", "r10b"}, 40}, |
80 | | {{"r11d", "r11w", "r11b"}, 41}, |
81 | | {{"r12d", "r12w", "r12b"}, 42}, |
82 | | {{"r13d", "r13w", "r13b"}, 43}, |
83 | | {{"r14d", "r14w", "r14b"}, 44}, |
84 | | {{"r15d", "r15w", "r15b"}, 45}, |
85 | | }; |
86 | | |
87 | | } // namespace targets |
88 | | } // namespace clang |
89 | | |
90 | | using namespace clang; |
91 | | using namespace clang::targets; |
92 | | |
93 | 5 | bool X86TargetInfo::setFPMath(StringRef Name) { |
94 | 5 | if (Name == "387") { |
95 | 2 | FPMath = FP_387; |
96 | 2 | return true; |
97 | 2 | } |
98 | 3 | if (Name == "sse") { |
99 | 2 | FPMath = FP_SSE; |
100 | 2 | return true; |
101 | 2 | } |
102 | 1 | return false; |
103 | 1 | } |
104 | | |
105 | | bool X86TargetInfo::initFeatureMap( |
106 | | llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, |
107 | 126k | const std::vector<std::string> &FeaturesVec) const { |
108 | | // FIXME: This *really* should not be here. |
109 | | // X86_64 always has SSE2. |
110 | 126k | if (getTriple().getArch() == llvm::Triple::x86_64) |
111 | 111k | setFeatureEnabled(Features, "sse2", true); |
112 | | |
113 | 126k | using namespace llvm::X86; |
114 | | |
115 | 126k | SmallVector<StringRef, 16> CPUFeatures; |
116 | 126k | getFeaturesForCPU(CPU, CPUFeatures); |
117 | 126k | for (auto &F : CPUFeatures) |
118 | 501k | setFeatureEnabled(Features, F, true); |
119 | | |
120 | 126k | if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) |
121 | 0 | return false; |
122 | | |
123 | | // Can't do this earlier because we need to be able to explicitly enable |
124 | | // or disable these features and the things that they depend upon. |
125 | | |
126 | | // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. |
127 | 126k | auto I = Features.find("sse4.2"); |
128 | 126k | if (I != Features.end() && I->getValue()40.2k && |
129 | 40.2k | llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) |
130 | 40.2k | Features["popcnt"] = true; |
131 | | |
132 | | // Additionally, if SSE is enabled and mmx is not explicitly disabled, |
133 | | // then enable MMX. |
134 | 126k | I = Features.find("sse"); |
135 | 126k | if (I != Features.end() && I->getValue()121k && |
136 | 121k | llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) |
137 | 121k | Features["mmx"] = true; |
138 | | |
139 | | // Enable xsave if avx is enabled and xsave is not explicitly disabled. |
140 | 126k | I = Features.find("avx"); |
141 | 126k | if (I != Features.end() && I->getValue()40.0k && |
142 | 39.9k | llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) |
143 | 39.9k | Features["xsave"] = true; |
144 | | |
145 | 126k | return true; |
146 | 126k | } |
147 | | |
148 | | void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, |
149 | 731k | StringRef Name, bool Enabled) const { |
150 | 731k | if (Name == "sse4") { |
151 | | // We can get here via the __target__ attribute since that's not controlled |
152 | | // via the -msse4/-mno-sse4 command line alias. Handle this the same way |
153 | | // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if |
154 | | // disabled. |
155 | 4 | if (Enabled) |
156 | 2 | Name = "sse4.2"; |
157 | 2 | else |
158 | 2 | Name = "sse4.1"; |
159 | 4 | } |
160 | | |
161 | 731k | Features[Name] = Enabled; |
162 | 731k | llvm::X86::updateImpliedFeatures(Name, Enabled, Features); |
163 | 731k | } |
164 | | |
165 | | /// handleTargetFeatures - Perform initialization based on the user |
166 | | /// configured set of features. |
167 | | bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, |
168 | 79.5k | DiagnosticsEngine &Diags) { |
169 | 503k | for (const auto &Feature : Features) { |
170 | 503k | if (Feature[0] != '+') |
171 | 976 | continue; |
172 | | |
173 | 502k | if (Feature == "+aes") { |
174 | 95 | HasAES = true; |
175 | 502k | } else if (Feature == "+vaes") { |
176 | 16 | HasVAES = true; |
177 | 502k | } else if (Feature == "+pclmul") { |
178 | 120 | HasPCLMUL = true; |
179 | 502k | } else if (Feature == "+vpclmulqdq") { |
180 | 16 | HasVPCLMULQDQ = true; |
181 | 502k | } else if (Feature == "+lzcnt") { |
182 | 107 | HasLZCNT = true; |
183 | 502k | } else if (Feature == "+rdrnd") { |
184 | 86 | HasRDRND = true; |
185 | 502k | } else if (Feature == "+fsgsbase") { |
186 | 85 | HasFSGSBASE = true; |
187 | 502k | } else if (Feature == "+bmi") { |
188 | 95 | HasBMI = true; |
189 | 501k | } else if (Feature == "+bmi2") { |
190 | 77 | HasBMI2 = true; |
191 | 501k | } else if (Feature == "+popcnt") { |
192 | 308 | HasPOPCNT = true; |
193 | 501k | } else if (Feature == "+rtm") { |
194 | 1 | HasRTM = true; |
195 | 501k | } else if (Feature == "+prfchw") { |
196 | 110 | HasPRFCHW = true; |
197 | 501k | } else if (Feature == "+rdseed") { |
198 | 72 | HasRDSEED = true; |
199 | 501k | } else if (Feature == "+adx") { |
200 | 66 | HasADX = true; |
201 | 501k | } else if (Feature == "+tbm") { |
202 | 11 | HasTBM = true; |
203 | 501k | } else if (Feature == "+lwp") { |
204 | 15 | HasLWP = true; |
205 | 501k | } else if (Feature == "+fma") { |
206 | 183 | HasFMA = true; |
207 | 501k | } else if (Feature == "+f16c") { |
208 | 196 | HasF16C = true; |
209 | 500k | } else if (Feature == "+gfni") { |
210 | 16 | HasGFNI = true; |
211 | 500k | } else if (Feature == "+avx512cd") { |
212 | 46 | HasAVX512CD = true; |
213 | 500k | } else if (Feature == "+avx512vpopcntdq") { |
214 | 15 | HasAVX512VPOPCNTDQ = true; |
215 | 500k | } else if (Feature == "+avx512vnni") { |
216 | 17 | HasAVX512VNNI = true; |
217 | 500k | } else if (Feature == "+avx512bf16") { |
218 | 8 | HasAVX512BF16 = true; |
219 | 500k | } else if (Feature == "+avx512er") { |
220 | 12 | HasAVX512ER = true; |
221 | 500k | } else if (Feature == "+avx512pf") { |
222 | 11 | HasAVX512PF = true; |
223 | 500k | } else if (Feature == "+avx512dq") { |
224 | 37 | HasAVX512DQ = true; |
225 | 500k | } else if (Feature == "+avx512bitalg") { |
226 | 13 | HasAVX512BITALG = true; |
227 | 500k | } else if (Feature == "+avx512bw") { |
228 | 53 | HasAVX512BW = true; |
229 | 500k | } else if (Feature == "+avx512vl") { |
230 | 58 | HasAVX512VL = true; |
231 | 500k | } else if (Feature == "+avx512vbmi") { |
232 | 16 | HasAVX512VBMI = true; |
233 | 500k | } else if (Feature == "+avx512vbmi2") { |
234 | 13 | HasAVX512VBMI2 = true; |
235 | 500k | } else if (Feature == "+avx512ifma") { |
236 | 16 | HasAVX512IFMA = true; |
237 | 500k | } else if (Feature == "+avx512vp2intersect") { |
238 | 9 | HasAVX512VP2INTERSECT = true; |
239 | 500k | } else if (Feature == "+sha") { |
240 | 30 | HasSHA = true; |
241 | 500k | } else if (Feature == "+shstk") { |
242 | 10 | HasSHSTK = true; |
243 | 500k | } else if (Feature == "+movbe") { |
244 | 156 | HasMOVBE = true; |
245 | 500k | } else if (Feature == "+sgx") { |
246 | 25 | HasSGX = true; |
247 | 500k | } else if (Feature == "+cx8") { |
248 | 79.4k | HasCX8 = true; |
249 | 420k | } else if (Feature == "+cx16") { |
250 | 16.0k | HasCX16 = true; |
251 | 404k | } else if (Feature == "+fxsr") { |
252 | 33.7k | HasFXSR = true; |
253 | 371k | } else if (Feature == "+xsave") { |
254 | 300 | HasXSAVE = true; |
255 | 370k | } else if (Feature == "+xsaveopt") { |
256 | 113 | HasXSAVEOPT = true; |
257 | 370k | } else if (Feature == "+xsavec") { |
258 | 63 | HasXSAVEC = true; |
259 | 370k | } else if (Feature == "+xsaves") { |
260 | 63 | HasXSAVES = true; |
261 | 370k | } else if (Feature == "+mwaitx") { |
262 | 16 | HasMWAITX = true; |
263 | 370k | } else if (Feature == "+pku") { |
264 | 37 | HasPKU = true; |
265 | 370k | } else if (Feature == "+clflushopt") { |
266 | 57 | HasCLFLUSHOPT = true; |
267 | 370k | } else if (Feature == "+clwb") { |
268 | 39 | HasCLWB = true; |
269 | 370k | } else if (Feature == "+wbnoinvd") { |
270 | 15 | HasWBNOINVD = true; |
271 | 370k | } else if (Feature == "+prefetchwt1") { |
272 | 11 | HasPREFETCHWT1 = true; |
273 | 370k | } else if (Feature == "+clzero") { |
274 | 14 | HasCLZERO = true; |
275 | 370k | } else if (Feature == "+cldemote") { |
276 | 9 | HasCLDEMOTE = true; |
277 | 370k | } else if (Feature == "+rdpid") { |
278 | 22 | HasRDPID = true; |
279 | 370k | } else if (Feature == "+kl") { |
280 | 8 | HasKL = true; |
281 | 370k | } else if (Feature == "+widekl") { |
282 | 7 | HasWIDEKL = true; |
283 | 370k | } else if (Feature == "+retpoline-external-thunk") { |
284 | 0 | HasRetpolineExternalThunk = true; |
285 | 370k | } else if (Feature == "+sahf") { |
286 | 16.0k | HasLAHFSAHF = true; |
287 | 354k | } else if (Feature == "+waitpkg") { |
288 | 6 | HasWAITPKG = true; |
289 | 354k | } else if (Feature == "+movdiri") { |
290 | 9 | HasMOVDIRI = true; |
291 | 354k | } else if (Feature == "+movdir64b") { |
292 | 9 | HasMOVDIR64B = true; |
293 | 354k | } else if (Feature == "+pconfig") { |
294 | 7 | HasPCONFIG = true; |
295 | 354k | } else if (Feature == "+ptwrite") { |
296 | 10 | HasPTWRITE = true; |
297 | 354k | } else if (Feature == "+invpcid") { |
298 | 65 | HasINVPCID = true; |
299 | 354k | } else if (Feature == "+enqcmd") { |
300 | 5 | HasENQCMD = true; |
301 | 354k | } else if (Feature == "+hreset") { |
302 | 5 | HasHRESET = true; |
303 | 354k | } else if (Feature == "+amx-bf16") { |
304 | 7 | HasAMXBF16 = true; |
305 | 354k | } else if (Feature == "+amx-int8") { |
306 | 7 | HasAMXINT8 = true; |
307 | 354k | } else if (Feature == "+amx-tile") { |
308 | 9 | HasAMXTILE = true; |
309 | 354k | } else if (Feature == "+avxvnni") { |
310 | 6 | HasAVXVNNI = true; |
311 | 354k | } else if (Feature == "+serialize") { |
312 | 7 | HasSERIALIZE = true; |
313 | 354k | } else if (Feature == "+tsxldtrk") { |
314 | 5 | HasTSXLDTRK = true; |
315 | 354k | } else if (Feature == "+uintr") { |
316 | 4 | HasUINTR = true; |
317 | 4 | } |
318 | | |
319 | 502k | X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) |
320 | 502k | .Case("+avx512f", AVX512F) |
321 | 502k | .Case("+avx2", AVX2) |
322 | 502k | .Case("+avx", AVX) |
323 | 502k | .Case("+sse4.2", SSE42) |
324 | 502k | .Case("+sse4.1", SSE41) |
325 | 502k | .Case("+ssse3", SSSE3) |
326 | 502k | .Case("+sse3", SSE3) |
327 | 502k | .Case("+sse2", SSE2) |
328 | 502k | .Case("+sse", SSE1) |
329 | 502k | .Default(NoSSE); |
330 | 502k | SSELevel = std::max(SSELevel, Level); |
331 | | |
332 | 502k | MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) |
333 | 502k | .Case("+3dnowa", AMD3DNowAthlon) |
334 | 502k | .Case("+3dnow", AMD3DNow) |
335 | 502k | .Case("+mmx", MMX) |
336 | 502k | .Default(NoMMX3DNow); |
337 | 502k | MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); |
338 | | |
339 | 502k | XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) |
340 | 502k | .Case("+xop", XOP) |
341 | 502k | .Case("+fma4", FMA4) |
342 | 502k | .Case("+sse4a", SSE4A) |
343 | 502k | .Default(NoXOP); |
344 | 502k | XOPLevel = std::max(XOPLevel, XLevel); |
345 | 502k | } |
346 | | |
347 | | // LLVM doesn't have a separate switch for fpmath, so only accept it if it |
348 | | // matches the selected sse level. |
349 | 79.5k | if ((FPMath == FP_SSE && SSELevel < SSE12 ) || |
350 | 79.5k | (FPMath == FP_387 && SSELevel >= SSE12 )) { |
351 | 2 | Diags.Report(diag::err_target_unsupported_fpmath) |
352 | 1 | << (FPMath == FP_SSE ? "sse" : "387"); |
353 | 2 | return false; |
354 | 2 | } |
355 | | |
356 | 79.5k | SimdDefaultAlign = |
357 | 79.3k | hasFeature("avx512f") ? 512140 : hasFeature("avx") ? 256126 : 12879.2k ; |
358 | 79.5k | return true; |
359 | 79.5k | } |
360 | | |
361 | | /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro |
362 | | /// definitions for this particular subtarget. |
363 | | void X86TargetInfo::getTargetDefines(const LangOptions &Opts, |
364 | 71.8k | MacroBuilder &Builder) const { |
365 | | // Inline assembly supports X86 flag outputs. |
366 | 71.8k | Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); |
367 | | |
368 | 71.8k | std::string CodeModel = getTargetOpts().CodeModel; |
369 | 71.8k | if (CodeModel == "default") |
370 | 58.4k | CodeModel = "small"; |
371 | 71.8k | Builder.defineMacro("__code_model_" + CodeModel + "__"); |
372 | | |
373 | | // Target identification. |
374 | 71.8k | if (getTriple().getArch() == llvm::Triple::x86_64) { |
375 | 57.9k | Builder.defineMacro("__amd64__"); |
376 | 57.9k | Builder.defineMacro("__amd64"); |
377 | 57.9k | Builder.defineMacro("__x86_64"); |
378 | 57.9k | Builder.defineMacro("__x86_64__"); |
379 | 57.9k | if (getTriple().getArchName() == "x86_64h") { |
380 | 2 | Builder.defineMacro("__x86_64h"); |
381 | 2 | Builder.defineMacro("__x86_64h__"); |
382 | 2 | } |
383 | 13.9k | } else { |
384 | 13.9k | DefineStd(Builder, "i386", Opts); |
385 | 13.9k | } |
386 | | |
387 | 71.8k | Builder.defineMacro("__SEG_GS"); |
388 | 71.8k | Builder.defineMacro("__SEG_FS"); |
389 | 71.8k | Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); |
390 | 71.8k | Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); |
391 | | |
392 | | // Subtarget options. |
393 | | // FIXME: We are hard-coding the tune parameters based on the CPU, but they |
394 | | // truly should be based on -mtune options. |
395 | 71.8k | using namespace llvm::X86; |
396 | 71.8k | switch (CPU) { |
397 | 38.0k | case CK_None: |
398 | 38.0k | break; |
399 | 29 | case CK_i386: |
400 | | // The rest are coming from the i386 define above. |
401 | 29 | Builder.defineMacro("__tune_i386__"); |
402 | 29 | break; |
403 | 5 | case CK_i486: |
404 | 6 | case CK_WinChipC6: |
405 | 7 | case CK_WinChip2: |
406 | 8 | case CK_C3: |
407 | 8 | defineCPUMacros(Builder, "i486"); |
408 | 8 | break; |
409 | 1 | case CK_PentiumMMX: |
410 | 1 | Builder.defineMacro("__pentium_mmx__"); |
411 | 1 | Builder.defineMacro("__tune_pentium_mmx__"); |
412 | 1 | LLVM_FALLTHROUGH; |
413 | 3 | case CK_i586: |
414 | 7 | case CK_Pentium: |
415 | 7 | defineCPUMacros(Builder, "i586"); |
416 | 7 | defineCPUMacros(Builder, "pentium"); |
417 | 7 | break; |
418 | 4 | case CK_Pentium3: |
419 | 8 | case CK_PentiumM: |
420 | 8 | Builder.defineMacro("__tune_pentium3__"); |
421 | 8 | LLVM_FALLTHROUGH; |
422 | 9 | case CK_Pentium2: |
423 | 10 | case CK_C3_2: |
424 | 10 | Builder.defineMacro("__tune_pentium2__"); |
425 | 10 | LLVM_FALLTHROUGH; |
426 | 20 | case CK_PentiumPro: |
427 | 27 | case CK_i686: |
428 | 27 | defineCPUMacros(Builder, "i686"); |
429 | 27 | defineCPUMacros(Builder, "pentiumpro"); |
430 | 27 | break; |
431 | 9.29k | case CK_Pentium4: |
432 | 9.29k | defineCPUMacros(Builder, "pentium4"); |
433 | 9.29k | break; |
434 | 9 | case CK_Yonah: |
435 | 10 | case CK_Prescott: |
436 | 13 | case CK_Nocona: |
437 | 13 | defineCPUMacros(Builder, "nocona"); |
438 | 13 | break; |
439 | 144 | case CK_Core2: |
440 | 15.7k | case CK_Penryn: |
441 | 15.7k | defineCPUMacros(Builder, "core2"); |
442 | 15.7k | break; |
443 | 57 | case CK_Bonnell: |
444 | 57 | defineCPUMacros(Builder, "atom"); |
445 | 57 | break; |
446 | 4 | case CK_Silvermont: |
447 | 4 | defineCPUMacros(Builder, "slm"); |
448 | 4 | break; |
449 | 2 | case CK_Goldmont: |
450 | 2 | defineCPUMacros(Builder, "goldmont"); |
451 | 2 | break; |
452 | 2 | case CK_GoldmontPlus: |
453 | 2 | defineCPUMacros(Builder, "goldmont_plus"); |
454 | 2 | break; |
455 | 2 | case CK_Tremont: |
456 | 2 | defineCPUMacros(Builder, "tremont"); |
457 | 2 | break; |
458 | 7 | case CK_Nehalem: |
459 | 8 | case CK_Westmere: |
460 | 16 | case CK_SandyBridge: |
461 | 19 | case CK_IvyBridge: |
462 | 25 | case CK_Haswell: |
463 | 29 | case CK_Broadwell: |
464 | 33 | case CK_SkylakeClient: |
465 | 49 | case CK_SkylakeServer: |
466 | 51 | case CK_Cascadelake: |
467 | 53 | case CK_Cooperlake: |
468 | 56 | case CK_Cannonlake: |
469 | 59 | case CK_IcelakeClient: |
470 | 62 | case CK_IcelakeServer: |
471 | 64 | case CK_Tigerlake: |
472 | 66 | case CK_SapphireRapids: |
473 | 68 | case CK_Alderlake: |
474 | | // FIXME: Historically, we defined this legacy name, it would be nice to |
475 | | // remove it at some point. We've never exposed fine-grained names for |
476 | | // recent primary x86 CPUs, and we should keep it that way. |
477 | 68 | defineCPUMacros(Builder, "corei7"); |
478 | 68 | break; |
479 | 8 | case CK_KNL: |
480 | 8 | defineCPUMacros(Builder, "knl"); |
481 | 8 | break; |
482 | 3 | case CK_KNM: |
483 | 3 | break; |
484 | 1 | case CK_Lakemont: |
485 | 1 | defineCPUMacros(Builder, "i586", /*Tuning*/false); |
486 | 1 | defineCPUMacros(Builder, "pentium", /*Tuning*/false); |
487 | 1 | Builder.defineMacro("__tune_lakemont__"); |
488 | 1 | break; |
489 | 1 | case CK_K6_2: |
490 | 1 | Builder.defineMacro("__k6_2__"); |
491 | 1 | Builder.defineMacro("__tune_k6_2__"); |
492 | 1 | LLVM_FALLTHROUGH; |
493 | 2 | case CK_K6_3: |
494 | 2 | if (CPU != CK_K6_2) { // In case of fallthrough |
495 | | // FIXME: GCC may be enabling these in cases where some other k6 |
496 | | // architecture is specified but -m3dnow is explicitly provided. The |
497 | | // exact semantics need to be determined and emulated here. |
498 | 1 | Builder.defineMacro("__k6_3__"); |
499 | 1 | Builder.defineMacro("__tune_k6_3__"); |
500 | 1 | } |
501 | 2 | LLVM_FALLTHROUGH; |
502 | 3 | case CK_K6: |
503 | 3 | defineCPUMacros(Builder, "k6"); |
504 | 3 | break; |
505 | 2 | case CK_Athlon: |
506 | 5 | case CK_AthlonXP: |
507 | 5 | defineCPUMacros(Builder, "athlon"); |
508 | 5 | if (SSELevel != NoSSE) { |
509 | 3 | Builder.defineMacro("__athlon_sse__"); |
510 | 3 | Builder.defineMacro("__tune_athlon_sse__"); |
511 | 3 | } |
512 | 5 | break; |
513 | 12 | case CK_K8: |
514 | 21 | case CK_K8SSE3: |
515 | 8.38k | case CK_x86_64: |
516 | 8.38k | case CK_x86_64_v2: |
517 | 8.38k | case CK_x86_64_v3: |
518 | 8.38k | case CK_x86_64_v4: |
519 | 8.38k | defineCPUMacros(Builder, "k8"); |
520 | 8.38k | break; |
521 | 4 | case CK_AMDFAM10: |
522 | 4 | defineCPUMacros(Builder, "amdfam10"); |
523 | 4 | break; |
524 | 4 | case CK_BTVER1: |
525 | 4 | defineCPUMacros(Builder, "btver1"); |
526 | 4 | break; |
527 | 10 | case CK_BTVER2: |
528 | 10 | defineCPUMacros(Builder, "btver2"); |
529 | 10 | break; |
530 | 4 | case CK_BDVER1: |
531 | 4 | defineCPUMacros(Builder, "bdver1"); |
532 | 4 | break; |
533 | 4 | case CK_BDVER2: |
534 | 4 | defineCPUMacros(Builder, "bdver2"); |
535 | 4 | break; |
536 | 3 | case CK_BDVER3: |
537 | 3 | defineCPUMacros(Builder, "bdver3"); |
538 | 3 | break; |
539 | 3 | case CK_BDVER4: |
540 | 3 | defineCPUMacros(Builder, "bdver4"); |
541 | 3 | break; |
542 | 4 | case CK_ZNVER1: |
543 | 4 | defineCPUMacros(Builder, "znver1"); |
544 | 4 | break; |
545 | 3 | case CK_ZNVER2: |
546 | 3 | defineCPUMacros(Builder, "znver2"); |
547 | 3 | break; |
548 | 3 | case CK_ZNVER3: |
549 | 3 | defineCPUMacros(Builder, "znver3"); |
550 | 3 | break; |
551 | 1 | case CK_Geode: |
552 | 1 | defineCPUMacros(Builder, "geode"); |
553 | 1 | break; |
554 | 71.8k | } |
555 | | |
556 | | // Target properties. |
557 | 71.8k | Builder.defineMacro("__REGISTER_PREFIX__", ""); |
558 | | |
559 | | // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline |
560 | | // functions in glibc header files that use FP Stack inline asm which the |
561 | | // backend can't deal with (PR879). |
562 | 71.8k | Builder.defineMacro("__NO_MATH_INLINES"); |
563 | | |
564 | 71.8k | if (HasAES) |
565 | 93 | Builder.defineMacro("__AES__"); |
566 | | |
567 | 71.8k | if (HasVAES) |
568 | 16 | Builder.defineMacro("__VAES__"); |
569 | | |
570 | 71.8k | if (HasPCLMUL) |
571 | 118 | Builder.defineMacro("__PCLMUL__"); |
572 | | |
573 | 71.8k | if (HasVPCLMULQDQ) |
574 | 16 | Builder.defineMacro("__VPCLMULQDQ__"); |
575 | | |
576 | | // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, |
577 | | // the feature flag only applies to 64-bit mode. |
578 | 71.8k | if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x8655.8k ) |
579 | 29.7k | Builder.defineMacro("__LAHF_SAHF__"); |
580 | | |
581 | 71.8k | if (HasLZCNT) |
582 | 105 | Builder.defineMacro("__LZCNT__"); |
583 | | |
584 | 71.8k | if (HasRDRND) |
585 | 86 | Builder.defineMacro("__RDRND__"); |
586 | | |
587 | 71.8k | if (HasFSGSBASE) |
588 | 85 | Builder.defineMacro("__FSGSBASE__"); |
589 | | |
590 | 71.8k | if (HasBMI) |
591 | 93 | Builder.defineMacro("__BMI__"); |
592 | | |
593 | 71.8k | if (HasBMI2) |
594 | 77 | Builder.defineMacro("__BMI2__"); |
595 | | |
596 | 71.8k | if (HasPOPCNT) |
597 | 306 | Builder.defineMacro("__POPCNT__"); |
598 | | |
599 | 71.8k | if (HasRTM) |
600 | 1 | Builder.defineMacro("__RTM__"); |
601 | | |
602 | 71.8k | if (HasPRFCHW) |
603 | 108 | Builder.defineMacro("__PRFCHW__"); |
604 | | |
605 | 71.8k | if (HasRDSEED) |
606 | 72 | Builder.defineMacro("__RDSEED__"); |
607 | | |
608 | 71.8k | if (HasADX) |
609 | 66 | Builder.defineMacro("__ADX__"); |
610 | | |
611 | 71.8k | if (HasTBM) |
612 | 11 | Builder.defineMacro("__TBM__"); |
613 | | |
614 | 71.8k | if (HasLWP) |
615 | 15 | Builder.defineMacro("__LWP__"); |
616 | | |
617 | 71.8k | if (HasMWAITX) |
618 | 16 | Builder.defineMacro("__MWAITX__"); |
619 | | |
620 | 71.8k | if (HasMOVBE) |
621 | 154 | Builder.defineMacro("__MOVBE__"); |
622 | | |
623 | 71.8k | switch (XOPLevel) { |
624 | 18 | case XOP: |
625 | 18 | Builder.defineMacro("__XOP__"); |
626 | 18 | LLVM_FALLTHROUGH; |
627 | 19 | case FMA4: |
628 | 19 | Builder.defineMacro("__FMA4__"); |
629 | 19 | LLVM_FALLTHROUGH; |
630 | 47 | case SSE4A: |
631 | 47 | Builder.defineMacro("__SSE4A__"); |
632 | 47 | LLVM_FALLTHROUGH; |
633 | 71.8k | case NoXOP: |
634 | 71.8k | break; |
635 | 71.8k | } |
636 | | |
637 | 71.8k | if (HasFMA) |
638 | 183 | Builder.defineMacro("__FMA__"); |
639 | | |
640 | 71.8k | if (HasF16C) |
641 | 194 | Builder.defineMacro("__F16C__"); |
642 | | |
643 | 71.8k | if (HasGFNI) |
644 | 16 | Builder.defineMacro("__GFNI__"); |
645 | | |
646 | 71.8k | if (HasAVX512CD) |
647 | 46 | Builder.defineMacro("__AVX512CD__"); |
648 | 71.8k | if (HasAVX512VPOPCNTDQ) |
649 | 15 | Builder.defineMacro("__AVX512VPOPCNTDQ__"); |
650 | 71.8k | if (HasAVX512VNNI) |
651 | 17 | Builder.defineMacro("__AVX512VNNI__"); |
652 | 71.8k | if (HasAVX512BF16) |
653 | 8 | Builder.defineMacro("__AVX512BF16__"); |
654 | 71.8k | if (HasAVX512ER) |
655 | 12 | Builder.defineMacro("__AVX512ER__"); |
656 | 71.8k | if (HasAVX512PF) |
657 | 11 | Builder.defineMacro("__AVX512PF__"); |
658 | 71.8k | if (HasAVX512DQ) |
659 | 37 | Builder.defineMacro("__AVX512DQ__"); |
660 | 71.8k | if (HasAVX512BITALG) |
661 | 13 | Builder.defineMacro("__AVX512BITALG__"); |
662 | 71.8k | if (HasAVX512BW) |
663 | 53 | Builder.defineMacro("__AVX512BW__"); |
664 | 71.8k | if (HasAVX512VL) |
665 | 58 | Builder.defineMacro("__AVX512VL__"); |
666 | 71.8k | if (HasAVX512VBMI) |
667 | 16 | Builder.defineMacro("__AVX512VBMI__"); |
668 | 71.8k | if (HasAVX512VBMI2) |
669 | 13 | Builder.defineMacro("__AVX512VBMI2__"); |
670 | 71.8k | if (HasAVX512IFMA) |
671 | 16 | Builder.defineMacro("__AVX512IFMA__"); |
672 | 71.8k | if (HasAVX512VP2INTERSECT) |
673 | 9 | Builder.defineMacro("__AVX512VP2INTERSECT__"); |
674 | 71.8k | if (HasSHA) |
675 | 30 | Builder.defineMacro("__SHA__"); |
676 | | |
677 | 71.8k | if (HasFXSR) |
678 | 33.6k | Builder.defineMacro("__FXSR__"); |
679 | 71.8k | if (HasXSAVE) |
680 | 298 | Builder.defineMacro("__XSAVE__"); |
681 | 71.8k | if (HasXSAVEOPT) |
682 | 111 | Builder.defineMacro("__XSAVEOPT__"); |
683 | 71.8k | if (HasXSAVEC) |
684 | 63 | Builder.defineMacro("__XSAVEC__"); |
685 | 71.8k | if (HasXSAVES) |
686 | 63 | Builder.defineMacro("__XSAVES__"); |
687 | 71.8k | if (HasPKU) |
688 | 37 | Builder.defineMacro("__PKU__"); |
689 | 71.8k | if (HasCLFLUSHOPT) |
690 | 57 | Builder.defineMacro("__CLFLUSHOPT__"); |
691 | 71.8k | if (HasCLWB) |
692 | 39 | Builder.defineMacro("__CLWB__"); |
693 | 71.8k | if (HasWBNOINVD) |
694 | 15 | Builder.defineMacro("__WBNOINVD__"); |
695 | 71.8k | if (HasSHSTK) |
696 | 10 | Builder.defineMacro("__SHSTK__"); |
697 | 71.8k | if (HasSGX) |
698 | 25 | Builder.defineMacro("__SGX__"); |
699 | 71.8k | if (HasPREFETCHWT1) |
700 | 11 | Builder.defineMacro("__PREFETCHWT1__"); |
701 | 71.8k | if (HasCLZERO) |
702 | 14 | Builder.defineMacro("__CLZERO__"); |
703 | 71.8k | if (HasKL) |
704 | 8 | Builder.defineMacro("__KL__"); |
705 | 71.8k | if (HasWIDEKL) |
706 | 7 | Builder.defineMacro("__WIDEKL__"); |
707 | 71.8k | if (HasRDPID) |
708 | 22 | Builder.defineMacro("__RDPID__"); |
709 | 71.8k | if (HasCLDEMOTE) |
710 | 9 | Builder.defineMacro("__CLDEMOTE__"); |
711 | 71.8k | if (HasWAITPKG) |
712 | 6 | Builder.defineMacro("__WAITPKG__"); |
713 | 71.8k | if (HasMOVDIRI) |
714 | 9 | Builder.defineMacro("__MOVDIRI__"); |
715 | 71.8k | if (HasMOVDIR64B) |
716 | 9 | Builder.defineMacro("__MOVDIR64B__"); |
717 | 71.8k | if (HasPCONFIG) |
718 | 7 | Builder.defineMacro("__PCONFIG__"); |
719 | 71.8k | if (HasPTWRITE) |
720 | 10 | Builder.defineMacro("__PTWRITE__"); |
721 | 71.8k | if (HasINVPCID) |
722 | 65 | Builder.defineMacro("__INVPCID__"); |
723 | 71.8k | if (HasENQCMD) |
724 | 5 | Builder.defineMacro("__ENQCMD__"); |
725 | 71.8k | if (HasHRESET) |
726 | 5 | Builder.defineMacro("__HRESET__"); |
727 | 71.8k | if (HasAMXTILE) |
728 | 9 | Builder.defineMacro("__AMXTILE__"); |
729 | 71.8k | if (HasAMXINT8) |
730 | 7 | Builder.defineMacro("__AMXINT8__"); |
731 | 71.8k | if (HasAMXBF16) |
732 | 7 | Builder.defineMacro("__AMXBF16__"); |
733 | 71.8k | if (HasAVXVNNI) |
734 | 6 | Builder.defineMacro("__AVXVNNI__"); |
735 | 71.8k | if (HasSERIALIZE) |
736 | 7 | Builder.defineMacro("__SERIALIZE__"); |
737 | 71.8k | if (HasTSXLDTRK) |
738 | 5 | Builder.defineMacro("__TSXLDTRK__"); |
739 | 71.8k | if (HasUINTR) |
740 | 4 | Builder.defineMacro("__UINTR__"); |
741 | | |
742 | | // Each case falls through to the previous one here. |
743 | 71.8k | switch (SSELevel) { |
744 | 140 | case AVX512F: |
745 | 140 | Builder.defineMacro("__AVX512F__"); |
746 | 140 | LLVM_FALLTHROUGH; |
747 | 176 | case AVX2: |
748 | 176 | Builder.defineMacro("__AVX2__"); |
749 | 176 | LLVM_FALLTHROUGH; |
750 | 264 | case AVX: |
751 | 264 | Builder.defineMacro("__AVX__"); |
752 | 264 | LLVM_FALLTHROUGH; |
753 | 291 | case SSE42: |
754 | 291 | Builder.defineMacro("__SSE4_2__"); |
755 | 291 | LLVM_FALLTHROUGH; |
756 | 15.9k | case SSE41: |
757 | 15.9k | Builder.defineMacro("__SSE4_1__"); |
758 | 15.9k | LLVM_FALLTHROUGH; |
759 | 16.1k | case SSSE3: |
760 | 16.1k | Builder.defineMacro("__SSSE3__"); |
761 | 16.1k | LLVM_FALLTHROUGH; |
762 | 16.1k | case SSE3: |
763 | 16.1k | Builder.defineMacro("__SSE3__"); |
764 | 16.1k | LLVM_FALLTHROUGH; |
765 | 67.3k | case SSE2: |
766 | 67.3k | Builder.defineMacro("__SSE2__"); |
767 | 67.3k | Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. |
768 | 67.3k | LLVM_FALLTHROUGH; |
769 | 67.3k | case SSE1: |
770 | 67.3k | Builder.defineMacro("__SSE__"); |
771 | 67.3k | Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. |
772 | 67.3k | LLVM_FALLTHROUGH; |
773 | 71.8k | case NoSSE: |
774 | 71.8k | break; |
775 | 71.8k | } |
776 | | |
777 | 71.8k | if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x8610.4k ) { |
778 | 325 | switch (SSELevel) { |
779 | 2 | case AVX512F: |
780 | 4 | case AVX2: |
781 | 6 | case AVX: |
782 | 6 | case SSE42: |
783 | 6 | case SSE41: |
784 | 6 | case SSSE3: |
785 | 6 | case SSE3: |
786 | 48 | case SSE2: |
787 | 48 | Builder.defineMacro("_M_IX86_FP", Twine(2)); |
788 | 48 | break; |
789 | 2 | case SSE1: |
790 | 2 | Builder.defineMacro("_M_IX86_FP", Twine(1)); |
791 | 2 | break; |
792 | 275 | default: |
793 | 275 | Builder.defineMacro("_M_IX86_FP", Twine(0)); |
794 | 275 | break; |
795 | 71.8k | } |
796 | 71.8k | } |
797 | | |
798 | | // Each case falls through to the previous one here. |
799 | 71.8k | switch (MMX3DNowLevel) { |
800 | 33 | case AMD3DNowAthlon: |
801 | 33 | Builder.defineMacro("__3dNOW_A__"); |
802 | 33 | LLVM_FALLTHROUGH; |
803 | 39 | case AMD3DNow: |
804 | 39 | Builder.defineMacro("__3dNOW__"); |
805 | 39 | LLVM_FALLTHROUGH; |
806 | 67.4k | case MMX: |
807 | 67.4k | Builder.defineMacro("__MMX__"); |
808 | 67.4k | LLVM_FALLTHROUGH; |
809 | 71.8k | case NoMMX3DNow: |
810 | 71.8k | break; |
811 | 71.8k | } |
812 | | |
813 | 71.8k | if (CPU >= CK_i486 || CPU == CK_None38.1k ) { |
814 | 71.8k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); |
815 | 71.8k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); |
816 | 71.8k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); |
817 | 71.8k | } |
818 | 71.8k | if (HasCX8) |
819 | 71.8k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); |
820 | 71.8k | if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_6415.9k ) |
821 | 15.8k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); |
822 | | |
823 | 71.8k | if (HasFloat128) |
824 | 3.47k | Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); |
825 | 71.8k | } |
826 | | |
827 | 1.34M | bool X86TargetInfo::isValidFeatureName(StringRef Name) const { |
828 | 1.34M | return llvm::StringSwitch<bool>(Name) |
829 | 1.34M | .Case("3dnow", true) |
830 | 1.34M | .Case("3dnowa", true) |
831 | 1.34M | .Case("adx", true) |
832 | 1.34M | .Case("aes", true) |
833 | 1.34M | .Case("amx-bf16", true) |
834 | 1.34M | .Case("amx-int8", true) |
835 | 1.34M | .Case("amx-tile", true) |
836 | 1.34M | .Case("avx", true) |
837 | 1.34M | .Case("avx2", true) |
838 | 1.34M | .Case("avx512f", true) |
839 | 1.34M | .Case("avx512cd", true) |
840 | 1.34M | .Case("avx512vpopcntdq", true) |
841 | 1.34M | .Case("avx512vnni", true) |
842 | 1.34M | .Case("avx512bf16", true) |
843 | 1.34M | .Case("avx512er", true) |
844 | 1.34M | .Case("avx512pf", true) |
845 | 1.34M | .Case("avx512dq", true) |
846 | 1.34M | .Case("avx512bitalg", true) |
847 | 1.34M | .Case("avx512bw", true) |
848 | 1.34M | .Case("avx512vl", true) |
849 | 1.34M | .Case("avx512vbmi", true) |
850 | 1.34M | .Case("avx512vbmi2", true) |
851 | 1.34M | .Case("avx512ifma", true) |
852 | 1.34M | .Case("avx512vp2intersect", true) |
853 | 1.34M | .Case("avxvnni", true) |
854 | 1.34M | .Case("bmi", true) |
855 | 1.34M | .Case("bmi2", true) |
856 | 1.34M | .Case("cldemote", true) |
857 | 1.34M | .Case("clflushopt", true) |
858 | 1.34M | .Case("clwb", true) |
859 | 1.34M | .Case("clzero", true) |
860 | 1.34M | .Case("cx16", true) |
861 | 1.34M | .Case("enqcmd", true) |
862 | 1.34M | .Case("f16c", true) |
863 | 1.34M | .Case("fma", true) |
864 | 1.34M | .Case("fma4", true) |
865 | 1.34M | .Case("fsgsbase", true) |
866 | 1.34M | .Case("fxsr", true) |
867 | 1.34M | .Case("gfni", true) |
868 | 1.34M | .Case("hreset", true) |
869 | 1.34M | .Case("invpcid", true) |
870 | 1.34M | .Case("kl", true) |
871 | 1.34M | .Case("widekl", true) |
872 | 1.34M | .Case("lwp", true) |
873 | 1.34M | .Case("lzcnt", true) |
874 | 1.34M | .Case("mmx", true) |
875 | 1.34M | .Case("movbe", true) |
876 | 1.34M | .Case("movdiri", true) |
877 | 1.34M | .Case("movdir64b", true) |
878 | 1.34M | .Case("mwaitx", true) |
879 | 1.34M | .Case("pclmul", true) |
880 | 1.34M | .Case("pconfig", true) |
881 | 1.34M | .Case("pku", true) |
882 | 1.34M | .Case("popcnt", true) |
883 | 1.34M | .Case("prefetchwt1", true) |
884 | 1.34M | .Case("prfchw", true) |
885 | 1.34M | .Case("ptwrite", true) |
886 | 1.34M | .Case("rdpid", true) |
887 | 1.34M | .Case("rdrnd", true) |
888 | 1.34M | .Case("rdseed", true) |
889 | 1.34M | .Case("rtm", true) |
890 | 1.34M | .Case("sahf", true) |
891 | 1.34M | .Case("serialize", true) |
892 | 1.34M | .Case("sgx", true) |
893 | 1.34M | .Case("sha", true) |
894 | 1.34M | .Case("shstk", true) |
895 | 1.34M | .Case("sse", true) |
896 | 1.34M | .Case("sse2", true) |
897 | 1.34M | .Case("sse3", true) |
898 | 1.34M | .Case("ssse3", true) |
899 | 1.34M | .Case("sse4", true) |
900 | 1.34M | .Case("sse4.1", true) |
901 | 1.34M | .Case("sse4.2", true) |
902 | 1.34M | .Case("sse4a", true) |
903 | 1.34M | .Case("tbm", true) |
904 | 1.34M | .Case("tsxldtrk", true) |
905 | 1.34M | .Case("uintr", true) |
906 | 1.34M | .Case("vaes", true) |
907 | 1.34M | .Case("vpclmulqdq", true) |
908 | 1.34M | .Case("wbnoinvd", true) |
909 | 1.34M | .Case("waitpkg", true) |
910 | 1.34M | .Case("x87", true) |
911 | 1.34M | .Case("xop", true) |
912 | 1.34M | .Case("xsave", true) |
913 | 1.34M | .Case("xsavec", true) |
914 | 1.34M | .Case("xsaves", true) |
915 | 1.34M | .Case("xsaveopt", true) |
916 | 1.34M | .Default(false); |
917 | 1.34M | } |
918 | | |
919 | 407k | bool X86TargetInfo::hasFeature(StringRef Feature) const { |
920 | 407k | return llvm::StringSwitch<bool>(Feature) |
921 | 407k | .Case("adx", HasADX) |
922 | 407k | .Case("aes", HasAES) |
923 | 407k | .Case("amx-bf16", HasAMXBF16) |
924 | 407k | .Case("amx-int8", HasAMXINT8) |
925 | 407k | .Case("amx-tile", HasAMXTILE) |
926 | 407k | .Case("avxvnni", HasAVXVNNI) |
927 | 407k | .Case("avx", SSELevel >= AVX) |
928 | 407k | .Case("avx2", SSELevel >= AVX2) |
929 | 407k | .Case("avx512f", SSELevel >= AVX512F) |
930 | 407k | .Case("avx512cd", HasAVX512CD) |
931 | 407k | .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) |
932 | 407k | .Case("avx512vnni", HasAVX512VNNI) |
933 | 407k | .Case("avx512bf16", HasAVX512BF16) |
934 | 407k | .Case("avx512er", HasAVX512ER) |
935 | 407k | .Case("avx512pf", HasAVX512PF) |
936 | 407k | .Case("avx512dq", HasAVX512DQ) |
937 | 407k | .Case("avx512bitalg", HasAVX512BITALG) |
938 | 407k | .Case("avx512bw", HasAVX512BW) |
939 | 407k | .Case("avx512vl", HasAVX512VL) |
940 | 407k | .Case("avx512vbmi", HasAVX512VBMI) |
941 | 407k | .Case("avx512vbmi2", HasAVX512VBMI2) |
942 | 407k | .Case("avx512ifma", HasAVX512IFMA) |
943 | 407k | .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) |
944 | 407k | .Case("bmi", HasBMI) |
945 | 407k | .Case("bmi2", HasBMI2) |
946 | 407k | .Case("cldemote", HasCLDEMOTE) |
947 | 407k | .Case("clflushopt", HasCLFLUSHOPT) |
948 | 407k | .Case("clwb", HasCLWB) |
949 | 407k | .Case("clzero", HasCLZERO) |
950 | 407k | .Case("cx8", HasCX8) |
951 | 407k | .Case("cx16", HasCX16) |
952 | 407k | .Case("enqcmd", HasENQCMD) |
953 | 407k | .Case("f16c", HasF16C) |
954 | 407k | .Case("fma", HasFMA) |
955 | 407k | .Case("fma4", XOPLevel >= FMA4) |
956 | 407k | .Case("fsgsbase", HasFSGSBASE) |
957 | 407k | .Case("fxsr", HasFXSR) |
958 | 407k | .Case("gfni", HasGFNI) |
959 | 407k | .Case("hreset", HasHRESET) |
960 | 407k | .Case("invpcid", HasINVPCID) |
961 | 407k | .Case("kl", HasKL) |
962 | 407k | .Case("widekl", HasWIDEKL) |
963 | 407k | .Case("lwp", HasLWP) |
964 | 407k | .Case("lzcnt", HasLZCNT) |
965 | 407k | .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) |
966 | 407k | .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) |
967 | 407k | .Case("mmx", MMX3DNowLevel >= MMX) |
968 | 407k | .Case("movbe", HasMOVBE) |
969 | 407k | .Case("movdiri", HasMOVDIRI) |
970 | 407k | .Case("movdir64b", HasMOVDIR64B) |
971 | 407k | .Case("mwaitx", HasMWAITX) |
972 | 407k | .Case("pclmul", HasPCLMUL) |
973 | 407k | .Case("pconfig", HasPCONFIG) |
974 | 407k | .Case("pku", HasPKU) |
975 | 407k | .Case("popcnt", HasPOPCNT) |
976 | 407k | .Case("prefetchwt1", HasPREFETCHWT1) |
977 | 407k | .Case("prfchw", HasPRFCHW) |
978 | 407k | .Case("ptwrite", HasPTWRITE) |
979 | 407k | .Case("rdpid", HasRDPID) |
980 | 407k | .Case("rdrnd", HasRDRND) |
981 | 407k | .Case("rdseed", HasRDSEED) |
982 | 407k | .Case("retpoline-external-thunk", HasRetpolineExternalThunk) |
983 | 407k | .Case("rtm", HasRTM) |
984 | 407k | .Case("sahf", HasLAHFSAHF) |
985 | 407k | .Case("serialize", HasSERIALIZE) |
986 | 407k | .Case("sgx", HasSGX) |
987 | 407k | .Case("sha", HasSHA) |
988 | 407k | .Case("shstk", HasSHSTK) |
989 | 407k | .Case("sse", SSELevel >= SSE1) |
990 | 407k | .Case("sse2", SSELevel >= SSE2) |
991 | 407k | .Case("sse3", SSELevel >= SSE3) |
992 | 407k | .Case("ssse3", SSELevel >= SSSE3) |
993 | 407k | .Case("sse4.1", SSELevel >= SSE41) |
994 | 407k | .Case("sse4.2", SSELevel >= SSE42) |
995 | 407k | .Case("sse4a", XOPLevel >= SSE4A) |
996 | 407k | .Case("tbm", HasTBM) |
997 | 407k | .Case("tsxldtrk", HasTSXLDTRK) |
998 | 407k | .Case("uintr", HasUINTR) |
999 | 407k | .Case("vaes", HasVAES) |
1000 | 407k | .Case("vpclmulqdq", HasVPCLMULQDQ) |
1001 | 407k | .Case("wbnoinvd", HasWBNOINVD) |
1002 | 407k | .Case("waitpkg", HasWAITPKG) |
1003 | 407k | .Case("x86", true) |
1004 | 407k | .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) |
1005 | 407k | .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) |
1006 | 407k | .Case("xop", XOPLevel >= XOP) |
1007 | 407k | .Case("xsave", HasXSAVE) |
1008 | 407k | .Case("xsavec", HasXSAVEC) |
1009 | 407k | .Case("xsaves", HasXSAVES) |
1010 | 407k | .Case("xsaveopt", HasXSAVEOPT) |
1011 | 407k | .Default(false); |
1012 | 407k | } |
1013 | | |
1014 | | // We can't use a generic validation scheme for the features accepted here |
1015 | | // versus subtarget features accepted in the target attribute because the |
1016 | | // bitfield structure that's initialized in the runtime only supports the |
1017 | | // below currently rather than the full range of subtarget features. (See |
1018 | | // X86TargetInfo::hasFeature for a somewhat comprehensive list). |
1019 | 730 | bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { |
1020 | 730 | return llvm::StringSwitch<bool>(FeatureStr) |
1021 | 27.7k | #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) |
1022 | 730 | #include "llvm/Support/X86TargetParser.def" |
1023 | 730 | .Default(false); |
1024 | 730 | } |
1025 | | |
1026 | 158 | static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { |
1027 | 158 | return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) |
1028 | 6.00k | #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) |
1029 | 158 | #include "llvm/Support/X86TargetParser.def" |
1030 | 158 | ; |
1031 | | // Note, this function should only be used after ensuring the value is |
1032 | | // correct, so it asserts if the value is out of range. |
1033 | 158 | } |
1034 | | |
1035 | 416 | static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { |
1036 | 416 | enum class FeatPriority { |
1037 | 416 | #define FEATURE(FEAT) FEAT, |
1038 | 416 | #include "clang/Basic/X86Target.def" |
1039 | 416 | }; |
1040 | 416 | switch (Feat) { |
1041 | 0 | #define FEATURE(FEAT) \ |
1042 | 416 | case llvm::X86::FEAT: \ |
1043 | 416 | return static_cast<unsigned>(FeatPriority::FEAT); |
1044 | 0 | #include "clang/Basic/X86Target.def" |
1045 | 0 | default: |
1046 | 0 | llvm_unreachable("No Feature Priority for non-CPUSupports Features"); |
1047 | 416 | } |
1048 | 416 | } |
1049 | | |
1050 | 416 | unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { |
1051 | | // Valid CPUs have a 'key feature' that compares just better than its key |
1052 | | // feature. |
1053 | 416 | using namespace llvm::X86; |
1054 | 416 | CPUKind Kind = parseArchX86(Name); |
1055 | 416 | if (Kind != CK_None) { |
1056 | 258 | ProcessorFeatures KeyFeature = getKeyFeature(Kind); |
1057 | 258 | return (getFeaturePriority(KeyFeature) << 1) + 1; |
1058 | 258 | } |
1059 | | |
1060 | | // Now we know we have a feature, so get its priority and shift it a few so |
1061 | | // that we have sufficient room for the CPUs (above). |
1062 | 158 | return getFeaturePriority(getFeature(Name)) << 1; |
1063 | 158 | } |
1064 | | |
1065 | 163 | bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { |
1066 | 163 | return llvm::StringSwitch<bool>(Name) |
1067 | 4.56k | #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) |
1068 | 978 | #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) |
1069 | 163 | #include "clang/Basic/X86Target.def" |
1070 | 163 | .Default(false); |
1071 | 163 | } |
1072 | | |
1073 | 350 | static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { |
1074 | 350 | return llvm::StringSwitch<StringRef>(Name) |
1075 | 2.10k | #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) |
1076 | 350 | #include "clang/Basic/X86Target.def" |
1077 | 350 | .Default(Name); |
1078 | 350 | } |
1079 | | |
1080 | 250 | char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { |
1081 | 250 | return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) |
1082 | 7.00k | #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) |
1083 | 250 | #include "clang/Basic/X86Target.def" |
1084 | 250 | .Default(0); |
1085 | 250 | } |
1086 | | |
1087 | | void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( |
1088 | 100 | StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { |
1089 | 100 | StringRef WholeList = |
1090 | 100 | llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) |
1091 | 2.80k | #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) |
1092 | 100 | #include "clang/Basic/X86Target.def" |
1093 | 100 | .Default(""); |
1094 | 100 | WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); |
1095 | 100 | } |
1096 | | |
1097 | | // We can't use a generic validation scheme for the cpus accepted here |
1098 | | // versus subtarget cpus accepted in the target attribute because the |
1099 | | // variables intitialized by the runtime only support the below currently |
1100 | | // rather than the full range of cpus. |
1101 | 181 | bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { |
1102 | 181 | return llvm::StringSwitch<bool>(FeatureStr) |
1103 | 362 | #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) |
1104 | 724 | #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) |
1105 | 2.71k | #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) |
1106 | 4.70k | #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) |
1107 | 181 | #include "llvm/Support/X86TargetParser.def" |
1108 | 181 | .Default(false); |
1109 | 181 | } |
1110 | | |
1111 | 87 | static unsigned matchAsmCCConstraint(const char *&Name) { |
1112 | 87 | auto RV = llvm::StringSwitch<unsigned>(Name) |
1113 | 87 | .Case("@cca", 4) |
1114 | 87 | .Case("@ccae", 5) |
1115 | 87 | .Case("@ccb", 4) |
1116 | 87 | .Case("@ccbe", 5) |
1117 | 87 | .Case("@ccc", 4) |
1118 | 87 | .Case("@cce", 4) |
1119 | 87 | .Case("@ccz", 4) |
1120 | 87 | .Case("@ccg", 4) |
1121 | 87 | .Case("@ccge", 5) |
1122 | 87 | .Case("@ccl", 4) |
1123 | 87 | .Case("@ccle", 5) |
1124 | 87 | .Case("@ccna", 5) |
1125 | 87 | .Case("@ccnae", 6) |
1126 | 87 | .Case("@ccnb", 5) |
1127 | 87 | .Case("@ccnbe", 6) |
1128 | 87 | .Case("@ccnc", 5) |
1129 | 87 | .Case("@ccne", 5) |
1130 | 87 | .Case("@ccnz", 5) |
1131 | 87 | .Case("@ccng", 5) |
1132 | 87 | .Case("@ccnge", 6) |
1133 | 87 | .Case("@ccnl", 5) |
1134 | 87 | .Case("@ccnle", 6) |
1135 | 87 | .Case("@ccno", 5) |
1136 | 87 | .Case("@ccnp", 5) |
1137 | 87 | .Case("@ccns", 5) |
1138 | 87 | .Case("@cco", 4) |
1139 | 87 | .Case("@ccp", 4) |
1140 | 87 | .Case("@ccs", 4) |
1141 | 87 | .Default(0); |
1142 | 87 | return RV; |
1143 | 87 | } |
1144 | | |
1145 | | bool X86TargetInfo::validateAsmConstraint( |
1146 | 9.82k | const char *&Name, TargetInfo::ConstraintInfo &Info) const { |
1147 | 9.82k | switch (*Name) { |
1148 | 3 | default: |
1149 | 3 | return false; |
1150 | | // Constant constraints. |
1151 | 9 | case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 |
1152 | | // instructions. |
1153 | 17 | case 'Z': // 32-bit unsigned integer constant for use with zero-extending |
1154 | | // x86_64 instructions. |
1155 | 17 | case 's': |
1156 | 17 | Info.setRequiresImmediate(); |
1157 | 17 | return true; |
1158 | 28 | case 'I': |
1159 | 28 | Info.setRequiresImmediate(0, 31); |
1160 | 28 | return true; |
1161 | 14 | case 'J': |
1162 | 14 | Info.setRequiresImmediate(0, 63); |
1163 | 14 | return true; |
1164 | 14 | case 'K': |
1165 | 14 | Info.setRequiresImmediate(-128, 127); |
1166 | 14 | return true; |
1167 | 30 | case 'L': |
1168 | 30 | Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); |
1169 | 30 | return true; |
1170 | 14 | case 'M': |
1171 | 14 | Info.setRequiresImmediate(0, 3); |
1172 | 14 | return true; |
1173 | 16 | case 'N': |
1174 | 16 | Info.setRequiresImmediate(0, 255); |
1175 | 16 | return true; |
1176 | 6 | case 'O': |
1177 | 6 | Info.setRequiresImmediate(0, 127); |
1178 | 6 | return true; |
1179 | | // Register constraints. |
1180 | 52 | case 'Y': // 'Y' is the first character for several 2-character constraints. |
1181 | | // Shift the pointer to the second character of the constraint. |
1182 | 52 | Name++; |
1183 | 52 | switch (*Name) { |
1184 | 0 | default: |
1185 | 0 | return false; |
1186 | 20 | case 'z': // First SSE register. |
1187 | 26 | case '2': |
1188 | 32 | case 't': // Any SSE register, when SSE2 is enabled. |
1189 | 42 | case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. |
1190 | 44 | case 'm': // Any MMX register, when inter-unit moves enabled. |
1191 | 52 | case 'k': // AVX512 arch mask registers: k1-k7. |
1192 | 52 | Info.setAllowsRegister(); |
1193 | 52 | return true; |
1194 | 0 | } |
1195 | 3 | case 'f': // Any x87 floating point stack register. |
1196 | | // Constraint 'f' cannot be used for output operands. |
1197 | 3 | if (Info.ConstraintStr[0] == '=') |
1198 | 1 | return false; |
1199 | 2 | Info.setAllowsRegister(); |
1200 | 2 | return true; |
1201 | 2.54k | case 'a': // eax. |
1202 | 4.61k | case 'b': // ebx. |
1203 | 6.85k | case 'c': // ecx. |
1204 | 8.96k | case 'd': // edx. |
1205 | 9.05k | case 'S': // esi. |
1206 | 9.18k | case 'D': // edi. |
1207 | 9.20k | case 'A': // edx:eax. |
1208 | 9.22k | case 't': // Top of floating point stack. |
1209 | 9.22k | case 'u': // Second from top of floating point stack. |
1210 | 9.25k | case 'q': // Any register accessible as [r]l: a, b, c, and d. |
1211 | 9.29k | case 'y': // Any MMX register. |
1212 | 9.35k | case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) |
1213 | 9.47k | case 'x': // Any SSE register. |
1214 | 9.50k | case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 |
1215 | | // for intermideate k reg operations). |
1216 | 9.52k | case 'Q': // Any register accessible as [r]h: a, b, c, and d. |
1217 | 9.54k | case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. |
1218 | 9.55k | case 'l': // "Index" registers: any general register that can be used as an |
1219 | | // index in a base+index memory access. |
1220 | 9.55k | Info.setAllowsRegister(); |
1221 | 9.55k | return true; |
1222 | | // Floating point constant constraints. |
1223 | 8 | case 'C': // SSE floating point constant. |
1224 | 16 | case 'G': // x87 floating point constant. |
1225 | 16 | return true; |
1226 | 58 | case '@': |
1227 | | // CC condition changes. |
1228 | 58 | if (auto Len = matchAsmCCConstraint(Name)) { |
1229 | 58 | Name += Len - 1; |
1230 | 58 | Info.setAllowsRegister(); |
1231 | 58 | return true; |
1232 | 58 | } |
1233 | 0 | return false; |
1234 | 9.82k | } |
1235 | 9.82k | } |
1236 | | |
1237 | | // Below is based on the following information: |
1238 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1239 | | // | Processor Name | Cache Line Size (Bytes) | Source | |
1240 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1241 | | // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | |
1242 | | // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | |
1243 | | // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | |
1244 | | // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | |
1245 | | // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | |
1246 | | // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | |
1247 | | // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | |
1248 | | // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | |
1249 | | // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | |
1250 | | // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | |
1251 | | // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | |
1252 | | // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | |
1253 | | // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | |
1254 | | // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | |
1255 | | // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | |
1256 | | // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | |
1257 | | // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | |
1258 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1259 | 0 | Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { |
1260 | 0 | using namespace llvm::X86; |
1261 | 0 | switch (CPU) { |
1262 | | // i386 |
1263 | 0 | case CK_i386: |
1264 | | // i486 |
1265 | 0 | case CK_i486: |
1266 | 0 | case CK_WinChipC6: |
1267 | 0 | case CK_WinChip2: |
1268 | 0 | case CK_C3: |
1269 | | // Lakemont |
1270 | 0 | case CK_Lakemont: |
1271 | 0 | return 16; |
1272 | | |
1273 | | // i586 |
1274 | 0 | case CK_i586: |
1275 | 0 | case CK_Pentium: |
1276 | 0 | case CK_PentiumMMX: |
1277 | | // i686 |
1278 | 0 | case CK_PentiumPro: |
1279 | 0 | case CK_i686: |
1280 | 0 | case CK_Pentium2: |
1281 | 0 | case CK_Pentium3: |
1282 | 0 | case CK_PentiumM: |
1283 | 0 | case CK_C3_2: |
1284 | | // K6 |
1285 | 0 | case CK_K6: |
1286 | 0 | case CK_K6_2: |
1287 | 0 | case CK_K6_3: |
1288 | | // Geode |
1289 | 0 | case CK_Geode: |
1290 | 0 | return 32; |
1291 | | |
1292 | | // Netburst |
1293 | 0 | case CK_Pentium4: |
1294 | 0 | case CK_Prescott: |
1295 | 0 | case CK_Nocona: |
1296 | | // Atom |
1297 | 0 | case CK_Bonnell: |
1298 | 0 | case CK_Silvermont: |
1299 | 0 | case CK_Goldmont: |
1300 | 0 | case CK_GoldmontPlus: |
1301 | 0 | case CK_Tremont: |
1302 | |
|
1303 | 0 | case CK_Westmere: |
1304 | 0 | case CK_SandyBridge: |
1305 | 0 | case CK_IvyBridge: |
1306 | 0 | case CK_Haswell: |
1307 | 0 | case CK_Broadwell: |
1308 | 0 | case CK_SkylakeClient: |
1309 | 0 | case CK_SkylakeServer: |
1310 | 0 | case CK_Cascadelake: |
1311 | 0 | case CK_Nehalem: |
1312 | 0 | case CK_Cooperlake: |
1313 | 0 | case CK_Cannonlake: |
1314 | 0 | case CK_Tigerlake: |
1315 | 0 | case CK_SapphireRapids: |
1316 | 0 | case CK_IcelakeClient: |
1317 | 0 | case CK_IcelakeServer: |
1318 | 0 | case CK_Alderlake: |
1319 | 0 | case CK_KNL: |
1320 | 0 | case CK_KNM: |
1321 | | // K7 |
1322 | 0 | case CK_Athlon: |
1323 | 0 | case CK_AthlonXP: |
1324 | | // K8 |
1325 | 0 | case CK_K8: |
1326 | 0 | case CK_K8SSE3: |
1327 | 0 | case CK_AMDFAM10: |
1328 | | // Bobcat |
1329 | 0 | case CK_BTVER1: |
1330 | 0 | case CK_BTVER2: |
1331 | | // Bulldozer |
1332 | 0 | case CK_BDVER1: |
1333 | 0 | case CK_BDVER2: |
1334 | 0 | case CK_BDVER3: |
1335 | 0 | case CK_BDVER4: |
1336 | | // Zen |
1337 | 0 | case CK_ZNVER1: |
1338 | 0 | case CK_ZNVER2: |
1339 | 0 | case CK_ZNVER3: |
1340 | | // Deprecated |
1341 | 0 | case CK_x86_64: |
1342 | 0 | case CK_x86_64_v2: |
1343 | 0 | case CK_x86_64_v3: |
1344 | 0 | case CK_x86_64_v4: |
1345 | 0 | case CK_Yonah: |
1346 | 0 | case CK_Penryn: |
1347 | 0 | case CK_Core2: |
1348 | 0 | return 64; |
1349 | | |
1350 | | // The following currently have unknown cache line sizes (but they are probably all 64): |
1351 | | // Core |
1352 | 0 | case CK_None: |
1353 | 0 | return None; |
1354 | 0 | } |
1355 | 0 | llvm_unreachable("Unknown CPU kind"); |
1356 | 0 | } |
1357 | | |
1358 | | bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, |
1359 | | StringRef Constraint, |
1360 | 5.30k | unsigned Size) const { |
1361 | | // Strip off constraint modifiers. |
1362 | 10.6k | while (Constraint[0] == '=' || Constraint[0] == '+'5.77k || Constraint[0] == '&'5.31k ) |
1363 | 5.31k | Constraint = Constraint.substr(1); |
1364 | | |
1365 | 5.30k | return validateOperandSize(FeatureMap, Constraint, Size); |
1366 | 5.30k | } |
1367 | | |
1368 | | bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, |
1369 | | StringRef Constraint, |
1370 | 5.58k | unsigned Size) const { |
1371 | 5.58k | return validateOperandSize(FeatureMap, Constraint, Size); |
1372 | 5.58k | } |
1373 | | |
1374 | | bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, |
1375 | | StringRef Constraint, |
1376 | 8.99k | unsigned Size) const { |
1377 | 8.99k | switch (Constraint[0]) { |
1378 | 8.81k | default: |
1379 | 8.81k | break; |
1380 | 12 | case 'k': |
1381 | | // Registers k0-k7 (AVX512) size limit is 64 bit. |
1382 | 30 | case 'y': |
1383 | 30 | return Size <= 64; |
1384 | 2 | case 'f': |
1385 | 13 | case 't': |
1386 | 18 | case 'u': |
1387 | 18 | return Size <= 128; |
1388 | 26 | case 'Y': |
1389 | | // 'Y' is the first character for several 2-character constraints. |
1390 | 26 | switch (Constraint[1]) { |
1391 | 0 | default: |
1392 | 0 | return false; |
1393 | 1 | case 'm': |
1394 | | // 'Ym' is synonymous with 'y'. |
1395 | 5 | case 'k': |
1396 | 5 | return Size <= 64; |
1397 | 10 | case 'z': |
1398 | | // XMM0/YMM/ZMM0 |
1399 | 10 | if (FeatureMap.lookup("avx512f")) |
1400 | | // ZMM0 can be used if target supports AVX512F. |
1401 | 7 | return Size <= 512U; |
1402 | 3 | else if (FeatureMap.lookup("avx")) |
1403 | | // YMM0 can be used if target supports AVX. |
1404 | 2 | return Size <= 256U; |
1405 | 1 | else if (FeatureMap.lookup("sse")) |
1406 | 1 | return Size <= 128U; |
1407 | 0 | return false; |
1408 | 5 | case 'i': |
1409 | 8 | case 't': |
1410 | 11 | case '2': |
1411 | | // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. |
1412 | 11 | if (SSELevel < SSE2) |
1413 | 0 | return false; |
1414 | 11 | break; |
1415 | 11 | } |
1416 | 11 | break; |
1417 | 30 | case 'v': |
1418 | 107 | case 'x': |
1419 | 107 | if (FeatureMap.lookup("avx512f")) |
1420 | | // 512-bit zmm registers can be used if target supports AVX512F. |
1421 | 46 | return Size <= 512U; |
1422 | 61 | else if (FeatureMap.lookup("avx")) |
1423 | | // 256-bit ymm registers can be used if target supports AVX. |
1424 | 27 | return Size <= 256U; |
1425 | 34 | return Size <= 128U; |
1426 | | |
1427 | 8.82k | } |
1428 | | |
1429 | 8.82k | return true; |
1430 | 8.82k | } |
1431 | | |
1432 | 1.75k | std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { |
1433 | 1.75k | switch (*Constraint) { |
1434 | 29 | case '@': |
1435 | 29 | if (auto Len = matchAsmCCConstraint(Constraint)) { |
1436 | 29 | std::string Converted = "{" + std::string(Constraint, Len) + "}"; |
1437 | 29 | Constraint += Len - 1; |
1438 | 29 | return Converted; |
1439 | 29 | } |
1440 | 0 | return std::string(1, *Constraint); |
1441 | 84 | case 'a': |
1442 | 84 | return std::string("{ax}"); |
1443 | 42 | case 'b': |
1444 | 42 | return std::string("{bx}"); |
1445 | 73 | case 'c': |
1446 | 73 | return std::string("{cx}"); |
1447 | 40 | case 'd': |
1448 | 40 | return std::string("{dx}"); |
1449 | 31 | case 'S': |
1450 | 31 | return std::string("{si}"); |
1451 | 39 | case 'D': |
1452 | 39 | return std::string("{di}"); |
1453 | 4 | case 'p': // address |
1454 | 4 | return std::string("im"); |
1455 | 5 | case 't': // top of floating point stack. |
1456 | 5 | return std::string("{st}"); |
1457 | 1 | case 'u': // second from top of floating point stack. |
1458 | 1 | return std::string("{st(1)}"); // second from top of floating point stack. |
1459 | 26 | case 'Y': |
1460 | 26 | switch (Constraint[1]) { |
1461 | 0 | default: |
1462 | | // Break from inner switch and fall through (copy single char), |
1463 | | // continue parsing after copying the current constraint into |
1464 | | // the return string. |
1465 | 0 | break; |
1466 | 4 | case 'k': |
1467 | 5 | case 'm': |
1468 | 10 | case 'i': |
1469 | 13 | case 't': |
1470 | 23 | case 'z': |
1471 | 26 | case '2': |
1472 | | // "^" hints llvm that this is a 2 letter constraint. |
1473 | | // "Constraint++" is used to promote the string iterator |
1474 | | // to the next constraint. |
1475 | 26 | return std::string("^") + std::string(Constraint++, 2); |
1476 | 0 | } |
1477 | 0 | LLVM_FALLTHROUGH; |
1478 | 1.38k | default: |
1479 | 1.38k | return std::string(1, *Constraint); |
1480 | 1.75k | } |
1481 | 1.75k | } |
1482 | | |
1483 | 31 | void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { |
1484 | 31 | bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; |
1485 | 31 | llvm::X86::fillValidCPUArchList(Values, Only64Bit); |
1486 | 31 | } |
1487 | | |
1488 | 5 | void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { |
1489 | 5 | llvm::X86::fillValidTuneCPUList(Values); |
1490 | 5 | } |
1491 | | |
1492 | 3.56k | ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { |
1493 | 3.56k | return llvm::makeArrayRef(GCCRegNames); |
1494 | 3.56k | } |
1495 | | |
1496 | 2.97k | ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { |
1497 | 2.97k | return llvm::makeArrayRef(AddlRegNames); |
1498 | 2.97k | } |
1499 | | |
1500 | 13.9k | ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { |
1501 | 13.9k | return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - |
1502 | 13.9k | Builtin::FirstTSBuiltin + 1); |
1503 | 13.9k | } |
1504 | | |
1505 | 58.0k | ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { |
1506 | 58.0k | return llvm::makeArrayRef(BuiltinInfoX86, |
1507 | 58.0k | X86::LastTSBuiltin - Builtin::FirstTSBuiltin); |
1508 | 58.0k | } |