Coverage Report

Created: 2021-08-24 07:12

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
Line
Count
Source (jump to first uncovered line)
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//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/X86TargetParser.h"
21
#include <numeric>
22
23
namespace clang {
24
namespace targets {
25
26
const Builtin::Info BuiltinInfoX86[] = {
27
#define BUILTIN(ID, TYPE, ATTRS)                                               \
28
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
29
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
30
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
31
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
32
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
33
#include "clang/Basic/BuiltinsX86.def"
34
35
#define BUILTIN(ID, TYPE, ATTRS)                                               \
36
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
37
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
38
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
39
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
40
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
41
#include "clang/Basic/BuiltinsX86_64.def"
42
};
43
44
static const char *const GCCRegNames[] = {
45
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
46
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
47
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
48
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
49
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
50
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
51
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
52
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
53
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
54
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
55
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
56
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
57
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
58
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
59
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
60
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
61
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
62
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
63
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
64
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
65
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
66
    "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
67
};
68
69
const TargetInfo::AddlRegName AddlRegNames[] = {
70
    {{"al", "ah", "eax", "rax"}, 0},
71
    {{"bl", "bh", "ebx", "rbx"}, 3},
72
    {{"cl", "ch", "ecx", "rcx"}, 2},
73
    {{"dl", "dh", "edx", "rdx"}, 1},
74
    {{"esi", "rsi"}, 4},
75
    {{"edi", "rdi"}, 5},
76
    {{"esp", "rsp"}, 7},
77
    {{"ebp", "rbp"}, 6},
78
    {{"r8d", "r8w", "r8b"}, 38},
79
    {{"r9d", "r9w", "r9b"}, 39},
80
    {{"r10d", "r10w", "r10b"}, 40},
81
    {{"r11d", "r11w", "r11b"}, 41},
82
    {{"r12d", "r12w", "r12b"}, 42},
83
    {{"r13d", "r13w", "r13b"}, 43},
84
    {{"r14d", "r14w", "r14b"}, 44},
85
    {{"r15d", "r15w", "r15b"}, 45},
86
};
87
88
} // namespace targets
89
} // namespace clang
90
91
using namespace clang;
92
using namespace clang::targets;
93
94
5
bool X86TargetInfo::setFPMath(StringRef Name) {
95
5
  if (Name == "387") {
96
2
    FPMath = FP_387;
97
2
    return true;
98
2
  }
99
3
  if (Name == "sse") {
100
2
    FPMath = FP_SSE;
101
2
    return true;
102
2
  }
103
1
  return false;
104
3
}
105
106
bool X86TargetInfo::initFeatureMap(
107
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
108
144k
    const std::vector<std::string> &FeaturesVec) const {
109
  // FIXME: This *really* should not be here.
110
  // X86_64 always has SSE2.
111
144k
  if (getTriple().getArch() == llvm::Triple::x86_64)
112
129k
    setFeatureEnabled(Features, "sse2", true);
113
114
144k
  using namespace llvm::X86;
115
116
144k
  SmallVector<StringRef, 16> CPUFeatures;
117
144k
  getFeaturesForCPU(CPU, CPUFeatures);
118
144k
  for (auto &F : CPUFeatures)
119
538k
    setFeatureEnabled(Features, F, true);
120
121
144k
  std::vector<std::string> UpdatedFeaturesVec;
122
144k
  for (const auto &Feature : FeaturesVec) {
123
    // Expand general-regs-only to -x86, -mmx and -sse
124
129k
    if (Feature == "+general-regs-only") {
125
12
      UpdatedFeaturesVec.push_back("-x87");
126
12
      UpdatedFeaturesVec.push_back("-mmx");
127
12
      UpdatedFeaturesVec.push_back("-sse");
128
12
      continue;
129
12
    }
130
131
129k
    UpdatedFeaturesVec.push_back(Feature);
132
129k
  }
133
134
144k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
135
0
    return false;
136
137
  // Can't do this earlier because we need to be able to explicitly enable
138
  // or disable these features and the things that they depend upon.
139
140
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
141
144k
  auto I = Features.find("sse4.2");
142
144k
  if (I != Features.end() && 
I->getValue()44.2k
&&
143
144k
      
llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end()44.1k
)
144
44.1k
    Features["popcnt"] = true;
145
146
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
147
  // then enable MMX.
148
144k
  I = Features.find("sse");
149
144k
  if (I != Features.end() && 
I->getValue()139k
&&
150
144k
      
llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end()139k
)
151
139k
    Features["mmx"] = true;
152
153
  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
154
144k
  I = Features.find("avx");
155
144k
  if (I != Features.end() && 
I->getValue()44.0k
&&
156
144k
      
llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end()43.9k
)
157
43.9k
    Features["xsave"] = true;
158
159
144k
  return true;
160
144k
}
161
162
void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
163
4.74M
                                      StringRef Name, bool Enabled) const {
164
4.74M
  if (Name == "sse4") {
165
    // We can get here via the __target__ attribute since that's not controlled
166
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
167
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
168
    // disabled.
169
4
    if (Enabled)
170
2
      Name = "sse4.2";
171
2
    else
172
2
      Name = "sse4.1";
173
4
  }
174
175
4.74M
  Features[Name] = Enabled;
176
4.74M
  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
177
4.74M
}
178
179
/// handleTargetFeatures - Perform initialization based on the user
180
/// configured set of features.
181
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
182
93.8k
                                         DiagnosticsEngine &Diags) {
183
579k
  for (const auto &Feature : Features) {
184
579k
    if (Feature[0] != '+')
185
1.25k
      continue;
186
187
578k
    if (Feature == "+aes") {
188
97
      HasAES = true;
189
578k
    } else if (Feature == "+vaes") {
190
20
      HasVAES = true;
191
578k
    } else if (Feature == "+pclmul") {
192
122
      HasPCLMUL = true;
193
577k
    } else if (Feature == "+vpclmulqdq") {
194
20
      HasVPCLMULQDQ = true;
195
577k
    } else if (Feature == "+lzcnt") {
196
109
      HasLZCNT = true;
197
577k
    } else if (Feature == "+rdrnd") {
198
88
      HasRDRND = true;
199
577k
    } else if (Feature == "+fsgsbase") {
200
87
      HasFSGSBASE = true;
201
577k
    } else if (Feature == "+bmi") {
202
97
      HasBMI = true;
203
577k
    } else if (Feature == "+bmi2") {
204
79
      HasBMI2 = true;
205
577k
    } else if (Feature == "+popcnt") {
206
328
      HasPOPCNT = true;
207
577k
    } else if (Feature == "+rtm") {
208
1
      HasRTM = true;
209
577k
    } else if (Feature == "+prfchw") {
210
112
      HasPRFCHW = true;
211
577k
    } else if (Feature == "+rdseed") {
212
74
      HasRDSEED = true;
213
576k
    } else if (Feature == "+adx") {
214
68
      HasADX = true;
215
576k
    } else if (Feature == "+tbm") {
216
11
      HasTBM = true;
217
576k
    } else if (Feature == "+lwp") {
218
15
      HasLWP = true;
219
576k
    } else if (Feature == "+fma") {
220
200
      HasFMA = true;
221
576k
    } else if (Feature == "+f16c") {
222
213
      HasF16C = true;
223
576k
    } else if (Feature == "+gfni") {
224
20
      HasGFNI = true;
225
576k
    } else if (Feature == "+avx512cd") {
226
48
      HasAVX512CD = true;
227
576k
    } else if (Feature == "+avx512vpopcntdq") {
228
17
      HasAVX512VPOPCNTDQ = true;
229
576k
    } else if (Feature == "+avx512vnni") {
230
19
      HasAVX512VNNI = true;
231
576k
    } else if (Feature == "+avx512bf16") {
232
8
      HasAVX512BF16 = true;
233
576k
    } else if (Feature == "+avx512er") {
234
12
      HasAVX512ER = true;
235
576k
    } else if (Feature == "+avx512fp16") {
236
9
      HasAVX512FP16 = true;
237
9
      HasFloat16 = true;
238
576k
    } else if (Feature == "+avx512pf") {
239
11
      HasAVX512PF = true;
240
576k
    } else if (Feature == "+avx512dq") {
241
52
      HasAVX512DQ = true;
242
576k
    } else if (Feature == "+avx512bitalg") {
243
15
      HasAVX512BITALG = true;
244
576k
    } else if (Feature == "+avx512bw") {
245
64
      HasAVX512BW = true;
246
576k
    } else if (Feature == "+avx512vl") {
247
69
      HasAVX512VL = true;
248
576k
    } else if (Feature == "+avx512vbmi") {
249
18
      HasAVX512VBMI = true;
250
576k
    } else if (Feature == "+avx512vbmi2") {
251
15
      HasAVX512VBMI2 = true;
252
576k
    } else if (Feature == "+avx512ifma") {
253
18
      HasAVX512IFMA = true;
254
576k
    } else if (Feature == "+avx512vp2intersect") {
255
9
      HasAVX512VP2INTERSECT = true;
256
576k
    } else if (Feature == "+sha") {
257
34
      HasSHA = true;
258
576k
    } else if (Feature == "+shstk") {
259
12
      HasSHSTK = true;
260
575k
    } else if (Feature == "+movbe") {
261
162
      HasMOVBE = true;
262
575k
    } else if (Feature == "+sgx") {
263
25
      HasSGX = true;
264
575k
    } else if (Feature == "+cx8") {
265
93.8k
      HasCX8 = true;
266
481k
    } else if (Feature == "+cx16") {
267
16.5k
      HasCX16 = true;
268
465k
    } else if (Feature == "+fxsr") {
269
34.7k
      HasFXSR = true;
270
430k
    } else if (Feature == "+xsave") {
271
320
      HasXSAVE = true;
272
430k
    } else if (Feature == "+xsaveopt") {
273
115
      HasXSAVEOPT = true;
274
430k
    } else if (Feature == "+xsavec") {
275
65
      HasXSAVEC = true;
276
430k
    } else if (Feature == "+xsaves") {
277
65
      HasXSAVES = true;
278
430k
    } else if (Feature == "+mwaitx") {
279
16
      HasMWAITX = true;
280
430k
    } else if (Feature == "+pku") {
281
41
      HasPKU = true;
282
430k
    } else if (Feature == "+clflushopt") {
283
59
      HasCLFLUSHOPT = true;
284
429k
    } else if (Feature == "+clwb") {
285
38
      HasCLWB = true;
286
429k
    } else if (Feature == "+wbnoinvd") {
287
15
      HasWBNOINVD = true;
288
429k
    } else if (Feature == "+prefetchwt1") {
289
11
      HasPREFETCHWT1 = true;
290
429k
    } else if (Feature == "+clzero") {
291
14
      HasCLZERO = true;
292
429k
    } else if (Feature == "+cldemote") {
293
9
      HasCLDEMOTE = true;
294
429k
    } else if (Feature == "+rdpid") {
295
26
      HasRDPID = true;
296
429k
    } else if (Feature == "+kl") {
297
8
      HasKL = true;
298
429k
    } else if (Feature == "+widekl") {
299
7
      HasWIDEKL = true;
300
429k
    } else if (Feature == "+retpoline-external-thunk") {
301
0
      HasRetpolineExternalThunk = true;
302
429k
    } else if (Feature == "+sahf") {
303
16.5k
      HasLAHFSAHF = true;
304
413k
    } else if (Feature == "+waitpkg") {
305
6
      HasWAITPKG = true;
306
413k
    } else if (Feature == "+movdiri") {
307
11
      HasMOVDIRI = true;
308
413k
    } else if (Feature == "+movdir64b") {
309
11
      HasMOVDIR64B = true;
310
413k
    } else if (Feature == "+pconfig") {
311
9
      HasPCONFIG = true;
312
413k
    } else if (Feature == "+ptwrite") {
313
10
      HasPTWRITE = true;
314
413k
    } else if (Feature == "+invpcid") {
315
67
      HasINVPCID = true;
316
413k
    } else if (Feature == "+enqcmd") {
317
5
      HasENQCMD = true;
318
413k
    } else if (Feature == "+hreset") {
319
5
      HasHRESET = true;
320
413k
    } else if (Feature == "+amx-bf16") {
321
7
      HasAMXBF16 = true;
322
413k
    } else if (Feature == "+amx-int8") {
323
7
      HasAMXINT8 = true;
324
413k
    } else if (Feature == "+amx-tile") {
325
9
      HasAMXTILE = true;
326
413k
    } else if (Feature == "+avxvnni") {
327
6
      HasAVXVNNI = true;
328
413k
    } else if (Feature == "+serialize") {
329
7
      HasSERIALIZE = true;
330
413k
    } else if (Feature == "+tsxldtrk") {
331
5
      HasTSXLDTRK = true;
332
413k
    } else if (Feature == "+uintr") {
333
4
      HasUINTR = true;
334
4
    }
335
336
578k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
337
578k
                           .Case("+avx512f", AVX512F)
338
578k
                           .Case("+avx2", AVX2)
339
578k
                           .Case("+avx", AVX)
340
578k
                           .Case("+sse4.2", SSE42)
341
578k
                           .Case("+sse4.1", SSE41)
342
578k
                           .Case("+ssse3", SSSE3)
343
578k
                           .Case("+sse3", SSE3)
344
578k
                           .Case("+sse2", SSE2)
345
578k
                           .Case("+sse", SSE1)
346
578k
                           .Default(NoSSE);
347
578k
    SSELevel = std::max(SSELevel, Level);
348
349
578k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
350
578k
                                      .Case("+3dnowa", AMD3DNowAthlon)
351
578k
                                      .Case("+3dnow", AMD3DNow)
352
578k
                                      .Case("+mmx", MMX)
353
578k
                                      .Default(NoMMX3DNow);
354
578k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
355
356
578k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
357
578k
                         .Case("+xop", XOP)
358
578k
                         .Case("+fma4", FMA4)
359
578k
                         .Case("+sse4a", SSE4A)
360
578k
                         .Default(NoXOP);
361
578k
    XOPLevel = std::max(XOPLevel, XLevel);
362
578k
  }
363
364
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
365
  // matches the selected sse level.
366
93.8k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
367
93.8k
      
(93.8k
FPMath == FP_38793.8k
&&
SSELevel >= SSE12
)) {
368
2
    Diags.Report(diag::err_target_unsupported_fpmath)
369
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
370
2
    return false;
371
2
  }
372
373
93.8k
  SimdDefaultAlign =
374
93.8k
      hasFeature("avx512f") ? 
512157
:
hasFeature("avx")93.7k
?
256129
:
12893.5k
;
375
93.8k
  return true;
376
93.8k
}
377
378
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
379
/// definitions for this particular subtarget.
380
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
381
85.7k
                                     MacroBuilder &Builder) const {
382
  // Inline assembly supports X86 flag outputs.
383
85.7k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
384
385
85.7k
  std::string CodeModel = getTargetOpts().CodeModel;
386
85.7k
  if (CodeModel == "default")
387
60.3k
    CodeModel = "small";
388
85.7k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
389
390
  // Target identification.
391
85.7k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
392
71.5k
    Builder.defineMacro("__amd64__");
393
71.5k
    Builder.defineMacro("__amd64");
394
71.5k
    Builder.defineMacro("__x86_64");
395
71.5k
    Builder.defineMacro("__x86_64__");
396
71.5k
    if (getTriple().getArchName() == "x86_64h") {
397
2
      Builder.defineMacro("__x86_64h");
398
2
      Builder.defineMacro("__x86_64h__");
399
2
    }
400
71.5k
  } else {
401
14.2k
    DefineStd(Builder, "i386", Opts);
402
14.2k
  }
403
404
85.7k
  Builder.defineMacro("__SEG_GS");
405
85.7k
  Builder.defineMacro("__SEG_FS");
406
85.7k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
407
85.7k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
408
409
  // Subtarget options.
410
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
411
  // truly should be based on -mtune options.
412
85.7k
  using namespace llvm::X86;
413
85.7k
  switch (CPU) {
414
51.0k
  case CK_None:
415
51.0k
    break;
416
29
  case CK_i386:
417
    // The rest are coming from the i386 define above.
418
29
    Builder.defineMacro("__tune_i386__");
419
29
    break;
420
5
  case CK_i486:
421
6
  case CK_WinChipC6:
422
7
  case CK_WinChip2:
423
8
  case CK_C3:
424
8
    defineCPUMacros(Builder, "i486");
425
8
    break;
426
1
  case CK_PentiumMMX:
427
1
    Builder.defineMacro("__pentium_mmx__");
428
1
    Builder.defineMacro("__tune_pentium_mmx__");
429
1
    LLVM_FALLTHROUGH;
430
3
  case CK_i586:
431
7
  case CK_Pentium:
432
7
    defineCPUMacros(Builder, "i586");
433
7
    defineCPUMacros(Builder, "pentium");
434
7
    break;
435
4
  case CK_Pentium3:
436
8
  case CK_PentiumM:
437
8
    Builder.defineMacro("__tune_pentium3__");
438
8
    LLVM_FALLTHROUGH;
439
9
  case CK_Pentium2:
440
10
  case CK_C3_2:
441
10
    Builder.defineMacro("__tune_pentium2__");
442
10
    LLVM_FALLTHROUGH;
443
20
  case CK_PentiumPro:
444
27
  case CK_i686:
445
27
    defineCPUMacros(Builder, "i686");
446
27
    defineCPUMacros(Builder, "pentiumpro");
447
27
    break;
448
9.51k
  case CK_Pentium4:
449
9.51k
    defineCPUMacros(Builder, "pentium4");
450
9.51k
    break;
451
8
  case CK_Yonah:
452
9
  case CK_Prescott:
453
12
  case CK_Nocona:
454
12
    defineCPUMacros(Builder, "nocona");
455
12
    break;
456
150
  case CK_Core2:
457
16.3k
  case CK_Penryn:
458
16.3k
    defineCPUMacros(Builder, "core2");
459
16.3k
    break;
460
61
  case CK_Bonnell:
461
61
    defineCPUMacros(Builder, "atom");
462
61
    break;
463
4
  case CK_Silvermont:
464
4
    defineCPUMacros(Builder, "slm");
465
4
    break;
466
2
  case CK_Goldmont:
467
2
    defineCPUMacros(Builder, "goldmont");
468
2
    break;
469
2
  case CK_GoldmontPlus:
470
2
    defineCPUMacros(Builder, "goldmont_plus");
471
2
    break;
472
2
  case CK_Tremont:
473
2
    defineCPUMacros(Builder, "tremont");
474
2
    break;
475
7
  case CK_Nehalem:
476
8
  case CK_Westmere:
477
16
  case CK_SandyBridge:
478
19
  case CK_IvyBridge:
479
25
  case CK_Haswell:
480
29
  case CK_Broadwell:
481
33
  case CK_SkylakeClient:
482
49
  case CK_SkylakeServer:
483
51
  case CK_Cascadelake:
484
53
  case CK_Cooperlake:
485
56
  case CK_Cannonlake:
486
59
  case CK_IcelakeClient:
487
61
  case CK_Rocketlake:
488
64
  case CK_IcelakeServer:
489
66
  case CK_Tigerlake:
490
68
  case CK_SapphireRapids:
491
70
  case CK_Alderlake:
492
    // FIXME: Historically, we defined this legacy name, it would be nice to
493
    // remove it at some point. We've never exposed fine-grained names for
494
    // recent primary x86 CPUs, and we should keep it that way.
495
70
    defineCPUMacros(Builder, "corei7");
496
70
    break;
497
8
  case CK_KNL:
498
8
    defineCPUMacros(Builder, "knl");
499
8
    break;
500
3
  case CK_KNM:
501
3
    break;
502
1
  case CK_Lakemont:
503
1
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
504
1
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
505
1
    Builder.defineMacro("__tune_lakemont__");
506
1
    break;
507
1
  case CK_K6_2:
508
1
    Builder.defineMacro("__k6_2__");
509
1
    Builder.defineMacro("__tune_k6_2__");
510
1
    LLVM_FALLTHROUGH;
511
2
  case CK_K6_3:
512
2
    if (CPU != CK_K6_2) { // In case of fallthrough
513
      // FIXME: GCC may be enabling these in cases where some other k6
514
      // architecture is specified but -m3dnow is explicitly provided. The
515
      // exact semantics need to be determined and emulated here.
516
1
      Builder.defineMacro("__k6_3__");
517
1
      Builder.defineMacro("__tune_k6_3__");
518
1
    }
519
2
    LLVM_FALLTHROUGH;
520
3
  case CK_K6:
521
3
    defineCPUMacros(Builder, "k6");
522
3
    break;
523
2
  case CK_Athlon:
524
5
  case CK_AthlonXP:
525
5
    defineCPUMacros(Builder, "athlon");
526
5
    if (SSELevel != NoSSE) {
527
3
      Builder.defineMacro("__athlon_sse__");
528
3
      Builder.defineMacro("__tune_athlon_sse__");
529
3
    }
530
5
    break;
531
12
  case CK_K8:
532
21
  case CK_K8SSE3:
533
8.58k
  case CK_x86_64:
534
8.58k
    defineCPUMacros(Builder, "k8");
535
8.58k
    break;
536
1
  case CK_x86_64_v2:
537
2
  case CK_x86_64_v3:
538
3
  case CK_x86_64_v4:
539
3
    break;
540
4
  case CK_AMDFAM10:
541
4
    defineCPUMacros(Builder, "amdfam10");
542
4
    break;
543
4
  case CK_BTVER1:
544
4
    defineCPUMacros(Builder, "btver1");
545
4
    break;
546
10
  case CK_BTVER2:
547
10
    defineCPUMacros(Builder, "btver2");
548
10
    break;
549
4
  case CK_BDVER1:
550
4
    defineCPUMacros(Builder, "bdver1");
551
4
    break;
552
4
  case CK_BDVER2:
553
4
    defineCPUMacros(Builder, "bdver2");
554
4
    break;
555
3
  case CK_BDVER3:
556
3
    defineCPUMacros(Builder, "bdver3");
557
3
    break;
558
3
  case CK_BDVER4:
559
3
    defineCPUMacros(Builder, "bdver4");
560
3
    break;
561
4
  case CK_ZNVER1:
562
4
    defineCPUMacros(Builder, "znver1");
563
4
    break;
564
3
  case CK_ZNVER2:
565
3
    defineCPUMacros(Builder, "znver2");
566
3
    break;
567
3
  case CK_ZNVER3:
568
3
    defineCPUMacros(Builder, "znver3");
569
3
    break;
570
1
  case CK_Geode:
571
1
    defineCPUMacros(Builder, "geode");
572
1
    break;
573
85.7k
  }
574
575
  // Target properties.
576
85.7k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
577
578
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
579
  // functions in glibc header files that use FP Stack inline asm which the
580
  // backend can't deal with (PR879).
581
85.7k
  Builder.defineMacro("__NO_MATH_INLINES");
582
583
85.7k
  if (HasAES)
584
95
    Builder.defineMacro("__AES__");
585
586
85.7k
  if (HasVAES)
587
20
    Builder.defineMacro("__VAES__");
588
589
85.7k
  if (HasPCLMUL)
590
120
    Builder.defineMacro("__PCLMUL__");
591
592
85.7k
  if (HasVPCLMULQDQ)
593
20
    Builder.defineMacro("__VPCLMULQDQ__");
594
595
  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
596
  // the feature flag only applies to 64-bit mode.
597
85.7k
  if (HasLAHFSAHF || 
getTriple().getArch() == llvm::Triple::x8669.2k
)
598
30.6k
    Builder.defineMacro("__LAHF_SAHF__");
599
600
85.7k
  if (HasLZCNT)
601
107
    Builder.defineMacro("__LZCNT__");
602
603
85.7k
  if (HasRDRND)
604
88
    Builder.defineMacro("__RDRND__");
605
606
85.7k
  if (HasFSGSBASE)
607
87
    Builder.defineMacro("__FSGSBASE__");
608
609
85.7k
  if (HasBMI)
610
95
    Builder.defineMacro("__BMI__");
611
612
85.7k
  if (HasBMI2)
613
79
    Builder.defineMacro("__BMI2__");
614
615
85.7k
  if (HasPOPCNT)
616
326
    Builder.defineMacro("__POPCNT__");
617
618
85.7k
  if (HasRTM)
619
1
    Builder.defineMacro("__RTM__");
620
621
85.7k
  if (HasPRFCHW)
622
110
    Builder.defineMacro("__PRFCHW__");
623
624
85.7k
  if (HasRDSEED)
625
74
    Builder.defineMacro("__RDSEED__");
626
627
85.7k
  if (HasADX)
628
68
    Builder.defineMacro("__ADX__");
629
630
85.7k
  if (HasTBM)
631
11
    Builder.defineMacro("__TBM__");
632
633
85.7k
  if (HasLWP)
634
15
    Builder.defineMacro("__LWP__");
635
636
85.7k
  if (HasMWAITX)
637
16
    Builder.defineMacro("__MWAITX__");
638
639
85.7k
  if (HasMOVBE)
640
160
    Builder.defineMacro("__MOVBE__");
641
642
85.7k
  switch (XOPLevel) {
643
18
  case XOP:
644
18
    Builder.defineMacro("__XOP__");
645
18
    LLVM_FALLTHROUGH;
646
19
  case FMA4:
647
19
    Builder.defineMacro("__FMA4__");
648
19
    LLVM_FALLTHROUGH;
649
47
  case SSE4A:
650
47
    Builder.defineMacro("__SSE4A__");
651
47
    LLVM_FALLTHROUGH;
652
85.7k
  case NoXOP:
653
85.7k
    break;
654
85.7k
  }
655
656
85.7k
  if (HasFMA)
657
200
    Builder.defineMacro("__FMA__");
658
659
85.7k
  if (HasF16C)
660
211
    Builder.defineMacro("__F16C__");
661
662
85.7k
  if (HasGFNI)
663
20
    Builder.defineMacro("__GFNI__");
664
665
85.7k
  if (HasAVX512CD)
666
48
    Builder.defineMacro("__AVX512CD__");
667
85.7k
  if (HasAVX512VPOPCNTDQ)
668
17
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
669
85.7k
  if (HasAVX512VNNI)
670
19
    Builder.defineMacro("__AVX512VNNI__");
671
85.7k
  if (HasAVX512BF16)
672
8
    Builder.defineMacro("__AVX512BF16__");
673
85.7k
  if (HasAVX512ER)
674
12
    Builder.defineMacro("__AVX512ER__");
675
85.7k
  if (HasAVX512FP16)
676
9
    Builder.defineMacro("__AVX512FP16__");
677
85.7k
  if (HasAVX512PF)
678
11
    Builder.defineMacro("__AVX512PF__");
679
85.7k
  if (HasAVX512DQ)
680
52
    Builder.defineMacro("__AVX512DQ__");
681
85.7k
  if (HasAVX512BITALG)
682
15
    Builder.defineMacro("__AVX512BITALG__");
683
85.7k
  if (HasAVX512BW)
684
64
    Builder.defineMacro("__AVX512BW__");
685
85.7k
  if (HasAVX512VL)
686
69
    Builder.defineMacro("__AVX512VL__");
687
85.7k
  if (HasAVX512VBMI)
688
18
    Builder.defineMacro("__AVX512VBMI__");
689
85.7k
  if (HasAVX512VBMI2)
690
15
    Builder.defineMacro("__AVX512VBMI2__");
691
85.7k
  if (HasAVX512IFMA)
692
18
    Builder.defineMacro("__AVX512IFMA__");
693
85.7k
  if (HasAVX512VP2INTERSECT)
694
9
    Builder.defineMacro("__AVX512VP2INTERSECT__");
695
85.7k
  if (HasSHA)
696
34
    Builder.defineMacro("__SHA__");
697
698
85.7k
  if (HasFXSR)
699
34.6k
    Builder.defineMacro("__FXSR__");
700
85.7k
  if (HasXSAVE)
701
318
    Builder.defineMacro("__XSAVE__");
702
85.7k
  if (HasXSAVEOPT)
703
113
    Builder.defineMacro("__XSAVEOPT__");
704
85.7k
  if (HasXSAVEC)
705
65
    Builder.defineMacro("__XSAVEC__");
706
85.7k
  if (HasXSAVES)
707
65
    Builder.defineMacro("__XSAVES__");
708
85.7k
  if (HasPKU)
709
41
    Builder.defineMacro("__PKU__");
710
85.7k
  if (HasCLFLUSHOPT)
711
59
    Builder.defineMacro("__CLFLUSHOPT__");
712
85.7k
  if (HasCLWB)
713
38
    Builder.defineMacro("__CLWB__");
714
85.7k
  if (HasWBNOINVD)
715
15
    Builder.defineMacro("__WBNOINVD__");
716
85.7k
  if (HasSHSTK)
717
12
    Builder.defineMacro("__SHSTK__");
718
85.7k
  if (HasSGX)
719
25
    Builder.defineMacro("__SGX__");
720
85.7k
  if (HasPREFETCHWT1)
721
11
    Builder.defineMacro("__PREFETCHWT1__");
722
85.7k
  if (HasCLZERO)
723
14
    Builder.defineMacro("__CLZERO__");
724
85.7k
  if (HasKL)
725
8
    Builder.defineMacro("__KL__");
726
85.7k
  if (HasWIDEKL)
727
7
    Builder.defineMacro("__WIDEKL__");
728
85.7k
  if (HasRDPID)
729
26
    Builder.defineMacro("__RDPID__");
730
85.7k
  if (HasCLDEMOTE)
731
9
    Builder.defineMacro("__CLDEMOTE__");
732
85.7k
  if (HasWAITPKG)
733
6
    Builder.defineMacro("__WAITPKG__");
734
85.7k
  if (HasMOVDIRI)
735
11
    Builder.defineMacro("__MOVDIRI__");
736
85.7k
  if (HasMOVDIR64B)
737
11
    Builder.defineMacro("__MOVDIR64B__");
738
85.7k
  if (HasPCONFIG)
739
9
    Builder.defineMacro("__PCONFIG__");
740
85.7k
  if (HasPTWRITE)
741
10
    Builder.defineMacro("__PTWRITE__");
742
85.7k
  if (HasINVPCID)
743
67
    Builder.defineMacro("__INVPCID__");
744
85.7k
  if (HasENQCMD)
745
5
    Builder.defineMacro("__ENQCMD__");
746
85.7k
  if (HasHRESET)
747
5
    Builder.defineMacro("__HRESET__");
748
85.7k
  if (HasAMXTILE)
749
9
    Builder.defineMacro("__AMXTILE__");
750
85.7k
  if (HasAMXINT8)
751
7
    Builder.defineMacro("__AMXINT8__");
752
85.7k
  if (HasAMXBF16)
753
7
    Builder.defineMacro("__AMXBF16__");
754
85.7k
  if (HasAVXVNNI)
755
6
    Builder.defineMacro("__AVXVNNI__");
756
85.7k
  if (HasSERIALIZE)
757
7
    Builder.defineMacro("__SERIALIZE__");
758
85.7k
  if (HasTSXLDTRK)
759
5
    Builder.defineMacro("__TSXLDTRK__");
760
85.7k
  if (HasUINTR)
761
4
    Builder.defineMacro("__UINTR__");
762
763
  // Each case falls through to the previous one here.
764
85.7k
  switch (SSELevel) {
765
157
  case AVX512F:
766
157
    Builder.defineMacro("__AVX512F__");
767
157
    LLVM_FALLTHROUGH;
768
195
  case AVX2:
769
195
    Builder.defineMacro("__AVX2__");
770
195
    LLVM_FALLTHROUGH;
771
284
  case AVX:
772
284
    Builder.defineMacro("__AVX__");
773
284
    LLVM_FALLTHROUGH;
774
311
  case SSE42:
775
311
    Builder.defineMacro("__SSE4_2__");
776
311
    LLVM_FALLTHROUGH;
777
16.4k
  case SSE41:
778
16.4k
    Builder.defineMacro("__SSE4_1__");
779
16.4k
    LLVM_FALLTHROUGH;
780
16.6k
  case SSSE3:
781
16.6k
    Builder.defineMacro("__SSSE3__");
782
16.6k
    LLVM_FALLTHROUGH;
783
16.7k
  case SSE3:
784
16.7k
    Builder.defineMacro("__SSE3__");
785
16.7k
    LLVM_FALLTHROUGH;
786
81.2k
  case SSE2:
787
81.2k
    Builder.defineMacro("__SSE2__");
788
81.2k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
789
81.2k
    LLVM_FALLTHROUGH;
790
81.2k
  case SSE1:
791
81.2k
    Builder.defineMacro("__SSE__");
792
81.2k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
793
81.2k
    LLVM_FALLTHROUGH;
794
85.7k
  case NoSSE:
795
85.7k
    break;
796
85.7k
  }
797
798
85.7k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x8610.6k
) {
799
328
    switch (SSELevel) {
800
2
    case AVX512F:
801
4
    case AVX2:
802
6
    case AVX:
803
6
    case SSE42:
804
6
    case SSE41:
805
6
    case SSSE3:
806
6
    case SSE3:
807
48
    case SSE2:
808
48
      Builder.defineMacro("_M_IX86_FP", Twine(2));
809
48
      break;
810
2
    case SSE1:
811
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
812
2
      break;
813
278
    default:
814
278
      Builder.defineMacro("_M_IX86_FP", Twine(0));
815
278
      break;
816
328
    }
817
328
  }
818
819
  // Each case falls through to the previous one here.
820
85.7k
  switch (MMX3DNowLevel) {
821
33
  case AMD3DNowAthlon:
822
33
    Builder.defineMacro("__3dNOW_A__");
823
33
    LLVM_FALLTHROUGH;
824
39
  case AMD3DNow:
825
39
    Builder.defineMacro("__3dNOW__");
826
39
    LLVM_FALLTHROUGH;
827
81.2k
  case MMX:
828
81.2k
    Builder.defineMacro("__MMX__");
829
81.2k
    LLVM_FALLTHROUGH;
830
85.7k
  case NoMMX3DNow:
831
85.7k
    break;
832
85.7k
  }
833
834
85.7k
  if (CPU >= CK_i486 || 
CPU == CK_None51.0k
) {
835
85.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
836
85.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
837
85.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
838
85.7k
  }
839
85.7k
  if (HasCX8)
840
85.7k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
841
85.7k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6416.5k
)
842
16.3k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
843
844
85.7k
  if (HasFloat128)
845
3.91k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
846
85.7k
}
847
848
1.34M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
849
1.34M
  return llvm::StringSwitch<bool>(Name)
850
1.34M
      .Case("3dnow", true)
851
1.34M
      .Case("3dnowa", true)
852
1.34M
      .Case("adx", true)
853
1.34M
      .Case("aes", true)
854
1.34M
      .Case("amx-bf16", true)
855
1.34M
      .Case("amx-int8", true)
856
1.34M
      .Case("amx-tile", true)
857
1.34M
      .Case("avx", true)
858
1.34M
      .Case("avx2", true)
859
1.34M
      .Case("avx512f", true)
860
1.34M
      .Case("avx512cd", true)
861
1.34M
      .Case("avx512vpopcntdq", true)
862
1.34M
      .Case("avx512vnni", true)
863
1.34M
      .Case("avx512bf16", true)
864
1.34M
      .Case("avx512er", true)
865
1.34M
      .Case("avx512fp16", true)
866
1.34M
      .Case("avx512pf", true)
867
1.34M
      .Case("avx512dq", true)
868
1.34M
      .Case("avx512bitalg", true)
869
1.34M
      .Case("avx512bw", true)
870
1.34M
      .Case("avx512vl", true)
871
1.34M
      .Case("avx512vbmi", true)
872
1.34M
      .Case("avx512vbmi2", true)
873
1.34M
      .Case("avx512ifma", true)
874
1.34M
      .Case("avx512vp2intersect", true)
875
1.34M
      .Case("avxvnni", true)
876
1.34M
      .Case("bmi", true)
877
1.34M
      .Case("bmi2", true)
878
1.34M
      .Case("cldemote", true)
879
1.34M
      .Case("clflushopt", true)
880
1.34M
      .Case("clwb", true)
881
1.34M
      .Case("clzero", true)
882
1.34M
      .Case("cx16", true)
883
1.34M
      .Case("enqcmd", true)
884
1.34M
      .Case("f16c", true)
885
1.34M
      .Case("fma", true)
886
1.34M
      .Case("fma4", true)
887
1.34M
      .Case("fsgsbase", true)
888
1.34M
      .Case("fxsr", true)
889
1.34M
      .Case("general-regs-only", true)
890
1.34M
      .Case("gfni", true)
891
1.34M
      .Case("hreset", true)
892
1.34M
      .Case("invpcid", true)
893
1.34M
      .Case("kl", true)
894
1.34M
      .Case("widekl", true)
895
1.34M
      .Case("lwp", true)
896
1.34M
      .Case("lzcnt", true)
897
1.34M
      .Case("mmx", true)
898
1.34M
      .Case("movbe", true)
899
1.34M
      .Case("movdiri", true)
900
1.34M
      .Case("movdir64b", true)
901
1.34M
      .Case("mwaitx", true)
902
1.34M
      .Case("pclmul", true)
903
1.34M
      .Case("pconfig", true)
904
1.34M
      .Case("pku", true)
905
1.34M
      .Case("popcnt", true)
906
1.34M
      .Case("prefetchwt1", true)
907
1.34M
      .Case("prfchw", true)
908
1.34M
      .Case("ptwrite", true)
909
1.34M
      .Case("rdpid", true)
910
1.34M
      .Case("rdrnd", true)
911
1.34M
      .Case("rdseed", true)
912
1.34M
      .Case("rtm", true)
913
1.34M
      .Case("sahf", true)
914
1.34M
      .Case("serialize", true)
915
1.34M
      .Case("sgx", true)
916
1.34M
      .Case("sha", true)
917
1.34M
      .Case("shstk", true)
918
1.34M
      .Case("sse", true)
919
1.34M
      .Case("sse2", true)
920
1.34M
      .Case("sse3", true)
921
1.34M
      .Case("ssse3", true)
922
1.34M
      .Case("sse4", true)
923
1.34M
      .Case("sse4.1", true)
924
1.34M
      .Case("sse4.2", true)
925
1.34M
      .Case("sse4a", true)
926
1.34M
      .Case("tbm", true)
927
1.34M
      .Case("tsxldtrk", true)
928
1.34M
      .Case("uintr", true)
929
1.34M
      .Case("vaes", true)
930
1.34M
      .Case("vpclmulqdq", true)
931
1.34M
      .Case("wbnoinvd", true)
932
1.34M
      .Case("waitpkg", true)
933
1.34M
      .Case("x87", true)
934
1.34M
      .Case("xop", true)
935
1.34M
      .Case("xsave", true)
936
1.34M
      .Case("xsavec", true)
937
1.34M
      .Case("xsaves", true)
938
1.34M
      .Case("xsaveopt", true)
939
1.34M
      .Default(false);
940
1.34M
}
941
942
477k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
943
477k
  return llvm::StringSwitch<bool>(Feature)
944
477k
      .Case("adx", HasADX)
945
477k
      .Case("aes", HasAES)
946
477k
      .Case("amx-bf16", HasAMXBF16)
947
477k
      .Case("amx-int8", HasAMXINT8)
948
477k
      .Case("amx-tile", HasAMXTILE)
949
477k
      .Case("avxvnni", HasAVXVNNI)
950
477k
      .Case("avx", SSELevel >= AVX)
951
477k
      .Case("avx2", SSELevel >= AVX2)
952
477k
      .Case("avx512f", SSELevel >= AVX512F)
953
477k
      .Case("avx512cd", HasAVX512CD)
954
477k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
955
477k
      .Case("avx512vnni", HasAVX512VNNI)
956
477k
      .Case("avx512bf16", HasAVX512BF16)
957
477k
      .Case("avx512er", HasAVX512ER)
958
477k
      .Case("avx512fp16", HasAVX512FP16)
959
477k
      .Case("avx512pf", HasAVX512PF)
960
477k
      .Case("avx512dq", HasAVX512DQ)
961
477k
      .Case("avx512bitalg", HasAVX512BITALG)
962
477k
      .Case("avx512bw", HasAVX512BW)
963
477k
      .Case("avx512vl", HasAVX512VL)
964
477k
      .Case("avx512vbmi", HasAVX512VBMI)
965
477k
      .Case("avx512vbmi2", HasAVX512VBMI2)
966
477k
      .Case("avx512ifma", HasAVX512IFMA)
967
477k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
968
477k
      .Case("bmi", HasBMI)
969
477k
      .Case("bmi2", HasBMI2)
970
477k
      .Case("cldemote", HasCLDEMOTE)
971
477k
      .Case("clflushopt", HasCLFLUSHOPT)
972
477k
      .Case("clwb", HasCLWB)
973
477k
      .Case("clzero", HasCLZERO)
974
477k
      .Case("cx8", HasCX8)
975
477k
      .Case("cx16", HasCX16)
976
477k
      .Case("enqcmd", HasENQCMD)
977
477k
      .Case("f16c", HasF16C)
978
477k
      .Case("fma", HasFMA)
979
477k
      .Case("fma4", XOPLevel >= FMA4)
980
477k
      .Case("fsgsbase", HasFSGSBASE)
981
477k
      .Case("fxsr", HasFXSR)
982
477k
      .Case("gfni", HasGFNI)
983
477k
      .Case("hreset", HasHRESET)
984
477k
      .Case("invpcid", HasINVPCID)
985
477k
      .Case("kl", HasKL)
986
477k
      .Case("widekl", HasWIDEKL)
987
477k
      .Case("lwp", HasLWP)
988
477k
      .Case("lzcnt", HasLZCNT)
989
477k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
990
477k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
991
477k
      .Case("mmx", MMX3DNowLevel >= MMX)
992
477k
      .Case("movbe", HasMOVBE)
993
477k
      .Case("movdiri", HasMOVDIRI)
994
477k
      .Case("movdir64b", HasMOVDIR64B)
995
477k
      .Case("mwaitx", HasMWAITX)
996
477k
      .Case("pclmul", HasPCLMUL)
997
477k
      .Case("pconfig", HasPCONFIG)
998
477k
      .Case("pku", HasPKU)
999
477k
      .Case("popcnt", HasPOPCNT)
1000
477k
      .Case("prefetchwt1", HasPREFETCHWT1)
1001
477k
      .Case("prfchw", HasPRFCHW)
1002
477k
      .Case("ptwrite", HasPTWRITE)
1003
477k
      .Case("rdpid", HasRDPID)
1004
477k
      .Case("rdrnd", HasRDRND)
1005
477k
      .Case("rdseed", HasRDSEED)
1006
477k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1007
477k
      .Case("rtm", HasRTM)
1008
477k
      .Case("sahf", HasLAHFSAHF)
1009
477k
      .Case("serialize", HasSERIALIZE)
1010
477k
      .Case("sgx", HasSGX)
1011
477k
      .Case("sha", HasSHA)
1012
477k
      .Case("shstk", HasSHSTK)
1013
477k
      .Case("sse", SSELevel >= SSE1)
1014
477k
      .Case("sse2", SSELevel >= SSE2)
1015
477k
      .Case("sse3", SSELevel >= SSE3)
1016
477k
      .Case("ssse3", SSELevel >= SSSE3)
1017
477k
      .Case("sse4.1", SSELevel >= SSE41)
1018
477k
      .Case("sse4.2", SSELevel >= SSE42)
1019
477k
      .Case("sse4a", XOPLevel >= SSE4A)
1020
477k
      .Case("tbm", HasTBM)
1021
477k
      .Case("tsxldtrk", HasTSXLDTRK)
1022
477k
      .Case("uintr", HasUINTR)
1023
477k
      .Case("vaes", HasVAES)
1024
477k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1025
477k
      .Case("wbnoinvd", HasWBNOINVD)
1026
477k
      .Case("waitpkg", HasWAITPKG)
1027
477k
      .Case("x86", true)
1028
477k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1029
477k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1030
477k
      .Case("xop", XOPLevel >= XOP)
1031
477k
      .Case("xsave", HasXSAVE)
1032
477k
      .Case("xsavec", HasXSAVEC)
1033
477k
      .Case("xsaves", HasXSAVES)
1034
477k
      .Case("xsaveopt", HasXSAVEOPT)
1035
477k
      .Default(false);
1036
477k
}
1037
1038
// We can't use a generic validation scheme for the features accepted here
1039
// versus subtarget features accepted in the target attribute because the
1040
// bitfield structure that's initialized in the runtime only supports the
1041
// below currently rather than the full range of subtarget features. (See
1042
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1043
855
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1044
855
  return llvm::StringSwitch<bool>(FeatureStr)
1045
32.4k
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1046
855
#include "llvm/Support/X86TargetParser.def"
1047
855
      .Default(false);
1048
855
}
1049
1050
157
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1051
157
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1052
157
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1053
5.96k
  .Case(STR, llvm::X86::FEATURE_##ENUM)
1054
1055
157
#include "llvm/Support/X86TargetParser.def"
1056
157
      ;
1057
  // Note, this function should only be used after ensuring the value is
1058
  // correct, so it asserts if the value is out of range.
1059
157
}
1060
1061
433
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1062
433
#ifndef NDEBUG
1063
  // Check that priorities are set properly in the .def file. We expect that
1064
  // "compat" features are assigned non-duplicate consecutive priorities
1065
  // starting from zero (0, 1, ..., num_features - 1).
1066
16.4k
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
1067
433
  unsigned Priorities[] = {
1068
433
#include "llvm/Support/X86TargetParser.def"
1069
433
      std::numeric_limits<unsigned>::max() // Need to consume last comma.
1070
433
  };
1071
433
  std::array<unsigned, llvm::array_lengthof(Priorities) - 1> HelperList;
1072
433
  std::iota(HelperList.begin(), HelperList.end(), 0);
1073
433
  assert(std::is_permutation(HelperList.begin(), HelperList.end(),
1074
433
                             std::begin(Priorities),
1075
433
                             std::prev(std::end(Priorities))) &&
1076
433
         "Priorities don't form consecutive range!");
1077
0
#endif
1078
1079
0
  switch (Feat) {
1080
0
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1081
433
  case llvm::X86::FEATURE_##ENUM:                                              \
1082
433
    return PRIORITY;
1083
0
#include "llvm/Support/X86TargetParser.def"
1084
0
  default:
1085
0
    llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1086
433
  }
1087
433
}
1088
1089
433
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1090
  // Valid CPUs have a 'key feature' that compares just better than its key
1091
  // feature.
1092
433
  using namespace llvm::X86;
1093
433
  CPUKind Kind = parseArchX86(Name);
1094
433
  if (Kind != CK_None) {
1095
276
    ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1096
276
    return (getFeaturePriority(KeyFeature) << 1) + 1;
1097
276
  }
1098
1099
  // Now we know we have a feature, so get its priority and shift it a few so
1100
  // that we have sufficient room for the CPUs (above).
1101
157
  return getFeaturePriority(getFeature(Name)) << 1;
1102
433
}
1103
1104
191
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1105
191
  return llvm::StringSwitch<bool>(Name)
1106
5.34k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1107
1.14k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1108
191
#include "clang/Basic/X86Target.def"
1109
191
      .Default(false);
1110
191
}
1111
1112
440
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1113
440
  return llvm::StringSwitch<StringRef>(Name)
1114
2.64k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1115
440
#include "clang/Basic/X86Target.def"
1116
440
      .Default(Name);
1117
440
}
1118
1119
298
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1120
298
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1121
8.34k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1122
298
#include "clang/Basic/X86Target.def"
1123
298
      .Default(0);
1124
298
}
1125
1126
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1127
142
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1128
142
  StringRef WholeList =
1129
142
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1130
3.97k
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1131
142
#include "clang/Basic/X86Target.def"
1132
142
          .Default("");
1133
142
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1134
142
}
1135
1136
// We can't use a generic validation scheme for the cpus accepted here
1137
// versus subtarget cpus accepted in the target attribute because the
1138
// variables intitialized by the runtime only support the below currently
1139
// rather than the full range of cpus.
1140
184
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1141
184
  return llvm::StringSwitch<bool>(FeatureStr)
1142
368
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1143
736
#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1144
2.76k
#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1145
4.96k
#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1146
184
#include "llvm/Support/X86TargetParser.def"
1147
184
      .Default(false);
1148
184
}
1149
1150
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1151
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1152
87
                .Case("@cca", 4)
1153
87
                .Case("@ccae", 5)
1154
87
                .Case("@ccb", 4)
1155
87
                .Case("@ccbe", 5)
1156
87
                .Case("@ccc", 4)
1157
87
                .Case("@cce", 4)
1158
87
                .Case("@ccz", 4)
1159
87
                .Case("@ccg", 4)
1160
87
                .Case("@ccge", 5)
1161
87
                .Case("@ccl", 4)
1162
87
                .Case("@ccle", 5)
1163
87
                .Case("@ccna", 5)
1164
87
                .Case("@ccnae", 6)
1165
87
                .Case("@ccnb", 5)
1166
87
                .Case("@ccnbe", 6)
1167
87
                .Case("@ccnc", 5)
1168
87
                .Case("@ccne", 5)
1169
87
                .Case("@ccnz", 5)
1170
87
                .Case("@ccng", 5)
1171
87
                .Case("@ccnge", 6)
1172
87
                .Case("@ccnl", 5)
1173
87
                .Case("@ccnle", 6)
1174
87
                .Case("@ccno", 5)
1175
87
                .Case("@ccnp", 5)
1176
87
                .Case("@ccns", 5)
1177
87
                .Case("@cco", 4)
1178
87
                .Case("@ccp", 4)
1179
87
                .Case("@ccs", 4)
1180
87
                .Default(0);
1181
87
  return RV;
1182
87
}
1183
1184
bool X86TargetInfo::validateAsmConstraint(
1185
9.87k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1186
9.87k
  switch (*Name) {
1187
3
  default:
1188
3
    return false;
1189
  // Constant constraints.
1190
9
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1191
            // instructions.
1192
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1193
            // x86_64 instructions.
1194
17
  case 's':
1195
17
    Info.setRequiresImmediate();
1196
17
    return true;
1197
28
  case 'I':
1198
28
    Info.setRequiresImmediate(0, 31);
1199
28
    return true;
1200
14
  case 'J':
1201
14
    Info.setRequiresImmediate(0, 63);
1202
14
    return true;
1203
14
  case 'K':
1204
14
    Info.setRequiresImmediate(-128, 127);
1205
14
    return true;
1206
30
  case 'L':
1207
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1208
30
    return true;
1209
14
  case 'M':
1210
14
    Info.setRequiresImmediate(0, 3);
1211
14
    return true;
1212
16
  case 'N':
1213
16
    Info.setRequiresImmediate(0, 255);
1214
16
    return true;
1215
6
  case 'O':
1216
6
    Info.setRequiresImmediate(0, 127);
1217
6
    return true;
1218
  // Register constraints.
1219
52
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1220
    // Shift the pointer to the second character of the constraint.
1221
52
    Name++;
1222
52
    switch (*Name) {
1223
0
    default:
1224
0
      return false;
1225
20
    case 'z': // First SSE register.
1226
26
    case '2':
1227
32
    case 't': // Any SSE register, when SSE2 is enabled.
1228
42
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1229
44
    case 'm': // Any MMX register, when inter-unit moves enabled.
1230
52
    case 'k': // AVX512 arch mask registers: k1-k7.
1231
52
      Info.setAllowsRegister();
1232
52
      return true;
1233
52
    }
1234
3
  case 'f': // Any x87 floating point stack register.
1235
    // Constraint 'f' cannot be used for output operands.
1236
3
    if (Info.ConstraintStr[0] == '=')
1237
1
      return false;
1238
2
    Info.setAllowsRegister();
1239
2
    return true;
1240
2.55k
  case 'a': // eax.
1241
4.64k
  case 'b': // ebx.
1242
6.89k
  case 'c': // ecx.
1243
9.03k
  case 'd': // edx.
1244
9.10k
  case 'S': // esi.
1245
9.23k
  case 'D': // edi.
1246
9.25k
  case 'A': // edx:eax.
1247
9.27k
  case 't': // Top of floating point stack.
1248
9.27k
  case 'u': // Second from top of floating point stack.
1249
9.29k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1250
9.33k
  case 'y': // Any MMX register.
1251
9.39k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1252
9.52k
  case 'x': // Any SSE register.
1253
9.54k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1254
            // for intermideate k reg operations).
1255
9.56k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1256
9.58k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1257
9.60k
  case 'l': // "Index" registers: any general register that can be used as an
1258
            // index in a base+index memory access.
1259
9.60k
    Info.setAllowsRegister();
1260
9.60k
    return true;
1261
  // Floating point constant constraints.
1262
8
  case 'C': // SSE floating point constant.
1263
16
  case 'G': // x87 floating point constant.
1264
16
    return true;
1265
58
  case '@':
1266
    // CC condition changes.
1267
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1268
58
      Name += Len - 1;
1269
58
      Info.setAllowsRegister();
1270
58
      return true;
1271
58
    }
1272
0
    return false;
1273
9.87k
  }
1274
9.87k
}
1275
1276
// Below is based on the following information:
1277
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1278
// |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1279
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1280
// | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1281
// | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1282
// | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1283
// | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1284
// | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1285
// | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1286
// | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1287
// | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1288
// | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1289
// | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1290
// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1291
// | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1292
// | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1293
// | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1294
// | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1295
// | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1296
// | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1297
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1298
0
Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1299
0
  using namespace llvm::X86;
1300
0
  switch (CPU) {
1301
    // i386
1302
0
    case CK_i386:
1303
    // i486
1304
0
    case CK_i486:
1305
0
    case CK_WinChipC6:
1306
0
    case CK_WinChip2:
1307
0
    case CK_C3:
1308
    // Lakemont
1309
0
    case CK_Lakemont:
1310
0
      return 16;
1311
1312
    // i586
1313
0
    case CK_i586:
1314
0
    case CK_Pentium:
1315
0
    case CK_PentiumMMX:
1316
    // i686
1317
0
    case CK_PentiumPro:
1318
0
    case CK_i686:
1319
0
    case CK_Pentium2:
1320
0
    case CK_Pentium3:
1321
0
    case CK_PentiumM:
1322
0
    case CK_C3_2:
1323
    // K6
1324
0
    case CK_K6:
1325
0
    case CK_K6_2:
1326
0
    case CK_K6_3:
1327
    // Geode
1328
0
    case CK_Geode:
1329
0
      return 32;
1330
1331
    // Netburst
1332
0
    case CK_Pentium4:
1333
0
    case CK_Prescott:
1334
0
    case CK_Nocona:
1335
    // Atom
1336
0
    case CK_Bonnell:
1337
0
    case CK_Silvermont:
1338
0
    case CK_Goldmont:
1339
0
    case CK_GoldmontPlus:
1340
0
    case CK_Tremont:
1341
1342
0
    case CK_Westmere:
1343
0
    case CK_SandyBridge:
1344
0
    case CK_IvyBridge:
1345
0
    case CK_Haswell:
1346
0
    case CK_Broadwell:
1347
0
    case CK_SkylakeClient:
1348
0
    case CK_SkylakeServer:
1349
0
    case CK_Cascadelake:
1350
0
    case CK_Nehalem:
1351
0
    case CK_Cooperlake:
1352
0
    case CK_Cannonlake:
1353
0
    case CK_Tigerlake:
1354
0
    case CK_SapphireRapids:
1355
0
    case CK_IcelakeClient:
1356
0
    case CK_Rocketlake:
1357
0
    case CK_IcelakeServer:
1358
0
    case CK_Alderlake:
1359
0
    case CK_KNL:
1360
0
    case CK_KNM:
1361
    // K7
1362
0
    case CK_Athlon:
1363
0
    case CK_AthlonXP:
1364
    // K8
1365
0
    case CK_K8:
1366
0
    case CK_K8SSE3:
1367
0
    case CK_AMDFAM10:
1368
    // Bobcat
1369
0
    case CK_BTVER1:
1370
0
    case CK_BTVER2:
1371
    // Bulldozer
1372
0
    case CK_BDVER1:
1373
0
    case CK_BDVER2:
1374
0
    case CK_BDVER3:
1375
0
    case CK_BDVER4:
1376
    // Zen
1377
0
    case CK_ZNVER1:
1378
0
    case CK_ZNVER2:
1379
0
    case CK_ZNVER3:
1380
    // Deprecated
1381
0
    case CK_x86_64:
1382
0
    case CK_x86_64_v2:
1383
0
    case CK_x86_64_v3:
1384
0
    case CK_x86_64_v4:
1385
0
    case CK_Yonah:
1386
0
    case CK_Penryn:
1387
0
    case CK_Core2:
1388
0
      return 64;
1389
1390
    // The following currently have unknown cache line sizes (but they are probably all 64):
1391
    // Core
1392
0
    case CK_None:
1393
0
      return None;
1394
0
  }
1395
0
  llvm_unreachable("Unknown CPU kind");
1396
0
}
1397
1398
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1399
                                       StringRef Constraint,
1400
5.41k
                                       unsigned Size) const {
1401
  // Strip off constraint modifiers.
1402
10.8k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'5.89k
||
Constraint[0] == '&'5.43k
)
1403
5.43k
    Constraint = Constraint.substr(1);
1404
1405
5.41k
  return validateOperandSize(FeatureMap, Constraint, Size);
1406
5.41k
}
1407
1408
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1409
                                      StringRef Constraint,
1410
5.85k
                                      unsigned Size) const {
1411
5.85k
  return validateOperandSize(FeatureMap, Constraint, Size);
1412
5.85k
}
1413
1414
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1415
                                        StringRef Constraint,
1416
9.36k
                                        unsigned Size) const {
1417
9.36k
  switch (Constraint[0]) {
1418
9.18k
  default:
1419
9.18k
    break;
1420
9.18k
  case 'k':
1421
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1422
30
  case 'y':
1423
30
    return Size <= 64;
1424
2
  case 'f':
1425
13
  case 't':
1426
18
  case 'u':
1427
18
    return Size <= 128;
1428
26
  case 'Y':
1429
    // 'Y' is the first character for several 2-character constraints.
1430
26
    switch (Constraint[1]) {
1431
0
    default:
1432
0
      return false;
1433
1
    case 'm':
1434
      // 'Ym' is synonymous with 'y'.
1435
5
    case 'k':
1436
5
      return Size <= 64;
1437
10
    case 'z':
1438
      // XMM0/YMM/ZMM0
1439
10
      if (hasFeatureEnabled(FeatureMap, "avx512f"))
1440
        // ZMM0 can be used if target supports AVX512F.
1441
7
        return Size <= 512U;
1442
3
      else if (hasFeatureEnabled(FeatureMap, "avx"))
1443
        // YMM0 can be used if target supports AVX.
1444
2
        return Size <= 256U;
1445
1
      else if (hasFeatureEnabled(FeatureMap, "sse"))
1446
1
        return Size <= 128U;
1447
0
      return false;
1448
5
    case 'i':
1449
8
    case 't':
1450
11
    case '2':
1451
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1452
11
      if (SSELevel < SSE2)
1453
0
        return false;
1454
11
      break;
1455
26
    }
1456
11
    break;
1457
30
  case 'v':
1458
107
  case 'x':
1459
107
    if (hasFeatureEnabled(FeatureMap, "avx512f"))
1460
      // 512-bit zmm registers can be used if target supports AVX512F.
1461
46
      return Size <= 512U;
1462
61
    else if (hasFeatureEnabled(FeatureMap, "avx"))
1463
      // 256-bit ymm registers can be used if target supports AVX.
1464
27
      return Size <= 256U;
1465
34
    return Size <= 128U;
1466
1467
9.36k
  }
1468
1469
9.19k
  return true;
1470
9.36k
}
1471
1472
1.77k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1473
1.77k
  switch (*Constraint) {
1474
29
  case '@':
1475
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1476
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1477
29
      Constraint += Len - 1;
1478
29
      return Converted;
1479
29
    }
1480
0
    return std::string(1, *Constraint);
1481
78
  case 'a':
1482
78
    return std::string("{ax}");
1483
39
  case 'b':
1484
39
    return std::string("{bx}");
1485
67
  case 'c':
1486
67
    return std::string("{cx}");
1487
40
  case 'd':
1488
40
    return std::string("{dx}");
1489
25
  case 'S':
1490
25
    return std::string("{si}");
1491
39
  case 'D':
1492
39
    return std::string("{di}");
1493
4
  case 'p': // address
1494
4
    return std::string("im");
1495
5
  case 't': // top of floating point stack.
1496
5
    return std::string("{st}");
1497
1
  case 'u':                        // second from top of floating point stack.
1498
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1499
26
  case 'Y':
1500
26
    switch (Constraint[1]) {
1501
0
    default:
1502
      // Break from inner switch and fall through (copy single char),
1503
      // continue parsing after copying the current constraint into
1504
      // the return string.
1505
0
      break;
1506
4
    case 'k':
1507
5
    case 'm':
1508
10
    case 'i':
1509
13
    case 't':
1510
23
    case 'z':
1511
26
    case '2':
1512
      // "^" hints llvm that this is a 2 letter constraint.
1513
      // "Constraint++" is used to promote the string iterator
1514
      // to the next constraint.
1515
26
      return std::string("^") + std::string(Constraint++, 2);
1516
26
    }
1517
26
    
LLVM_FALLTHROUGH0
;0
1518
1.41k
  default:
1519
1.41k
    return std::string(1, *Constraint);
1520
1.77k
  }
1521
1.77k
}
1522
1523
31
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1524
31
  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1525
31
  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1526
31
}
1527
1528
5
void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1529
5
  llvm::X86::fillValidTuneCPUList(Values);
1530
5
}
1531
1532
3.45k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1533
3.45k
  return llvm::makeArrayRef(GCCRegNames);
1534
3.45k
}
1535
1536
2.86k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1537
2.86k
  return llvm::makeArrayRef(AddlRegNames);
1538
2.86k
}
1539
1540
14.2k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1541
14.2k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1542
14.2k
                                                Builtin::FirstTSBuiltin + 1);
1543
14.2k
}
1544
1545
71.7k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1546
71.7k
  return llvm::makeArrayRef(BuiltinInfoX86,
1547
71.7k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1548
71.7k
}