/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
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1 | | //===--- X86.cpp - Implement X86 target feature support -------------------===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file implements X86 TargetInfo objects. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "X86.h" |
14 | | #include "clang/Basic/Builtins.h" |
15 | | #include "clang/Basic/Diagnostic.h" |
16 | | #include "clang/Basic/TargetBuiltins.h" |
17 | | #include "llvm/ADT/StringExtras.h" |
18 | | #include "llvm/ADT/StringRef.h" |
19 | | #include "llvm/ADT/StringSwitch.h" |
20 | | #include "llvm/TargetParser/X86TargetParser.h" |
21 | | #include <optional> |
22 | | |
23 | | namespace clang { |
24 | | namespace targets { |
25 | | |
26 | | static constexpr Builtin::Info BuiltinInfoX86[] = { |
27 | | #define BUILTIN(ID, TYPE, ATTRS) \ |
28 | | {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, |
29 | | #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ |
30 | | {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, |
31 | | #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ |
32 | | {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, |
33 | | #include "clang/Basic/BuiltinsX86.def" |
34 | | |
35 | | #define BUILTIN(ID, TYPE, ATTRS) \ |
36 | | {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, |
37 | | #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ |
38 | | {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, |
39 | | #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ |
40 | | {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, |
41 | | #include "clang/Basic/BuiltinsX86_64.def" |
42 | | }; |
43 | | |
44 | | static const char *const GCCRegNames[] = { |
45 | | "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", |
46 | | "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", |
47 | | "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", |
48 | | "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", |
49 | | "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", |
50 | | "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", |
51 | | "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", |
52 | | "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", |
53 | | "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", |
54 | | "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", |
55 | | "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", |
56 | | "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", |
57 | | "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", |
58 | | "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", |
59 | | "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", |
60 | | "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", |
61 | | "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", |
62 | | "k2", "k3", "k4", "k5", "k6", "k7", |
63 | | "cr0", "cr2", "cr3", "cr4", "cr8", |
64 | | "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", |
65 | | "bnd0", "bnd1", "bnd2", "bnd3", |
66 | | "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", |
67 | | }; |
68 | | |
69 | | const TargetInfo::AddlRegName AddlRegNames[] = { |
70 | | {{"al", "ah", "eax", "rax"}, 0}, |
71 | | {{"bl", "bh", "ebx", "rbx"}, 3}, |
72 | | {{"cl", "ch", "ecx", "rcx"}, 2}, |
73 | | {{"dl", "dh", "edx", "rdx"}, 1}, |
74 | | {{"esi", "rsi"}, 4}, |
75 | | {{"edi", "rdi"}, 5}, |
76 | | {{"esp", "rsp"}, 7}, |
77 | | {{"ebp", "rbp"}, 6}, |
78 | | {{"r8d", "r8w", "r8b"}, 38}, |
79 | | {{"r9d", "r9w", "r9b"}, 39}, |
80 | | {{"r10d", "r10w", "r10b"}, 40}, |
81 | | {{"r11d", "r11w", "r11b"}, 41}, |
82 | | {{"r12d", "r12w", "r12b"}, 42}, |
83 | | {{"r13d", "r13w", "r13b"}, 43}, |
84 | | {{"r14d", "r14w", "r14b"}, 44}, |
85 | | {{"r15d", "r15w", "r15b"}, 45}, |
86 | | }; |
87 | | |
88 | | } // namespace targets |
89 | | } // namespace clang |
90 | | |
91 | | using namespace clang; |
92 | | using namespace clang::targets; |
93 | | |
94 | 5 | bool X86TargetInfo::setFPMath(StringRef Name) { |
95 | 5 | if (Name == "387") { |
96 | 2 | FPMath = FP_387; |
97 | 2 | return true; |
98 | 2 | } |
99 | 3 | if (Name == "sse") { |
100 | 2 | FPMath = FP_SSE; |
101 | 2 | return true; |
102 | 2 | } |
103 | 1 | return false; |
104 | 3 | } |
105 | | |
106 | | bool X86TargetInfo::initFeatureMap( |
107 | | llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, |
108 | 148k | const std::vector<std::string> &FeaturesVec) const { |
109 | | // FIXME: This *really* should not be here. |
110 | | // X86_64 always has SSE2. |
111 | 148k | if (getTriple().getArch() == llvm::Triple::x86_64) |
112 | 125k | setFeatureEnabled(Features, "sse2", true); |
113 | | |
114 | 148k | using namespace llvm::X86; |
115 | | |
116 | 148k | SmallVector<StringRef, 16> CPUFeatures; |
117 | 148k | getFeaturesForCPU(CPU, CPUFeatures); |
118 | 148k | for (auto &F : CPUFeatures) |
119 | 614k | setFeatureEnabled(Features, F, true); |
120 | | |
121 | 148k | std::vector<std::string> UpdatedFeaturesVec; |
122 | 148k | std::vector<std::string> UpdatedAVX10FeaturesVec; |
123 | 148k | enum { FE_NOSET = -1, FE_FALSE, FE_TRUE }; |
124 | 148k | int HasEVEX512 = FE_NOSET; |
125 | 148k | bool HasAVX512F = false; |
126 | 148k | bool HasAVX10 = false; |
127 | 148k | bool HasAVX10_512 = false; |
128 | 148k | std::string LastAVX10; |
129 | 148k | std::string LastAVX512; |
130 | 209k | for (const auto &Feature : FeaturesVec) { |
131 | | // Expand general-regs-only to -x86, -mmx and -sse |
132 | 209k | if (Feature == "+general-regs-only") { |
133 | 30 | UpdatedFeaturesVec.push_back("-x87"); |
134 | 30 | UpdatedFeaturesVec.push_back("-mmx"); |
135 | 30 | UpdatedFeaturesVec.push_back("-sse"); |
136 | 30 | continue; |
137 | 30 | } |
138 | | |
139 | 209k | if (Feature.substr(1, 6) == "avx10.") { |
140 | 94 | if (Feature[0] == '+') { |
141 | 94 | HasAVX10 = true; |
142 | 94 | if (Feature.substr(Feature.size() - 3, 3) == "512") |
143 | 43 | HasAVX10_512 = true; |
144 | 94 | LastAVX10 = Feature; |
145 | 94 | } else if (0 HasAVX100 && Feature == "-avx10.1-256"0 ) { |
146 | 0 | HasAVX10 = false; |
147 | 0 | HasAVX10_512 = false; |
148 | 0 | } else if (HasAVX10_512 && Feature == "-avx10.1-512") { |
149 | 0 | HasAVX10_512 = false; |
150 | 0 | } |
151 | | // Postpone AVX10 features handling after AVX512 settled. |
152 | 94 | UpdatedAVX10FeaturesVec.push_back(Feature); |
153 | 94 | continue; |
154 | 209k | } else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512"101k ) { |
155 | 39.2k | HasAVX512F = true; |
156 | 39.2k | LastAVX512 = Feature; |
157 | 170k | } else if (HasAVX512F && Feature == "-avx512f"108k ) { |
158 | 4 | HasAVX512F = false; |
159 | 170k | } else if (HasEVEX512 != FE_TRUE && Feature == "+evex512"170k ) { |
160 | 16.7k | HasEVEX512 = FE_TRUE; |
161 | 16.7k | continue; |
162 | 153k | } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512"153k ) { |
163 | 33.7k | HasEVEX512 = FE_FALSE; |
164 | 33.7k | continue; |
165 | 33.7k | } |
166 | | |
167 | 158k | UpdatedFeaturesVec.push_back(Feature); |
168 | 158k | } |
169 | 148k | llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec); |
170 | | // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512 |
171 | | // according to other features. |
172 | 148k | if (HasAVX512F) { |
173 | 39.2k | UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512"21.7k |
174 | 39.2k | : "+evex512"17.5k ); |
175 | 39.2k | if (HasAVX10 && !HasAVX10_51249 && HasEVEX512 != FE_FALSE24 ) |
176 | 24 | Diags.Report(diag::warn_invalid_feature_combination) |
177 | 24 | << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512"; |
178 | 109k | } else if (HasAVX10) { |
179 | 45 | if (HasEVEX512 != FE_NOSET) |
180 | 1 | Diags.Report(diag::warn_invalid_feature_combination) |
181 | 1 | << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512"0 : " -evex512"); |
182 | 45 | UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512"18 : "-evex512"27 ); |
183 | 45 | } |
184 | | |
185 | 148k | if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) |
186 | 0 | return false; |
187 | | |
188 | | // Can't do this earlier because we need to be able to explicitly enable |
189 | | // or disable these features and the things that they depend upon. |
190 | | |
191 | | // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. |
192 | 148k | auto I = Features.find("sse4.2"); |
193 | 148k | if (I != Features.end() && I->getValue()50.3k && |
194 | 148k | !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")50.2k ) |
195 | 50.2k | Features["popcnt"] = true; |
196 | | |
197 | | // Additionally, if SSE is enabled and mmx is not explicitly disabled, |
198 | | // then enable MMX. |
199 | 148k | I = Features.find("sse"); |
200 | 148k | if (I != Features.end() && I->getValue()142k && |
201 | 148k | !llvm::is_contained(UpdatedFeaturesVec, "-mmx")142k ) |
202 | 142k | Features["mmx"] = true; |
203 | | |
204 | | // Enable xsave if avx is enabled and xsave is not explicitly disabled. |
205 | 148k | I = Features.find("avx"); |
206 | 148k | if (I != Features.end() && I->getValue()49.9k && |
207 | 148k | !llvm::is_contained(UpdatedFeaturesVec, "-xsave")49.8k ) |
208 | 49.8k | Features["xsave"] = true; |
209 | | |
210 | | // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. |
211 | 148k | I = Features.find("sse4.2"); |
212 | 148k | if (I != Features.end() && I->getValue()50.3k && |
213 | 148k | !llvm::is_contained(UpdatedFeaturesVec, "-crc32")50.2k ) |
214 | 50.2k | Features["crc32"] = true; |
215 | | |
216 | 148k | return true; |
217 | 148k | } |
218 | | |
219 | | void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, |
220 | 4.31M | StringRef Name, bool Enabled) const { |
221 | 4.31M | if (Name == "sse4") { |
222 | | // We can get here via the __target__ attribute since that's not controlled |
223 | | // via the -msse4/-mno-sse4 command line alias. Handle this the same way |
224 | | // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if |
225 | | // disabled. |
226 | 4 | if (Enabled) |
227 | 2 | Name = "sse4.2"; |
228 | 2 | else |
229 | 2 | Name = "sse4.1"; |
230 | 4 | } |
231 | | |
232 | 4.31M | Features[Name] = Enabled; |
233 | 4.31M | llvm::X86::updateImpliedFeatures(Name, Enabled, Features); |
234 | 4.31M | } |
235 | | |
236 | | /// handleTargetFeatures - Perform initialization based on the user |
237 | | /// configured set of features. |
238 | | bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, |
239 | 88.8k | DiagnosticsEngine &Diags) { |
240 | 611k | for (const auto &Feature : Features) { |
241 | 611k | if (Feature[0] != '+') |
242 | 3.73k | continue; |
243 | | |
244 | 608k | if (Feature == "+aes") { |
245 | 151 | HasAES = true; |
246 | 608k | } else if (Feature == "+vaes") { |
247 | 62 | HasVAES = true; |
248 | 608k | } else if (Feature == "+pclmul") { |
249 | 186 | HasPCLMUL = true; |
250 | 607k | } else if (Feature == "+vpclmulqdq") { |
251 | 62 | HasVPCLMULQDQ = true; |
252 | 607k | } else if (Feature == "+lzcnt") { |
253 | 154 | HasLZCNT = true; |
254 | 607k | } else if (Feature == "+rdrnd") { |
255 | 127 | HasRDRND = true; |
256 | 607k | } else if (Feature == "+fsgsbase") { |
257 | 123 | HasFSGSBASE = true; |
258 | 607k | } else if (Feature == "+bmi") { |
259 | 142 | HasBMI = true; |
260 | 607k | } else if (Feature == "+bmi2") { |
261 | 115 | HasBMI2 = true; |
262 | 607k | } else if (Feature == "+popcnt") { |
263 | 516 | HasPOPCNT = true; |
264 | 606k | } else if (Feature == "+rtm") { |
265 | 1 | HasRTM = true; |
266 | 606k | } else if (Feature == "+prfchw") { |
267 | 155 | HasPRFCHW = true; |
268 | 606k | } else if (Feature == "+rdseed") { |
269 | 107 | HasRDSEED = true; |
270 | 606k | } else if (Feature == "+adx") { |
271 | 100 | HasADX = true; |
272 | 606k | } else if (Feature == "+tbm") { |
273 | 11 | HasTBM = true; |
274 | 606k | } else if (Feature == "+lwp") { |
275 | 15 | HasLWP = true; |
276 | 606k | } else if (Feature == "+fma") { |
277 | 289 | HasFMA = true; |
278 | 605k | } else if (Feature == "+f16c") { |
279 | 313 | HasF16C = true; |
280 | 605k | } else if (Feature == "+gfni") { |
281 | 50 | HasGFNI = true; |
282 | 605k | } else if (Feature == "+evex512") { |
283 | 203 | HasEVEX512 = true; |
284 | 605k | } else if (Feature == "+avx10.1-256") { |
285 | 13 | HasAVX10_1 = true; |
286 | 605k | } else if (Feature == "+avx10.1-512") { |
287 | 5 | HasAVX10_1_512 = true; |
288 | 605k | } else if (Feature == "+avx512cd") { |
289 | 71 | HasAVX512CD = true; |
290 | 605k | } else if (Feature == "+avx512vpopcntdq") { |
291 | 39 | HasAVX512VPOPCNTDQ = true; |
292 | 605k | } else if (Feature == "+avx512vnni") { |
293 | 41 | HasAVX512VNNI = true; |
294 | 605k | } else if (Feature == "+avx512bf16") { |
295 | 30 | HasAVX512BF16 = true; |
296 | 605k | } else if (Feature == "+avx512er") { |
297 | 13 | HasAVX512ER = true; |
298 | 605k | } else if (Feature == "+avx512fp16") { |
299 | 49 | HasAVX512FP16 = true; |
300 | 49 | HasLegalHalfType = true; |
301 | 605k | } else if (Feature == "+avx512pf") { |
302 | 11 | HasAVX512PF = true; |
303 | 605k | } else if (Feature == "+avx512dq") { |
304 | 95 | HasAVX512DQ = true; |
305 | 604k | } else if (Feature == "+avx512bitalg") { |
306 | 37 | HasAVX512BITALG = true; |
307 | 604k | } else if (Feature == "+avx512bw") { |
308 | 112 | HasAVX512BW = true; |
309 | 604k | } else if (Feature == "+avx512vl") { |
310 | 117 | HasAVX512VL = true; |
311 | 604k | } else if (Feature == "+avx512vbmi") { |
312 | 40 | HasAVX512VBMI = true; |
313 | 604k | } else if (Feature == "+avx512vbmi2") { |
314 | 37 | HasAVX512VBMI2 = true; |
315 | 604k | } else if (Feature == "+avx512ifma") { |
316 | 40 | HasAVX512IFMA = true; |
317 | 604k | } else if (Feature == "+avx512vp2intersect") { |
318 | 7 | HasAVX512VP2INTERSECT = true; |
319 | 604k | } else if (Feature == "+sha") { |
320 | 66 | HasSHA = true; |
321 | 604k | } else if (Feature == "+sha512") { |
322 | 11 | HasSHA512 = true; |
323 | 604k | } else if (Feature == "+shstk") { |
324 | 41 | HasSHSTK = true; |
325 | 604k | } else if (Feature == "+sm3") { |
326 | 12 | HasSM3 = true; |
327 | 604k | } else if (Feature == "+sm4") { |
328 | 11 | HasSM4 = true; |
329 | 604k | } else if (Feature == "+movbe") { |
330 | 252 | HasMOVBE = true; |
331 | 604k | } else if (Feature == "+sgx") { |
332 | 57 | HasSGX = true; |
333 | 604k | } else if (Feature == "+cx8") { |
334 | 88.8k | HasCX8 = true; |
335 | 515k | } else if (Feature == "+cx16") { |
336 | 18.6k | HasCX16 = true; |
337 | 496k | } else if (Feature == "+fxsr") { |
338 | 38.2k | HasFXSR = true; |
339 | 458k | } else if (Feature == "+xsave") { |
340 | 475 | HasXSAVE = true; |
341 | 457k | } else if (Feature == "+xsaveopt") { |
342 | 164 | HasXSAVEOPT = true; |
343 | 457k | } else if (Feature == "+xsavec") { |
344 | 97 | HasXSAVEC = true; |
345 | 457k | } else if (Feature == "+xsaves") { |
346 | 97 | HasXSAVES = true; |
347 | 457k | } else if (Feature == "+mwaitx") { |
348 | 22 | HasMWAITX = true; |
349 | 457k | } else if (Feature == "+pku") { |
350 | 70 | HasPKU = true; |
351 | 457k | } else if (Feature == "+clflushopt") { |
352 | 91 | HasCLFLUSHOPT = true; |
353 | 457k | } else if (Feature == "+clwb") { |
354 | 70 | HasCLWB = true; |
355 | 457k | } else if (Feature == "+wbnoinvd") { |
356 | 27 | HasWBNOINVD = true; |
357 | 457k | } else if (Feature == "+prefetchi") { |
358 | 9 | HasPREFETCHI = true; |
359 | 457k | } else if (Feature == "+prefetchwt1") { |
360 | 11 | HasPREFETCHWT1 = true; |
361 | 457k | } else if (Feature == "+clzero") { |
362 | 20 | HasCLZERO = true; |
363 | 457k | } else if (Feature == "+cldemote") { |
364 | 35 | HasCLDEMOTE = true; |
365 | 457k | } else if (Feature == "+rdpid") { |
366 | 58 | HasRDPID = true; |
367 | 457k | } else if (Feature == "+rdpru") { |
368 | 15 | HasRDPRU = true; |
369 | 457k | } else if (Feature == "+kl") { |
370 | 28 | HasKL = true; |
371 | 457k | } else if (Feature == "+widekl") { |
372 | 27 | HasWIDEKL = true; |
373 | 457k | } else if (Feature == "+retpoline-external-thunk") { |
374 | 0 | HasRetpolineExternalThunk = true; |
375 | 457k | } else if (Feature == "+sahf") { |
376 | 18.6k | HasLAHFSAHF = true; |
377 | 438k | } else if (Feature == "+waitpkg") { |
378 | 32 | HasWAITPKG = true; |
379 | 438k | } else if (Feature == "+movdiri") { |
380 | 35 | HasMOVDIRI = true; |
381 | 438k | } else if (Feature == "+movdir64b") { |
382 | 35 | HasMOVDIR64B = true; |
383 | 438k | } else if (Feature == "+pconfig") { |
384 | 41 | HasPCONFIG = true; |
385 | 438k | } else if (Feature == "+ptwrite") { |
386 | 36 | HasPTWRITE = true; |
387 | 438k | } else if (Feature == "+invpcid") { |
388 | 100 | HasINVPCID = true; |
389 | 438k | } else if (Feature == "+enqcmd") { |
390 | 25 | HasENQCMD = true; |
391 | 438k | } else if (Feature == "+hreset") { |
392 | 31 | HasHRESET = true; |
393 | 438k | } else if (Feature == "+amx-bf16") { |
394 | 15 | HasAMXBF16 = true; |
395 | 438k | } else if (Feature == "+amx-fp16") { |
396 | 8 | HasAMXFP16 = true; |
397 | 438k | } else if (Feature == "+amx-int8") { |
398 | 14 | HasAMXINT8 = true; |
399 | 437k | } else if (Feature == "+amx-tile") { |
400 | 21 | HasAMXTILE = true; |
401 | 437k | } else if (Feature == "+amx-complex") { |
402 | 6 | HasAMXCOMPLEX = true; |
403 | 437k | } else if (Feature == "+cmpccxadd") { |
404 | 18 | HasCMPCCXADD = true; |
405 | 437k | } else if (Feature == "+raoint") { |
406 | 5 | HasRAOINT = true; |
407 | 437k | } else if (Feature == "+avxifma") { |
408 | 17 | HasAVXIFMA = true; |
409 | 437k | } else if (Feature == "+avxneconvert") { |
410 | 17 | HasAVXNECONVERT= true; |
411 | 437k | } else if (Feature == "+avxvnni") { |
412 | 33 | HasAVXVNNI = true; |
413 | 437k | } else if (Feature == "+avxvnniint16") { |
414 | 11 | HasAVXVNNIINT16 = true; |
415 | 437k | } else if (Feature == "+avxvnniint8") { |
416 | 17 | HasAVXVNNIINT8 = true; |
417 | 437k | } else if (Feature == "+serialize") { |
418 | 33 | HasSERIALIZE = true; |
419 | 437k | } else if (Feature == "+tsxldtrk") { |
420 | 11 | HasTSXLDTRK = true; |
421 | 437k | } else if (Feature == "+uintr") { |
422 | 24 | HasUINTR = true; |
423 | 437k | } else if (Feature == "+usermsr") { |
424 | 5 | HasUSERMSR = true; |
425 | 437k | } else if (Feature == "+crc32") { |
426 | 513 | HasCRC32 = true; |
427 | 437k | } else if (Feature == "+x87") { |
428 | 88.8k | HasX87 = true; |
429 | 348k | } else if (Feature == "+fullbf16") { |
430 | 18 | HasFullBFloat16 = true; |
431 | 18 | } |
432 | | |
433 | 608k | X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) |
434 | 608k | .Case("+avx512f", AVX512F) |
435 | 608k | .Case("+avx2", AVX2) |
436 | 608k | .Case("+avx", AVX) |
437 | 608k | .Case("+sse4.2", SSE42) |
438 | 608k | .Case("+sse4.1", SSE41) |
439 | 608k | .Case("+ssse3", SSSE3) |
440 | 608k | .Case("+sse3", SSE3) |
441 | 608k | .Case("+sse2", SSE2) |
442 | 608k | .Case("+sse", SSE1) |
443 | 608k | .Default(NoSSE); |
444 | 608k | SSELevel = std::max(SSELevel, Level); |
445 | | |
446 | 608k | HasFloat16 = SSELevel >= SSE2; |
447 | | |
448 | | // X86 target has bfloat16 emulation support in the backend, where |
449 | | // bfloat16 is treated as a 32-bit float, arithmetic operations are |
450 | | // performed in 32-bit, and the result is converted back to bfloat16. |
451 | | // Truncation and extension between bfloat16 and 32-bit float are supported |
452 | | // by the compiler-rt library. However, native bfloat16 support is currently |
453 | | // not available in the X86 target. Hence, HasFullBFloat16 will be false |
454 | | // until native bfloat16 support is available. HasFullBFloat16 is used to |
455 | | // determine whether to automatically use excess floating point precision |
456 | | // for bfloat16 arithmetic operations in the front-end. |
457 | 608k | HasBFloat16 = SSELevel >= SSE2; |
458 | | |
459 | 608k | MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) |
460 | 608k | .Case("+3dnowa", AMD3DNowAthlon) |
461 | 608k | .Case("+3dnow", AMD3DNow) |
462 | 608k | .Case("+mmx", MMX) |
463 | 608k | .Default(NoMMX3DNow); |
464 | 608k | MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); |
465 | | |
466 | 608k | XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) |
467 | 608k | .Case("+xop", XOP) |
468 | 608k | .Case("+fma4", FMA4) |
469 | 608k | .Case("+sse4a", SSE4A) |
470 | 608k | .Default(NoXOP); |
471 | 608k | XOPLevel = std::max(XOPLevel, XLevel); |
472 | 608k | } |
473 | | |
474 | | // LLVM doesn't have a separate switch for fpmath, so only accept it if it |
475 | | // matches the selected sse level. |
476 | 88.8k | if ((FPMath == FP_SSE && SSELevel < SSE12 ) || |
477 | 88.8k | (88.8k FPMath == FP_38788.8k && SSELevel >= SSE12 )) { |
478 | 2 | Diags.Report(diag::err_target_unsupported_fpmath) |
479 | 2 | << (FPMath == FP_SSE ? "sse"1 : "387"1 ); |
480 | 2 | return false; |
481 | 2 | } |
482 | | |
483 | | // FIXME: We should allow long double type on 32-bits to match with GCC. |
484 | | // This requires backend to be able to lower f80 without x87 first. |
485 | 88.8k | if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()34 ) |
486 | 34 | HasLongDouble = false; |
487 | | |
488 | 88.8k | return true; |
489 | 88.8k | } |
490 | | |
491 | | /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro |
492 | | /// definitions for this particular subtarget. |
493 | | void X86TargetInfo::getTargetDefines(const LangOptions &Opts, |
494 | 81.7k | MacroBuilder &Builder) const { |
495 | | // Inline assembly supports X86 flag outputs. |
496 | 81.7k | Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); |
497 | | |
498 | 81.7k | std::string CodeModel = getTargetOpts().CodeModel; |
499 | 81.7k | if (CodeModel == "default") |
500 | 68.6k | CodeModel = "small"; |
501 | 81.7k | Builder.defineMacro("__code_model_" + CodeModel + "__"); |
502 | | |
503 | | // Target identification. |
504 | 81.7k | if (getTriple().getArch() == llvm::Triple::x86_64) { |
505 | 66.2k | Builder.defineMacro("__amd64__"); |
506 | 66.2k | Builder.defineMacro("__amd64"); |
507 | 66.2k | Builder.defineMacro("__x86_64"); |
508 | 66.2k | Builder.defineMacro("__x86_64__"); |
509 | 66.2k | if (getTriple().getArchName() == "x86_64h") { |
510 | 4 | Builder.defineMacro("__x86_64h"); |
511 | 4 | Builder.defineMacro("__x86_64h__"); |
512 | 4 | } |
513 | 66.2k | } else { |
514 | 15.4k | DefineStd(Builder, "i386", Opts); |
515 | 15.4k | } |
516 | | |
517 | 81.7k | Builder.defineMacro("__SEG_GS"); |
518 | 81.7k | Builder.defineMacro("__SEG_FS"); |
519 | 81.7k | Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); |
520 | 81.7k | Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); |
521 | | |
522 | | // Subtarget options. |
523 | | // FIXME: We are hard-coding the tune parameters based on the CPU, but they |
524 | | // truly should be based on -mtune options. |
525 | 81.7k | using namespace llvm::X86; |
526 | 81.7k | switch (CPU) { |
527 | 43.8k | case CK_None: |
528 | 43.8k | break; |
529 | 33 | case CK_i386: |
530 | | // The rest are coming from the i386 define above. |
531 | 33 | Builder.defineMacro("__tune_i386__"); |
532 | 33 | break; |
533 | 6 | case CK_i486: |
534 | 7 | case CK_WinChipC6: |
535 | 8 | case CK_WinChip2: |
536 | 9 | case CK_C3: |
537 | 9 | defineCPUMacros(Builder, "i486"); |
538 | 9 | break; |
539 | 2 | case CK_PentiumMMX: |
540 | 2 | Builder.defineMacro("__pentium_mmx__"); |
541 | 2 | Builder.defineMacro("__tune_pentium_mmx__"); |
542 | 2 | [[fallthrough]]; |
543 | 4 | case CK_i586: |
544 | 8 | case CK_Pentium: |
545 | 8 | defineCPUMacros(Builder, "i586"); |
546 | 8 | defineCPUMacros(Builder, "pentium"); |
547 | 8 | break; |
548 | 4 | case CK_Pentium3: |
549 | 8 | case CK_PentiumM: |
550 | 8 | Builder.defineMacro("__tune_pentium3__"); |
551 | 8 | [[fallthrough]]; |
552 | 9 | case CK_Pentium2: |
553 | 10 | case CK_C3_2: |
554 | 10 | Builder.defineMacro("__tune_pentium2__"); |
555 | 10 | [[fallthrough]]; |
556 | 20 | case CK_PentiumPro: |
557 | 36 | case CK_i686: |
558 | 36 | defineCPUMacros(Builder, "i686"); |
559 | 36 | defineCPUMacros(Builder, "pentiumpro"); |
560 | 36 | break; |
561 | 10.2k | case CK_Pentium4: |
562 | 10.2k | defineCPUMacros(Builder, "pentium4"); |
563 | 10.2k | break; |
564 | 10 | case CK_Yonah: |
565 | 11 | case CK_Prescott: |
566 | 14 | case CK_Nocona: |
567 | 14 | defineCPUMacros(Builder, "nocona"); |
568 | 14 | break; |
569 | 179 | case CK_Core2: |
570 | 17.9k | case CK_Penryn: |
571 | 17.9k | defineCPUMacros(Builder, "core2"); |
572 | 17.9k | break; |
573 | 104 | case CK_Bonnell: |
574 | 104 | defineCPUMacros(Builder, "atom"); |
575 | 104 | break; |
576 | 6 | case CK_Silvermont: |
577 | 6 | defineCPUMacros(Builder, "slm"); |
578 | 6 | break; |
579 | 2 | case CK_Goldmont: |
580 | 2 | defineCPUMacros(Builder, "goldmont"); |
581 | 2 | break; |
582 | 2 | case CK_GoldmontPlus: |
583 | 2 | defineCPUMacros(Builder, "goldmont_plus"); |
584 | 2 | break; |
585 | 2 | case CK_Tremont: |
586 | 2 | defineCPUMacros(Builder, "tremont"); |
587 | 2 | break; |
588 | | // Gracemont and later atom-cores use P-core cpu macros. |
589 | 2 | case CK_Gracemont: |
590 | 19 | case CK_Nehalem: |
591 | 22 | case CK_Westmere: |
592 | 32 | case CK_SandyBridge: |
593 | 37 | case CK_IvyBridge: |
594 | 47 | case CK_Haswell: |
595 | 51 | case CK_Broadwell: |
596 | 55 | case CK_SkylakeClient: |
597 | 71 | case CK_SkylakeServer: |
598 | 73 | case CK_Cascadelake: |
599 | 75 | case CK_Cooperlake: |
600 | 78 | case CK_Cannonlake: |
601 | 81 | case CK_IcelakeClient: |
602 | 83 | case CK_Rocketlake: |
603 | 86 | case CK_IcelakeServer: |
604 | 88 | case CK_Tigerlake: |
605 | 90 | case CK_SapphireRapids: |
606 | 92 | case CK_Alderlake: |
607 | 94 | case CK_Raptorlake: |
608 | 96 | case CK_Meteorlake: |
609 | 98 | case CK_Arrowlake: |
610 | 100 | case CK_ArrowlakeS: |
611 | 106 | case CK_Lunarlake: |
612 | 106 | case CK_Pantherlake: |
613 | 108 | case CK_Sierraforest: |
614 | 110 | case CK_Grandridge: |
615 | 112 | case CK_Graniterapids: |
616 | 114 | case CK_GraniterapidsD: |
617 | 116 | case CK_Emeraldrapids: |
618 | 116 | case CK_Clearwaterforest: |
619 | | // FIXME: Historically, we defined this legacy name, it would be nice to |
620 | | // remove it at some point. We've never exposed fine-grained names for |
621 | | // recent primary x86 CPUs, and we should keep it that way. |
622 | 116 | defineCPUMacros(Builder, "corei7"); |
623 | 116 | break; |
624 | 8 | case CK_KNL: |
625 | 8 | defineCPUMacros(Builder, "knl"); |
626 | 8 | break; |
627 | 3 | case CK_KNM: |
628 | 3 | break; |
629 | 1 | case CK_Lakemont: |
630 | 1 | defineCPUMacros(Builder, "i586", /*Tuning*/false); |
631 | 1 | defineCPUMacros(Builder, "pentium", /*Tuning*/false); |
632 | 1 | Builder.defineMacro("__tune_lakemont__"); |
633 | 1 | break; |
634 | 1 | case CK_K6_2: |
635 | 1 | Builder.defineMacro("__k6_2__"); |
636 | 1 | Builder.defineMacro("__tune_k6_2__"); |
637 | 1 | [[fallthrough]]; |
638 | 2 | case CK_K6_3: |
639 | 2 | if (CPU != CK_K6_2) { // In case of fallthrough |
640 | | // FIXME: GCC may be enabling these in cases where some other k6 |
641 | | // architecture is specified but -m3dnow is explicitly provided. The |
642 | | // exact semantics need to be determined and emulated here. |
643 | 1 | Builder.defineMacro("__k6_3__"); |
644 | 1 | Builder.defineMacro("__tune_k6_3__"); |
645 | 1 | } |
646 | 2 | [[fallthrough]]; |
647 | 3 | case CK_K6: |
648 | 3 | defineCPUMacros(Builder, "k6"); |
649 | 3 | break; |
650 | 2 | case CK_Athlon: |
651 | 5 | case CK_AthlonXP: |
652 | 5 | defineCPUMacros(Builder, "athlon"); |
653 | 5 | if (SSELevel != NoSSE) { |
654 | 3 | Builder.defineMacro("__athlon_sse__"); |
655 | 3 | Builder.defineMacro("__tune_athlon_sse__"); |
656 | 3 | } |
657 | 5 | break; |
658 | 12 | case CK_K8: |
659 | 21 | case CK_K8SSE3: |
660 | 9.19k | case CK_x86_64: |
661 | 9.19k | defineCPUMacros(Builder, "k8"); |
662 | 9.19k | break; |
663 | 1 | case CK_x86_64_v2: |
664 | 2 | case CK_x86_64_v3: |
665 | 3 | case CK_x86_64_v4: |
666 | 3 | break; |
667 | 4 | case CK_AMDFAM10: |
668 | 4 | defineCPUMacros(Builder, "amdfam10"); |
669 | 4 | break; |
670 | 4 | case CK_BTVER1: |
671 | 4 | defineCPUMacros(Builder, "btver1"); |
672 | 4 | break; |
673 | 19 | case CK_BTVER2: |
674 | 19 | defineCPUMacros(Builder, "btver2"); |
675 | 19 | break; |
676 | 4 | case CK_BDVER1: |
677 | 4 | defineCPUMacros(Builder, "bdver1"); |
678 | 4 | break; |
679 | 4 | case CK_BDVER2: |
680 | 4 | defineCPUMacros(Builder, "bdver2"); |
681 | 4 | break; |
682 | 3 | case CK_BDVER3: |
683 | 3 | defineCPUMacros(Builder, "bdver3"); |
684 | 3 | break; |
685 | 3 | case CK_BDVER4: |
686 | 3 | defineCPUMacros(Builder, "bdver4"); |
687 | 3 | break; |
688 | 4 | case CK_ZNVER1: |
689 | 4 | defineCPUMacros(Builder, "znver1"); |
690 | 4 | break; |
691 | 6 | case CK_ZNVER2: |
692 | 6 | defineCPUMacros(Builder, "znver2"); |
693 | 6 | break; |
694 | 3 | case CK_ZNVER3: |
695 | 3 | defineCPUMacros(Builder, "znver3"); |
696 | 3 | break; |
697 | 3 | case CK_ZNVER4: |
698 | 3 | defineCPUMacros(Builder, "znver4"); |
699 | 3 | break; |
700 | 1 | case CK_Geode: |
701 | 1 | defineCPUMacros(Builder, "geode"); |
702 | 1 | break; |
703 | 81.7k | } |
704 | | |
705 | | // Target properties. |
706 | 81.7k | Builder.defineMacro("__REGISTER_PREFIX__", ""); |
707 | | |
708 | | // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline |
709 | | // functions in glibc header files that use FP Stack inline asm which the |
710 | | // backend can't deal with (PR879). |
711 | 81.7k | Builder.defineMacro("__NO_MATH_INLINES"); |
712 | | |
713 | 81.7k | if (HasAES) |
714 | 149 | Builder.defineMacro("__AES__"); |
715 | | |
716 | 81.7k | if (HasVAES) |
717 | 62 | Builder.defineMacro("__VAES__"); |
718 | | |
719 | 81.7k | if (HasPCLMUL) |
720 | 184 | Builder.defineMacro("__PCLMUL__"); |
721 | | |
722 | 81.7k | if (HasVPCLMULQDQ) |
723 | 62 | Builder.defineMacro("__VPCLMULQDQ__"); |
724 | | |
725 | | // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, |
726 | | // the feature flag only applies to 64-bit mode. |
727 | 81.7k | if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x8663.4k ) |
728 | 33.4k | Builder.defineMacro("__LAHF_SAHF__"); |
729 | | |
730 | 81.7k | if (HasLZCNT) |
731 | 152 | Builder.defineMacro("__LZCNT__"); |
732 | | |
733 | 81.7k | if (HasRDRND) |
734 | 127 | Builder.defineMacro("__RDRND__"); |
735 | | |
736 | 81.7k | if (HasFSGSBASE) |
737 | 123 | Builder.defineMacro("__FSGSBASE__"); |
738 | | |
739 | 81.7k | if (HasBMI) |
740 | 140 | Builder.defineMacro("__BMI__"); |
741 | | |
742 | 81.7k | if (HasBMI2) |
743 | 115 | Builder.defineMacro("__BMI2__"); |
744 | | |
745 | 81.7k | if (HasPOPCNT) |
746 | 514 | Builder.defineMacro("__POPCNT__"); |
747 | | |
748 | 81.7k | if (HasRTM) |
749 | 1 | Builder.defineMacro("__RTM__"); |
750 | | |
751 | 81.7k | if (HasPRFCHW) |
752 | 153 | Builder.defineMacro("__PRFCHW__"); |
753 | | |
754 | 81.7k | if (HasRDSEED) |
755 | 107 | Builder.defineMacro("__RDSEED__"); |
756 | | |
757 | 81.7k | if (HasADX) |
758 | 100 | Builder.defineMacro("__ADX__"); |
759 | | |
760 | 81.7k | if (HasTBM) |
761 | 11 | Builder.defineMacro("__TBM__"); |
762 | | |
763 | 81.7k | if (HasLWP) |
764 | 15 | Builder.defineMacro("__LWP__"); |
765 | | |
766 | 81.7k | if (HasMWAITX) |
767 | 22 | Builder.defineMacro("__MWAITX__"); |
768 | | |
769 | 81.7k | if (HasMOVBE) |
770 | 250 | Builder.defineMacro("__MOVBE__"); |
771 | | |
772 | 81.7k | switch (XOPLevel) { |
773 | 22 | case XOP: |
774 | 22 | Builder.defineMacro("__XOP__"); |
775 | 22 | [[fallthrough]]; |
776 | 24 | case FMA4: |
777 | 24 | Builder.defineMacro("__FMA4__"); |
778 | 24 | [[fallthrough]]; |
779 | 68 | case SSE4A: |
780 | 68 | Builder.defineMacro("__SSE4A__"); |
781 | 68 | [[fallthrough]]; |
782 | 81.7k | case NoXOP: |
783 | 81.7k | break; |
784 | 81.7k | } |
785 | | |
786 | 81.7k | if (HasFMA) |
787 | 289 | Builder.defineMacro("__FMA__"); |
788 | | |
789 | 81.7k | if (HasF16C) |
790 | 311 | Builder.defineMacro("__F16C__"); |
791 | | |
792 | 81.7k | if (HasGFNI) |
793 | 50 | Builder.defineMacro("__GFNI__"); |
794 | | |
795 | 81.7k | if (HasEVEX512) |
796 | 203 | Builder.defineMacro("__EVEX512__"); |
797 | 81.7k | if (HasAVX10_1) |
798 | 13 | Builder.defineMacro("__AVX10_1__"); |
799 | 81.7k | if (HasAVX10_1_512) |
800 | 5 | Builder.defineMacro("__AVX10_1_512__"); |
801 | 81.7k | if (HasAVX512CD) |
802 | 71 | Builder.defineMacro("__AVX512CD__"); |
803 | 81.7k | if (HasAVX512VPOPCNTDQ) |
804 | 39 | Builder.defineMacro("__AVX512VPOPCNTDQ__"); |
805 | 81.7k | if (HasAVX512VNNI) |
806 | 41 | Builder.defineMacro("__AVX512VNNI__"); |
807 | 81.7k | if (HasAVX512BF16) |
808 | 30 | Builder.defineMacro("__AVX512BF16__"); |
809 | 81.7k | if (HasAVX512ER) |
810 | 13 | Builder.defineMacro("__AVX512ER__"); |
811 | 81.7k | if (HasAVX512FP16) |
812 | 49 | Builder.defineMacro("__AVX512FP16__"); |
813 | 81.7k | if (HasAVX512PF) |
814 | 11 | Builder.defineMacro("__AVX512PF__"); |
815 | 81.7k | if (HasAVX512DQ) |
816 | 95 | Builder.defineMacro("__AVX512DQ__"); |
817 | 81.7k | if (HasAVX512BITALG) |
818 | 37 | Builder.defineMacro("__AVX512BITALG__"); |
819 | 81.7k | if (HasAVX512BW) |
820 | 112 | Builder.defineMacro("__AVX512BW__"); |
821 | 81.7k | if (HasAVX512VL) { |
822 | 117 | Builder.defineMacro("__AVX512VL__"); |
823 | 117 | Builder.defineMacro("__EVEX256__"); |
824 | 117 | } |
825 | 81.7k | if (HasAVX512VBMI) |
826 | 40 | Builder.defineMacro("__AVX512VBMI__"); |
827 | 81.7k | if (HasAVX512VBMI2) |
828 | 37 | Builder.defineMacro("__AVX512VBMI2__"); |
829 | 81.7k | if (HasAVX512IFMA) |
830 | 40 | Builder.defineMacro("__AVX512IFMA__"); |
831 | 81.7k | if (HasAVX512VP2INTERSECT) |
832 | 7 | Builder.defineMacro("__AVX512VP2INTERSECT__"); |
833 | 81.7k | if (HasSHA) |
834 | 66 | Builder.defineMacro("__SHA__"); |
835 | 81.7k | if (HasSHA512) |
836 | 11 | Builder.defineMacro("__SHA512__"); |
837 | | |
838 | 81.7k | if (HasFXSR) |
839 | 37.7k | Builder.defineMacro("__FXSR__"); |
840 | 81.7k | if (HasXSAVE) |
841 | 473 | Builder.defineMacro("__XSAVE__"); |
842 | 81.7k | if (HasXSAVEOPT) |
843 | 162 | Builder.defineMacro("__XSAVEOPT__"); |
844 | 81.7k | if (HasXSAVEC) |
845 | 97 | Builder.defineMacro("__XSAVEC__"); |
846 | 81.7k | if (HasXSAVES) |
847 | 97 | Builder.defineMacro("__XSAVES__"); |
848 | 81.7k | if (HasPKU) |
849 | 70 | Builder.defineMacro("__PKU__"); |
850 | 81.7k | if (HasCLFLUSHOPT) |
851 | 91 | Builder.defineMacro("__CLFLUSHOPT__"); |
852 | 81.7k | if (HasCLWB) |
853 | 70 | Builder.defineMacro("__CLWB__"); |
854 | 81.7k | if (HasWBNOINVD) |
855 | 27 | Builder.defineMacro("__WBNOINVD__"); |
856 | 81.7k | if (HasSHSTK) |
857 | 41 | Builder.defineMacro("__SHSTK__"); |
858 | 81.7k | if (HasSGX) |
859 | 57 | Builder.defineMacro("__SGX__"); |
860 | 81.7k | if (HasSM3) |
861 | 12 | Builder.defineMacro("__SM3__"); |
862 | 81.7k | if (HasSM4) |
863 | 11 | Builder.defineMacro("__SM4__"); |
864 | 81.7k | if (HasPREFETCHI) |
865 | 9 | Builder.defineMacro("__PREFETCHI__"); |
866 | 81.7k | if (HasPREFETCHWT1) |
867 | 11 | Builder.defineMacro("__PREFETCHWT1__"); |
868 | 81.7k | if (HasCLZERO) |
869 | 20 | Builder.defineMacro("__CLZERO__"); |
870 | 81.7k | if (HasKL) |
871 | 28 | Builder.defineMacro("__KL__"); |
872 | 81.7k | if (HasWIDEKL) |
873 | 27 | Builder.defineMacro("__WIDEKL__"); |
874 | 81.7k | if (HasRDPID) |
875 | 58 | Builder.defineMacro("__RDPID__"); |
876 | 81.7k | if (HasRDPRU) |
877 | 15 | Builder.defineMacro("__RDPRU__"); |
878 | 81.7k | if (HasCLDEMOTE) |
879 | 35 | Builder.defineMacro("__CLDEMOTE__"); |
880 | 81.7k | if (HasWAITPKG) |
881 | 32 | Builder.defineMacro("__WAITPKG__"); |
882 | 81.7k | if (HasMOVDIRI) |
883 | 35 | Builder.defineMacro("__MOVDIRI__"); |
884 | 81.7k | if (HasMOVDIR64B) |
885 | 35 | Builder.defineMacro("__MOVDIR64B__"); |
886 | 81.7k | if (HasPCONFIG) |
887 | 41 | Builder.defineMacro("__PCONFIG__"); |
888 | 81.7k | if (HasPTWRITE) |
889 | 36 | Builder.defineMacro("__PTWRITE__"); |
890 | 81.7k | if (HasINVPCID) |
891 | 100 | Builder.defineMacro("__INVPCID__"); |
892 | 81.7k | if (HasENQCMD) |
893 | 25 | Builder.defineMacro("__ENQCMD__"); |
894 | 81.7k | if (HasHRESET) |
895 | 31 | Builder.defineMacro("__HRESET__"); |
896 | 81.7k | if (HasAMXTILE) |
897 | 21 | Builder.defineMacro("__AMX_TILE__"); |
898 | 81.7k | if (HasAMXINT8) |
899 | 14 | Builder.defineMacro("__AMX_INT8__"); |
900 | 81.7k | if (HasAMXBF16) |
901 | 15 | Builder.defineMacro("__AMX_BF16__"); |
902 | 81.7k | if (HasAMXFP16) |
903 | 8 | Builder.defineMacro("__AMX_FP16__"); |
904 | 81.7k | if (HasAMXCOMPLEX) |
905 | 6 | Builder.defineMacro("__AMX_COMPLEX__"); |
906 | 81.7k | if (HasCMPCCXADD) |
907 | 18 | Builder.defineMacro("__CMPCCXADD__"); |
908 | 81.7k | if (HasRAOINT) |
909 | 5 | Builder.defineMacro("__RAOINT__"); |
910 | 81.7k | if (HasAVXIFMA) |
911 | 17 | Builder.defineMacro("__AVXIFMA__"); |
912 | 81.7k | if (HasAVXNECONVERT) |
913 | 17 | Builder.defineMacro("__AVXNECONVERT__"); |
914 | 81.7k | if (HasAVXVNNI) |
915 | 33 | Builder.defineMacro("__AVXVNNI__"); |
916 | 81.7k | if (HasAVXVNNIINT16) |
917 | 11 | Builder.defineMacro("__AVXVNNIINT16__"); |
918 | 81.7k | if (HasAVXVNNIINT8) |
919 | 17 | Builder.defineMacro("__AVXVNNIINT8__"); |
920 | 81.7k | if (HasSERIALIZE) |
921 | 33 | Builder.defineMacro("__SERIALIZE__"); |
922 | 81.7k | if (HasTSXLDTRK) |
923 | 11 | Builder.defineMacro("__TSXLDTRK__"); |
924 | 81.7k | if (HasUINTR) |
925 | 24 | Builder.defineMacro("__UINTR__"); |
926 | 81.7k | if (HasUSERMSR) |
927 | 5 | Builder.defineMacro("__USERMSR__"); |
928 | 81.7k | if (HasCRC32) |
929 | 511 | Builder.defineMacro("__CRC32__"); |
930 | | |
931 | | // Each case falls through to the previous one here. |
932 | 81.7k | switch (SSELevel) { |
933 | 217 | case AVX512F: |
934 | 217 | Builder.defineMacro("__AVX512F__"); |
935 | 217 | [[fallthrough]]; |
936 | 315 | case AVX2: |
937 | 315 | Builder.defineMacro("__AVX2__"); |
938 | 315 | [[fallthrough]]; |
939 | 439 | case AVX: |
940 | 439 | Builder.defineMacro("__AVX__"); |
941 | 439 | [[fallthrough]]; |
942 | 499 | case SSE42: |
943 | 499 | Builder.defineMacro("__SSE4_2__"); |
944 | 499 | [[fallthrough]]; |
945 | 18.2k | case SSE41: |
946 | 18.2k | Builder.defineMacro("__SSE4_1__"); |
947 | 18.2k | [[fallthrough]]; |
948 | 18.4k | case SSSE3: |
949 | 18.4k | Builder.defineMacro("__SSSE3__"); |
950 | 18.4k | [[fallthrough]]; |
951 | 18.5k | case SSE3: |
952 | 18.5k | Builder.defineMacro("__SSE3__"); |
953 | 18.5k | [[fallthrough]]; |
954 | 76.8k | case SSE2: |
955 | 76.8k | Builder.defineMacro("__SSE2__"); |
956 | 76.8k | Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. |
957 | 76.8k | [[fallthrough]]; |
958 | 76.8k | case SSE1: |
959 | 76.8k | Builder.defineMacro("__SSE__"); |
960 | 76.8k | Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. |
961 | 76.8k | [[fallthrough]]; |
962 | 81.7k | case NoSSE: |
963 | 81.7k | break; |
964 | 81.7k | } |
965 | | |
966 | 81.7k | if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x8611.8k ) { |
967 | 360 | switch (SSELevel) { |
968 | 2 | case AVX512F: |
969 | 4 | case AVX2: |
970 | 6 | case AVX: |
971 | 6 | case SSE42: |
972 | 6 | case SSE41: |
973 | 6 | case SSSE3: |
974 | 6 | case SSE3: |
975 | 66 | case SSE2: |
976 | 66 | Builder.defineMacro("_M_IX86_FP", Twine(2)); |
977 | 66 | break; |
978 | 2 | case SSE1: |
979 | 2 | Builder.defineMacro("_M_IX86_FP", Twine(1)); |
980 | 2 | break; |
981 | 292 | default: |
982 | 292 | Builder.defineMacro("_M_IX86_FP", Twine(0)); |
983 | 292 | break; |
984 | 360 | } |
985 | 360 | } |
986 | | |
987 | | // Each case falls through to the previous one here. |
988 | 81.7k | switch (MMX3DNowLevel) { |
989 | 34 | case AMD3DNowAthlon: |
990 | 34 | Builder.defineMacro("__3dNOW_A__"); |
991 | 34 | [[fallthrough]]; |
992 | 40 | case AMD3DNow: |
993 | 40 | Builder.defineMacro("__3dNOW__"); |
994 | 40 | [[fallthrough]]; |
995 | 76.8k | case MMX: |
996 | 76.8k | Builder.defineMacro("__MMX__"); |
997 | 76.8k | [[fallthrough]]; |
998 | 81.7k | case NoMMX3DNow: |
999 | 81.7k | break; |
1000 | 81.7k | } |
1001 | | |
1002 | 81.7k | if (CPU >= CK_i486 || CPU == CK_None43.9k ) { |
1003 | 81.6k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); |
1004 | 81.6k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); |
1005 | 81.6k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); |
1006 | 81.6k | } |
1007 | 81.7k | if (HasCX8) |
1008 | 81.6k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); |
1009 | 81.7k | if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_6418.2k ) |
1010 | 18.0k | Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); |
1011 | | |
1012 | 81.7k | if (HasFloat128) |
1013 | 4.71k | Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); |
1014 | 81.7k | } |
1015 | | |
1016 | 3.50M | bool X86TargetInfo::isValidFeatureName(StringRef Name) const { |
1017 | 3.50M | return llvm::StringSwitch<bool>(Name) |
1018 | 3.50M | .Case("3dnow", true) |
1019 | 3.50M | .Case("3dnowa", true) |
1020 | 3.50M | .Case("adx", true) |
1021 | 3.50M | .Case("aes", true) |
1022 | 3.50M | .Case("amx-bf16", true) |
1023 | 3.50M | .Case("amx-complex", true) |
1024 | 3.50M | .Case("amx-fp16", true) |
1025 | 3.50M | .Case("amx-int8", true) |
1026 | 3.50M | .Case("amx-tile", true) |
1027 | 3.50M | .Case("avx", true) |
1028 | 3.50M | .Case("avx10.1-256", true) |
1029 | 3.50M | .Case("avx10.1-512", true) |
1030 | 3.50M | .Case("avx2", true) |
1031 | 3.50M | .Case("avx512f", true) |
1032 | 3.50M | .Case("avx512cd", true) |
1033 | 3.50M | .Case("avx512vpopcntdq", true) |
1034 | 3.50M | .Case("avx512vnni", true) |
1035 | 3.50M | .Case("avx512bf16", true) |
1036 | 3.50M | .Case("avx512er", true) |
1037 | 3.50M | .Case("avx512fp16", true) |
1038 | 3.50M | .Case("avx512pf", true) |
1039 | 3.50M | .Case("avx512dq", true) |
1040 | 3.50M | .Case("avx512bitalg", true) |
1041 | 3.50M | .Case("avx512bw", true) |
1042 | 3.50M | .Case("avx512vl", true) |
1043 | 3.50M | .Case("avx512vbmi", true) |
1044 | 3.50M | .Case("avx512vbmi2", true) |
1045 | 3.50M | .Case("avx512ifma", true) |
1046 | 3.50M | .Case("avx512vp2intersect", true) |
1047 | 3.50M | .Case("avxifma", true) |
1048 | 3.50M | .Case("avxneconvert", true) |
1049 | 3.50M | .Case("avxvnni", true) |
1050 | 3.50M | .Case("avxvnniint16", true) |
1051 | 3.50M | .Case("avxvnniint8", true) |
1052 | 3.50M | .Case("bmi", true) |
1053 | 3.50M | .Case("bmi2", true) |
1054 | 3.50M | .Case("cldemote", true) |
1055 | 3.50M | .Case("clflushopt", true) |
1056 | 3.50M | .Case("clwb", true) |
1057 | 3.50M | .Case("clzero", true) |
1058 | 3.50M | .Case("cmpccxadd", true) |
1059 | 3.50M | .Case("crc32", true) |
1060 | 3.50M | .Case("cx16", true) |
1061 | 3.50M | .Case("enqcmd", true) |
1062 | 3.50M | .Case("evex512", true) |
1063 | 3.50M | .Case("f16c", true) |
1064 | 3.50M | .Case("fma", true) |
1065 | 3.50M | .Case("fma4", true) |
1066 | 3.50M | .Case("fsgsbase", true) |
1067 | 3.50M | .Case("fxsr", true) |
1068 | 3.50M | .Case("general-regs-only", true) |
1069 | 3.50M | .Case("gfni", true) |
1070 | 3.50M | .Case("hreset", true) |
1071 | 3.50M | .Case("invpcid", true) |
1072 | 3.50M | .Case("kl", true) |
1073 | 3.50M | .Case("widekl", true) |
1074 | 3.50M | .Case("lwp", true) |
1075 | 3.50M | .Case("lzcnt", true) |
1076 | 3.50M | .Case("mmx", true) |
1077 | 3.50M | .Case("movbe", true) |
1078 | 3.50M | .Case("movdiri", true) |
1079 | 3.50M | .Case("movdir64b", true) |
1080 | 3.50M | .Case("mwaitx", true) |
1081 | 3.50M | .Case("pclmul", true) |
1082 | 3.50M | .Case("pconfig", true) |
1083 | 3.50M | .Case("pku", true) |
1084 | 3.50M | .Case("popcnt", true) |
1085 | 3.50M | .Case("prefetchi", true) |
1086 | 3.50M | .Case("prefetchwt1", true) |
1087 | 3.50M | .Case("prfchw", true) |
1088 | 3.50M | .Case("ptwrite", true) |
1089 | 3.50M | .Case("raoint", true) |
1090 | 3.50M | .Case("rdpid", true) |
1091 | 3.50M | .Case("rdpru", true) |
1092 | 3.50M | .Case("rdrnd", true) |
1093 | 3.50M | .Case("rdseed", true) |
1094 | 3.50M | .Case("rtm", true) |
1095 | 3.50M | .Case("sahf", true) |
1096 | 3.50M | .Case("serialize", true) |
1097 | 3.50M | .Case("sgx", true) |
1098 | 3.50M | .Case("sha", true) |
1099 | 3.50M | .Case("sha512", true) |
1100 | 3.50M | .Case("shstk", true) |
1101 | 3.50M | .Case("sm3", true) |
1102 | 3.50M | .Case("sm4", true) |
1103 | 3.50M | .Case("sse", true) |
1104 | 3.50M | .Case("sse2", true) |
1105 | 3.50M | .Case("sse3", true) |
1106 | 3.50M | .Case("ssse3", true) |
1107 | 3.50M | .Case("sse4", true) |
1108 | 3.50M | .Case("sse4.1", true) |
1109 | 3.50M | .Case("sse4.2", true) |
1110 | 3.50M | .Case("sse4a", true) |
1111 | 3.50M | .Case("tbm", true) |
1112 | 3.50M | .Case("tsxldtrk", true) |
1113 | 3.50M | .Case("uintr", true) |
1114 | 3.50M | .Case("usermsr", true) |
1115 | 3.50M | .Case("vaes", true) |
1116 | 3.50M | .Case("vpclmulqdq", true) |
1117 | 3.50M | .Case("wbnoinvd", true) |
1118 | 3.50M | .Case("waitpkg", true) |
1119 | 3.50M | .Case("x87", true) |
1120 | 3.50M | .Case("xop", true) |
1121 | 3.50M | .Case("xsave", true) |
1122 | 3.50M | .Case("xsavec", true) |
1123 | 3.50M | .Case("xsaves", true) |
1124 | 3.50M | .Case("xsaveopt", true) |
1125 | 3.50M | .Default(false); |
1126 | 3.50M | } |
1127 | | |
1128 | 266k | bool X86TargetInfo::hasFeature(StringRef Feature) const { |
1129 | 266k | return llvm::StringSwitch<bool>(Feature) |
1130 | 266k | .Case("adx", HasADX) |
1131 | 266k | .Case("aes", HasAES) |
1132 | 266k | .Case("amx-bf16", HasAMXBF16) |
1133 | 266k | .Case("amx-complex", HasAMXCOMPLEX) |
1134 | 266k | .Case("amx-fp16", HasAMXFP16) |
1135 | 266k | .Case("amx-int8", HasAMXINT8) |
1136 | 266k | .Case("amx-tile", HasAMXTILE) |
1137 | 266k | .Case("avx", SSELevel >= AVX) |
1138 | 266k | .Case("avx10.1-256", HasAVX10_1) |
1139 | 266k | .Case("avx10.1-512", HasAVX10_1_512) |
1140 | 266k | .Case("avx2", SSELevel >= AVX2) |
1141 | 266k | .Case("avx512f", SSELevel >= AVX512F) |
1142 | 266k | .Case("avx512cd", HasAVX512CD) |
1143 | 266k | .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) |
1144 | 266k | .Case("avx512vnni", HasAVX512VNNI) |
1145 | 266k | .Case("avx512bf16", HasAVX512BF16) |
1146 | 266k | .Case("avx512er", HasAVX512ER) |
1147 | 266k | .Case("avx512fp16", HasAVX512FP16) |
1148 | 266k | .Case("avx512pf", HasAVX512PF) |
1149 | 266k | .Case("avx512dq", HasAVX512DQ) |
1150 | 266k | .Case("avx512bitalg", HasAVX512BITALG) |
1151 | 266k | .Case("avx512bw", HasAVX512BW) |
1152 | 266k | .Case("avx512vl", HasAVX512VL) |
1153 | 266k | .Case("avx512vbmi", HasAVX512VBMI) |
1154 | 266k | .Case("avx512vbmi2", HasAVX512VBMI2) |
1155 | 266k | .Case("avx512ifma", HasAVX512IFMA) |
1156 | 266k | .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) |
1157 | 266k | .Case("avxifma", HasAVXIFMA) |
1158 | 266k | .Case("avxneconvert", HasAVXNECONVERT) |
1159 | 266k | .Case("avxvnni", HasAVXVNNI) |
1160 | 266k | .Case("avxvnniint16", HasAVXVNNIINT16) |
1161 | 266k | .Case("avxvnniint8", HasAVXVNNIINT8) |
1162 | 266k | .Case("bmi", HasBMI) |
1163 | 266k | .Case("bmi2", HasBMI2) |
1164 | 266k | .Case("cldemote", HasCLDEMOTE) |
1165 | 266k | .Case("clflushopt", HasCLFLUSHOPT) |
1166 | 266k | .Case("clwb", HasCLWB) |
1167 | 266k | .Case("clzero", HasCLZERO) |
1168 | 266k | .Case("cmpccxadd", HasCMPCCXADD) |
1169 | 266k | .Case("crc32", HasCRC32) |
1170 | 266k | .Case("cx8", HasCX8) |
1171 | 266k | .Case("cx16", HasCX16) |
1172 | 266k | .Case("enqcmd", HasENQCMD) |
1173 | 266k | .Case("evex512", HasEVEX512) |
1174 | 266k | .Case("f16c", HasF16C) |
1175 | 266k | .Case("fma", HasFMA) |
1176 | 266k | .Case("fma4", XOPLevel >= FMA4) |
1177 | 266k | .Case("fsgsbase", HasFSGSBASE) |
1178 | 266k | .Case("fxsr", HasFXSR) |
1179 | 266k | .Case("gfni", HasGFNI) |
1180 | 266k | .Case("hreset", HasHRESET) |
1181 | 266k | .Case("invpcid", HasINVPCID) |
1182 | 266k | .Case("kl", HasKL) |
1183 | 266k | .Case("widekl", HasWIDEKL) |
1184 | 266k | .Case("lwp", HasLWP) |
1185 | 266k | .Case("lzcnt", HasLZCNT) |
1186 | 266k | .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) |
1187 | 266k | .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) |
1188 | 266k | .Case("mmx", MMX3DNowLevel >= MMX) |
1189 | 266k | .Case("movbe", HasMOVBE) |
1190 | 266k | .Case("movdiri", HasMOVDIRI) |
1191 | 266k | .Case("movdir64b", HasMOVDIR64B) |
1192 | 266k | .Case("mwaitx", HasMWAITX) |
1193 | 266k | .Case("pclmul", HasPCLMUL) |
1194 | 266k | .Case("pconfig", HasPCONFIG) |
1195 | 266k | .Case("pku", HasPKU) |
1196 | 266k | .Case("popcnt", HasPOPCNT) |
1197 | 266k | .Case("prefetchi", HasPREFETCHI) |
1198 | 266k | .Case("prefetchwt1", HasPREFETCHWT1) |
1199 | 266k | .Case("prfchw", HasPRFCHW) |
1200 | 266k | .Case("ptwrite", HasPTWRITE) |
1201 | 266k | .Case("raoint", HasRAOINT) |
1202 | 266k | .Case("rdpid", HasRDPID) |
1203 | 266k | .Case("rdpru", HasRDPRU) |
1204 | 266k | .Case("rdrnd", HasRDRND) |
1205 | 266k | .Case("rdseed", HasRDSEED) |
1206 | 266k | .Case("retpoline-external-thunk", HasRetpolineExternalThunk) |
1207 | 266k | .Case("rtm", HasRTM) |
1208 | 266k | .Case("sahf", HasLAHFSAHF) |
1209 | 266k | .Case("serialize", HasSERIALIZE) |
1210 | 266k | .Case("sgx", HasSGX) |
1211 | 266k | .Case("sha", HasSHA) |
1212 | 266k | .Case("sha512", HasSHA512) |
1213 | 266k | .Case("shstk", HasSHSTK) |
1214 | 266k | .Case("sm3", HasSM3) |
1215 | 266k | .Case("sm4", HasSM4) |
1216 | 266k | .Case("sse", SSELevel >= SSE1) |
1217 | 266k | .Case("sse2", SSELevel >= SSE2) |
1218 | 266k | .Case("sse3", SSELevel >= SSE3) |
1219 | 266k | .Case("ssse3", SSELevel >= SSSE3) |
1220 | 266k | .Case("sse4.1", SSELevel >= SSE41) |
1221 | 266k | .Case("sse4.2", SSELevel >= SSE42) |
1222 | 266k | .Case("sse4a", XOPLevel >= SSE4A) |
1223 | 266k | .Case("tbm", HasTBM) |
1224 | 266k | .Case("tsxldtrk", HasTSXLDTRK) |
1225 | 266k | .Case("uintr", HasUINTR) |
1226 | 266k | .Case("usermsr", HasUSERMSR) |
1227 | 266k | .Case("vaes", HasVAES) |
1228 | 266k | .Case("vpclmulqdq", HasVPCLMULQDQ) |
1229 | 266k | .Case("wbnoinvd", HasWBNOINVD) |
1230 | 266k | .Case("waitpkg", HasWAITPKG) |
1231 | 266k | .Case("x86", true) |
1232 | 266k | .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) |
1233 | 266k | .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) |
1234 | 266k | .Case("x87", HasX87) |
1235 | 266k | .Case("xop", XOPLevel >= XOP) |
1236 | 266k | .Case("xsave", HasXSAVE) |
1237 | 266k | .Case("xsavec", HasXSAVEC) |
1238 | 266k | .Case("xsaves", HasXSAVES) |
1239 | 266k | .Case("xsaveopt", HasXSAVEOPT) |
1240 | 266k | .Case("fullbf16", HasFullBFloat16) |
1241 | 266k | .Default(false); |
1242 | 266k | } |
1243 | | |
1244 | | // We can't use a generic validation scheme for the features accepted here |
1245 | | // versus subtarget features accepted in the target attribute because the |
1246 | | // bitfield structure that's initialized in the runtime only supports the |
1247 | | // below currently rather than the full range of subtarget features. (See |
1248 | | // X86TargetInfo::hasFeature for a somewhat comprehensive list). |
1249 | 1.92k | bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { |
1250 | 1.92k | return llvm::StringSwitch<bool>(FeatureStr) |
1251 | 73.1k | #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) |
1252 | 7.69k | #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true) |
1253 | 1.92k | #include "llvm/TargetParser/X86TargetParser.def" |
1254 | 1.92k | .Default(false); |
1255 | 1.92k | } |
1256 | | |
1257 | 190 | static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { |
1258 | 190 | return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) |
1259 | 190 | #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ |
1260 | 7.22k | .Case(STR, llvm::X86::FEATURE_##ENUM) |
1261 | | |
1262 | 190 | #include "llvm/TargetParser/X86TargetParser.def" |
1263 | 190 | ; |
1264 | | // Note, this function should only be used after ensuring the value is |
1265 | | // correct, so it asserts if the value is out of range. |
1266 | 190 | } |
1267 | | |
1268 | 739 | unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { |
1269 | | // Valid CPUs have a 'key feature' that compares just better than its key |
1270 | | // feature. |
1271 | 739 | using namespace llvm::X86; |
1272 | 739 | CPUKind Kind = parseArchX86(Name); |
1273 | 739 | if (Kind != CK_None) { |
1274 | 549 | ProcessorFeatures KeyFeature = getKeyFeature(Kind); |
1275 | 549 | return (getFeaturePriority(KeyFeature) << 1) + 1; |
1276 | 549 | } |
1277 | | |
1278 | | // Now we know we have a feature, so get its priority and shift it a few so |
1279 | | // that we have sufficient room for the CPUs (above). |
1280 | 190 | return getFeaturePriority(getFeature(Name)) << 1; |
1281 | 739 | } |
1282 | | |
1283 | 419 | bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { |
1284 | 419 | return llvm::X86::validateCPUSpecificCPUDispatch(Name); |
1285 | 419 | } |
1286 | | |
1287 | 504 | char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { |
1288 | 504 | return llvm::X86::getCPUDispatchMangling(Name); |
1289 | 504 | } |
1290 | | |
1291 | | void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( |
1292 | 492 | StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { |
1293 | 492 | SmallVector<StringRef, 32> TargetCPUFeatures; |
1294 | 492 | llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true); |
1295 | 492 | for (auto &F : TargetCPUFeatures) |
1296 | 12.7k | Features.push_back(F); |
1297 | 492 | } |
1298 | | |
1299 | | // We can't use a generic validation scheme for the cpus accepted here |
1300 | | // versus subtarget cpus accepted in the target attribute because the |
1301 | | // variables intitialized by the runtime only support the below currently |
1302 | | // rather than the full range of cpus. |
1303 | 244 | bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { |
1304 | 244 | return llvm::StringSwitch<bool>(FeatureStr) |
1305 | 488 | #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) |
1306 | 976 | #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) |
1307 | 4.63k | #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) |
1308 | 1.22k | #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) |
1309 | 8.29k | #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) |
1310 | 244 | #include "llvm/TargetParser/X86TargetParser.def" |
1311 | 244 | .Default(false); |
1312 | 244 | } |
1313 | | |
1314 | 93 | static unsigned matchAsmCCConstraint(const char *Name) { |
1315 | 93 | auto RV = llvm::StringSwitch<unsigned>(Name) |
1316 | 93 | .Case("@cca", 4) |
1317 | 93 | .Case("@ccae", 5) |
1318 | 93 | .Case("@ccb", 4) |
1319 | 93 | .Case("@ccbe", 5) |
1320 | 93 | .Case("@ccc", 4) |
1321 | 93 | .Case("@cce", 4) |
1322 | 93 | .Case("@ccz", 4) |
1323 | 93 | .Case("@ccg", 4) |
1324 | 93 | .Case("@ccge", 5) |
1325 | 93 | .Case("@ccl", 4) |
1326 | 93 | .Case("@ccle", 5) |
1327 | 93 | .Case("@ccna", 5) |
1328 | 93 | .Case("@ccnae", 6) |
1329 | 93 | .Case("@ccnb", 5) |
1330 | 93 | .Case("@ccnbe", 6) |
1331 | 93 | .Case("@ccnc", 5) |
1332 | 93 | .Case("@ccne", 5) |
1333 | 93 | .Case("@ccnz", 5) |
1334 | 93 | .Case("@ccng", 5) |
1335 | 93 | .Case("@ccnge", 6) |
1336 | 93 | .Case("@ccnl", 5) |
1337 | 93 | .Case("@ccnle", 6) |
1338 | 93 | .Case("@ccno", 5) |
1339 | 93 | .Case("@ccnp", 5) |
1340 | 93 | .Case("@ccns", 5) |
1341 | 93 | .Case("@cco", 4) |
1342 | 93 | .Case("@ccp", 4) |
1343 | 93 | .Case("@ccs", 4) |
1344 | 93 | .Default(0); |
1345 | 93 | return RV; |
1346 | 93 | } |
1347 | | |
1348 | | bool X86TargetInfo::validateAsmConstraint( |
1349 | 12.5k | const char *&Name, TargetInfo::ConstraintInfo &Info) const { |
1350 | 12.5k | switch (*Name) { |
1351 | 2 | default: |
1352 | 2 | return false; |
1353 | | // Constant constraints. |
1354 | 9 | case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 |
1355 | | // instructions. |
1356 | 17 | case 'Z': // 32-bit unsigned integer constant for use with zero-extending |
1357 | | // x86_64 instructions. |
1358 | 17 | case 's': |
1359 | 17 | Info.setRequiresImmediate(); |
1360 | 17 | return true; |
1361 | 28 | case 'I': |
1362 | 28 | Info.setRequiresImmediate(0, 31); |
1363 | 28 | return true; |
1364 | 14 | case 'J': |
1365 | 14 | Info.setRequiresImmediate(0, 63); |
1366 | 14 | return true; |
1367 | 14 | case 'K': |
1368 | 14 | Info.setRequiresImmediate(-128, 127); |
1369 | 14 | return true; |
1370 | 30 | case 'L': |
1371 | 30 | Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); |
1372 | 30 | return true; |
1373 | 14 | case 'M': |
1374 | 14 | Info.setRequiresImmediate(0, 3); |
1375 | 14 | return true; |
1376 | 16 | case 'N': |
1377 | 16 | Info.setRequiresImmediate(0, 255); |
1378 | 16 | return true; |
1379 | 6 | case 'O': |
1380 | 6 | Info.setRequiresImmediate(0, 127); |
1381 | 6 | return true; |
1382 | | // Register constraints. |
1383 | 52 | case 'Y': // 'Y' is the first character for several 2-character constraints. |
1384 | | // Shift the pointer to the second character of the constraint. |
1385 | 52 | Name++; |
1386 | 52 | switch (*Name) { |
1387 | 0 | default: |
1388 | 0 | return false; |
1389 | 20 | case 'z': // First SSE register. |
1390 | 26 | case '2': |
1391 | 32 | case 't': // Any SSE register, when SSE2 is enabled. |
1392 | 42 | case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. |
1393 | 44 | case 'm': // Any MMX register, when inter-unit moves enabled. |
1394 | 52 | case 'k': // AVX512 arch mask registers: k1-k7. |
1395 | 52 | Info.setAllowsRegister(); |
1396 | 52 | return true; |
1397 | 52 | } |
1398 | 3 | case 'f': // Any x87 floating point stack register. |
1399 | | // Constraint 'f' cannot be used for output operands. |
1400 | 3 | if (Info.ConstraintStr[0] == '=') |
1401 | 1 | return false; |
1402 | 2 | Info.setAllowsRegister(); |
1403 | 2 | return true; |
1404 | 3.28k | case 'a': // eax. |
1405 | 6.01k | case 'b': // ebx. |
1406 | 8.91k | case 'c': // ecx. |
1407 | 11.6k | case 'd': // edx. |
1408 | 11.7k | case 'S': // esi. |
1409 | 11.9k | case 'D': // edi. |
1410 | 11.9k | case 'A': // edx:eax. |
1411 | 11.9k | case 't': // Top of floating point stack. |
1412 | 11.9k | case 'u': // Second from top of floating point stack. |
1413 | 11.9k | case 'q': // Any register accessible as [r]l: a, b, c, and d. |
1414 | 12.0k | case 'y': // Any MMX register. |
1415 | 12.0k | case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) |
1416 | 12.1k | case 'x': // Any SSE register. |
1417 | 12.2k | case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 |
1418 | | // for intermideate k reg operations). |
1419 | 12.2k | case 'Q': // Any register accessible as [r]h: a, b, c, and d. |
1420 | 12.2k | case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. |
1421 | 12.2k | case 'l': // "Index" registers: any general register that can be used as an |
1422 | | // index in a base+index memory access. |
1423 | 12.2k | Info.setAllowsRegister(); |
1424 | 12.2k | return true; |
1425 | | // Floating point constant constraints. |
1426 | 8 | case 'C': // SSE floating point constant. |
1427 | 16 | case 'G': // x87 floating point constant. |
1428 | 16 | return true; |
1429 | 62 | case '@': |
1430 | | // CC condition changes. |
1431 | 62 | if (auto Len = matchAsmCCConstraint(Name)) { |
1432 | 62 | Name += Len - 1; |
1433 | 62 | Info.setAllowsRegister(); |
1434 | 62 | return true; |
1435 | 62 | } |
1436 | 0 | return false; |
1437 | 12.5k | } |
1438 | 12.5k | } |
1439 | | |
1440 | | // Below is based on the following information: |
1441 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1442 | | // | Processor Name | Cache Line Size (Bytes) | Source | |
1443 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1444 | | // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | |
1445 | | // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | |
1446 | | // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | |
1447 | | // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | |
1448 | | // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | |
1449 | | // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | |
1450 | | // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | |
1451 | | // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | |
1452 | | // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | |
1453 | | // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | |
1454 | | // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | |
1455 | | // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | |
1456 | | // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | |
1457 | | // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | |
1458 | | // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | |
1459 | | // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | |
1460 | | // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | |
1461 | | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1462 | 0 | std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { |
1463 | 0 | using namespace llvm::X86; |
1464 | 0 | switch (CPU) { |
1465 | | // i386 |
1466 | 0 | case CK_i386: |
1467 | | // i486 |
1468 | 0 | case CK_i486: |
1469 | 0 | case CK_WinChipC6: |
1470 | 0 | case CK_WinChip2: |
1471 | 0 | case CK_C3: |
1472 | | // Lakemont |
1473 | 0 | case CK_Lakemont: |
1474 | 0 | return 16; |
1475 | | |
1476 | | // i586 |
1477 | 0 | case CK_i586: |
1478 | 0 | case CK_Pentium: |
1479 | 0 | case CK_PentiumMMX: |
1480 | | // i686 |
1481 | 0 | case CK_PentiumPro: |
1482 | 0 | case CK_i686: |
1483 | 0 | case CK_Pentium2: |
1484 | 0 | case CK_Pentium3: |
1485 | 0 | case CK_PentiumM: |
1486 | 0 | case CK_C3_2: |
1487 | | // K6 |
1488 | 0 | case CK_K6: |
1489 | 0 | case CK_K6_2: |
1490 | 0 | case CK_K6_3: |
1491 | | // Geode |
1492 | 0 | case CK_Geode: |
1493 | 0 | return 32; |
1494 | | |
1495 | | // Netburst |
1496 | 0 | case CK_Pentium4: |
1497 | 0 | case CK_Prescott: |
1498 | 0 | case CK_Nocona: |
1499 | | // Atom |
1500 | 0 | case CK_Bonnell: |
1501 | 0 | case CK_Silvermont: |
1502 | 0 | case CK_Goldmont: |
1503 | 0 | case CK_GoldmontPlus: |
1504 | 0 | case CK_Tremont: |
1505 | 0 | case CK_Gracemont: |
1506 | |
|
1507 | 0 | case CK_Westmere: |
1508 | 0 | case CK_SandyBridge: |
1509 | 0 | case CK_IvyBridge: |
1510 | 0 | case CK_Haswell: |
1511 | 0 | case CK_Broadwell: |
1512 | 0 | case CK_SkylakeClient: |
1513 | 0 | case CK_SkylakeServer: |
1514 | 0 | case CK_Cascadelake: |
1515 | 0 | case CK_Nehalem: |
1516 | 0 | case CK_Cooperlake: |
1517 | 0 | case CK_Cannonlake: |
1518 | 0 | case CK_Tigerlake: |
1519 | 0 | case CK_SapphireRapids: |
1520 | 0 | case CK_IcelakeClient: |
1521 | 0 | case CK_Rocketlake: |
1522 | 0 | case CK_IcelakeServer: |
1523 | 0 | case CK_Alderlake: |
1524 | 0 | case CK_Raptorlake: |
1525 | 0 | case CK_Meteorlake: |
1526 | 0 | case CK_Arrowlake: |
1527 | 0 | case CK_ArrowlakeS: |
1528 | 0 | case CK_Lunarlake: |
1529 | 0 | case CK_Pantherlake: |
1530 | 0 | case CK_Sierraforest: |
1531 | 0 | case CK_Grandridge: |
1532 | 0 | case CK_Graniterapids: |
1533 | 0 | case CK_GraniterapidsD: |
1534 | 0 | case CK_Emeraldrapids: |
1535 | 0 | case CK_Clearwaterforest: |
1536 | 0 | case CK_KNL: |
1537 | 0 | case CK_KNM: |
1538 | | // K7 |
1539 | 0 | case CK_Athlon: |
1540 | 0 | case CK_AthlonXP: |
1541 | | // K8 |
1542 | 0 | case CK_K8: |
1543 | 0 | case CK_K8SSE3: |
1544 | 0 | case CK_AMDFAM10: |
1545 | | // Bobcat |
1546 | 0 | case CK_BTVER1: |
1547 | 0 | case CK_BTVER2: |
1548 | | // Bulldozer |
1549 | 0 | case CK_BDVER1: |
1550 | 0 | case CK_BDVER2: |
1551 | 0 | case CK_BDVER3: |
1552 | 0 | case CK_BDVER4: |
1553 | | // Zen |
1554 | 0 | case CK_ZNVER1: |
1555 | 0 | case CK_ZNVER2: |
1556 | 0 | case CK_ZNVER3: |
1557 | 0 | case CK_ZNVER4: |
1558 | | // Deprecated |
1559 | 0 | case CK_x86_64: |
1560 | 0 | case CK_x86_64_v2: |
1561 | 0 | case CK_x86_64_v3: |
1562 | 0 | case CK_x86_64_v4: |
1563 | 0 | case CK_Yonah: |
1564 | 0 | case CK_Penryn: |
1565 | 0 | case CK_Core2: |
1566 | 0 | return 64; |
1567 | | |
1568 | | // The following currently have unknown cache line sizes (but they are probably all 64): |
1569 | | // Core |
1570 | 0 | case CK_None: |
1571 | 0 | return std::nullopt; |
1572 | 0 | } |
1573 | 0 | llvm_unreachable("Unknown CPU kind"); |
1574 | 0 | } |
1575 | | |
1576 | | bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, |
1577 | | StringRef Constraint, |
1578 | 6.59k | unsigned Size) const { |
1579 | | // Strip off constraint modifiers. |
1580 | 13.1k | while (Constraint[0] == '=' || Constraint[0] == '+'7.17k || Constraint[0] == '&'6.60k ) |
1581 | 6.60k | Constraint = Constraint.substr(1); |
1582 | | |
1583 | 6.59k | return validateOperandSize(FeatureMap, Constraint, Size); |
1584 | 6.59k | } |
1585 | | |
1586 | | bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, |
1587 | | StringRef Constraint, |
1588 | 6.95k | unsigned Size) const { |
1589 | 6.95k | return validateOperandSize(FeatureMap, Constraint, Size); |
1590 | 6.95k | } |
1591 | | |
1592 | | bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, |
1593 | | StringRef Constraint, |
1594 | 10.1k | unsigned Size) const { |
1595 | 10.1k | switch (Constraint[0]) { |
1596 | 10.0k | default: |
1597 | 10.0k | break; |
1598 | 10.0k | case 'k': |
1599 | | // Registers k0-k7 (AVX512) size limit is 64 bit. |
1600 | 30 | case 'y': |
1601 | 30 | return Size <= 64; |
1602 | 2 | case 'f': |
1603 | 9 | case 't': |
1604 | 14 | case 'u': |
1605 | 14 | return Size <= 128; |
1606 | 26 | case 'Y': |
1607 | | // 'Y' is the first character for several 2-character constraints. |
1608 | 26 | switch (Constraint[1]) { |
1609 | 0 | default: |
1610 | 0 | return false; |
1611 | 1 | case 'm': |
1612 | | // 'Ym' is synonymous with 'y'. |
1613 | 5 | case 'k': |
1614 | 5 | return Size <= 64; |
1615 | 10 | case 'z': |
1616 | | // XMM0/YMM/ZMM0 |
1617 | 10 | if (hasFeatureEnabled(FeatureMap, "avx512f") && |
1618 | 10 | hasFeatureEnabled(FeatureMap, "evex512")7 ) |
1619 | | // ZMM0 can be used if target supports AVX512F and EVEX512 is set. |
1620 | 7 | return Size <= 512U; |
1621 | 3 | else if (hasFeatureEnabled(FeatureMap, "avx")) |
1622 | | // YMM0 can be used if target supports AVX. |
1623 | 2 | return Size <= 256U; |
1624 | 1 | else if (hasFeatureEnabled(FeatureMap, "sse")) |
1625 | 1 | return Size <= 128U; |
1626 | 0 | return false; |
1627 | 5 | case 'i': |
1628 | 8 | case 't': |
1629 | 11 | case '2': |
1630 | | // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. |
1631 | 11 | if (SSELevel < SSE2) |
1632 | 0 | return false; |
1633 | 11 | break; |
1634 | 26 | } |
1635 | 11 | break; |
1636 | 30 | case 'v': |
1637 | 101 | case 'x': |
1638 | 101 | if (hasFeatureEnabled(FeatureMap, "avx512f") && |
1639 | 101 | hasFeatureEnabled(FeatureMap, "evex512")46 ) |
1640 | | // 512-bit zmm registers can be used if target supports AVX512F and |
1641 | | // EVEX512 is set. |
1642 | 46 | return Size <= 512U; |
1643 | 55 | else if (hasFeatureEnabled(FeatureMap, "avx")) |
1644 | | // 256-bit ymm registers can be used if target supports AVX. |
1645 | 27 | return Size <= 256U; |
1646 | 28 | return Size <= 128U; |
1647 | | |
1648 | 10.1k | } |
1649 | | |
1650 | 10.0k | return true; |
1651 | 10.1k | } |
1652 | | |
1653 | 2.00k | std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { |
1654 | 2.00k | switch (*Constraint) { |
1655 | 31 | case '@': |
1656 | 31 | if (auto Len = matchAsmCCConstraint(Constraint)) { |
1657 | 31 | std::string Converted = "{" + std::string(Constraint, Len) + "}"; |
1658 | 31 | Constraint += Len - 1; |
1659 | 31 | return Converted; |
1660 | 31 | } |
1661 | 0 | return std::string(1, *Constraint); |
1662 | 135 | case 'a': |
1663 | 135 | return std::string("{ax}"); |
1664 | 84 | case 'b': |
1665 | 84 | return std::string("{bx}"); |
1666 | 121 | case 'c': |
1667 | 121 | return std::string("{cx}"); |
1668 | 84 | case 'd': |
1669 | 84 | return std::string("{dx}"); |
1670 | 29 | case 'S': |
1671 | 29 | return std::string("{si}"); |
1672 | 51 | case 'D': |
1673 | 51 | return std::string("{di}"); |
1674 | 5 | case 'p': // Keep 'p' constraint (address). |
1675 | 5 | return std::string("p"); |
1676 | 3 | case 't': // top of floating point stack. |
1677 | 3 | return std::string("{st}"); |
1678 | 1 | case 'u': // second from top of floating point stack. |
1679 | 1 | return std::string("{st(1)}"); // second from top of floating point stack. |
1680 | 26 | case 'Y': |
1681 | 26 | switch (Constraint[1]) { |
1682 | 0 | default: |
1683 | | // Break from inner switch and fall through (copy single char), |
1684 | | // continue parsing after copying the current constraint into |
1685 | | // the return string. |
1686 | 0 | break; |
1687 | 4 | case 'k': |
1688 | 5 | case 'm': |
1689 | 10 | case 'i': |
1690 | 13 | case 't': |
1691 | 23 | case 'z': |
1692 | 26 | case '2': |
1693 | | // "^" hints llvm that this is a 2 letter constraint. |
1694 | | // "Constraint++" is used to promote the string iterator |
1695 | | // to the next constraint. |
1696 | 26 | return std::string("^") + std::string(Constraint++, 2); |
1697 | 26 | } |
1698 | 26 | [[fallthrough]];0 |
1699 | 1.43k | default: |
1700 | 1.43k | return std::string(1, *Constraint); |
1701 | 2.00k | } |
1702 | 2.00k | } |
1703 | | |
1704 | 31 | void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { |
1705 | 31 | bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; |
1706 | 31 | llvm::X86::fillValidCPUArchList(Values, Only64Bit); |
1707 | 31 | } |
1708 | | |
1709 | 5 | void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { |
1710 | 5 | llvm::X86::fillValidTuneCPUList(Values); |
1711 | 5 | } |
1712 | | |
1713 | 3.65k | ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { |
1714 | 3.65k | return llvm::ArrayRef(GCCRegNames); |
1715 | 3.65k | } |
1716 | | |
1717 | 3.18k | ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { |
1718 | 3.18k | return llvm::ArrayRef(AddlRegNames); |
1719 | 3.18k | } |
1720 | | |
1721 | 15.4k | ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { |
1722 | 15.4k | return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - |
1723 | 15.4k | Builtin::FirstTSBuiltin + 1); |
1724 | 15.4k | } |
1725 | | |
1726 | 66.9k | ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { |
1727 | 66.9k | return llvm::ArrayRef(BuiltinInfoX86, |
1728 | 66.9k | X86::LastTSBuiltin - Builtin::FirstTSBuiltin); |
1729 | 66.9k | } |