Coverage Report

Created: 2020-02-15 09:57

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/CodeGen/TargetInfo.cpp
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Source (jump to first uncovered line)
1
//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// These classes wrap the information about a call or function
10
// definition used to handle ABI compliancy.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "TargetInfo.h"
15
#include "ABIInfo.h"
16
#include "CGBlocks.h"
17
#include "CGCXXABI.h"
18
#include "CGValue.h"
19
#include "CodeGenFunction.h"
20
#include "clang/AST/Attr.h"
21
#include "clang/AST/RecordLayout.h"
22
#include "clang/Basic/CodeGenOptions.h"
23
#include "clang/CodeGen/CGFunctionInfo.h"
24
#include "clang/CodeGen/SwiftCallingConv.h"
25
#include "llvm/ADT/SmallBitVector.h"
26
#include "llvm/ADT/StringExtras.h"
27
#include "llvm/ADT/StringSwitch.h"
28
#include "llvm/ADT/Triple.h"
29
#include "llvm/ADT/Twine.h"
30
#include "llvm/IR/DataLayout.h"
31
#include "llvm/IR/Type.h"
32
#include "llvm/Support/raw_ostream.h"
33
#include <algorithm> // std::sort
34
35
using namespace clang;
36
using namespace CodeGen;
37
38
// Helper for coercing an aggregate argument or return value into an integer
39
// array of the same size (including padding) and alignment.  This alternate
40
// coercion happens only for the RenderScript ABI and can be removed after
41
// runtimes that rely on it are no longer supported.
42
//
43
// RenderScript assumes that the size of the argument / return value in the IR
44
// is the same as the size of the corresponding qualified type. This helper
45
// coerces the aggregate type into an array of the same size (including
46
// padding).  This coercion is used in lieu of expansion of struct members or
47
// other canonical coercions that return a coerced-type of larger size.
48
//
49
// Ty          - The argument / return value type
50
// Context     - The associated ASTContext
51
// LLVMContext - The associated LLVMContext
52
static ABIArgInfo coerceToIntArray(QualType Ty,
53
                                   ASTContext &Context,
54
19
                                   llvm::LLVMContext &LLVMContext) {
55
19
  // Alignment and Size are measured in bits.
56
19
  const uint64_t Size = Context.getTypeSize(Ty);
57
19
  const uint64_t Alignment = Context.getTypeAlign(Ty);
58
19
  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
59
19
  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
60
19
  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
61
19
}
62
63
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
64
                               llvm::Value *Array,
65
                               llvm::Value *Value,
66
                               unsigned FirstIndex,
67
10
                               unsigned LastIndex) {
68
10
  // Alternatively, we could emit this as a loop in the source.
69
215
  for (unsigned I = FirstIndex; I <= LastIndex; 
++I205
) {
70
205
    llvm::Value *Cell =
71
205
        Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
72
205
    Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
73
205
  }
74
10
}
75
76
95.9k
static bool isAggregateTypeForABI(QualType T) {
77
95.9k
  return !CodeGenFunction::hasScalarEvaluationKind(T) ||
78
95.9k
         
T->isMemberFunctionPointerType()90.4k
;
79
95.9k
}
80
81
ABIArgInfo
82
ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
83
2.68k
                                 llvm::Type *Padding) const {
84
2.68k
  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
85
2.68k
                                 ByRef, Realign, Padding);
86
2.68k
}
87
88
ABIArgInfo
89
25
ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
90
25
  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
91
25
                                      /*ByRef*/ false, Realign);
92
25
}
93
94
Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
95
0
                             QualType Ty) const {
96
0
  return Address::invalid();
97
0
}
98
99
25.8k
ABIInfo::~ABIInfo() {}
100
101
/// Does the given lowering require more than the given number of
102
/// registers when expanded?
103
///
104
/// This is intended to be the basis of a reasonable basic implementation
105
/// of should{Pass,Return}IndirectlyForSwift.
106
///
107
/// For most targets, a limit of four total registers is reasonable; this
108
/// limits the amount of code required in order to move around the value
109
/// in case it wasn't produced immediately prior to the call by the caller
110
/// (or wasn't produced in exactly the right registers) or isn't used
111
/// immediately within the callee.  But some targets may need to further
112
/// limit the register count due to an inability to support that many
113
/// return registers.
114
static bool occupiesMoreThan(CodeGenTypes &cgt,
115
                             ArrayRef<llvm::Type*> scalarTypes,
116
1.04k
                             unsigned maxAllRegisters) {
117
1.04k
  unsigned intCount = 0, fpCount = 0;
118
4.17k
  for (llvm::Type *type : scalarTypes) {
119
4.17k
    if (type->isPointerTy()) {
120
0
      intCount++;
121
4.17k
    } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
122
2.28k
      auto ptrWidth = cgt.getTarget().getPointerWidth(0);
123
2.28k
      intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
124
2.28k
    } else {
125
1.88k
      assert(type->isVectorTy() || type->isFloatingPointTy());
126
1.88k
      fpCount++;
127
1.88k
    }
128
4.17k
  }
129
1.04k
130
1.04k
  return (intCount + fpCount > maxAllRegisters);
131
1.04k
}
132
133
bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
134
                                             llvm::Type *eltTy,
135
440
                                             unsigned numElts) const {
136
440
  // The default implementation of this assumes that the target guarantees
137
440
  // 128-bit SIMD support but nothing more.
138
440
  return (vectorSize.getQuantity() > 8 && 
vectorSize.getQuantity() <= 16432
);
139
440
}
140
141
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
142
18.4k
                                              CGCXXABI &CXXABI) {
143
18.4k
  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
144
18.4k
  if (!RD) {
145
3.63k
    if (!RT->getDecl()->canPassInRegisters())
146
8
      return CGCXXABI::RAA_Indirect;
147
3.62k
    return CGCXXABI::RAA_Default;
148
3.62k
  }
149
14.8k
  return CXXABI.getRecordArgABI(RD);
150
14.8k
}
151
152
static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
153
9.73k
                                              CGCXXABI &CXXABI) {
154
9.73k
  const RecordType *RT = T->getAs<RecordType>();
155
9.73k
  if (!RT)
156
5.62k
    return CGCXXABI::RAA_Default;
157
4.11k
  return getRecordArgABI(RT, CXXABI);
158
4.11k
}
159
160
static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
161
156k
                               const ABIInfo &Info) {
162
156k
  QualType Ty = FI.getReturnType();
163
156k
164
156k
  if (const auto *RT = Ty->getAs<RecordType>())
165
4.96k
    if (!isa<CXXRecordDecl>(RT->getDecl()) &&
166
4.96k
        
!RT->getDecl()->canPassInRegisters()1.14k
) {
167
12
      FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
168
12
      return true;
169
12
    }
170
156k
171
156k
  return CXXABI.classifyReturnType(FI);
172
156k
}
173
174
/// Pass transparent unions as if they were the type of the first element. Sema
175
/// should ensure that all elements of the union have the same "machine type".
176
306k
static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
177
306k
  if (const RecordType *UT = Ty->getAsUnionType()) {
178
113
    const RecordDecl *UD = UT->getDecl();
179
113
    if (UD->hasAttr<TransparentUnionAttr>()) {
180
22
      assert(!UD->field_empty() && "sema created an empty transparent union");
181
22
      return UD->field_begin()->getType();
182
22
    }
183
306k
  }
184
306k
  return Ty;
185
306k
}
186
187
202k
CGCXXABI &ABIInfo::getCXXABI() const {
188
202k
  return CGT.getCXXABI();
189
202k
}
190
191
340k
ASTContext &ABIInfo::getContext() const {
192
340k
  return CGT.getContext();
193
340k
}
194
195
16.3k
llvm::LLVMContext &ABIInfo::getVMContext() const {
196
16.3k
  return CGT.getLLVMContext();
197
16.3k
}
198
199
17.8k
const llvm::DataLayout &ABIInfo::getDataLayout() const {
200
17.8k
  return CGT.getDataLayout();
201
17.8k
}
202
203
26.8k
const TargetInfo &ABIInfo::getTarget() const {
204
26.8k
  return CGT.getTarget();
205
26.8k
}
206
207
0
const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
208
0
  return CGT.getCodeGenOpts();
209
0
}
210
211
3.95k
bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
212
213
0
bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
214
0
  return false;
215
0
}
216
217
bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
218
0
                                                uint64_t Members) const {
219
0
  return false;
220
0
}
221
222
0
LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
223
0
  raw_ostream &OS = llvm::errs();
224
0
  OS << "(ABIArgInfo Kind=";
225
0
  switch (TheKind) {
226
0
  case Direct:
227
0
    OS << "Direct Type=";
228
0
    if (llvm::Type *Ty = getCoerceToType())
229
0
      Ty->print(OS);
230
0
    else
231
0
      OS << "null";
232
0
    break;
233
0
  case Extend:
234
0
    OS << "Extend";
235
0
    break;
236
0
  case Ignore:
237
0
    OS << "Ignore";
238
0
    break;
239
0
  case InAlloca:
240
0
    OS << "InAlloca Offset=" << getInAllocaFieldIndex();
241
0
    break;
242
0
  case Indirect:
243
0
    OS << "Indirect Align=" << getIndirectAlign().getQuantity()
244
0
       << " ByVal=" << getIndirectByVal()
245
0
       << " Realign=" << getIndirectRealign();
246
0
    break;
247
0
  case Expand:
248
0
    OS << "Expand";
249
0
    break;
250
0
  case CoerceAndExpand:
251
0
    OS << "CoerceAndExpand Type=";
252
0
    getCoerceAndExpandType()->print(OS);
253
0
    break;
254
0
  }
255
0
  OS << ")\n";
256
0
}
257
258
// Dynamically round a pointer up to a multiple of the given alignment.
259
static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
260
                                                  llvm::Value *Ptr,
261
93
                                                  CharUnits Align) {
262
93
  llvm::Value *PtrAsInt = Ptr;
263
93
  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
264
93
  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
265
93
  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
266
93
        llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
267
93
  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
268
93
           llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
269
93
  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
270
93
                                        Ptr->getType(),
271
93
                                        Ptr->getName() + ".aligned");
272
93
  return PtrAsInt;
273
93
}
274
275
/// Emit va_arg for a platform using the common void* representation,
276
/// where arguments are simply emitted in an array of slots on the stack.
277
///
278
/// This version implements the core direct-value passing rules.
279
///
280
/// \param SlotSize - The size and alignment of a stack slot.
281
///   Each argument will be allocated to a multiple of this number of
282
///   slots, and all the slots will be aligned to this value.
283
/// \param AllowHigherAlign - The slot alignment is not a cap;
284
///   an argument type with an alignment greater than the slot size
285
///   will be emitted on a higher-alignment address, potentially
286
///   leaving one or more empty slots behind as padding.  If this
287
///   is false, the returned address might be less-aligned than
288
///   DirectAlign.
289
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
290
                                      Address VAListAddr,
291
                                      llvm::Type *DirectTy,
292
                                      CharUnits DirectSize,
293
                                      CharUnits DirectAlign,
294
                                      CharUnits SlotSize,
295
249
                                      bool AllowHigherAlign) {
296
249
  // Cast the element type to i8* if necessary.  Some platforms define
297
249
  // va_list as a struct containing an i8* instead of just an i8*.
298
249
  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
299
54
    VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
300
249
301
249
  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
302
249
303
249
  // If the CC aligns values higher than the slot size, do so if needed.
304
249
  Address Addr = Address::invalid();
305
249
  if (AllowHigherAlign && 
DirectAlign > SlotSize228
) {
306
73
    Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
307
73
                                                 DirectAlign);
308
176
  } else {
309
176
    Addr = Address(Ptr, SlotSize);
310
176
  }
311
249
312
249
  // Advance the pointer past the argument, then store that back.
313
249
  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
314
249
  Address NextPtr =
315
249
      CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
316
249
  CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
317
249
318
249
  // If the argument is smaller than a slot, and this is a big-endian
319
249
  // target, the argument will be right-adjusted in its slot.
320
249
  if (DirectSize < SlotSize && 
CGF.CGM.getDataLayout().isBigEndian()32
&&
321
249
      
!DirectTy->isStructTy()7
) {
322
1
    Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
323
1
  }
324
249
325
249
  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
326
249
  return Addr;
327
249
}
328
329
/// Emit va_arg for a platform using the common void* representation,
330
/// where arguments are simply emitted in an array of slots on the stack.
331
///
332
/// \param IsIndirect - Values of this type are passed indirectly.
333
/// \param ValueInfo - The size and alignment of this type, generally
334
///   computed with getContext().getTypeInfoInChars(ValueTy).
335
/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
336
///   Each argument will be allocated to a multiple of this number of
337
///   slots, and all the slots will be aligned to this value.
338
/// \param AllowHigherAlign - The slot alignment is not a cap;
339
///   an argument type with an alignment greater than the slot size
340
///   will be emitted on a higher-alignment address, potentially
341
///   leaving one or more empty slots behind as padding.
342
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
343
                                QualType ValueTy, bool IsIndirect,
344
                                std::pair<CharUnits, CharUnits> ValueInfo,
345
                                CharUnits SlotSizeAndAlign,
346
241
                                bool AllowHigherAlign) {
347
241
  // The size and alignment of the value that was passed directly.
348
241
  CharUnits DirectSize, DirectAlign;
349
241
  if (IsIndirect) {
350
31
    DirectSize = CGF.getPointerSize();
351
31
    DirectAlign = CGF.getPointerAlign();
352
210
  } else {
353
210
    DirectSize = ValueInfo.first;
354
210
    DirectAlign = ValueInfo.second;
355
210
  }
356
241
357
241
  // Cast the address we've calculated to the right type.
358
241
  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
359
241
  if (IsIndirect)
360
31
    DirectTy = DirectTy->getPointerTo(0);
361
241
362
241
  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
363
241
                                        DirectSize, DirectAlign,
364
241
                                        SlotSizeAndAlign,
365
241
                                        AllowHigherAlign);
366
241
367
241
  if (IsIndirect) {
368
31
    Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
369
31
  }
370
241
371
241
  return Addr;
372
241
373
241
}
374
375
static Address emitMergePHI(CodeGenFunction &CGF,
376
                            Address Addr1, llvm::BasicBlock *Block1,
377
                            Address Addr2, llvm::BasicBlock *Block2,
378
343
                            const llvm::Twine &Name = "") {
379
343
  assert(Addr1.getType() == Addr2.getType());
380
343
  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
381
343
  PHI->addIncoming(Addr1.getPointer(), Block1);
382
343
  PHI->addIncoming(Addr2.getPointer(), Block2);
383
343
  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
384
343
  return Address(PHI, Align);
385
343
}
386
387
25.6k
TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
388
389
// If someone can figure out a general rule for this, that would be great.
390
// It's probably just doomed to be platform-dependent, though.
391
5
unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
392
5
  // Verified for:
393
5
  //   x86-64     FreeBSD, Linux, Darwin
394
5
  //   x86-32     FreeBSD, Linux, Darwin
395
5
  //   PowerPC    Linux, Darwin
396
5
  //   ARM        Darwin (*not* EABI)
397
5
  //   AArch64    Linux
398
5
  return 32;
399
5
}
400
401
bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
402
187
                                     const FunctionNoProtoType *fnType) const {
403
187
  // The following conventions are known to require this to be false:
404
187
  //   x86_stdcall
405
187
  //   MIPS
406
187
  // For everything else, we just prefer false unless we opt out.
407
187
  return false;
408
187
}
409
410
void
411
TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
412
2
                                             llvm::SmallString<24> &Opt) const {
413
2
  // This assumes the user is passing a library name like "rt" instead of a
414
2
  // filename like "librt.a/so", and that they don't care whether it's static or
415
2
  // dynamic.
416
2
  Opt = "-l";
417
2
  Opt += Lib;
418
2
}
419
420
39
unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
421
39
  // OpenCL kernels are called via an explicit runtime API with arguments
422
39
  // set with clSetKernelArg(), not as normal sub-functions.
423
39
  // Return SPIR_KERNEL by default as the kernel calling convention to
424
39
  // ensure the fingerprint is fixed such way that each OpenCL argument
425
39
  // gets one matching argument in the produced kernel function argument
426
39
  // list to enable feasible implementation of clSetKernelArg() with
427
39
  // aggregates etc. In case we would use the default C calling conv here,
428
39
  // clSetKernelArg() might break depending on the target-specific
429
39
  // conventions; different targets might split structs passed as values
430
39
  // to multiple function arguments etc.
431
39
  return llvm::CallingConv::SPIR_KERNEL;
432
39
}
433
434
llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
435
27.9k
    llvm::PointerType *T, QualType QT) const {
436
27.9k
  return llvm::ConstantPointerNull::get(T);
437
27.9k
}
438
439
LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
440
55.9k
                                                   const VarDecl *D) const {
441
55.9k
  assert(!CGM.getLangOpts().OpenCL &&
442
55.9k
         !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
443
55.9k
         "Address space agnostic languages only");
444
55.9k
  return D ? 
D->getType().getAddressSpace()54.2k
:
LangAS::Default1.73k
;
445
55.9k
}
446
447
llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
448
    CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
449
4.07k
    LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
450
4.07k
  // Since target may map different address spaces in AST to the same address
451
4.07k
  // space, an address space conversion may end up as a bitcast.
452
4.07k
  if (auto *C = dyn_cast<llvm::Constant>(Src))
453
47
    return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
454
4.02k
  // Try to preserve the source's name to make IR more readable.
455
4.02k
  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
456
4.02k
      Src, DestTy, Src->hasName() ? 
Src->getName() + ".ascast"3.89k
:
""135
);
457
4.02k
}
458
459
llvm::Constant *
460
TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
461
                                        LangAS SrcAddr, LangAS DestAddr,
462
277
                                        llvm::Type *DestTy) const {
463
277
  // Since target may map different address spaces in AST to the same address
464
277
  // space, an address space conversion may end up as a bitcast.
465
277
  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
466
277
}
467
468
llvm::SyncScope::ID
469
TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
470
                                      SyncScope Scope,
471
                                      llvm::AtomicOrdering Ordering,
472
0
                                      llvm::LLVMContext &Ctx) const {
473
0
  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
474
0
}
475
476
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
477
478
/// isEmptyField - Return true iff a the field is "empty", that is it
479
/// is an unnamed bit-field or an (array of) empty record(s).
480
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
481
5.04k
                         bool AllowArrays) {
482
5.04k
  if (FD->isUnnamedBitfield())
483
88
    return true;
484
4.95k
485
4.95k
  QualType FT = FD->getType();
486
4.95k
487
4.95k
  // Constant arrays of empty records count as empty, strip them off.
488
4.95k
  // Constant arrays of zero length always count as empty.
489
4.95k
  if (AllowArrays)
490
6.50k
    
while (const ConstantArrayType *4.78k
AT = Context.getAsConstantArrayType(FT)) {
491
1.73k
      if (AT->getSize() == 0)
492
11
        return true;
493
1.72k
      FT = AT->getElementType();
494
1.72k
    }
495
4.95k
496
4.95k
  const RecordType *RT = FT->getAs<RecordType>();
497
4.94k
  if (!RT)
498
4.58k
    return false;
499
356
500
356
  // C++ record fields are never empty, at least in the Itanium ABI.
501
356
  //
502
356
  // FIXME: We should use a predicate for whether this behavior is true in the
503
356
  // current ABI.
504
356
  if (isa<CXXRecordDecl>(RT->getDecl()))
505
23
    return false;
506
333
507
333
  return isEmptyRecord(Context, FT, AllowArrays);
508
333
}
509
510
/// isEmptyRecord - Return true iff a structure contains only empty
511
/// fields. Note that a structure with a flexible array member is not
512
/// considered empty.
513
8.23k
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
514
8.23k
  const RecordType *RT = T->getAs<RecordType>();
515
8.23k
  if (!RT)
516
4.08k
    return false;
517
4.14k
  const RecordDecl *RD = RT->getDecl();
518
4.14k
  if (RD->hasFlexibleArrayMember())
519
4
    return false;
520
4.14k
521
4.14k
  // If this is a C++ record, check the bases first.
522
4.14k
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
523
744
    for (const auto &I : CXXRD->bases())
524
103
      if (!isEmptyRecord(Context, I.getType(), true))
525
97
        return false;
526
4.14k
527
4.14k
  
for (const auto *I : RD->fields())4.04k
528
3.83k
    if (!isEmptyField(Context, I, AllowArrays))
529
3.59k
      return false;
530
4.04k
  
return true445
;
531
4.04k
}
532
533
/// isSingleElementStruct - Determine if a structure is a "single
534
/// element struct", i.e. it has exactly one non-empty field or
535
/// exactly one field which is itself a single element
536
/// struct. Structures with flexible array members are never
537
/// considered single element structs.
538
///
539
/// \return The field declaration for the single non-empty field, if
540
/// it exists.
541
56.4k
static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
542
56.4k
  const RecordType *RT = T->getAs<RecordType>();
543
56.4k
  if (!RT)
544
55.6k
    return nullptr;
545
794
546
794
  const RecordDecl *RD = RT->getDecl();
547
794
  if (RD->hasFlexibleArrayMember())
548
4
    return nullptr;
549
790
550
790
  const Type *Found = nullptr;
551
790
552
790
  // If this is a C++ record, check the bases first.
553
790
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
554
216
    for (const auto &I : CXXRD->bases()) {
555
39
      // Ignore empty records.
556
39
      if (isEmptyRecord(Context, I.getType(), true))
557
4
        continue;
558
35
559
35
      // If we already found an element then this isn't a single-element struct.
560
35
      if (Found)
561
11
        return nullptr;
562
24
563
24
      // If this is non-empty and not a single element struct, the composite
564
24
      // cannot be a single element struct.
565
24
      Found = isSingleElementStruct(I.getType(), Context);
566
24
      if (!Found)
567
1
        return nullptr;
568
24
    }
569
216
  }
570
790
571
790
  // Check for single element.
572
1.09k
  
for (const auto *FD : RD->fields())778
{
573
1.09k
    QualType FT = FD->getType();
574
1.09k
575
1.09k
    // Ignore empty fields.
576
1.09k
    if (isEmptyField(Context, FD, true))
577
15
      continue;
578
1.07k
579
1.07k
    // If we already found an element then this isn't a single-element
580
1.07k
    // struct.
581
1.07k
    if (Found)
582
326
      return nullptr;
583
750
584
750
    // Treat single element arrays as the element.
585
764
    
while (const ConstantArrayType *750
AT = Context.getAsConstantArrayType(FT)) {
586
179
      if (AT->getSize().getZExtValue() != 1)
587
165
        break;
588
14
      FT = AT->getElementType();
589
14
    }
590
750
591
750
    if (!isAggregateTypeForABI(FT)) {
592
559
      Found = FT.getTypePtr();
593
559
    } else {
594
191
      Found = isSingleElementStruct(FT, Context);
595
191
      if (!Found)
596
181
        return nullptr;
597
191
    }
598
750
  }
599
778
600
778
  // We don't consider a struct a single-element struct if it has
601
778
  // padding beyond the element type.
602
778
  
if (271
Found271
&&
Context.getTypeSize(Found) != Context.getTypeSize(T)255
)
603
3
    return nullptr;
604
268
605
268
  return Found;
606
268
}
607
608
namespace {
609
Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
610
9
                       const ABIArgInfo &AI) {
611
9
  // This default implementation defers to the llvm backend's va_arg
612
9
  // instruction. It can handle only passing arguments directly
613
9
  // (typically only handled in the backend for primitive types), or
614
9
  // aggregates passed indirectly by pointer (NOTE: if the "byval"
615
9
  // flag has ABI impact in the callee, this implementation cannot
616
9
  // work.)
617
9
618
9
  // Only a few cases are covered here at the moment -- those needed
619
9
  // by the default abi.
620
9
  llvm::Value *Val;
621
9
622
9
  if (AI.isIndirect()) {
623
1
    assert(!AI.getPaddingType() &&
624
1
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
625
1
    assert(
626
1
        !AI.getIndirectRealign() &&
627
1
        "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
628
1
629
1
    auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
630
1
    CharUnits TyAlignForABI = TyInfo.second;
631
1
632
1
    llvm::Type *BaseTy =
633
1
        llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
634
1
    llvm::Value *Addr =
635
1
        CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
636
1
    return Address(Addr, TyAlignForABI);
637
8
  } else {
638
8
    assert((AI.isDirect() || AI.isExtend()) &&
639
8
           "Unexpected ArgInfo Kind in generic VAArg emitter!");
640
8
641
8
    assert(!AI.getInReg() &&
642
8
           "Unexpected InReg seen in arginfo in generic VAArg emitter!");
643
8
    assert(!AI.getPaddingType() &&
644
8
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
645
8
    assert(!AI.getDirectOffset() &&
646
8
           "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
647
8
    assert(!AI.getCoerceToType() &&
648
8
           "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
649
8
650
8
    Address Temp = CGF.CreateMemTemp(Ty, "varet");
651
8
    Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
652
8
    CGF.Builder.CreateStore(Val, Temp);
653
8
    return Temp;
654
8
  }
655
9
}
656
657
/// DefaultABIInfo - The default implementation for ABI specific
658
/// details. This implementation provides information which results in
659
/// self-consistent and sensible LLVM IR generation, but does not
660
/// conform to any particular ABI.
661
class DefaultABIInfo : public ABIInfo {
662
public:
663
549
  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
664
665
  ABIArgInfo classifyReturnType(QualType RetTy) const;
666
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
667
668
845
  void computeInfo(CGFunctionInfo &FI) const override {
669
845
    if (!getCXXABI().classifyReturnType(FI))
670
844
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
671
845
    for (auto &I : FI.arguments())
672
1.39k
      I.info = classifyArgumentType(I.type);
673
845
  }
674
675
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
676
3
                    QualType Ty) const override {
677
3
    return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
678
3
  }
679
};
680
681
class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
682
public:
683
  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
684
24
    : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
685
};
686
687
2.60k
ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
688
2.60k
  Ty = useFirstFieldIfTransparentUnion(Ty);
689
2.60k
690
2.60k
  if (isAggregateTypeForABI(Ty)) {
691
104
    // Records with non-trivial destructors/copy-constructors should not be
692
104
    // passed by value.
693
104
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
694
2
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
695
102
696
102
    return getNaturalAlignIndirect(Ty);
697
102
  }
698
2.49k
699
2.49k
  // Treat an enum type as its underlying type.
700
2.49k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
701
9
    Ty = EnumTy->getDecl()->getIntegerType();
702
2.49k
703
2.49k
  return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)89
704
2.49k
                                        : 
ABIArgInfo::getDirect()2.40k
);
705
2.49k
}
706
707
1.89k
ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
708
1.89k
  if (RetTy->isVoidType())
709
1.04k
    return ABIArgInfo::getIgnore();
710
847
711
847
  if (isAggregateTypeForABI(RetTy))
712
48
    return getNaturalAlignIndirect(RetTy);
713
799
714
799
  // Treat an enum type as its underlying type.
715
799
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
716
0
    RetTy = EnumTy->getDecl()->getIntegerType();
717
799
718
799
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)69
719
799
                                           : 
ABIArgInfo::getDirect()730
);
720
799
}
721
722
//===----------------------------------------------------------------------===//
723
// WebAssembly ABI Implementation
724
//
725
// This is a very simple ABI that relies a lot on DefaultABIInfo.
726
//===----------------------------------------------------------------------===//
727
728
class WebAssemblyABIInfo final : public SwiftABIInfo {
729
public:
730
  enum ABIKind {
731
    MVP = 0,
732
    ExperimentalMV = 1,
733
  };
734
735
private:
736
  DefaultABIInfo defaultInfo;
737
  ABIKind Kind;
738
739
public:
740
  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind)
741
33
      : SwiftABIInfo(CGT), defaultInfo(CGT), Kind(Kind) {}
742
743
private:
744
  ABIArgInfo classifyReturnType(QualType RetTy) const;
745
  ABIArgInfo classifyArgumentType(QualType Ty) const;
746
747
  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
748
  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
749
  // overload them.
750
316
  void computeInfo(CGFunctionInfo &FI) const override {
751
316
    if (!getCXXABI().classifyReturnType(FI))
752
308
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
753
316
    for (auto &Arg : FI.arguments())
754
300
      Arg.info = classifyArgumentType(Arg.type);
755
316
  }
756
757
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
758
                    QualType Ty) const override;
759
760
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
761
0
                                    bool asReturnValue) const override {
762
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
763
0
  }
764
765
0
  bool isSwiftErrorInRegister() const override {
766
0
    return false;
767
0
  }
768
};
769
770
class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
771
public:
772
  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
773
                                        WebAssemblyABIInfo::ABIKind K)
774
33
      : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT, K)) {}
775
776
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
777
1.11k
                           CodeGen::CodeGenModule &CGM) const override {
778
1.11k
    TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
779
1.11k
    if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
780
964
      if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
781
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
782
1
        llvm::AttrBuilder B;
783
1
        B.addAttribute("wasm-import-module", Attr->getImportModule());
784
1
        Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
785
1
      }
786
964
      if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
787
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
788
1
        llvm::AttrBuilder B;
789
1
        B.addAttribute("wasm-import-name", Attr->getImportName());
790
1
        Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
791
1
      }
792
964
      if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) {
793
2
        llvm::Function *Fn = cast<llvm::Function>(GV);
794
2
        llvm::AttrBuilder B;
795
2
        B.addAttribute("wasm-export-name", Attr->getExportName());
796
2
        Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
797
2
      }
798
964
    }
799
1.11k
800
1.11k
    if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
801
964
      llvm::Function *Fn = cast<llvm::Function>(GV);
802
964
      if (!FD->doesThisDeclarationHaveABody() && 
!FD->hasPrototype()66
)
803
1
        Fn->addFnAttr("no-prototype");
804
964
    }
805
1.11k
  }
806
};
807
808
/// Classify argument of given type \p Ty.
809
300
ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
810
300
  Ty = useFirstFieldIfTransparentUnion(Ty);
811
300
812
300
  if (isAggregateTypeForABI(Ty)) {
813
42
    // Records with non-trivial destructors/copy-constructors should not be
814
42
    // passed by value.
815
42
    if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
816
8
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
817
34
    // Ignore empty structs/unions.
818
34
    if (isEmptyRecord(getContext(), Ty, true))
819
4
      return ABIArgInfo::getIgnore();
820
30
    // Lower single-element structs to just pass a regular value. TODO: We
821
30
    // could do reasonable-size multiple-element structs too, using getExpand(),
822
30
    // though watch out for things like bitfields.
823
30
    if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
824
11
      return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
825
19
    // For the experimental multivalue ABI, fully expand all other aggregates
826
19
    if (Kind == ABIKind::ExperimentalMV) {
827
3
      const RecordType *RT = Ty->getAs<RecordType>();
828
3
      assert(RT);
829
3
      bool HasBitField = false;
830
5
      for (auto *Field : RT->getDecl()->fields()) {
831
5
        if (Field->isBitField()) {
832
1
          HasBitField = true;
833
1
          break;
834
1
        }
835
5
      }
836
3
      if (!HasBitField)
837
2
        return ABIArgInfo::getExpand();
838
275
    }
839
19
  }
840
275
841
275
  // Otherwise just do the default thing.
842
275
  return defaultInfo.classifyArgumentType(Ty);
843
275
}
844
845
308
ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
846
308
  if (isAggregateTypeForABI(RetTy)) {
847
30
    // Records with non-trivial destructors/copy-constructors should not be
848
30
    // returned by value.
849
30
    if (!getRecordArgABI(RetTy, getCXXABI())) {
850
30
      // Ignore empty structs/unions.
851
30
      if (isEmptyRecord(getContext(), RetTy, true))
852
4
        return ABIArgInfo::getIgnore();
853
26
      // Lower single-element structs to just return a regular value. TODO: We
854
26
      // could do reasonable-size multiple-element structs too, using
855
26
      // ABIArgInfo::getDirect().
856
26
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
857
11
        return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
858
15
      // For the experimental multivalue ABI, return all other aggregates
859
15
      if (Kind == ABIKind::ExperimentalMV)
860
3
        return ABIArgInfo::getDirect();
861
290
    }
862
30
  }
863
290
864
290
  // Otherwise just do the default thing.
865
290
  return defaultInfo.classifyReturnType(RetTy);
866
290
}
867
868
Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
869
5
                                      QualType Ty) const {
870
5
  bool IsIndirect = isAggregateTypeForABI(Ty) &&
871
5
                    
!isEmptyRecord(getContext(), Ty, true)3
&&
872
5
                    
!isSingleElementStruct(Ty, getContext())2
;
873
5
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
874
5
                          getContext().getTypeInfoInChars(Ty),
875
5
                          CharUnits::fromQuantity(4),
876
5
                          /*AllowHigherAlign=*/true);
877
5
}
878
879
//===----------------------------------------------------------------------===//
880
// le32/PNaCl bitcode ABI Implementation
881
//
882
// This is a simplified version of the x86_32 ABI.  Arguments and return values
883
// are always passed on the stack.
884
//===----------------------------------------------------------------------===//
885
886
class PNaClABIInfo : public ABIInfo {
887
 public:
888
16
  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
889
890
  ABIArgInfo classifyReturnType(QualType RetTy) const;
891
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
892
893
  void computeInfo(CGFunctionInfo &FI) const override;
894
  Address EmitVAArg(CodeGenFunction &CGF,
895
                    Address VAListAddr, QualType Ty) const override;
896
};
897
898
class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
899
 public:
900
  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
901
16
    : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
902
};
903
904
91
void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
905
91
  if (!getCXXABI().classifyReturnType(FI))
906
91
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
907
91
908
91
  for (auto &I : FI.arguments())
909
62
    I.info = classifyArgumentType(I.type);
910
91
}
911
912
Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
913
3
                                QualType Ty) const {
914
3
  // The PNaCL ABI is a bit odd, in that varargs don't use normal
915
3
  // function classification. Structs get passed directly for varargs
916
3
  // functions, through a rewriting transform in
917
3
  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
918
3
  // this target to actually support a va_arg instructions with an
919
3
  // aggregate type, unlike other targets.
920
3
  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
921
3
}
922
923
/// Classify argument of given type \p Ty.
924
62
ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
925
62
  if (isAggregateTypeForABI(Ty)) {
926
9
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
927
0
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
928
9
    return getNaturalAlignIndirect(Ty);
929
53
  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
930
1
    // Treat an enum type as its underlying type.
931
1
    Ty = EnumTy->getDecl()->getIntegerType();
932
52
  } else if (Ty->isFloatingType()) {
933
19
    // Floating-point types don't go inreg.
934
19
    return ABIArgInfo::getDirect();
935
19
  }
936
34
937
34
  return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)5
938
34
                                        : 
ABIArgInfo::getDirect()29
);
939
34
}
940
941
91
ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
942
91
  if (RetTy->isVoidType())
943
35
    return ABIArgInfo::getIgnore();
944
56
945
56
  // In the PNaCl ABI we always return records/structures on the stack.
946
56
  if (isAggregateTypeForABI(RetTy))
947
2
    return getNaturalAlignIndirect(RetTy);
948
54
949
54
  // Treat an enum type as its underlying type.
950
54
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
951
0
    RetTy = EnumTy->getDecl()->getIntegerType();
952
54
953
54
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)18
954
54
                                           : 
ABIArgInfo::getDirect()36
);
955
54
}
956
957
/// IsX86_MMXType - Return true if this is an MMX type.
958
51
bool IsX86_MMXType(llvm::Type *IRType) {
959
51
  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
960
51
  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
961
51
    
cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy()18
&&
962
51
    
IRType->getScalarSizeInBits() != 6416
;
963
51
}
964
965
static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
966
                                          StringRef Constraint,
967
1.04k
                                          llvm::Type* Ty) {
968
1.04k
  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
969
1.04k
                     .Cases("y", "&y", "^Ym", true)
970
1.04k
                     .Default(false);
971
1.04k
  if (IsMMXCons && 
Ty->isVectorTy()18
) {
972
14
    if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
973
0
      // Invalid MMX constraint
974
0
      return nullptr;
975
0
    }
976
14
977
14
    return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
978
14
  }
979
1.03k
980
1.03k
  // No operation needed
981
1.03k
  return Ty;
982
1.03k
}
983
984
/// Returns true if this type can be passed in SSE registers with the
985
/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
986
760
static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
987
760
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
988
464
    if (BT->isFloatingPoint() && 
BT->getKind() != BuiltinType::Half272
) {
989
272
      if (BT->getKind() == BuiltinType::LongDouble) {
990
6
        if (&Context.getTargetInfo().getLongDoubleFormat() ==
991
6
            &llvm::APFloat::x87DoubleExtended())
992
2
          return false;
993
270
      }
994
270
      return true;
995
270
    }
996
296
  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
997
263
    // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
998
263
    // registers specially.
999
263
    unsigned VecSize = Context.getTypeSize(VT);
1000
263
    if (VecSize == 128 || 
VecSize == 2560
||
VecSize == 5120
)
1001
263
      return true;
1002
225
  }
1003
225
  return false;
1004
225
}
1005
1006
/// Returns true if this aggregate is small enough to be passed in SSE registers
1007
/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1008
721
static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
1009
721
  return NumMembers <= 4;
1010
721
}
1011
1012
/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
1013
30
static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
1014
30
  auto AI = ABIArgInfo::getDirect(T);
1015
30
  AI.setInReg(true);
1016
30
  AI.setCanBeFlattened(false);
1017
30
  return AI;
1018
30
}
1019
1020
//===----------------------------------------------------------------------===//
1021
// X86-32 ABI Implementation
1022
//===----------------------------------------------------------------------===//
1023
1024
/// Similar to llvm::CCState, but for Clang.
1025
struct CCState {
1026
  CCState(CGFunctionInfo &FI)
1027
15.4k
      : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {}
1028
1029
  llvm::SmallBitVector IsPreassigned;
1030
  unsigned CC = CallingConv::CC_C;
1031
  unsigned FreeRegs = 0;
1032
  unsigned FreeSSERegs = 0;
1033
};
1034
1035
enum {
1036
  // Vectorcall only allows the first 6 parameters to be passed in registers.
1037
  VectorcallMaxParamNumAsReg = 6
1038
};
1039
1040
/// X86_32ABIInfo - The X86-32 ABI information.
1041
class X86_32ABIInfo : public SwiftABIInfo {
1042
  enum Class {
1043
    Integer,
1044
    Float
1045
  };
1046
1047
  static const unsigned MinABIStackAlignInBytes = 4;
1048
1049
  bool IsDarwinVectorABI;
1050
  bool IsRetSmallStructInRegABI;
1051
  bool IsWin32StructABI;
1052
  bool IsSoftFloatABI;
1053
  bool IsMCUABI;
1054
  unsigned DefaultNumRegisterParameters;
1055
1056
525
  static bool isRegisterSize(unsigned Size) {
1057
525
    return (Size == 8 || 
Size == 16494
||
Size == 32475
||
Size == 64233
);
1058
525
  }
1059
1060
391
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1061
391
    // FIXME: Assumes vectorcall is in use.
1062
391
    return isX86VectorTypeForVectorCall(getContext(), Ty);
1063
391
  }
1064
1065
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1066
315
                                         uint64_t NumMembers) const override {
1067
315
    // FIXME: Assumes vectorcall is in use.
1068
315
    return isX86VectorCallAggregateSmallEnough(NumMembers);
1069
315
  }
1070
1071
  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1072
1073
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1074
  /// such that the argument will be passed in memory.
1075
  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1076
1077
  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1078
1079
  /// Return the alignment to use for the given type on the stack.
1080
  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1081
1082
  Class classify(QualType Ty) const;
1083
  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1084
  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1085
1086
  /// Updates the number of available free registers, returns
1087
  /// true if any registers were allocated.
1088
  bool updateFreeRegs(QualType Ty, CCState &State) const;
1089
1090
  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1091
                                bool &NeedsPadding) const;
1092
  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1093
1094
  bool canExpandIndirectArgument(QualType Ty) const;
1095
1096
  /// Rewrite the function info so that all memory arguments use
1097
  /// inalloca.
1098
  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1099
1100
  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1101
                           CharUnits &StackOffset, ABIArgInfo &Info,
1102
                           QualType Type) const;
1103
  void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
1104
1105
public:
1106
1107
  void computeInfo(CGFunctionInfo &FI) const override;
1108
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1109
                    QualType Ty) const override;
1110
1111
  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1112
                bool RetSmallStructInRegABI, bool Win32StructABI,
1113
                unsigned NumRegisterParameters, bool SoftFloatABI)
1114
    : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1115
      IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1116
      IsWin32StructABI(Win32StructABI),
1117
      IsSoftFloatABI(SoftFloatABI),
1118
      IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1119
2.45k
      DefaultNumRegisterParameters(NumRegisterParameters) {}
1120
1121
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1122
0
                                    bool asReturnValue) const override {
1123
0
    // LLVM's x86-32 lowering currently only assigns up to three
1124
0
    // integer registers and three fp registers.  Oddly, it'll use up to
1125
0
    // four vector registers for vectors, but those can overlap with the
1126
0
    // scalar registers.
1127
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1128
0
  }
1129
1130
0
  bool isSwiftErrorInRegister() const override {
1131
0
    // x86-32 lowering does not support passing swifterror in a register.
1132
0
    return false;
1133
0
  }
1134
};
1135
1136
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1137
public:
1138
  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1139
                          bool RetSmallStructInRegABI, bool Win32StructABI,
1140
                          unsigned NumRegisterParameters, bool SoftFloatABI)
1141
      : TargetCodeGenInfo(new X86_32ABIInfo(
1142
            CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1143
2.45k
            NumRegisterParameters, SoftFloatABI)) {}
1144
1145
  static bool isStructReturnInRegABI(
1146
      const llvm::Triple &Triple, const CodeGenOptions &Opts);
1147
1148
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1149
                           CodeGen::CodeGenModule &CGM) const override;
1150
1151
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1152
0
    // Darwin uses different dwarf register numbers for EH.
1153
0
    if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1154
0
    return 4;
1155
0
  }
1156
1157
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1158
                               llvm::Value *Address) const override;
1159
1160
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1161
                                  StringRef Constraint,
1162
537
                                  llvm::Type* Ty) const override {
1163
537
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1164
537
  }
1165
1166
  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1167
                                std::string &Constraints,
1168
                                std::vector<llvm::Type *> &ResultRegTypes,
1169
                                std::vector<llvm::Type *> &ResultTruncRegTypes,
1170
                                std::vector<LValue> &ResultRegDests,
1171
                                std::string &AsmString,
1172
                                unsigned NumOutputs) const override;
1173
1174
  llvm::Constant *
1175
37
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1176
37
    unsigned Sig = (0xeb << 0) |  // jmp rel8
1177
37
                   (0x06 << 8) |  //           .+0x08
1178
37
                   ('v' << 16) |
1179
37
                   ('2' << 24);
1180
37
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1181
37
  }
1182
1183
7
  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1184
7
    return "movl\t%ebp, %ebp"
1185
7
           "\t\t// marker for objc_retainAutoreleaseReturnValue";
1186
7
  }
1187
};
1188
1189
}
1190
1191
/// Rewrite input constraint references after adding some output constraints.
1192
/// In the case where there is one output and one input and we add one output,
1193
/// we need to replace all operand references greater than or equal to 1:
1194
///     mov $0, $1
1195
///     mov eax, $1
1196
/// The result will be:
1197
///     mov $0, $2
1198
///     mov eax, $2
1199
static void rewriteInputConstraintReferences(unsigned FirstIn,
1200
                                             unsigned NumNewOuts,
1201
23
                                             std::string &AsmString) {
1202
23
  std::string Buf;
1203
23
  llvm::raw_string_ostream OS(Buf);
1204
23
  size_t Pos = 0;
1205
75
  while (Pos < AsmString.size()) {
1206
52
    size_t DollarStart = AsmString.find('$', Pos);
1207
52
    if (DollarStart == std::string::npos)
1208
16
      DollarStart = AsmString.size();
1209
52
    size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1210
52
    if (DollarEnd == std::string::npos)
1211
16
      DollarEnd = AsmString.size();
1212
52
    OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1213
52
    Pos = DollarEnd;
1214
52
    size_t NumDollars = DollarEnd - DollarStart;
1215
52
    if (NumDollars % 2 != 0 && 
Pos < AsmString.size()18
) {
1216
18
      // We have an operand reference.
1217
18
      size_t DigitStart = Pos;
1218
18
      if (AsmString[DigitStart] == '{') {
1219
3
        OS << '{';
1220
3
        ++DigitStart;
1221
3
      }
1222
18
      size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1223
18
      if (DigitEnd == std::string::npos)
1224
5
        DigitEnd = AsmString.size();
1225
18
      StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1226
18
      unsigned OperandIndex;
1227
18
      if (!OperandStr.getAsInteger(10, OperandIndex)) {
1228
18
        if (OperandIndex >= FirstIn)
1229
14
          OperandIndex += NumNewOuts;
1230
18
        OS << OperandIndex;
1231
18
      } else {
1232
0
        OS << OperandStr;
1233
0
      }
1234
18
      Pos = DigitEnd;
1235
18
    }
1236
52
  }
1237
23
  AsmString = std::move(OS.str());
1238
23
}
1239
1240
/// Add output constraints for EAX:EDX because they are return registers.
1241
void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1242
    CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1243
    std::vector<llvm::Type *> &ResultRegTypes,
1244
    std::vector<llvm::Type *> &ResultTruncRegTypes,
1245
    std::vector<LValue> &ResultRegDests, std::string &AsmString,
1246
23
    unsigned NumOutputs) const {
1247
23
  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1248
23
1249
23
  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1250
23
  // larger.
1251
23
  if (!Constraints.empty())
1252
3
    Constraints += ',';
1253
23
  if (RetWidth <= 32) {
1254
20
    Constraints += "={eax}";
1255
20
    ResultRegTypes.push_back(CGF.Int32Ty);
1256
20
  } else {
1257
3
    // Use the 'A' constraint for EAX:EDX.
1258
3
    Constraints += "=A";
1259
3
    ResultRegTypes.push_back(CGF.Int64Ty);
1260
3
  }
1261
23
1262
23
  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1263
23
  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1264
23
  ResultTruncRegTypes.push_back(CoerceTy);
1265
23
1266
23
  // Coerce the integer by bitcasting the return slot pointer.
1267
23
  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(CGF),
1268
23
                                                  CoerceTy->getPointerTo()));
1269
23
  ResultRegDests.push_back(ReturnSlot);
1270
23
1271
23
  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1272
23
}
1273
1274
/// shouldReturnTypeInRegister - Determine if the given type should be
1275
/// returned in a register (for the Darwin and MCU ABI).
1276
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1277
544
                                               ASTContext &Context) const {
1278
544
  uint64_t Size = Context.getTypeSize(Ty);
1279
544
1280
544
  // For i386, type must be register sized.
1281
544
  // For the MCU ABI, it only needs to be <= 8-byte
1282
544
  if ((IsMCUABI && 
Size > 6419
) ||
(541
!IsMCUABI541
&&
!isRegisterSize(Size)525
))
1283
68
   return false;
1284
476
1285
476
  if (Ty->isVectorType()) {
1286
4
    // 64- and 128- bit vectors inside structures are not returned in
1287
4
    // registers.
1288
4
    if (Size == 64 || 
Size == 1281
)
1289
3
      return false;
1290
1
1291
1
    return true;
1292
1
  }
1293
472
1294
472
  // If this is a builtin, pointer, enum, complex type, member pointer, or
1295
472
  // member function pointer it is ok.
1296
472
  if (Ty->getAs<BuiltinType>() || 
Ty->hasPointerRepresentation()380
||
1297
472
      
Ty->isAnyComplexType()374
||
Ty->isEnumeralType()355
||
1298
472
      
Ty->isBlockPointerType()353
||
Ty->isMemberPointerType()353
)
1299
381
    return true;
1300
91
1301
91
  // Arrays are treated like records.
1302
91
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1303
6
    return shouldReturnTypeInRegister(AT->getElementType(), Context);
1304
85
1305
85
  // Otherwise, it must be a record type.
1306
85
  const RecordType *RT = Ty->getAs<RecordType>();
1307
85
  if (!RT) 
return false0
;
1308
85
1309
85
  // FIXME: Traverse bases here too.
1310
85
1311
85
  // Structure types are passed in register if all fields would be
1312
85
  // passed in a register.
1313
119
  
for (const auto *FD : RT->getDecl()->fields())85
{
1314
119
    // Empty fields are ignored.
1315
119
    if (isEmptyField(Context, FD, true))
1316
11
      continue;
1317
108
1318
108
    // Check fields recursively.
1319
108
    if (!shouldReturnTypeInRegister(FD->getType(), Context))
1320
4
      return false;
1321
108
  }
1322
85
  
return true81
;
1323
85
}
1324
1325
204
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1326
204
  // Treat complex types as the element type.
1327
204
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1328
2
    Ty = CTy->getElementType();
1329
204
1330
204
  // Check for a type which we know has a simple scalar argument-passing
1331
204
  // convention without any padding.  (We're specifically looking for 32
1332
204
  // and 64-bit integer and integer-equivalents, float, and double.)
1333
204
  if (!Ty->getAs<BuiltinType>() && 
!Ty->hasPointerRepresentation()36
&&
1334
204
      
!Ty->isEnumeralType()31
&&
!Ty->isBlockPointerType()28
)
1335
28
    return false;
1336
176
1337
176
  uint64_t Size = Context.getTypeSize(Ty);
1338
176
  return Size == 32 || 
Size == 6428
;
1339
176
}
1340
1341
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1342
240
                          uint64_t &Size) {
1343
240
  for (const auto *FD : RD->fields()) {
1344
204
    // Scalar arguments on the stack get 4 byte alignment on x86. If the
1345
204
    // argument is smaller than 32-bits, expanding the struct will create
1346
204
    // alignment padding.
1347
204
    if (!is32Or64BitBasicType(FD->getType(), Context))
1348
49
      return false;
1349
155
1350
155
    // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1351
155
    // how to expand them yet, and the predicate for telling if a bitfield still
1352
155
    // counts as "basic" is more complicated than what we were doing previously.
1353
155
    if (FD->isBitField())
1354
2
      return false;
1355
153
1356
153
    Size += Context.getTypeSize(FD->getType());
1357
153
  }
1358
240
  
return true189
;
1359
240
}
1360
1361
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1362
138
                                 uint64_t &Size) {
1363
138
  // Don't do this if there are any non-empty bases.
1364
138
  for (const CXXBaseSpecifier &Base : RD->bases()) {
1365
1
    if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1366
1
                              Size))
1367
0
      return false;
1368
1
  }
1369
138
  if (!addFieldSizes(Context, RD, Size))
1370
9
    return false;
1371
129
  return true;
1372
129
}
1373
1374
/// Test whether an argument type which is to be passed indirectly (on the
1375
/// stack) would have the equivalent layout if it was expanded into separate
1376
/// arguments. If so, we prefer to do the latter to avoid inhibiting
1377
/// optimizations.
1378
318
bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1379
318
  // We can only expand structure types.
1380
318
  const RecordType *RT = Ty->getAs<RecordType>();
1381
318
  if (!RT)
1382
66
    return false;
1383
252
  const RecordDecl *RD = RT->getDecl();
1384
252
  uint64_t Size = 0;
1385
252
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1386
150
    if (!IsWin32StructABI) {
1387
33
      // On non-Windows, we have to conservatively match our old bitcode
1388
33
      // prototypes in order to be ABI-compatible at the bitcode level.
1389
33
      if (!CXXRD->isCLike())
1390
13
        return false;
1391
117
    } else {
1392
117
      // Don't do this for dynamic classes.
1393
117
      if (CXXRD->isDynamicClass())
1394
0
        return false;
1395
137
    }
1396
137
    if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1397
9
      return false;
1398
102
  } else {
1399
102
    if (!addFieldSizes(getContext(), RD, Size))
1400
42
      return false;
1401
188
  }
1402
188
1403
188
  // We can do this if there was no alignment padding.
1404
188
  return Size == getContext().getTypeSize(Ty);
1405
188
}
1406
1407
137
ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1408
137
  // If the return value is indirect, then the hidden argument is consuming one
1409
137
  // integer register.
1410
137
  if (State.FreeRegs) {
1411
6
    --State.FreeRegs;
1412
6
    if (!IsMCUABI)
1413
3
      return getNaturalAlignIndirectInReg(RetTy);
1414
134
  }
1415
134
  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1416
134
}
1417
1418
ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1419
15.3k
                                             CCState &State) const {
1420
15.3k
  if (RetTy->isVoidType())
1421
9.92k
    return ABIArgInfo::getIgnore();
1422
5.41k
1423
5.41k
  const Type *Base = nullptr;
1424
5.41k
  uint64_t NumElts = 0;
1425
5.41k
  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1426
5.41k
       
State.CC == llvm::CallingConv::X86_RegCall5.40k
) &&
1427
5.41k
      
isHomogeneousAggregate(RetTy, Base, NumElts)23
) {
1428
14
    // The LLVM struct type for such an aggregate should lower properly.
1429
14
    return ABIArgInfo::getDirect();
1430
14
  }
1431
5.39k
1432
5.39k
  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1433
31
    // On Darwin, some vectors are returned in registers.
1434
31
    if (IsDarwinVectorABI) {
1435
15
      uint64_t Size = getContext().getTypeSize(RetTy);
1436
15
1437
15
      // 128-bit vectors are a special case; they are returned in
1438
15
      // registers and we need to make sure to pick a type the LLVM
1439
15
      // backend will like.
1440
15
      if (Size == 128)
1441
5
        return ABIArgInfo::getDirect(llvm::VectorType::get(
1442
5
                  llvm::Type::getInt64Ty(getVMContext()), 2));
1443
10
1444
10
      // Always return in register if it fits in a general purpose
1445
10
      // register, or if it is 64 bits and has a single element.
1446
10
      if ((Size == 8 || Size == 16 || Size == 32) ||
1447
10
          
(7
Size == 647
&&
VT->getNumElements() == 17
))
1448
7
        return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1449
7
                                                            Size));
1450
3
1451
3
      return getIndirectReturnResult(RetTy, State);
1452
3
    }
1453
16
1454
16
    return ABIArgInfo::getDirect();
1455
16
  }
1456
5.36k
1457
5.36k
  if (isAggregateTypeForABI(RetTy)) {
1458
527
    if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1459
205
      // Structures with flexible arrays are always indirect.
1460
205
      if (RT->getDecl()->hasFlexibleArrayMember())
1461
1
        return getIndirectReturnResult(RetTy, State);
1462
526
    }
1463
526
1464
526
    // If specified, structs and unions are always indirect.
1465
526
    if (!IsRetSmallStructInRegABI && 
!RetTy->isAnyComplexType()106
)
1466
62
      return getIndirectReturnResult(RetTy, State);
1467
464
1468
464
    // Ignore empty structs/unions.
1469
464
    if (isEmptyRecord(getContext(), RetTy, true))
1470
34
      return ABIArgInfo::getIgnore();
1471
430
1472
430
    // Small structures which are register sized are generally returned
1473
430
    // in a register.
1474
430
    if (shouldReturnTypeInRegister(RetTy, getContext())) {
1475
359
      uint64_t Size = getContext().getTypeSize(RetTy);
1476
359
1477
359
      // As a special-case, if the struct is a "single-element" struct, and
1478
359
      // the field is of type "float" or "double", return it in a
1479
359
      // floating-point register. (MSVC does not apply this special case.)
1480
359
      // We apply a similar transformation for pointer types to improve the
1481
359
      // quality of the generated IR.
1482
359
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1483
54
        if ((!IsWin32StructABI && 
SeltTy->isRealFloatingType()42
)
1484
54
            || 
SeltTy->hasPointerRepresentation()38
)
1485
20
          return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1486
339
1487
339
      // FIXME: We should be able to narrow this integer in cases with dead
1488
339
      // padding.
1489
339
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1490
339
    }
1491
71
1492
71
    return getIndirectReturnResult(RetTy, State);
1493
71
  }
1494
4.83k
1495
4.83k
  // Treat an enum type as its underlying type.
1496
4.83k
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1497
35
    RetTy = EnumTy->getDecl()->getIntegerType();
1498
4.83k
1499
4.83k
  return (RetTy->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(RetTy)117
1500
4.83k
                                           : 
ABIArgInfo::getDirect()4.72k
);
1501
4.83k
}
1502
1503
36
static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1504
36
  return Ty->getAs<VectorType>() && 
Context.getTypeSize(Ty) == 12812
;
1505
36
}
1506
1507
28
static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1508
28
  const RecordType *RT = Ty->getAs<RecordType>();
1509
28
  if (!RT)
1510
12
    return 0;
1511
16
  const RecordDecl *RD = RT->getDecl();
1512
16
1513
16
  // If this is a C++ record, check the bases first.
1514
16
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1515
0
    for (const auto &I : CXXRD->bases())
1516
0
      if (!isRecordWithSSEVectorType(Context, I.getType()))
1517
0
        return false;
1518
16
1519
19
  
for (const auto *i : RD->fields())16
{
1520
19
    QualType FT = i->getType();
1521
19
1522
19
    if (isSSEVectorType(Context, FT))
1523
7
      return true;
1524
12
1525
12
    if (isRecordWithSSEVectorType(Context, FT))
1526
0
      return true;
1527
12
  }
1528
16
1529
16
  
return false9
;
1530
16
}
1531
1532
unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1533
295
                                                 unsigned Align) const {
1534
295
  // Otherwise, if the alignment is less than or equal to the minimum ABI
1535
295
  // alignment, just use the default; the backend will handle this.
1536
295
  if (Align <= MinABIStackAlignInBytes)
1537
245
    return 0; // Use default alignment.
1538
50
1539
50
  // On non-Darwin, the stack type alignment is always 4.
1540
50
  if (!IsDarwinVectorABI) {
1541
23
    // Set explicit alignment, since we may need to realign the top.
1542
23
    return MinABIStackAlignInBytes;
1543
23
  }
1544
27
1545
27
  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1546
27
  if (Align >= 16 && 
(17
isSSEVectorType(getContext(), Ty)17
||
1547
17
                      
isRecordWithSSEVectorType(getContext(), Ty)16
))
1548
8
    return 16;
1549
19
1550
19
  return MinABIStackAlignInBytes;
1551
19
}
1552
1553
ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1554
421
                                            CCState &State) const {
1555
421
  if (!ByVal) {
1556
138
    if (State.FreeRegs) {
1557
22
      --State.FreeRegs; // Non-byval indirects just use one pointer.
1558
22
      if (!IsMCUABI)
1559
22
        return getNaturalAlignIndirectInReg(Ty);
1560
116
    }
1561
116
    return getNaturalAlignIndirect(Ty, false);
1562
116
  }
1563
283
1564
283
  // Compute the byval alignment.
1565
283
  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1566
283
  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1567
283
  if (StackAlign == 0)
1568
235
    return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1569
48
1570
48
  // If the stack alignment is less than the type alignment, realign the
1571
48
  // argument.
1572
48
  bool Realign = TypeAlign > StackAlign;
1573
48
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1574
48
                                 /*ByVal=*/true, Realign);
1575
48
}
1576
1577
25.8k
X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1578
25.8k
  const Type *T = isSingleElementStruct(Ty, getContext());
1579
25.8k
  if (!T)
1580
25.7k
    T = Ty.getTypePtr();
1581
25.8k
1582
25.8k
  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1583
8.40k
    BuiltinType::Kind K = BT->getKind();
1584
8.40k
    if (K == BuiltinType::Float || 
K == BuiltinType::Double8.15k
)
1585
403
      return Float;
1586
25.4k
  }
1587
25.4k
  return Integer;
1588
25.4k
}
1589
1590
25.9k
bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1591
25.9k
  if (!IsSoftFloatABI) {
1592
25.8k
    Class C = classify(Ty);
1593
25.8k
    if (C == Float)
1594
403
      return false;
1595
25.5k
  }
1596
25.5k
1597
25.5k
  unsigned Size = getContext().getTypeSize(Ty);
1598
25.5k
  unsigned SizeInRegs = (Size + 31) / 32;
1599
25.5k
1600
25.5k
  if (SizeInRegs == 0)
1601
2
    return false;
1602
25.4k
1603
25.4k
  if (!IsMCUABI) {
1604
25.4k
    if (SizeInRegs > State.FreeRegs) {
1605
25.2k
      State.FreeRegs = 0;
1606
25.2k
      return false;
1607
25.2k
    }
1608
42
  } else {
1609
42
    // The MCU psABI allows passing parameters in-reg even if there are
1610
42
    // earlier parameters that are passed on the stack. Also,
1611
42
    // it does not allow passing >8-byte structs in-register,
1612
42
    // even if there are 3 free registers available.
1613
42
    if (SizeInRegs > State.FreeRegs || 
SizeInRegs > 234
)
1614
9
      return false;
1615
238
  }
1616
238
1617
238
  State.FreeRegs -= SizeInRegs;
1618
238
  return true;
1619
238
}
1620
1621
bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1622
                                             bool &InReg,
1623
384
                                             bool &NeedsPadding) const {
1624
384
  // On Windows, aggregates other than HFAs are never passed in registers, and
1625
384
  // they do not consume register slots. Homogenous floating-point aggregates
1626
384
  // (HFAs) have already been dealt with at this point.
1627
384
  if (IsWin32StructABI && 
isAggregateTypeForABI(Ty)164
)
1628
164
    return false;
1629
220
1630
220
  NeedsPadding = false;
1631
220
  InReg = !IsMCUABI;
1632
220
1633
220
  if (!updateFreeRegs(Ty, State))
1634
200
    return false;
1635
20
1636
20
  if (IsMCUABI)
1637
7
    return true;
1638
13
1639
13
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1640
13
      
State.CC == llvm::CallingConv::X86_VectorCall10
||
1641
13
      
State.CC == llvm::CallingConv::X86_RegCall10
) {
1642
4
    if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1643
3
      NeedsPadding = true;
1644
4
1645
4
    return false;
1646
4
  }
1647
9
1648
9
  return true;
1649
9
}
1650
1651
25.6k
bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1652
25.6k
  if (!updateFreeRegs(Ty, State))
1653
25.4k
    return false;
1654
218
1655
218
  if (IsMCUABI)
1656
26
    return false;
1657
192
1658
192
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1659
192
      
State.CC == llvm::CallingConv::X86_VectorCall136
||
1660
192
      
State.CC == llvm::CallingConv::X86_RegCall94
) {
1661
141
    if (getContext().getTypeSize(Ty) > 32)
1662
13
      return false;
1663
128
1664
128
    return (Ty->isIntegralOrEnumerationType() || 
Ty->isPointerType()27
||
1665
128
        
Ty->isReferenceType()7
);
1666
128
  }
1667
51
1668
51
  return true;
1669
51
}
1670
1671
54
void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
1672
54
  // Vectorcall x86 works subtly different than in x64, so the format is
1673
54
  // a bit different than the x64 version.  First, all vector types (not HVAs)
1674
54
  // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
1675
54
  // This differs from the x64 implementation, where the first 6 by INDEX get
1676
54
  // registers.
1677
54
  // In the second pass over the arguments, HVAs are passed in the remaining
1678
54
  // vector registers if possible, or indirectly by address. The address will be
1679
54
  // passed in ECX/EDX if available. Any other arguments are passed according to
1680
54
  // the usual fastcall rules.
1681
54
  MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
1682
165
  for (int I = 0, E = Args.size(); I < E; 
++I111
) {
1683
111
    const Type *Base = nullptr;
1684
111
    uint64_t NumElts = 0;
1685
111
    const QualType &Ty = Args[I].type;
1686
111
    if ((Ty->isVectorType() || 
Ty->isBuiltinType()90
) &&
1687
111
        
isHomogeneousAggregate(Ty, Base, NumElts)81
) {
1688
40
      if (State.FreeSSERegs >= NumElts) {
1689
36
        State.FreeSSERegs -= NumElts;
1690
36
        Args[I].info = ABIArgInfo::getDirect();
1691
36
        State.IsPreassigned.set(I);
1692
36
      }
1693
40
    }
1694
111
  }
1695
54
}
1696
1697
ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1698
26.4k
                                               CCState &State) const {
1699
26.4k
  // FIXME: Set alignment on indirect arguments.
1700
26.4k
  bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
1701
26.4k
  bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
1702
26.4k
  bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
1703
26.4k
1704
26.4k
  Ty = useFirstFieldIfTransparentUnion(Ty);
1705
26.4k
  TypeInfo TI = getContext().getTypeInfo(Ty);
1706
26.4k
1707
26.4k
  // Check with the C++ ABI first.
1708
26.4k
  const RecordType *RT = Ty->getAs<RecordType>();
1709
26.4k
  if (RT) {
1710
575
    CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1711
575
    if (RAA == CGCXXABI::RAA_Indirect) {
1712
98
      return getIndirectResult(Ty, false, State);
1713
477
    } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1714
82
      // The field index doesn't matter, we'll fix it up later.
1715
82
      return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1716
82
    }
1717
26.2k
  }
1718
26.2k
1719
26.2k
  // Regcall uses the concept of a homogenous vector aggregate, similar
1720
26.2k
  // to other targets.
1721
26.2k
  const Type *Base = nullptr;
1722
26.2k
  uint64_t NumElts = 0;
1723
26.2k
  if ((IsRegCall || 
IsVectorCall26.1k
) &&
1724
26.2k
      
isHomogeneousAggregate(Ty, Base, NumElts)176
) {
1725
77
    if (State.FreeSSERegs >= NumElts) {
1726
55
      State.FreeSSERegs -= NumElts;
1727
55
1728
55
      // Vectorcall passes HVAs directly and does not flatten them, but regcall
1729
55
      // does.
1730
55
      if (IsVectorCall)
1731
12
        return getDirectX86Hva();
1732
43
1733
43
      if (Ty->isBuiltinType() || 
Ty->isVectorType()33
)
1734
20
        return ABIArgInfo::getDirect();
1735
23
      return ABIArgInfo::getExpand();
1736
23
    }
1737
22
    return getIndirectResult(Ty, /*ByVal=*/false, State);
1738
22
  }
1739
26.2k
1740
26.2k
  if (isAggregateTypeForABI(Ty)) {
1741
423
    // Structures with flexible arrays are always indirect.
1742
423
    // FIXME: This should not be byval!
1743
423
    if (RT && 
RT->getDecl()->hasFlexibleArrayMember()347
)
1744
1
      return getIndirectResult(Ty, true, State);
1745
422
1746
422
    // Ignore empty structs/unions on non-Windows.
1747
422
    if (!IsWin32StructABI && 
isEmptyRecord(getContext(), Ty, true)258
)
1748
38
      return ABIArgInfo::getIgnore();
1749
384
1750
384
    llvm::LLVMContext &LLVMContext = getVMContext();
1751
384
    llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1752
384
    bool NeedsPadding = false;
1753
384
    bool InReg;
1754
384
    if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1755
16
      unsigned SizeInRegs = (TI.Width + 31) / 32;
1756
16
      SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1757
16
      llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1758
16
      if (InReg)
1759
9
        return ABIArgInfo::getDirectInReg(Result);
1760
7
      else
1761
7
        return ABIArgInfo::getDirect(Result);
1762
368
    }
1763
368
    llvm::IntegerType *PaddingType = NeedsPadding ? 
Int323
:
nullptr365
;
1764
368
1765
368
    // Pass over-aligned aggregates on Windows indirectly. This behavior was
1766
368
    // added in MSVC 2015.
1767
368
    if (IsWin32StructABI && 
TI.AlignIsRequired164
&&
TI.Align > 321
)
1768
1
      return getIndirectResult(Ty, /*ByVal=*/false, State);
1769
367
1770
367
    // Expand small (<= 128-bit) record types when we know that the stack layout
1771
367
    // of those arguments will match the struct. This is important because the
1772
367
    // LLVM backend isn't smart enough to remove byval, which inhibits many
1773
367
    // optimizations.
1774
367
    // Don't do this for the MCU if there are still free integer registers
1775
367
    // (see X86_64 ABI for full explanation).
1776
367
    if (TI.Width <= 4 * 32 && 
(321
!IsMCUABI321
||
State.FreeRegs == 05
) &&
1777
367
        
canExpandIndirectArgument(Ty)318
)
1778
85
      return ABIArgInfo::getExpandWithPadding(
1779
85
          IsFastCall || 
IsVectorCall81
||
IsRegCall80
, PaddingType);
1780
282
1781
282
    return getIndirectResult(Ty, true, State);
1782
282
  }
1783
25.7k
1784
25.7k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1785
103
    // On Windows, vectors are passed directly if registers are available, or
1786
103
    // indirectly if not. This avoids the need to align argument memory. Pass
1787
103
    // user-defined vector types larger than 512 bits indirectly for simplicity.
1788
103
    if (IsWin32StructABI) {
1789
45
      if (TI.Width <= 512 && 
State.FreeSSERegs > 040
) {
1790
28
        --State.FreeSSERegs;
1791
28
        return ABIArgInfo::getDirectInReg();
1792
28
      }
1793
17
      return getIndirectResult(Ty, /*ByVal=*/false, State);
1794
17
    }
1795
58
1796
58
    // On Darwin, some vectors are passed in memory, we handle this by passing
1797
58
    // it as an i8/i16/i32/i64.
1798
58
    if (IsDarwinVectorABI) {
1799
24
      if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
1800
24
          
(22
TI.Width == 6422
&&
VT->getNumElements() == 110
))
1801
7
        return ABIArgInfo::getDirect(
1802
7
            llvm::IntegerType::get(getVMContext(), TI.Width));
1803
51
    }
1804
51
1805
51
    if (IsX86_MMXType(CGT.ConvertType(Ty)))
1806
8
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1807
43
1808
43
    return ABIArgInfo::getDirect();
1809
43
  }
1810
25.6k
1811
25.6k
1812
25.6k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1813
20
    Ty = EnumTy->getDecl()->getIntegerType();
1814
25.6k
1815
25.6k
  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1816
25.6k
1817
25.6k
  if (Ty->isPromotableIntegerType()) {
1818
217
    if (InReg)
1819
25
      return ABIArgInfo::getExtendInReg(Ty);
1820
192
    return ABIArgInfo::getExtend(Ty);
1821
192
  }
1822
25.4k
1823
25.4k
  if (InReg)
1824
154
    return ABIArgInfo::getDirectInReg();
1825
25.3k
  return ABIArgInfo::getDirect();
1826
25.3k
}
1827
1828
15.4k
void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1829
15.4k
  CCState State(FI);
1830
15.4k
  if (IsMCUABI)
1831
33
    State.FreeRegs = 3;
1832
15.3k
  else if (State.CC == llvm::CallingConv::X86_FastCall) {
1833
70
    State.FreeRegs = 2;
1834
70
    State.FreeSSERegs = 3;
1835
15.3k
  } else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1836
54
    State.FreeRegs = 2;
1837
54
    State.FreeSSERegs = 6;
1838
15.2k
  } else if (FI.getHasRegParm())
1839
32
    State.FreeRegs = FI.getRegParm();
1840
15.2k
  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1841
50
    State.FreeRegs = 5;
1842
50
    State.FreeSSERegs = 8;
1843
15.1k
  } else if (IsWin32StructABI) {
1844
3.81k
    // Since MSVC 2015, the first three SSE vectors have been passed in
1845
3.81k
    // registers. The rest are passed indirectly.
1846
3.81k
    State.FreeRegs = DefaultNumRegisterParameters;
1847
3.81k
    State.FreeSSERegs = 3;
1848
3.81k
  } else
1849
11.3k
    State.FreeRegs = DefaultNumRegisterParameters;
1850
15.4k
1851
15.4k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1852
15.3k
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1853
15.3k
  } else 
if (79
FI.getReturnInfo().isIndirect()79
) {
1854
79
    // The C++ ABI is not aware of register usage, so we have to check if the
1855
79
    // return value was sret and put it in a register ourselves if appropriate.
1856
79
    if (State.FreeRegs) {
1857
4
      --State.FreeRegs;  // The sret parameter consumes a register.
1858
4
      if (!IsMCUABI)
1859
4
        FI.getReturnInfo().setInReg(true);
1860
4
    }
1861
79
  }
1862
15.4k
1863
15.4k
  // The chain argument effectively gives us another free register.
1864
15.4k
  if (FI.isChainCall())
1865
4
    ++State.FreeRegs;
1866
15.4k
1867
15.4k
  // For vectorcall, do a first pass over the arguments, assigning FP and vector
1868
15.4k
  // arguments to XMM registers as available.
1869
15.4k
  if (State.CC == llvm::CallingConv::X86_VectorCall)
1870
54
    runVectorCallFirstPass(FI, State);
1871
15.4k
1872
15.4k
  bool UsedInAlloca = false;
1873
15.4k
  MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
1874
41.9k
  for (int I = 0, E = Args.size(); I < E; 
++I26.5k
) {
1875
26.5k
    // Skip arguments that have already been assigned.
1876
26.5k
    if (State.IsPreassigned.test(I))
1877
36
      continue;
1878
26.4k
1879
26.4k
    Args[I].info = classifyArgumentType(Args[I].type, State);
1880
26.4k
    UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
1881
26.4k
  }
1882
15.4k
1883
15.4k
  // If we needed to use inalloca for any argument, do a second pass and rewrite
1884
15.4k
  // all the memory arguments to use inalloca.
1885
15.4k
  if (UsedInAlloca)
1886
70
    rewriteWithInAlloca(FI);
1887
15.4k
}
1888
1889
void
1890
X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1891
                                   CharUnits &StackOffset, ABIArgInfo &Info,
1892
168
                                   QualType Type) const {
1893
168
  // Arguments are always 4-byte-aligned.
1894
168
  CharUnits WordSize = CharUnits::fromQuantity(4);
1895
168
  assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct");
1896
168
1897
168
  // sret pointers and indirect things will require an extra pointer
1898
168
  // indirection, unless they are byval. Most things are byval, and will not
1899
168
  // require this indirection.
1900
168
  bool IsIndirect = false;
1901
168
  if (Info.isIndirect() && 
!Info.getIndirectByVal()16
)
1902
13
    IsIndirect = true;
1903
168
  Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
1904
168
  llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
1905
168
  if (IsIndirect)
1906
13
    LLTy = LLTy->getPointerTo(0);
1907
168
  FrameFields.push_back(LLTy);
1908
168
  StackOffset += IsIndirect ? 
WordSize13
:
getContext().getTypeSizeInChars(Type)155
;
1909
168
1910
168
  // Insert padding bytes to respect alignment.
1911
168
  CharUnits FieldEnd = StackOffset;
1912
168
  StackOffset = FieldEnd.alignTo(WordSize);
1913
168
  if (StackOffset != FieldEnd) {
1914
40
    CharUnits NumBytes = StackOffset - FieldEnd;
1915
40
    llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1916
40
    Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1917
40
    FrameFields.push_back(Ty);
1918
40
  }
1919
168
}
1920
1921
172
static bool isArgInAlloca(const ABIArgInfo &Info) {
1922
172
  // Leave ignored and inreg arguments alone.
1923
172
  switch (Info.getKind()) {
1924
82
  case ABIArgInfo::InAlloca:
1925
82
    return true;
1926
0
  case ABIArgInfo::Ignore:
1927
0
    return false;
1928
89
  case ABIArgInfo::Indirect:
1929
89
  case ABIArgInfo::Direct:
1930
89
  case ABIArgInfo::Extend:
1931
89
    return !Info.getInReg();
1932
89
  case ABIArgInfo::Expand:
1933
1
  case ABIArgInfo::CoerceAndExpand:
1934
1
    // These are aggregate types which are never passed in registers when
1935
1
    // inalloca is involved.
1936
1
    return true;
1937
0
  }
1938
0
  llvm_unreachable("invalid enum");
1939
0
}
1940
1941
70
void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1942
70
  assert(IsWin32StructABI && "inalloca only supported on win32");
1943
70
1944
70
  // Build a packed struct type for all of the arguments in memory.
1945
70
  SmallVector<llvm::Type *, 6> FrameFields;
1946
70
1947
70
  // The stack alignment is always 4.
1948
70
  CharUnits StackAlign = CharUnits::fromQuantity(4);
1949
70
1950
70
  CharUnits StackOffset;
1951
70
  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1952
70
1953
70
  // Put 'this' into the struct before 'sret', if necessary.
1954
70
  bool IsThisCall =
1955
70
      FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1956
70
  ABIArgInfo &Ret = FI.getReturnInfo();
1957
70
  if (Ret.isIndirect() && 
Ret.isSRetAfterThis()9
&&
!IsThisCall7
&&
1958
70
      
isArgInAlloca(I->info)6
) {
1959
5
    addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1960
5
    ++I;
1961
5
  }
1962
70
1963
70
  // Put the sret parameter into the inalloca struct if it's in memory.
1964
70
  if (Ret.isIndirect() && 
!Ret.getInReg()9
) {
1965
8
    addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
1966
8
    // On Windows, the hidden sret parameter is always returned in eax.
1967
8
    Ret.setInAllocaSRet(IsWin32StructABI);
1968
8
  }
1969
70
1970
70
  // Skip the 'this' parameter in ecx.
1971
70
  if (IsThisCall)
1972
16
    ++I;
1973
70
1974
70
  // Put arguments passed in memory into the struct.
1975
236
  for (; I != E; 
++I166
) {
1976
166
    if (isArgInAlloca(I->info))
1977
155
      addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1978
166
  }
1979
70
1980
70
  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1981
70
                                        /*isPacked=*/true),
1982
70
                  StackAlign);
1983
70
}
1984
1985
Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1986
12
                                 Address VAListAddr, QualType Ty) const {
1987
12
1988
12
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1989
12
1990
12
  // x86-32 changes the alignment of certain arguments on the stack.
1991
12
  //
1992
12
  // Just messing with TypeInfo like this works because we never pass
1993
12
  // anything indirectly.
1994
12
  TypeInfo.second = CharUnits::fromQuantity(
1995
12
                getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1996
12
1997
12
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1998
12
                          TypeInfo, CharUnits::fromQuantity(4),
1999
12
                          /*AllowHigherAlign*/ true);
2000
12
}
2001
2002
bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
2003
2.45k
    const llvm::Triple &Triple, const CodeGenOptions &Opts) {
2004
2.45k
  assert(Triple.getArch() == llvm::Triple::x86);
2005
2.45k
2006
2.45k
  switch (Opts.getStructReturnConvention()) {
2007
2.45k
  case CodeGenOptions::SRCK_Default:
2008
2.45k
    break;
2009
3
  case CodeGenOptions::SRCK_OnStack:  // -fpcc-struct-return
2010
3
    return false;
2011
3
  case CodeGenOptions::SRCK_InRegs:  // -freg-struct-return
2012
3
    return true;
2013
2.45k
  }
2014
2.45k
2015
2.45k
  if (Triple.isOSDarwin() || 
Triple.isOSIAMCU()2.27k
)
2016
176
    return true;
2017
2.27k
2018
2.27k
  switch (Triple.getOS()) {
2019
411
  case llvm::Triple::DragonFly:
2020
411
  case llvm::Triple::FreeBSD:
2021
411
  case llvm::Triple::OpenBSD:
2022
411
  case llvm::Triple::Win32:
2023
411
    return true;
2024
1.86k
  default:
2025
1.86k
    return false;
2026
2.27k
  }
2027
2.27k
}
2028
2029
void X86_32TargetCodeGenInfo::setTargetAttributes(
2030
54.1k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2031
54.1k
  if (GV->isDeclaration())
2032
33.1k
    return;
2033
21.0k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2034
17.5k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2035
2
      llvm::Function *Fn = cast<llvm::Function>(GV);
2036
2
      Fn->addFnAttr("stackrealign");
2037
2
    }
2038
17.5k
    if (FD->hasAttr<AnyX86InterruptAttr>()) {
2039
10
      llvm::Function *Fn = cast<llvm::Function>(GV);
2040
10
      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2041
10
    }
2042
17.5k
  }
2043
21.0k
}
2044
2045
bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
2046
                                               CodeGen::CodeGenFunction &CGF,
2047
0
                                               llvm::Value *Address) const {
2048
0
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
2049
0
2050
0
  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
2051
0
2052
0
  // 0-7 are the eight integer registers;  the order is different
2053
0
  //   on Darwin (for EH), but the range is the same.
2054
0
  // 8 is %eip.
2055
0
  AssignToArrayRange(Builder, Address, Four8, 0, 8);
2056
0
2057
0
  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2058
0
    // 12-16 are st(0..4).  Not sure why we stop at 4.
2059
0
    // These have size 16, which is sizeof(long double) on
2060
0
    // platforms with 8-byte alignment for that type.
2061
0
    llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2062
0
    AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2063
0
2064
0
  } else {
2065
0
    // 9 is %eflags, which doesn't get a size on Darwin for some
2066
0
    // reason.
2067
0
    Builder.CreateAlignedStore(
2068
0
        Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2069
0
                               CharUnits::One());
2070
0
2071
0
    // 11-16 are st(0..5).  Not sure why we stop at 5.
2072
0
    // These have size 12, which is sizeof(long double) on
2073
0
    // platforms with 4-byte alignment for that type.
2074
0
    llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2075
0
    AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2076
0
  }
2077
0
2078
0
  return false;
2079
0
}
2080
2081
//===----------------------------------------------------------------------===//
2082
// X86-64 ABI Implementation
2083
//===----------------------------------------------------------------------===//
2084
2085
2086
namespace {
2087
/// The AVX ABI level for X86 targets.
2088
enum class X86AVXABILevel {
2089
  None,
2090
  AVX,
2091
  AVX512
2092
};
2093
2094
/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2095
3.47k
static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2096
3.47k
  switch (AVXLevel) {
2097
2.58k
  case X86AVXABILevel::AVX512:
2098
2.58k
    return 512;
2099
678
  case X86AVXABILevel::AVX:
2100
678
    return 256;
2101
216
  case X86AVXABILevel::None:
2102
216
    return 128;
2103
0
  }
2104
0
  llvm_unreachable("Unknown AVXLevel");
2105
0
}
2106
2107
/// X86_64ABIInfo - The X86_64 ABI information.
2108
class X86_64ABIInfo : public SwiftABIInfo {
2109
  enum Class {
2110
    Integer = 0,
2111
    SSE,
2112
    SSEUp,
2113
    X87,
2114
    X87Up,
2115
    ComplexX87,
2116
    NoClass,
2117
    Memory
2118
  };
2119
2120
  /// merge - Implement the X86_64 ABI merging algorithm.
2121
  ///
2122
  /// Merge an accumulating classification \arg Accum with a field
2123
  /// classification \arg Field.
2124
  ///
2125
  /// \param Accum - The accumulating classification. This should
2126
  /// always be either NoClass or the result of a previous merge
2127
  /// call. In addition, this should never be Memory (the caller
2128
  /// should just return Memory for the aggregate).
2129
  static Class merge(Class Accum, Class Field);
2130
2131
  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2132
  ///
2133
  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2134
  /// final MEMORY or SSE classes when necessary.
2135
  ///
2136
  /// \param AggregateSize - The size of the current aggregate in
2137
  /// the classification process.
2138
  ///
2139
  /// \param Lo - The classification for the parts of the type
2140
  /// residing in the low word of the containing object.
2141
  ///
2142
  /// \param Hi - The classification for the parts of the type
2143
  /// residing in the higher words of the containing object.
2144
  ///
2145
  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2146
2147
  /// classify - Determine the x86_64 register classes in which the
2148
  /// given type T should be passed.
2149
  ///
2150
  /// \param Lo - The classification for the parts of the type
2151
  /// residing in the low word of the containing object.
2152
  ///
2153
  /// \param Hi - The classification for the parts of the type
2154
  /// residing in the high word of the containing object.
2155
  ///
2156
  /// \param OffsetBase - The bit offset of this type in the
2157
  /// containing object.  Some parameters are classified different
2158
  /// depending on whether they straddle an eightbyte boundary.
2159
  ///
2160
  /// \param isNamedArg - Whether the argument in question is a "named"
2161
  /// argument, as used in AMD64-ABI 3.5.7.
2162
  ///
2163
  /// If a word is unused its result will be NoClass; if a type should
2164
  /// be passed in Memory then at least the classification of \arg Lo
2165
  /// will be Memory.
2166
  ///
2167
  /// The \arg Lo class will be NoClass iff the argument is ignored.
2168
  ///
2169
  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2170
  /// also be ComplexX87.
2171
  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2172
                bool isNamedArg) const;
2173
2174
  llvm::Type *GetByteVectorType(QualType Ty) const;
2175
  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2176
                                 unsigned IROffset, QualType SourceTy,
2177
                                 unsigned SourceOffset) const;
2178
  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2179
                                     unsigned IROffset, QualType SourceTy,
2180
                                     unsigned SourceOffset) const;
2181
2182
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2183
  /// such that the argument will be returned in memory.
2184
  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2185
2186
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2187
  /// such that the argument will be passed in memory.
2188
  ///
2189
  /// \param freeIntRegs - The number of free integer registers remaining
2190
  /// available.
2191
  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2192
2193
  ABIArgInfo classifyReturnType(QualType RetTy) const;
2194
2195
  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2196
                                  unsigned &neededInt, unsigned &neededSSE,
2197
                                  bool isNamedArg) const;
2198
2199
  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2200
                                       unsigned &NeededSSE) const;
2201
2202
  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2203
                                           unsigned &NeededSSE) const;
2204
2205
  bool IsIllegalVectorType(QualType Ty) const;
2206
2207
  /// The 0.98 ABI revision clarified a lot of ambiguities,
2208
  /// unfortunately in ways that were not always consistent with
2209
  /// certain previous compilers.  In particular, platforms which
2210
  /// required strict binary compatibility with older versions of GCC
2211
  /// may need to exempt themselves.
2212
17
  bool honorsRevision0_98() const {
2213
17
    return !getTarget().getTriple().isOSDarwin();
2214
17
  }
2215
2216
  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2217
  /// classify it as INTEGER (for compatibility with older clang compilers).
2218
181
  bool classifyIntegerMMXAsSSE() const {
2219
181
    // Clang <= 3.8 did not do this.
2220
181
    if (getContext().getLangOpts().getClangABICompat() <=
2221
181
        LangOptions::ClangABI::Ver3_8)
2222
2
      return false;
2223
179
2224
179
    const llvm::Triple &Triple = getTarget().getTriple();
2225
179
    if (Triple.isOSDarwin() || 
Triple.getOS() == llvm::Triple::PS462
)
2226
122
      return false;
2227
57
    if (Triple.isOSFreeBSD() && 
Triple.getOSMajorVersion() >= 100
)
2228
0
      return false;
2229
57
    return true;
2230
57
  }
2231
2232
  // GCC classifies vectors of __int128 as memory.
2233
10.5k
  bool passInt128VectorsInMem() const {
2234
10.5k
    // Clang <= 9.0 did not do this.
2235
10.5k
    if (getContext().getLangOpts().getClangABICompat() <=
2236
10.5k
        LangOptions::ClangABI::Ver9)
2237
36
      return false;
2238
10.5k
2239
10.5k
    const llvm::Triple &T = getTarget().getTriple();
2240
10.5k
    return T.isOSLinux() || 
T.isOSNetBSD()9.87k
;
2241
10.5k
  }
2242
2243
  X86AVXABILevel AVXLevel;
2244
  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2245
  // 64-bit hardware.
2246
  bool Has64BitPointers;
2247
2248
public:
2249
  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2250
      SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2251
19.3k
      Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2252
19.3k
  }
2253
2254
91
  bool isPassedUsingAVXType(QualType type) const {
2255
91
    unsigned neededInt, neededSSE;
2256
91
    // The freeIntRegs argument doesn't matter here.
2257
91
    ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2258
91
                                           /*isNamedArg*/true);
2259
91
    if (info.isDirect()) {
2260
90
      llvm::Type *ty = info.getCoerceToType();
2261
90
      if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2262
2
        return (vectorTy->getBitWidth() > 128);
2263
89
    }
2264
89
    return false;
2265
89
  }
2266
2267
  void computeInfo(CGFunctionInfo &FI) const override;
2268
2269
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2270
                    QualType Ty) const override;
2271
  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2272
                      QualType Ty) const override;
2273
2274
0
  bool has64BitPointers() const {
2275
0
    return Has64BitPointers;
2276
0
  }
2277
2278
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2279
298
                                    bool asReturnValue) const override {
2280
298
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2281
298
  }
2282
0
  bool isSwiftErrorInRegister() const override {
2283
0
    return true;
2284
0
  }
2285
};
2286
2287
/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2288
class WinX86_64ABIInfo : public SwiftABIInfo {
2289
public:
2290
  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2291
      : SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2292
335
        IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2293
2294
  void computeInfo(CGFunctionInfo &FI) const override;
2295
2296
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2297
                    QualType Ty) const override;
2298
2299
369
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2300
369
    // FIXME: Assumes vectorcall is in use.
2301
369
    return isX86VectorTypeForVectorCall(getContext(), Ty);
2302
369
  }
2303
2304
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2305
406
                                         uint64_t NumMembers) const override {
2306
406
    // FIXME: Assumes vectorcall is in use.
2307
406
    return isX86VectorCallAggregateSmallEnough(NumMembers);
2308
406
  }
2309
2310
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2311
25
                                    bool asReturnValue) const override {
2312
25
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2313
25
  }
2314
2315
0
  bool isSwiftErrorInRegister() const override {
2316
0
    return true;
2317
0
  }
2318
2319
private:
2320
  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2321
                      bool IsVectorCall, bool IsRegCall) const;
2322
  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2323
                                      const ABIArgInfo &current) const;
2324
  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2325
                             bool IsVectorCall, bool IsRegCall) const;
2326
2327
  X86AVXABILevel AVXLevel;
2328
2329
  bool IsMingw64;
2330
};
2331
2332
class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2333
public:
2334
  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2335
19.3k
      : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2336
2337
91
  const X86_64ABIInfo &getABIInfo() const {
2338
91
    return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2339
91
  }
2340
2341
  /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2342
  /// the autoreleaseRV/retainRV optimization.
2343
227
  bool shouldSuppressTailCallsOfRetainAutoreleasedReturnValue() const override {
2344
227
    return true;
2345
227
  }
2346
2347
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2348
0
    return 7;
2349
0
  }
2350
2351
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2352
0
                               llvm::Value *Address) const override {
2353
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2354
0
2355
0
    // 0-15 are the 16 integer registers.
2356
0
    // 16 is %rip.
2357
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2358
0
    return false;
2359
0
  }
2360
2361
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2362
                                  StringRef Constraint,
2363
508
                                  llvm::Type* Ty) const override {
2364
508
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2365
508
  }
2366
2367
  bool isNoProtoCallVariadic(const CallArgList &args,
2368
641
                             const FunctionNoProtoType *fnType) const override {
2369
641
    // The default CC on x86-64 sets %al to the number of SSA
2370
641
    // registers used, and GCC sets this when calling an unprototyped
2371
641
    // function, so we override the default behavior.  However, don't do
2372
641
    // that when AVX types are involved: the ABI explicitly states it is
2373
641
    // undefined, and it doesn't work in practice because of how the ABI
2374
641
    // defines varargs anyway.
2375
641
    if (fnType->getCallConv() == CC_C) {
2376
641
      bool HasAVXType = false;
2377
641
      for (CallArgList::const_iterator
2378
730
             it = args.begin(), ie = args.end(); it != ie; 
++it89
) {
2379
91
        if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2380
2
          HasAVXType = true;
2381
2
          break;
2382
2
        }
2383
91
      }
2384
641
2385
641
      if (!HasAVXType)
2386
639
        return true;
2387
2
    }
2388
2
2389
2
    return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2390
2
  }
2391
2392
  llvm::Constant *
2393
84
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2394
84
    unsigned Sig = (0xeb << 0) | // jmp rel8
2395
84
                   (0x06 << 8) | //           .+0x08
2396
84
                   ('v' << 16) |
2397
84
                   ('2' << 24);
2398
84
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2399
84
  }
2400
2401
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2402
332k
                           CodeGen::CodeGenModule &CGM) const override {
2403
332k
    if (GV->isDeclaration())
2404
185k
      return;
2405
147k
    if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2406
138k
      if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2407
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
2408
1
        Fn->addFnAttr("stackrealign");
2409
1
      }
2410
138k
      if (FD->hasAttr<AnyX86InterruptAttr>()) {
2411
10
        llvm::Function *Fn = cast<llvm::Function>(GV);
2412
10
        Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2413
10
      }
2414
138k
    }
2415
147k
  }
2416
};
2417
2418
75
static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2419
75
  // If the argument does not end in .lib, automatically add the suffix.
2420
75
  // If the argument contains a space, enclose it in quotes.
2421
75
  // This matches the behavior of MSVC.
2422
75
  bool Quote = (Lib.find(" ") != StringRef::npos);
2423
75
  std::string ArgStr = Quote ? 
"\""4
:
""71
;
2424
75
  ArgStr += Lib;
2425
75
  if (!Lib.endswith_lower(".lib") && 
!Lib.endswith_lower(".a")63
)
2426
63
    ArgStr += ".lib";
2427
75
  ArgStr += Quote ? 
"\""4
:
""71
;
2428
75
  return ArgStr;
2429
75
}
2430
2431
class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2432
public:
2433
  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2434
        bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2435
        unsigned NumRegisterParameters)
2436
    : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2437
411
        Win32StructABI, NumRegisterParameters, false) {}
2438
2439
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2440
                           CodeGen::CodeGenModule &CGM) const override;
2441
2442
  void getDependentLibraryOption(llvm::StringRef Lib,
2443
31
                                 llvm::SmallString<24> &Opt) const override {
2444
31
    Opt = "/DEFAULTLIB:";
2445
31
    Opt += qualifyWindowsLibrary(Lib);
2446
31
  }
2447
2448
  void getDetectMismatchOption(llvm::StringRef Name,
2449
                               llvm::StringRef Value,
2450
2
                               llvm::SmallString<32> &Opt) const override {
2451
2
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2452
2
  }
2453
};
2454
2455
static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2456
16.4k
                                          CodeGen::CodeGenModule &CGM) {
2457
16.4k
  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2458
14.0k
2459
14.0k
    if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2460
1
      Fn->addFnAttr("stack-probe-size",
2461
1
                    llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2462
14.0k
    if (CGM.getCodeGenOpts().NoStackArgProbe)
2463
4
      Fn->addFnAttr("no-stack-arg-probe");
2464
14.0k
  }
2465
16.4k
}
2466
2467
void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2468
17.0k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2469
17.0k
  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2470
17.0k
  if (GV->isDeclaration())
2471
9.72k
    return;
2472
7.32k
  addStackProbeTargetAttributes(D, GV, CGM);
2473
7.32k
}
2474
2475
class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2476
public:
2477
  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2478
                             X86AVXABILevel AVXLevel)
2479
324
      : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT, AVXLevel)) {}
2480
2481
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2482
                           CodeGen::CodeGenModule &CGM) const override;
2483
2484
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2485
0
    return 7;
2486
0
  }
2487
2488
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2489
0
                               llvm::Value *Address) const override {
2490
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2491
0
2492
0
    // 0-15 are the 16 integer registers.
2493
0
    // 16 is %rip.
2494
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2495
0
    return false;
2496
0
  }
2497
2498
  void getDependentLibraryOption(llvm::StringRef Lib,
2499
33
                                 llvm::SmallString<24> &Opt) const override {
2500
33
    Opt = "/DEFAULTLIB:";
2501
33
    Opt += qualifyWindowsLibrary(Lib);
2502
33
  }
2503
2504
  void getDetectMismatchOption(llvm::StringRef Name,
2505
                               llvm::StringRef Value,
2506
4
                               llvm::SmallString<32> &Opt) const override {
2507
4
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2508
4
  }
2509
};
2510
2511
void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2512
18.0k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2513
18.0k
  TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2514
18.0k
  if (GV->isDeclaration())
2515
9.82k
    return;
2516
8.26k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2517
7.25k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2518
0
      llvm::Function *Fn = cast<llvm::Function>(GV);
2519
0
      Fn->addFnAttr("stackrealign");
2520
0
    }
2521
7.25k
    if (FD->hasAttr<AnyX86InterruptAttr>()) {
2522
5
      llvm::Function *Fn = cast<llvm::Function>(GV);
2523
5
      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2524
5
    }
2525
7.25k
  }
2526
8.26k
2527
8.26k
  addStackProbeTargetAttributes(D, GV, CGM);
2528
8.26k
}
2529
}
2530
2531
void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2532
13.3k
                              Class &Hi) const {
2533
13.3k
  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2534
13.3k
  //
2535
13.3k
  // (a) If one of the classes is Memory, the whole argument is passed in
2536
13.3k
  //     memory.
2537
13.3k
  //
2538
13.3k
  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2539
13.3k
  //     memory.
2540
13.3k
  //
2541
13.3k
  // (c) If the size of the aggregate exceeds two eightbytes and the first
2542
13.3k
  //     eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2543
13.3k
  //     argument is passed in memory. NOTE: This is necessary to keep the
2544
13.3k
  //     ABI working for processors that don't support the __m256 type.
2545
13.3k
  //
2546
13.3k
  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2547
13.3k
  //
2548
13.3k
  // Some of these are enforced by the merging logic.  Others can arise
2549
13.3k
  // only with unions; for example:
2550
13.3k
  //   union { _Complex double; unsigned; }
2551
13.3k
  //
2552
13.3k
  // Note that clauses (b) and (c) were added in 0.98.
2553
13.3k
  //
2554
13.3k
  if (Hi == Memory)
2555
0
    Lo = Memory;
2556
13.3k
  if (Hi == X87Up && 
Lo != X87354
&&
honorsRevision0_98()17
)
2557
15
    Lo = Memory;
2558
13.3k
  if (AggregateSize > 128 && 
(303
Lo != SSE303
||
Hi != SSEUp21
))
2559
282
    Lo = Memory;
2560
13.3k
  if (Hi == SSEUp && 
Lo != SSE30
)
2561
1
    Hi = SSE;
2562
13.3k
}
2563
2564
18.9k
X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2565
18.9k
  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2566
18.9k
  // classified recursively so that always two fields are
2567
18.9k
  // considered. The resulting class is calculated according to
2568
18.9k
  // the classes of the fields in the eightbyte:
2569
18.9k
  //
2570
18.9k
  // (a) If both classes are equal, this is the resulting class.
2571
18.9k
  //
2572
18.9k
  // (b) If one of the classes is NO_CLASS, the resulting class is
2573
18.9k
  // the other class.
2574
18.9k
  //
2575
18.9k
  // (c) If one of the classes is MEMORY, the result is the MEMORY
2576
18.9k
  // class.
2577
18.9k
  //
2578
18.9k
  // (d) If one of the classes is INTEGER, the result is the
2579
18.9k
  // INTEGER.
2580
18.9k
  //
2581
18.9k
  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2582
18.9k
  // MEMORY is used as class.
2583
18.9k
  //
2584
18.9k
  // (f) Otherwise class SSE is used.
2585
18.9k
2586
18.9k
  // Accum should never be memory (we should have returned) or
2587
18.9k
  // ComplexX87 (because this cannot be passed in a structure).
2588
18.9k
  assert((Accum != Memory && Accum != ComplexX87) &&
2589
18.9k
         "Invalid accumulated classification during merge.");
2590
18.9k
  if (Accum == Field || 
Field == NoClass10.1k
)
2591
10.3k
    return Accum;
2592
8.64k
  if (Field == Memory)
2593
13
    return Memory;
2594
8.63k
  if (Accum == NoClass)
2595
8.53k
    return Field;
2596
100
  if (Accum == Integer || 
Field == Integer72
)
2597
97
    return Integer;
2598
3
  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2599
3
      Accum == X87 || 
Accum == X87Up0
)
2600
3
    return Memory;
2601
0
  return SSE;
2602
0
}
2603
2604
void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2605
378k
                             Class &Lo, Class &Hi, bool isNamedArg) const {
2606
378k
  // FIXME: This code can be simplified by introducing a simple value class for
2607
378k
  // Class pairs with appropriate constructor methods for the various
2608
378k
  // situations.
2609
378k
2610
378k
  // FIXME: Some of the split computations are wrong; unaligned vectors
2611
378k
  // shouldn't be passed in registers for example, so there is no chance they
2612
378k
  // can straddle an eightbyte. Verify & simplify.
2613
378k
2614
378k
  Lo = Hi = NoClass;
2615
378k
2616
378k
  Class &Current = OffsetBase < 64 ? 
Lo376k
:
Hi1.62k
;
2617
378k
  Current = Memory;
2618
378k
2619
378k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2620
141k
    BuiltinType::Kind k = BT->getKind();
2621
141k
2622
141k
    if (k == BuiltinType::Void) {
2623
53.7k
      Current = NoClass;
2624
88.0k
    } else if (k == BuiltinType::Int128 || 
k == BuiltinType::UInt12888.0k
) {
2625
26
      Lo = Integer;
2626
26
      Hi = Integer;
2627
88.0k
    } else if (k >= BuiltinType::Bool && 
k <= BuiltinType::LongLong88.0k
) {
2628
83.4k
      Current = Integer;
2629
83.4k
    } else 
if (4.59k
k == BuiltinType::Float4.59k
||
k == BuiltinType::Double2.75k
) {
2630
3.44k
      Current = SSE;
2631
3.44k
    } else 
if (1.15k
k == BuiltinType::LongDouble1.15k
) {
2632
937
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2633
937
      if (LDF == &llvm::APFloat::IEEEquad()) {
2634
15
        Lo = SSE;
2635
15
        Hi = SSEUp;
2636
922
      } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2637
900
        Lo = X87;
2638
900
        Hi = X87Up;
2639
900
      } else 
if (22
LDF == &llvm::APFloat::IEEEdouble()22
) {
2640
22
        Current = SSE;
2641
22
      } else
2642
22
        
llvm_unreachable0
("unexpected long double representation!");
2643
937
    }
2644
141k
    // FIXME: _Decimal32 and _Decimal64 are SSE.
2645
141k
    // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2646
141k
    return;
2647
236k
  }
2648
236k
2649
236k
  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2650
890
    // Classify the underlying integer type.
2651
890
    classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2652
890
    return;
2653
890
  }
2654
235k
2655
235k
  if (Ty->hasPointerRepresentation()) {
2656
215k
    Current = Integer;
2657
215k
    return;
2658
215k
  }
2659
19.8k
2660
19.8k
  if (Ty->isMemberPointerType()) {
2661
111
    if (Ty->isMemberFunctionPointerType()) {
2662
70
      if (Has64BitPointers) {
2663
62
        // If Has64BitPointers, this is an {i64, i64}, so classify both
2664
62
        // Lo and Hi now.
2665
62
        Lo = Hi = Integer;
2666
62
      } else {
2667
8
        // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2668
8
        // straddles an eightbyte boundary, Hi should be classified as well.
2669
8
        uint64_t EB_FuncPtr = (OffsetBase) / 64;
2670
8
        uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2671
8
        if (EB_FuncPtr != EB_ThisAdj) {
2672
2
          Lo = Hi = Integer;
2673
6
        } else {
2674
6
          Current = Integer;
2675
6
        }
2676
8
      }
2677
70
    } else {
2678
41
      Current = Integer;
2679
41
    }
2680
111
    return;
2681
111
  }
2682
19.7k
2683
19.7k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2684
5.64k
    uint64_t Size = getContext().getTypeSize(VT);
2685
5.64k
    if (Size == 1 || Size == 8 || 
Size == 165.64k
||
Size == 325.64k
) {
2686
5
      // gcc passes the following as integer:
2687
5
      // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2688
5
      // 2 bytes - <2 x char>, <1 x short>
2689
5
      // 1 byte  - <1 x char>
2690
5
      Current = Integer;
2691
5
2692
5
      // If this type crosses an eightbyte boundary, it should be
2693
5
      // split.
2694
5
      uint64_t EB_Lo = (OffsetBase) / 64;
2695
5
      uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2696
5
      if (EB_Lo != EB_Hi)
2697
0
        Hi = Lo;
2698
5.63k
    } else if (Size == 64) {
2699
181
      QualType ElementType = VT->getElementType();
2700
181
2701
181
      // gcc passes <1 x double> in memory. :(
2702
181
      if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2703
0
        return;
2704
181
2705
181
      // gcc passes <1 x long long> as SSE but clang used to unconditionally
2706
181
      // pass them as integer.  For platforms where clang is the de facto
2707
181
      // platform compiler, we must continue to use integer.
2708
181
      if (!classifyIntegerMMXAsSSE() &&
2709
181
          
(124
ElementType->isSpecificBuiltinType(BuiltinType::LongLong)124
||
2710
124
           
ElementType->isSpecificBuiltinType(BuiltinType::ULongLong)45
||
2711
124
           
ElementType->isSpecificBuiltinType(BuiltinType::Long)45
||
2712
124
           
ElementType->isSpecificBuiltinType(BuiltinType::ULong)45
))
2713
79
        Current = Integer;
2714
102
      else
2715
102
        Current = SSE;
2716
181
2717
181
      // If this type crosses an eightbyte boundary, it should be
2718
181
      // split.
2719
181
      if (OffsetBase && 
OffsetBase != 640
)
2720
0
        Hi = Lo;
2721
5.45k
    } else if (Size == 128 ||
2722
5.45k
               
(3.29k
isNamedArg3.29k
&&
Size <= getNativeVectorSizeForAVXABI(AVXLevel)3.27k
)) {
2723
5.28k
      QualType ElementType = VT->getElementType();
2724
5.28k
2725
5.28k
      // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :(
2726
5.28k
      if (passInt128VectorsInMem() && 
Size != 128353
&&
2727
5.28k
          
(151
ElementType->isSpecificBuiltinType(BuiltinType::Int128)151
||
2728
151
           ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
2729
6
        return;
2730
5.27k
2731
5.27k
      // Arguments of 256-bits are split into four eightbyte chunks. The
2732
5.27k
      // least significant one belongs to class SSE and all the others to class
2733
5.27k
      // SSEUP. The original Lo and Hi design considers that types can't be
2734
5.27k
      // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2735
5.27k
      // This design isn't correct for 256-bits, but since there're no cases
2736
5.27k
      // where the upper parts would need to be inspected, avoid adding
2737
5.27k
      // complexity and just consider Hi to match the 64-256 part.
2738
5.27k
      //
2739
5.27k
      // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2740
5.27k
      // registers if they are "named", i.e. not part of the "..." of a
2741
5.27k
      // variadic function.
2742
5.27k
      //
2743
5.27k
      // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2744
5.27k
      // split into eight eightbyte chunks, one SSE and seven SSEUP.
2745
5.27k
      Lo = SSE;
2746
5.27k
      Hi = SSEUp;
2747
5.27k
    }
2748
5.64k
    
return5.63k
;
2749
14.1k
  }
2750
14.1k
2751
14.1k
  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2752
373
    QualType ET = getContext().getCanonicalType(CT->getElementType());
2753
373
2754
373
    uint64_t Size = getContext().getTypeSize(Ty);
2755
373
    if (ET->isIntegralOrEnumerationType()) {
2756
30
      if (Size <= 64)
2757
28
        Current = Integer;
2758
2
      else if (Size <= 128)
2759
2
        Lo = Hi = Integer;
2760
343
    } else if (ET == getContext().FloatTy) {
2761
127
      Current = SSE;
2762
216
    } else if (ET == getContext().DoubleTy) {
2763
109
      Lo = Hi = SSE;
2764
109
    } else 
if (107
ET == getContext().LongDoubleTy107
) {
2765
107
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2766
107
      if (LDF == &llvm::APFloat::IEEEquad())
2767
8
        Current = Memory;
2768
99
      else if (LDF == &llvm::APFloat::x87DoubleExtended())
2769
91
        Current = ComplexX87;
2770
8
      else if (LDF == &llvm::APFloat::IEEEdouble())
2771
8
        Lo = Hi = SSE;
2772
8
      else
2773
8
        
llvm_unreachable0
("unexpected long double representation!");
2774
107
    }
2775
373
2776
373
    // If this complex type crosses an eightbyte boundary then it
2777
373
    // should be split.
2778
373
    uint64_t EB_Real = (OffsetBase) / 64;
2779
373
    uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2780
373
    if (Hi == NoClass && 
EB_Real != EB_Imag254
)
2781
102
      Hi = Lo;
2782
373
2783
373
    return;
2784
13.7k
  }
2785
13.7k
2786
13.7k
  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2787
54
    // Arrays are treated like structures.
2788
54
2789
54
    uint64_t Size = getContext().getTypeSize(Ty);
2790
54
2791
54
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2792
54
    // than eight eightbytes, ..., it has class MEMORY.
2793
54
    if (Size > 512)
2794
0
      return;
2795
54
2796
54
    // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2797
54
    // fields, it has class MEMORY.
2798
54
    //
2799
54
    // Only need to check alignment of array base.
2800
54
    if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2801
0
      return;
2802
54
2803
54
    // Otherwise implement simplified merge. We could be smarter about
2804
54
    // this, but it isn't worth it and would be harder to verify.
2805
54
    Current = NoClass;
2806
54
    uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2807
54
    uint64_t ArraySize = AT->getSize().getZExtValue();
2808
54
2809
54
    // The only case a 256-bit wide vector could be used is when the array
2810
54
    // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2811
54
    // to work for sizes wider than 128, early check and fallback to memory.
2812
54
    //
2813
54
    if (Size > 128 &&
2814
54
        
(15
Size != EltSize15
||
Size > getNativeVectorSizeForAVXABI(AVXLevel)4
))
2815
11
      return;
2816
43
2817
196
    
for (uint64_t i=0, Offset=OffsetBase; 43
i<ArraySize;
++i, Offset += EltSize153
) {
2818
153
      Class FieldLo, FieldHi;
2819
153
      classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2820
153
      Lo = merge(Lo, FieldLo);
2821
153
      Hi = merge(Hi, FieldHi);
2822
153
      if (Lo == Memory || Hi == Memory)
2823
0
        break;
2824
153
    }
2825
43
2826
43
    postMerge(Size, Lo, Hi);
2827
43
    assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2828
43
    return;
2829
43
  }
2830
13.6k
2831
13.6k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2832
13.6k
    uint64_t Size = getContext().getTypeSize(Ty);
2833
13.6k
2834
13.6k
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2835
13.6k
    // than eight eightbytes, ..., it has class MEMORY.
2836
13.6k
    if (Size > 512)
2837
108
      return;
2838
13.5k
2839
13.5k
    // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2840
13.5k
    // copy constructor or a non-trivial destructor, it is passed by invisible
2841
13.5k
    // reference.
2842
13.5k
    if (getRecordArgABI(RT, getCXXABI()))
2843
307
      return;
2844
13.2k
2845
13.2k
    const RecordDecl *RD = RT->getDecl();
2846
13.2k
2847
13.2k
    // Assume variable sized types are passed in memory.
2848
13.2k
    if (RD->hasFlexibleArrayMember())
2849
0
      return;
2850
13.2k
2851
13.2k
    const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2852
13.2k
2853
13.2k
    // Reset Lo class, this will be recomputed.
2854
13.2k
    Current = NoClass;
2855
13.2k
2856
13.2k
    // If this is a C++ record, classify the bases first.
2857
13.2k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2858
12.7k
      for (const auto &I : CXXRD->bases()) {
2859
1.10k
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2860
1.10k
               "Unexpected base class!");
2861
1.10k
        const auto *Base =
2862
1.10k
            cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
2863
1.10k
2864
1.10k
        // Classify this field.
2865
1.10k
        //
2866
1.10k
        // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2867
1.10k
        // single eightbyte, each is classified separately. Each eightbyte gets
2868
1.10k
        // initialized to class NO_CLASS.
2869
1.10k
        Class FieldLo, FieldHi;
2870
1.10k
        uint64_t Offset =
2871
1.10k
          OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2872
1.10k
        classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2873
1.10k
        Lo = merge(Lo, FieldLo);
2874
1.10k
        Hi = merge(Hi, FieldHi);
2875
1.10k
        if (Lo == Memory || 
Hi == Memory1.10k
) {
2876
6
          postMerge(Size, Lo, Hi);
2877
6
          return;
2878
6
        }
2879
1.10k
      }
2880
12.7k
    }
2881
13.2k
2882
13.2k
    // Classify the fields one at a time, merging the results.
2883
13.2k
    unsigned idx = 0;
2884
13.2k
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2885
21.4k
           i != e; 
++i, ++idx8.23k
) {
2886
8.54k
      uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2887
8.54k
      bool BitField = i->isBitField();
2888
8.54k
2889
8.54k
      // Ignore padding bit-fields.
2890
8.54k
      if (BitField && 
i->isUnnamedBitfield()42
)
2891
12
        continue;
2892
8.52k
2893
8.52k
      // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2894
8.52k
      // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2895
8.52k
      //
2896
8.52k
      // The only case a 256-bit wide vector could be used is when the struct
2897
8.52k
      // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2898
8.52k
      // to work for sizes wider than 128, early check and fallback to memory.
2899
8.52k
      //
2900
8.52k
      if (Size > 128 && 
(297
Size != getContext().getTypeSize(i->getType())297
||
2901
297
                         
Size > getNativeVectorSizeForAVXABI(AVXLevel)74
)) {
2902
271
        Lo = Memory;
2903
271
        postMerge(Size, Lo, Hi);
2904
271
        return;
2905
271
      }
2906
8.25k
      // Note, skip this test for bit-fields, see below.
2907
8.25k
      if (!BitField && 
Offset % getContext().getTypeAlign(i->getType())8.22k
) {
2908
20
        Lo = Memory;
2909
20
        postMerge(Size, Lo, Hi);
2910
20
        return;
2911
20
      }
2912
8.23k
2913
8.23k
      // Classify this field.
2914
8.23k
      //
2915
8.23k
      // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2916
8.23k
      // exceeds a single eightbyte, each is classified
2917
8.23k
      // separately. Each eightbyte gets initialized to class
2918
8.23k
      // NO_CLASS.
2919
8.23k
      Class FieldLo, FieldHi;
2920
8.23k
2921
8.23k
      // Bit-fields require special handling, they do not force the
2922
8.23k
      // structure to be passed in memory even if unaligned, and
2923
8.23k
      // therefore they can straddle an eightbyte.
2924
8.23k
      if (BitField) {
2925
30
        assert(!i->isUnnamedBitfield());
2926
30
        uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2927
30
        uint64_t Size = i->getBitWidthValue(getContext());
2928
30
2929
30
        uint64_t EB_Lo = Offset / 64;
2930
30
        uint64_t EB_Hi = (Offset + Size - 1) / 64;
2931
30
2932
30
        if (EB_Lo) {
2933
0
          assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2934
0
          FieldLo = NoClass;
2935
0
          FieldHi = Integer;
2936
30
        } else {
2937
30
          FieldLo = Integer;
2938
30
          FieldHi = EB_Hi ? 
Integer0
: NoClass;
2939
30
        }
2940
30
      } else
2941
8.20k
        classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2942
8.23k
      Lo = merge(Lo, FieldLo);
2943
8.23k
      Hi = merge(Hi, FieldHi);
2944
8.23k
      if (Lo == Memory || 
Hi == Memory8.22k
)
2945
10
        break;
2946
8.23k
    }
2947
13.2k
2948
13.2k
    postMerge(Size, Lo, Hi);
2949
12.9k
  }
2950
13.6k
}
2951
2952
342
ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2953
342
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2954
342
  // place naturally.
2955
342
  if (!isAggregateTypeForABI(Ty)) {
2956
151
    // Treat an enum type as its underlying type.
2957
151
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2958
0
      Ty = EnumTy->getDecl()->getIntegerType();
2959
151
2960
151
    return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)0
2961
151
                                          : ABIArgInfo::getDirect());
2962
151
  }
2963
191
2964
191
  return getNaturalAlignIndirect(Ty);
2965
191
}
2966
2967
2.56k
bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2968
2.56k
  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2969
126
    uint64_t Size = getContext().getTypeSize(VecTy);
2970
126
    unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2971
126
    if (Size <= 64 || 
Size > LargestVector120
)
2972
108
      return true;
2973
18
    QualType EltTy = VecTy->getElementType();
2974
18
    if (passInt128VectorsInMem() &&
2975
18
        
(6
EltTy->isSpecificBuiltinType(BuiltinType::Int128)6
||
2976
6
         EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
2977
6
      return true;
2978
2.45k
  }
2979
2.45k
2980
2.45k
  return false;
2981
2.45k
}
2982
2983
ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2984
3.19k
                                            unsigned freeIntRegs) const {
2985
3.19k
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2986
3.19k
  // place naturally.
2987
3.19k
  //
2988
3.19k
  // This assumption is optimistic, as there could be free registers available
2989
3.19k
  // when we need to pass this argument in memory, and LLVM could try to pass
2990
3.19k
  // the argument in the free register. This does not seem to happen currently,
2991
3.19k
  // but this code would be much safer if we could mark the argument with
2992
3.19k
  // 'onstack'. See PR12193.
2993
3.19k
  if (!isAggregateTypeForABI(Ty) && 
!IsIllegalVectorType(Ty)2.56k
) {
2994
2.45k
    // Treat an enum type as its underlying type.
2995
2.45k
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2996
0
      Ty = EnumTy->getDecl()->getIntegerType();
2997
2.45k
2998
2.45k
    return (Ty->isPromotableIntegerType() ? 
ABIArgInfo::getExtend(Ty)286
2999
2.45k
                                          : 
ABIArgInfo::getDirect()2.16k
);
3000
2.45k
  }
3001
743
3002
743
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
3003
317
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3004
426
3005
426
  // Compute the byval alignment. We specify the alignment of the byval in all
3006
426
  // cases so that the mid-level optimizer knows the alignment of the byval.
3007
426
  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
3008
426
3009
426
  // Attempt to avoid passing indirect results using byval when possible. This
3010
426
  // is important for good codegen.
3011
426
  //
3012
426
  // We do this by coercing the value into a scalar type which the backend can
3013
426
  // handle naturally (i.e., without using byval).
3014
426
  //
3015
426
  // For simplicity, we currently only do this when we have exhausted all of the
3016
426
  // free integer registers. Doing this when there are free integer registers
3017
426
  // would require more care, as we would have to ensure that the coerced value
3018
426
  // did not claim the unused register. That would require either reording the
3019
426
  // arguments to the function (so that any subsequent inreg values came first),
3020
426
  // or only doing this optimization when there were no following arguments that
3021
426
  // might be inreg.
3022
426
  //
3023
426
  // We currently expect it to be rare (particularly in well written code) for
3024
426
  // arguments to be passed on the stack when there are still free integer
3025
426
  // registers available (this would typically imply large structs being passed
3026
426
  // by value), so this seems like a fair tradeoff for now.
3027
426
  //
3028
426
  // We can revisit this if the backend grows support for 'onstack' parameter
3029
426
  // attributes. See PR12193.
3030
426
  if (freeIntRegs == 0) {
3031
28
    uint64_t Size = getContext().getTypeSize(Ty);
3032
28
3033
28
    // If this type fits in an eightbyte, coerce it into the matching integral
3034
28
    // type, which will end up on the stack (with alignment 8).
3035
28
    if (Align == 8 && 
Size <= 6418
)
3036
4
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
3037
4
                                                          Size));
3038
422
  }
3039
422
3040
422
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
3041
422
}
3042
3043
/// The ABI specifies that a value should be passed in a full vector XMM/YMM
3044
/// register. Pick an LLVM IR type that will be passed as a vector register.
3045
5.29k
llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
3046
5.29k
  // Wrapper structs/arrays that only contain vectors are passed just like
3047
5.29k
  // vectors; strip them off if present.
3048
5.29k
  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
3049
25
    Ty = QualType(InnerTy, 0);
3050
5.29k
3051
5.29k
  llvm::Type *IRType = CGT.ConvertType(Ty);
3052
5.29k
  if (isa<llvm::VectorType>(IRType)) {
3053
5.27k
    // Don't pass vXi128 vectors in their native type, the backend can't
3054
5.27k
    // legalize them.
3055
5.27k
    if (passInt128VectorsInMem() &&
3056
5.27k
        
IRType->getVectorElementType()->isIntegerTy(128)347
) {
3057
6
      // Use a vXi64 vector.
3058
6
      uint64_t Size = getContext().getTypeSize(Ty);
3059
6
      return llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()),
3060
6
                                   Size / 64);
3061
6
    }
3062
5.27k
3063
5.27k
    return IRType;
3064
5.27k
  }
3065
15
3066
15
  if (IRType->getTypeID() == llvm::Type::FP128TyID)
3067
15
    return IRType;
3068
0
3069
0
  // We couldn't find the preferred IR vector type for 'Ty'.
3070
0
  uint64_t Size = getContext().getTypeSize(Ty);
3071
0
  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
3072
0
3073
0
3074
0
  // Return a LLVM IR vector type based on the size of 'Ty'.
3075
0
  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
3076
0
                               Size / 64);
3077
0
}
3078
3079
/// BitsContainNoUserData - Return true if the specified [start,end) bit range
3080
/// is known to either be off the end of the specified type or being in
3081
/// alignment padding.  The user type specified is known to be at most 128 bits
3082
/// in size, and have passed through X86_64ABIInfo::classify with a successful
3083
/// classification that put one of the two halves in the INTEGER class.
3084
///
3085
/// It is conservatively correct to return false.
3086
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
3087
73.0k
                                  unsigned EndBit, ASTContext &Context) {
3088
73.0k
  // If the bytes being queried are off the end of the type, there is no user
3089
73.0k
  // data hiding here.  This handles analysis of builtins, vectors and other
3090
73.0k
  // types that don't contain interesting padding.
3091
73.0k
  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3092
73.0k
  if (TySize <= StartBit)
3093
63.8k
    return true;
3094
9.24k
3095
9.24k
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3096
32
    unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3097
32
    unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3098
32
3099
32
    // Check each element to see if the element overlaps with the queried range.
3100
89
    for (unsigned i = 0; i != NumElts; 
++i57
) {
3101
86
      // If the element is after the span we care about, then we're done..
3102
86
      unsigned EltOffset = i*EltSize;
3103
86
      if (EltOffset >= EndBit) 
break0
;
3104
86
3105
86
      unsigned EltStart = EltOffset < StartBit ? 
StartBit-EltOffset64
:
022
;
3106
86
      if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3107
86
                                 EndBit-EltOffset, Context))
3108
29
        return false;
3109
86
    }
3110
32
    // If it overlaps no elements, then it is safe to process as padding.
3111
32
    
return true3
;
3112
9.21k
  }
3113
9.21k
3114
9.21k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3115
1.28k
    const RecordDecl *RD = RT->getDecl();
3116
1.28k
    const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3117
1.28k
3118
1.28k
    // If this is a C++ record, check the bases first.
3119
1.28k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3120
1.00k
      for (const auto &I : CXXRD->bases()) {
3121
29
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3122
29
               "Unexpected base class!");
3123
29
        const auto *Base =
3124
29
            cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
3125
29
3126
29
        // If the base is after the span we care about, ignore it.
3127
29
        unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3128
29
        if (BaseOffset >= EndBit) 
continue0
;
3129
29
3130
29
        unsigned BaseStart = BaseOffset < StartBit ? 
StartBit-BaseOffset26
:
03
;
3131
29
        if (!BitsContainNoUserData(I.getType(), BaseStart,
3132
29
                                   EndBit-BaseOffset, Context))
3133
24
          return false;
3134
29
      }
3135
1.00k
    }
3136
1.28k
3137
1.28k
    // Verify that no field has data that overlaps the region of interest.  Yes
3138
1.28k
    // this could be sped up a lot by being smarter about queried fields,
3139
1.28k
    // however we're only looking at structs up to 16 bytes, so we don't care
3140
1.28k
    // much.
3141
1.28k
    unsigned idx = 0;
3142
1.25k
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3143
2.85k
         i != e; 
++i, ++idx1.59k
) {
3144
2.55k
      unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3145
2.55k
3146
2.55k
      // If we found a field after the region we care about, then we're done.
3147
2.55k
      if (FieldOffset >= EndBit) 
break139
;
3148
2.41k
3149
2.41k
      unsigned FieldStart = FieldOffset < StartBit ? 
StartBit-FieldOffset1.84k
:
0567
;
3150
2.41k
      if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3151
2.41k
                                 Context))
3152
817
        return false;
3153
2.41k
    }
3154
1.25k
3155
1.25k
    // If nothing in this record overlapped the area of interest, then we're
3156
1.25k
    // clean.
3157
1.25k
    
return true442
;
3158
7.93k
  }
3159
7.93k
3160
7.93k
  return false;
3161
7.93k
}
3162
3163
/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3164
/// float member at the specified offset.  For example, {int,{float}} has a
3165
/// float at offset 4.  It is conservatively correct for this routine to return
3166
/// false.
3167
static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3168
8.86k
                                  const llvm::DataLayout &TD) {
3169
8.86k
  // Base case if we find a float.
3170
8.86k
  if (IROffset == 0 && 
IRType->isFloatTy()8.31k
)
3171
546
    return true;
3172
8.31k
3173
8.31k
  // If this is a struct, recurse into the field at the specified offset.
3174
8.31k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3175
1.04k
    const llvm::StructLayout *SL = TD.getStructLayout(STy);
3176
1.04k
    unsigned Elt = SL->getElementContainingOffset(IROffset);
3177
1.04k
    IROffset -= SL->getElementOffset(Elt);
3178
1.04k
    return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3179
1.04k
  }
3180
7.27k
3181
7.27k
  // If this is an array, recurse into the field at the specified offset.
3182
7.27k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3183
17
    llvm::Type *EltTy = ATy->getElementType();
3184
17
    unsigned EltSize = TD.getTypeAllocSize(EltTy);
3185
17
    IROffset -= IROffset/EltSize*EltSize;
3186
17
    return ContainsFloatAtOffset(EltTy, IROffset, TD);
3187
17
  }
3188
7.25k
3189
7.25k
  return false;
3190
7.25k
}
3191
3192
3193
/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3194
/// low 8 bytes of an XMM register, corresponding to the SSE class.
3195
llvm::Type *X86_64ABIInfo::
3196
GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3197
8.98k
                   QualType SourceTy, unsigned SourceOffset) const {
3198
8.98k
  // The only three choices we have are either double, <2 x float>, or float. We
3199
8.98k
  // pass as float if the last 4 bytes is just padding.  This happens for
3200
8.98k
  // structs that contain 3 floats.
3201
8.98k
  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3202
8.98k
                            SourceOffset*8+64, getContext()))
3203
1.45k
    return llvm::Type::getFloatTy(getVMContext());
3204
7.52k
3205
7.52k
  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3206
7.52k
  // offset+0 and offset+4.  Walk the LLVM IR type to find out if this is the
3207
7.52k
  // case.
3208
7.52k
  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3209
7.52k
      
ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())273
)
3210
273
    return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3211
7.25k
3212
7.25k
  return llvm::Type::getDoubleTy(getVMContext());
3213
7.25k
}
3214
3215
3216
/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3217
/// an 8-byte GPR.  This means that we either have a scalar or we are talking
3218
/// about the high or low part of an up-to-16-byte struct.  This routine picks
3219
/// the best LLVM IR type to represent this, which may be i64 or may be anything
3220
/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3221
/// etc).
3222
///
3223
/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3224
/// the source type.  IROffset is an offset in bytes into the LLVM IR type that
3225
/// the 8-byte value references.  PrefType may be null.
3226
///
3227
/// SourceTy is the source-level type for the entire argument.  SourceOffset is
3228
/// an offset into this that we're processing (which is always either 0 or 8).
3229
///
3230
llvm::Type *X86_64ABIInfo::
3231
GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3232
306k
                       QualType SourceTy, unsigned SourceOffset) const {
3233
306k
  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3234
306k
  // returning an 8-byte unit starting with it.  See if we can safely use it.
3235
306k
  if (IROffset == 0) {
3236
304k
    // Pointers and int64's always fill the 8-byte unit.
3237
304k
    if ((isa<llvm::PointerType>(IRType) && 
Has64BitPointers215k
) ||
3238
304k
        
IRType->isIntegerTy(64)89.1k
)
3239
234k
      return IRType;
3240
70.7k
3241
70.7k
    // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3242
70.7k
    // goodness in the source type is just tail padding.  This is allowed to
3243
70.7k
    // kick in for struct {double,int} on the int, but not on
3244
70.7k
    // struct{double,int,int} because we wouldn't return the second int.  We
3245
70.7k
    // have to do this analysis on the source type because we can't depend on
3246
70.7k
    // unions being lowered a specific way etc.
3247
70.7k
    if (IRType->isIntegerTy(8) || 
IRType->isIntegerTy(16)67.2k
||
3248
70.7k
        
IRType->isIntegerTy(32)66.5k
||
3249
70.7k
        
(9.23k
isa<llvm::PointerType>(IRType)9.23k
&&
!Has64BitPointers90
)) {
3250
61.5k
      unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 
3290
:
3251
61.5k
          
cast<llvm::IntegerType>(IRType)->getBitWidth()61.4k
;
3252
61.5k
3253
61.5k
      if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3254
61.5k
                                SourceOffset*8+64, getContext()))
3255
61.1k
        return IRType;
3256
10.9k
    }
3257
70.7k
  }
3258
10.9k
3259
10.9k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3260
7.30k
    // If this is a struct, recurse into the field at the specified offset.
3261
7.30k
    const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3262
7.30k
    if (IROffset < SL->getSizeInBytes()) {
3263
7.30k
      unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3264
7.30k
      IROffset -= SL->getElementOffset(FieldIdx);
3265
7.30k
3266
7.30k
      return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3267
7.30k
                                    SourceTy, SourceOffset);
3268
7.30k
    }
3269
3.62k
  }
3270
3.62k
3271
3.62k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3272
52
    llvm::Type *EltTy = ATy->getElementType();
3273
52
    unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3274
52
    unsigned EltOffset = IROffset/EltSize*EltSize;
3275
52
    return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3276
52
                                  SourceOffset);
3277
52
  }
3278
3.57k
3279
3.57k
  // Okay, we don't have any better idea of what to pass, so we pass this in an
3280
3.57k
  // integer register that isn't too big to fit the rest of the struct.
3281
3.57k
  unsigned TySizeInBytes =
3282
3.57k
    (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3283
3.57k
3284
3.57k
  assert(TySizeInBytes != SourceOffset && "Empty field?");
3285
3.57k
3286
3.57k
  // It is always safe to classify this as an integer type up to i64 that
3287
3.57k
  // isn't larger than the structure.
3288
3.57k
  return llvm::IntegerType::get(getVMContext(),
3289
3.57k
                                std::min(TySizeInBytes-SourceOffset, 8U)*8);
3290
3.57k
}
3291
3292
3293
/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3294
/// be used as elements of a two register pair to pass or return, return a
3295
/// first class aggregate to represent them.  For example, if the low part of
3296
/// a by-value argument should be passed as i32* and the high part as float,
3297
/// return {i32*, float}.
3298
static llvm::Type *
3299
GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3300
1.57k
                           const llvm::DataLayout &TD) {
3301
1.57k
  // In order to correctly satisfy the ABI, we need to the high part to start
3302
1.57k
  // at offset 8.  If the high and low parts we inferred are both 4-byte types
3303
1.57k
  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3304
1.57k
  // the second element at offset 8.  Check for this:
3305
1.57k
  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3306
1.57k
  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3307
1.57k
  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3308
1.57k
  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3309
1.57k
3310
1.57k
  // To handle this, we have to increase the size of the low part so that the
3311
1.57k
  // second element will start at an 8 byte offset.  We can't increase the size
3312
1.57k
  // of the second element because it might make us access off the end of the
3313
1.57k
  // struct.
3314
1.57k
  if (HiStart != 8) {
3315
5
    // There are usually two sorts of types the ABI generation code can produce
3316
5
    // for the low part of a pair that aren't 8 bytes in size: float or
3317
5
    // i8/i16/i32.  This can also include pointers when they are 32-bit (X32 and
3318
5
    // NaCl).
3319
5
    // Promote these to a larger type.
3320
5
    if (Lo->isFloatTy())
3321
0
      Lo = llvm::Type::getDoubleTy(Lo->getContext());
3322
5
    else {
3323
5
      assert((Lo->isIntegerTy() || Lo->isPointerTy())
3324
5
             && "Invalid/unknown lo type");
3325
5
      Lo = llvm::Type::getInt64Ty(Lo->getContext());
3326
5
    }
3327
5
  }
3328
1.57k
3329
1.57k
  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3330
1.57k
3331
1.57k
  // Verify that the second element is at an 8-byte offset.
3332
1.57k
  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3333
1.57k
         "Invalid x86-64 argument pair!");
3334
1.57k
  return Result;
3335
1.57k
}
3336
3337
ABIArgInfo X86_64ABIInfo::
3338
132k
classifyReturnType(QualType RetTy) const {
3339
132k
  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3340
132k
  // classification algorithm.
3341
132k
  X86_64ABIInfo::Class Lo, Hi;
3342
132k
  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3343
132k
3344
132k
  // Check some invariants.
3345
132k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3346
132k
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3347
132k
3348
132k
  llvm::Type *ResType = nullptr;
3349
132k
  switch (Lo) {
3350
54.0k
  case NoClass:
3351
54.0k
    if (Hi == NoClass)
3352
54.0k
      return ABIArgInfo::getIgnore();
3353
1
    // If the low part is just padding, it takes no register, leave ResType
3354
1
    // null.
3355
1
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3356
1
           "Unknown missing lo part");
3357
1
    break;
3358
1
3359
1
  case SSEUp:
3360
0
  case X87Up:
3361
0
    llvm_unreachable("Invalid classification for lo word.");
3362
0
3363
0
    // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3364
0
    // hidden argument.
3365
341
  case Memory:
3366
341
    return getIndirectReturnResult(RetTy);
3367
0
3368
0
    // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3369
0
    // available register of the sequence %rax, %rdx is used.
3370
74.5k
  case Integer:
3371
74.5k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3372
74.5k
3373
74.5k
    // If we have a sign or zero extended integer, make sure to return Extend
3374
74.5k
    // so that the parameter gets the right LLVM IR attributes.
3375
74.5k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)73.8k
) {
3376
39.2k
      // Treat an enum type as its underlying type.
3377
39.2k
      if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3378
89
        RetTy = EnumTy->getDecl()->getIntegerType();
3379
39.2k
3380
39.2k
      if (RetTy->isIntegralOrEnumerationType() &&
3381
39.2k
          
RetTy->isPromotableIntegerType()38.4k
)
3382
3.85k
        return ABIArgInfo::getExtend(RetTy);
3383
70.6k
    }
3384
70.6k
    break;
3385
70.6k
3386
70.6k
    // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3387
70.6k
    // available SSE register of the sequence %xmm0, %xmm1 is used.
3388
70.6k
  case SSE:
3389
2.91k
    ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3390
2.91k
    break;
3391
70.6k
3392
70.6k
    // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3393
70.6k
    // returned on the X87 stack in %st0 as 80-bit x87 number.
3394
70.6k
  case X87:
3395
646
    ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3396
646
    break;
3397
70.6k
3398
70.6k
    // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3399
70.6k
    // part of the value is returned in %st0 and the imaginary part in
3400
70.6k
    // %st1.
3401
70.6k
  case ComplexX87:
3402
37
    assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3403
37
    ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3404
37
                                    llvm::Type::getX86_FP80Ty(getVMContext()));
3405
37
    break;
3406
74.2k
  }
3407
74.2k
3408
74.2k
  llvm::Type *HighPart = nullptr;
3409
74.2k
  switch (Hi) {
3410
0
    // Memory was handled previously and X87 should
3411
0
    // never occur as a hi class.
3412
0
  case Memory:
3413
0
  case X87:
3414
0
    llvm_unreachable("Invalid classification for hi word.");
3415
0
3416
70.9k
  case ComplexX87: // Previously handled.
3417
70.9k
  case NoClass:
3418
70.9k
    break;
3419
70.9k
3420
70.9k
  case Integer:
3421
641
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3422
641
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3423
0
      return ABIArgInfo::getDirect(HighPart, 8);
3424
641
    break;
3425
641
  case SSE:
3426
135
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3427
135
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3428
1
      return ABIArgInfo::getDirect(HighPart, 8);
3429
134
    break;
3430
134
3431
134
    // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3432
134
    // is passed in the next available eightbyte chunk if the last used
3433
134
    // vector register.
3434
134
    //
3435
134
    // SSEUP should always be preceded by SSE, just widen.
3436
1.94k
  case SSEUp:
3437
1.94k
    assert(Lo == SSE && "Unexpected SSEUp classification.");
3438
1.94k
    ResType = GetByteVectorType(RetTy);
3439
1.94k
    break;
3440
134
3441
134
    // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3442
134
    // returned together with the previous X87 value in %st0.
3443
646
  case X87Up:
3444
646
    // If X87Up is preceded by X87, we don't need to do
3445
646
    // anything. However, in some cases with unions it may not be
3446
646
    // preceded by X87. In such situations we follow gcc and pass the
3447
646
    // extra bits in an SSE reg.
3448
646
    if (Lo != X87) {
3449
0
      HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3450
0
      if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3451
0
        return ABIArgInfo::getDirect(HighPart, 8);
3452
646
    }
3453
646
    break;
3454
74.2k
  }
3455
74.2k
3456
74.2k
  // If a high part was specified, merge it together with the low part.  It is
3457
74.2k
  // known to pass in the high eightbyte of the result.  We do this by forming a
3458
74.2k
  // first class struct aggregate with the high and low part: {low, high}
3459
74.2k
  if (HighPart)
3460
775
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3461
74.2k
3462
74.2k
  return ABIArgInfo::getDirect(ResType);
3463
74.2k
}
3464
3465
ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3466
  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3467
  bool isNamedArg)
3468
  const
3469
235k
{
3470
235k
  Ty = useFirstFieldIfTransparentUnion(Ty);
3471
235k
3472
235k
  X86_64ABIInfo::Class Lo, Hi;
3473
235k
  classify(Ty, 0, Lo, Hi, isNamedArg);
3474
235k
3475
235k
  // Check some invariants.
3476
235k
  // FIXME: Enforce these by construction.
3477
235k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3478
235k
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3479
235k
3480
235k
  neededInt = 0;
3481
235k
  neededSSE = 0;
3482
235k
  llvm::Type *ResType = nullptr;
3483
235k
  switch (Lo) {
3484
5.59k
  case NoClass:
3485
5.59k
    if (Hi == NoClass)
3486
5.58k
      return ABIArgInfo::getIgnore();
3487
2
    // If the low part is just padding, it takes no register, leave ResType
3488
2
    // null.
3489
2
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3490
2
           "Unknown missing lo part");
3491
2
    break;
3492
2
3493
2
    // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3494
2
    // on the stack.
3495
1.08k
  case Memory:
3496
1.08k
3497
1.08k
    // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3498
1.08k
    // COMPLEX_X87, it is passed in memory.
3499
1.08k
  case X87:
3500
1.08k
  case ComplexX87:
3501
1.08k
    if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3502
317
      ++neededInt;
3503
1.08k
    return getIndirectResult(Ty, freeIntRegs);
3504
1.08k
3505
1.08k
  case SSEUp:
3506
0
  case X87Up:
3507
0
    llvm_unreachable("Invalid classification for lo word.");
3508
0
3509
0
    // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3510
0
    // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3511
0
    // and %r9 is used.
3512
223k
  case Integer:
3513
223k
    ++neededInt;
3514
223k
3515
223k
    // Pick an 8-byte type based on the preferred type.
3516
223k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3517
223k
3518
223k
    // If we have a sign or zero extended integer, make sure to return Extend
3519
223k
    // so that the parameter gets the right LLVM IR attributes.
3520
223k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)222k
) {
3521
42.4k
      // Treat an enum type as its underlying type.
3522
42.4k
      if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3523
801
        Ty = EnumTy->getDecl()->getIntegerType();
3524
42.4k
3525
42.4k
      if (Ty->isIntegralOrEnumerationType() &&
3526
42.4k
          
Ty->isPromotableIntegerType()42.0k
)
3527
2.87k
        return ABIArgInfo::getExtend(Ty);
3528
220k
    }
3529
220k
3530
220k
    break;
3531
220k
3532
220k
    // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3533
220k
    // available SSE register is used, the registers are taken in the
3534
220k
    // order from %xmm0 to %xmm7.
3535
220k
  case SSE: {
3536
5.78k
    llvm::Type *IRType = CGT.ConvertType(Ty);
3537
5.78k
    ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3538
5.78k
    ++neededSSE;
3539
5.78k
    break;
3540
225k
  }
3541
225k
  }
3542
225k
3543
225k
  llvm::Type *HighPart = nullptr;
3544
225k
  switch (Hi) {
3545
0
    // Memory was handled previously, ComplexX87 and X87 should
3546
0
    // never occur as hi classes, and X87Up must be preceded by X87,
3547
0
    // which is passed in memory.
3548
0
  case Memory:
3549
0
  case X87:
3550
0
  case ComplexX87:
3551
0
    llvm_unreachable("Invalid classification for hi word.");
3552
0
3553
221k
  case NoClass: break;
3554
0
3555
649
  case Integer:
3556
649
    ++neededInt;
3557
649
    // Pick an 8-byte type based on the preferred type.
3558
649
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3559
649
3560
649
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3561
2
      return ABIArgInfo::getDirect(HighPart, 8);
3562
647
    break;
3563
647
3564
647
    // X87Up generally doesn't occur here (long double is passed in
3565
647
    // memory), except in situations involving unions.
3566
647
  case X87Up:
3567
152
  case SSE:
3568
152
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3569
152
3570
152
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3571
0
      return ABIArgInfo::getDirect(HighPart, 8);
3572
152
3573
152
    ++neededSSE;
3574
152
    break;
3575
152
3576
152
    // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3577
152
    // eightbyte is passed in the upper half of the last used SSE
3578
152
    // register.  This only happens when 128-bit vectors are passed.
3579
3.35k
  case SSEUp:
3580
3.35k
    assert(Lo == SSE && "Unexpected SSEUp classification");
3581
3.35k
    ResType = GetByteVectorType(Ty);
3582
3.35k
    break;
3583
225k
  }
3584
225k
3585
225k
  // If a high part was specified, merge it together with the low part.  It is
3586
225k
  // known to pass in the high eightbyte of the result.  We do this by forming a
3587
225k
  // first class struct aggregate with the high and low part: {low, high}
3588
225k
  if (HighPart)
3589
799
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3590
225k
3591
225k
  return ABIArgInfo::getDirect(ResType);
3592
225k
}
3593
3594
ABIArgInfo
3595
X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3596
18
                                             unsigned &NeededSSE) const {
3597
18
  auto RT = Ty->getAs<RecordType>();
3598
18
  assert(RT && "classifyRegCallStructType only valid with struct types");
3599
18
3600
18
  if (RT->getDecl()->hasFlexibleArrayMember())
3601
0
    return getIndirectReturnResult(Ty);
3602
18
3603
18
  // Sum up bases
3604
18
  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3605
0
    if (CXXRD->isDynamicClass()) {
3606
0
      NeededInt = NeededSSE = 0;
3607
0
      return getIndirectReturnResult(Ty);
3608
0
    }
3609
0
3610
0
    for (const auto &I : CXXRD->bases())
3611
0
      if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3612
0
              .isIndirect()) {
3613
0
        NeededInt = NeededSSE = 0;
3614
0
        return getIndirectReturnResult(Ty);
3615
0
      }
3616
0
  }
3617
18
3618
18
  // Sum up members
3619
44
  
for (const auto *FD : RT->getDecl()->fields())18
{
3620
44
    if (FD->getType()->isRecordType() && 
!FD->getType()->isUnionType()0
) {
3621
0
      if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3622
0
              .isIndirect()) {
3623
0
        NeededInt = NeededSSE = 0;
3624
0
        return getIndirectReturnResult(Ty);
3625
0
      }
3626
44
    } else {
3627
44
      unsigned LocalNeededInt, LocalNeededSSE;
3628
44
      if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3629
44
                               LocalNeededSSE, true)
3630
44
              .isIndirect()) {
3631
0
        NeededInt = NeededSSE = 0;
3632
0
        return getIndirectReturnResult(Ty);
3633
0
      }
3634
44
      NeededInt += LocalNeededInt;
3635
44
      NeededSSE += LocalNeededSSE;
3636
44
    }
3637
44
  }
3638
18
3639
18
  return ABIArgInfo::getDirect();
3640
18
}
3641
3642
ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3643
                                                    unsigned &NeededInt,
3644
18
                                                    unsigned &NeededSSE) const {
3645
18
3646
18
  NeededInt = 0;
3647
18
  NeededSSE = 0;
3648
18
3649
18
  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3650
18
}
3651
3652
133k
void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3653
133k
3654
133k
  const unsigned CallingConv = FI.getCallingConvention();
3655
133k
  // It is possible to force Win64 calling convention on any x86_64 target by
3656
133k
  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3657
133k
  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3658
133k
  if (CallingConv == llvm::CallingConv::Win64) {
3659
11
    WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
3660
11
    Win64ABIInfo.computeInfo(FI);
3661
11
    return;
3662
11
  }
3663
133k
3664
133k
  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3665
133k
3666
133k
  // Keep track of the number of assigned registers.
3667
133k
  unsigned FreeIntRegs = IsRegCall ? 
1123
:
6133k
;
3668
133k
  unsigned FreeSSERegs = IsRegCall ? 
1623
:
8133k
;
3669
133k
  unsigned NeededInt, NeededSSE;
3670
133k
3671
133k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3672
132k
    if (IsRegCall && 
FI.getReturnType()->getTypePtr()->isRecordType()22
&&
3673
132k
        
!FI.getReturnType()->getTypePtr()->isUnionType()2
) {
3674
2
      FI.getReturnInfo() =
3675
2
          classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3676
2
      if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3677
2
        FreeIntRegs -= NeededInt;
3678
2
        FreeSSERegs -= NeededSSE;
3679
2
      } else {
3680
0
        FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3681
0
      }
3682
132k
    } else if (IsRegCall && 
FI.getReturnType()->getAs<ComplexType>()20
) {
3683
1
      // Complex Long Double Type is passed in Memory when Regcall
3684
1
      // calling convention is used.
3685
1
      const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3686
1
      if (getContext().getCanonicalType(CT->getElementType()) ==
3687
1
          getContext().LongDoubleTy)
3688
1
        FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3689
1
    } else
3690
132k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3691
132k
  }
3692
133k
3693
133k
  // If the return value is indirect, then the hidden argument is consuming one
3694
133k
  // integer register.
3695
133k
  if (FI.getReturnInfo().isIndirect())
3696
747
    --FreeIntRegs;
3697
133k
3698
133k
  // The chain argument effectively gives us another free register.
3699
133k
  if (FI.isChainCall())
3700
4
    ++FreeIntRegs;
3701
133k
3702
133k
  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3703
133k
  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3704
133k
  // get assigned (in left-to-right order) for passing as follows...
3705
133k
  unsigned ArgNo = 0;
3706
133k
  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3707
368k
       it != ie; 
++it, ++ArgNo235k
) {
3708
235k
    bool IsNamedArg = ArgNo < NumRequiredArgs;
3709
235k
3710
235k
    if (IsRegCall && 
it->type->isStructureOrClassType()53
)
3711
16
      it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3712
235k
    else
3713
235k
      it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3714
235k
                                      NeededSSE, IsNamedArg);
3715
235k
3716
235k
    // AMD64-ABI 3.2.3p3: If there are no registers available for any
3717
235k
    // eightbyte of an argument, the whole argument is passed on the
3718
235k
    // stack. If registers have already been assigned for some
3719
235k
    // eightbytes of such an argument, the assignments get reverted.
3720
235k
    if (FreeIntRegs >= NeededInt && 
FreeSSERegs >= NeededSSE233k
) {
3721
233k
      FreeIntRegs -= NeededInt;
3722
233k
      FreeSSERegs -= NeededSSE;
3723
233k
    } else {
3724
2.11k
      it->info = getIndirectResult(it->type, FreeIntRegs);
3725
2.11k
    }
3726
235k
  }
3727
133k
}
3728
3729
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3730
87
                                         Address VAListAddr, QualType Ty) {
3731
87
  Address overflow_arg_area_p =
3732
87
      CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
3733
87
  llvm::Value *overflow_arg_area =
3734
87
    CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3735
87
3736
87
  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3737
87
  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3738
87
  // It isn't stated explicitly in the standard, but in practice we use
3739
87
  // alignment greater than 16 where necessary.
3740
87
  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3741
87
  if (Align > CharUnits::fromQuantity(8)) {
3742
18
    overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3743
18
                                                      Align);
3744
18
  }
3745
87
3746
87
  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3747
87
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3748
87
  llvm::Value *Res =
3749
87
    CGF.Builder.CreateBitCast(overflow_arg_area,
3750
87
                              llvm::PointerType::getUnqual(LTy));
3751
87
3752
87
  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3753
87
  // l->overflow_arg_area + sizeof(type).
3754
87
  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3755
87
  // an 8 byte boundary.
3756
87
3757
87
  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3758
87
  llvm::Value *Offset =
3759
87
      llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7)  & ~7);
3760
87
  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3761
87
                                            "overflow_arg_area.next");
3762
87
  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3763
87
3764
87
  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3765
87
  return Address(Res, Align);
3766
87
}
3767
3768
Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3769
87
                                 QualType Ty) const {
3770
87
  // Assume that va_list type is correct; should be pointer to LLVM type:
3771
87
  // struct {
3772
87
  //   i32 gp_offset;
3773
87
  //   i32 fp_offset;
3774
87
  //   i8* overflow_arg_area;
3775
87
  //   i8* reg_save_area;
3776
87
  // };
3777
87
  unsigned neededInt, neededSSE;
3778
87
3779
87
  Ty = getContext().getCanonicalType(Ty);
3780
87
  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3781
87
                                       /*isNamedArg*/false);
3782
87
3783
87
  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3784
87
  // in the registers. If not go to step 7.
3785
87
  if (!neededInt && 
!neededSSE30
)
3786
14
    return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3787
73
3788
73
  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3789
73
  // general purpose registers needed to pass type and num_fp to hold
3790
73
  // the number of floating point registers needed.
3791
73
3792
73
  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3793
73
  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3794
73
  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3795
73
  //
3796
73
  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3797
73
  // register save space).
3798
73
3799
73
  llvm::Value *InRegs = nullptr;
3800
73
  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3801
73
  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3802
73
  if (neededInt) {
3803
57
    gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
3804
57
    gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3805
57
    InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3806
57
    InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3807
57
  }
3808
73
3809
73
  if (neededSSE) {
3810
20
    fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
3811
20
    fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3812
20
    llvm::Value *FitsInFP =
3813
20
      llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3814
20
    FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3815
20
    InRegs = InRegs ? 
CGF.Builder.CreateAnd(InRegs, FitsInFP)4
:
FitsInFP16
;
3816
20
  }
3817
73
3818
73
  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3819
73
  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3820
73
  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3821
73
  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3822
73
3823
73
  // Emit code to load the value if it was passed in registers.
3824
73
3825
73
  CGF.EmitBlock(InRegBlock);
3826
73
3827
73
  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3828
73
  // an offset of l->gp_offset and/or l->fp_offset. This may require
3829
73
  // copying to a temporary location in case the parameter is passed
3830
73
  // in different register classes or requires an alignment greater
3831
73
  // than 8 for general purpose registers and 16 for XMM registers.
3832
73
  //
3833
73
  // FIXME: This really results in shameful code when we end up needing to
3834
73
  // collect arguments from different places; often what should result in a
3835
73
  // simple assembling of a structure from scattered addresses has many more
3836
73
  // loads than necessary. Can we clean this up?
3837
73
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3838
73
  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3839
73
      CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
3840
73
3841
73
  Address RegAddr = Address::invalid();
3842
73
  if (neededInt && 
neededSSE57
) {
3843
4
    // FIXME: Cleanup.
3844
4
    assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3845
4
    llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3846
4
    Address Tmp = CGF.CreateMemTemp(Ty);
3847
4
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3848
4
    assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3849
4
    llvm::Type *TyLo = ST->getElementType(0);
3850
4
    llvm::Type *TyHi = ST->getElementType(1);
3851
4
    assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3852
4
           "Unexpected ABI info for mixed regs");
3853
4
    llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3854
4
    llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3855
4
    llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3856
4
    llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3857
4
    llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? 
FPAddr1
:
GPAddr3
;
3858
4
    llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? 
GPAddr1
:
FPAddr3
;
3859
4
3860
4
    // Copy the first element.
3861
4
    // FIXME: Our choice of alignment here and below is probably pessimistic.
3862
4
    llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3863
4
        TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3864
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3865
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3866
4
3867
4
    // Copy the second element.
3868
4
    V = CGF.Builder.CreateAlignedLoad(
3869
4
        TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3870
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3871
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3872
4
3873
4
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3874
69
  } else if (neededInt) {
3875
53
    RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3876
53
                      CharUnits::fromQuantity(8));
3877
53
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3878
53
3879
53
    // Copy to a temporary if necessary to ensure the appropriate alignment.
3880
53
    std::pair<CharUnits, CharUnits> SizeAlign =
3881
53
        getContext().getTypeInfoInChars(Ty);
3882
53
    uint64_t TySize = SizeAlign.first.getQuantity();
3883
53
    CharUnits TyAlign = SizeAlign.second;
3884
53
3885
53
    // Copy into a temporary if the type is more aligned than the
3886
53
    // register save area.
3887
53
    if (TyAlign.getQuantity() > 8) {
3888
3
      Address Tmp = CGF.CreateMemTemp(Ty);
3889
3
      CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3890
3
      RegAddr = Tmp;
3891
3
    }
3892
53
3893
53
  } else 
if (16
neededSSE == 116
) {
3894
7
    RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3895
7
                      CharUnits::fromQuantity(16));
3896
7
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3897
9
  } else {
3898
9
    assert(neededSSE == 2 && "Invalid number of needed registers!");
3899
9
    // SSE registers are spaced 16 bytes apart in the register save
3900
9
    // area, we need to collect the two eightbytes together.
3901
9
    // The ABI isn't explicit about this, but it seems reasonable
3902
9
    // to assume that the slots are 16-byte aligned, since the stack is
3903
9
    // naturally 16-byte aligned and the prologue is expected to store
3904
9
    // all the SSE registers to the RSA.
3905
9
    Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3906
9
                                CharUnits::fromQuantity(16));
3907
9
    Address RegAddrHi =
3908
9
      CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3909
9
                                             CharUnits::fromQuantity(16));
3910
9
    llvm::Type *ST = AI.canHaveCoerceToType()
3911
9
                         ? AI.getCoerceToType()
3912
9
                         : 
llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy)0
;
3913
9
    llvm::Value *V;
3914
9
    Address Tmp = CGF.CreateMemTemp(Ty);
3915
9
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3916
9
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3917
9
        RegAddrLo, ST->getStructElementType(0)));
3918
9
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3919
9
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3920
9
        RegAddrHi, ST->getStructElementType(1)));
3921
9
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3922
9
3923
9
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3924
9
  }
3925
73
3926
73
  // AMD64-ABI 3.5.7p5: Step 5. Set:
3927
73
  // l->gp_offset = l->gp_offset + num_gp * 8
3928
73
  // l->fp_offset = l->fp_offset + num_fp * 16.
3929
73
  if (neededInt) {
3930
57
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3931
57
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3932
57
                            gp_offset_p);
3933
57
  }
3934
73
  if (neededSSE) {
3935
20
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3936
20
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3937
20
                            fp_offset_p);
3938
20
  }
3939
73
  CGF.EmitBranch(ContBlock);
3940
73
3941
73
  // Emit code to load the value if it was passed in memory.
3942
73
3943
73
  CGF.EmitBlock(InMemBlock);
3944
73
  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3945
73
3946
73
  // Return the appropriate result.
3947
73
3948
73
  CGF.EmitBlock(ContBlock);
3949
73
  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3950
73
                                 "vaarg.addr");
3951
73
  return ResAddr;
3952
73
}
3953
3954
Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3955
8
                                   QualType Ty) const {
3956
8
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3957
8
                          CGF.getContext().getTypeInfoInChars(Ty),
3958
8
                          CharUnits::fromQuantity(8),
3959
8
                          /*allowHigherAlign*/ false);
3960
8
}
3961
3962
ABIArgInfo
3963
WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3964
97
                                    const ABIArgInfo &current) const {
3965
97
  // Assumes vectorCall calling convention.
3966
97
  const Type *Base = nullptr;
3967
97
  uint64_t NumElts = 0;
3968
97
3969
97
  if (!Ty->isBuiltinType() && 
!Ty->isVectorType()49
&&
3970
97
      
isHomogeneousAggregate(Ty, Base, NumElts)36
&&
FreeSSERegs >= NumElts27
) {
3971
18
    FreeSSERegs -= NumElts;
3972
18
    return getDirectX86Hva();
3973
18
  }
3974
79
  return current;
3975
79
}
3976
3977
ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3978
                                      bool IsReturnType, bool IsVectorCall,
3979
9.01k
                                      bool IsRegCall) const {
3980
9.01k
3981
9.01k
  if (Ty->isVoidType())
3982
1.44k
    return ABIArgInfo::getIgnore();
3983
7.57k
3984
7.57k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3985
15
    Ty = EnumTy->getDecl()->getIntegerType();
3986
7.57k
3987
7.57k
  TypeInfo Info = getContext().getTypeInfo(Ty);
3988
7.57k
  uint64_t Width = Info.Width;
3989
7.57k
  CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3990
7.57k
3991
7.57k
  const RecordType *RT = Ty->getAs<RecordType>();
3992
7.57k
  if (RT) {
3993
256
    if (!IsReturnType) {
3994
226
      if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3995
71
        return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3996
185
    }
3997
185
3998
185
    if (RT->getDecl()->hasFlexibleArrayMember())
3999
0
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4000
7.50k
4001
7.50k
  }
4002
7.50k
4003
7.50k
  const Type *Base = nullptr;
4004
7.50k
  uint64_t NumElts = 0;
4005
7.50k
  // vectorcall adds the concept of a homogenous vector aggregate, similar to
4006
7.50k
  // other targets.
4007
7.50k
  if ((IsVectorCall || 
IsRegCall7.38k
) &&
4008
7.50k
      
isHomogeneousAggregate(Ty, Base, NumElts)169
) {
4009
92
    if (IsRegCall) {
4010
29
      if (FreeSSERegs >= NumElts) {
4011
29
        FreeSSERegs -= NumElts;
4012
29
        if (IsReturnType || 
Ty->isBuiltinType()26
||
Ty->isVectorType()20
)
4013
15
          return ABIArgInfo::getDirect();
4014
14
        return ABIArgInfo::getExpand();
4015
14
      }
4016
0
      return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4017
63
    } else if (IsVectorCall) {
4018
63
      if (FreeSSERegs >= NumElts &&
4019
63
          
(57
IsReturnType57
||
Ty->isBuiltinType()45
||
Ty->isVectorType()36
)) {
4020
34
        FreeSSERegs -= NumElts;
4021
34
        return ABIArgInfo::getDirect();
4022
34
      } else 
if (29
IsReturnType29
) {
4023
0
        return ABIArgInfo::getExpand();
4024
29
      } else if (!Ty->isBuiltinType() && 
!Ty->isVectorType()27
) {
4025
27
        // HVAs are delayed and reclassified in the 2nd step.
4026
27
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4027
27
      }
4028
7.41k
    }
4029
92
  }
4030
7.41k
4031
7.41k
  if (Ty->isMemberPointerType()) {
4032
156
    // If the member pointer is represented by an LLVM int or ptr, pass it
4033
156
    // directly.
4034
156
    llvm::Type *LLTy = CGT.ConvertType(Ty);
4035
156
    if (LLTy->isPointerTy() || 
LLTy->isIntegerTy()75
)
4036
88
      return ABIArgInfo::getDirect();
4037
7.32k
  }
4038
7.32k
4039
7.32k
  if (RT || 
Ty->isAnyComplexType()7.18k
||
Ty->isMemberPointerType()7.17k
) {
4040
218
    // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4041
218
    // not 1, 2, 4, or 8 bytes, must be passed by reference."
4042
218
    if (Width > 64 || 
!llvm::isPowerOf2_64(Width)117
)
4043
101
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4044
117
4045
117
    // Otherwise, coerce it to a small integer.
4046
117
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
4047
117
  }
4048
7.10k
4049
7.10k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4050
1.93k
    switch (BT->getKind()) {
4051
29
    case BuiltinType::Bool:
4052
29
      // Bool type is always extended to the ABI, other builtin types are not
4053
29
      // extended.
4054
29
      return ABIArgInfo::getExtend(Ty);
4055
0
4056
56
    case BuiltinType::LongDouble:
4057
56
      // Mingw64 GCC uses the old 80 bit extended precision floating point
4058
56
      // unit. It passes them indirectly through memory.
4059
56
      if (IsMingw64) {
4060
6
        const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
4061
6
        if (LDF == &llvm::APFloat::x87DoubleExtended())
4062
6
          return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4063
50
      }
4064
50
      break;
4065
50
4066
50
    case BuiltinType::Int128:
4067
8
    case BuiltinType::UInt128:
4068
8
      // If it's a parameter type, the normal ABI rule is that arguments larger
4069
8
      // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
4070
8
      // even though it isn't particularly efficient.
4071
8
      if (!IsReturnType)
4072
4
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4073
4
4074
4
      // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
4075
4
      // Clang matches them for compatibility.
4076
4
      return ABIArgInfo::getDirect(
4077
4
          llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2));
4078
4
4079
1.84k
    default:
4080
1.84k
      break;
4081
7.06k
    }
4082
7.06k
  }
4083
7.06k
4084
7.06k
  return ABIArgInfo::getDirect();
4085
7.06k
}
4086
4087
void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
4088
                                             unsigned FreeSSERegs,
4089
                                             bool IsVectorCall,
4090
48
                                             bool IsRegCall) const {
4091
48
  unsigned Count = 0;
4092
97
  for (auto &I : FI.arguments()) {
4093
97
    // Vectorcall in x64 only permits the first 6 arguments to be passed
4094
97
    // as XMM/YMM registers.
4095
97
    if (Count < VectorcallMaxParamNumAsReg)
4096
92
      I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4097
5
    else {
4098
5
      // Since these cannot be passed in registers, pretend no registers
4099
5
      // are left.
4100
5
      unsigned ZeroSSERegsAvail = 0;
4101
5
      I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
4102
5
                        IsVectorCall, IsRegCall);
4103
5
    }
4104
97
    ++Count;
4105
97
  }
4106
48
4107
97
  for (auto &I : FI.arguments()) {
4108
97
    I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
4109
97
  }
4110
48
}
4111
4112
3.67k
void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4113
3.67k
  const unsigned CC = FI.getCallingConvention();
4114
3.67k
  bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
4115
3.67k
  bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
4116
3.67k
4117
3.67k
  // If __attribute__((sysv_abi)) is in use, use the SysV argument
4118
3.67k
  // classification rules.
4119
3.67k
  if (CC == llvm::CallingConv::X86_64_SysV) {
4120
14
    X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
4121
14
    SysVABIInfo.computeInfo(FI);
4122
14
    return;
4123
14
  }
4124
3.66k
4125
3.66k
  unsigned FreeSSERegs = 0;
4126
3.66k
  if (IsVectorCall) {
4127
48
    // We can use up to 4 SSE return registers with vectorcall.
4128
48
    FreeSSERegs = 4;
4129
3.61k
  } else if (IsRegCall) {
4130
22
    // RegCall gives us 16 SSE registers.
4131
22
    FreeSSERegs = 16;
4132
22
  }
4133
3.66k
4134
3.66k
  if (!getCXXABI().classifyReturnType(FI))
4135
3.62k
    FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4136
3.62k
                                  IsVectorCall, IsRegCall);
4137
3.66k
4138
3.66k
  if (IsVectorCall) {
4139
48
    // We can use up to 6 SSE register parameters with vectorcall.
4140
48
    FreeSSERegs = 6;
4141
3.61k
  } else if (IsRegCall) {
4142
22
    // RegCall gives us 16 SSE registers, we can reuse the return registers.
4143
22
    FreeSSERegs = 16;
4144
22
  }
4145
3.66k
4146
3.66k
  if (IsVectorCall) {
4147
48
    computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4148
3.61k
  } else {
4149
3.61k
    for (auto &I : FI.arguments())
4150
5.28k
      I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4151
3.61k
  }
4152
3.66k
4153
3.66k
}
4154
4155
Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4156
9
                                    QualType Ty) const {
4157
9
4158
9
  bool IsIndirect = false;
4159
9
4160
9
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4161
9
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4162
9
  if (isAggregateTypeForABI(Ty) || 
Ty->isMemberPointerType()3
) {
4163
6
    uint64_t Width = getContext().getTypeSize(Ty);
4164
6
    IsIndirect = Width > 64 || 
!llvm::isPowerOf2_64(Width)0
;
4165
6
  }
4166
9
4167
9
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4168
9
                          CGF.getContext().getTypeInfoInChars(Ty),
4169
9
                          CharUnits::fromQuantity(8),
4170
9
                          /*allowHigherAlign*/ false);
4171
9
}
4172
4173
// PowerPC-32
4174
namespace {
4175
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4176
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4177
  bool IsSoftFloatABI;
4178
4179
  CharUnits getParamTypeAlignment(QualType Ty) const;
4180
4181
public:
4182
  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4183
29
      : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4184
4185
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4186
                    QualType Ty) const override;
4187
};
4188
4189
class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4190
public:
4191
  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4192
29
      : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4193
4194
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4195
0
    // This is recovered from gcc output.
4196
0
    return 1; // r1 is the dedicated stack pointer
4197
0
  }
4198
4199
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4200
                               llvm::Value *Address) const override;
4201
};
4202
}
4203
4204
0
CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4205
0
  // Complex types are passed just like their elements
4206
0
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4207
0
    Ty = CTy->getElementType();
4208
0
4209
0
  if (Ty->isVectorType())
4210
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4211
0
                                                                       : 4);
4212
0
4213
0
  // For single-element float/vector structs, we consider the whole type
4214
0
  // to have the same alignment requirements as its single element.
4215
0
  const Type *AlignTy = nullptr;
4216
0
  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4217
0
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
4218
0
    if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4219
0
        (BT && BT->isFloatingPoint()))
4220
0
      AlignTy = EltType;
4221
0
  }
4222
0
4223
0
  if (AlignTy)
4224
0
    return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4225
0
  return CharUnits::fromQuantity(4);
4226
0
}
4227
4228
// TODO: this implementation is now likely redundant with
4229
// DefaultABIInfo::EmitVAArg.
4230
Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4231
3
                                      QualType Ty) const {
4232
3
  if (getTarget().getTriple().isOSDarwin()) {
4233
0
    auto TI = getContext().getTypeInfoInChars(Ty);
4234
0
    TI.second = getParamTypeAlignment(Ty);
4235
0
4236
0
    CharUnits SlotSize = CharUnits::fromQuantity(4);
4237
0
    return emitVoidPtrVAArg(CGF, VAList, Ty,
4238
0
                            classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4239
0
                            /*AllowHigherAlign=*/true);
4240
0
  }
4241
3
4242
3
  const unsigned OverflowLimit = 8;
4243
3
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4244
0
    // TODO: Implement this. For now ignore.
4245
0
    (void)CTy;
4246
0
    return Address::invalid(); // FIXME?
4247
0
  }
4248
3
4249
3
  // struct __va_list_tag {
4250
3
  //   unsigned char gpr;
4251
3
  //   unsigned char fpr;
4252
3
  //   unsigned short reserved;
4253
3
  //   void *overflow_arg_area;
4254
3
  //   void *reg_save_area;
4255
3
  // };
4256
3
4257
3
  bool isI64 = Ty->isIntegerType() && 
getContext().getTypeSize(Ty) == 641
;
4258
3
  bool isInt =
4259
3
      Ty->isIntegerType() || 
Ty->isPointerType()2
||
Ty->isAggregateType()2
;
4260
3
  bool isF64 = Ty->isFloatingType() && 
getContext().getTypeSize(Ty) == 641
;
4261
3
4262
3
  // All aggregates are passed indirectly?  That doesn't seem consistent
4263
3
  // with the argument-lowering code.
4264
3
  bool isIndirect = Ty->isAggregateType();
4265
3
4266
3
  CGBuilderTy &Builder = CGF.Builder;
4267
3
4268
3
  // The calling convention either uses 1-2 GPRs or 1 FPR.
4269
3
  Address NumRegsAddr = Address::invalid();
4270
3
  if (isInt || 
IsSoftFloatABI1
) {
4271
3
    NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4272
3
  } else {
4273
0
    NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4274
0
  }
4275
3
4276
3
  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4277
3
4278
3
  // "Align" the register count when TY is i64.
4279
3
  if (isI64 || (isF64 && 
IsSoftFloatABI1
)) {
4280
1
    NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4281
1
    NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4282
1
  }
4283
3
4284
3
  llvm::Value *CC =
4285
3
      Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4286
3
4287
3
  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4288
3
  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4289
3
  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4290
3
4291
3
  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4292
3
4293
3
  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4294
3
  if (isIndirect) 
DirectTy = DirectTy->getPointerTo(0)1
;
4295
3
4296
3
  // Case 1: consume registers.
4297
3
  Address RegAddr = Address::invalid();
4298
3
  {
4299
3
    CGF.EmitBlock(UsingRegs);
4300
3
4301
3
    Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4302
3
    RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4303
3
                      CharUnits::fromQuantity(8));
4304
3
    assert(RegAddr.getElementType() == CGF.Int8Ty);
4305
3
4306
3
    // Floating-point registers start after the general-purpose registers.
4307
3
    if (!(isInt || 
IsSoftFloatABI1
)) {
4308
0
      RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4309
0
                                                   CharUnits::fromQuantity(32));
4310
0
    }
4311
3
4312
3
    // Get the address of the saved value by scaling the number of
4313
3
    // registers we've used by the number of
4314
3
    CharUnits RegSize = CharUnits::fromQuantity((isInt || 
IsSoftFloatABI1
) ? 4 :
80
);
4315
3
    llvm::Value *RegOffset =
4316
3
      Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4317
3
    RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4318
3
                                            RegAddr.getPointer(), RegOffset),
4319
3
                      RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4320
3
    RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4321
3
4322
3
    // Increase the used-register count.
4323
3
    NumRegs =
4324
3
      Builder.CreateAdd(NumRegs,
4325
3
                        Builder.getInt8((isI64 || (isF64 && 
IsSoftFloatABI1
)) ?
21
:
12
));
4326
3
    Builder.CreateStore(NumRegs, NumRegsAddr);
4327
3
4328
3
    CGF.EmitBranch(Cont);
4329
3
  }
4330
3
4331
3
  // Case 2: consume space in the overflow area.
4332
3
  Address MemAddr = Address::invalid();
4333
3
  {
4334
3
    CGF.EmitBlock(UsingOverflow);
4335
3
4336
3
    Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4337
3
4338
3
    // Everything in the overflow area is rounded up to a size of at least 4.
4339
3
    CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4340
3
4341
3
    CharUnits Size;
4342
3
    if (!isIndirect) {
4343
2
      auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4344
2
      Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4345
2
    } else {
4346
1
      Size = CGF.getPointerSize();
4347
1
    }
4348
3
4349
3
    Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4350
3
    Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4351
3
                         OverflowAreaAlign);
4352
3
    // Round up address of argument to alignment
4353
3
    CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4354
3
    if (Align > OverflowAreaAlign) {
4355
2
      llvm::Value *Ptr = OverflowArea.getPointer();
4356
2
      OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4357
2
                                                           Align);
4358
2
    }
4359
3
4360
3
    MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4361
3
4362
3
    // Increase the overflow area.
4363
3
    OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4364
3
    Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4365
3
    CGF.EmitBranch(Cont);
4366
3
  }
4367
3
4368
3
  CGF.EmitBlock(Cont);
4369
3
4370
3
  // Merge the cases with a phi.
4371
3
  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4372
3
                                "vaarg.addr");
4373
3
4374
3
  // Load the pointer if the argument was passed indirectly.
4375
3
  if (isIndirect) {
4376
1
    Result = Address(Builder.CreateLoad(Result, "aggr"),
4377
1
                     getContext().getTypeAlignInChars(Ty));
4378
1
  }
4379
3
4380
3
  return Result;
4381
3
}
4382
4383
bool
4384
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4385
0
                                                llvm::Value *Address) const {
4386
0
  // This is calculated from the LLVM and GCC tables and verified
4387
0
  // against gcc output.  AFAIK all ABIs use the same encoding.
4388
0
4389
0
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4390
0
4391
0
  llvm::IntegerType *i8 = CGF.Int8Ty;
4392
0
  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4393
0
  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4394
0
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4395
0
4396
0
  // 0-31: r0-31, the 4-byte general-purpose registers
4397
0
  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4398
0
4399
0
  // 32-63: fp0-31, the 8-byte floating-point registers
4400
0
  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4401
0
4402
0
  // 64-76 are various 4-byte special-purpose registers:
4403
0
  // 64: mq
4404
0
  // 65: lr
4405
0
  // 66: ctr
4406
0
  // 67: ap
4407
0
  // 68-75 cr0-7
4408
0
  // 76: xer
4409
0
  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4410
0
4411
0
  // 77-108: v0-31, the 16-byte vector registers
4412
0
  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4413
0
4414
0
  // 109: vrsave
4415
0
  // 110: vscr
4416
0
  // 111: spe_acc
4417
0
  // 112: spefscr
4418
0
  // 113: sfp
4419
0
  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4420
0
4421
0
  return false;
4422
0
}
4423
4424
// PowerPC-64
4425
4426
namespace {
4427
/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4428
class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4429
public:
4430
  enum ABIKind {
4431
    ELFv1 = 0,
4432
    ELFv2
4433
  };
4434
4435
private:
4436
  static const unsigned GPRBits = 64;
4437
  ABIKind Kind;
4438
  bool HasQPX;
4439
  bool IsSoftFloatABI;
4440
4441
  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4442
  // will be passed in a QPX register.
4443
4.60k
  bool IsQPXVectorTy(const Type *Ty) const {
4444
4.60k
    if (!HasQPX)
4445
4.59k
      return false;
4446
9
4447
9
    if (const VectorType *VT = Ty->getAs<VectorType>()) {
4448
6
      unsigned NumElements = VT->getNumElements();
4449
6
      if (NumElements == 1)
4450
0
        return false;
4451
6
4452
6
      if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4453
3
        if (getContext().getTypeSize(Ty) <= 256)
4454
3
          return true;
4455
3
      } else if (VT->getElementType()->
4456
3
                   isSpecificBuiltinType(BuiltinType::Float)) {
4457
3
        if (getContext().getTypeSize(Ty) <= 128)
4458
3
          return true;
4459
3
      }
4460
6
    }
4461
3
4462
3
    return false;
4463
3
  }
4464
4465
4.53k
  bool IsQPXVectorTy(QualType Ty) const {
4466
4.53k
    return IsQPXVectorTy(Ty.getTypePtr());
4467
4.53k
  }
4468
4469
public:
4470
  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4471
                     bool SoftFloatABI)
4472
      : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4473
1.88k
        IsSoftFloatABI(SoftFloatABI) {}
4474
4475
  bool isPromotableTypeForABI(QualType Ty) const;
4476
  CharUnits getParamTypeAlignment(QualType Ty) const;
4477
4478
  ABIArgInfo classifyReturnType(QualType RetTy) const;
4479
  ABIArgInfo classifyArgumentType(QualType Ty) const;
4480
4481
  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4482
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4483
                                         uint64_t Members) const override;
4484
4485
  // TODO: We can add more logic to computeInfo to improve performance.
4486
  // Example: For aggregate arguments that fit in a register, we could
4487
  // use getDirectInReg (as is done below for structs containing a single
4488
  // floating-point value) to avoid pushing them to memory on function
4489
  // entry.  This would require changing the logic in PPCISelLowering
4490
  // when lowering the parameters in the caller and args in the callee.
4491
11.9k
  void computeInfo(CGFunctionInfo &FI) const override {
4492
11.9k
    if (!getCXXABI().classifyReturnType(FI))
4493
11.9k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4494
24.1k
    for (auto &I : FI.arguments()) {
4495
24.1k
      // We rely on the default argument classification for the most part.
4496
24.1k
      // One exception:  An aggregate containing a single floating-point
4497
24.1k
      // or vector item must be passed in a register if one is available.
4498
24.1k
      const Type *T = isSingleElementStruct(I.type, getContext());
4499
24.1k
      if (T) {
4500
18
        const BuiltinType *BT = T->getAs<BuiltinType>();
4501
18
        if (IsQPXVectorTy(T) ||
4502
18
            
(16
T->isVectorType()16
&&
getContext().getTypeSize(T) == 1286
) ||
4503
18
            
(12
BT12
&&
BT->isFloatingPoint()8
)) {
4504
14
          QualType QT(T, 0);
4505
14
          I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4506
14
          continue;
4507
14
        }
4508
24.1k
      }
4509
24.1k
      I.info = classifyArgumentType(I.type);
4510
24.1k
    }
4511
11.9k
  }
4512
4513
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4514
                    QualType Ty) const override;
4515
4516
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4517
0
                                    bool asReturnValue) const override {
4518
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4519
0
  }
4520
4521
0
  bool isSwiftErrorInRegister() const override {
4522
0
    return false;
4523
0
  }
4524
};
4525
4526
class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4527
4528
public:
4529
  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4530
                               PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4531
                               bool SoftFloatABI)
4532
      : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4533
1.88k
                                                 SoftFloatABI)) {}
4534
4535
1
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4536
1
    // This is recovered from gcc output.
4537
1
    return 1; // r1 is the dedicated stack pointer
4538
1
  }
4539
4540
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4541
                               llvm::Value *Address) const override;
4542
};
4543
4544
class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4545
public:
4546
0
  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4547
4548
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4549
0
    // This is recovered from gcc output.
4550
0
    return 1; // r1 is the dedicated stack pointer
4551
0
  }
4552
4553
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4554
                               llvm::Value *Address) const override;
4555
};
4556
4557
}
4558
4559
// Return true if the ABI requires Ty to be passed sign- or zero-
4560
// extended to 64 bits.
4561
bool
4562
27.9k
PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4563
27.9k
  // Treat an enum type as its underlying type.
4564
27.9k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4565
2
    Ty = EnumTy->getDecl()->getIntegerType();
4566
27.9k
4567
27.9k
  // Promotable integer types are required to be promoted by the ABI.
4568
27.9k
  if (Ty->isPromotableIntegerType())
4569
265
    return true;
4570
27.6k
4571
27.6k
  // In addition to the usual promotable integer types, we also need to
4572
27.6k
  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4573
27.6k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4574
10.2k
    switch (BT->getKind()) {
4575
4.38k
    case BuiltinType::Int:
4576
4.38k
    case BuiltinType::UInt:
4577
4.38k
      return true;
4578
5.87k
    default:
4579
5.87k
      break;
4580
23.3k
    }
4581
23.3k
4582
23.3k
  return false;
4583
23.3k
}
4584
4585
/// isAlignedParamType - Determine whether a type requires 16-byte or
4586
/// higher alignment in the parameter area.  Always returns at least 8.
4587
119
CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4588
119
  // Complex types are passed just like their elements.
4589
119
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4590
8
    Ty = CTy->getElementType();
4591
119
4592
119
  // Only vector types of size 16 bytes need alignment (larger types are
4593
119
  // passed via reference, smaller types are not aligned).
4594
119
  if (IsQPXVectorTy(Ty)) {
4595
0
    if (getContext().getTypeSize(Ty) > 128)
4596
0
      return CharUnits::fromQuantity(32);
4597
0
4598
0
    return CharUnits::fromQuantity(16);
4599
119
  } else if (Ty->isVectorType()) {
4600
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4601
0
  }
4602
119
4603
119
  // For single-element float/vector structs, we consider the whole type
4604
119
  // to have the same alignment requirements as its single element.
4605
119
  const Type *AlignAsType = nullptr;
4606
119
  const Type *EltType = isSingleElementStruct(Ty, getContext());
4607
119
  if (EltType) {
4608
4
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
4609
4
    if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4610
4
         
getContext().getTypeSize(EltType) == 1283
) ||
4611
4
        
(3
BT3
&&
BT->isFloatingPoint()1
))
4612
2
      AlignAsType = EltType;
4613
4
  }
4614
119
4615
119
  // Likewise for ELFv2 homogeneous aggregates.
4616
119
  const Type *Base = nullptr;
4617
119
  uint64_t Members = 0;
4618
119
  if (!AlignAsType && 
Kind == ELFv2117
&&
4619
119
      
isAggregateTypeForABI(Ty)78
&&
isHomogeneousAggregate(Ty, Base, Members)74
)
4620
46
    AlignAsType = Base;
4621
119
4622
119
  // With special case aggregates, only vector base types need alignment.
4623
119
  if (AlignAsType && 
IsQPXVectorTy(AlignAsType)48
) {
4624
0
    if (getContext().getTypeSize(AlignAsType) > 128)
4625
0
      return CharUnits::fromQuantity(32);
4626
0
4627
0
    return CharUnits::fromQuantity(16);
4628
119
  } else if (AlignAsType) {
4629
48
    return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 
1619
:
829
);
4630
48
  }
4631
71
4632
71
  // Otherwise, we only need alignment for any aggregate type that
4633
71
  // has an alignment requirement of >= 16 bytes.
4634
71
  if (isAggregateTypeForABI(Ty) && 
getContext().getTypeAlign(Ty) >= 12861
) {
4635
19
    if (HasQPX && 
getContext().getTypeAlign(Ty) >= 2562
)
4636
1
      return CharUnits::fromQuantity(32);
4637
18
    return CharUnits::fromQuantity(16);
4638
18
  }
4639
52
4640
52
  return CharUnits::fromQuantity(8);
4641
52
}
4642
4643
/// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4644
/// aggregate.  Base is set to the base element type, and Members is set
4645
/// to the number of base elements.
4646
bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4647
5.52k
                                     uint64_t &Members) const {
4648
5.52k
  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4649
1.02k
    uint64_t NElements = AT->getSize().getZExtValue();
4650
1.02k
    if (NElements == 0)
4651
0
      return false;
4652
1.02k
    if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4653
130
      return false;
4654
896
    Members *= NElements;
4655
4.49k
  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4656
1.80k
    const RecordDecl *RD = RT->getDecl();
4657
1.80k
    if (RD->hasFlexibleArrayMember())
4658
0
      return false;
4659
1.80k
4660
1.80k
    Members = 0;
4661
1.80k
4662
1.80k
    // If this is a C++ record, check the bases first.
4663
1.80k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4664
395
      for (const auto &I : CXXRD->bases()) {
4665
163
        // Ignore empty records.
4666
163
        if (isEmptyRecord(getContext(), I.getType(), true))
4667
6
          continue;
4668
157
4669
157
        uint64_t FldMembers;
4670
157
        if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4671
23
          return false;
4672
134
4673
134
        Members += FldMembers;
4674
134
      }
4675
395
    }
4676
1.80k
4677
2.26k
    
for (const auto *FD : RD->fields())1.77k
{
4678
2.26k
      // Ignore (non-zero arrays of) empty records.
4679
2.26k
      QualType FT = FD->getType();
4680
3.29k
      while (const ConstantArrayType *AT =
4681
1.02k
             getContext().getAsConstantArrayType(FT)) {
4682
1.02k
        if (AT->getSize().getZExtValue() == 0)
4683
0
          return false;
4684
1.02k
        FT = AT->getElementType();
4685
1.02k
      }
4686
2.26k
      if (isEmptyRecord(getContext(), FT, true))
4687
10
        continue;
4688
2.25k
4689
2.25k
      // For compatibility with GCC, ignore empty bitfields in C++ mode.
4690
2.25k
      if (getContext().getLangOpts().CPlusPlus &&
4691
2.25k
          
FD->isZeroLengthBitField(getContext())349
)
4692
6
        continue;
4693
2.25k
4694
2.25k
      uint64_t FldMembers;
4695
2.25k
      if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4696
490
        return false;
4697
1.76k
4698
1.76k
      Members = (RD->isUnion() ?
4699
1.73k
                 
std::max(Members, FldMembers)27
: Members + FldMembers);
4700
1.76k
    }
4701
1.77k
4702
1.77k
    
if (1.28k
!Base1.28k
)
4703
23
      return false;
4704
1.26k
4705
1.26k
    // Ensure there is no padding.
4706
1.26k
    if (getContext().getTypeSize(Base) * Members !=
4707
1.26k
        getContext().getTypeSize(Ty))
4708
0
      return false;
4709
2.69k
  } else {
4710
2.69k
    Members = 1;
4711
2.69k
    if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4712
124
      Members = 2;
4713
124
      Ty = CT->getElementType();
4714
124
    }
4715
2.69k
4716
2.69k
    // Most ABIs only support float, double, and some vector type widths.
4717
2.69k
    if (!isHomogeneousAggregateBaseType(Ty))
4718
696
      return false;
4719
2.00k
4720
2.00k
    // The base type must be the same for all members.  Types that
4721
2.00k
    // agree in both total size and mode (float vs. vector) are
4722
2.00k
    // treated as being equivalent here.
4723
2.00k
    const Type *TyPtr = Ty.getTypePtr();
4724
2.00k
    if (!Base) {
4725
1.40k
      Base = TyPtr;
4726
1.40k
      // If it's a non-power-of-2 vector, its size is already a power-of-2,
4727
1.40k
      // so make sure to widen it explicitly.
4728
1.40k
      if (const VectorType *VT = Base->getAs<VectorType>()) {
4729
947
        QualType EltTy = VT->getElementType();
4730
947
        unsigned NumElements =
4731
947
            getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4732
947
        Base = getContext()
4733
947
                   .getVectorType(EltTy, NumElements, VT->getVectorKind())
4734
947
                   .getTypePtr();
4735
947
      }
4736
1.40k
    }
4737
2.00k
4738
2.00k
    if (Base->isVectorType() != TyPtr->isVectorType() ||
4739
2.00k
        getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4740
7
      return false;
4741
4.15k
  }
4742
4.15k
  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4743
4.15k
}
4744
4745
301
bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4746
301
  // Homogeneous aggregates for ELFv2 must have base types of float,
4747
301
  // double, long double, or 128-bit vectors.
4748
301
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4749
217
    if (BT->getKind() == BuiltinType::Float ||
4750
217
        
BT->getKind() == BuiltinType::Double107
||
4751
217
        
BT->getKind() == BuiltinType::LongDouble77
||
4752
217
        
(77
getContext().getTargetInfo().hasFloat128Type()77
&&
4753
186
          
(BT->getKind() == BuiltinType::Float128)46
)) {
4754
186
      if (IsSoftFloatABI)
4755
34
        return false;
4756
152
      return true;
4757
152
    }
4758
217
  }
4759
115
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4760
80
    if (getContext().getTypeSize(VT) == 128 || 
IsQPXVectorTy(Ty)0
)
4761
80
      return true;
4762
35
  }
4763
35
  return false;
4764
35
}
4765
4766
bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4767
519
    const Type *Base, uint64_t Members) const {
4768
519
  // Vector and fp128 types require one register, other floating point types
4769
519
  // require one or two registers depending on their size.
4770
519
  uint32_t NumRegs =
4771
519
      ((getContext().getTargetInfo().hasFloat128Type() &&
4772
519
          
Base->isFloat128Type()108
) ||
4773
519
        
Base->isVectorType()411
) ?
1294
4774
519
                              : 
(getContext().getTypeSize(Base) + 63) / 64225
;
4775
519
4776
519
  // Homogeneous Aggregates may occupy at most 8 registers.
4777
519
  return Members * NumRegs <= 8;
4778
519
}
4779
4780
ABIArgInfo
4781
24.1k
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4782
24.1k
  Ty = useFirstFieldIfTransparentUnion(Ty);
4783
24.1k
4784
24.1k
  if (Ty->isAnyComplexType())
4785
17
    return ABIArgInfo::getDirect();
4786
24.1k
4787
24.1k
  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4788
24.1k
  // or via reference (larger than 16 bytes).
4789
24.1k
  if (Ty->isVectorType() && 
!IsQPXVectorTy(Ty)2.81k
) {
4790
2.81k
    uint64_t Size = getContext().getTypeSize(Ty);
4791
2.81k
    if (Size > 128)
4792
2
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4793
2.81k
    else if (Size < 128) {
4794
3
      llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4795
3
      return ABIArgInfo::getDirect(CoerceTy);
4796
3
    }
4797
24.1k
  }
4798
24.1k
4799
24.1k
  if (isAggregateTypeForABI(Ty)) {
4800
150
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4801
48
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4802
102
4803
102
    uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4804
102
    uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4805
102
4806
102
    // ELFv2 homogeneous aggregates are passed as array types.
4807
102
    const Type *Base = nullptr;
4808
102
    uint64_t Members = 0;
4809
102
    if (Kind == ELFv2 &&
4810
102
        
isHomogeneousAggregate(Ty, Base, Members)74
) {
4811
46
      llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4812
46
      llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4813
46
      return ABIArgInfo::getDirect(CoerceTy);
4814
46
    }
4815
56
4816
56
    // If an aggregate may end up fully in registers, we do not
4817
56
    // use the ByVal method, but pass the aggregate as array.
4818
56
    // This is usually beneficial since we avoid forcing the
4819
56
    // back-end to store the argument to memory.
4820
56
    uint64_t Bits = getContext().getTypeSize(Ty);
4821
56
    if (Bits > 0 && Bits <= 8 * GPRBits) {
4822
50
      llvm::Type *CoerceTy;
4823
50
4824
50
      // Types up to 8 bytes are passed as integer type (which will be
4825
50
      // properly aligned in the argument save area doubleword).
4826
50
      if (Bits <= GPRBits)
4827
14
        CoerceTy =
4828
14
            llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4829
36
      // Larger types are passed as arrays, with the base type selected
4830
36
      // according to the required alignment in the save area.
4831
36
      else {
4832
36
        uint64_t RegBits = ABIAlign * 8;
4833
36
        uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4834
36
        llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4835
36
        CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4836
36
      }
4837
50
4838
50
      return ABIArgInfo::getDirect(CoerceTy);
4839
50
    }
4840
6
4841
6
    // All other aggregates are passed ByVal.
4842
6
    return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4843
6
                                   /*ByVal=*/true,
4844
6
                                   /*Realign=*/TyAlign > ABIAlign);
4845
6
  }
4846
23.9k
4847
23.9k
  return (isPromotableTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)2.46k
4848
23.9k
                                     : 
ABIArgInfo::getDirect()21.4k
);
4849
23.9k
}
4850
4851
ABIArgInfo
4852
11.9k
PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4853
11.9k
  if (RetTy->isVoidType())
4854
7.83k
    return ABIArgInfo::getIgnore();
4855
4.15k
4856
4.15k
  if (RetTy->isAnyComplexType())
4857
29
    return ABIArgInfo::getDirect();
4858
4.12k
4859
4.12k
  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4860
4.12k
  // or via reference (larger than 16 bytes).
4861
4.12k
  if (RetTy->isVectorType() && 
!IsQPXVectorTy(RetTy)1.59k
) {
4862
1.59k
    uint64_t Size = getContext().getTypeSize(RetTy);
4863
1.59k
    if (Size > 128)
4864
2
      return getNaturalAlignIndirect(RetTy);
4865
1.59k
    else if (Size < 128) {
4866
3
      llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4867
3
      return ABIArgInfo::getDirect(CoerceTy);
4868
3
    }
4869
4.11k
  }
4870
4.11k
4871
4.11k
  if (isAggregateTypeForABI(RetTy)) {
4872
113
    // ELFv2 homogeneous aggregates are returned as array types.
4873
113
    const Type *Base = nullptr;
4874
113
    uint64_t Members = 0;
4875
113
    if (Kind == ELFv2 &&
4876
113
        
isHomogeneousAggregate(RetTy, Base, Members)90
) {
4877
48
      llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4878
48
      llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4879
48
      return ABIArgInfo::getDirect(CoerceTy);
4880
48
    }
4881
65
4882
65
    // ELFv2 small aggregates are returned in up to two registers.
4883
65
    uint64_t Bits = getContext().getTypeSize(RetTy);
4884
65
    if (Kind == ELFv2 && 
Bits <= 2 * GPRBits42
) {
4885
26
      if (Bits == 0)
4886
0
        return ABIArgInfo::getIgnore();
4887
26
4888
26
      llvm::Type *CoerceTy;
4889
26
      if (Bits > GPRBits) {
4890
6
        CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4891
6
        CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4892
6
      } else
4893
20
        CoerceTy =
4894
20
            llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4895
26
      return ABIArgInfo::getDirect(CoerceTy);
4896
26
    }
4897
39
4898
39
    // All other aggregates are returned indirectly.
4899
39
    return getNaturalAlignIndirect(RetTy);
4900
39
  }
4901
4.00k
4902
4.00k
  return (isPromotableTypeForABI(RetTy) ? 
ABIArgInfo::getExtend(RetTy)2.18k
4903
4.00k
                                        : 
ABIArgInfo::getDirect()1.81k
);
4904
4.00k
}
4905
4906
// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4907
Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4908
17
                                      QualType Ty) const {
4909
17
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4910
17
  TypeInfo.second = getParamTypeAlignment(Ty);
4911
17
4912
17
  CharUnits SlotSize = CharUnits::fromQuantity(8);
4913
17
4914
17
  // If we have a complex type and the base type is smaller than 8 bytes,
4915
17
  // the ABI calls for the real and imaginary parts to be right-adjusted
4916
17
  // in separate doublewords.  However, Clang expects us to produce a
4917
17
  // pointer to a structure with the two parts packed tightly.  So generate
4918
17
  // loads of the real and imaginary parts relative to the va_list pointer,
4919
17
  // and store them to a temporary structure.
4920
17
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4921
8
    CharUnits EltSize = TypeInfo.first / 2;
4922
8
    if (EltSize < SlotSize) {
4923
8
      Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4924
8
                                            SlotSize * 2, SlotSize,
4925
8
                                            SlotSize, /*AllowHigher*/ true);
4926
8
4927
8
      Address RealAddr = Addr;
4928
8
      Address ImagAddr = RealAddr;
4929
8
      if (CGF.CGM.getDataLayout().isBigEndian()) {
4930
4
        RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4931
4
                                                          SlotSize - EltSize);
4932
4
        ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4933
4
                                                      2 * SlotSize - EltSize);
4934
4
      } else {
4935
4
        ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4936
4
      }
4937
8
4938
8
      llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4939
8
      RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4940
8
      ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4941
8
      llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4942
8
      llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4943
8
4944
8
      Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4945
8
      CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4946
8
                             /*init*/ true);
4947
8
      return Temp;
4948
8
    }
4949
9
  }
4950
9
4951
9
  // Otherwise, just use the general rule.
4952
9
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4953
9
                          TypeInfo, SlotSize, /*AllowHigher*/ true);
4954
9
}
4955
4956
static bool
4957
PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4958
1
                              llvm::Value *Address) {
4959
1
  // This is calculated from the LLVM and GCC tables and verified
4960
1
  // against gcc output.  AFAIK all ABIs use the same encoding.
4961
1
4962
1
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4963
1
4964
1
  llvm::IntegerType *i8 = CGF.Int8Ty;
4965
1
  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4966
1
  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4967
1
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4968
1
4969
1
  // 0-31: r0-31, the 8-byte general-purpose registers
4970
1
  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4971
1
4972
1
  // 32-63: fp0-31, the 8-byte floating-point registers
4973
1
  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4974
1
4975
1
  // 64-67 are various 8-byte special-purpose registers:
4976
1
  // 64: mq
4977
1
  // 65: lr
4978
1
  // 66: ctr
4979
1
  // 67: ap
4980
1
  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4981
1
4982
1
  // 68-76 are various 4-byte special-purpose registers:
4983
1
  // 68-75 cr0-7
4984
1
  // 76: xer
4985
1
  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4986
1
4987
1
  // 77-108: v0-31, the 16-byte vector registers
4988
1
  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4989
1
4990
1
  // 109: vrsave
4991
1
  // 110: vscr
4992
1
  // 111: spe_acc
4993
1
  // 112: spefscr
4994
1
  // 113: sfp
4995
1
  // 114: tfhar
4996
1
  // 115: tfiar
4997
1
  // 116: texasr
4998
1
  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4999
1
5000
1
  return false;
5001
1
}
5002
5003
bool
5004
PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
5005
  CodeGen::CodeGenFunction &CGF,
5006
1
  llvm::Value *Address) const {
5007
1
5008
1
  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
5009
1
}
5010
5011
bool
5012
PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5013
0
                                                llvm::Value *Address) const {
5014
0
5015
0
  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
5016
0
}
5017
5018
//===----------------------------------------------------------------------===//
5019
// AArch64 ABI Implementation
5020
//===----------------------------------------------------------------------===//
5021
5022
namespace {
5023
5024
class AArch64ABIInfo : public SwiftABIInfo {
5025
public:
5026
  enum ABIKind {
5027
    AAPCS = 0,
5028
    DarwinPCS,
5029
    Win64
5030
  };
5031
5032
private:
5033
  ABIKind Kind;
5034
5035
public:
5036
  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
5037
294
    : SwiftABIInfo(CGT), Kind(Kind) {}
5038
5039
private:
5040
0
  ABIKind getABIKind() const { return Kind; }
5041
396
  bool isDarwinPCS() const { return Kind == DarwinPCS; }
5042
5043
  ABIArgInfo classifyReturnType(QualType RetTy, bool IsVariadic) const;
5044
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
5045
  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5046
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5047
                                         uint64_t Members) const override;
5048
5049
  bool isIllegalVectorType(QualType Ty) const;
5050
5051
3.45k
  void computeInfo(CGFunctionInfo &FI) const override {
5052
3.45k
    if (!::classifyReturnType(getCXXABI(), FI, *this))
5053
3.41k
      FI.getReturnInfo() =
5054
3.41k
          classifyReturnType(FI.getReturnType(), FI.isVariadic());
5055
3.45k
5056
3.45k
    for (auto &it : FI.arguments())
5057
5.28k
      it.info = classifyArgumentType(it.type);
5058
3.45k
  }
5059
5060
  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5061
                          CodeGenFunction &CGF) const;
5062
5063
  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
5064
                         CodeGenFunction &CGF) const;
5065
5066
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5067
107
                    QualType Ty) const override {
5068
107
    return Kind == Win64 ? 
EmitMSVAArg(CGF, VAListAddr, Ty)3
5069
107
                         : 
isDarwinPCS() 104
?
EmitDarwinVAArg(VAListAddr, Ty, CGF)34
5070
104
                                         : 
EmitAAPCSVAArg(VAListAddr, Ty, CGF)70
;
5071
107
  }
5072
5073
  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5074
                      QualType Ty) const override;
5075
5076
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5077
298
                                    bool asReturnValue) const override {
5078
298
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5079
298
  }
5080
0
  bool isSwiftErrorInRegister() const override {
5081
0
    return true;
5082
0
  }
5083
5084
  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5085
                                 unsigned elts) const override;
5086
};
5087
5088
class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
5089
public:
5090
  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
5091
294
      : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
5092
5093
16
  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5094
16
    return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
5095
16
  }
5096
5097
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5098
0
    return 31;
5099
0
  }
5100
5101
12
  bool doesReturnSlotInterfereWithArgs() const override { return false; }
5102
5103