Coverage Report

Created: 2022-01-18 06:27

/Users/buildslave/jenkins/workspace/coverage/llvm-project/lldb/include/lldb/Utility/ArchSpec.h
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//===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_UTILITY_ARCHSPEC_H
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#define LLDB_UTILITY_ARCHSPEC_H
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#include "lldb/Utility/CompletionRequest.h"
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#include "lldb/Utility/ConstString.h"
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#include "lldb/lldb-enumerations.h"
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#include "lldb/lldb-forward.h"
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#include "lldb/lldb-private-enumerations.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/YAMLTraits.h"
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#include <cstddef>
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#include <cstdint>
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#include <string>
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namespace lldb_private {
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/// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
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/// specification class.
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///
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/// A class designed to be created from a cpu type and subtype, a
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/// string representation, or an llvm::Triple.  Keeping all of the conversions
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/// of strings to architecture enumeration values confined to this class
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/// allows new architecture support to be added easily.
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class ArchSpec {
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public:
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  enum MIPSSubType {
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    eMIPSSubType_unknown,
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    eMIPSSubType_mips32,
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    eMIPSSubType_mips32r2,
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    eMIPSSubType_mips32r6,
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    eMIPSSubType_mips32el,
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    eMIPSSubType_mips32r2el,
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    eMIPSSubType_mips32r6el,
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    eMIPSSubType_mips64,
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    eMIPSSubType_mips64r2,
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    eMIPSSubType_mips64r6,
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    eMIPSSubType_mips64el,
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    eMIPSSubType_mips64r2el,
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    eMIPSSubType_mips64r6el,
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  };
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  // Masks for the ases word of an ABI flags structure.
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  enum MIPSASE {
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    eMIPSAse_dsp = 0x00000001,       // DSP ASE
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    eMIPSAse_dspr2 = 0x00000002,     // DSP R2 ASE
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    eMIPSAse_eva = 0x00000004,       // Enhanced VA Scheme
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    eMIPSAse_mcu = 0x00000008,       // MCU (MicroController) ASE
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    eMIPSAse_mdmx = 0x00000010,      // MDMX ASE
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    eMIPSAse_mips3d = 0x00000020,    // MIPS-3D ASE
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    eMIPSAse_mt = 0x00000040,        // MT ASE
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    eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
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    eMIPSAse_virt = 0x00000100,      // VZ ASE
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    eMIPSAse_msa = 0x00000200,       // MSA ASE
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    eMIPSAse_mips16 = 0x00000400,    // MIPS16 ASE
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    eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
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    eMIPSAse_xpa = 0x00001000,       // XPA ASE
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    eMIPSAse_mask = 0x00001fff,
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    eMIPSABI_O32 = 0x00002000,
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    eMIPSABI_N32 = 0x00004000,
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    eMIPSABI_N64 = 0x00008000,
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    eMIPSABI_O64 = 0x00020000,
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    eMIPSABI_EABI32 = 0x00040000,
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    eMIPSABI_EABI64 = 0x00080000,
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    eMIPSABI_mask = 0x000ff000
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  };
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  // MIPS Floating point ABI Values
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  enum MIPS_ABI_FP {
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    eMIPS_ABI_FP_ANY = 0x00000000,
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    eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
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    eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
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    eMIPS_ABI_FP_SOFT = 0x00300000,   // soft float
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    eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
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    eMIPS_ABI_FP_XX = 0x00500000,     // -mfpxx
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    eMIPS_ABI_FP_64 = 0x00600000,     // -mips32r2 -mfp64
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    eMIPS_ABI_FP_64A = 0x00700000,    // -mips32r2 -mfp64 -mno-odd-spreg
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    eMIPS_ABI_FP_mask = 0x00700000
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  };
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  // ARM specific e_flags
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  enum ARMeflags {
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    eARM_abi_soft_float = 0x00000200,
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    eARM_abi_hard_float = 0x00000400
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  };
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  enum RISCVSubType {
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    eRISCVSubType_unknown,
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    eRISCVSubType_riscv32,
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    eRISCVSubType_riscv64,
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  };
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  enum Core {
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    eCore_arm_generic,
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    eCore_arm_armv4,
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    eCore_arm_armv4t,
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    eCore_arm_armv5,
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    eCore_arm_armv5e,
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    eCore_arm_armv5t,
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    eCore_arm_armv6,
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    eCore_arm_armv6m,
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    eCore_arm_armv7,
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    eCore_arm_armv7l,
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    eCore_arm_armv7f,
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    eCore_arm_armv7s,
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    eCore_arm_armv7k,
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    eCore_arm_armv7m,
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    eCore_arm_armv7em,
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    eCore_arm_xscale,
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    eCore_thumb,
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    eCore_thumbv4t,
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    eCore_thumbv5,
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    eCore_thumbv5e,
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    eCore_thumbv6,
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    eCore_thumbv6m,
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    eCore_thumbv7,
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    eCore_thumbv7s,
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    eCore_thumbv7k,
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    eCore_thumbv7f,
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    eCore_thumbv7m,
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    eCore_thumbv7em,
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    eCore_arm_arm64,
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    eCore_arm_armv8,
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    eCore_arm_armv8l,
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    eCore_arm_arm64e,
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    eCore_arm_arm64_32,
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    eCore_arm_aarch64,
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    eCore_mips32,
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    eCore_mips32r2,
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    eCore_mips32r3,
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    eCore_mips32r5,
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    eCore_mips32r6,
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    eCore_mips32el,
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    eCore_mips32r2el,
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    eCore_mips32r3el,
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    eCore_mips32r5el,
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    eCore_mips32r6el,
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    eCore_mips64,
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    eCore_mips64r2,
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    eCore_mips64r3,
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    eCore_mips64r5,
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    eCore_mips64r6,
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    eCore_mips64el,
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    eCore_mips64r2el,
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    eCore_mips64r3el,
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    eCore_mips64r5el,
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    eCore_mips64r6el,
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    eCore_ppc_generic,
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    eCore_ppc_ppc601,
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    eCore_ppc_ppc602,
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    eCore_ppc_ppc603,
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    eCore_ppc_ppc603e,
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    eCore_ppc_ppc603ev,
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    eCore_ppc_ppc604,
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    eCore_ppc_ppc604e,
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    eCore_ppc_ppc620,
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    eCore_ppc_ppc750,
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    eCore_ppc_ppc7400,
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    eCore_ppc_ppc7450,
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    eCore_ppc_ppc970,
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    eCore_ppc64le_generic,
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    eCore_ppc64_generic,
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    eCore_ppc64_ppc970_64,
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    eCore_s390x_generic,
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    eCore_sparc_generic,
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    eCore_sparc9_generic,
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    eCore_x86_32_i386,
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    eCore_x86_32_i486,
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    eCore_x86_32_i486sx,
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    eCore_x86_32_i686,
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    eCore_x86_64_x86_64,
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    eCore_x86_64_x86_64h, // Haswell enabled x86_64
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    eCore_hexagon_generic,
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    eCore_hexagon_hexagonv4,
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    eCore_hexagon_hexagonv5,
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    eCore_riscv32,
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    eCore_riscv64,
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    eCore_uknownMach32,
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    eCore_uknownMach64,
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    eCore_arc, // little endian ARC
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    eCore_avr,
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    eCore_wasm32,
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    kNumCores,
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    kCore_invalid,
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    // The following constants are used for wildcard matching only
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    kCore_any,
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    kCore_arm_any,
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    kCore_ppc_any,
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    kCore_ppc64_any,
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    kCore_x86_32_any,
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    kCore_x86_64_any,
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    kCore_hexagon_any,
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    kCore_arm_first = eCore_arm_generic,
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    kCore_arm_last = eCore_arm_xscale,
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    kCore_thumb_first = eCore_thumb,
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    kCore_thumb_last = eCore_thumbv7em,
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    kCore_ppc_first = eCore_ppc_generic,
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    kCore_ppc_last = eCore_ppc_ppc970,
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    kCore_ppc64_first = eCore_ppc64_generic,
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    kCore_ppc64_last = eCore_ppc64_ppc970_64,
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    kCore_x86_32_first = eCore_x86_32_i386,
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    kCore_x86_32_last = eCore_x86_32_i686,
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    kCore_x86_64_first = eCore_x86_64_x86_64,
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    kCore_x86_64_last = eCore_x86_64_x86_64h,
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    kCore_hexagon_first = eCore_hexagon_generic,
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    kCore_hexagon_last = eCore_hexagon_hexagonv5,
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    kCore_mips32_first = eCore_mips32,
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    kCore_mips32_last = eCore_mips32r6,
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    kCore_mips32el_first = eCore_mips32el,
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    kCore_mips32el_last = eCore_mips32r6el,
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    kCore_mips64_first = eCore_mips64,
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    kCore_mips64_last = eCore_mips64r6,
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    kCore_mips64el_first = eCore_mips64el,
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    kCore_mips64el_last = eCore_mips64r6el,
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    kCore_mips_first = eCore_mips32,
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    kCore_mips_last = eCore_mips64r6el
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  };
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  /// Default constructor.
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  ///
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  /// Default constructor that initializes the object with invalid cpu type
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  /// and subtype values.
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  ArchSpec();
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  /// Constructor over triple.
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  ///
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  /// Constructs an ArchSpec with properties consistent with the given Triple.
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  explicit ArchSpec(const llvm::Triple &triple);
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  explicit ArchSpec(const char *triple_cstr);
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  explicit ArchSpec(llvm::StringRef triple_str);
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  /// Constructor over architecture name.
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  ///
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  /// Constructs an ArchSpec with properties consistent with the given object
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  /// type and architecture name.
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  explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
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                    uint32_t cpu_subtype);
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  /// Destructor.
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  ~ArchSpec();
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  /// Returns true if the OS, vendor and environment fields of the triple are
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  /// unset. The triple is expected to be normalized
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  /// (llvm::Triple::normalize).
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  static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
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  static void ListSupportedArchNames(StringList &list);
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  static void AutoComplete(CompletionRequest &request);
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  /// Returns a static string representing the current architecture.
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  ///
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  /// \return A static string corresponding to the current
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  ///         architecture.
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  const char *GetArchitectureName() const;
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  /// if MIPS architecture return true.
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  ///
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  ///  \return a boolean value.
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  bool IsMIPS() const;
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  /// Returns a string representing current architecture as a target CPU for
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  /// tools like compiler, disassembler etc.
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  ///
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  /// \return A string representing target CPU for the current
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  ///         architecture.
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  std::string GetClangTargetCPU() const;
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  /// Return a string representing target application ABI.
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  ///
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  /// \return A string representing target application ABI.
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  std::string GetTargetABI() const;
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  /// Clears the object state.
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  ///
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  /// Clears the object state back to a default invalid state.
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  void Clear();
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  /// Returns the size in bytes of an address of the current architecture.
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  ///
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  /// \return The byte size of an address of the current architecture.
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  uint32_t GetAddressByteSize() const;
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  /// Returns a machine family for the current architecture.
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  ///
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  /// \return An LLVM arch type.
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  llvm::Triple::ArchType GetMachine() const;
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  /// Returns the distribution id of the architecture.
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  ///
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  /// This will be something like "ubuntu", "fedora", etc. on Linux.
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  ///
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  /// \return A ConstString ref containing the distribution id,
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  ///         potentially empty.
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  ConstString GetDistributionId() const;
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  /// Set the distribution id of the architecture.
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  ///
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  /// This will be something like "ubuntu", "fedora", etc. on Linux. This
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  /// should be the same value returned by HostInfo::GetDistributionId ().
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  void SetDistributionId(const char *distribution_id);
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  /// Tests if this ArchSpec is valid.
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  ///
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  /// \return True if the current architecture is valid, false
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  ///         otherwise.
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3.67M
  bool IsValid() const {
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3.67M
    return 
m_core >= eCore_arm_generic3.67M
&& m_core < kNumCores;
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3.67M
  }
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48.3k
  explicit operator bool() const { return IsValid(); }
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177k
  bool TripleVendorWasSpecified() const {
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177k
    return !m_triple.getVendorName().empty();
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177k
  }
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177k
  bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
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324k
  bool TripleEnvironmentWasSpecified() const {
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324k
    return m_triple.hasEnvironment();
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324k
  }
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  /// Merges fields from another ArchSpec into this ArchSpec.
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  ///
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  /// This will use the supplied ArchSpec to fill in any fields of the triple
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  /// in this ArchSpec which were unspecified.  This can be used to refine a
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  /// generic ArchSpec with a more specific one. For example, if this
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  /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
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  /// have a triple which is x64-pc-windows-msvc, then merging that triple
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  /// into this one will result in the triple i386-pc-windows-msvc.
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  ///
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  void MergeFrom(const ArchSpec &other);
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  /// Change the architecture object type, CPU type and OS type.
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  ///
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  /// \param[in] arch_type The object type of this ArchSpec.
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  ///
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  /// \param[in] cpu The required CPU type.
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  ///
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  /// \param[in] os The optional OS type
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  /// The default value of 0 was chosen to from the ELF spec value
376
  /// ELFOSABI_NONE.  ELF is the only one using this parameter.  If another
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  /// format uses this parameter and 0 does not work, use a value over
378
  /// 255 because in the ELF header this is value is only a byte.
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  ///
380
  /// \return True if the object, and CPU were successfully set.
381
  ///
382
  /// As a side effect, the vendor value is usually set to unknown. The
383
  /// exceptions are
384
  ///   aarch64-apple-ios
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  ///   arm-apple-ios
386
  ///   thumb-apple-ios
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  ///   x86-apple-
388
  ///   x86_64-apple-
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  ///
390
  /// As a side effect, the os value is usually set to unknown The exceptions
391
  /// are
392
  ///   *-*-aix
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  ///   aarch64-apple-ios
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  ///   arm-apple-ios
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  ///   thumb-apple-ios
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  ///   powerpc-apple-darwin
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  ///   *-*-freebsd
398
  ///   *-*-linux
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  ///   *-*-netbsd
400
  ///   *-*-openbsd
401
  ///   *-*-solaris
402
  bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
403
                       uint32_t os = 0);
404
405
  /// Returns the byte order for the architecture specification.
406
  ///
407
  /// \return The endian enumeration for the current endianness of
408
  ///     the architecture specification
409
  lldb::ByteOrder GetByteOrder() const;
410
411
  /// Sets this ArchSpec's byte order.
412
  ///
413
  /// In the common case there is no need to call this method as the byte
414
  /// order can almost always be determined by the architecture. However, many
415
  /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
416
  /// byte order may be incorrect.
417
0
  void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
418
419
  uint32_t GetMinimumOpcodeByteSize() const;
420
421
  uint32_t GetMaximumOpcodeByteSize() const;
422
423
1.73M
  Core GetCore() const { return m_core; }
424
425
  uint32_t GetMachOCPUType() const;
426
427
  uint32_t GetMachOCPUSubType() const;
428
429
  /// Architecture data byte width accessor
430
  ///
431
  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
432
  /// from the Architecture's data bus
433
  uint32_t GetDataByteSize() const;
434
435
  /// Architecture code byte width accessor
436
  ///
437
  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
438
  /// from the Architecture's code bus
439
  uint32_t GetCodeByteSize() const;
440
441
  /// Architecture triple accessor.
442
  ///
443
  /// \return A triple describing this ArchSpec.
444
2.40M
  llvm::Triple &GetTriple() { return m_triple; }
445
446
  /// Architecture triple accessor.
447
  ///
448
  /// \return A triple describing this ArchSpec.
449
3.21M
  const llvm::Triple &GetTriple() const { return m_triple; }
450
451
  void DumpTriple(llvm::raw_ostream &s) const;
452
453
  /// Architecture triple setter.
454
  ///
455
  /// Configures this ArchSpec according to the given triple.  If the triple
456
  /// has unknown components in all of the vendor, OS, and the optional
457
  /// environment field (i.e. "i386-unknown-unknown") then default values are
458
  /// taken from the host.  Architecture and environment components are used
459
  /// to further resolve the CPU type and subtype, endian characteristics,
460
  /// etc.
461
  ///
462
  /// \return A triple describing this ArchSpec.
463
  bool SetTriple(const llvm::Triple &triple);
464
465
  bool SetTriple(llvm::StringRef triple_str);
466
467
  /// Returns the default endianness of the architecture.
468
  ///
469
  /// \return The endian enumeration for the default endianness of
470
  ///         the architecture.
471
  lldb::ByteOrder GetDefaultEndian() const;
472
473
  /// Returns true if 'char' is a signed type by default in the architecture
474
  /// false otherwise
475
  ///
476
  /// \return True if 'char' is a signed type by default on the
477
  ///         architecture and false otherwise.
478
  bool CharIsSignedByDefault() const;
479
480
  /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type
481
  /// match between them. e.g. armv7s is not an exact match with armv7 - this
482
  /// would return false
483
  ///
484
  /// \return true if the two ArchSpecs match.
485
  bool IsExactMatch(const ArchSpec &rhs) const;
486
487
  /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type
488
  /// match between them. e.g. armv7s is compatible with armv7 - this method
489
  /// would return true
490
  ///
491
  /// \return true if the two ArchSpecs are compatible
492
  bool IsCompatibleMatch(const ArchSpec &rhs) const;
493
494
  bool IsFullySpecifiedTriple() const;
495
496
  void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different,
497
                              bool &vendor_different, bool &os_different,
498
                              bool &os_version_different,
499
                              bool &env_different) const;
500
501
  /// Detect whether this architecture uses thumb code exclusively
502
  ///
503
  /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
504
  /// the Thumb instructions, never Arm.  We should normally pick up
505
  /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
506
  /// on each function - but when doing bare-boards low level debugging
507
  /// (especially common with these embedded processors), we may not have
508
  /// those things easily accessible.
509
  ///
510
  /// \return true if this is an arm ArchSpec which can only execute Thumb
511
  ///         instructions
512
  bool IsAlwaysThumbInstructions() const;
513
514
324k
  uint32_t GetFlags() const { return m_flags; }
515
516
162k
  void SetFlags(uint32_t flags) { m_flags = flags; }
517
518
  void SetFlags(const std::string &elf_abi);
519
520
protected:
521
  bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const;
522
  void UpdateCore();
523
524
  llvm::Triple m_triple;
525
  Core m_core = kCore_invalid;
526
  lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid;
527
528
  // Additional arch flags which we cannot get from triple and core For MIPS
529
  // these are application specific extensions like micromips, mips16 etc.
530
  uint32_t m_flags = 0;
531
532
  ConstString m_distribution_id;
533
534
  // Called when m_def or m_entry are changed.  Fills in all remaining members
535
  // with default values.
536
  void CoreUpdated(bool update_triple);
537
};
538
539
/// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
540
/// operator.
541
///
542
/// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
543
///
544
/// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
545
/// rhs The Left Hand Side ArchSpec object to compare.
546
///
547
/// \return true if \a lhs is less than \a rhs
548
bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
549
bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
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bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
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} // namespace lldb_private
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namespace llvm {
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namespace yaml {
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template <> struct ScalarTraits<lldb_private::ArchSpec> {
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  static void output(const lldb_private::ArchSpec &, void *, raw_ostream &);
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  static StringRef input(StringRef, void *, lldb_private::ArchSpec &);
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12
  static QuotingType mustQuote(StringRef S) { return QuotingType::Double; }
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};
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} // namespace yaml
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} // namespace llvm
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LLVM_YAML_IS_SEQUENCE_VECTOR(lldb_private::ArchSpec)
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#endif // LLDB_UTILITY_ARCHSPEC_H