Coverage Report

Created: 2022-01-22 13:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/lldb/source/Plugins/ABI/X86/ABIX86.cpp
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//===-- ABIX86.cpp --------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ABIMacOSX_i386.h"
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#include "ABISysV_i386.h"
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#include "ABISysV_x86_64.h"
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#include "ABIWindows_x86_64.h"
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#include "ABIX86.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Target/Process.h"
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using namespace lldb;
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using namespace lldb_private;
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LLDB_PLUGIN_DEFINE(ABIX86)
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void ABIX86::Initialize() {
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  ABIMacOSX_i386::Initialize();
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  ABISysV_i386::Initialize();
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  ABISysV_x86_64::Initialize();
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  ABIWindows_x86_64::Initialize();
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}
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void ABIX86::Terminate() {
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  ABIMacOSX_i386::Terminate();
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  ABISysV_i386::Terminate();
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  ABISysV_x86_64::Terminate();
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  ABIWindows_x86_64::Terminate();
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}
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namespace {
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enum RegKind {
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  GPR32,
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  GPR16,
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  GPR8h,
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  GPR8,
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  MM,
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  YMM_YMMh,
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  YMM_XMM,
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  RegKindCount
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};
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}
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struct RegData {
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  RegKind subreg_kind;
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  llvm::StringRef subreg_name;
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  llvm::Optional<uint32_t> base_index;
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};
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static void
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addPartialRegisters(std::vector<DynamicRegisterInfo::Register> &regs,
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                    llvm::ArrayRef<RegData *> subregs, uint32_t base_size,
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                    lldb::Encoding encoding, lldb::Format format,
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                    uint32_t subreg_size, uint32_t subreg_offset = 0) {
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  for (const RegData *subreg : subregs) {
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    assert(subreg);
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    uint32_t base_index = subreg->base_index.getValue();
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    DynamicRegisterInfo::Register &full_reg = regs[base_index];
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    if (full_reg.byte_size != base_size)
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      continue;
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    lldb_private::DynamicRegisterInfo::Register new_reg{
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        lldb_private::ConstString(subreg->subreg_name),
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        lldb_private::ConstString(),
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        lldb_private::ConstString("supplementary registers"),
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        subreg_size,
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        LLDB_INVALID_INDEX32,
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        encoding,
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        format,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        {base_index},
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        {},
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        subreg_offset};
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    addSupplementaryRegister(regs, new_reg);
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  }
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}
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static void
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addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> &regs,
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                     llvm::ArrayRef<RegData *> subregs1,
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                     llvm::ArrayRef<RegData *> subregs2, uint32_t base_size,
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                     lldb::Encoding encoding, lldb::Format format) {
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  for (auto it : llvm::zip(subregs1, subregs2)) {
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    RegData *regdata1, *regdata2;
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    std::tie(regdata1, regdata2) = it;
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    assert(regdata1);
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    assert(regdata2);
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    // verify that we've got matching target registers
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    if (regdata1->subreg_name != regdata2->subreg_name)
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      continue;
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    uint32_t base_index1 = regdata1->base_index.getValue();
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    uint32_t base_index2 = regdata2->base_index.getValue();
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    if (regs[base_index1].byte_size != base_size ||
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        regs[base_index2].byte_size != base_size)
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      continue;
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    lldb_private::DynamicRegisterInfo::Register new_reg{
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        lldb_private::ConstString(regdata1->subreg_name),
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        lldb_private::ConstString(),
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        lldb_private::ConstString("supplementary registers"),
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        base_size * 2,
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        LLDB_INVALID_INDEX32,
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        encoding,
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        format,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        LLDB_INVALID_REGNUM,
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        {base_index1, base_index2},
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        {}};
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    addSupplementaryRegister(regs, new_reg);
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  }
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}
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typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64>
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    BaseRegToRegsMap;
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#define GPRh(l)                                                                \
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  {                                                                            \
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    is64bit                                                                    \
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        ? BaseRegToRegsMap::value_type("r" l "x",                              \
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                                       {{GPR32, "e" l "x", llvm::None},        \
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                                        {GPR16, l "x", llvm::None},            \
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                                        {GPR8h, l "h", llvm::None},            \
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                                        {GPR8, l "l", llvm::None}})            \
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        : BaseRegToRegsMap::value_type("e" l "x", {{GPR16, l "x", llvm::None}, \
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                                                   {GPR8h, l "h", llvm::None}, \
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                                                   {GPR8, l "l", llvm::None}}) \
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  }
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#define GPR(r16)                                                               \
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  {                                                                            \
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    is64bit                                                                    \
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        ? BaseRegToRegsMap::value_type("r" r16, {{GPR32, "e" r16, llvm::None}, \
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                                                 {GPR16, r16, llvm::None},     \
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                                                 {GPR8, r16 "l", llvm::None}}) \
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        : BaseRegToRegsMap::value_type("e" r16, {{GPR16, r16, llvm::None},     \
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                                                 {GPR8, r16 "l", llvm::None}}) \
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  }
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#define GPR64(n)                                                               \
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  {                                                                            \
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    BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", llvm::None},     \
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                                          {GPR16, "r" #n "w", llvm::None},     \
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                                          {GPR8, "r" #n "l", llvm::None}})     \
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  }
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#define STMM(n)                                                                \
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  { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, llvm::None}}) }
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#define YMM(n)                                                                 \
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  {BaseRegToRegsMap::value_type("ymm" #n "h",                                  \
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                                {{YMM_YMMh, "ymm" #n, llvm::None}})},          \
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  {                                                                            \
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    BaseRegToRegsMap::value_type("xmm" #n, {{YMM_XMM, "ymm" #n, llvm::None}})  \
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  }
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BaseRegToRegsMap makeBaseRegMap(bool is64bit) {
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  BaseRegToRegsMap out{
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      {// GPRs common to amd64 & i386
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       GPRh("a"), GPRh("b"), GPRh("c"), GPRh("d"), GPR("si"), GPR("di"),
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       GPR("bp"), GPR("sp"),
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       // ST/MM registers
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       STMM(0), STMM(1), STMM(2), STMM(3), STMM(4), STMM(5), STMM(6), STMM(7),
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       // lower YMM registers (common to amd64 & i386)
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       YMM(0), YMM(1), YMM(2), YMM(3), YMM(4), YMM(5), YMM(6), YMM(7)}};
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  if (is64bit) {
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    BaseRegToRegsMap amd64_regs{{// GPRs specific to amd64
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                                 GPR64(8), GPR64(9), GPR64(10), GPR64(11),
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                                 GPR64(12), GPR64(13), GPR64(14), GPR64(15),
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                                 // higher YMM registers (specific to amd64)
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                                 YMM(8), YMM(9), YMM(10), YMM(11), YMM(12),
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                                 YMM(13), YMM(14), YMM(15)}};
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    out.insert(amd64_regs.begin(), amd64_regs.end());
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  }
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  return out;
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}
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void ABIX86::AugmentRegisterInfo(
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    std::vector<DynamicRegisterInfo::Register> &regs) {
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  MCBasedABI::AugmentRegisterInfo(regs);
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  ProcessSP process_sp = GetProcessSP();
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  if (!process_sp)
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    return;
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  uint32_t gpr_base_size =
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      process_sp->GetTarget().GetArchitecture().GetAddressByteSize();
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  // primary map from a base register to its subregisters
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  BaseRegToRegsMap base_reg_map = makeBaseRegMap(gpr_base_size == 8);
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  // set used for fast matching of register names to subregisters
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  llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set;
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  // convenience array providing access to all subregisters of given kind,
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  // sorted by base register index
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  std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind;
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  // prepare the set of all known subregisters
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  for (const auto &x : base_reg_map) {
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    for (const auto &subreg : x.second)
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      subreg_name_set.insert(subreg.subreg_name);
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  }
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  // iterate over all registers
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  for (const auto &x : llvm::enumerate(regs)) {
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    llvm::StringRef reg_name = x.value().name.GetStringRef();
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    // abort if at least one sub-register is already present
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    if (llvm::is_contained(subreg_name_set, reg_name))
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      return;
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    auto found = base_reg_map.find(reg_name);
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    if (found == base_reg_map.end())
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      continue;
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for (auto &subreg : found->second)41.9k
{
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      // fill in base register indices
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      subreg.base_index = x.index();
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      // fill subreg_by_kind map-array
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      subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back(
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          &subreg);
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    }
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  }
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  // now add registers by kind
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  addPartialRegisters(regs, subreg_by_kind[GPR32], gpr_base_size, eEncodingUint,
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                      eFormatHex, 4);
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  addPartialRegisters(regs, subreg_by_kind[GPR16], gpr_base_size, eEncodingUint,
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                      eFormatHex, 2);
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  addPartialRegisters(regs, subreg_by_kind[GPR8h], gpr_base_size, eEncodingUint,
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                      eFormatHex, 1, 1);
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  addPartialRegisters(regs, subreg_by_kind[GPR8], gpr_base_size, eEncodingUint,
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                      eFormatHex, 1);
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  addPartialRegisters(regs, subreg_by_kind[MM], 10, eEncodingUint, eFormatHex,
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                      8);
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  addCombinedRegisters(regs, subreg_by_kind[YMM_XMM], subreg_by_kind[YMM_YMMh],
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                       16, eEncodingVector, eFormatVectorOfUInt8);
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}