Coverage Report

Created: 2022-01-22 13:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/lldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- ArchitectureArm.cpp -----------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "Plugins/Architecture/Arm/ArchitectureArm.h"
10
#include "Plugins/Process/Utility/ARMDefines.h"
11
#include "Plugins/Process/Utility/InstructionUtils.h"
12
#include "lldb/Core/PluginManager.h"
13
#include "lldb/Target/RegisterContext.h"
14
#include "lldb/Target/Thread.h"
15
#include "lldb/Utility/ArchSpec.h"
16
17
using namespace lldb_private;
18
using namespace lldb;
19
20
LLDB_PLUGIN_DEFINE(ArchitectureArm)
21
22
3.44k
void ArchitectureArm::Initialize() {
23
3.44k
  PluginManager::RegisterPlugin(GetPluginNameStatic(),
24
3.44k
                                "Arm-specific algorithms",
25
3.44k
                                &ArchitectureArm::Create);
26
3.44k
}
27
28
3.43k
void ArchitectureArm::Terminate() {
29
3.43k
  PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
30
3.43k
}
31
32
12.3k
std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
33
12.3k
  if (arch.GetMachine() != llvm::Triple::arm)
34
12.2k
    return nullptr;
35
31
  return std::unique_ptr<Architecture>(new ArchitectureArm());
36
12.3k
}
37
38
6
void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
39
  // We need to check if we are stopped in Thumb mode in a IT instruction and
40
  // detect if the condition doesn't pass. If this is the case it means we
41
  // won't actually execute this instruction. If this happens we need to clear
42
  // the stop reason to no thread plans think we are stopped for a reason and
43
  // the plans should keep going.
44
  //
45
  // We do this because when single stepping many ARM processes, debuggers
46
  // often use the BVR/BCR registers that says "stop when the PC is not equal
47
  // to its current value". This method of stepping means we can end up
48
  // stopping on instructions inside an if/then block that wouldn't get
49
  // executed. By fixing this we can stop the debugger from seeming like you
50
  // stepped through both the "if" _and_ the "else" clause when source level
51
  // stepping because the debugger stops regardless due to the BVR/BCR
52
  // triggering a stop.
53
  //
54
  // It also means we can set breakpoints on instructions inside an an if/then
55
  // block and correctly skip them if we use the BKPT instruction. The ARM and
56
  // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
57
  // block.
58
  //
59
  // If your debugger inserts software traps in ARM/Thumb code, it will need to
60
  // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
61
  // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
62
  // bit thumb instruction for an opcode that is inside an if/then, it will
63
  // change the it/then to conditionally execute your
64
  // 16 bit trap and then cause your program to crash if it executes the
65
  // trailing 16 bits (the second half of the 32 bit thumb instruction you
66
  // partially overwrote).
67
68
6
  RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
69
6
  if (!reg_ctx_sp)
70
0
    return;
71
72
6
  const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
73
6
  if (cpsr == 0)
74
5
    return;
75
76
  // Read the J and T bits to get the ISETSTATE
77
1
  const uint32_t J = Bit32(cpsr, 24);
78
1
  const uint32_t T = Bit32(cpsr, 5);
79
1
  const uint32_t ISETSTATE = J << 1 | T;
80
1
  if (ISETSTATE == 0) {
81
// NOTE: I am pretty sure we want to enable the code below
82
// that detects when we stop on an instruction in ARM mode that is conditional
83
// and the condition doesn't pass. This can happen if you set a breakpoint on
84
// an instruction that is conditional. We currently will _always_ stop on the
85
// instruction which is bad. You can also run into this while single stepping
86
// and you could appear to run code in the "if" and in the "else" clause
87
// because it would stop at all of the conditional instructions in both. In
88
// such cases, we really don't want to stop at this location.
89
// I will check with the lldb-dev list first before I enable this.
90
#if 0
91
    // ARM mode: check for condition on instruction
92
    const addr_t pc = reg_ctx_sp->GetPC();
93
    Status error;
94
    // If we fail to read the opcode we will get UINT64_MAX as the result in
95
    // "opcode" which we can use to detect if we read a valid opcode.
96
    const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
97
    if (opcode <= UINT32_MAX)
98
    {
99
        const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
100
        if (!ARMConditionPassed(condition, cpsr))
101
        {
102
            // We ARE stopped on an ARM instruction whose condition doesn't
103
            // pass so this instruction won't get executed. Regardless of why
104
            // it stopped, we need to clear the stop info
105
            thread.SetStopInfo (StopInfoSP());
106
        }
107
    }
108
#endif
109
1
  } else 
if (0
ISETSTATE == 10
) {
110
    // Thumb mode
111
0
    const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
112
0
    if (ITSTATE != 0) {
113
0
      const uint32_t condition = Bits32(ITSTATE, 7, 4);
114
0
      if (!ARMConditionPassed(condition, cpsr)) {
115
        // We ARE stopped in a Thumb IT instruction on an instruction whose
116
        // condition doesn't pass so this instruction won't get executed.
117
        // Regardless of why it stopped, we need to clear the stop info
118
0
        thread.SetStopInfo(StopInfoSP());
119
0
      }
120
0
    }
121
0
  }
122
1
}
123
124
addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
125
0
                                               AddressClass addr_class) const {
126
0
  bool is_alternate_isa = false;
127
128
0
  switch (addr_class) {
129
0
  case AddressClass::eData:
130
0
  case AddressClass::eDebug:
131
0
    return LLDB_INVALID_ADDRESS;
132
0
  case AddressClass::eCodeAlternateISA:
133
0
    is_alternate_isa = true;
134
0
    break;
135
0
  default: break;
136
0
  }
137
138
0
  if ((code_addr & 2u) || is_alternate_isa)
139
0
    return code_addr | 1u;
140
0
  return code_addr;
141
0
}
142
143
addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
144
24
                                             AddressClass addr_class) const {
145
24
  switch (addr_class) {
146
0
  case AddressClass::eData:
147
0
  case AddressClass::eDebug:
148
0
    return LLDB_INVALID_ADDRESS;
149
24
  default: break;
150
24
  }
151
24
  return opcode_addr & ~(1ull);
152
24
}