Coverage Report

Created: 2022-01-22 13:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
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//===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H
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#define LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H
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#include "Plugins/Process/Utility/ARMDefines.h"
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#include "lldb/Core/EmulateInstruction.h"
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#include "lldb/Utility/ConstString.h"
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#include "lldb/Utility/Status.h"
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namespace lldb_private {
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// ITSession - Keep track of the IT Block progression.
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class ITSession {
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public:
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  ITSession() = default;
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  ~ITSession() = default;
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  // InitIT - Initializes ITCounter/ITState.
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  bool InitIT(uint32_t bits7_0);
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  // ITAdvance - Updates ITCounter/ITState as IT Block progresses.
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  void ITAdvance();
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  // InITBlock - Returns true if we're inside an IT Block.
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  bool InITBlock();
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  // LastInITBlock - Returns true if we're the last instruction inside an IT
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  // Block.
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  bool LastInITBlock();
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  // GetCond - Gets condition bits for the current thumb instruction.
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  uint32_t GetCond();
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private:
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  uint32_t ITCounter = 0; // Possible values: 0, 1, 2, 3, 4.
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  uint32_t ITState = 0;   // A2.5.2 Consists of IT[7:5] and IT[4:0] initially.
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};
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class EmulateInstructionARM : public EmulateInstruction {
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public:
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  enum ARMEncoding {
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    eEncodingA1,
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    eEncodingA2,
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    eEncodingA3,
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    eEncodingA4,
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    eEncodingA5,
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    eEncodingT1,
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    eEncodingT2,
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    eEncodingT3,
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    eEncodingT4,
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    eEncodingT5
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  };
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  static void Initialize();
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  static void Terminate();
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  static llvm::StringRef GetPluginNameStatic() { return "arm"; }
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  static llvm::StringRef GetPluginDescriptionStatic();
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  static lldb_private::EmulateInstruction *
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  CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type);
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  static bool
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  SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) {
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    switch (inst_type) {
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    case eInstructionTypeAny:
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    case eInstructionTypePrologueEpilogue:
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    case eInstructionTypePCModifying:
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      return true;
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    case eInstructionTypeAll:
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      return false;
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    }
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    return false;
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  }
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  llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
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  bool SetTargetTriple(const ArchSpec &arch) override;
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  enum Mode { eModeInvalid = -1, eModeARM, eModeThumb };
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  EmulateInstructionARM(const ArchSpec &arch)
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      : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid),
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        m_opcode_cpsr(0), m_it_session(), m_ignore_conditions(false) {
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    SetArchitecture(arch);
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  }
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  //    EmulateInstructionARM (const ArchSpec &arch,
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  //                           bool ignore_conditions,
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  //                           void *baton,
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  //                           ReadMemory read_mem_callback,
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  //                           WriteMemory write_mem_callback,
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  //                           ReadRegister read_reg_callback,
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  //                           WriteRegister write_reg_callback) :
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  //        EmulateInstruction (arch,
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  //                            ignore_conditions,
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  //                            baton,
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  //                            read_mem_callback,
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  //                            write_mem_callback,
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  //                            read_reg_callback,
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  //                            write_reg_callback),
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  //        m_arm_isa (0),
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  //        m_opcode_mode (eModeInvalid),
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  //        m_opcode_cpsr (0),
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  //        m_it_session ()
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  //    {
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  //    }
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  bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
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    return SupportsEmulatingInstructionsOfTypeStatic(inst_type);
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  }
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  virtual bool SetArchitecture(const ArchSpec &arch);
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  bool ReadInstruction() override;
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  bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr,
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                      Target *target) override;
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  bool EvaluateInstruction(uint32_t evaluate_options) override;
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  InstructionCondition GetInstructionCondition() override;
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  bool TestEmulation(Stream *out_stream, ArchSpec &arch,
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                     OptionValueDictionary *test_data) override;
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  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
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                       RegisterInfo &reg_info) override;
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  bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
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  uint32_t ArchVersion();
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  bool ConditionPassed(const uint32_t opcode);
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  uint32_t CurrentCond(const uint32_t opcode);
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  // InITBlock - Returns true if we're in Thumb mode and inside an IT Block.
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  bool InITBlock();
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  // LastInITBlock - Returns true if we're in Thumb mode and the last
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  // instruction inside an IT Block.
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  bool LastInITBlock();
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  bool BadMode(uint32_t mode);
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  bool CurrentModeIsPrivileged();
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  void CPSRWriteByInstr(uint32_t value, uint32_t bytemask,
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                        bool affect_execstate);
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  bool BranchWritePC(const Context &context, uint32_t addr);
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  bool BXWritePC(Context &context, uint32_t addr);
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  bool LoadWritePC(Context &context, uint32_t addr);
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  bool ALUWritePC(Context &context, uint32_t addr);
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  Mode CurrentInstrSet();
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  bool SelectInstrSet(Mode arm_or_thumb);
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  bool WriteBits32Unknown(int n);
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  bool WriteBits32UnknownToMemory(lldb::addr_t address);
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  bool UnalignedSupport();
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  typedef struct {
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    uint32_t result;
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    uint8_t carry_out;
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    uint8_t overflow;
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  } AddWithCarryResult;
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  AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in);
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  // Helper method to read the content of an ARM core register.
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  uint32_t ReadCoreReg(uint32_t regnum, bool *success);
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  // See A8.6.96 MOV (immediate) Operation.
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  // Default arguments are specified for carry and overflow parameters, which
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  // means
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  // not to update the respective flags even if setflags is true.
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  bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result,
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                                 const uint32_t Rd, bool setflags,
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                                 const uint32_t carry = ~0u,
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                                 const uint32_t overflow = ~0u);
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  bool WriteCoreReg(Context &context, const uint32_t result,
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                    const uint32_t Rd) {
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    // Don't set the flags.
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    return WriteCoreRegOptionalFlags(context, result, Rd, false);
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  }
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  // See A8.6.35 CMP (immediate) Operation.
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  // Default arguments are specified for carry and overflow parameters, which
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  // means
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  // not to update the respective flags.
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  bool WriteFlags(Context &context, const uint32_t result,
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                  const uint32_t carry = ~0u, const uint32_t overflow = ~0u);
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  inline uint64_t MemARead(EmulateInstruction::Context &context,
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                           lldb::addr_t address, uint32_t size,
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                           uint64_t fail_value, bool *success_ptr) {
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    // This is a stub function corresponding to "MemA[]" in the ARM manual
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    // pseudocode, for
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    // aligned reads from memory.  Since we are not trying to write a full
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    // hardware simulator, and since
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    // we are running in User mode (rather than Kernel mode) and therefore won't
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    // have access to many of the
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    // system registers we would need in order to fully implement this function,
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    // we will just call
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    // ReadMemoryUnsigned from here.  In the future, if we decide we do need to
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    // do more faithful emulation of
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    // the hardware, we can update this function appropriately.
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    return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr);
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  }
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  inline bool MemAWrite(EmulateInstruction::Context &context,
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                        lldb::addr_t address, uint64_t data_val, uint32_t size)
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  {
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    // This is a stub function corresponding to "MemA[]" in the ARM manual
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    // pseudocode, for
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    // aligned writes to memory.  Since we are not trying to write a full
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    // hardware simulator, and since
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    // we are running in User mode (rather than Kernel mode) and therefore won't
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    // have access to many of the
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    // system registers we would need in order to fully implement this function,
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    // we will just call
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    // WriteMemoryUnsigned from here.  In the future, if we decide we do need to
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    // do more faithful emulation of
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    // the hardware, we can update this function appropriately.
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    return WriteMemoryUnsigned(context, address, data_val, size);
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  }
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  inline uint64_t MemURead(EmulateInstruction::Context &context,
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                           lldb::addr_t address, uint32_t size,
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                           uint64_t fail_value, bool *success_ptr) {
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    // This is a stub function corresponding to "MemU[]" in the ARM manual
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    // pseudocode, for
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    // unaligned reads from memory.  Since we are not trying to write a full
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    // hardware simulator, and since
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    // we are running in User mode (rather than Kernel mode) and therefore won't
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    // have access to many of the
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    // system registers we would need in order to fully implement this function,
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    // we will just call
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    // ReadMemoryUnsigned from here.  In the future, if we decide we do need to
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    // do more faithful emulation of
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    // the hardware, we can update this function appropriately.
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    return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr);
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  }
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  inline bool MemUWrite(EmulateInstruction::Context &context,
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                        lldb::addr_t address, uint64_t data_val, uint32_t size)
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  {
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    // This is a stub function corresponding to "MemU[]" in the ARM manual
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    // pseudocode, for
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    // unaligned writes to memory.  Since we are not trying to write a full
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    // hardware simulator, and since
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    // we are running in User mode (rather than Kernel mode) and therefore won't
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    // have access to many of the
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    // system registers we would need in order to fully implement this function,
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    // we will just call
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    // WriteMemoryUnsigned from here.  In the future, if we decide we do need to
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    // do more faithful emulation of
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    // the hardware, we can update this function appropriately.
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    return WriteMemoryUnsigned(context, address, data_val, size);
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  }
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protected:
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  // Typedef for the callback function used during the emulation.
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  // Pass along (ARMEncoding)encoding as the callback data.
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  enum ARMInstrSize { eSize16, eSize32 };
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  typedef struct {
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    uint32_t mask;
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    uint32_t value;
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    uint32_t variants;
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    EmulateInstructionARM::ARMEncoding encoding;
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    uint32_t vfp_variants;
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    ARMInstrSize size;
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    bool (EmulateInstructionARM::*callback)(
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        const uint32_t opcode,
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        const EmulateInstructionARM::ARMEncoding encoding);
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    const char *name;
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  } ARMOpcode;
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  uint32_t GetFramePointerRegisterNumber() const;
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  uint32_t GetFramePointerDWARFRegisterNumber() const;
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  static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode,
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                                               uint32_t isa_mask);
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  static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode,
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                                                 uint32_t isa_mask);
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  // A8.6.123 PUSH
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  bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.122 POP
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  bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.8 ADD (SP plus immediate)
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  bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
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  bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7
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  bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.59 LDR (literal)
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  bool EmulateLDRRtPCRelative(const uint32_t opcode,
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                              const ARMEncoding encoding);
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  // A8.6.8 ADD (SP plus immediate)
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  bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.9 ADD (SP plus register)
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  bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.23 BL, BLX (immediate)
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  bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.24 BLX (register)
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  bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.25 BX
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  bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.26 BXJ
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  bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
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  bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.215 SUB (SP minus immediate) -- Rd == ip
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  bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.215 SUB (SP minus immediate)
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  bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.216 SUB (SP minus register)
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  bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.194 STR (immediate, ARM) -- Rn == sp
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  bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.355 VPUSH
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  bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.354 VPOP
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  bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.218 SVC (previously SWI)
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  bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.50 IT
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  bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding);
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  // NOP
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  bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.16 B
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  bool EmulateB(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.27 CBNZ, CBZ
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  bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.226 TBB, TBH
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  bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.4 ADD (immediate, Thumb)
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  bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.5 ADD (immediate, ARM)
395
  bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.6 ADD (register)
398
  bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.7 ADD (register-shifted register)
401
  bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding);
402
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  // A8.6.97 MOV (register)
404
  bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding);
405
406
  // A8.6.96 MOV (immediate)
407
  bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding);
408
409
  // A8.6.35 CMP (immediate)
410
  bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding);
411
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  // A8.6.36 CMP (register)
413
  bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding);
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  // A8.6.14 ASR (immediate)
416
  bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding);
417
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  // A8.6.15 ASR (register)
419
  bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding);
420
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  // A8.6.88 LSL (immediate)
422
  bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding);
423
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  // A8.6.89 LSL (register)
425
  bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding);
426
427
  // A8.6.90 LSR (immediate)
428
  bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding);
429
430
  // A8.6.91 LSR (register)
431
  bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding);
432
433
  // A8.6.139 ROR (immediate)
434
  bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding);
435
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  // A8.6.140 ROR (register)
437
  bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding);
438
439
  // A8.6.141 RRX
440
  bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding);
441
442
  // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX
443
  bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding,
444
                       ARM_ShifterType shift_type);
445
446
  // Helper method for ASR, LSL, LSR, and ROR (register)
447
  bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding,
448
                       ARM_ShifterType shift_type);
449
450
  // LOAD FUNCTIONS
451
452
  // A8.6.53 LDM/LDMIA/LDMFD
453
  bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding);
454
455
  // A8.6.54 LDMDA/LDMFA
456
  bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding);
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458
  // A8.6.55 LDMDB/LDMEA
459
  bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding);
460
461
  // A8.6.56 LDMIB/LDMED
462
  bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding);
463
464
  // A8.6.57 LDR (immediate, Thumb) -- Encoding T1
465
  bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding);
466
467
  // A8.6.58 LDR (immediate, ARM) - Encoding A1
468
  bool EmulateLDRImmediateARM(const uint32_t opcode,
469
                              const ARMEncoding encoding);
470
471
  // A8.6.59 LDR (literal)
472
  bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding);
473
474
  // A8.6.60 LDR (register) - Encoding T1, T2, A1
475
  bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding);
476
477
  // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3
478
  bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding);
479
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  // A8.6.62 LDRB (immediate, ARM)
481
  bool EmulateLDRBImmediateARM(const uint32_t opcode,
482
                               const ARMEncoding encoding);
483
484
  // A8.6.63 LDRB (literal) - Encoding T1, A1
485
  bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding);
486
487
  // A8.6.64 LDRB (register) - Encoding T1, T2, A1
488
  bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding);
489
490
  // A8.6.65 LDRBT
491
  bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding);
492
493
  // A8.6.66 LDRD (immediate)
494
  bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding);
495
496
  // A8.6.67
497
  bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding);
498
499
  // A8.6.68 LDRD (register)
500
  bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding);
501
502
  // A8.6.69 LDREX
503
  bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding);
504
505
  // A8.6.70 LDREXB
506
  bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding);
507
508
  // A8.6.71 LDREXD
509
  bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding);
510
511
  // A8.6.72 LDREXH
512
  bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding);
513
514
  // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3
515
  bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding);
516
517
  // A8.6.74 LDRS (immediate, ARM)
518
  bool EmulateLDRHImmediateARM(const uint32_t opcode,
519
                               const ARMEncoding encoding);
520
521
  // A8.6.75 LDRH (literal) - Encoding T1, A1
522
  bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding);
523
524
  // A8.6.76 LDRH (register) - Encoding T1, T2, A1
525
  bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding);
526
527
  // A8.6.77 LDRHT
528
  bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding);
529
530
  // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1
531
  bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding);
532
533
  // A8.6.79 LDRSB (literal) - Encoding T1, A1
534
  bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding);
535
536
  // A8.6.80 LDRSB (register) - Encoding T1, T2, A1
537
  bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding);
538
539
  // A8.6.81 LDRSBT
540
  bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding);
541
542
  // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1
543
  bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding);
544
545
  // A8.6.83 LDRSH (literal) - Encoding T1, A1
546
  bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding);
547
548
  // A8.6.84 LDRSH (register) - Encoding T1, T2, A1
549
  bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding);
550
551
  // A8.6.85 LDRSHT
552
  bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding);
553
554
  // A8.6.86
555
  bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding);
556
557
  // STORE FUNCTIONS
558
559
  // A8.6.189 STM/STMIA/STMEA
560
  bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding);
561
562
  // A8.6.190 STMDA/STMED
563
  bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding);
564
565
  // A8.6.191 STMDB/STMFD
566
  bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding);
567
568
  // A8.6.192 STMIB/STMFA
569
  bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding);
570
571
  // A8.6.193 STR (immediate, Thumb)
572
  bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding);
573
574
  // A8.6.194 STR (immediate, ARM)
575
  bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding);
576
577
  // A8.6.195 STR (register)
578
  bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding);
579
580
  // A8.6.196 STRB (immediate, Thumb)
581
  bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding);
582
583
  // A8.6.197 STRB (immediate, ARM)
584
  bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding);
585
586
  // A8.6.198 STRB (register)
587
  bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding);
588
589
  // A8.6.199 STRBT
590
  bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding);
591
592
  // A8.6.200 STRD (immediate)
593
  bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding);
594
595
  // A8.6.201 STRD (register)
596
  bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding);
597
598
  // A8.6.202 STREX
599
  bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding);
600
601
  // A8.6.203 STREXB
602
  bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding);
603
604
  // A8.6.204 STREXD
605
  bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding);
606
607
  // A8.6.205 STREXH
608
  bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding);
609
610
  // A8.6.206 STRH (immediate, Thumb)
611
  bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding);
612
613
  // A8.6.207 STRH (immediate, ARM)
614
  bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding);
615
616
  // A8.6.208 STRH (register)
617
  bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding);
618
619
  // A8.6.209 STRHT
620
  bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding);
621
622
  // A8.6.210 STRT
623
  bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding);
624
625
  // A8.6.1 ADC (immediate)
626
  bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding);
627
628
  // A8.6.2 ADC (Register)
629
  bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding);
630
631
  // A8.6.10 ADR
632
  bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding);
633
634
  // A8.6.11 AND (immediate)
635
  bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding);
636
637
  // A8.6.12 AND (register)
638
  bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding);
639
640
  // A8.6.19 BIC (immediate)
641
  bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding);
642
643
  // A8.6.20 BIC (register)
644
  bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding);
645
646
  // A8.6.26 BXJ
647
  bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding);
648
649
  // A8.6.32 CMN (immediate)
650
  bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding);
651
652
  // A8.6.33 CMN (register)
653
  bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding);
654
655
  // A8.6.44 EOR (immediate)
656
  bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding);
657
658
  // A8.6.45 EOR (register)
659
  bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding);
660
661
  // A8.6.105 MUL
662
  bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding);
663
664
  // A8.6.106 MVN (immediate)
665
  bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding);
666
667
  // A8.6.107 MVN (register)
668
  bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding);
669
670
  // A8.6.113 ORR (immediate)
671
  bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding);
672
673
  // A8.6.114 ORR (register)
674
  bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding);
675
676
  // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1
677
  bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding);
678
679
  // A8.6.119 PLI (immediate,literal) - Encoding T3, A1
680
  bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding);
681
682
  // A8.6.120 PLI (register) - Encoding T1, A1
683
  bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding);
684
685
  // A8.6.141 RSB (immediate)
686
  bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding);
687
688
  // A8.6.142 RSB (register)
689
  bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding);
690
691
  // A8.6.144 RSC (immediate)
692
  bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding);
693
694
  // A8.6.145 RSC (register)
695
  bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding);
696
697
  // A8.6.150 SBC (immediate)
698
  bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding);
699
700
  // A8.6.151 SBC (register)
701
  bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding);
702
703
  // A8.6.211 SUB (immediate, Thumb)
704
  bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding);
705
706
  // A8.6.212 SUB (immediate, ARM)
707
  bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding);
708
709
  // A8.6.213 SUB (register)
710
  bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding);
711
712
  // A8.6.214 SUB (register-shifted register)
713
  bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding);
714
715
  // A8.6.222 SXTB  - Encoding T1
716
  bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding);
717
718
  // A8.6.224 SXTH  - EncodingT1
719
  bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding);
720
721
  // A8.6.227 TEQ (immediate) - Encoding A1
722
  bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding);
723
724
  // A8.6.228 TEQ (register)  - Encoding A1
725
  bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding);
726
727
  // A8.6.230 TST (immediate) - Encoding A1
728
  bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding);
729
730
  // A8.6.231 TST (register)  - Encoding T1, A1
731
  bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding);
732
733
  // A8.6.262 UXTB  - Encoding T1
734
  bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding);
735
736
  // A8.6.264 UXTH  - Encoding T1
737
  bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding);
738
739
  // B6.1.8  RFE
740
  bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding);
741
742
  // A8.6.319 VLDM
743
  bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding);
744
745
  // A8.6.399 VSTM
746
  bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding);
747
748
  // A8.6.307 VLD1 (multiple single elements)
749
  bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding);
750
751
  // A8.6.308 VLD1 (single element to one lane)
752
  bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding);
753
754
  // A8.6.309 VLD1 (single element to all lanes)
755
  bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding);
756
757
  // A8.6.391 VST1 (multiple single elements)
758
  bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding);
759
760
  // A8.6.392 VST1 (single element from one lane)
761
  bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding);
762
763
  // A8.6.317 VLDR
764
  bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding);
765
766
  // A8.6.400 VSTR
767
  bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding);
768
769
  // B6.2.13 SUBS PC, LR and related instructions
770
  bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding);
771
772
  uint32_t m_arm_isa;
773
  Mode m_opcode_mode;
774
  uint32_t m_opcode_cpsr;
775
  uint32_t m_new_inst_cpsr; // This can get updated by the opcode.
776
  ITSession m_it_session;
777
  bool m_ignore_conditions;
778
};
779
780
} // namespace lldb_private
781
782
#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H