/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
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1 | | //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | /// \file This file declares the API for the instruction selector. |
11 | | /// This class is responsible for selecting machine instructions. |
12 | | /// It's implemented by the target. It's used by the InstructionSelect pass. |
13 | | // |
14 | | //===----------------------------------------------------------------------===// |
15 | | |
16 | | #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H |
17 | | #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H |
18 | | |
19 | | #include "llvm/ADT/SmallVector.h" |
20 | | #include <bitset> |
21 | | #include <cstddef> |
22 | | #include <cstdint> |
23 | | #include <functional> |
24 | | #include <initializer_list> |
25 | | #include <vector> |
26 | | |
27 | | namespace llvm { |
28 | | |
29 | | class LLT; |
30 | | class MachineInstr; |
31 | | class MachineInstrBuilder; |
32 | | class MachineOperand; |
33 | | class MachineRegisterInfo; |
34 | | class RegisterBankInfo; |
35 | | class TargetInstrInfo; |
36 | | class TargetRegisterClass; |
37 | | class TargetRegisterInfo; |
38 | | |
39 | | /// Container class for CodeGen predicate results. |
40 | | /// This is convenient because std::bitset does not have a constructor |
41 | | /// with an initializer list of set bits. |
42 | | /// |
43 | | /// Each InstructionSelector subclass should define a PredicateBitset class |
44 | | /// with: |
45 | | /// const unsigned MAX_SUBTARGET_PREDICATES = 192; |
46 | | /// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; |
47 | | /// and updating the constant to suit the target. Tablegen provides a suitable |
48 | | /// definition for the predicates in use in <Target>GenGlobalISel.inc when |
49 | | /// GET_GLOBALISEL_PREDICATE_BITSET is defined. |
50 | | template <std::size_t MaxPredicates> |
51 | | class PredicateBitsetImpl : public std::bitset<MaxPredicates> { |
52 | | public: |
53 | | // Cannot inherit constructors because it's not supported by VC++.. |
54 | 2.38M | PredicateBitsetImpl() = default; llvm::PredicateBitsetImpl<14ul>::PredicateBitsetImpl() Line | Count | Source | 54 | 2.17M | PredicateBitsetImpl() = default; |
llvm::PredicateBitsetImpl<61ul>::PredicateBitsetImpl() Line | Count | Source | 54 | 103k | PredicateBitsetImpl() = default; |
llvm::PredicateBitsetImpl<91ul>::PredicateBitsetImpl() Line | Count | Source | 54 | 111k | PredicateBitsetImpl() = default; |
|
55 | | |
56 | | PredicateBitsetImpl(const std::bitset<MaxPredicates> &B) |
57 | 2.05M | : std::bitset<MaxPredicates>(B) {} llvm::PredicateBitsetImpl<14ul>::PredicateBitsetImpl(std::__1::bitset<14ul> const&) Line | Count | Source | 57 | 2.05M | : std::bitset<MaxPredicates>(B) {} |
llvm::PredicateBitsetImpl<61ul>::PredicateBitsetImpl(std::__1::bitset<61ul> const&) Line | Count | Source | 57 | 646 | : std::bitset<MaxPredicates>(B) {} |
llvm::PredicateBitsetImpl<91ul>::PredicateBitsetImpl(std::__1::bitset<91ul> const&) Line | Count | Source | 57 | 1.34k | : std::bitset<MaxPredicates>(B) {} |
|
58 | | |
59 | 10.0M | PredicateBitsetImpl(std::initializer_list<unsigned> Init) { |
60 | 10.0M | for (auto I : Init) |
61 | 16.6M | std::bitset<MaxPredicates>::set(I); |
62 | 10.0M | } llvm::PredicateBitsetImpl<14ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>) Line | Count | Source | 59 | 906k | PredicateBitsetImpl(std::initializer_list<unsigned> Init) { | 60 | 906k | for (auto I : Init) | 61 | 1.08M | std::bitset<MaxPredicates>::set(I); | 62 | 906k | } |
llvm::PredicateBitsetImpl<61ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>) Line | Count | Source | 59 | 4.71M | PredicateBitsetImpl(std::initializer_list<unsigned> Init) { | 60 | 4.71M | for (auto I : Init) | 61 | 9.79M | std::bitset<MaxPredicates>::set(I); | 62 | 4.71M | } |
llvm::PredicateBitsetImpl<91ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>) Line | Count | Source | 59 | 4.45M | PredicateBitsetImpl(std::initializer_list<unsigned> Init) { | 60 | 4.45M | for (auto I : Init) | 61 | 5.72M | std::bitset<MaxPredicates>::set(I); | 62 | 4.45M | } |
|
63 | | }; |
64 | | |
65 | | enum { |
66 | | /// Begin a try-block to attempt a match and jump to OnFail if it is |
67 | | /// unsuccessful. |
68 | | /// - OnFail - The MatchTable entry at which to resume if the match fails. |
69 | | /// |
70 | | /// FIXME: This ought to take an argument indicating the number of try-blocks |
71 | | /// to exit on failure. It's usually one but the last match attempt of |
72 | | /// a block will need more. The (implemented) alternative is to tack a |
73 | | /// GIM_Reject on the end of each try-block which is simpler but |
74 | | /// requires an extra opcode and iteration in the interpreter on each |
75 | | /// failed match. |
76 | | GIM_Try, |
77 | | |
78 | | /// Record the specified instruction |
79 | | /// - NewInsnID - Instruction ID to define |
80 | | /// - InsnID - Instruction ID |
81 | | /// - OpIdx - Operand index |
82 | | GIM_RecordInsn, |
83 | | |
84 | | /// Check the feature bits |
85 | | /// - Expected features |
86 | | GIM_CheckFeatures, |
87 | | |
88 | | /// Check the opcode on the specified instruction |
89 | | /// - InsnID - Instruction ID |
90 | | /// - Expected opcode |
91 | | GIM_CheckOpcode, |
92 | | /// Check the instruction has the right number of operands |
93 | | /// - InsnID - Instruction ID |
94 | | /// - Expected number of operands |
95 | | GIM_CheckNumOperands, |
96 | | /// Check an immediate predicate on the specified instruction |
97 | | /// - InsnID - Instruction ID |
98 | | /// - The predicate to test |
99 | | GIM_CheckImmPredicate, |
100 | | |
101 | | /// Check the type for the specified operand |
102 | | /// - InsnID - Instruction ID |
103 | | /// - OpIdx - Operand index |
104 | | /// - Expected type |
105 | | GIM_CheckType, |
106 | | /// Check the register bank for the specified operand |
107 | | /// - InsnID - Instruction ID |
108 | | /// - OpIdx - Operand index |
109 | | /// - Expected register bank (specified as a register class) |
110 | | GIM_CheckRegBankForClass, |
111 | | /// Check the operand matches a complex predicate |
112 | | /// - InsnID - Instruction ID |
113 | | /// - OpIdx - Operand index |
114 | | /// - RendererID - The renderer to hold the result |
115 | | /// - Complex predicate ID |
116 | | GIM_CheckComplexPattern, |
117 | | /// Check the operand is a specific integer |
118 | | /// - InsnID - Instruction ID |
119 | | /// - OpIdx - Operand index |
120 | | /// - Expected integer |
121 | | GIM_CheckConstantInt, |
122 | | /// Check the operand is a specific literal integer (i.e. MO.isImm() or |
123 | | /// MO.isCImm() is true). |
124 | | /// - InsnID - Instruction ID |
125 | | /// - OpIdx - Operand index |
126 | | /// - Expected integer |
127 | | GIM_CheckLiteralInt, |
128 | | /// Check the operand is a specific intrinsic ID |
129 | | /// - InsnID - Instruction ID |
130 | | /// - OpIdx - Operand index |
131 | | /// - Expected Intrinsic ID |
132 | | GIM_CheckIntrinsicID, |
133 | | /// Check the specified operand is an MBB |
134 | | /// - InsnID - Instruction ID |
135 | | /// - OpIdx - Operand index |
136 | | GIM_CheckIsMBB, |
137 | | |
138 | | /// Check if the specified operand is safe to fold into the current |
139 | | /// instruction. |
140 | | /// - InsnID - Instruction ID |
141 | | GIM_CheckIsSafeToFold, |
142 | | |
143 | | /// Fail the current try-block, or completely fail to match if there is no |
144 | | /// current try-block. |
145 | | GIM_Reject, |
146 | | |
147 | | //=== Renderers === |
148 | | |
149 | | /// Mutate an instruction |
150 | | /// - NewInsnID - Instruction ID to define |
151 | | /// - OldInsnID - Instruction ID to mutate |
152 | | /// - NewOpcode - The new opcode to use |
153 | | GIR_MutateOpcode, |
154 | | /// Build a new instruction |
155 | | /// - InsnID - Instruction ID to define |
156 | | /// - Opcode - The new opcode to use |
157 | | GIR_BuildMI, |
158 | | |
159 | | /// Copy an operand to the specified instruction |
160 | | /// - NewInsnID - Instruction ID to modify |
161 | | /// - OldInsnID - Instruction ID to copy from |
162 | | /// - OpIdx - The operand to copy |
163 | | GIR_Copy, |
164 | | /// Copy an operand to the specified instruction |
165 | | /// - NewInsnID - Instruction ID to modify |
166 | | /// - OldInsnID - Instruction ID to copy from |
167 | | /// - OpIdx - The operand to copy |
168 | | /// - SubRegIdx - The subregister to copy |
169 | | GIR_CopySubReg, |
170 | | /// Add an implicit register def to the specified instruction |
171 | | /// - InsnID - Instruction ID to modify |
172 | | /// - RegNum - The register to add |
173 | | GIR_AddImplicitDef, |
174 | | /// Add an implicit register use to the specified instruction |
175 | | /// - InsnID - Instruction ID to modify |
176 | | /// - RegNum - The register to add |
177 | | GIR_AddImplicitUse, |
178 | | /// Add an register to the specified instruction |
179 | | /// - InsnID - Instruction ID to modify |
180 | | /// - RegNum - The register to add |
181 | | GIR_AddRegister, |
182 | | /// Add an immediate to the specified instruction |
183 | | /// - InsnID - Instruction ID to modify |
184 | | /// - Imm - The immediate to add |
185 | | GIR_AddImm, |
186 | | /// Render complex operands to the specified instruction |
187 | | /// - InsnID - Instruction ID to modify |
188 | | /// - RendererID - The renderer to call |
189 | | GIR_ComplexRenderer, |
190 | | |
191 | | /// Render a G_CONSTANT operator as a sign-extended immediate. |
192 | | /// - NewInsnID - Instruction ID to modify |
193 | | /// - OldInsnID - Instruction ID to copy from |
194 | | /// The operand index is implicitly 1. |
195 | | GIR_CopyConstantAsSImm, |
196 | | |
197 | | /// Constrain an instruction operand to a register class. |
198 | | /// - InsnID - Instruction ID to modify |
199 | | /// - OpIdx - Operand index |
200 | | /// - RCEnum - Register class enumeration value |
201 | | GIR_ConstrainOperandRC, |
202 | | /// Constrain an instructions operands according to the instruction |
203 | | /// description. |
204 | | /// - InsnID - Instruction ID to modify |
205 | | GIR_ConstrainSelectedInstOperands, |
206 | | /// Merge all memory operands into instruction. |
207 | | /// - InsnID - Instruction ID to modify |
208 | | /// - MergeInsnID... - One or more Instruction ID to merge into the result. |
209 | | /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to |
210 | | /// merge. |
211 | | GIR_MergeMemOperands, |
212 | | /// Erase from parent. |
213 | | /// - InsnID - Instruction ID to erase |
214 | | GIR_EraseFromParent, |
215 | | |
216 | | /// A successful emission |
217 | | GIR_Done, |
218 | | }; |
219 | | |
220 | | enum { |
221 | | /// Indicates the end of the variable-length MergeInsnID list in a |
222 | | /// GIR_MergeMemOperands opcode. |
223 | | GIU_MergeMemOperands_EndOfList = -1, |
224 | | }; |
225 | | |
226 | | /// Provides the logic to select generic machine instructions. |
227 | | class InstructionSelector { |
228 | | public: |
229 | | typedef bool(*ImmediatePredicateFn)(int64_t); |
230 | | |
231 | 15.1k | virtual ~InstructionSelector() = default; |
232 | | |
233 | | /// Select the (possibly generic) instruction \p I to only use target-specific |
234 | | /// opcodes. It is OK to insert multiple instructions, but they cannot be |
235 | | /// generic pre-isel instructions. |
236 | | /// |
237 | | /// \returns whether selection succeeded. |
238 | | /// \pre I.getParent() && I.getParent()->getParent() |
239 | | /// \post |
240 | | /// if returns true: |
241 | | /// for I in all mutated/inserted instructions: |
242 | | /// !isPreISelGenericOpcode(I.getOpcode()) |
243 | | /// |
244 | | virtual bool select(MachineInstr &I) const = 0; |
245 | | |
246 | | protected: |
247 | | using ComplexRendererFn = std::function<void(MachineInstrBuilder &)>; |
248 | | using RecordedMIVector = SmallVector<MachineInstr *, 4>; |
249 | | using NewMIVector = SmallVector<MachineInstrBuilder, 4>; |
250 | | |
251 | | struct MatcherState { |
252 | | std::vector<ComplexRendererFn> Renderers; |
253 | | RecordedMIVector MIs; |
254 | | |
255 | | MatcherState(unsigned MaxRenderers); |
256 | | }; |
257 | | |
258 | | public: |
259 | | template <class PredicateBitset, class ComplexMatcherMemFn> |
260 | | struct MatcherInfoTy { |
261 | | const LLT *TypeObjects; |
262 | | const PredicateBitset *FeatureBitsets; |
263 | | const ImmediatePredicateFn *ImmPredicateFns; |
264 | | const std::vector<ComplexMatcherMemFn> ComplexPredicates; |
265 | | }; |
266 | | |
267 | | protected: |
268 | | InstructionSelector(); |
269 | | |
270 | | /// Execute a given matcher table and return true if the match was successful |
271 | | /// and false otherwise. |
272 | | template <class TgtInstructionSelector, class PredicateBitset, |
273 | | class ComplexMatcherMemFn> |
274 | | bool executeMatchTable( |
275 | | TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, |
276 | | const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> &MatcherInfo, |
277 | | const int64_t *MatchTable, const TargetInstrInfo &TII, |
278 | | MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, |
279 | | const RegisterBankInfo &RBI, |
280 | | const PredicateBitset &AvailableFeatures) const; |
281 | | |
282 | | /// Constrain a register operand of an instruction \p I to a specified |
283 | | /// register class. This could involve inserting COPYs before (for uses) or |
284 | | /// after (for defs) and may replace the operand of \p I. |
285 | | /// \returns whether operand regclass constraining succeeded. |
286 | | bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx, |
287 | | const TargetRegisterClass &RC, |
288 | | const TargetInstrInfo &TII, |
289 | | const TargetRegisterInfo &TRI, |
290 | | const RegisterBankInfo &RBI) const; |
291 | | |
292 | | /// Mutate the newly-selected instruction \p I to constrain its (possibly |
293 | | /// generic) virtual register operands to the instruction's register class. |
294 | | /// This could involve inserting COPYs before (for uses) or after (for defs). |
295 | | /// This requires the number of operands to match the instruction description. |
296 | | /// \returns whether operand regclass constraining succeeded. |
297 | | /// |
298 | | // FIXME: Not all instructions have the same number of operands. We should |
299 | | // probably expose a constrain helper per operand and let the target selector |
300 | | // constrain individual registers, like fast-isel. |
301 | | bool constrainSelectedInstRegOperands(MachineInstr &I, |
302 | | const TargetInstrInfo &TII, |
303 | | const TargetRegisterInfo &TRI, |
304 | | const RegisterBankInfo &RBI) const; |
305 | | |
306 | | bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, |
307 | | const MachineRegisterInfo &MRI) const; |
308 | | |
309 | | bool isObviouslySafeToFold(MachineInstr &MI) const; |
310 | | }; |
311 | | |
312 | | } // end namespace llvm |
313 | | |
314 | | #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H |