/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/Target/TargetSubtargetInfo.h
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1 | | //===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file describes the subtarget options of a Target machine. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H |
15 | | #define LLVM_TARGET_TARGETSUBTARGETINFO_H |
16 | | |
17 | | #include "llvm/ADT/ArrayRef.h" |
18 | | #include "llvm/ADT/SmallVector.h" |
19 | | #include "llvm/ADT/StringRef.h" |
20 | | #include "llvm/CodeGen/PBQPRAConstraint.h" |
21 | | #include "llvm/CodeGen/ScheduleDAGMutation.h" |
22 | | #include "llvm/CodeGen/SchedulerRegistry.h" |
23 | | #include "llvm/MC/MCSubtargetInfo.h" |
24 | | #include "llvm/Support/CodeGen.h" |
25 | | #include <memory> |
26 | | #include <vector> |
27 | | |
28 | | |
29 | | namespace llvm { |
30 | | |
31 | | class CallLowering; |
32 | | class InstrItineraryData; |
33 | | struct InstrStage; |
34 | | class InstructionSelector; |
35 | | class LegalizerInfo; |
36 | | class MachineInstr; |
37 | | struct MachineSchedPolicy; |
38 | | struct MCReadAdvanceEntry; |
39 | | struct MCWriteLatencyEntry; |
40 | | struct MCWriteProcResEntry; |
41 | | class RegisterBankInfo; |
42 | | class SDep; |
43 | | class SelectionDAGTargetInfo; |
44 | | struct SubtargetFeatureKV; |
45 | | struct SubtargetInfoKV; |
46 | | class SUnit; |
47 | | class TargetFrameLowering; |
48 | | class TargetInstrInfo; |
49 | | class TargetLowering; |
50 | | class TargetRegisterClass; |
51 | | class TargetRegisterInfo; |
52 | | class TargetSchedModel; |
53 | | class Triple; |
54 | | |
55 | | //===----------------------------------------------------------------------===// |
56 | | /// |
57 | | /// TargetSubtargetInfo - Generic base class for all target subtargets. All |
58 | | /// Target-specific options that control code generation and printing should |
59 | | /// be exposed through a TargetSubtargetInfo-derived class. |
60 | | /// |
61 | | class TargetSubtargetInfo : public MCSubtargetInfo { |
62 | | protected: // Can only create subclasses... |
63 | | TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, |
64 | | ArrayRef<SubtargetFeatureKV> PF, |
65 | | ArrayRef<SubtargetFeatureKV> PD, |
66 | | const SubtargetInfoKV *ProcSched, |
67 | | const MCWriteProcResEntry *WPR, |
68 | | const MCWriteLatencyEntry *WL, |
69 | | const MCReadAdvanceEntry *RA, const InstrStage *IS, |
70 | | const unsigned *OC, const unsigned *FP); |
71 | | |
72 | | public: |
73 | | // AntiDepBreakMode - Type of anti-dependence breaking that should |
74 | | // be performed before post-RA scheduling. |
75 | | using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }; |
76 | | using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>; |
77 | | |
78 | | TargetSubtargetInfo() = delete; |
79 | | TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; |
80 | | TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete; |
81 | | ~TargetSubtargetInfo() override; |
82 | | |
83 | 0 | virtual bool isXRaySupported() const { return false; } |
84 | | |
85 | | // Interfaces to the major aspects of target machine information: |
86 | | // |
87 | | // -- Instruction opcode and operand information |
88 | | // -- Pipelines and scheduling information |
89 | | // -- Stack frame information |
90 | | // -- Selection DAG lowering information |
91 | | // -- Call lowering information |
92 | | // |
93 | | // N.B. These objects may change during compilation. It's not safe to cache |
94 | | // them between functions. |
95 | 0 | virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; } |
96 | 0 | virtual const TargetFrameLowering *getFrameLowering() const { |
97 | 0 | return nullptr; |
98 | 0 | } |
99 | 0 | virtual const TargetLowering *getTargetLowering() const { return nullptr; } |
100 | 0 | virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const { |
101 | 0 | return nullptr; |
102 | 0 | } |
103 | 0 | virtual const CallLowering *getCallLowering() const { return nullptr; } |
104 | | |
105 | | // FIXME: This lets targets specialize the selector by subtarget (which lets |
106 | | // us do things like a dedicated avx512 selector). However, we might want |
107 | | // to also specialize selectors by MachineFunction, which would let us be |
108 | | // aware of optsize/optnone and such. |
109 | 0 | virtual const InstructionSelector *getInstructionSelector() const { |
110 | 0 | return nullptr; |
111 | 0 | } |
112 | | |
113 | 0 | virtual unsigned getHwMode() const { return 0; } |
114 | | |
115 | | /// Target can subclass this hook to select a different DAG scheduler. |
116 | | virtual RegisterScheduler::FunctionPassCtor |
117 | 3.42M | getDAGScheduler(CodeGenOpt::Level) const { |
118 | 3.42M | return nullptr; |
119 | 3.42M | } |
120 | | |
121 | 0 | virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; } |
122 | | |
123 | | /// getRegisterInfo - If register information is available, return it. If |
124 | | /// not, return null. |
125 | 0 | virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } |
126 | | |
127 | | /// If the information for the register banks is available, return it. |
128 | | /// Otherwise return nullptr. |
129 | 100 | virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; } |
130 | | |
131 | | /// getInstrItineraryData - Returns instruction itinerary data for the target |
132 | | /// or specific subtarget. |
133 | 3.65M | virtual const InstrItineraryData *getInstrItineraryData() const { |
134 | 3.65M | return nullptr; |
135 | 3.65M | } |
136 | | |
137 | | /// Resolve a SchedClass at runtime, where SchedClass identifies an |
138 | | /// MCSchedClassDesc with the isVariant property. This may return the ID of |
139 | | /// another variant SchedClass, but repeated invocation must quickly terminate |
140 | | /// in a nonvariant SchedClass. |
141 | | virtual unsigned resolveSchedClass(unsigned SchedClass, |
142 | | const MachineInstr *MI, |
143 | 0 | const TargetSchedModel *SchedModel) const { |
144 | 0 | return 0; |
145 | 0 | } |
146 | | |
147 | | /// \brief True if the subtarget should run MachineScheduler after aggressive |
148 | | /// coalescing. |
149 | | /// |
150 | | /// This currently replaces the SelectionDAG scheduler with the "source" order |
151 | | /// scheduler (though see below for an option to turn this off and use the |
152 | | /// TargetLowering preference). It does not yet disable the postRA scheduler. |
153 | | virtual bool enableMachineScheduler() const; |
154 | | |
155 | | /// \brief Support printing of [latency:throughput] comment in output .S file. |
156 | 522k | virtual bool supportPrintSchedInfo() const { return false; } |
157 | | |
158 | | /// \brief True if the machine scheduler should disable the TLI preference |
159 | | /// for preRA scheduling with the source level scheduler. |
160 | 3.34M | virtual bool enableMachineSchedDefaultSched() const { return true; } |
161 | | |
162 | | /// \brief True if the subtarget should enable joining global copies. |
163 | | /// |
164 | | /// By default this is enabled if the machine scheduler is enabled, but |
165 | | /// can be overridden. |
166 | | virtual bool enableJoinGlobalCopies() const; |
167 | | |
168 | | /// True if the subtarget should run a scheduler after register allocation. |
169 | | /// |
170 | | /// By default this queries the PostRAScheduling bit in the scheduling model |
171 | | /// which is the preferred way to influence this. |
172 | | virtual bool enablePostRAScheduler() const; |
173 | | |
174 | | /// \brief True if the subtarget should run the atomic expansion pass. |
175 | | virtual bool enableAtomicExpand() const; |
176 | | |
177 | | /// \brief Override generic scheduling policy within a region. |
178 | | /// |
179 | | /// This is a convenient way for targets that don't provide any custom |
180 | | /// scheduling heuristics (no custom MachineSchedStrategy) to make |
181 | | /// changes to the generic scheduling policy. |
182 | | virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, |
183 | 300k | unsigned NumRegionInstrs) const {} |
184 | | |
185 | | // \brief Perform target specific adjustments to the latency of a schedule |
186 | | // dependency. |
187 | 14.8M | virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {} |
188 | | |
189 | | // For use with PostRAScheduling: get the anti-dependence breaking that should |
190 | | // be performed before post-RA scheduling. |
191 | 45.7k | virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; } |
192 | | |
193 | | // For use with PostRAScheduling: in CriticalPathRCs, return any register |
194 | | // classes that should only be considered for anti-dependence breaking if they |
195 | | // are on the critical path. |
196 | 105k | virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { |
197 | 105k | return CriticalPathRCs.clear(); |
198 | 105k | } |
199 | | |
200 | | // \brief Provide an ordered list of schedule DAG mutations for the post-RA |
201 | | // scheduler. |
202 | | virtual void getPostRAMutations( |
203 | 21.5k | std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { |
204 | 21.5k | } |
205 | | |
206 | | // \brief Provide an ordered list of schedule DAG mutations for the machine |
207 | | // pipeliner. |
208 | | virtual void getSMSMutations( |
209 | 0 | std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { |
210 | 0 | } |
211 | | |
212 | | // For use with PostRAScheduling: get the minimum optimization level needed |
213 | | // to enable post-RA scheduling. |
214 | 34.3k | virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const { |
215 | 34.3k | return CodeGenOpt::Default; |
216 | 34.3k | } |
217 | | |
218 | | /// \brief True if the subtarget should run the local reassignment |
219 | | /// heuristic of the register allocator. |
220 | | /// This heuristic may be compile time intensive, \p OptLevel provides |
221 | | /// a finer grain to tune the register allocator. |
222 | | virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; |
223 | | |
224 | | /// \brief Enable use of alias analysis during code generation (during MI |
225 | | /// scheduling, DAGCombine, etc.). |
226 | | virtual bool useAA() const; |
227 | | |
228 | | /// \brief Enable the use of the early if conversion pass. |
229 | 0 | virtual bool enableEarlyIfConversion() const { return false; } |
230 | | |
231 | | /// \brief Return PBQPConstraint(s) for the target. |
232 | | /// |
233 | | /// Override to provide custom PBQP constraints. |
234 | 2 | virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const { |
235 | 2 | return nullptr; |
236 | 2 | } |
237 | | |
238 | | /// Enable tracking of subregister liveness in register allocator. |
239 | | /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where |
240 | | /// possible. |
241 | 634k | virtual bool enableSubRegLiveness() const { return false; } |
242 | | |
243 | | /// Returns string representation of scheduler comment |
244 | | std::string getSchedInfoStr(const MachineInstr &MI) const override; |
245 | | std::string getSchedInfoStr(MCInst const &MCI) const override; |
246 | | }; |
247 | | |
248 | | } // end namespace llvm |
249 | | |
250 | | #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H |